diff --git a/Documentation/platforms/arm/ra4m1/boards/arduino-r4-minima/arduino-r4-minima.png b/Documentation/platforms/arm/ra4m1/boards/arduino-r4-minima/arduino-r4-minima.png
new file mode 100644
index 0000000000000..720e2cac37054
Binary files /dev/null and b/Documentation/platforms/arm/ra4m1/boards/arduino-r4-minima/arduino-r4-minima.png differ
diff --git a/Documentation/platforms/arm/ra4m1/boards/arduino-r4-minima/index.rst b/Documentation/platforms/arm/ra4m1/boards/arduino-r4-minima/index.rst
new file mode 100644
index 0000000000000..a200ab3b42b77
--- /dev/null
+++ b/Documentation/platforms/arm/ra4m1/boards/arduino-r4-minima/index.rst
@@ -0,0 +1,106 @@
+=================
+Arduino R4 Minima
+=================
+
+This board features the R7FA4M1ABxCFM MCU with 256 KiB of FLASH
+and 32 KiB of SRAM running at 64 MHz (internal clock - HOCO).
+
+.. figure:: arduino-r4-minima.png
+ :align: center
+
+See the `Arduino website `_ for
+information about Arduino R4 Minima.
+
+Buttons and LEDs
+================
+
+Buttons
+-------
+
+There are no buttons on the Arduino R4 Minima board.
+
+LEDs
+----
+
+There are three user-controllable LEDs on board the Arduino R4 Minima:
+
+ ============== =====
+ LED GPIO
+ ============== =====
+ L Amber LED P111
+ TX Yellow LED P012
+ RX Yellow LED P013
+ ============== =====
+
+LED L is connected to ground and can be illuminated by driving the P111
+output high. The TX and RX LEDs are pulled high and can be illuminated by
+driving the corresponding GPIO output low.
+
+These LEDs are not used by the board port unless ``CONFIG_ARCH_LEDS`` is
+defined. In that case, the usage by the board port is defined in
+``include/board.h`` and ``src/ra_autoleds.c``. The LEDs are used to encode OS-related
+events as follows:
+
+ ================== ========================= ====== ===== =====
+ SYMBOL MEANING L TX RX
+ ================== ========================= ====== ===== =====
+ LED_STARTED NuttX has been started OFF OFF OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF OFF OFF
+ LED_IRQSENABLED Interrupts enabled OFF OFF OFF
+ LED_STACKCREATED Idle stack created ON OFF OFF
+ LED_INIRQ In an interrupt N/C GLOW OFF
+ LED_SIGNAL In a signal handler N/C GLOW OFF
+ LED_ASSERTION An assertion failed N/C GLOW OFF
+ LED_PANIC The system has crashed N/C N/C Blinking
+ LED_IDLE MCU is in sleep mode NA NA NA
+ ================== ========================= ====== ===== =====
+
+
+Thus, if LED L is statically on, NuttX has successfully booted and is
+apparently running normally. If LED RX is glowing, then NuttX is
+handling interrupts (and also signals and assertions). If TX is flashing
+at approximately 2 Hz, then a fatal error has been detected, and the system
+has halted.
+
+Serial Consoles
+===============
+
+The R7FA4M1ABxCFM has a UART and 4 SCI (UARTs).
+
+Any of the SCI interfaces may be used as a serial console. By default,
+SCI2 is used as the serial console in all configurations. This can be
+easily changed by modifying the configuration.
+
+ ================== ============
+ Arduino R4 Minima R7FA4M1ABxCFM
+ Pin (Label) SCI Mapping
+ ================== ============
+ 0 (RX0<-0) RXD2
+ 1 (TX0->1) TXD2
+ 13 (12) RXD9
+ 14 (~11) TXD9
+ SWD-7 RXD1
+ SWD-8 TXD1
+ ================== ============
+
+Loading Code
+============
+
+It is possible to use J-Link on the SWD connector or use USB Boot
+available through the USB-C connector.
+
+RA USB Boot:
+------------
+
+Reboot the board with BOOT shorted to GND and press the reset button twice (double click). The board will enumerate as "Renesas RA USB Boot."
+
+Then, flash the ``nuttx.hex`` file using ``rfp-cli``:
+(https://www.renesas.com/en/software-tool/renesas-flash-programmer-programming-gui)
+
+Example command:
+
+.. code-block:: bash
+
+ rfp-cli -device ra -port /dev/ttyACM0 -p ./build/nuttx.hex
+
+*Note:* Programming using the binary format will fail because, by default, the RA4M1 NuttX port writes to the ``.idcode`` section, which is located beyond the end of the flash area. This causes the RFP to attempt writing to protected regions, leading to failures.
diff --git a/Documentation/platforms/arm/ra4m1/index.rst b/Documentation/platforms/arm/ra4m1/index.rst
new file mode 100644
index 0000000000000..6cddb7612ef29
--- /dev/null
+++ b/Documentation/platforms/arm/ra4m1/index.rst
@@ -0,0 +1,85 @@
+=============
+Renesas RA4M1
+=============
+
+Supported MCUs
+==============
+
+The following list includes MCUs from RA4M1 series and indicates whether
+they are supported in NuttX
+
+============= ======= ================
+MCU Support Note
+============= ======= ================
+R7FA4M1ABxCFP Yes
+R7FA4M1ABxCLJ No
+R7FA4M1ABxCFM Yes
+R7FA4M1ABxCNB No
+R7FA4M1ABxCFL Yes
+R7FA4M1ABxCNE No
+R7FA4M1ABxCNF No
+============= ======= ================
+
+Peripheral Support
+==================
+
+The following list indicates peripherals supported in NuttX:
+
+========== ======= =====================================
+Peripheral Support Notes
+========== ======= =====================================
+FLASH No
+CLOCK Yes Partially, just internal clock (HOCO)
+ICU Yes
+KINT No
+ELC No
+DTC No
+DMAC No
+GPT No
+AGT No
+RTC No
+WDT No
+IWDT No
+SCI Yes Just UART
+IIC No
+SPI No
+SSIE No
+QSPI No
+SDHI No
+CAN No
+USBFS No
+ADC14 No
+DAC12 No
+DAC8 No
+ACMPLP No
+OPAMP No
+TSN No
+SLCDC No
+CTSU No
+CRC No
+DOC No
+GPIO Yes
+========== ======= =====================================
+
+SCI
+----
+
+The Serial Communications Interface (SCI) is configurable to support several serial communication modes: Asynchronous (UART), Clock synchronous, Simple SPI
+Smart card interface, Simple IIC (master-only).
+Nuttx driver support UART mode (No-FIFO).
+
+GPIO
+-----
+
+
+
+Pins can be configured/operated using ``ra_gpio_*`` functions.
+
+Supported Boards
+================
+
+.. toctree::
+ :glob:
+ :maxdepth: 1
+
+ boards/*/*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 560a6e42229cb..9155c72e46f3b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -362,6 +362,11 @@ config ARCH_CHIP_MCX_NXXX
---help---
NXXx architectures (Cortex-M33)
+config ARCH_CHIP_RA4
+ bool "Renesas RA4"
+ ---help---
+ Renesas RA4 Architecture (ARM Cortex-M4F/M33).
+
config ARCH_CHIP_RP2040
bool "Raspberry Pi RP2040"
select ARCH_CORTEXM0
@@ -1163,6 +1168,7 @@ config ARCH_CHIP
default "nrf53" if ARCH_CHIP_NRF53
default "nrf91" if ARCH_CHIP_NRF91
default "nuc1xx" if ARCH_CHIP_NUC1XX
+ default "ra4" if ARCH_CHIP_RA4
default "rp2040" if ARCH_CHIP_RP2040
default "rp23xx" if ARCH_CHIP_RP23XX
default "s32k1xx" if ARCH_CHIP_S32K1XX
@@ -1625,6 +1631,9 @@ endif
if ARCH_CHIP_NUC1XX
source "arch/arm/src/nuc1xx/Kconfig"
endif
+if ARCH_CHIP_RA4
+source "arch/arm/src/ra4/Kconfig"
+endif
if ARCH_CHIP_RP2040
source "arch/arm/src/rp2040/Kconfig"
endif
diff --git a/arch/arm/include/ra4/chip.h b/arch/arm/include/ra4/chip.h
new file mode 100644
index 0000000000000..c6e3d542f00f8
--- /dev/null
+++ b/arch/arm/include/ra4/chip.h
@@ -0,0 +1,87 @@
+/****************************************************************************
+ * arch/arm/include/ra4/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_RA_CHIP_H
+#define __ARCH_ARM_INCLUDE_RA_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* Get customizations for each supported chip */
+
+/* RA Family */
+
+/* Common FEATURES
+ * Flash 256KB
+ * DataFlash 8KB
+ * SRAM 32+16KB
+ */
+
+/* Internal memory */
+
+# define RA_FLASH_SIZE (256*1024) /* 256KB */
+# define RA_SRAM0_SIZE (48*1024) /* 48KB */
+
+/* FEATURE R7FA4M1ABxxFP R7FA4M1ABxxLJ R7FA4M1ABxxFM R7FA4M1ABxxNB
+ * ----------- ------------- ------------- ------------- -------------
+ * Package LQFP100 LGA100 LQFP64 QFNP64
+ * No. PIOs 81 81 49 49
+ * SCI 4 4 4 4
+ *
+ * FEATURE R7FA4M1ABxxFL R7FA4M1ABxxNE R7FA4M1ABxxNF
+ * ----------- ------------- ------------- -------------
+ * Package LQFP48 QFNP48 QFN40
+ * No. PIOs 33 33 25
+ * SCI 4 4 4
+ */
+
+/* NVIC priority levels *****************************************************/
+
+/* Each priority field holds a priority value, 0-15. The lower the value, the
+ * greater the priority of the corresponding interrupt. The processor
+ * implements only bits[7:4] of each field, bits[3:0] read as zero and ignore
+ * writes.
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_INCLUDE_RA_CHIP_H */
diff --git a/arch/arm/include/ra4/irq.h b/arch/arm/include/ra4/irq.h
new file mode 100644
index 0000000000000..3eec8f2c083b3
--- /dev/null
+++ b/arch/arm/include/ra4/irq.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm/include/ra4/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_RA_IRQ_H
+#define __ARCH_ARM_INCLUDE_RA_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* IRQ numbers.
+ * The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC. This does, however, waste several words of memory in
+ * the IRQ to handle mapping tables.
+ */
+
+/* Common Processor Exceptions (vectors 0-15) */
+
+#define RA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
+ /* Vector 0: Reset stack pointer value */
+ /* Vector 1: Reset (not handler as an IRQ) */
+#define RA_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
+#define RA_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
+#define RA_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
+#define RA_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
+#define RA_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
+#define RA_IRQ_SVCALL (11) /* Vector 11: SVC call */
+#define RA_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
+ /* Vector 13: Reserved */
+#define RA_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
+#define RA_IRQ_SYSTICK (15) /* Vector 15: System tick */
+
+/* Chip-Specific External interrupts */
+
+#define RA_IRQ_FIRST (16) /* Vector number of the first external interrupt */
+
+#if defined(CONFIG_RA4M1_FAMILY)
+# include
+#else
+# error Unrecognized RA architecture
+#endif
+
+#define NR_IRQS (RA_IRQ_FIRST + RA_IRQ_NEXTINT)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_RA_IRQ_H */
diff --git a/arch/arm/include/ra4/ra4m1_irq.h b/arch/arm/include/ra4/ra4m1_irq.h
new file mode 100644
index 0000000000000..afc16a40bbb5f
--- /dev/null
+++ b/arch/arm/include/ra4/ra4m1_irq.h
@@ -0,0 +1,131 @@
+/****************************************************************************
+ * arch/arm/include/ra4/ra4m1_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_RA_RA4M1_IRQ_H
+#define __ARCH_ARM_INCLUDE_RA_RA4M1_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include
+#include
+#include
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* Total number of IRQ numbers */
+# define RA_IRQ_IELSR0 (RA_IRQ_FIRST + 0) /* 0: Event selected in the ICU.IELSR0 register */
+# define RA_IRQ_IELSR1 (RA_IRQ_FIRST + 1) /* 1: Event selected in the ICU.IELSR1 register */
+# define RA_IRQ_IELSR2 (RA_IRQ_FIRST + 2) /* 2: Event selected in the ICU.IELSR2 register */
+# define RA_IRQ_IELSR3 (RA_IRQ_FIRST + 3) /* 3: Event selected in the ICU.IELSR3 register */
+# define RA_IRQ_IELSR4 (RA_IRQ_FIRST + 4) /* 4: Event selected in the ICU.IELSR4 register */
+# define RA_IRQ_IELSR5 (RA_IRQ_FIRST + 5) /* 5: Event selected in the ICU.IELSR5 register */
+# define RA_IRQ_IELSR6 (RA_IRQ_FIRST + 6) /* 6: Event selected in the ICU.IELSR6 register */
+# define RA_IRQ_IELSR7 (RA_IRQ_FIRST + 7) /* 7: Event selected in the ICU.IELSR7 register */
+# define RA_IRQ_IELSR8 (RA_IRQ_FIRST + 8) /* 8: Event selected in the ICU.IELSR8 register */
+# define RA_IRQ_IELSR9 (RA_IRQ_FIRST + 9) /* 9: Event selected in the ICU.IELSR9 register */
+# define RA_IRQ_IELSR10 (RA_IRQ_FIRST + 10) /* 10: Event selected in the ICU.IELSR10 register */
+# define RA_IRQ_IELSR11 (RA_IRQ_FIRST + 11) /* 11: Event selected in the ICU.IELSR11 register */
+# define RA_IRQ_IELSR12 (RA_IRQ_FIRST + 12) /* 12: Event selected in the ICU.IELSR12 register */
+# define RA_IRQ_IELSR13 (RA_IRQ_FIRST + 13) /* 13: Event selected in the ICU.IELSR13 register */
+# define RA_IRQ_IELSR14 (RA_IRQ_FIRST + 14) /* 14: Event selected in the ICU.IELSR14 register */
+# define RA_IRQ_IELSR15 (RA_IRQ_FIRST + 15) /* 15: Event selected in the ICU.IELSR15 register */
+# define RA_IRQ_IELSR16 (RA_IRQ_FIRST + 16) /* 16: Event selected in the ICU.IELSR16 register */
+# define RA_IRQ_IELSR17 (RA_IRQ_FIRST + 17) /* 17: Event selected in the ICU.IELSR17 register */
+# define RA_IRQ_IELSR18 (RA_IRQ_FIRST + 18) /* 18: Event selected in the ICU.IELSR18 register */
+# define RA_IRQ_IELSR19 (RA_IRQ_FIRST + 19) /* 19: Event selected in the ICU.IELSR19 register */
+# define RA_IRQ_IELSR20 (RA_IRQ_FIRST + 20) /* 20: Event selected in the ICU.IELSR20 register */
+# define RA_IRQ_IELSR21 (RA_IRQ_FIRST + 21) /* 21: Event selected in the ICU.IELSR21 register */
+# define RA_IRQ_IELSR22 (RA_IRQ_FIRST + 22) /* 22: Event selected in the ICU.IELSR22 register */
+# define RA_IRQ_IELSR23 (RA_IRQ_FIRST + 23) /* 23: Event selected in the ICU.IELSR23 register */
+# define RA_IRQ_IELSR24 (RA_IRQ_FIRST + 24) /* 24: Event selected in the ICU.IELSR24 register */
+# define RA_IRQ_IELSR25 (RA_IRQ_FIRST + 25) /* 25: Event selected in the ICU.IELSR25 register */
+# define RA_IRQ_IELSR26 (RA_IRQ_FIRST + 26) /* 26: Event selected in the ICU.IELSR26 register */
+# define RA_IRQ_IELSR27 (RA_IRQ_FIRST + 27) /* 27: Event selected in the ICU.IELSR27 register */
+# define RA_IRQ_IELSR28 (RA_IRQ_FIRST + 28) /* 28: Event selected in the ICU.IELSR28 register */
+# define RA_IRQ_IELSR29 (RA_IRQ_FIRST + 29) /* 29: Event selected in the ICU.IELSR29 register */
+# define RA_IRQ_IELSR30 (RA_IRQ_FIRST + 30) /* 30: Event selected in the ICU.IELSR30 register */
+# define RA_IRQ_IELSR31 (RA_IRQ_FIRST + 31) /* 31: Event selected in the ICU.IELSR31 register */
+# define RA_IRQ_NEXTINT (32)
+
+#if (CONFIG_RA_SCI0_UART)
+#define SCI0_RXI (RA_IRQ_FIRST + __COUNTER__) /* Receive data full */
+#define SCI0_TXI (RA_IRQ_FIRST + __COUNTER__) /* Transmit data empty */
+#define SCI0_TEI (RA_IRQ_FIRST + __COUNTER__) /* Transmit end */
+#define SCI0_ERI (RA_IRQ_FIRST + __COUNTER__) /* Receive error */
+#endif
+
+#if (CONFIG_RA_SCI1_UART)
+#define SCI1_RXI (RA_IRQ_FIRST + __COUNTER__) /* Receive data full */
+#define SCI1_TXI (RA_IRQ_FIRST + __COUNTER__) /* Transmit data empty */
+#define SCI1_TEI (RA_IRQ_FIRST + __COUNTER__) /* Transmit end */
+#define SCI1_ERI (RA_IRQ_FIRST + __COUNTER__) /* Receive error */
+#endif
+
+#if (CONFIG_RA_SCI2_UART)
+#define SCI2_RXI (RA_IRQ_FIRST + __COUNTER__) /* Receive data full */
+#define SCI2_TXI (RA_IRQ_FIRST + __COUNTER__) /* Transmit data empty */
+#define SCI2_TEI (RA_IRQ_FIRST + __COUNTER__) /* Transmit end */
+#define SCI2_ERI (RA_IRQ_FIRST + __COUNTER__) /* Receive error */
+#endif
+
+#if (CONFIG_RA_SCI9_UART)
+#define SCI9_RXI (RA_IRQ_FIRST + __COUNTER__) /* Receive data full */
+#define SCI9_TXI (RA_IRQ_FIRST + __COUNTER__) /* Transmit data empty */
+#define SCI9_TEI (RA_IRQ_FIRST + __COUNTER__) /* Transmit end */
+#define SCI9_ERI (RA_IRQ_FIRST + __COUNTER__) /* Receive error */
+#endif
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_RA_RA_IRQ_H */
diff --git a/arch/arm/src/ra4/CMakeLists.txt b/arch/arm/src/ra4/CMakeLists.txt
new file mode 100644
index 0000000000000..d7323dff88638
--- /dev/null
+++ b/arch/arm/src/ra4/CMakeLists.txt
@@ -0,0 +1,32 @@
+# ##############################################################################
+# arch/arm/src/nrf53/CMakeLists.txt
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements. See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership. The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License. You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+set(SRCS
+ ra_start.c
+ ra_serial.c
+ ra_timerisr.c
+ ra_clockconfig.c
+ ra_irq.c
+ ra_lowputc.c
+ ra_icu.c
+ ra_gpio.c
+ ra_allocateheap.c)
+
+target_sources(arch PRIVATE ${SRCS})
diff --git a/arch/arm/src/ra4/Kconfig b/arch/arm/src/ra4/Kconfig
new file mode 100644
index 0000000000000..0c539252229d0
--- /dev/null
+++ b/arch/arm/src/ra4/Kconfig
@@ -0,0 +1,86 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+comment "RA Configuration Options"
+
+choice
+ prompt "RA Chip Selection"
+ default ARCH_CHIP_R7FA4M1ABxxFM
+ depends on ARCH_CHIP_RA4
+
+config ARCH_CHIP_R7FA4M1ABxxFP
+ bool "R7FA4M1ABxxFP"
+ select RA_HAVE_SCI0_UART
+ select RA_HAVE_SCI1_UART
+ select RA_HAVE_SCI2_UART
+ select RA_HAVE_SCI9_UART
+ select RA4M1_FAMILY
+
+config ARCH_CHIP_R7FA4M1ABxxFM
+ bool "R7FA4M1ABxxFM"
+ select RA_HAVE_SCI0_UART
+ select RA_HAVE_SCI1_UART
+ select RA_HAVE_SCI2_UART
+ select RA_HAVE_SCI9_UART
+ select RA4M1_FAMILY
+
+config ARCH_CHIP_R7FA4M1ABxxFL
+ bool "R7FA4M1ABxxFL"
+ select RA_HAVE_SCI0_UART
+ select RA_HAVE_SCI1_UART
+ select RA_HAVE_SCI2_UART
+ select RA_HAVE_SCI9_UART
+ select RA4M1_FAMILY
+
+endchoice # RA4 Chip Selection
+
+config RA4M1_FAMILY
+ bool
+ default n
+ select ARCH_CORTEXM4
+
+menu "RA4M1 Peripheral Support"
+
+config RA_HAVE_SCI0_UART
+ bool
+ default n
+
+config RA_HAVE_SCI1_UART
+ bool
+ default n
+
+config RA_HAVE_SCI2_UART
+ bool
+ default n
+
+config RA_HAVE_SCI9_UART
+ bool
+ default n
+
+config RA_SCI0_UART
+ bool "UART 0"
+ default n
+ depends on RA_HAVE_SCI0_UART
+ select SCI0_SERIALDRIVER
+
+config RA_SCI1_UART
+ bool "UART 1"
+ default n
+ depends on RA_HAVE_SCI1_UART
+ select SCI1_SERIALDRIVER
+
+config RA_SCI2_UART
+ bool "UART 2"
+ default y
+ depends on RA_HAVE_SCI2_UART
+ select SCI2_SERIALDRIVER
+
+config RA_SCI9_UART
+ bool "UART 9"
+ default n
+ depends on RA_HAVE_SCI9_UART
+ select SCI9_SERIALDRIVER
+
+endmenu # RA4M1 Peripheral Support
diff --git a/arch/arm/src/ra4/Make.defs b/arch/arm/src/ra4/Make.defs
new file mode 100644
index 0000000000000..346211b8ffd42
--- /dev/null
+++ b/arch/arm/src/ra4/Make.defs
@@ -0,0 +1,37 @@
+############################################################################
+# arch/arm/src/ra4/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# The start-up, "head", file
+
+# Common ARM and Cortex-M4 files
+
+include armv7-m/Make.defs
+
+# Required RA files
+
+CHIP_CSRCS += ra_start.c
+CHIP_CSRCS += ra_clockconfig.c
+CHIP_CSRCS += ra_irq.c
+CHIP_CSRCS += ra_icu.c
+CHIP_CSRCS += ra_gpio.c
+CHIP_CSRCS += ra_serial.c
+CHIP_CSRCS += ra_lowputc.c
+CHIP_CSRCS += ra_allocateheap.c
+CHIP_CSRCS += ra_timerisr.c
diff --git a/arch/arm/src/ra4/chip.h b/arch/arm/src/ra4/chip.h
new file mode 100644
index 0000000000000..4f9e0824c61e2
--- /dev/null
+++ b/arch/arm/src/ra4/chip.h
@@ -0,0 +1,53 @@
+/****************************************************************************
+ * arch/arm/src/ra4/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_CHIP_H
+#define __ARCH_ARM_SRC_RA_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+/* Include the memory map and the chip definitions file.
+ * Other chip hardware files should then include this file for the proper
+ * setup.
+ */
+
+#include
+#include "hardware/ra4m1_memorymap.h"
+
+/* Include the chip interrupt definition file */
+
+#include
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Provide the required number of peripheral interrupt vector definitions as
+ * well. The definition RA_IRQ_NEXTINT simply comes from the chip-specific
+ * IRQ header file included by arch/ra4/irq.h.
+ */
+
+#define ARMV7M_PERIPHERAL_INTERRUPTS 53
+
+#endif /* __ARCH_ARM_SRC_RA_CHIP_H */
diff --git a/arch/arm/src/ra4/hardware/ra4m1_icu.h b/arch/arm/src/ra4/hardware/ra4m1_icu.h
new file mode 100644
index 0000000000000..d6bc7dba3b6ab
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra4m1_icu.h
@@ -0,0 +1,238 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra4m1_icu.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_ICU_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_ICU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+#if defined(CONFIG_RA4M1_FAMILY)
+# include "hardware/ra4m1_icu.h"
+#else
+# error "Unsupported RA memory map"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+ #define EVENT_NONE (0x00) /* Link disabled */
+ #define EVENT_ICU_IRQ0 (0x01) /* External pin interrupt 0 */
+ #define EVENT_ICU_IRQ1 (0x02) /* External pin interrupt 1 */
+ #define EVENT_ICU_IRQ2 (0x03) /* External pin interrupt 2 */
+ #define EVENT_ICU_IRQ3 (0x04) /* External pin interrupt 3 */
+ #define EVENT_ICU_IRQ4 (0x05) /* External pin interrupt 4 */
+ #define EVENT_ICU_IRQ5 (0x06) /* External pin interrupt 5 */
+ #define EVENT_ICU_IRQ6 (0x07) /* External pin interrupt 6 */
+ #define EVENT_ICU_IRQ7 (0x08) /* External pin interrupt 7 */
+ #define EVENT_ICU_IRQ8 (0x09) /* External pin interrupt 8 */
+ #define EVENT_ICU_IRQ9 (0x0A) /* External pin interrupt 9 */
+ #define EVENT_ICU_IRQ10 (0x0B) /* External pin interrupt 10 */
+ #define EVENT_ICU_IRQ11 (0x0C) /* External pin interrupt 11 */
+ #define EVENT_ICU_IRQ12 (0x0D) /* External pin interrupt 12 */
+ #define EVENT_ICU_IRQ14 (0x0F) /* External pin interrupt 14 */
+ #define EVENT_ICU_IRQ15 (0x10) /* External pin interrupt 15 */
+ #define EVENT_DMAC0_INT (0x11) /* DMAC0 transfer end */
+ #define EVENT_DMAC1_INT (0x12) /* DMAC1 transfer end */
+ #define EVENT_DMAC2_INT (0x13) /* DMAC2 transfer end */
+ #define EVENT_DMAC3_INT (0x14) /* DMAC3 transfer end */
+ #define EVENT_DTC_COMPLETE (0x15) /* DTC transfer complete */
+ #define EVENT_DTC_END (0x16) /* DTC transfer end */
+ #define EVENT_ICU_SNOOZE_CANCEL (0x17) /* Canceling from Snooze mode */
+ #define EVENT_FCU_FRDYI (0x18) /* Flash ready interrupt */
+ #define EVENT_LVD_LVD1 (0x19) /* Voltage monitor 1 interrupt */
+ #define EVENT_LVD_LVD2 (0x1A) /* Voltage monitor 2 interrupt */
+ #define EVENT_LVD_VBATT (0x1B) /* VBATT low voltage detect */
+ #define EVENT_CGC_MOSC_STOP (0x1C) /* Main Clock oscillation stop */
+ #define EVENT_LPM_SNOOZE_REQUEST (0x1D) /* Snooze entry */
+ #define EVENT_AGT0_INT (0x1E) /* AGT interrupt */
+ #define EVENT_AGT0_COMPARE_A (0x1F) /* Compare match A */
+ #define EVENT_AGT0_COMPARE_B (0x20) /* Compare match B */
+ #define EVENT_AGT1_INT (0x21) /* AGT interrupt */
+ #define EVENT_AGT1_COMPARE_A (0x22) /* Compare match A */
+ #define EVENT_AGT1_COMPARE_B (0x23) /* Compare match B */
+ #define EVENT_IWDT_UNDERFLOW (0x24) /* IWDT underflow */
+ #define EVENT_WDT_UNDERFLOW (0x25) /* WDT underflow */
+ #define EVENT_RTC_ALARM (0x26) /* Alarm interrupt */
+ #define EVENT_RTC_PERIOD (0x27) /* Periodic interrupt */
+ #define EVENT_RTC_CARRY (0x28) /* Carry interrupt */
+ #define EVENT_ADC0_SCAN_END (0x29) /* End of A/D scanning operation */
+ #define EVENT_ADC0_SCAN_END_B (0x2A) /* A/D scan end interrupt for group B */
+ #define EVENT_ADC0_WINDOW_A (0x2B) /* Window A Compare match interrupt */
+ #define EVENT_ADC0_WINDOW_B (0x2C) /* Window B Compare match interrupt */
+ #define EVENT_ADC0_COMPARE_MATCH (0x2D) /* Compare match */
+ #define EVENT_ADC0_COMPARE_MISMATCH (0x2E) /* Compare mismatch */
+ #define EVENT_ACMPLP0_INT (0x2F) /* Low Power Comparator channel 0 interrupt */
+ #define EVENT_ACMPLP1_INT (0x30) /* Low Power Comparator channel 1 interrupt */
+ #define EVENT_USBFS_FIFO_0 (0x31) /* DMA transfer request 0 */
+ #define EVENT_USBFS_FIFO_1 (0x32) /* DMA transfer request 1 */
+ #define EVENT_USBFS_INT (0x33) /* USBFS interrupt */
+ #define EVENT_USBFS_RESUME (0x34) /* USBFS resume interrupt */
+ #define EVENT_IIC0_RXI (0x35) /* Receive data full */
+ #define EVENT_IIC0_TXI (0x36) /* Transmit data empty */
+ #define EVENT_IIC0_TEI (0x37) /* Transmit end */
+ #define EVENT_IIC0_ERI (0x38) /* Transfer error */
+ #define EVENT_IIC0_WUI (0x39) /* Wakeup interrupt */
+ #define EVENT_IIC1_RXI (0x3A) /* Receive data full */
+ #define EVENT_IIC1_TXI (0x3B) /* Transmit data empty */
+ #define EVENT_IIC1_TEI (0x3C) /* Transmit end */
+ #define EVENT_IIC1_ERI (0x3D) /* Transfer error */
+ #define EVENT_SSI0_TXI (0x3E) /* Transmit data empty */
+ #define EVENT_SSI0_RXI (0x3F) /* Receive data full */
+ #define EVENT_SSI0_INT (0x41) /* Error interrupt */
+ #define EVENT_CTSU_WRITE (0x42) /* Write request interrupt */
+ #define EVENT_CTSU_READ (0x43) /* Measurement data transfer request interrupt */
+ #define EVENT_CTSU_END (0x44) /* Measurement end interrupt */
+ #define EVENT_KEY_INT (0x45) /* Key interrupt */
+ #define EVENT_DOC_INT (0x46) /* Data operation circuit interrupt */
+ #define EVENT_CAC_FREQUENCY_ERROR (0x47) /* Frequency error interrupt */
+ #define EVENT_CAC_MEASUREMENT_END (0x48) /* Measurement end interrupt */
+ #define EVENT_CAC_OVERFLOW (0x49) /* Overflow interrupt */
+ #define EVENT_CAN0_ERROR (0x4A) /* Error interrupt */
+ #define EVENT_CAN0_FIFO_RX (0x4B) /* Receive FIFO interrupt */
+ #define EVENT_CAN0_FIFO_TX (0x4C) /* Transmit FIFO interrupt */
+ #define EVENT_CAN0_MAILBOX_RX (0x4D) /* Reception complete interrupt */
+ #define EVENT_CAN0_MAILBOX_TX (0x4E) /* Transmission complete interrupt */
+ #define EVENT_IOPORT_EVENT_1 (0x4F) /* Port 1 event */
+ #define EVENT_IOPORT_EVENT_2 (0x50) /* Port 2 event */
+ #define EVENT_IOPORT_EVENT_3 (0x51) /* Port 3 event */
+ #define EVENT_IOPORT_EVENT_4 (0x52) /* Port 4 event */
+ #define EVENT_SOFTWARE_EVENT_0 (0x53) /* Software event 0 */
+ #define EVENT_SOFTWARE_EVENT_1 (0x54) /* Software event 1 */
+ #define EVENT_POEG0_EVENT (0x55) /* Port Output disable 0 interrupt */
+ #define EVENT_POEG1_EVENT (0x56) /* Port Output disable 1 interrupt */
+ #define EVENT_GPT0_CAPTURE_COMPARE_A (0x57) /* Capture/Compare match A */
+ #define EVENT_GPT0_CAPTURE_COMPARE_B (0x58) /* Capture/Compare match B */
+ #define EVENT_GPT0_COMPARE_C (0x59) /* Compare match C */
+ #define EVENT_GPT0_COMPARE_D (0x5A) /* Compare match D */
+ #define EVENT_GPT0_COMPARE_E (0x5B) /* Compare match E */
+ #define EVENT_GPT0_COMPARE_F (0x5C) /* Compare match F */
+ #define EVENT_GPT0_COUNTER_OVERFLOW (0x5D) /* Overflow */
+ #define EVENT_GPT0_COUNTER_UNDERFLOW (0x5E) /* Underflow */
+ #define EVENT_GPT1_CAPTURE_COMPARE_A (0x5F) /* Capture/Compare match A */
+ #define EVENT_GPT1_CAPTURE_COMPARE_B (0x60) /* Capture/Compare match B */
+ #define EVENT_GPT1_COMPARE_C (0x61) /* Compare match C */
+ #define EVENT_GPT1_COMPARE_D (0x62) /* Compare match D */
+ #define EVENT_GPT1_COMPARE_E (0x63) /* Compare match E */
+ #define EVENT_GPT1_COMPARE_F (0x64) /* Compare match F */
+ #define EVENT_GPT1_COUNTER_OVERFLOW (0x65) /* Overflow */
+ #define EVENT_GPT1_COUNTER_UNDERFLOW (0x66) /* Underflow */
+ #define EVENT_GPT2_CAPTURE_COMPARE_A (0x67) /* Capture/Compare match A */
+ #define EVENT_GPT2_CAPTURE_COMPARE_B (0x68) /* Capture/Compare match B */
+ #define EVENT_GPT2_COMPARE_C (0x69) /* Compare match C */
+ #define EVENT_GPT2_COMPARE_D (0x6A) /* Compare match D */
+ #define EVENT_GPT2_COMPARE_E (0x6B) /* Compare match E */
+ #define EVENT_GPT2_COMPARE_F (0x6C) /* Compare match F */
+ #define EVENT_GPT2_COUNTER_OVERFLOW (0x6D) /* Overflow */
+ #define EVENT_GPT2_COUNTER_UNDERFLOW (0x6E) /* Underflow */
+ #define EVENT_GPT3_CAPTURE_COMPARE_A (0x6F) /* Capture/Compare match A */
+ #define EVENT_GPT3_CAPTURE_COMPARE_B (0x70) /* Capture/Compare match B */
+ #define EVENT_GPT3_COMPARE_C (0x71) /* Compare match C */
+ #define EVENT_GPT3_COMPARE_D (0x72) /* Compare match D */
+ #define EVENT_GPT3_COMPARE_E (0x73) /* Compare match E */
+ #define EVENT_GPT3_COMPARE_F (0x74) /* Compare match F */
+ #define EVENT_GPT3_COUNTER_OVERFLOW (0x75) /* Overflow */
+ #define EVENT_GPT3_COUNTER_UNDERFLOW (0x76) /* Underflow */
+ #define EVENT_GPT4_CAPTURE_COMPARE_A (0x77) /* Capture/Compare match A */
+ #define EVENT_GPT4_CAPTURE_COMPARE_B (0x78) /* Capture/Compare match B */
+ #define EVENT_GPT4_COMPARE_C (0x79) /* Compare match C */
+ #define EVENT_GPT4_COMPARE_D (0x7A) /* Compare match D */
+ #define EVENT_GPT4_COMPARE_E (0x7B) /* Compare match E */
+ #define EVENT_GPT4_COMPARE_F (0x7C) /* Compare match F */
+ #define EVENT_GPT4_COUNTER_OVERFLOW (0x7D) /* Overflow */
+ #define EVENT_GPT4_COUNTER_UNDERFLOW (0x7E) /* Underflow */
+ #define EVENT_GPT5_CAPTURE_COMPARE_A (0x7F) /* Capture/Compare match A */
+ #define EVENT_GPT5_CAPTURE_COMPARE_B (0x80) /* Capture/Compare match B */
+ #define EVENT_GPT5_COMPARE_C (0x81) /* Compare match C */
+ #define EVENT_GPT5_COMPARE_D (0x82) /* Compare match D */
+ #define EVENT_GPT5_COMPARE_E (0x83) /* Compare match E */
+ #define EVENT_GPT5_COMPARE_F (0x84) /* Compare match F */
+ #define EVENT_GPT5_COUNTER_OVERFLOW (0x85) /* Overflow */
+ #define EVENT_GPT5_COUNTER_UNDERFLOW (0x86) /* Underflow */
+ #define EVENT_GPT6_CAPTURE_COMPARE_A (0x87) /* Capture/Compare match A */
+ #define EVENT_GPT6_CAPTURE_COMPARE_B (0x88) /* Capture/Compare match B */
+ #define EVENT_GPT6_COMPARE_C (0x89) /* Compare match C */
+ #define EVENT_GPT6_COMPARE_D (0x8A) /* Compare match D */
+ #define EVENT_GPT6_COMPARE_E (0x8B) /* Compare match E */
+ #define EVENT_GPT6_COMPARE_F (0x8C) /* Compare match F */
+ #define EVENT_GPT6_COUNTER_OVERFLOW (0x8D) /* Overflow */
+ #define EVENT_GPT6_COUNTER_UNDERFLOW (0x8E) /* Underflow */
+ #define EVENT_GPT7_CAPTURE_COMPARE_A (0x8F) /* Capture/Compare match A */
+ #define EVENT_GPT7_CAPTURE_COMPARE_B (0x90) /* Capture/Compare match B */
+ #define EVENT_GPT7_COMPARE_C (0x91) /* Compare match C */
+ #define EVENT_GPT7_COMPARE_D (0x92) /* Compare match D */
+ #define EVENT_GPT7_COMPARE_E (0x93) /* Compare match E */
+ #define EVENT_GPT7_COMPARE_F (0x94) /* Compare match F */
+ #define EVENT_GPT7_COUNTER_OVERFLOW (0x95) /* Overflow */
+ #define EVENT_GPT7_COUNTER_UNDERFLOW (0x96) /* Underflow */
+ #define EVENT_OPS_UVW_EDGE (0x97) /* UVW edge event */
+ #define EVENT_SCI0_RXI (0x98) /* Receive data full */
+ #define EVENT_SCI0_TXI (0x99) /* Transmit data empty */
+ #define EVENT_SCI0_TEI (0x9A) /* Transmit end */
+ #define EVENT_SCI0_ERI (0x9B) /* Receive error */
+ #define EVENT_SCI0_AM (0x9C) /* Address match event */
+ #define EVENT_SCI0_RXI_OR_ERI (0x9D) /* Receive data full/Receive error */
+ #define EVENT_SCI1_RXI (0x9E) /* Receive data full */
+ #define EVENT_SCI1_TXI (0x9F) /* Transmit data empty */
+ #define EVENT_SCI1_TEI (0xA0) /* Transmit end */
+ #define EVENT_SCI1_ERI (0xA1) /* Receive error */
+ #define EVENT_SCI1_AM (0xA2) /* Address match event */
+ #define EVENT_SCI2_RXI (0xA3) /* Receive data full */
+ #define EVENT_SCI2_TXI (0xA4) /* Transmit data empty */
+ #define EVENT_SCI2_TEI (0xA5) /* Transmit end */
+ #define EVENT_SCI2_ERI (0xA6) /* Receive error */
+ #define EVENT_SCI2_AM (0xA7) /* Address match event */
+ #define EVENT_SCI9_RXI (0xA8) /* Receive data full */
+ #define EVENT_SCI9_TXI (0xA9) /* Transmit data empty */
+ #define EVENT_SCI9_TEI (0xAA) /* Transmit end */
+ #define EVENT_SCI9_ERI (0xAB) /* Receive error */
+ #define EVENT_SCI9_AM (0xAC) /* Address match event */
+ #define EVENT_SPI0_RXI (0xAD) /* Receive buffer full */
+ #define EVENT_SPI0_TXI (0xAE) /* Transmit buffer empty */
+ #define EVENT_SPI0_IDLE (0xAF) /* Idle */
+ #define EVENT_SPI0_ERI (0xB0) /* Error */
+ #define EVENT_SPI0_TEI (0xB1) /* Transmission complete event */
+ #define EVENT_SPI1_RXI (0xB2) /* Receive buffer full */
+ #define EVENT_SPI1_TXI (0xB3) /* Transmit buffer empty */
+ #define EVENT_SPI1_IDLE (0xB4) /* Idle */
+ #define EVENT_SPI1_ERI (0xB5) /* Error */
+ #define EVENT_SPI1_TEI (0xB6) /* Transmission complete event */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_ICU_H */
diff --git a/arch/arm/src/ra4/hardware/ra4m1_memorymap.h b/arch/arm/src/ra4/hardware/ra4m1_memorymap.h
new file mode 100644
index 0000000000000..3064bebe1ba09
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra4m1_memorymap.h
@@ -0,0 +1,172 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra4m1_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA4M1_MEMORYMAP_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA4M1_MEMORYMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Registers Base Addresses */
+
+ #define R_ACMPLP_BASE 0x40085E00UL
+ #define R_ADC0_BASE 0x4005C000UL
+ #define R_ADC1_BASE 0x4005C200UL
+ #define R_BUS_BASE 0x40003000UL
+ #define R_CAC_BASE 0x40044600UL
+ #define R_CAN0_BASE 0x40050000UL
+ #define R_CAN1_BASE 0x40051000UL
+ #define R_CRC_BASE 0x40074000UL
+ #define R_CTSU_BASE 0x40081000UL
+ #define R_DAC_BASE 0x4005E000UL
+ #define R_DAC8_BASE 0x4009E000UL
+ #define R_DEBUG_BASE 0x4001B000UL
+ #define R_DMA_BASE 0x40005200UL
+ #define R_DMAC0_BASE 0x40005000UL
+ #define R_DMAC1_BASE 0x40005040UL
+ #define R_DMAC2_BASE 0x40005080UL
+ #define R_DMAC3_BASE 0x400050C0UL
+ #define R_DMAC4_BASE 0x40005100UL
+ #define R_DMAC5_BASE 0x40005140UL
+ #define R_DMAC6_BASE 0x40005180UL
+ #define R_DMAC7_BASE 0x400051C0UL
+ #define R_DOC_BASE 0x40054100UL
+ #define R_DTC_BASE 0x40005400UL
+ #define R_ELC_BASE 0x40041000UL
+ #define R_FACI_LP_BASE 0x407EC000UL
+ #define R_FCACHE_BASE 0x4001C000UL
+ #define R_GPT0_BASE 0x40078000UL
+ #define R_GPT1_BASE 0x40078100UL
+ #define R_GPT2_BASE 0x40078200UL
+ #define R_GPT3_BASE 0x40078300UL
+ #define R_GPT4_BASE 0x40078400UL
+ #define R_GPT5_BASE 0x40078500UL
+ #define R_GPT6_BASE 0x40078600UL
+ #define R_GPT7_BASE 0x40078700UL
+ #define R_GPT8_BASE 0x40078800UL
+ #define R_GPT9_BASE 0x40078900UL
+ #define R_GPT10_BASE 0x40078A00UL
+ #define R_GPT11_BASE 0x40078B00UL
+ #define R_GPT12_BASE 0x40078C00UL
+ #define R_GPT13_BASE 0x40078D00UL
+ #define R_GPT_OPS_BASE 0x40078FF0UL
+ #define R_GPT_POEG0_BASE 0x40042000UL
+ #define R_GPT_POEG1_BASE 0x40042100UL
+ #define R_GPT_POEG2_BASE 0x40042200UL
+ #define R_GPT_POEG3_BASE 0x40042300UL
+ #define R_ICU_BASE 0x40006000UL
+ #define R_IIC0_BASE 0x40053000UL
+ #define R_IIC1_BASE 0x40053100UL
+ #define R_IIC2_BASE 0x40053200UL
+ #define R_IWDT_BASE 0x40044400UL
+ #define R_KINT_BASE 0x40080000UL
+ #define R_MPU_MMPU_BASE 0x40000000UL
+ #define R_MPU_SMPU_BASE 0x40000C00UL
+ #define R_MPU_SPMON_BASE 0x40000D00UL
+ #define R_MSTP_BASE 0x40047000UL
+ #define R_OPAMP_BASE 0x40086000UL
+ #define R_PORT0_BASE 0x40040000UL
+ #define R_PORT1_BASE 0x40040020UL
+ #define R_PORT2_BASE 0x40040040UL
+ #define R_PORT3_BASE 0x40040060UL
+ #define R_PORT4_BASE 0x40040080UL
+ #define R_PORT5_BASE 0x400400A0UL
+ #define R_PORT6_BASE 0x400400C0UL
+ #define R_PORT7_BASE 0x400400E0UL
+ #define R_PORT8_BASE 0x40040100UL
+ #define R_PORT9_BASE 0x40040120UL
+ #define R_PORT10_BASE 0x40040140UL
+ #define R_PORT11_BASE 0x40040160UL
+ #define R_PORT12_BASE 0x40040180UL
+ #define R_PORT13_BASE 0x400401A0UL
+ #define R_PORT14_BASE 0x400401C0UL
+ #define R_PFS_BASE 0x40040800UL
+ #define R_PMISC_BASE 0x40040D00UL
+ #define R_RTC_BASE 0x40044000UL
+ #define R_SCI0_BASE 0x40070000UL
+ #define R_SCI1_BASE 0x40070020UL
+ #define R_SCI2_BASE 0x40070040UL
+ #define R_SCI3_BASE 0x40070060UL
+ #define R_SCI4_BASE 0x40070080UL
+ #define R_SCI5_BASE 0x400700A0UL
+ #define R_SCI6_BASE 0x400700C0UL
+ #define R_SCI7_BASE 0x400700E0UL
+ #define R_SCI8_BASE 0x40070100UL
+ #define R_SCI9_BASE 0x40070120UL
+ #define R_SLCDC_BASE 0x40082000UL
+ #define R_SPI0_BASE 0x40072000UL
+ #define R_SPI1_BASE 0x40072100UL
+ #define R_SRAM_BASE 0x40002000UL
+ #define R_SSI0_BASE 0x4004E000UL
+ #define R_SSI1_BASE 0x4004E100UL
+ #define R_SYSTEM_BASE 0x4001E000UL
+ #define R_TSN_BASE 0x407EC000UL
+ #define R_USB_FS0_BASE 0x40090000UL
+ #define R_WDT_BASE 0x40044200UL
+ #define R_AGTX0_BASE 0x40084000UL
+ #define R_AGTX1_BASE 0x40084100UL
+ #define R_AGTX2_BASE 0x40084200UL
+ #define R_AGTX3_BASE 0x40084300UL
+ #define R_AGTX4_BASE 0x40084400UL
+ #define R_AGTX5_BASE 0x40084500UL
+ #define R_AGTX6_BASE 0x40084600UL
+ #define R_AGTX7_BASE 0x40084700UL
+ #define R_AGTX8_BASE 0x40084800UL
+ #define R_AGTX9_BASE 0x40084900UL
+ #define R_OFS_BASE 0x00000400UL
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_SRC_RA_HARDWARE_RA4M1_MEMORYMAP_H */
diff --git a/arch/arm/src/ra4/hardware/ra4m1_mstp.h b/arch/arm/src/ra4/hardware/ra4m1_mstp.h
new file mode 100644
index 0000000000000..e81ef7fee0aec
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra4m1_mstp.h
@@ -0,0 +1,94 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra4m1_mstp.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4_MSTP_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4_MSTP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_MSTP_MSTPCRB_OFFSET 0x0000
+#define R_MSTP_MSTPCRC_OFFSET 0x0004
+#define R_MSTP_MSTPCRD_OFFSET 0x0008
+
+/* Register Addresses *******************************************************/
+
+#define R_MSTP_MSTPCRB (R_MSTP_BASE + R_MSTP_MSTPCRB_OFFSET)
+#define R_MSTP_MSTPCRC (R_MSTP_BASE + R_MSTP_MSTPCRC_OFFSET)
+#define R_MSTP_MSTPCRD (R_MSTP_BASE + R_MSTP_MSTPCRD_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+#define R_MSTP_MSTPCRB_SCI0 (1 << 31) /* 80000000: Serial Communication Interface 0 Module Stop */
+#define R_MSTP_MSTPCRB_SCI1 (1 << 30) /* 40000000: Serial Communication Interface 1 Module Stop */
+#define R_MSTP_MSTPCRB_SCI2 (1 << 29) /* 20000000: Serial Communication Interface 2 Module Stop */
+#define R_MSTP_MSTPCRB_SCI9 (1 << 22) /* 400000: Serial Communication Interface 9 Module Stop */
+#define R_MSTP_MSTPCRB_SPI0 (1 << 19) /* 80000: Serial Peripheral Interface 0 Module Stop */
+#define R_MSTP_MSTPCRB_SPI1 (1 << 18) /* 40000: Serial Peripheral Interface 1 Module Stop */
+#define R_MSTP_MSTPCRB_USBFS (1 << 11) /* 800: Universal Serial Bus 2.0 FS Interface Module Stop */
+#define R_MSTP_MSTPCRB_IIC0 (1 << 9) /* 200: I2C Bus Interface 0 Module Stop */
+#define R_MSTP_MSTPCRB_IIC1 (1 << 8) /* 100: I2C Bus Interface 1 Module Stop */
+#define R_MSTP_MSTPCRB_CAN (1 << 2) /* 04: Controller Area Network Module Stop */
+
+#define R_MSTP_MSTPCRC_SCE5 (1 << 31) /* 80000000: SCE5 Module Stop */
+#define R_MSTP_MSTPCRC_ELC (1 << 14) /* 4000: Event Link Controller Module Stop */
+#define R_MSTP_MSTPCRC_DOC (1 << 13) /* 2000: Data Operation Circuit Module Stop */
+#define R_MSTP_MSTPCRC_SSIE0 (1 << 8) /* 100: Synchronous Serial Interface 0 Module Stop */
+#define R_MSTP_MSTPCRC_SLCDC (1 << 4) /* 10: Segment LCD Controller Module Stop */
+#define R_MSTP_MSTPCRC_CTSU (1 << 3) /* 08: Capacitive Touch Sensing Unit Module Stop */
+#define R_MSTP_MSTPCRC_CRC (1 << 1) /* 02: Cyclic Redundancy Check Calculator Module Stop */
+#define R_MSTP_MSTPCRC_CAC (1 << 0) /* 01: Clock Frequency Accuracy Measurement Circuit Module Stop */
+
+#define R_MSTP_MSTPCRD_OPAMP (1 << 31) /* 80000000: Operational Amplifier Module Stop */
+#define R_MSTP_MSTPCRD_ACMPLP (1 << 29) /* 20000000: Low-Power Analog Comparator Module Stop */
+#define R_MSTP_MSTPCRD_DAC12 (1 << 20) /* 100000: 12-Bit D/A Converter Module Stop */
+#define R_MSTP_MSTPCRD_DAC8 (1 << 19) /* 80000: 8-bit D/A Converter Module Stop */
+#define R_MSTP_MSTPCRD_ADC14 (1 << 16) /* 10000: 14-Bit A/D Converter Module Stop */
+#define R_MSTP_MSTPCRD_POEG (1 << 14) /* 4000: Port Output Enable for GPT Module Stop */
+#define R_MSTP_MSTPCRD_GPT_1 (1 << 6) /* 40: General PWM Timer 169 to 164 Module Stop */
+#define R_MSTP_MSTPCRD_GPT_2 (1 << 5) /* 20: General PWM Timer 323 to 320 Module Stop */
+#define R_MSTP_MSTPCRD_AGT0 (1 << 3) /* 08: Asynchronous General Purpose Timer 0 Module Stop */
+#define R_MSTP_MSTPCRD_AGT1 (1 << 2) /* 04: Asynchronous General Purpose Timer 1 Module Stop */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4_MSTP_H */
diff --git a/arch/arm/src/ra4/hardware/ra4m1_pinmap.h b/arch/arm/src/ra4/hardware/ra4m1_pinmap.h
new file mode 100644
index 0000000000000..3bfe48256dc6d
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra4m1_pinmap.h
@@ -0,0 +1,139 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra4m1_pinmap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA4M1_PINMAP_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA4M1_PINMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+#define R_PFS_PSEL_PORT_OFFSET 0x40
+#define R_PFS_PSEL_PIN_OFFSET 0x04
+#define R_PMISC_PWPR_OFFSET 0x0003
+
+/* Register Addresses *******************************************************/
+
+#define R_PFS(port,pin) (R_PFS_BASE + (port)*R_PFS_PSEL_PORT_OFFSET + (pin)*R_PFS_PSEL_PIN_OFFSET)
+#define R_PMISC_PWPR (R_PMISC_BASE + R_PMISC_PWPR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* PFS - Pmn Pin Function Control Register */
+
+#define R_PFS_PSEL_SHIFT (24) /* 1000000: Port Function Select These bits select the peripheral function. For individual pin functions, see the MPC table */
+#define R_PFS_PSEL_MASK (0x1f)
+#define R_PFS_PMR (1 << 16) /* Bit 16: Port Mode Control */
+#define R_PFS_ASEL (1 << 15) /* Bit 15: Analog Input enable */
+#define R_PFS_ISEL (1 << 14) /* Bit 14: IRQ input enable */
+#define R_PFS_EOR (1 << 13) /* Bit 13: Event on Rising */
+#define R_PFS_EOF (1 << 12) /* Bit 12: Event on Falling */
+#define R_PFS_DSCR1 (1 << 11) /* Bit 11: Port Drive Capability 1 */
+#define R_PFS_DSCR (1 << 10) /* Bit 10: Port Drive Capability */
+#define R_PFS_NCODR (1 << 6) /* Bit 6: N-Channel Open Drain Control */
+#define R_PFS_PCR (1 << 4) /* Bit 4: Pull-up Control */
+#define R_PFS_PDR (1 << 2) /* Bit 2: Port Direction */
+#define R_PFS_PIDR (1 << 1) /* Bit 1: Port Input Data */
+#define R_PFS_PODR (1 << 0) /* Bit 0: Port Output Data */
+
+/* PMISC - Miscellaneous Port Control Register */
+
+#define R_PMISC_PWPR_B0WI (1 << 7) /* 80: PFSWE Bit Write Disable */
+#define R_PMISC_PWPR_PFSWE (1 << 6) /* 40: PFS Register Write Enable */
+
+#define PFS_PSEL_HIZ (0x00 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_AGT (0x01 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_GPT (0x02 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_AGT1 (0x03 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_SCI (0x04 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_SCI1 (0x05 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_SPI (0x06 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_IIC (0x07 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_KINT (0x08 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_CLKOUT_ACMPLP_RTC (0x09 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_CAC_ADC14 (0x0a << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_CTSU (0x0c << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_SLCDC (0x0d << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_CAN (0x10 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_SSIE (0x12 << R_PFS_PSEL_SHIFT)
+#define PFS_PSEL_USBFS (0x13 << R_PFS_PSEL_SHIFT)
+
+/* SCI Alternative */
+
+#define GPIO_RXD0_MISO0_SCL0_1 (gpio_pinset_t){ PORT1,PIN0, (PFS_PSEL_SCI | R_PFS_PMR)}
+#define GPIO_TXD0_MOSI0_SDA0_1 (gpio_pinset_t){ PORT1,PIN1, (PFS_PSEL_SCI | R_PFS_PMR)}
+#define GPIO_RXD0_MISO0_SCL0_2 (gpio_pinset_t){ PORT2,PIN6, (PFS_PSEL_SCI | R_PFS_PMR)}
+#define GPIO_TXD0_MOSI0_SDA0_2 (gpio_pinset_t){ PORT2,PIN5, (PFS_PSEL_SCI | R_PFS_PMR)}
+#define GPIO_RXD0_MISO0_SCL0_3 (gpio_pinset_t){ PORT4,PIN10, (PFS_PSEL_SCI | R_PFS_PMR)}
+#define GPIO_TXD0_MOSI0_SDA0_3 (gpio_pinset_t){ PORT14,PIN11, (PFS_PSEL_SCI | R_PFS_PMR)}
+
+#define GPIO_RXD1_MISO1_SCL1_1 (gpio_pinset_t){ PORT2,PIN12, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_TXD1_MOSI1_SDA1_1 (gpio_pinset_t){ PORT2,PIN13, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_RXD1_MISO1_SCL1_2 (gpio_pinset_t){ PORT4,PIN2, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_TXD1_MOSI1_SDA1_2 (gpio_pinset_t){ PORT4,PIN1, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_RXD1_MISO1_SCL1_3 (gpio_pinset_t){ PORT5,PIN2, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_TXD1_MOSI1_SDA1_3 (gpio_pinset_t){ PORT5,PIN1, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+
+#define GPIO_RXD2_MISO2_SCL2_1 (gpio_pinset_t){ PORT3,PIN1, (PFS_PSEL_SCI | R_PFS_PMR)}
+#define GPIO_TXD2_MOSI2_SDA2_1 (gpio_pinset_t){ PORT3,PIN2, (PFS_PSEL_SCI | R_PFS_PMR)}
+
+#define GPIO_RXD9_MISO9_SCL9_1 (gpio_pinset_t){ PORT1,PIN10, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_TXD9_MOSI9_SDA9_1 (gpio_pinset_t){ PORT1,PIN9, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_RXD9_MISO9_SCL9_2 (gpio_pinset_t){ PORT2,PIN2, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_TXD9_MOSI9_SDA9_2 (gpio_pinset_t){ PORT2,PIN3, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_RXD9_MISO9_SCL9_3 (gpio_pinset_t){ PORT4,PIN8, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_TXD9_MOSI9_SDA9_3 (gpio_pinset_t){ PORT4,PIN9, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_RXD9_MISO9_SCL9_4 (gpio_pinset_t){ PORT6,PIN1, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+#define GPIO_TXD9_MOSI9_SDA9_4 (gpio_pinset_t){ PORT6,PIN2, (PFS_PSEL_SCI1 | R_PFS_PMR)}
+
+/* GPIO Configuration */
+
+#define GPIO_OUPUT R_PFS_PDR
+#define GPIO_INPUT ~(R_PFS_PDR | 0xFFFFFFFF)
+
+#define GPIO_LOW_DRIVE ~(R_PFS_DSCR | 0xFFFFFFFF)
+#define GPIO_MIDDLE_DRIVE R_PFS_DSCR
+
+#define GPIO_OUTPUT_HIGH R_PFS_PODR
+#define GPIO_OUTPUT_LOW ~(R_PFS_PODR | 0xFFFFFFFF)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_RA_HARDWARE_RA4M1_PINMAP_H */
diff --git a/arch/arm/src/ra4/hardware/ra_flash.h b/arch/arm/src/ra4/hardware/ra_flash.h
new file mode 100644
index 0000000000000..7d95031d1da7d
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra_flash.h
@@ -0,0 +1,63 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra_flash.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_FLASH_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_FLASH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+#include "ra_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_FCACHE_FCACHEE_OFFSET 0x0100 /* Flash Cache Enable Register (16-Bits) */
+#define R_FCACHE_FCACHEIV_OFFSET 0x0104 /* Flash Cache Invalidate Register (16-Bits) */
+#define R_FCACHE_FLWT_OFFSET 0x011c /* Flash Cache FLWT (8-Bits) */
+
+/* Register Addresses *******************************************************/
+
+# define R_FCACHE_FCACHEE (R_FCACHE_BASE + R_FCACHE_FCACHEE_OFFSET)
+# define R_FCACHE_FCACHEIV (R_FCACHE_BASE + R_FCACHE_FCACHEIV_OFFSET)
+# define R_FCACHE_FLWT (R_FCACHE_BASE + R_FCACHE_FLWT_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Flash Cache Enable Register (16-Bits) */
+
+#define R_FCACHE_FCACHEE_FCACHEEN (1 << 0) /* 01: FCACHE Enable */
+
+/* Flash Cache Invalidate Register (16-Bits) */
+
+#define R_FCACHE_FCACHEIV_FCACHEIV (1 << 0) /* 01: FCACHE Invalidation */
+
+/* Flash Cache FLWT (8-Bits) */
+
+#define R_FCACHE_FLWT_FLWT (3 << 0) /* 01: These bits represent the ratio of the CPU clock period to the Flash memory access time. */
+#define R_FCACHE_FLWT_FLWT_MASK (0x07)
+
+#endif /* __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_FLASH_H */
diff --git a/arch/arm/src/ra4/hardware/ra_gpio.h b/arch/arm/src/ra4/hardware/ra_gpio.h
new file mode 100644
index 0000000000000..25e49d4e0936a
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra_gpio.h
@@ -0,0 +1,188 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA_GPIO_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_PORT_PCNTR1_OFFSET 0x0000 /* Port Control Register 1 (32-bits) */
+#define R_PORT_PODR_OFFSET 0x0000 /* Pmn Output Data (16-bits) */
+#define R_PORT_PDR_OFFSET 0x0002 /* Pmn Direction (16-bits) */
+#define R_PORT_PCNTR2_OFFSET 0x0004 /* Port Control Register 2 (32-bits) */
+#define R_PORT_EIDR_OFFSET 0x0004 /* Port Event Input Data (16-bits) */
+#define R_PORT_PIDR_OFFSET 0x0006 /* Pmn State (16-bits) */
+#define R_PORT_PCNTR3_OFFSET 0x0008 /* Port Control Register 3 (32-bits) */
+#define R_PORT_PORR_OFFSET 0x0008 /* Pmn Output Reset (16-bits) */
+#define R_PORT_POSR_OFFSET 0x000a /* Pmn Output Set (16-bits) */
+#define R_PORT_PCNTR4_OFFSET 0x000c /* Port Control Register 3 (32-bits) */
+#define R_PORT_EORR_OFFSET 0x000c /* Pmn Event Output Set (16-bits) */
+#define R_PORT_EOSR_OFFSET 0x000e /* Pmn Output Reset (16-bits) */
+
+#define R_PORT_OFFSET 0x0020 /* Relative Port Offset */
+
+/* Register Addresses *******************************************************/
+
+#define PORT0 (0)
+#define PORT1 (1)
+#define PORT2 (2)
+#define PORT3 (3)
+#define PORT4 (4)
+#define PORT5 (5)
+#define PORT6 (6)
+#define PORT7 (7)
+#define PORT8 (8)
+#define PORT9 (9)
+
+#define PIN0 (0)
+#define PIN1 (1)
+#define PIN2 (2)
+#define PIN3 (3)
+#define PIN4 (4)
+#define PIN5 (5)
+#define PIN6 (6)
+#define PIN7 (7)
+#define PIN8 (8)
+#define PIN9 (9)
+#define PIN10 (10)
+#define PIN11 (11)
+#define PIN12 (12)
+#define PIN13 (13)
+#define PIN14 (14)
+#define PIN15 (15)
+
+/* Relative PORT Registers */
+
+# define R_PORT_PCNTR1(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PCNTR1_OFFSET)
+# define R_PORT_PODR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PODR_OFFSET)
+# define R_PORT_PDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PDR_OFFSET)
+# define R_PORT_PCNTR2(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PCNTR2_OFFSET)
+# define R_PORT_EIDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_EIDR_OFFSET)
+# define R_PORT_PIDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PIDR_OFFSET)
+# define R_PORT_PCNTR3(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PCNTR3_OFFSET)
+# define R_PORT_PORR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PORR_OFFSET)
+# define R_PORT_POSR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_POSR_OFFSET)
+# define R_PORT_PCNTR4(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PCNTR4_OFFSET)
+# define R_PORT_EORR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_EORR_OFFSET)
+# define R_PORT_EOSR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_EOSR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Port Control Register 1 (32-bits) */
+
+#define R_PORT_PCNTR1_PODR_SHIFT (16) /* 10000: Pmn Output Data */
+#define R_PORT_PCNTR1_PODR_MASK (0xffff)
+#define R_PORT_PCNTR1_PDR_SHIFT (0) /* 01: Pmn Direction */
+#define R_PORT_PCNTR1_PDR_MASK (0xffff)
+
+/* Pmn Output Data (16-bits) */
+
+#define R_PORT_PODR_PODR_SHIFT (0) /* 01: Pmn Output Data */
+#define R_PORT_PODR_PODR_MASK (0xffff)
+
+/* Pmn Direction (16-bits) */
+
+#define R_PORT_PDR_PDR_SHIFT (0) /* 01: Pmn Direction */
+#define R_PORT_PDR_PDR_MASK (0xffff)
+
+/* Port Control Register 2 (32-bits) */
+
+#define R_PORT_PCNTR2_EIDR_SHIFT (16) /* 10000: Pmn Event Input Data */
+#define R_PORT_PCNTR2_EIDR_MASK (0xffff)
+#define R_PORT_PCNTR2_PIDR_SHIFT (0) /* 01: Pmn Input Data */
+#define R_PORT_PCNTR2_PIDR_MASK (0xffff)
+
+/* Port Event Input Data (16-bits) */
+
+#define R_PORT_EIDR_EIDR_SHIFT (0) /* 01: Pmn Event Input Data */
+#define R_PORT_EIDR_EIDR_MASK (0xffff)
+
+/* Pmn State (16-bits) */
+
+#define R_PORT_PIDR_PIDR_SHIFT (0) /* 01: Pmn Input Data */
+#define R_PORT_PIDR_PIDR_MASK (0xffff)
+
+/* Port Control Register 3 (32-bits) */
+
+#define R_PORT_PCNTR3_PORR_SHIFT (16) /* 10000: Pmn Output Reset */
+#define R_PORT_PCNTR3_PORR_MASK (0xffff)
+#define R_PORT_PCNTR3_POSR_SHIFT (0) /* 01: Pmn Output Set */
+#define R_PORT_PCNTR3_POSR_MASK (0xffff)
+
+/* Pmn Output Reset (16-bits) */
+
+#define R_PORT_PORR_PORR_SHIFT (0) /* 01: Pmn Output Reset */
+#define R_PORT_PORR_PORR_MASK (0xffff)
+
+/* Pmn Output Set (16-bits) */
+
+#define R_PORT_POSR_POSR_SHIFT (0) /* 01: Pmn Output Set */
+#define R_PORT_POSR_POSR_MASK (0xffff)
+
+/* Port Control Register 3 (32-bits) */
+
+#define R_PORT_PCNTR4_EORR_SHIFT (16) /* 10000: Pmn Event Output Reset */
+#define R_PORT_PCNTR4_EORR_MASK (0xffff)
+#define R_PORT_PCNTR4_EOSR_SHIFT (0) /* 01: Pmn Event Output Set */
+#define R_PORT_PCNTR4_EOSR_MASK (0xffff)
+
+/* Pmn Event Output Set (16-bits) */
+
+#define R_PORT_EORR_EORR_SHIFT (0) /* 01: Pmn Event Output Reset */
+#define R_PORT_EORR_EORR_MASK (0xffff)
+
+/* Pmn Output Reset (16-bits) */
+
+#define R_PORT_EOSR_EOSR_SHIFT (0) /* 01: Pmn Event Output Set */
+#define R_PORT_EOSR_EOSR_MASK (0xffff)
+
+/* PMISC - Miscellaneous Port Control Register */
+
+#define R_PMISC_PWPR_OFFSET 0x0003
+#define R_PMISC_PWPR (R_PMISC_BASE + R_PMISC_PWPR_OFFSET)
+#define R_PMISC_PWPR_B0WI (1 << 7) /* 80: PFSWE Bit Write Disable */
+#define R_PMISC_PWPR_PFSWE (1 << 6) /* 40: PFS Register Write Enable */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_RA_HARDWARE_RA_GPIO_H */
diff --git a/arch/arm/src/ra4/hardware/ra_icu.h b/arch/arm/src/ra4/hardware/ra_icu.h
new file mode 100644
index 0000000000000..846699e0ca720
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra_icu.h
@@ -0,0 +1,191 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra_icu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA_ICU_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA_ICU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+#if defined(CONFIG_RA4M1_FAMILY)
+# include "hardware/ra4m1_icu.h"
+#else
+# error "Unsupported RA memory map"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_ICU_IRQCR_OFFSET 0x0000 /* IRQ Control Register (8-bits) */
+#define R_ICU_NMISR_OFFSET 0x0140 /* Non-Maskable Interrupt Status Register (16-bits) */
+#define R_ICU_NMIER_OFFSET 0x0120 /* Non-Maskable Interrupt Enable Register (16-bits) */
+#define R_ICU_NMICLR_OFFSET 0x0130 /* Non-Maskable Interrupt Status Clear Register (16-bits) */
+#define R_ICU_NMICR_OFFSET 0x0100 /* NMI Pin Interrupt Control Register (8-bits) */
+#define R_ICU_IELSR_OFFSET 0x0300 /* ICU Event Link Setting Register (32-bits) */
+#define R_ICU_DELSR_OFFSET 0x0280 /* DMAC Event Link Setting Register (32-bits) */
+#define R_ICU_SELSR0_OFFSET 0x0200 /* SYS Event Link Setting Register (16-bits) */
+#define R_ICU_WUPEN_OFFSET 0x01a0 /* Wake Up Interrupt Enable Register (32-bits) */
+
+/* Register Addresses *******************************************************/
+
+#define R_ICU_IRQCR(p) (R_ICU_BASE + R_ICU_IRQCR_OFFSET + (p)*0x0001)
+#define R_ICU_NMISR (R_ICU_BASE + R_ICU_NMISR_OFFSET)
+#define R_ICU_NMIER (R_ICU_BASE + R_ICU_NMIER_OFFSET)
+#define R_ICU_NMICLR (R_ICU_BASE + R_ICU_NMICLR_OFFSET)
+#define R_ICU_NMICR (R_ICU_BASE + R_ICU_NMICR_OFFSET)
+#define R_ICU_IELSR(p) (R_ICU_BASE + R_ICU_IELSR_OFFSET + (p)*0x0004)
+#define R_ICU_DELSR(p) (R_ICU_BASE + R_ICU_DELSR_OFFSET + (p)*0x0004)
+#define R_ICU_SELSR0 (R_ICU_BASE + R_ICU_SELSR0_OFFSET)
+#define R_ICU_WUPEN (R_ICU_BASE + R_ICU_WUPEN_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* IRQ Control Register (8-bits) */
+
+#define R_ICU_IRQCR_SIZE 15
+#define R_ICU_IRQCR_FLTEN (1 << 7) /* 80: IRQ Digital Filter Enable */
+#define R_ICU_IRQCR_FCLKSEL_SHIFT (4) /* 10: IRQ Digital Filter Sampling Clock Select */
+#define R_ICU_IRQCR_FCLKSEL_MASK (0x03)
+#define R_ICU_IRQCR_IRQMD (0) /* 01: IRQ Detection Sense Select */
+#define R_ICU_IRQCR_IRQMD_MASK (0x03)
+
+/* Non-Maskable Interrupt Status Register (16-bits) */
+
+#define R_ICU_NMISR_SPEST (1 << 12) /* 1000: CPU Stack pointer monitor Interrupt Status Flag */
+#define R_ICU_NMISR_BUSMST (1 << 11) /* 800: MPU Bus Master Error Interrupt Status Flag */
+#define R_ICU_NMISR_BUSSST (1 << 10) /* 400: MPU Bus Slave Error Interrupt Status Flag */
+#define R_ICU_NMISR_RECCST (1 << 9) /* 200: RAM ECC Error Interrupt Status Flag */
+#define R_ICU_NMISR_RPEST (1 << 8) /* 100: RAM Parity Error Interrupt Status Flag */
+#define R_ICU_NMISR_NMIST (1 << 7) /* 80: NMI Status Flag */
+#define R_ICU_NMISR_OSTST (1 << 6) /* 40: Oscillation Stop Detection Interrupt Status Flag */
+#define R_ICU_NMISR_VBATTST (1 << 4) /* 10: VBATT monitor Interrupt Status Flag */
+#define R_ICU_NMISR_LVD2ST (1 << 3) /* 08: Voltage-Monitoring 2 Interrupt Status Flag */
+#define R_ICU_NMISR_LVD1ST (1 << 2) /* 04: Voltage-Monitoring 1 Interrupt Status Flag */
+#define R_ICU_NMISR_WDTST (1 << 1) /* 02: WDT Underflow/Refresh Error Status Flag */
+#define R_ICU_NMISR_IWDTST (1 << 0) /* 01: IWDT Underflow/Refresh Error Status Flag */
+
+/* Non-Maskable Interrupt Enable Register (16-bits) */
+
+#define R_ICU_NMIER_SPEEN (1 << 12) /* 1000: CPU Stack pointer monitor Interrupt Enable */
+#define R_ICU_NMIER_BUSMEN (1 << 11) /* 800: MPU Bus Master Error Interrupt Enable */
+#define R_ICU_NMIER_BUSSEN (1 << 10) /* 400: MPU Bus Slave Error Interrupt Enable */
+#define R_ICU_NMIER_RECCEN (1 << 9) /* 200: RAM ECC Error Interrupt Enable */
+#define R_ICU_NMIER_RPEEN (1 << 8) /* 100: RAM Parity Error Interrupt Enable */
+#define R_ICU_NMIER_NMIEN (1 << 7) /* 80: NMI Pin Interrupt Enable */
+#define R_ICU_NMIER_OSTEN (1 << 6) /* 40: Oscillation Stop Detection Interrupt Enable */
+#define R_ICU_NMIER_VBATTEN (1 << 4) /* 10: VBATT monitor Interrupt Enable */
+#define R_ICU_NMIER_LVD2EN (1 << 3) /* 08: Voltage-Monitoring 2 Interrupt Enable */
+#define R_ICU_NMIER_LVD1EN (1 << 2) /* 04: Voltage-Monitoring 1 Interrupt Enable */
+#define R_ICU_NMIER_WDTEN (1 << 1) /* 02: WDT Underflow/Refresh Error Interrupt Enable */
+#define R_ICU_NMIER_IWDTEN (1 << 0) /* 01: IWDT Underflow/Refresh Error Interrupt Enable */
+
+/* Non-Maskable Interrupt Status Clear Register (16-bits) */
+
+#define R_ICU_NMICLR_SPECLR (1 << 12) /* 1000: CPU Stack Pointer Monitor Interrupt Clear */
+#define R_ICU_NMICLR_BUSMCLR (1 << 11) /* 800: Bus Master Error Clear */
+#define R_ICU_NMICLR_BUSSCLR (1 << 10) /* 400: Bus Slave Error Clear */
+#define R_ICU_NMICLR_RECCCLR (1 << 9) /* 200: SRAM ECC Error Clear */
+#define R_ICU_NMICLR_RPECLR (1 << 8) /* 100: SRAM Parity Error Clear */
+#define R_ICU_NMICLR_NMICLR (1 << 7) /* 80: NMI Clear */
+#define R_ICU_NMICLR_OSTCLR (1 << 6) /* 40: OST Clear */
+#define R_ICU_NMICLR_VBATTCLR (1 << 4) /* 10: VBATT Clear */
+#define R_ICU_NMICLR_LVD2CLR (1 << 3) /* 08: LVD2 Clear */
+#define R_ICU_NMICLR_LVD1CLR (1 << 2) /* 04: LVD1 Clear */
+#define R_ICU_NMICLR_WDTCLR (1 << 1) /* 02: WDT Clear */
+#define R_ICU_NMICLR_IWDTCLR (1 << 0) /* 01: IWDT Clear */
+
+/* NMI Pin Interrupt Control Register (8-bits) */
+
+#define R_ICU_NMICR_NFLTEN (1 << 7) /* 80: NMI Digital Filter Enable */
+#define R_ICU_NMICR_NFCLKSEL_SHIFT (4) /* 10: NMI Digital Filter Sampling Clock Select */
+#define R_ICU_NMICR_NFCLKSEL_MASK (0x03)
+#define R_ICU_NMICR_NMIMD (1 << 0) /* 01: NMI Detection Set */
+
+/* ICU Event Link Setting Register (32-bits) */
+
+#define R_ICU_IELSR_SIZE 32
+#define R_ICU_IELSR_DTCE (1 << 24) /* 1000000: DTC Activation Enable */
+#define R_ICU_IELSR_IR (1 << 16) /* 10000: Interrupt Status Flag */
+#define R_ICU_IELSR_IELS_SHIFT (0) /* 01: ICU Event selection to NVIC Set the number for the event signal to be linked . */
+#define R_ICU_IELSR_IELS_MASK (0xff)
+
+/* DMAC Event Link Setting Register (32-bits) */
+
+#define R_ICU_DELSR_SIZE 4
+#define R_ICU_DELSR_DELS_SHIFT (0) /* 01: Event selection to DMAC Start request */
+#define R_ICU_DELSR_DELS_MASK (0xff)
+
+/* SYS Event Link Setting Register (16-bits) */
+
+#define R_ICU_SELSR0_SELS_SHIFT (0) /* 01: SYS Event Link Select */
+#define R_ICU_SELSR0_SELS_MASK (0xff)
+
+/* Wake Up Interrupt Enable Register (32-bits) */
+
+#define R_ICU_WUPEN_IIC0WUPEN (1 << 31) /* 80000000: IIC0 address match interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_AGT1CBWUPEN (1 << 30) /* 40000000: AGT1 compare match B interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_AGT1CAWUPEN (1 << 29) /* 20000000: AGT1 compare match A interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_AGT1UDWUPEN (1 << 28) /* 10000000: AGT1 underflow interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_USBFSWUPEN (1 << 27) /* 8000000: USBFS interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_RTCPRDWUPEN (1 << 25) /* 2000000: RCT period interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_RTCALMWUPEN (1 << 24) /* 1000000: RTC alarm interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_ACMPLP0WUPEN (1 << 23) /* 800000: ACMPLP0 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_VBATTWUPEN (1 << 20) /* 100000: VBATT monitor interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_LVD2WUPEN (1 << 19) /* 80000: LVD2 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_LVD1WUPEN (1 << 18) /* 40000: LVD1 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_KEYWUPEN (1 << 17) /* 20000: Key interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IWDTWUPEN (1 << 16) /* 10000: IWDT interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN15 (1 << 15) /* 8000: IRQ15 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN14 (1 << 14) /* 4000: IRQ14 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN12 (1 << 12) /* 1000: IRQ12 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN11 (1 << 11) /* 800: IRQ11 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN10 (1 << 10) /* 400: IRQ10 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN9 (1 << 9) /* 200: IRQ9 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN8 (1 << 8) /* 100: IRQ8 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN7 (1 << 7) /* 80: IRQ7 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN6 (1 << 6) /* 40: IRQ6 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN5 (1 << 5) /* 20: IRQ5 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN4 (1 << 4) /* 10: IRQ4 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN3 (1 << 3) /* 08: IRQ3 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN2 (1 << 2) /* 04: IRQ2 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN1 (1 << 1) /* 02: IRQ1 interrupt S/W standby returns enable */
+#define R_ICU_WUPEN_IRQWUPEN0 (1 << 0) /* 01: IRQ0 interrupt S/W standby returns enable */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_RA4M1_HARDWARE_RA_ICU_H */
diff --git a/arch/arm/src/ra4/hardware/ra_memorymap.h b/arch/arm/src/ra4/hardware/ra_memorymap.h
new file mode 100644
index 0000000000000..f3b7c05dd2a0c
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra_memorymap.h
@@ -0,0 +1,37 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA_MEMORYMAP_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA_MEMORYMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include "chip.h"
+
+#if defined(CONFIG_RA4M1_FAMILY)
+# include "hardware/ra4m1_memorymap.h"
+#else
+# error "Unsupported RA memory map"
+#endif
+
+#endif /* __ARCH_ARM_SRC_RA_HARDWARE_RA_MEMORYMAP_H */
diff --git a/arch/arm/src/ra4/hardware/ra_mpu.h b/arch/arm/src/ra4/hardware/ra_mpu.h
new file mode 100644
index 0000000000000..0278c1a052592
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra_mpu.h
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra_mpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+#include "ra4m1_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_MMPU_MMPUCTLA_OFFSET 0x0000
+#define R_MMPU_MMPUACA_OFFSET 0x0200
+#define R_MMPU_MMPUSA_OFFSET 0x0204
+#define R_MMPU_MMPUEA_OFFSET 0x0208
+#define R_MMPU_MMPUPTA_OFFSET 0x0102
+#define R_SMPU_SMPUCTL_OFFSET 0x0000
+#define R_SMPU_SMPUMBIU_OFFSET 0x0010
+#define R_SMPU_SMPUFBIU_OFFSET 0x0014
+#define R_SMPU_SMPUSRAM0_OFFSET 0x0018
+#define R_SMPU_SMPUPBIU_OFFSET 0x0020
+#define R_SPMON_MSPMPUOAD_OFFSET 0x0000
+#define R_SPMON_MSPMPUCTL_OFFSET 0x0004
+#define R_SPMON_MSPMPUPT_OFFSET 0x0006
+#define R_SPMON_MSPMPUSA_OFFSET 0x0008
+#define R_SPMON_MSPMPUEA_OFFSET 0x000c
+#define R_SPMON_PSPMPUOAD_OFFSET 0x0010
+#define R_SPMON_PSPMPUCTL_OFFSET 0x0014
+#define R_SPMON_PSPMPUPT_OFFSET 0x0016
+#define R_SPMON_PSPMPUSA_OFFSET 0x0018
+#define R_SPMON_PSPMPUEA_OFFSET 0x001c
+
+/* Register Addresses *******************************************************/
+
+#define R_MMPU_MMPUCTLA (R_MMPU_BASE + R_MMPU_MMPUCTLA_OFFSET) /* MMPU Control Register A (32-bits) */
+#define R_MMPU_MMPUACA(p) (R_MMPU_BASE + R_MMPU_MMPUACA_OFFSET + (p)*0x0010) /* MMPU Access Control Register A (32-bits) */
+#define R_MMPU_MMPUSA(p) (R_MMPU_BASE + R_MMPU_MMPUSA_OFFSET + (p)*0x0010) /* MMPU Start Address Register A (32-bits) */
+#define R_MMPU_MMPUEA(p) (R_MMPU_BASE + R_MMPU_MMPUEA_OFFSET + (p)*0x0010) /* MMPU End Address Register A (32-bits) */
+#define R_MMPU_MMPUPTA (R_MMPU_BASE + R_MMPU_MMPUPTA_OFFSET) /* MMPU Protection Type Register A (16-bits) */
+#define R_SMPU_SMPUCTL (R_SMPU_BASE + R_SMPU_SMPUCTL_OFFSET) /* SMPU Control Register (32-bits) */
+#define R_SMPU_SMPUMBIU (R_SMPU_BASE + R_SMPU_SMPUMBIU_OFFSET) /* SMPU Master Bus Interface Unit Register (32-bits) */
+#define R_SMPU_SMPUFBIU (R_SMPU_BASE + R_SMPU_SMPUFBIU_OFFSET) /* SMPU Function Bus Interface Unit Register (32-bits) */
+#define R_SMPU_SMPUSRAM0 (R_SMPU_BASE + R_SMPU_SMPUSRAM0_OFFSET) /* SMPU SRAM Protection Register 0 (32-bits) */
+#define R_SMPU_SMPUPBIU(p) (R_SMPU_BASE + R_SMPU_SMPUPBIU_OFFSET + (p)*0x0004) /* SMPU Peripheral Bus Interface Unit Register (32-bits) */
+#define R_SPMON_MSPMPUOAD (R_SPMON_BASE + R_SPMON_MSPMPUOAD_OFFSET) /* Secure Protection Monitor Master MPU Override Address Register (32-bits) */
+#define R_SPMON_MSPMPUCTL (R_SPMON_BASE + R_SPMON_MSPMPUCTL_OFFSET) /* Secure Protection Monitor Master MPU Control Register (32-bits) */
+#define R_SPMON_MSPMPUPT (R_SPMON_BASE + R_SPMON_MSPMPUPT_OFFSET) /* Secure Protection Monitor Master MPU Protection Type Register (16-bits) */
+#define R_SPMON_MSPMPUSA (R_SPMON_BASE + R_SPMON_MSPMPUSA_OFFSET) /* Secure Protection Monitor Master MPU Start Address Register (32-bits) */
+#define R_SPMON_MSPMPUEA (R_SPMON_BASE + R_SPMON_MSPMPUEA_OFFSET) /* Secure Protection Monitor Master MPU End Address Register (32-bits) */
+#define R_SPMON_PSPMPUOAD (R_SPMON_BASE + R_SPMON_PSPMPUOAD_OFFSET) /* Secure Protection Monitor Peripheral MPU Override Address Register (32-bits) */
+#define R_SPMON_PSPMPUCTL (R_SPMON_BASE + R_SPMON_PSPMPUCTL_OFFSET) /* Secure Protection Monitor Peripheral MPU Control Register (32-bits) */
+#define R_SPMON_PSPMPUPT (R_SPMON_BASE + R_SPMON_PSPMPUPT_OFFSET) /* Secure Protection Monitor Peripheral MPU Protection Type Register (16-bits) */
+#define R_SPMON_PSPMPUSA (R_SPMON_BASE + R_SPMON_PSPMPUSA_OFFSET) /* Secure Protection Monitor Peripheral MPU Start Address Register (32-bits) */
+#define R_SPMON_PSPMPUEA (R_SPMON_BASE + R_SPMON_PSPMPUEA_OFFSET) /* Secure Protection Monitor Peripheral MPU End Address Register (32-bits) */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MMPU Control Register A (32-bits) */
+
+#define R_MMPU_MMPUCTLA_KEY (8 << 8) /* 100: Key Code These bits are used to enable or disable writing of the OAD and ENABLE bit. */
+#define R_MMPU_MMPUCTLA_KEY_MASK (0xff)
+#define R_MMPU_MMPUCTLA_OAD (1 << 1) /* 02: Operation after detection */
+#define R_MMPU_MMPUCTLA_ENABLE (1 << 0) /* 01: Master Group enable */
+#define R_MMPU_MMPUACA_SIZE (16)
+
+/* MMPU Access Control Register A (32-bits) */
+
+#define R_MMPU_MMPUACA_WP (1 << 2) /* 04: Write protection */
+#define R_MMPU_MMPUACA_RP (1 << 1) /* 02: Read protection */
+#define R_MMPU_MMPUACA_ENABLE (1 << 0) /* 01: Region enable */
+#define R_MMPU_MMPUSA_SIZE (16)
+
+/* MMPU Start Address Register A (32-bits) */
+
+#define R_MMPU_MMPUSA_MMPUSA (32 << 0) /* 01: Address where the region starts, for use in region determination. NOTE: The low-order 2 bits are fixed to 0. */
+#define R_MMPU_MMPUSA_MMPUSA_MASK (0xffffffff)
+#define R_MMPU_MMPUEA_SIZE (16)
+
+/* MMPU End Address Register A (32-bits) */
+
+#define R_MMPU_MMPUEA_MMPUEA (32 << 0) /* 01: Region end address register Address where the region end, for use in region determination. NOTE: The low-order 2 bits are fixed to 1. */
+#define R_MMPU_MMPUEA_MMPUEA_MASK (0xffffffff)
+
+/* MMPU Protection Type Register A (16-bits) */
+
+#define R_MMPU_MMPUPTA_KEY (8 << 8) /* 100: Write Keyword The data written to these bits are not stored. */
+#define R_MMPU_MMPUPTA_KEY_MASK (0xff)
+#define R_MMPU_MMPUPTA_PROTECT (1 << 0) /* 01: Protection of register (MMPUSAn, MMPUEAn and MMPUACAn) */
+
+/* SMPU Control Register (32-bits) */
+
+#define R_SMPU_SMPUCTL_KEY (8 << 8) /* 100: Key Code This bit is used to enable or disable rewriting of the PROTECT and OAD bit. */
+#define R_SMPU_SMPUCTL_KEY_MASK (0xff)
+#define R_SMPU_SMPUCTL_PROTECT (1 << 1) /* 02: Protection of register */
+#define R_SMPU_SMPUCTL_OAD (1 << 0) /* 01: Master Group enable */
+
+/* SMPU Master Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUMBIU_WPGRPA (1 << 3) /* 08: Master Group A Write protection */
+#define R_SMPU_SMPUMBIU_RPGRPA (1 << 2) /* 04: Master Group A Read protection */
+
+/* SMPU Function Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUFBIU_WPGRPA (1 << 3) /* 08: Master Group A Write protection */
+#define R_SMPU_SMPUFBIU_RPGRPA (1 << 2) /* 04: Master Group A Read protection */
+#define R_SMPU_SMPUFBIU_WPCPU (1 << 1) /* 02: CPU Write protection */
+#define R_SMPU_SMPUFBIU_RPCPU (1 << 0) /* 01: CPU Read protection */
+
+/* SMPU SRAM Protection Register 0 (32-bits) */
+
+#define R_SMPU_SMPUSRAM0_WPGRPA (1 << 3) /* 08: Master Group A Write protection */
+#define R_SMPU_SMPUSRAM0_RPGRPA (1 << 2) /* 04: Master Group A Read protection */
+#define R_SMPU_SMPUSRAM0_WPCPU (1 << 1) /* 02: CPU Write protection */
+#define R_SMPU_SMPUSRAM0_RPCPU (1 << 0) /* 01: CPU Read protection */
+#define R_SMPU_SMPUPBIU_SIZE (3)
+
+/* SMPU Peripheral Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUPBIU_WPGRPA (1 << 3) /* 08: Master Group A Write protection */
+#define R_SMPU_SMPUPBIU_RPGRPA (1 << 2) /* 04: Master Group A Read protection */
+#define R_SMPU_SMPUPBIU_WPCPU (1 << 1) /* 02: CPU Write protection */
+#define R_SMPU_SMPUPBIU_RPCPU (1 << 0) /* 01: CPU Read protection */
+
+/* Secure Protection Monitor Master MPU Override Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUOAD_KEY (8 << 8) /* 100: Write Keyword The data written to these bits are not stored. */
+#define R_SPMON_MSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUOAD_OAD (1 << 0) /* 01: Operation after detection */
+
+/* Secure Protection Monitor Master MPU Control Register (32-bits) */
+
+#define R_SPMON_MSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer Monitor Error Flag */
+#define R_SPMON_MSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer Monitor Enable */
+
+/* Secure Protection Monitor Master MPU Protection Type Register (16-bits) */
+
+#define R_SPMON_MSPMPUPT_KEY (8 << 8) /* 100: Write Keyword The data written to these bits are not stored. */
+#define R_SPMON_MSPMPUPT_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUPT_PROTECT (1 << 0) /* 01: Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */
+
+/* Secure Protection Monitor Master MPU Start Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUSA_MSPMPUSA (32 << 0) /* 01: Region start address register Address where the region starts, for use in region determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0. */
+#define R_SPMON_MSPMPUSA_MSPMPUSA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Master MPU End Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUEA_MSPMPUEA (32 << 0) /* 01: Region end address register Address where the region starts, for use in region determination. NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. */
+#define R_SPMON_MSPMPUEA_MSPMPUEA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Peripheral MPU Override
+ * Address Register (32-bits)
+ */
+
+#define R_SPMON_PSPMPUOAD_KEY (8 << 8) /* 100: Key Code The data written to these bits are not stored. */
+#define R_SPMON_PSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_PSPMPUOAD_OAD (1 << 0) /* 01: Operation after detection */
+
+/* Secure Protection Monitor Peripheral MPU Control Register (32-bits) */
+
+#define R_SPMON_PSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer Monitor Error Flag */
+#define R_SPMON_PSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer Monitor Enable */
+
+/* Secure Protection Monitor Peripheral MPU Protection
+ * Type Register (16-bits)
+ */
+
+#define R_SPMON_PSPMPUPT_KEY (8 << 8) /* 100: Key Code The data written to these bits are not stored. */
+#define R_SPMON_PSPMPUPT_KEY_MASK (0xff)
+#define R_SPMON_PSPMPUPT_PROTECT (1 << 0) /* 01: Protection register */
+
+/* Secure Protection Monitor Peripheral MPU Start
+ * Address Register (32-bits)
+ */
+
+#define R_SPMON_PSPMPUSA_PSPMPUSA (32 << 0) /* 01: Region start address register Address where the region starts, for use in region determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0. */
+#define R_SPMON_PSPMPUSA_PSPMPUSA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Peripheral MPU End Address Register (32-bits) */
+
+#define R_SPMON_PSPMPUEA_PSPMPUEA (32 << 0) /* 01: Region end address register Address where the region starts, for use in region determination. NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. */
+#define R_SPMON_PSPMPUEA_PSPMPUEA_MASK (0xffffffff)
+
+#endif /* __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_FLASH_H */
diff --git a/arch/arm/src/ra4/hardware/ra_mstp.h b/arch/arm/src/ra4/hardware/ra_mstp.h
new file mode 100644
index 0000000000000..24a34edc448b4
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra_mstp.h
@@ -0,0 +1,54 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra_mstp.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA_MSTP_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA_MSTP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+
+#if defined(CONFIG_RA4M1_FAMILY)
+# include "hardware/ra4m1_mstp.h"
+#else
+# error "Unsupported RA Module Stop Control map"
+#endif
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4_MSTP_H */
diff --git a/arch/arm/src/ra4/hardware/ra_option_setting.h b/arch/arm/src/ra4/hardware/ra_option_setting.h
new file mode 100644
index 0000000000000..b6745da7b8582
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra_option_setting.h
@@ -0,0 +1,162 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra_option_setting.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA_OFS_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA_OFS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+
+#if defined(CONFIG_RA4M1_FAMILY)
+# include "hardware/ra4m1_pinmap.h"
+#else
+# error "Unsupported RA memory map"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_OFS0_OFFSET 0x0000 /* Option Function Select Register 0 (32-bits) */
+#define R_OFS1_OFFSET 0x0004 /* Option Function Select Register 1 (32-bits) */
+
+/* Register Addresses *******************************************************/
+
+/* Option Function Select Registers */
+
+# define R_OFS0 (R_OFS_BASE + R_OFS0_OFFSET)
+# define R_OFS1 (R_OFS_BASE + R_OFS1_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Option Function Select Register 0 */
+
+#define R_OFS0_RESERVED_31 (1 << 31) /* Bit 31: Reserved */
+#define R_OFS0_WDTSTPCTL (1 << 30) /* Bit 30: WDT Stop Control */
+#define R_OFS0_RESERVED_29 (1 << 29) /* Bit 29: Reserved */
+#define R_OFS0_WDTRSTIRQS (1 << 28) /* Bit 28: WDT Reset Interrupt Request Select*/
+#define R_OFS0_WDTRPSS_SHIFT (26) /* Bit 27-26: WDT Window Start Position Select*/
+#define R_OFS0_WDTRPSS_MASK (3 << R_OFS0_WDTRPSS_SHIFT)
+# define R_OFS0_WDTRPSS_25 (0 << R_OFS0_WDTRPSS_SHIFT) /* WDT Window Start Position Select 25% */
+# define R_OFS0_WDTRPSS_50 (1 << R_OFS0_WDTRPSS_SHIFT) /* WDT Window Start Position Select 50% */
+# define R_OFS0_WDTRPSS_75 (2 << R_OFS0_WDTRPSS_SHIFT) /* WDT Window Start Position Select 75% */
+# define R_OFS0_WDTRPSS_100 (3 << R_OFS0_WDTRPSS_SHIFT) /* WDT Window Start Position Select 100% */
+#define R_OFS0_WDTRPES_SHIFT (24) /* Bit 25-24: WDT Window End Position Select*/
+#define R_OFS0_WDTRPES_MASK (3 << R_OFS0_WDTRPES_SHIFT)
+# define R_OFS0_WDTRPES_75 (0 << R_OFS0_WDTRPES_SHIFT) /* WDT Window End Position Select 75% */
+# define R_OFS0_WDTRPES_50 (1 << R_OFS0_WDTRPES_SHIFT) /* WDT Window End Position Select 50% */
+# define R_OFS0_WDTRPES_25 (2 << R_OFS0_WDTRPES_SHIFT) /* WDT Window End Position Select 25% */
+# define R_OFS0_WDTRPES_0 (3 << R_OFS0_WDTRPES_SHIFT) /* WDT Window End Position Select 0% */
+#define R_OFS0_WDTCKS_SHIFT (20) /* Bit 23-20: WDT Clock Frequency Division Ratio Select*/
+#define R_OFS0_WDTCKS_MASK (0xF << R_OFS0_WDTCKS_SHIFT)
+# define R_OFS0_WDTCKS_DIV_4 (1 << R_OFS0_WDTCKS_SHIFT) /* PCLKB divided by 4 */
+# define R_OFS0_WDTCKS_DIV_64 (4 << R_OFS0_WDTCKS_SHIFT) /* PCLKB divided by 64 */
+# define R_OFS0_WDTCKS_DIV_128 (15 << R_OFS0_WDTCKS_SHIFT) /* PCLKB divided by 128 */
+# define R_OFS0_WDTCKS_DIV_512 (6 << R_OFS0_WDTCKS_SHIFT) /* PCLKB divided by 512 */
+# define R_OFS0_WDTCKS_DIV_2048 (7 << R_OFS0_WDTCKS_SHIFT) /* PCLKB divided by 2048 */
+# define R_OFS0_WDTCKS_DIV_8192 (8 << R_OFS0_WDTCKS_SHIFT) /* PCLKB divided by 8192 */
+#define R_OFS0_WDTTOPS_SHIFT (18) /* Bit 19-18: WDT Timeout Period Select */
+#define R_OFS0_WDTTOPS_MASK (3 << R_OFS0_WDTTOPS_SHIFT)
+# define R_OFS0_WDTTOPS_1024_CYCLES (0 << R_OFS0_WDTTOPS_SHIFT) /* 1024 cycles */
+# define R_OFS0_WDTTOPS_4096_CYCLES (1 << R_OFS0_WDTTOPS_SHIFT) /* 4096 cycles */
+# define R_OFS0_WDTTOPS_8192_CYCLES (2 << R_OFS0_WDTTOPS_SHIFT) /* 8192 cycles */
+# define R_OFS0_WDTTOPS_16384_CYCLES (3 << R_OFS0_WDTTOPS_SHIFT) /* 16384 cycles */
+#define R_OFS0_RESERVED_16_15_SHIFT (15) /* Bit 16-15: Reserved */
+#define R_OFS0_RESERVED_16_15_MASK (3 << R_OFS0_RESERVED_16_15_SHIFT) /* Bit 16-15: Reserved */
+#define R_OFS0_WDTSTRT (1 << 17) /* Bit 17: WDT Start Mode Select */
+#define R_OFS0_IWDTSTPCTL (1 << 14) /* Bit 14: IWDT Stop Control */
+#define R_OFS0_RESERVED_13 (1 << 13) /* Bit 13: Reserved */
+#define R_OFS0_IWDTRSTIRQS (1 << 12) /* Bit 12: IWDT Reset Interrupt Request Select */
+#define R_OFS0_IWDTRPSS_SHIFT (10) /* Bit 11-10: IWDT Window Start Position Select */
+#define R_OFS0_IWDTRPSS_MASK (3 << R_OFS0_IWDTRPSS_SHIFT)
+# define R_OFS0_IWDTRPSS_25 (0 << R_OFS0_IWDTRPSS_SHIFT) /* IWDT Window Start Position Select 25% */
+# define R_OFS0_IWDTRPSS_50 (1 << R_OFS0_IWDTRPSS_SHIFT) /* IWDT Window Start Position Select 50% */
+# define R_OFS0_IWDTRPSS_75 (2 << R_OFS0_IWDTRPSS_SHIFT) /* IWDT Window Start Position Select 75% */
+# define R_OFS0_IWDTRPSS_100 (3 << R_OFS0_IWDTRPSS_SHIFT) /* IWDT Window Start Position Select 100% */
+#define R_OFS0_IWDTRPES_SHIFT (8) /* Bit 9-8: IWDT Window End Position Select*/
+#define R_OFS0_IWDTRPES_MASK (3 << R_OFS0_IWDTRPES_SHIFT)
+# define R_OFS0_IWDTRPES_75 (0 << R_OFS0_IWDTRPES_SHIFT) /* IWDT Window End Position Select 75% */
+# define R_OFS0_IWDTRPES_50 (1 << R_OFS0_IWDTRPES_SHIFT) /* IWDT Window End Position Select 50% */
+# define R_OFS0_IWDTRPES_25 (2 << R_OFS0_IWDTRPES_SHIFT) /* IWDT Window End Position Select 25% */
+# define R_OFS0_IWDTRPES_0 (3 << R_OFS0_IWDTRPES_SHIFT) /* IWDT Window End Position Select 0% */
+#define R_OFS0_IWDTCKS_SHIFT (4) /* Bit 7-4: IWDT Clock Frequency Division Ratio Select*/
+#define R_OFS0_IWDTCKS_MASK (0xF << R_OFS0_IWDTCKS_SHIFT)
+# define R_OFS0_IWDTCKS_DIV_1 (0 << R_OFS0_IWDTCKS_SHIFT) /* Divided by 1 */
+# define R_OFS0_IWDTCKS_DIV_16 (2 << R_OFS0_IWDTCKS_SHIFT) /* Divided by 16 */
+# define R_OFS0_IWDTCKS_DIV_32 (3 << R_OFS0_IWDTCKS_SHIFT) /* Divided by 32 */
+# define R_OFS0_IWDTCKS_DIV_64 (4 << R_OFS0_IWDTCKS_SHIFT) /* Divided by 64 */
+# define R_OFS0_IWDTCKS_DIV_128 (15 << R_OFS0_IWDTCKS_SHIFT) /* Divided by 128 */
+# define R_OFS0_IWDTCKS_DIV_256 (5 << R_OFS0_IWDTCKS_SHIFT) /* Divided by 256 */
+#define R_OFS0_IWDTTOPS_SHIFT (2) /* Bit 3-2: IWDT Timeout Period Select */
+#define R_OFS0_IWDTTOPS_MASK (3 << R_OFS0_IWDTTOPS_SHIFT)
+# define R_OFS0_IWDTTOPS_128_CYCLES (0 << R_OFS0_IWDTTOPS_SHIFT) /* 128 cycles */
+# define R_OFS0_IWDTTOPS_512_CYCLES (1 << R_OFS0_IWDTTOPS_SHIFT) /* 512 cycles */
+# define R_OFS0_IWDTTOPS_1024_CYCLES (2 << R_OFS0_IWDTTOPS_SHIFT) /* 1024 cycles */
+# define R_OFS0_IWDTTOPS_2048_CYCLES (3 << R_OFS0_IWDTTOPS_SHIFT) /* 2048 cycles */
+#define R_OFS0_IWDTSTRT (1 << 1) /* Bit 1: IWDT Start Mode Select */
+#define R_OFS0_RESERVED_0 (1 << 0) /* Bit 0: Reserved */
+
+/* Option Function Select Register 1 */
+
+#define R_OFS1_RESERVED_31_15_SHIFT (15) /* Bit 31-15: Reserved */
+#define R_OFS1_RESERVED_16_15_MASK (0x1FFFF << R_OFS1_RESERVED_31_15_SHIFT)
+#define R_OFS1_HOCOFRQ1_SHIFT (12) /* Bit 14-12: IWDT Timeout Period Select */
+#define R_OFS1_HOCOFRQ1_MASK (7 << R_OFS1_HOCOFRQ1_SHIFT)
+# define R_OFS1_HOCOFRQ1_24MHZ (0 << R_OFS1_HOCOFRQ1_SHIFT) /* HOCO 24 Mhz */
+# define R_OFS1_HOCOFRQ1_32MHZ (2 << R_OFS1_HOCOFRQ1_SHIFT) /* HOCO 32 Mhz */
+# define R_OFS1_HOCOFRQ1_48MHZ (4 << R_OFS1_HOCOFRQ1_SHIFT) /* HOCO 48 Mhz */
+# define R_OFS1_HOCOFRQ1_64MHZ (5 << R_OFS1_HOCOFRQ1_SHIFT) /* HOCO 64 Mhz */
+#define R_OFS1_RESERVED_11_9_SHIFT (9) /* Bit 11-9: Reserved */
+#define R_OFS1_RESERVED_11_9_MASK (7 << R_OFS1_RESERVED_11_9_SHIFT)
+#define R_OFS1_HOCOEN (1 << 8) /* Bit 8: HOCO Oscillation Enable */
+#define R_OFS1_RESERVED_7_6_SHIFT (6) /* Bit 7-6: Reserved */
+#define R_OFS1_RESERVED_7_6_MASK (3 << R_OFS1_RESERVED_7_6_SHIFT)
+#define R_OFS1_VDSEL1_SHIFT (3) /* Bit 5-3: Voltage Detection 0 Level Select */
+#define R_OFS1_VDSEL1_MASK (7 << R_OFS1_VDSEL1_SHIFT)
+# define R_OFS1_VDSEL1_3_84V (0 << R_OFS1_VDSEL1_SHIFT) /* Selects 3.84 V */
+# define R_OFS1_VDSEL1_2_82V (1 << R_OFS1_VDSEL1_SHIFT) /* Selects 2.82 V*/
+# define R_OFS1_VDSEL1_2_51V (2 << R_OFS1_VDSEL1_SHIFT) /* Selects 2.51 V */
+# define R_OFS1_VDSEL1_1_90V (3 << R_OFS1_VDSEL1_SHIFT) /* Selects 1.70 V */
+# define R_OFS1_VDSEL1_1_70V (4 << R_OFS1_VDSEL1_SHIFT) /* Selects 1.70 V */
+#define R_OFS1_LVDAS (1 << 2) /* Bit 8: Voltage Detection 0 Circuit Start*/
+#define R_OFS1_RESERVED_1_0_SHIFT (0) /* Bit 1-0: Reserved */
+#define R_OFS1_RESERVED_1_0_MASK (3 << R_OFS1_RESERVED_1_0_SHIFT)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_RA_HARDWARE_RA_OFS_H */
diff --git a/arch/arm/src/ra4/hardware/ra_pinmap.h b/arch/arm/src/ra4/hardware/ra_pinmap.h
new file mode 100644
index 0000000000000..643901b1a3046
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra_pinmap.h
@@ -0,0 +1,55 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra_pinmap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA_PINMAP_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA_PINMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+
+#if defined(CONFIG_RA4M1_FAMILY)
+# include "hardware/ra4m1_pinmap.h"
+#else
+# error "Unsupported RA memory map"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_RA_HARDWARE_RA_PINMAP_H */
diff --git a/arch/arm/src/ra4/hardware/ra_sci.h b/arch/arm/src/ra4/hardware/ra_sci.h
new file mode 100644
index 0000000000000..ca0aae53ac258
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra_sci.h
@@ -0,0 +1,382 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra_sci.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4_SCI_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4_SCI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include "chip.h"
+#include "hardware/ra4m1_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_SCI_SMR_OFFSET 0x0000 /* Status register (32-bits) */
+#define R_SCI_BRR_OFFSET 0x0001 /* Bit Rate Register (8-bits) */
+#define R_SCI_SCR_OFFSET 0x0002 /* Serial Control Register (8-bits) */
+#define R_SCI_TDR_OFFSET 0x0003 /* Transmit Data Register (8-bits) */
+#define R_SCI_SSR_OFFSET 0x0004 /* Serial Status Register (8-bits) */
+#define R_SCI_RDR_OFFSET 0x0005 /* Receive Data Register (8-bits) */
+#define R_SCI_SCMR_OFFSET 0x0006 /* Smart Card Mode Register (8-bits) */
+#define R_SCI_SEMR_OFFSET 0x0007 /* Serial Extended Mode Register (8-bits) */
+#define R_SCI_SNFR_OFFSET 0x0008 /* Noise Filter Setting Register (8-bits) */
+#define R_SCI_SIMR1_OFFSET 0x0009 /* I2C Mode Register 1 (8-bits) */
+#define R_SCI_SIMR2_OFFSET 0x000a /* I2C Mode Register 2 (8-bits) */
+#define R_SCI_SIMR3_OFFSET 0x000b /* I2C Mode Register 3 (8-bits) */
+#define R_SCI_SISR_OFFSET 0x000c /* I2C Status Register (8-bits) */
+#define R_SCI_SPMR_OFFSET 0x000d /* SPI Mode Register (8-bits) */
+#define R_SCI_TDRHL_OFFSET 0x000e /* Transmit 9-Bit Data Register (16-bits) */
+#define R_SCI_FTDRHL_OFFSET 0x000e /* Transmit FIFO Data Register HL (16-bits) */
+#define R_SCI_RDRHL_OFFSET 0x0010 /* Receive 9-bit Data Register (16-bits) */
+#define R_SCI_FRDRHL_OFFSET 0x0010 /* Receive FIFO Data Register HL (16-bits) */
+#define R_SCI_MDDR_OFFSET 0x0012 /* Modulation Duty Register (8-bits) */
+#define R_SCI_DCCR_OFFSET 0x0013 /* Data Compare Match Control Register (8-bits) */
+#define R_SCI_FCR_OFFSET 0x0014 /* FIFO Control Register (16-bits) */
+#define R_SCI_FDR_OFFSET 0x0016 /* FIFO Data Count Register (16-bits) */
+#define R_SCI_LSR_OFFSET 0x0018 /* Line Status Register (16-bits) */
+#define R_SCI_CDR_OFFSET 0x001a /* Compare Match Data Register (16-bits) */
+#define R_SCI_SPTR_OFFSET 0x001c /* Serial Port Register(8-bits) */
+
+/* Register Addresses *******************************************************/
+
+/* SCI0 Registers */
+
+# define R_SCI0_SMR (R_SCI0_BASE + R_SCI_SMR_OFFSET)
+# define R_SCI0_BRR (R_SCI0_BASE + R_SCI_BRR_OFFSET)
+# define R_SCI0_SCR (R_SCI0_BASE + R_SCI_SCR_OFFSET)
+# define R_SCI0_TDR (R_SCI0_BASE + R_SCI_TDR_OFFSET)
+# define R_SCI0_SSR (R_SCI0_BASE + R_SCI_SSR_OFFSET)
+# define R_SCI0_RDR (R_SCI0_BASE + R_SCI_RDR_OFFSET)
+# define R_SCI0_SCMR (R_SCI0_BASE + R_SCI_SCMR_OFFSET)
+# define R_SCI0_SEMR (R_SCI0_BASE + R_SCI_SEMR_OFFSET)
+# define R_SCI0_SNFR (R_SCI0_BASE + R_SCI_SNFR_OFFSET)
+# define R_SCI0_SIMR1 (R_SCI0_BASE + R_SCI_SIMR1_OFFSET)
+# define R_SCI0_SIMR2 (R_SCI0_BASE + R_SCI_SIMR2_OFFSET)
+# define R_SCI0_SIMR3 (R_SCI0_BASE + R_SCI_SIMR3_OFFSET)
+# define R_SCI0_SISR (R_SCI0_BASE + R_SCI_SISR_OFFSET)
+# define R_SCI0_SPMR (R_SCI0_BASE + R_SCI_SPMR_OFFSET)
+# define R_SCI0_TDRHL (R_SCI0_BASE + R_SCI_TDRHL_OFFSET)
+# define R_SCI0_FTDRHL (R_SCI0_BASE + R_SCI_FTDRHL_OFFSET)
+# define R_SCI0_RDRHL (R_SCI0_BASE + R_SCI_RDRHL_OFFSET)
+# define R_SCI0_FRDRHL (R_SCI0_BASE + R_SCI_FRDRHL_OFFSET)
+# define R_SCI0_MDDR (R_SCI0_BASE + R_SCI_MDDR_OFFSET)
+# define R_SCI0_DCCR (R_SCI0_BASE + R_SCI_DCCR_OFFSET)
+# define R_SCI0_FCR (R_SCI0_BASE + R_SCI_FCR_OFFSET)
+# define R_SCI0_FDR (R_SCI0_BASE + R_SCI_FDR_OFFSET)
+# define R_SCI0_LSR (R_SCI0_BASE + R_SCI_LSR_OFFSET)
+# define R_SCI0_CDR (R_SCI0_BASE + R_SCI_CDR_OFFSET)
+# define R_SCI0_SPTR (R_SCI0_BASE + R_SCI_SPTR_OFFSET)
+
+/* SCI1 Registers */
+
+# define R_SCI1_SMR (R_SCI1_BASE + R_SCI_SMR_OFFSET)
+# define R_SCI1_BRR (R_SCI1_BASE + R_SCI_BRR_OFFSET)
+# define R_SCI1_SCR (R_SCI1_BASE + R_SCI_SCR_OFFSET)
+# define R_SCI1_TDR (R_SCI1_BASE + R_SCI_TDR_OFFSET)
+# define R_SCI1_SSR (R_SCI1_BASE + R_SCI_SSR_OFFSET)
+# define R_SCI1_RDR (R_SCI1_BASE + R_SCI_RDR_OFFSET)
+# define R_SCI1_SCMR (R_SCI1_BASE + R_SCI_SCMR_OFFSET)
+# define R_SCI1_SEMR (R_SCI1_BASE + R_SCI_SEMR_OFFSET)
+# define R_SCI1_SNFR (R_SCI1_BASE + R_SCI_SNFR_OFFSET)
+# define R_SCI1_SIMR1 (R_SCI1_BASE + R_SCI_SIMR1_OFFSET)
+# define R_SCI1_SIMR2 (R_SCI1_BASE + R_SCI_SIMR2_OFFSET)
+# define R_SCI1_SIMR3 (R_SCI1_BASE + R_SCI_SIMR3_OFFSET)
+# define R_SCI1_SISR (R_SCI1_BASE + R_SCI_SISR_OFFSET)
+# define R_SCI1_SPMR (R_SCI1_BASE + R_SCI_SPMR_OFFSET)
+# define R_SCI1_TDRHL (R_SCI1_BASE + R_SCI_TDRHL_OFFSET)
+# define R_SCI1_FTDRHL (R_SCI1_BASE + R_SCI_FTDRHL_OFFSET)
+# define R_SCI1_RDRHL (R_SCI1_BASE + R_SCI_RDRHL_OFFSET)
+# define R_SCI1_FRDRHL (R_SCI1_BASE + R_SCI_FRDRHL_OFFSET)
+# define R_SCI1_MDDR (R_SCI1_BASE + R_SCI_MDDR_OFFSET)
+# define R_SCI1_DCCR (R_SCI1_BASE + R_SCI_DCCR_OFFSET)
+# define R_SCI1_FCR (R_SCI1_BASE + R_SCI_FCR_OFFSET)
+# define R_SCI1_FDR (R_SCI1_BASE + R_SCI_FDR_OFFSET)
+# define R_SCI1_LSR (R_SCI1_BASE + R_SCI_LSR_OFFSET)
+# define R_SCI1_CDR (R_SCI1_BASE + R_SCI_CDR_OFFSET)
+# define R_SCI1_SPTR (R_SCI1_BASE + R_SCI_SPTR_OFFSET)
+
+/* SCI2 Registers (No FIFO) */
+
+# define R_SCI2_SMR (R_SCI2_BASE + R_SCI_SMR_OFFSET)
+# define R_SCI2_BRR (R_SCI2_BASE + R_SCI_BRR_OFFSET)
+# define R_SCI2_SCR (R_SCI2_BASE + R_SCI_SCR_OFFSET)
+# define R_SCI2_TDR (R_SCI2_BASE + R_SCI_TDR_OFFSET)
+# define R_SCI2_SSR (R_SCI2_BASE + R_SCI_SSR_OFFSET)
+# define R_SCI2_RDR (R_SCI2_BASE + R_SCI_RDR_OFFSET)
+# define R_SCI2_SCMR (R_SCI2_BASE + R_SCI_SCMR_OFFSET)
+# define R_SCI2_SEMR (R_SCI2_BASE + R_SCI_SEMR_OFFSET)
+# define R_SCI2_SNFR (R_SCI2_BASE + R_SCI_SNFR_OFFSET)
+# define R_SCI2_SIMR1 (R_SCI2_BASE + R_SCI_SIMR1_OFFSET)
+# define R_SCI2_SIMR2 (R_SCI2_BASE + R_SCI_SIMR2_OFFSET)
+# define R_SCI2_SIMR3 (R_SCI2_BASE + R_SCI_SIMR3_OFFSET)
+# define R_SCI2_SISR (R_SCI2_BASE + R_SCI_SISR_OFFSET)
+# define R_SCI2_SPMR (R_SCI2_BASE + R_SCI_SPMR_OFFSET)
+# define R_SCI2_TDRHL (R_SCI2_BASE + R_SCI_TDRHL_OFFSET)
+# define R_SCI2_RDRHL (R_SCI2_BASE + R_SCI_RDRHL_OFFSET)
+# define R_SCI2_MDDR (R_SCI2_BASE + R_SCI_MDDR_OFFSET)
+# define R_SCI2_DCCR (R_SCI2_BASE + R_SCI_DCCR_OFFSET)
+# define R_SCI2_CDR (R_SCI2_BASE + R_SCI_CDR_OFFSET)
+# define R_SCI2_SPTR (R_SCI2_BASE + R_SCI_SPTR_OFFSET)
+
+/* SCI9 Registers (No FIFO) */
+
+# define R_SCI9_SMR (R_SCI9_BASE + R_SCI_SMR_OFFSET)
+# define R_SCI9_BRR (R_SCI9_BASE + R_SCI_BRR_OFFSET)
+# define R_SCI9_SCR (R_SCI9_BASE + R_SCI_SCR_OFFSET)
+# define R_SCI9_TDR (R_SCI9_BASE + R_SCI_TDR_OFFSET)
+# define R_SCI9_SSR (R_SCI9_BASE + R_SCI_SSR_OFFSET)
+# define R_SCI9_RDR (R_SCI9_BASE + R_SCI_RDR_OFFSET)
+# define R_SCI9_SCMR (R_SCI9_BASE + R_SCI_SCMR_OFFSET)
+# define R_SCI9_SEMR (R_SCI9_BASE + R_SCI_SEMR_OFFSET)
+# define R_SCI9_SNFR (R_SCI9_BASE + R_SCI_SNFR_OFFSET)
+# define R_SCI9_SIMR1 (R_SCI9_BASE + R_SCI_SIMR1_OFFSET)
+# define R_SCI9_SIMR2 (R_SCI9_BASE + R_SCI_SIMR2_OFFSET)
+# define R_SCI9_SIMR3 (R_SCI9_BASE + R_SCI_SIMR3_OFFSET)
+# define R_SCI9_SISR (R_SCI9_BASE + R_SCI_SISR_OFFSET)
+# define R_SCI9_SPMR (R_SCI9_BASE + R_SCI_SPMR_OFFSET)
+# define R_SCI9_TDRHL (R_SCI9_BASE + R_SCI_TDRHL_OFFSET)
+# define R_SCI9_RDRHL (R_SCI9_BASE + R_SCI_RDRHL_OFFSET)
+# define R_SCI9_MDDR (R_SCI9_BASE + R_SCI_MDDR_OFFSET)
+# define R_SCI9_DCCR (R_SCI9_BASE + R_SCI_DCCR_OFFSET)
+# define R_SCI9_CDR (R_SCI9_BASE + R_SCI_CDR_OFFSET)
+# define R_SCI9_SPTR (R_SCI9_BASE + R_SCI_SPTR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Status register */
+
+#define R_SCI_SMR_CM (1 << 7) /* Bit 7: Communication Mode */
+#define R_SCI_SMR_CHR (1 << 6) /* Bit 6: Character Length (Valid only in asynchronous mode) */
+#define R_SCI_SMR_PE (1 << 5) /* Bit 5: Parity Enable (Valid only in asynchronous mode) */
+#define R_SCI_SMR_PM (1 << 4) /* Bit 4: Parity Mode (Valid only when the PE bit is 1) */
+#define R_SCI_SMR_STOP (1 << 3) /* Bit 3: Stop Bit Length (Valid only in asynchronous mode) */
+#define R_SCI_SMR_MP (1 << 2) /* Bit 2: Multi-Processor Mode (Valid only in asynchronous mode) */
+#define R_SCI_SMR_CKS_SHIFT (0) /* Bits 1-0: Clock Select */
+#define R_SCI_SMR_CKS_MASK (3 << R_SCI_SMR_CKS_SHIFT)
+# define R_SCI_SMR_CKS_DIV_0 (0 << R_SCI_SMR_CKS_SHIFT) /* PCLKA clock (n = 0) */
+# define R_SCI_SMR_CKS_DIV_4 (1 << R_SCI_SMR_CKS_SHIFT) /* PCLKA/4 clock (n = 0) */
+# define R_SCI_SMR_CKS_DIV_16 (2 << R_SCI_SMR_CKS_SHIFT) /* PCLKA/16 clock (n = 0) */
+# define R_SCI_SMR_CKS_DIV_64 (3 << R_SCI_SMR_CKS_SHIFT) /* PCLKA/64 clock (n = 0) */
+
+/* Bit Rate Register */
+
+#define R_SCI_BRR_SHIFT (0) /* Bits 7-0: BRR is an 8-bit register that adjusts the bit rate. */
+#define R_SCI_BRR_MASK (0xff)
+
+/* Serial Control Register */
+
+#define R_SCI_SCR_TIE (1 << 7) /* Bit 7: Transmit Interrupt Enable */
+#define R_SCI_SCR_RIE (1 << 6) /* Bit 6: Receive Interrupt Enable */
+#define R_SCI_SCR_TE (1 << 5) /* Bit 5: Transmit Enable */
+#define R_SCI_SCR_RE (1 << 4) /* Bit 4: Receive Enable */
+#define R_SCI_SCR_MPIE (1 << 3) /* Bit 3: Multi-Processor Interrupt Enable (Valid in asynchronous mode when SMR.MP = 1) */
+#define R_SCI_SCR_TEIE (1 << 2) /* Bit 2: Transmit End Interrupt Enable */
+#define R_SCI_SCR_CKE_SHIFT (0) /* Bits 1-0: Clock Enable */
+#define R_SCI_SCR_CKE_MASK (3 << R_SCI_SCR_CKE_SHIFT)
+# define R_SCI_SCR_CKE_MOD0 (0 << R_SCI_SCR_CKE_SHIFT) /* Asynchronous mode: On-chip baud rate generator and the SCKn pin is available for use as an I/O port, Clock synchronous mode: Internal clock */
+# define R_SCI_SCR_CKE_MOD1 (1 << R_SCI_SCR_CKE_SHIFT) /* Asynchronous mode: On-chip baud rate generator and a same bit rate clock outputted on the SCKn pin, Clock synchronous mode: Internal clock */
+# define R_SCI_SCR_CKE_MOD2 (2 << R_SCI_SCR_CKE_SHIFT) /* External clock*/
+
+/* Transmit Data Register */
+
+#define R_SCI_TDR_SHIFT (0) /* Bits 7-0: TDR is an 8-bit register that stores transmit data. */
+#define R_SCI_TDR_MASK (0xff)
+
+/* Serial Status Register */
+
+#define R_SCI_SSR_TDRE (1 << 7) /* Bit 7: Transmit Data Empty Flag */
+#define R_SCI_SSR_RDRF (1 << 6) /* Bit 6: Receive Data Full Flag */
+#define R_SCI_SSR_ORER (1 << 5) /* Bit 5: Overrun Error Flag */
+#define R_SCI_SSR_FER (1 << 4) /* Bit 4: Framing Error Flag */
+#define R_SCI_SSR_PER (1 << 3) /* Bit 3: Parity Error Flag */
+#define R_SCI_SSR_TEND (1 << 2) /* Bit 2: Transmit End Flag */
+#define R_SCI_SSR_MPB (1 << 1) /* Bit 1: Multi-Processor */
+#define R_SCI_SSR_MPBT (1 << 0) /* Bit 0: Multi-Processor Bit Transfer */
+
+/* Receive Data Register */
+
+#define R_SCI_RDR_SHIFT (0) /* Bits 7-0: RDR is an 8-bit register that stores receive data. */
+#define R_SCI_RDR_MASK (0xff)
+
+/* Smart Card Mode Register */
+
+#define R_SCI_SCMR_BCP2 (1 << 7) /* Bit 7: Base Clock Pulse 2 Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits */
+#define R_SCI_SCMR_CHR1 (1 << 4) /* Bit 4: Character Length 1 (Only valid in asynchronous mode) */
+#define R_SCI_SCMR_SDIR (1 << 3) /* Bit 3: Transmitted/Received Data Transfer Direction NOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode. Set this bit to 1 if operation is to be in simple I2C mode. */
+#define R_SCI_SCMR_SINV (1 << 2) /* Bit 2: Transmitted/Received Data Invert Set this bit to 0 if operation is to be in simple I2C mode. */
+#define R_SCI_SCMR_SMIF (1 << 0) /* Bit 0: Smart Card Interface Mode Select */
+
+/* Serial Extended Mode Register */
+
+#define R_SCI_SEMR_RXDESEL (1 << 7) /* Bit 7: Asynchronous Start Bit Edge Detection Select (Valid only in asynchronous mode) */
+#define R_SCI_SEMR_BGDM (1 << 6) /* Bit 6: Baud Rate Generator Double-Speed Mode Select (Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). */
+#define R_SCI_SEMR_NFEN (1 << 5) /* Bit 5: Digital Noise Filter Function Enable (The NFEN bit should be 0 without simple I2C mode and asynchronous mode.) In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. */
+#define R_SCI_SEMR_ABCS (1 << 4) /* Bit 4: Asynchronous Mode Base Clock Select (Valid only in asynchronous mode) */
+#define R_SCI_SEMR_ABCSE (1 << 3) /* Bit 3: Asynchronous Mode Extended Base Clock Select 1 (Valid only in asynchronous mode and SCR.CKE[1]=0) */
+#define R_SCI_SEMR_BRME (1 << 2) /* Bit 2: Bit Rate Modulation Enable */
+
+/* Noise Filter Setting Register */
+
+#define R_SCI_SNFR_NFCS_SHIFT (0) /* Bits 3-0: Noise Filter Clock Select */
+#define R_SCI_SNFR_NFCS_MASK (7)
+# define R_SCI_SNFR_NFCS_DIV1_ASYNC (0 << R_SCI_SNFR_NFCS_SHIFT) /* Asynchronous mode: : The clock signal divided by 1 is used with the noise filter */
+# define R_SCI_SNFR_NFCS_DIV1_IIC (1 << R_SCI_SNFR_NFCS_SHIFT) /* simple IIC mode: The clock signal divided by 1 is used with the noise filter */
+# define R_SCI_SNFR_NFCS_DIV2_IIC (2 << R_SCI_SNFR_NFCS_SHIFT) /* simple IIC mode: The clock signal divided by 2 is used with the noise filter */
+# define R_SCI_SNFR_NFCS_DIV4_IIC (3 << R_SCI_SNFR_NFCS_SHIFT) /* simple IIC mode: The clock signal divided by 4 is used with the noise filter */
+# define R_SCI_SNFR_NFCS_DIV8_IIC (4 << R_SCI_SNFR_NFCS_SHIFT) /* simple IIC mode: The clock signal divided by 8 is used with the noise filter */
+
+/* I2C Mode Register 1 */
+
+#define R_SCI_SIMR1_IICDL_SHIFT (3) /* Bits 7-3: SDA Delay Output Select Cycles below are of the clock signal from the on-chip baud rate generator. */
+#define R_SCI_SIMR1_IICDL_MASK (0x1f)
+#define R_SCI_SIMR1_IICM (1 << 0) /* Bit 0: Simple I2C Mode Select */
+
+/* I2C Mode Register 2 */
+
+#define R_SCI_SIMR2_IICACKT (1 << 5) /* Bit 5: ACK Transmission Data */
+#define R_SCI_SIMR2_IICCSC (1 << 1) /* Bit 1: Clock Synchronization */
+#define R_SCI_SIMR2_IICINTM (1 << 0) /* Bit 0: I2C Interrupt Mode Select */
+
+/* I2C Mode Register 3 */
+#define R_SCI_SIMR3_IICSCLS_SHIFT (6) /* Bit 7-6: SCL Output Select */
+#define R_SCI_SIMR3_IICSCLS_MASK (3)
+# define R_SCI_SIMR3_IICSCLS_SCL_OUT_0 (0 << R_SCI_SIMR3_IICSCLS_SHIFT) /* SCL Output Select : Serial data output*/
+# define R_SCI_SIMR3_IICSCLS_SCL_OUT_1 (1 << R_SCI_SIMR3_IICSCLS_SHIFT) /* SCL Output Select : Generate a start, restart, or stop condition*/
+# define R_SCI_SIMR3_IICSCLS_SCL_OUT_2 (2 << R_SCI_SIMR3_IICSCLS_SHIFT) /* SCL Output Select : Output low level on the SCLn pin*/
+# define R_SCI_SIMR3_IICSCLS_SCL_OUT_3 (3 << R_SCI_SIMR3_IICSCLS_SHIFT) /* SCL Output Select : Drive SCLn pin to high-impedance state*/
+#define R_SCI_SIMR3_IICSDAS_SHIFT (4) /* Bit 5-4: SDA Output Select */
+#define R_SCI_SIMR3_IICSDAS_MASK (3)
+# define R_SCI_SIMR3_IICSDAS_SDA_OUT_0 (0 << R_SCI_SIMR3_IICSCLS_SHIFT) /* SDA Output Select : Serial data output*/
+# define R_SCI_SIMR3_IICSDAS_SDA_OUT_1 (1 << R_SCI_SIMR3_IICSCLS_SHIFT) /* SDA Output Select : Generate a start, restart, or stop condition*/
+# define R_SCI_SIMR3_IICSDAS_SDA_OUT_2 (2 << R_SCI_SIMR3_IICSCLS_SHIFT) /* SDA Output Select : Output low level on the SDAn pin*/
+# define R_SCI_SIMR3_IICSDAS_SDA_OUT_3 (3 << R_SCI_SIMR3_IICSCLS_SHIFT) /* SDA Output Select : Drive SDAn pin to high-impedance state*/
+#define R_SCI_SIMR3_IICSTIF (1 << 3) /* Bit 3: Issuing of Start, Restart, or Stop Condition Completed Flag (When 0 is written to IICSTIF, it is cleared to 0.) */
+#define R_SCI_SIMR3_IICSTPREQ (1 << 2) /* Bit 2: Stop Condition Generation */
+#define R_SCI_SIMR3_IICRSTAREQ (1 << 1) /* Bit 1: Restart Condition Generation */
+#define R_SCI_SIMR3_IICSTAREQ (1 << 0) /* Bit 0: Start Condition Generation */
+
+/* I2C Status Register */
+
+#define R_SCI_SISR_IICACKR (1 << 0) /* Bit 0: ACK Reception Data Flag */
+
+/* SPI Mode Register */
+
+#define R_SCI_SPMR_CKPH (1 << 7) /* Bit 7: Clock Phase Select */
+#define R_SCI_SPMR_CKPOL (1 << 6) /* Bit 6: Clock Polarity Select */
+#define R_SCI_SPMR_MFF (1 << 4) /* Bit 4: Mode Fault Flag */
+#define R_SCI_SPMR_MSS (1 << 2) /* Bit 2: Master Slave Select */
+#define R_SCI_SPMR_CTSE (1 << 1) /* Bit 1: CTS Enable */
+#define R_SCI_SPMR_SSE (1 << 0) /* Bit 0: SSn Pin Function Enable */
+
+/* Transmit 9-Bit Data Register */
+
+#define R_SCI_TDRHL_SHIFT (0) /* Bit 15-0: TDRHL is a 16-bit register that stores transmit data. */
+#define R_SCI_TDRHL_MASK (0xffff)
+
+/* Transmit FIFO Data Register HL */
+
+#define R_SCI_FTDRHL_MPBT (1 << 9) /* Bit 9: Multi-processor transfer bit flag (Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) */
+#define R_SCI_FTDRHL_TDAT_SHIFT (0) /* Bit 8-0: Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) */
+#define R_SCI_FTDRHL_TDAT_MASK (0x1ff)
+
+/* Receive 9-bit Data Register */
+
+#define R_SCI_RDRHL_SHIFT (0) /* Bit 15-0:: TDRHL is a 16-bit register that stores receive data. */
+#define R_SCI_RDRHL_MASK (0xffff)
+
+/* Transmit FIFO Data Register HL */
+
+#define R_SCI_FRDRHL_RDF (1 << 14) /* Bit 14: Receive FIFO data full flag (It is same as SSR.RDF) */
+#define R_SCI_FRDRHL_ORER (1 << 13) /* Bit 13: Overrun error flag (It is same as SSR.ORER) */
+#define R_SCI_FRDRHL_FER (1 << 12) /* Bit 12: Framing error flag */
+#define R_SCI_FRDRHL_PER (1 << 11) /* Bit 11: Parity error flag */
+#define R_SCI_FRDRHL_DR (1 << 10) /* Bit 10: Receive data ready flag (It is same as SSR.DR) */
+#define R_SCI_FRDRHL_MPB (1 << 9) /* Bit 9: Multi-processor bit flag (Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) */
+#define R_SCI_FRDRHL_RDAT_SHIFT (0) /* Bit 8-0: Serial receive data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) */
+#define R_SCI_FRDRHL_RDAT_MASK (0x1ff)
+
+/* Data Compare Match Control Register */
+
+#define R_SCI_DCCR_DCME (1 << 7) /* Bit 7: Data Compare Match Enable (Valid only in asynchronous mode(including multi-processor) */
+#define R_SCI_DCCR_IDSEL (1 << 6) /* Bit 6: ID frame select (Valid only in asynchronous mode(including multi-processor) */
+#define R_SCI_DCCR_DFER (1 << 4) /* Bit 4: Data Compare Match Framing Error Flag */
+#define R_SCI_DCCR_DPER (1 << 3) /* Bit 3: Data Compare Match Parity Error Flag */
+#define R_SCI_DCCR_DCMF (1 << 0) /* Bit 0: Data Compare Match Flag */
+
+/* FIFO Control Register */
+
+#define R_SCI_FCR_RSTRG_SHIFT (12) /* Bit 15-12: RTS Output Active Trigger Number Select (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) */
+#define R_SCI_FCR_RSTRG_MASK (0x0f)
+#define R_SCI_FCR_RTRG_SHIFT (8) /* Bit 11-8: Receive FIFO data trigger number (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) */
+#define R_SCI_FCR_RTRG_MASK (0x0f)
+#define R_SCI_FCR_TTRG_SHIFT (4) /* Bit 7-4: Transmit FIFO data trigger number (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) */
+#define R_SCI_FCR_TTRG_MASK (0x0f)
+#define R_SCI_FCR_DRES (1 << 3) /* Bit 3: Receive data ready error select bit (When detecting a reception data ready, the interrupt request is selected.) */
+#define R_SCI_FCR_TFRST (1 << 2) /* Bit 2: Transmit FIFO Data Register Reset (Valid only in FCR.FM=1) */
+#define R_SCI_FCR_RFRST (1 << 1) /* Bit 1: Receive FIFO Data Register Reset (Valid only in FCR.FM=1) */
+#define R_SCI_FCR_FM (1 << 0) /* Bit 0: FIFO Mode Select (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) */
+
+/* FIFO Data Count Register */
+
+#define R_SCI_FDR_T_SHIFT (8) /* Bit 12-8: Transmit FIFO Data Count Indicate the quantity of non-transmit data stored in FTDRH and FTDRL (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) */
+#define R_SCI_FDR_T_MASK (0x1f)
+#define R_SCI_FDR_R_SHIFT (0) /* Bit 4-0: Receive FIFO Data Count Indicate the quantity of receive data stored in FRDRH and FRDRL (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) */
+#define R_SCI_FDR_R_MASK (0x1f)
+
+/* Line Status Register */
+
+#define R_SCI_LSR_PNUM_SHIFT (8) /* Bit 12-8: Parity Error Count Indicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). */
+#define R_SCI_LSR_PNUM_MASK (0x1f)
+#define R_SCI_LSR_FNUM_SHIFT (2) /* Bit 6-2: Framing Error Count Indicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). */
+#define R_SCI_LSR_FNUM_MASK (0x1f)
+#define R_SCI_LSR_ORER (1 << 0) /* Bit 0: Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) */
+
+/* Compare Match Data Register */
+
+#define R_SCI_CDR_CMPD_SHIFT (0) /* Bit 8-0: Compare Match Data Compare data pattern for address match wake-up function */
+#define R_SCI_CDR_CMPD_MASK (0x1ff)
+
+/* Serial Port Register */
+
+#define R_SCI_SPTR_SPB2IO (1 << 2) /* 04: Serial port break I/O bit (It's selected whether the value of SPB2DT is output to TxD terminal.) */
+#define R_SCI_SPTR_SPB2DT (1 << 1) /* 02: Serial port break data select bit (The output level of TxD terminal is selected when.) */
+#define R_SCI_SPTR_RXDMON (1 << 0) /* 01: Serial input data monitor bit (The state of the RXD terminal is shown.) */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4_SCI_H */
diff --git a/arch/arm/src/ra4/hardware/ra_system.h b/arch/arm/src/ra4/hardware/ra_system.h
new file mode 100644
index 0000000000000..4fd0b63d99bd4
--- /dev/null
+++ b/arch/arm/src/ra4/hardware/ra_system.h
@@ -0,0 +1,581 @@
+/****************************************************************************
+ * arch/arm/src/ra4/hardware/ra_system.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_SYSTEM_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_SYSTEM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+#include "ra_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_SYSTEM_VBTCR1_OFFSET 0x041f /* VBATT Control Register 1 (8-bits) */
+#define R_SYSTEM_VBTCR2_OFFSET 0x04b0 /* VBATT Control Register 2 (8-bits) */
+#define R_SYSTEM_VBTSR_OFFSET 0x04b1 /* VBATT Status Register (8-bits) */
+#define R_SYSTEM_VBTCMPCR_OFFSET 0x04b2 /* VBATT Comparator Control Register (8-bits) */
+#define R_SYSTEM_VBTLVDICR_OFFSET 0x04b4 /* VBATT Pin Low Voltage Detect Interrupt Control Register (8-bits) */
+#define R_SYSTEM_VBTWCTLR_OFFSET 0x04b6 /* VBATT Wakeup Function Control Register (8-bits) */
+#define R_SYSTEM_VBTWCH0OTSR_OFFSET 0x04b8 /* VBATT Wakeup I/O 0 Output Trigger Select Register (8-bits) */
+#define R_SYSTEM_VBTWCH1OTSR_OFFSET 0x04b9 /* VBATT Wakeup I/O 1 Output Trigger Select Register (8-bits) */
+#define R_SYSTEM_VBTWCH2OTSR_OFFSET 0x04ba /* VBATT Wakeup I/O 2 Output Trigger Select Register (8-bits) */
+#define R_SYSTEM_VBTICTLR_OFFSET 0x04bb /* VBATT Input Control Register (8-bits) */
+#define R_SYSTEM_VBTOCTLR_OFFSET 0x04bc /* VBATT Output Control Register (8-bits) */
+#define R_SYSTEM_VBTWTER_OFFSET 0x04bd /* VBATT Wakeup Trigger Source Enable Register (8-bits) */
+#define R_SYSTEM_VBTWEGR_OFFSET 0x04be /* VBATT Wakeup Trigger Source Edge Register (8-bits) */
+#define R_SYSTEM_VBTWFR_OFFSET 0x04bf /* VBATT Wakeup Trigger Source Flag Register (8-bits) */
+#define R_SYSTEM_VBTBKR_OFFSET 0x0500 /* VBATT Backup Register (8-bits) */
+#define R_SYSTEM_SCKDIVCR_OFFSET 0x0020 /* System Clock Division Control Register (32-bits) */
+#define R_SYSTEM_SCKSCR_OFFSET 0x0026 /* System Clock Source Control Register (8-bits) */
+#define R_SYSTEM_PLLCR_OFFSET 0x002a /* PLL Control Register (8-bits) */
+#define R_SYSTEM_PLLCCR2_OFFSET 0x002b /* PLL Clock Control Register 2 (8-bits) */
+#define R_SYSTEM_MEMWAIT_OFFSET 0x0031 /* Memory Wait Cycle Control Register (8-bits) */
+#define R_SYSTEM_MOSCCR_OFFSET 0x0032 /* Main Clock Oscillator Control Register (8-bits) */
+#define R_SYSTEM_HOCOCR_OFFSET 0x0036 /* High-Speed On-Chip Oscillator Control Register (8-bits) */
+#define R_SYSTEM_MOCOCR_OFFSET 0x0038 /* Middle-Speed On-Chip Oscillator Control Register (8-bits) */
+#define R_SYSTEM_SOSCCR_OFFSET 0x0480 /* Sub-Clock Oscillator Control Register (8-bits) */
+#define R_SYSTEM_LOCOCR_OFFSET 0x0490 /* Low-Speed On-Chip Oscillator Control Register (8-bits) */
+#define R_SYSTEM_OSCSF_OFFSET 0x003c /* Oscillation Stabilization Flag Register (8-bits) */
+#define R_SYSTEM_CKOCR_OFFSET 0x003e /* Clock Out Control Register (8-bits) */
+#define R_SYSTEM_TRCKCR_OFFSET 0x003f /* Trace Clock Control Register (8-bits) */
+#define R_SYSTEM_OSTDCR_OFFSET 0x0040 /* Oscillation Stop Detection Control Register (8-bits) */
+#define R_SYSTEM_OSTDSR_OFFSET 0x0041 /* Oscillation Stop Detection Status Register (8-bits) */
+#define R_SYSTEM_SLCDSCKCR_OFFSET 0x0050 /* Segment LCD Source Clock Control Register (8-bits) */
+#define R_SYSTEM_MOCOUTCR_OFFSET 0x0061 /* MOCO User Trimming Control Register (8-bits) */
+#define R_SYSTEM_HOCOUTCR_OFFSET 0x0062 /* HOCO User Trimming Control Register (8-bits) */
+#define R_SYSTEM_MOSCWTCR_OFFSET 0x00a2 /* Main Clock Oscillator Wait Control Register (8-bits) */
+#define R_SYSTEM_HOCOWTCR_OFFSET 0x00a5 /* High-Speed On-Chip Oscillator Wait Control Register (8-bits) */
+#define R_SYSTEM_USBCKCR_OFFSET 0x00d0 /* USB Clock Control Register (8-bits) */
+#define R_SYSTEM_MOMCR_OFFSET 0x0413 /* Main Clock Oscillator Mode Oscillation Control Register (8-bits) */
+#define R_SYSTEM_SOMCR_OFFSET 0x0481 /* Sub-Clock Oscillator Mode Control Register (8-bits) */
+#define R_SYSTEM_LOCOUTCR_OFFSET 0x0492 /* LOCO User Trimming Control Register (8-bits) */
+#define R_SYSTEM_SBYCR_OFFSET 0x000c /* Standby Control Register (16-bits) */
+#define R_SYSTEM_MSTPCRA_OFFSET 0x001c /* Module Stop Control Register A (32-bits) */
+#define R_SYSTEM_SNZCR_OFFSET 0x0092 /* Snooze Control Register (8-bits) */
+#define R_SYSTEM_SNZEDCR_OFFSET 0x0094 /* Snooze End Control Register (8-bits) */
+#define R_SYSTEM_SNZREQCR_OFFSET 0x0098 /* Snooze Request Control Register (32-bits) */
+#define R_SYSTEM_FLSTOP_OFFSET 0x009e /* Flash Operation Control Register (8-bits) */
+#define R_SYSTEM_OPCCR_OFFSET 0x00a0 /* Operating Power Control Register (8-bits) */
+#define R_SYSTEM_SOPCCR_OFFSET 0x00aa /* Sub Operating Power Control Register (8-bits) */
+#define R_SYSTEM_SYOCDCR_OFFSET 0x040e /* System Control OCD Control Register (8-bits) */
+#define R_SYSTEM_LVCMPCR_OFFSET 0x0417 /* Voltage Monitor Circuit Control Register (8-bits) */
+#define R_SYSTEM_LVDLVLR_OFFSET 0x0418 /* Voltage Detection Level Select Register (8-bits) */
+#define R_SYSTEM_LVDCR0_OFFSET 0x041a /* Voltage Monitor Circuit Control Register 0 (8-bits) */
+#define R_SYSTEM_LVDCR1_OFFSET 0x00e0 /* Voltage Monitor Circuit Control Register 1 (8-bits) */
+#define R_SYSTEM_LVDSR_OFFSET 0x00e1 /* Voltage Monitor Circuit Status Register (8-bits) */
+#define R_SYSTEM_PRCR_OFFSET 0x03fe /* Protect Register (16-bits) */
+#define R_SYSTEM_RSTSR0_OFFSET 0x0410 /* Reset Status Register 0 (8-bits) */
+#define R_SYSTEM_RSTSR2_OFFSET 0x0411 /* Reset Status Register 2 (8-bits) */
+#define R_SYSTEM_RSTSR1_OFFSET 0x00c0 /* Reset Status Register 1 (16-bits) */
+#define R_SYSTEM_BKRACR_OFFSET 0x00c6 /* Backup Register Access Control Register (8-bits) */
+
+/* Register Addresses *******************************************************/
+
+# define R_SYSTEM_VBTCR1 (R_SYSTEM_BASE + R_SYSTEM_VBTCR1_OFFSET)
+# define R_SYSTEM_VBTCR2 (R_SYSTEM_BASE + R_SYSTEM_VBTCR2_OFFSET)
+# define R_SYSTEM_VBTSR (R_SYSTEM_BASE + R_SYSTEM_VBTSR_OFFSET)
+# define R_SYSTEM_VBTCMPCR (R_SYSTEM_BASE + R_SYSTEM_VBTCMPCR_OFFSET)
+# define R_SYSTEM_VBTLVDICR (R_SYSTEM_BASE + R_SYSTEM_VBTLVDICR_OFFSET)
+# define R_SYSTEM_VBTWCTLR (R_SYSTEM_BASE + R_SYSTEM_VBTWCTLR_OFFSET)
+# define R_SYSTEM_VBTWCH0OTSR (R_SYSTEM_BASE + R_SYSTEM_VBTWCH0OTSR_OFFSET)
+# define R_SYSTEM_VBTWCH1OTSR (R_SYSTEM_BASE + R_SYSTEM_VBTWCH1OTSR_OFFSET)
+# define R_SYSTEM_VBTWCH2OTSR (R_SYSTEM_BASE + R_SYSTEM_VBTWCH2OTSR_OFFSET)
+# define R_SYSTEM_VBTICTLR (R_SYSTEM_BASE + R_SYSTEM_VBTICTLR_OFFSET)
+# define R_SYSTEM_VBTOCTLR (R_SYSTEM_BASE + R_SYSTEM_VBTOCTLR_OFFSET)
+# define R_SYSTEM_VBTWTER (R_SYSTEM_BASE + R_SYSTEM_VBTWTER_OFFSET)
+# define R_SYSTEM_VBTWEGR (R_SYSTEM_BASE + R_SYSTEM_VBTWEGR_OFFSET)
+# define R_SYSTEM_VBTWFR (R_SYSTEM_BASE + R_SYSTEM_VBTWFR_OFFSET)
+# define R_SYSTEM_VBTBKR(p) (R_SYSTEM_BASE + R_SYSTEM_VBTBKR_OFFSET + p*0x0001)
+# define R_SYSTEM_SCKDIVCR (R_SYSTEM_BASE + R_SYSTEM_SCKDIVCR_OFFSET)
+# define R_SYSTEM_SCKSCR (R_SYSTEM_BASE + R_SYSTEM_SCKSCR_OFFSET)
+# define R_SYSTEM_PLLCR (R_SYSTEM_BASE + R_SYSTEM_PLLCR_OFFSET)
+# define R_SYSTEM_PLLCCR2 (R_SYSTEM_BASE + R_SYSTEM_PLLCCR2_OFFSET)
+# define R_SYSTEM_MEMWAIT (R_SYSTEM_BASE + R_SYSTEM_MEMWAIT_OFFSET)
+# define R_SYSTEM_MOSCCR (R_SYSTEM_BASE + R_SYSTEM_MOSCCR_OFFSET)
+# define R_SYSTEM_HOCOCR (R_SYSTEM_BASE + R_SYSTEM_HOCOCR_OFFSET)
+# define R_SYSTEM_MOCOCR (R_SYSTEM_BASE + R_SYSTEM_MOCOCR_OFFSET)
+# define R_SYSTEM_SOSCCR (R_SYSTEM_BASE + R_SYSTEM_SOSCCR_OFFSET)
+# define R_SYSTEM_LOCOCR (R_SYSTEM_BASE + R_SYSTEM_LOCOCR_OFFSET)
+# define R_SYSTEM_OSCSF (R_SYSTEM_BASE + R_SYSTEM_OSCSF_OFFSET)
+# define R_SYSTEM_CKOCR (R_SYSTEM_BASE + R_SYSTEM_CKOCR_OFFSET)
+# define R_SYSTEM_TRCKCR (R_SYSTEM_BASE + R_SYSTEM_TRCKCR_OFFSET)
+# define R_SYSTEM_OSTDCR (R_SYSTEM_BASE + R_SYSTEM_OSTDCR_OFFSET)
+# define R_SYSTEM_OSTDSR (R_SYSTEM_BASE + R_SYSTEM_OSTDSR_OFFSET)
+# define R_SYSTEM_SLCDSCKCR (R_SYSTEM_BASE + R_SYSTEM_SLCDSCKCR_OFFSET)
+# define R_SYSTEM_MOCOUTCR (R_SYSTEM_BASE + R_SYSTEM_MOCOUTCR_OFFSET)
+# define R_SYSTEM_HOCOUTCR (R_SYSTEM_BASE + R_SYSTEM_HOCOUTCR_OFFSET)
+# define R_SYSTEM_MOSCWTCR (R_SYSTEM_BASE + R_SYSTEM_MOSCWTCR_OFFSET)
+# define R_SYSTEM_HOCOWTCR (R_SYSTEM_BASE + R_SYSTEM_HOCOWTCR_OFFSET)
+# define R_SYSTEM_USBCKCR (R_SYSTEM_BASE + R_SYSTEM_USBCKCR_OFFSET)
+# define R_SYSTEM_MOMCR (R_SYSTEM_BASE + R_SYSTEM_MOMCR_OFFSET)
+# define R_SYSTEM_SOMCR (R_SYSTEM_BASE + R_SYSTEM_SOMCR_OFFSET)
+# define R_SYSTEM_LOCOUTCR (R_SYSTEM_BASE + R_SYSTEM_LOCOUTCR_OFFSET)
+# define R_SYSTEM_SBYCR (R_SYSTEM_BASE + R_SYSTEM_SBYCR_OFFSET)
+# define R_SYSTEM_MSTPCRA (R_SYSTEM_BASE + R_SYSTEM_MSTPCRA_OFFSET)
+# define R_SYSTEM_SNZCR (R_SYSTEM_BASE + R_SYSTEM_SNZCR_OFFSET)
+# define R_SYSTEM_SNZEDCR (R_SYSTEM_BASE + R_SYSTEM_SNZEDCR_OFFSET)
+# define R_SYSTEM_SNZREQCR (R_SYSTEM_BASE + R_SYSTEM_SNZREQCR_OFFSET)
+# define R_SYSTEM_FLSTOP (R_SYSTEM_BASE + R_SYSTEM_FLSTOP_OFFSET)
+# define R_SYSTEM_OPCCR (R_SYSTEM_BASE + R_SYSTEM_OPCCR_OFFSET)
+# define R_SYSTEM_SOPCCR (R_SYSTEM_BASE + R_SYSTEM_SOPCCR_OFFSET)
+# define R_SYSTEM_SYOCDCR (R_SYSTEM_BASE + R_SYSTEM_SYOCDCR_OFFSET)
+# define R_SYSTEM_LVCMPCR (R_SYSTEM_BASE + R_SYSTEM_LVCMPCR_OFFSET)
+# define R_SYSTEM_LVDLVLR (R_SYSTEM_BASE + R_SYSTEM_LVDLVLR_OFFSET)
+# define R_SYSTEM_LVDCR0 (R_SYSTEM_BASE + R_SYSTEM_LVDCR0_OFFSET)
+# define R_SYSTEM_LVDCR1 (R_SYSTEM_BASE + R_SYSTEM_LVDCR1_OFFSET)
+# define R_SYSTEM_LVDSR (R_SYSTEM_BASE + R_SYSTEM_LVDSR_OFFSET)
+# define R_SYSTEM_PRCR (R_SYSTEM_BASE + R_SYSTEM_PRCR_OFFSET)
+# define R_SYSTEM_RSTSR0 (R_SYSTEM_BASE + R_SYSTEM_RSTSR0_OFFSET)
+# define R_SYSTEM_RSTSR2 (R_SYSTEM_BASE + R_SYSTEM_RSTSR2_OFFSET)
+# define R_SYSTEM_RSTSR1 (R_SYSTEM_BASE + R_SYSTEM_RSTSR1_OFFSET)
+# define R_SYSTEM_BKRACR (R_SYSTEM_BASE + R_SYSTEM_BKRACR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* VBATT Control Register 1 (8-bits) */
+
+#define R_SYSTEM_VBTCR1_BPWSWSTP (1 << 0) /* 01: Battery Power supply Switch Stop */
+
+/* VBATT Control Register 2 (8-bits) */
+
+#define R_SYSTEM_VBTCR2_VBTLVDLVL_SHIFT (6) /* 40: VBATT Pin Voltage Low Voltage Detect Level Select Bit */
+#define R_SYSTEM_VBTCR2_VBTLVDLVL_MASK (3)
+#define R_SYSTEM_VBTCR2_VBTLVDEN (1 << 4) /* 10: VBATT Pin Low Voltage Detect Enable Bit */
+
+/* VBATT Status Register (8-bits) */
+
+#define R_SYSTEM_VBTSR_VBTRVLD (1 << 4) /* 10: VBATT_R Valid */
+#define R_SYSTEM_VBTSR_VBTBLDF (1 << 1) /* 02: VBATT Battery Low voltage Detect Flag */
+#define R_SYSTEM_VBTSR_VBTRDF (1 << 0) /* 01: VBAT_R Reset Detect Flag */
+
+/* VBATT Comparator Control Register (8-bits) */
+
+#define R_SYSTEM_VBTLVDICR_VBTLVDISEL (1 << 1) /* 02: Pin Low Voltage Detect Interrupt Select bit */
+#define R_SYSTEM_VBTLVDICR_VBTLVDIE (1 << 0) /* 01: VBATT Pin Low Voltage Detect Interrupt Enable bit */
+
+/* VBATT Pin Low Voltage Detect Interrupt Control Register (8-bits) */
+
+#define R_SYSTEM_VBTCMPCR_VBTCMPE (1 << 0) /* 01: VBATT pin low voltage detect circuit output enable */
+
+/* VBATT Wakeup Function Control Register (8-bits) */
+
+#define R_SYSTEM_VBTWCTLR_VWEN (1 << 0) /* 01: VBATT wakeup enable */
+
+/* VBATT Wakeup I/O 0 Output Trigger Select Register (8-bits) */
+
+#define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE (1 << 4) /* 10: VBATWIO0 Output RTC Alarm Signal Enable */
+#define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE (1 << 3) /* 08: VBATWIO0 Output RTC Periodic Signal Enable */
+#define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE (1 << 2) /* 04: VBATWIO0 Output VBATWIO2 Trigger Enable */
+#define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE (1 << 1) /* 02: VBATWIO0 Output VBATWIO1 Trigger Enable */
+
+/* VBATT Wakeup I/O 1 Output Trigger Select Register (8-bits) */
+
+#define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE (1 << 4) /* 10: VBATWIO1 Output RTC Alarm Signal Enable */
+#define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE (1 << 3) /* 08: VBATWIO1 Output RTC Periodic Signal Enable */
+#define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE (1 << 2) /* 04: VBATWIO1 Output VBATWIO2 Trigger Enable */
+#define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE (1 << 0) /* 01: VBATWIO1 Output VBATWIO0 Trigger Enable */
+
+/* VBATT Wakeup I/O 2 Output Trigger Select Register (8-bits) */
+
+#define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE (1 << 4) /* 10: VBATWIO2 Output RTC Alarm Signal Enable */
+#define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE (1 << 3) /* 08: VBATWIO2 Output RTC Periodic Signal Enable */
+#define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE (1 << 1) /* 02: VBATWIO2 Output VBATWIO1 Trigger Enable */
+#define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE (1 << 0) /* 01: VBATWIO2 Output VBATWIO0 Trigger Enable */
+
+/* VBATT Input Control Register (8-bits) */
+
+#define R_SYSTEM_VBTICTLR_VCH2INEN (1 << 2) /* 04: VBATT Wakeup I/O 2 Input Enable */
+#define R_SYSTEM_VBTICTLR_VCH1INEN (1 << 1) /* 02: VBATT Wakeup I/O 1 Input Enable */
+#define R_SYSTEM_VBTICTLR_VCH0INEN (1 << 0) /* 01: VBATT Wakeup I/O 0 Input Enable */
+
+/* VBATT Output Control Register (8-bits) */
+
+#define R_SYSTEM_VBTOCTLR_VOUT2LSEL (1 << 5) /* 20: VBATT Wakeup I/O 2 Output Level Selection */
+#define R_SYSTEM_VBTOCTLR_VOUT1LSEL (1 << 4) /* 10: VBATT Wakeup I/O 1 Output Level Selection */
+#define R_SYSTEM_VBTOCTLR_VOUT0LSEL (1 << 3) /* 08: VBATT Wakeup I/O 0 Output Level Selection */
+#define R_SYSTEM_VBTOCTLR_VCH2OEN (1 << 2) /* 04: VBATT Wakeup I/O 2 Output Enable */
+#define R_SYSTEM_VBTOCTLR_VCH1OEN (1 << 1) /* 02: VBATT Wakeup I/O 1 Output Enable */
+#define R_SYSTEM_VBTOCTLR_VCH0OEN (1 << 0) /* 01: VBATT Wakeup I/O 0 Output Enable */
+
+/* VBATT Wakeup Trigger Source Enable Register (8-bits) */
+
+#define R_SYSTEM_VBTWTER_VRTCAE (1 << 4) /* 10: RTC Alarm Signal Enable */
+#define R_SYSTEM_VBTWTER_VRTCIE (1 << 3) /* 08: RTC Periodic Signal Enable */
+#define R_SYSTEM_VBTWTER_VCH2E (1 << 2) /* 04: VBATWIO2 Pin Enable */
+#define R_SYSTEM_VBTWTER_VCH1E (1 << 1) /* 02: VBATWIO1 Pin Enable */
+#define R_SYSTEM_VBTWTER_VCH0E (1 << 0) /* 01: VBATWIO0 Pin Enable */
+
+/* VBATT Wakeup Trigger Source Edge Register (8-bits) */
+
+#define R_SYSTEM_VBTWEGR_VCH2EG (1 << 2) /* 04: VBATWIO2 Wakeup Trigger Source Edge Select */
+#define R_SYSTEM_VBTWEGR_VCH1EG (1 << 1) /* 02: VBATWIO1 Wakeup Trigger Source Edge Select */
+#define R_SYSTEM_VBTWEGR_VCH0EG (1 << 0) /* 01: VBATWIO0 Wakeup Trigger Source Edge Select */
+
+/* VBATT Wakeup Trigger Source Flag Register (8-bits) */
+
+#define R_SYSTEM_VBTWFR_VRTCAF (1 << 4) /* 10: VBATT RTC-Alarm Wakeup Trigger Flag */
+#define R_SYSTEM_VBTWFR_VRTCIF (1 << 3) /* 08: VBATT RTC-Interval Wakeup Trigger Flag */
+#define R_SYSTEM_VBTWFR_VCH2F (1 << 2) /* 04: VBATWIO2 Wakeup Trigger Flag */
+#define R_SYSTEM_VBTWFR_VCH1F (1 << 1) /* 02: VBATWIO1 Wakeup Trigger Flag */
+#define R_SYSTEM_VBTWFR_VCH0F (1 << 0) /* 01: VBATWIO0 Wakeup Trigger Flag */
+
+/* VBATT Backup Register (8-bits) */
+
+#define R_SYSTEM_VBTBKR_SIZE 512
+#define R_SYSTEM_VBTBKR_VBTBKR (8 << 0) /* 01: VBTBKR is a 512-byte readable/writable register to store data powered by VBATT. The value of this register is retained even when VCC is not powered but VBATT is powered. VBTBKR is initialized by VBATT selected voltage power-on-reset. */
+#define R_SYSTEM_VBTBKR_VBTBKR_MASK (0xff)
+
+/* System Clock Division Control Register (32-bits) */
+
+#define R_SYSTEM_SCKDIVCR_FCK_SHIFT (28) /* Bits 30-28: Flash IF Clock (FCLK) Select */
+#define R_SYSTEM_SCKDIVCR_FCK_MASK (0x07 << R_SYSTEM_SCKDIVCR_FCK_SHIFT)
+# define R_SYSTEM_SCKDIVCR_FCK_DIV_1 (0 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* CLK/1 */
+# define R_SYSTEM_SCKDIVCR_FCK_DIV_2 (1 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* CLK/2 */
+# define R_SYSTEM_SCKDIVCR_FCK_DIV_4 (2 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* CLK/4 */
+# define R_SYSTEM_SCKDIVCR_FCK_DIV_8 (3 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* CLK/8 */
+# define R_SYSTEM_SCKDIVCR_FCK_DIV_16 (4 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* CLK/16 */
+# define R_SYSTEM_SCKDIVCR_FCK_DIV_32 (5 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* CLK/32 */
+# define R_SYSTEM_SCKDIVCR_FCK_DIV_64 (6 << R_SYSTEM_SCKDIVCR_FCK_SHIFT) /* CLK/64 */
+#define R_SYSTEM_SCKDIVCR_ICK_SHIFT (24) /* Bits 26-24: System Clock (ICLK) Select */
+#define R_SYSTEM_SCKDIVCR_ICK_MASK (0x07 << R_SYSTEM_SCKDIVCR_ICK_SHIFT)
+# define R_SYSTEM_SCKDIVCR_ICK_DIV_1 (0 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* CLK/1 */
+# define R_SYSTEM_SCKDIVCR_ICK_DIV_2 (1 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* CLK/2 */
+# define R_SYSTEM_SCKDIVCR_ICK_DIV_4 (2 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* CLK/4 */
+# define R_SYSTEM_SCKDIVCR_ICK_DIV_8 (3 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* CLK/8 */
+# define R_SYSTEM_SCKDIVCR_ICK_DIV_16 (4 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* CLK/16 */
+# define R_SYSTEM_SCKDIVCR_ICK_DIV_32 (5 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* CLK/32 */
+# define R_SYSTEM_SCKDIVCR_ICK_DIV_64 (6 << R_SYSTEM_SCKDIVCR_ICK_SHIFT) /* CLK/64 */
+#define R_SYSTEM_SCKDIVCR_PCKA_SHIFT (12) /* Bits 14-10: Peripheral Module Clock A (PCLKA) Select */
+#define R_SYSTEM_SCKDIVCR_PCKA_MASK (0x07 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT)
+# define R_SYSTEM_SCKDIVCR_PCKA_DIV_1 (0 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* CLK/1 */
+# define R_SYSTEM_SCKDIVCR_PCKA_DIV_2 (1 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* CLK/2 */
+# define R_SYSTEM_SCKDIVCR_PCKA_DIV_4 (2 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* CLK/4 */
+# define R_SYSTEM_SCKDIVCR_PCKA_DIV_8 (3 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* CLK/8 */
+# define R_SYSTEM_SCKDIVCR_PCKA_DIV_16 (4 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* CLK/16 */
+# define R_SYSTEM_SCKDIVCR_PCKA_DIV_32 (5 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* CLK/32 */
+# define R_SYSTEM_SCKDIVCR_PCKA_DIV_64 (6 << R_SYSTEM_SCKDIVCR_PCKA_SHIFT) /* CLK/64 */
+#define R_SYSTEM_SCKDIVCR_PCKB_SHIFT (8) /* Bits 10-8: Peripheral Module Clock B (PCLKB) Select */
+#define R_SYSTEM_SCKDIVCR_PCKB_MASK (0x07 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT)
+# define R_SYSTEM_SCKDIVCR_PCKB_DIV_1 (0 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* CLK/1 */
+# define R_SYSTEM_SCKDIVCR_PCKB_DIV_2 (1 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* CLK/2 */
+# define R_SYSTEM_SCKDIVCR_PCKB_DIV_4 (2 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* CLK/4 */
+# define R_SYSTEM_SCKDIVCR_PCKB_DIV_8 (3 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* CLK/8 */
+# define R_SYSTEM_SCKDIVCR_PCKB_DIV_16 (4 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* CLK/16 */
+# define R_SYSTEM_SCKDIVCR_PCKB_DIV_32 (5 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* CLK/32 */
+# define R_SYSTEM_SCKDIVCR_PCKB_DIV_64 (6 << R_SYSTEM_SCKDIVCR_PCKB_SHIFT) /* CLK/64 */
+#define R_SYSTEM_SCKDIVCR_PCKC_SHIFT (4) /* Bits 6-4: Peripheral Module Clock C (PCLKC) Select */
+#define R_SYSTEM_SCKDIVCR_PCKC_MASK (0x07 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT)
+# define R_SYSTEM_SCKDIVCR_PCKC_DIV_1 (0 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* CLK/1 */
+# define R_SYSTEM_SCKDIVCR_PCKC_DIV_2 (1 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* CLK/2 */
+# define R_SYSTEM_SCKDIVCR_PCKC_DIV_4 (2 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* CLK/4 */
+# define R_SYSTEM_SCKDIVCR_PCKC_DIV_8 (3 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* CLK/8 */
+# define R_SYSTEM_SCKDIVCR_PCKC_DIV_16 (4 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* CLK/16 */
+# define R_SYSTEM_SCKDIVCR_PCKC_DIV_32 (5 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* CLK/32 */
+# define R_SYSTEM_SCKDIVCR_PCKC_DIV_64 (6 << R_SYSTEM_SCKDIVCR_PCKC_SHIFT) /* CLK/64 */
+#define R_SYSTEM_SCKDIVCR_PCKD_SHIFT (0) /* Bits 2-0: Peripheral Module Clock D (PCLKD) Select */
+#define R_SYSTEM_SCKDIVCR_PCKD_MASK (0x07 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT)
+# define R_SYSTEM_SCKDIVCR_PCKD_DIV_1 (0 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* CLK/1 */
+# define R_SYSTEM_SCKDIVCR_PCKD_DIV_2 (1 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* CLK/2 */
+# define R_SYSTEM_SCKDIVCR_PCKD_DIV_4 (2 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* CLK/4 */
+# define R_SYSTEM_SCKDIVCR_PCKD_DIV_8 (3 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* CLK/8 */
+# define R_SYSTEM_SCKDIVCR_PCKD_DIV_16 (4 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* CLK/16 */
+# define R_SYSTEM_SCKDIVCR_PCKD_DIV_32 (5 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* CLK/32 */
+# define R_SYSTEM_SCKDIVCR_PCKD_DIV_64 (6 << R_SYSTEM_SCKDIVCR_PCKD_SHIFT) /* CLK/64 */
+
+/* System Clock Source Control Register (8-bits) */
+
+#define R_SYSTEM_SCKSCR_CKSEL_SHIFT (0) /* 01: Clock Source Select Selecting the system clock source faster than 32MHz(system clock source > 32MHz ) is prohibit when SCKDIVCR.ICK[2:0] bits select the division-by-1 and MEMWAIT.MEMWAIT =0. */
+#define R_SYSTEM_SCKSCR_CKSEL_MASK (0x07 << R_SYSTEM_SCKSCR_CKSEL_SHIFT)
+# define R_SYSTEM_SCKSCR_CKSEL_HOCO (0 << R_SYSTEM_SCKSCR_CKSEL_SHIFT)
+# define R_SYSTEM_SCKSCR_CKSEL_MOCO (1 << R_SYSTEM_SCKSCR_CKSEL_SHIFT)
+# define R_SYSTEM_SCKSCR_CKSEL_LOCO (2 << R_SYSTEM_SCKSCR_CKSEL_SHIFT)
+# define R_SYSTEM_SCKSCR_CKSEL_MOSC (3 << R_SYSTEM_SCKSCR_CKSEL_SHIFT)
+# define R_SYSTEM_SCKSCR_CKSEL_SOSC (4 << R_SYSTEM_SCKSCR_CKSEL_SHIFT)
+# define R_SYSTEM_SCKSCR_CKSEL_PLL (5 << R_SYSTEM_SCKSCR_CKSEL_SHIFT)
+
+/* PLL Control Register (8-bits) */
+
+#define R_SYSTEM_PLLCR_PLLSTP (1 << 0) /* 01: PLL Stop Control */
+
+/* PLL Clock Control Register 2 (8-bits) */
+
+#define R_SYSTEM_PLLCCR2 (R_SYSTEM_BASE + R_SYSTEM_PLLCCR2_OFFSET)
+#define R_SYSTEM_PLLCCR2_PLODIV_SHIFT (6) /* 40: PLL Output Frequency Division Ratio Select */
+#define R_SYSTEM_PLLCCR2_PLODIV_MASK (0x03)
+#define R_SYSTEM_PLLCCR2_PLLMUL_SHIFT (0) /* 01: PLL Frequency Multiplication Factor Select */
+#define R_SYSTEM_PLLCCR2_PLLMUL_MASK (0x1f)
+
+/* Memory Wait Cycle Control Register (8-bits) */
+
+#define R_SYSTEM_MEMWAIT_MEMWAIT (1 << 0) /* 01: Memory Wait Cycle Select Note: Writing 0 to the MEMWAIT is prohibited when SCKDIVCR.ICK selects division by 1 and SCKSCR.CKSEL[2:0] bits select the system clock source that is faster than 32 MHz (ICLK > 32 MHz). */
+
+/* Main Clock Oscillator Control Register (8-bits) */
+
+#define R_SYSTEM_MOSCCR_MOSTP (1 << 0) /* 01: Main Clock Oscillator Stop Note: MOMCR register must be set before setting MOSTP to 0. */
+
+/* High-Speed On-Chip Oscillator Control Register (8-bits) */
+
+#define R_SYSTEM_HOCOCR_HCSTP (1 << 0) /* 01: HOCO Stop */
+
+/* Middle-Speed On-Chip Oscillator Control Register (8-bits) */
+
+#define R_SYSTEM_MOCOCR_MCSTP (1 << 0) /* 01: MOCO Stop */
+
+/* Sub-Clock Oscillator Control Register (8-bits) */
+
+#define R_SYSTEM_SOSCCR_SOSTP (1 << 0) /* 01: Sub-Clock Oscillator Stop */
+
+/* Low-Speed On-Chip Oscillator Control Register (8-bits) */
+
+#define R_SYSTEM_LOCOCR_LCSTP (1 << 0) /* 01: LOCO Stop */
+
+/* Oscillation Stabilization Flag Register (8-bits) */
+
+#define R_SYSTEM_OSCSF_PLLSF (1 << 5) /* 20: PLL Clock Oscillation Stabilization Flag */
+#define R_SYSTEM_OSCSF_MOSCSF (1 << 3) /* 08: Main Clock Oscillation Stabilization Flag */
+#define R_SYSTEM_OSCSF_HOCOSF (1 << 0) /* 01: HOCO Clock Oscillation Stabilization Flag NOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1. */
+
+/* Clock Out Control Register (8-bits) */
+
+#define R_SYSTEM_CKOCR_CKOEN (1 << 7) /* 80: Clock out enable */
+#define R_SYSTEM_CKOCR_CKODIV_SHIFT (4) /* 10: Clock out input frequency Division Select */
+#define R_SYSTEM_CKOCR_CKODIV_MASK (0x07)
+#define R_SYSTEM_CKOCR_CKOSEL_SHIFT (0) /* 01: Clock out source select */
+#define R_SYSTEM_CKOCR_CKOSEL_MASK (0x07)
+
+/* Trace Clock Control Register (8-bits) */
+
+#define R_SYSTEM_TRCKCR_TRCKEN (1 << 7) /* 80: Trace Clock operating enable */
+#define R_SYSTEM_TRCKCR_TRCK (4 << 0) /* 01: Trace Clock operating frequency select */
+#define R_SYSTEM_TRCKCR_TRCK_MASK (0x0f)
+
+/* Oscillation Stop Detection Control Register (8-bits) */
+
+#define R_SYSTEM_OSTDCR_OSTDE (1 << 7) /* 80: Oscillation Stop Detection Function Enable */
+#define R_SYSTEM_OSTDCR_OSTDIE (1 << 0) /* 01: Oscillation Stop Detection Interrupt Enable */
+
+/* Oscillation Stop Detection Status Register (8-bits) */
+
+#define R_SYSTEM_OSTDSR_OSTDF (1 << 0) /* 01: Oscillation Stop Detection Flag */
+
+/* Segment LCD Source Clock Control Register (8-bits) */
+
+#define R_SYSTEM_SLCDSCKCR_LCDSCKEN (1 << 7) /* 80: LCD Source Clock Out Enable */
+#define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_SHIFT (0) /* 01: LCD Source Clock (LCDSRCCLK) Select */
+#define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_MASK (0x07)
+
+/* MOCO User Trimming Control Register (8-bits) */
+
+#define R_SYSTEM_MOCOUTCR_MOCOUTRM_SHIFT (0) /* 01: MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127 These bits are added to original MOCO trimming bits */
+#define R_SYSTEM_MOCOUTCR_MOCOUTRM_MASK (0xff)
+
+/* HOCO User Trimming Control Register (8-bits) */
+
+#define R_SYSTEM_HOCOUTCR_HOCOUTRM_SHIFT (0) /* 01: HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127 These bits are added to original HOCO trimming bits */
+#define R_SYSTEM_HOCOUTCR_HOCOUTRM_MASK (0xff)
+
+/* Main Clock Oscillator Wait Control Register (8-bits) */
+
+#define R_SYSTEM_MOSCWTCR_MSTS_SHIFT (0) /* 01: Main clock oscillator wait time setting */
+#define R_SYSTEM_MOSCWTCR_MSTS_MASK (0x0f)
+
+/* High-Speed On-Chip Oscillator Wait Control Register (8-bits) */
+
+#define R_SYSTEM_HOCOWTCR_HSTS_SHIFT (0) /* 01: HOCO wait time setting */
+#define R_SYSTEM_HOCOWTCR_HSTS_MASK (0x07)
+
+/* USB Clock Control Register (8-bits) */
+
+#define R_SYSTEM_USBCKCR_USBCLKSEL (1 << 0) /* 01: USB Clock Source Select */
+
+/* Main Clock Oscillator Mode Oscillation Control Register (8-bits) */
+
+#define R_SYSTEM_MOMCR_MOSEL (1 << 6) /* 40: Main Clock Oscillator Switching */
+#define R_SYSTEM_MOMCR_MODRV1 (1 << 3) /* 08: Main Clock Oscillator Drive Capability 1 Switching */
+
+/* Sub-Clock Oscillator Mode Control Register (8-bits) */
+
+#define R_SYSTEM_SOMCR_SODRV_SHIFT (0) /* 01: Sub-Clock Oscillator Drive Capability Switching */
+#define R_SYSTEM_SOMCR_SODRV_MASK (0x03)
+
+/* LOCO User Trimming Control Register (8-bits) */
+
+#define R_SYSTEM_LOCOUTCR_LOCOUTRM_SHIFT (0) /* 01: LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127 These bits are added to original LOCO trimming bits */
+#define R_SYSTEM_LOCOUTCR_LOCOUTRM_MASK (0xff)
+
+/* Standby Control Register (16-bits) */
+
+#define R_SYSTEM_SBYCR_SSBY (1 << 15) /* 8000: Software Standby */
+
+/* Module Stop Control Register A (32-bits) */
+
+#define R_SYSTEM_MSTPCRA_MSTPA22 (1 << 22) /* 400000: DMA Controller/Data Transfer Controller Module Stop */
+#define R_SYSTEM_MSTPCRA_MSTPA6 (1 << 6) /* 40: ECCRAM Module Stop */
+#define R_SYSTEM_MSTPCRA_MSTPA0 (1 << 0) /* 01: RAM0 Module Stop */
+
+/* Snooze Control Register (8-bits) */
+
+#define R_SYSTEM_SNZCR_SNZE (1 << 7) /* 80: Snooze Mode Enable */
+#define R_SYSTEM_SNZCR_SNZDTCEN (1 << 1) /* 02: DTC Enable in Snooze Mode */
+#define R_SYSTEM_SNZCR_RXDREQEN (1 << 0) /* 01: RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode. */
+
+/* Snooze End Control Register (8-bits) */
+
+#define R_SYSTEM_SNZEDCR_SCI0UMTED (1 << 7) /* 80: SCI0 Address Mismatch Snooze End Enable */
+#define R_SYSTEM_SNZEDCR_AD0UMTED (1 << 4) /* 10: ADC140 Compare Mismatch Snooze End Enable */
+#define R_SYSTEM_SNZEDCR_AD0MATED (1 << 3) /* 08: ADC140 Compare Match Snooze End Enable */
+#define R_SYSTEM_SNZEDCR_DTCNZRED (1 << 2) /* 04: Not Last DTC Transmission Completion Snooze End Enable */
+#define R_SYSTEM_SNZEDCR_DTCZRED (1 << 1) /* 02: Last DTC Transmission Completion Snooze End Enable */
+#define R_SYSTEM_SNZEDCR_AGTUNFED (1 << 0) /* 01: AGT1 Underflow Snooze End Enable */
+
+/* Snooze Request Control Register (32-bits) */
+
+#define R_SYSTEM_SNZREQCR_SNZREQEN30 (1 << 30) /* 40000000: Snooze Request Enable 30 Enable AGT1 compare match B snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN29 (1 << 29) /* 20000000: Snooze Request Enable 29 Enable AGT1 compare match A snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN28 (1 << 28) /* 10000000: Snooze Request Enable 28 Enable AGT1 underflow snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN25 (1 << 25) /* 2000000: Snooze Request Enable 25 Enable RTC period snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN24 (1 << 24) /* 1000000: Snooze Request Enable 24 Enable RTC alarm snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN23 (1 << 23) /* 800000: Snooze Request Enable 23 Enable RTC alarm snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN17 (1 << 17) /* 20000: Snooze Request Enable 17 Enable KINT snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN15 (1 << 15) /* 8000: Snooze Request Enable 15 Enable IRQ15 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN14 (1 << 14) /* 4000: Snooze Request Enable 14 Enable IRQ14 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN12 (1 << 12) /* 1000: Snooze Request Enable 12 Enable IRQ12 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN11 (1 << 11) /* 800: Snooze Request Enable 11 Enable IRQ11 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN10 (1 << 10) /* 400: Snooze Request Enable 10 Enable IRQ10 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN9 (1 << 9) /* 200: Snooze Request Enable 9 Enable IRQ9 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN8 (1 << 8) /* 100: Snooze Request Enable 8 Enable IRQ8 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN7 (1 << 7) /* 80: Snooze Request Enable 7 Enable IRQ7 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN6 (1 << 6) /* 40: Snooze Request Enable 6 Enable IRQ6 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN5 (1 << 5) /* 20: Snooze Request Enable 5 Enable IRQ5 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN4 (1 << 4) /* 10: Snooze Request Enable 4 Enable IRQ4 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN3 (1 << 3) /* 08: Snooze Request Enable 3 Enable IRQ3 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN2 (1 << 2) /* 04: Snooze Request Enable 2 Enable IRQ2 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN1 (1 << 1) /* 02: Snooze Request Enable 1 Enable IRQ1 pin snooze request */
+#define R_SYSTEM_SNZREQCR_SNZREQEN0 (1 << 0) /* 01: Snooze Request Enable 0 Enable IRQ0 pin snooze request */
+
+/* Flash Operation Control Register (8-bits) */
+
+#define R_SYSTEM_FLSTOP_FLSTPF (1 << 4) /* 10: Flash Memory Operation Status Flag */
+#define R_SYSTEM_FLSTOP_FLSTOP (1 << 0) /* 01: Selecting ON/OFF of the Flash Memory Operation */
+
+/* Operating Power Control Register (8-bits) */
+
+#define R_SYSTEM_OPCCR_OPCMTSF (1 << 4) /* 10: Operating Power Control Mode Transition Status Flag */
+#define R_SYSTEM_OPCCR_OPCM_SHIFT (0) /* 01: Operating Power Control Mode Select */
+#define R_SYSTEM_OPCCR_OPCM_MASK (0x03)
+
+/* Sub Operating Power Control Register (8-bits) */
+
+#define R_SYSTEM_SOPCCR_SOPCMTSF (1 << 4) /* 10: Sub Operating Power Control Mode Transition Status Flag */
+#define R_SYSTEM_SOPCCR_SOPCM (1 << 0) /* 01: Sub Operating Power Control Mode Select */
+
+/* System Control OCD Control Register (8-bits) */
+
+#define R_SYSTEM_SYOCDCR_DBGEN (1 << 7) /* 80: Debugger Enable bit */
+
+/* Voltage Monitor Circuit Control Register (8-bits) */
+
+#define R_SYSTEM_LVCMPCR_LVD2E (1 << 6) /* 40: Voltage Detection 2 Enable */
+#define R_SYSTEM_LVCMPCR_LVD1E (1 << 5) /* 20: Voltage Detection 1 Enable */
+
+/* Voltage Detection Level Select Register (8-bits) */
+
+#define R_SYSTEM_LVDLVLR_LVD2LVL_SHIFT (5) /* 20: Voltage Detection 2 Level Select (Standard voltage during drop in voltage) */
+#define R_SYSTEM_LVDLVLR_LVD2LVL_MASK (0x07)
+#define R_SYSTEM_LVDLVLR_LVD1LVL_SHIFT (0) /* 01: Voltage Detection 1 Level Select (Standard voltage during drop in voltage) */
+#define R_SYSTEM_LVDLVLR_LVD1LVL_MASK (0x1f)
+#define R_SYSTEM_LVDCR0_SIZE (2)
+
+/* Voltage Monitor Circuit Control Register 0 (8-bits) */
+
+#define R_SYSTEM_LVDCR0_RN (1 << 7) /* 80: Voltage Monitor Reset Negate Select */
+#define R_SYSTEM_LVDCR0_RI (1 << 6) /* 40: Voltage Monitor Circuit Mode Select */
+#define R_SYSTEM_LVDCR0_CMPE (1 << 2) /* 04: Voltage Monitor Circuit Comparison Result Output Enable */
+#define R_SYSTEM_LVDCR0_RIE (1 << 0) /* 01: Voltage Monitor Interrupt/Reset Enable */
+#define R_SYSTEM_LVDCR1_SIZE (2)
+
+/* Voltage Monitor Circuit Control Register 1 (8-bits) */
+
+#define R_SYSTEM_LVDCR1_IRQSEL (1 << 2) /* 04: Voltage Monitor Interrupt Type Select */
+#define R_SYSTEM_LVDCR1_IDTSEL_SHIFT (0) /* 01: Voltage Monitor Interrupt Generation Condition Select */
+#define R_SYSTEM_LVDCR1_IDTSEL_MASK (0x03)
+#define R_SYSTEM_LVDSR_SIZE (2)
+
+/* Voltage Monitor Circuit Status Register (8-bits) */
+
+#define R_SYSTEM_LVDSR_MON (1 << 1) /* 02: Voltage Monitor 1 Signal Monitor Flag */
+#define R_SYSTEM_LVDSR_DET (1 << 0) /* 01: Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0. */
+
+/* Protect Register (16-bits) */
+
+#define R_SYSTEM_PRCR_PRKEY_SHIFT (8) /* 100: PRC Key Code */
+#define R_SYSTEM_PRCR_PRKEY_MASK (0xff)
+#define R_SYSTEM_PRCR_PRKEY_VALUE (0xA5)
+#define R_SYSTEM_PRCR_PRC3 (1 << 3) /* 08: Protect Bit 3 */
+#define R_SYSTEM_PRCR_PRC1 (1 << 1) /* 02: Protect Bit 1 */
+#define R_SYSTEM_PRCR_PRC0 (1 << 0) /* 01: Protect Bit 0 */
+
+/* Reset Status Register 0 (8-bits) */
+
+#define R_SYSTEM_RSTSR0_LVD2RF (1 << 3) /* 08: Voltage Monitor 2 Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. */
+#define R_SYSTEM_RSTSR0_LVD1RF (1 << 2) /* 04: Voltage Monitor 1 Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. */
+#define R_SYSTEM_RSTSR0_LVD0RF (1 << 1) /* 02: Voltage Monitor 0 Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. */
+#define R_SYSTEM_RSTSR0_PORF (1 << 0) /* 01: Power-On Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. */
+
+/* Reset Status Register 2 (8-bits) */
+
+#define R_SYSTEM_RSTSR2_CWSF (1 << 0) /* 01: Cold/Warm Start Determination Flag Note: Only 1 can be written to set the flag. */
+
+/* Reset Status Register 1 (16-bits) */
+
+#define R_SYSTEM_RSTSR1_SPERF (1 << 12) /* 1000: SP Error Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. */
+#define R_SYSTEM_RSTSR1_BUSMRF (1 << 11) /* 800: Bus Master MPU Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. */
+#define R_SYSTEM_RSTSR1_BUSSRF (1 << 10) /* 400: Bus Slave MPU Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. */
+#define R_SYSTEM_RSTSR1_REERF (1 << 9) /* 200: RAM ECC Error Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. */
+#define R_SYSTEM_RSTSR1_RPERF (1 << 8) /* 100: RAM Parity Error Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. */
+#define R_SYSTEM_RSTSR1_SWRF (1 << 2) /* 04: Software Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. */
+#define R_SYSTEM_RSTSR1_WDTRF (1 << 1) /* 02: Watchdog Timer Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. */
+#define R_SYSTEM_RSTSR1_IWDTRF (1 << 0) /* 01: Independent Watchdog Timer Reset Detect Flag Note: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. */
+
+/* Backup Register Access Control Register (8-bits) */
+
+#define R_SYSTEM_BKRACR_BKRACS_SHIFT (0) /* 01: Backup Register Access Control Register */
+#define R_SYSTEM_BKRACR_BKRACS_MASK (0x07)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_SYSTEM_H */
diff --git a/arch/arm/src/ra4/ra_allocateheap.c b/arch/arm/src/ra4/ra_allocateheap.c
new file mode 100644
index 0000000000000..cc2bc16b7a902
--- /dev/null
+++ b/arch/arm/src/ra4/ra_allocateheap.c
@@ -0,0 +1,98 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_allocateheap.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+
+#include "mpu.h"
+#include "arm_internal.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ * This function will be called to dynamically set aside the heap region.
+ *
+ * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
+ * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
+ * size of the unprotected, user-space heap.
+ *
+ * If a protected kernel-space heap is provided, the kernel heap must be
+ * allocated (and protected) by an analogous up_allocate_kheap().
+ *
+ * The following memory map is assumed for the flat build:
+ *
+ * .data region. Size determined at link time.
+ * .bss region Size determined at link time.
+ * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
+ * Heap. Extends to the end of SRAM.
+ *
+ * The following memory map is assumed for the kernel build:
+ *
+ * Kernel .data region. Size determined at link time.
+ * Kernel .bss region Size determined at link time.
+ * Kernel IDLE thread stack. Size determined by
+ * CONFIG_IDLETHREAD_STACKSIZE.
+ * Padding for alignment
+ * User .data region. Size determined at link time.
+ * User .bss region Size determined at link time.
+ * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
+ * User heap. Extends to the end of SRAM.
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(void **heap_start, size_t *heap_size)
+{
+ board_autoled_on(LED_HEAPALLOCATE);
+ *heap_start = (void *)g_idle_topstack;
+ *heap_size = CONFIG_RAM_END - g_idle_topstack;
+}
diff --git a/arch/arm/src/ra4/ra_clockconfig.c b/arch/arm/src/ra4/ra_clockconfig.c
new file mode 100644
index 0000000000000..61810d7768e9a
--- /dev/null
+++ b/arch/arm/src/ra4/ra_clockconfig.c
@@ -0,0 +1,176 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include
+
+#include
+#include
+
+#include
+#include
+
+#include "arm_internal.h"
+#include "ra_clockconfig.h"
+#include "hardware/ra_flash.h"
+#include "hardware/ra_system.h"
+#include "hardware/ra_option_setting.h"
+
+const uint32_t option_settings[] __attribute__((section(".rom_registers")))
+__attribute__((__used__)) =
+{
+ /* Option Function Select Register 0 */
+
+ (
+ R_OFS0_RESERVED_31 | R_OFS0_WDTSTPCTL | R_OFS0_RESERVED_29 |
+ R_OFS0_WDTRSTIRQS | R_OFS0_WDTRPSS_MASK | R_OFS0_WDTRPES_MASK |
+ R_OFS0_WDTCKS_MASK | R_OFS0_WDTTOPS_MASK | R_OFS0_WDTSTRT |
+ R_OFS0_RESERVED_16_15_MASK | R_OFS0_IWDTSTPCTL | R_OFS0_RESERVED_13 |
+ R_OFS0_IWDTRSTIRQS | R_OFS0_IWDTRPSS_MASK | R_OFS0_IWDTRPES_MASK |
+ R_OFS0_IWDTCKS_MASK | R_OFS0_IWDTTOPS_MASK | R_OFS0_IWDTSTRT |
+ R_OFS0_RESERVED_0
+ ),
+
+ /* Option Function Select Register 1 */
+
+ (
+ R_OFS1_RESERVED_16_15_MASK | RA_HOCO_FREQUENCY |
+ R_OFS1_RESERVED_11_9_MASK | RA_HOCOEN | R_OFS1_RESERVED_7_6_MASK |
+ R_OFS1_VDSEL1_MASK | R_OFS1_LVDAS | R_OFS1_RESERVED_1_0_MASK),
+
+ (uint32_t)0x00fffffc, /* Security MPU Program Counter Start Address
+ * Register (SECMPUPCS0) */
+ (uint32_t)0x00ffffff, /* Security MPU Program Counter End Address
+ * Register (SECMPUPCE0) */
+ (uint32_t)0x00fffffc, /* Security MPU Program Counter Start Address
+ * Register (SECMPUPCS1) */
+ (uint32_t)0x00ffffff, /* Security MPU Program Counter End Address
+ * Register (SECMPUPCE1) */
+ (uint32_t)0x00fffffc, /* Security MPU Region 0 Start Address
+ * Register (SECMPUS0) */
+ (uint32_t)0x00ffffff, /* Security MPU Region 0 END Address Register
+ * (SECMPUE0) */
+ (uint32_t)0x200ffffc, /* Security MPU Region 0 Start Address
+ * Register (SECMPUS1) */
+ (uint32_t)0x200fffff, /* Security MPU Region 0 END Address Register
+ * (SECMPUE1) */
+ (uint32_t)0x407ffffc, /* Security MPU Region 0 Start Address
+ * Register (SECMPUS2) */
+ (uint32_t)0x407fffff, /* Security MPU Region 0 END Address Register
+ * (SECMPUE2) */
+ (uint32_t)0x40dffffc, /* Security MPU Region 0 Start Address
+ * Register (SECMPUS3) */
+ (uint32_t)0x40dfffff, /* Security MPU Region 0 END Address Register
+ * (SECMPUE3) */
+ (uint32_t)0xffffffff, /* Security MPU Access Control Register
+ * (SECMPUAC) */
+};
+
+/** ID code definitions defined here. */
+
+static const uint32_t g_bsp_id_codes[] __attribute__((section(".id_code")))
+__attribute__((__used__)) =
+{
+ IDCODE1, IDCODE2, IDCODE3, IDCODE4
+};
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Key code for writing PRCR register. */
+
+#define BSP_PRV_PRCR_KEY (0xA500U)
+#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
+#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U)
+#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ra_clockconfig
+ *
+ * Description:
+ * Called to initialize the RA. This does whatever setup is needed to
+ * put the SoC in a usable state. This includes the initialization of
+ * clocking using the settings in board.h.
+ *
+ ****************************************************************************/
+
+void ra_clockconfig(void)
+{
+ /* Unlock VBTCR1 register. */
+
+ putreg16((BSP_PRV_PRCR_KEY | R_SYSTEM_PRCR_PRC0 | R_SYSTEM_PRCR_PRC1),
+ R_SYSTEM_PRCR);
+
+ /* The VBTCR1.BPWSWSTP must be set after reset on MCUs that have
+ * VBTCR1.BPWSWSTP.
+ * Reference section 11.2.1 "VBATT Control Register 1 (VBTCR1)" and Figure
+ * 11.2
+ * "Setting flow of the VBTCR1.BPWSWSTP bit" in the RA manual
+ * R01UM0007EU0110. This must be done before bsp_clock_init because LOCOCR,
+ * LOCOUTCR, SOSCCR, and SOMCR cannot be accessed until VBTSR.VBTRVLD is
+ * set.
+ * */
+
+ modifyreg8(R_SYSTEM_VBTCR1, 0, R_SYSTEM_VBTCR1_BPWSWSTP);
+ while ((getreg8(R_SYSTEM_VBTSR) & R_SYSTEM_VBTSR_VBTRVLD) == 0)
+ {
+ }
+
+ /* Disable FCache. */
+
+ modifyreg16(R_FCACHE_FCACHEE, R_FCACHE_FCACHEE_FCACHEEN, 0);
+
+ modifyreg8(R_SYSTEM_SCKSCR, R_SYSTEM_SCKSCR_CKSEL_MASK, RA_CKSEL);
+
+ /* lock VBTCR1 register. */
+
+ putreg16(0, R_SYSTEM_PRCR);
+
+#if (RA_ICLK_FREQUENCY > 32000000)
+ modifyreg8(R_SYSTEM_MEMWAIT, 0, R_SYSTEM_MEMWAIT_MEMWAIT);
+#endif
+
+ modifyreg32(R_SYSTEM_SCKDIVCR,
+ (R_SYSTEM_SCKDIVCR_FCK_MASK | R_SYSTEM_SCKDIVCR_ICK_MASK |
+ R_SYSTEM_SCKDIVCR_PCKA_MASK | R_SYSTEM_SCKDIVCR_PCKB_MASK |
+ R_SYSTEM_SCKDIVCR_PCKC_MASK | R_SYSTEM_SCKDIVCR_PCKD_MASK),
+ (RA_FCK_DIV | RA_ICK_DIV | RA_PCKA_DIV | RA_PCKB_DIV |
+ RA_PCKC_DIV |
+ RA_PCKD_DIV));
+}
diff --git a/arch/arm/src/ra4/ra_clockconfig.h b/arch/arm/src/ra4/ra_clockconfig.h
new file mode 100644
index 0000000000000..a255d95b04895
--- /dev/null
+++ b/arch/arm/src/ra4/ra_clockconfig.h
@@ -0,0 +1,79 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_clockconfig.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_CLOCKCONFIG_H
+#define __ARCH_ARM_SRC_RA_CLOCKCONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ra4m1_clockconfig
+ *
+ * Description:
+ * Called to initialize the RA. This does whatever setup is needed to
+ * put the SoC in a usable state. This includes the initialization of
+ * clocking using the settings in board.h.
+ *
+ ****************************************************************************/
+
+void ra_clockconfig(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_RA_CLOCKCONFIG_H */
diff --git a/arch/arm/src/ra4/ra_gpio.c b/arch/arm/src/ra4/ra_gpio.c
new file mode 100644
index 0000000000000..0df772ccfa205
--- /dev/null
+++ b/arch/arm/src/ra4/ra_gpio.c
@@ -0,0 +1,107 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "arm_internal.h"
+#include "chip.h"
+#include "ra_gpio.h"
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ra_configgpio
+ *
+ * Description:
+ * Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+void ra_configgpio(gpio_pinset_t cfgset)
+{
+ uint8_t regval;
+
+ regval = R_PMISC_PWPR_PFSWE;
+ putreg8(0, R_PMISC_PWPR);
+ putreg8(regval, R_PMISC_PWPR);
+
+ putreg32(cfgset.cfg, R_PFS(cfgset.port, cfgset.pin));
+
+ regval = R_PMISC_PWPR_B0WI;
+ putreg8(0, R_PMISC_PWPR);
+ putreg8(regval, R_PMISC_PWPR);
+}
+
+/****************************************************************************
+ * Name: ra_gpiowrite
+ *
+ * Description:
+ * Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void ra_gpiowrite(gpio_pinset_t pinset, bool value)
+{
+ if (value)
+ {
+ putreg16((1 << pinset.pin), R_PORT_POSR(pinset.port));
+ }
+ else
+ {
+ putreg16((1 << pinset.pin), R_PORT_PORR(pinset.port));
+ }
+}
+
+/****************************************************************************
+ * Name: ra_gpioread
+ *
+ * Description:
+ * Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+bool ra_gpioread(gpio_pinset_t pinset)
+{
+ return (getreg16(R_PORT_PIDR(pinset.port)) &
+ (uint16_t)(0x01 << pinset.pin));
+}
diff --git a/arch/arm/src/ra4/ra_gpio.h b/arch/arm/src/ra4/ra_gpio.h
new file mode 100644
index 0000000000000..c0f8a8c41f762
--- /dev/null
+++ b/arch/arm/src/ra4/ra_gpio.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_GPIO_H
+#define __ARCH_ARM_SRC_RA_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+
+#include "chip.h"
+#include "hardware/ra_gpio.h"
+#include "hardware/ra_pinmap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* Must be big enough to hold the 32-bit encoding */
+
+typedef struct gpio_pinset
+{
+ uint8_t port;
+ uint8_t pin;
+ uint32_t cfg;
+}gpio_pinset_t;
+
+/****************************************************************************
+ * Name: ra_configgpio
+ *
+ * Description:
+ * Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+void ra_configgpio(gpio_pinset_t cfgset);
+
+/****************************************************************************
+ * Name: ra_gpiowrite
+ *
+ * Description:
+ * Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void ra_gpiowrite(gpio_pinset_t pinset, bool value);
+
+/****************************************************************************
+ * Name: ra_gpioread
+ *
+ * Description:
+ * Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+bool ra_gpioread(gpio_pinset_t pinset);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_RA_GPIO_H */
diff --git a/arch/arm/src/ra4/ra_icu.c b/arch/arm/src/ra4/ra_icu.c
new file mode 100644
index 0000000000000..c2674f6f81d99
--- /dev/null
+++ b/arch/arm/src/ra4/ra_icu.c
@@ -0,0 +1,102 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_icu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#ifdef CONFIG_SERIAL_TERMIOS
+#include
+#endif
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "arm_internal.h"
+#include "chip.h"
+
+#include "hardware/ra_sci.h"
+#include "hardware/ra_mstp.h"
+#include "hardware/ra_system.h"
+#include "ra_icu.h"
+#include "ra_lowputc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void ra_attach_icu(void)
+{
+#ifdef CONFIG_RA_SCI0_UART
+ putreg32(EVENT_SCI0_RXI, R_ICU_IELSR(SCI0_RXI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI0_TXI, R_ICU_IELSR(SCI0_TXI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI0_TEI, R_ICU_IELSR(SCI0_TEI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI0_ERI, R_ICU_IELSR(SCI0_ERI - RA_IRQ_FIRST));
+#endif
+#ifdef CONFIG_RA_SCI1_UART
+ putreg32(EVENT_SCI1_RXI, R_ICU_IELSR(SCI1_RXI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI1_TXI, R_ICU_IELSR(SCI1_TXI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI1_TEI, R_ICU_IELSR(SCI1_TEI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI1_ERI, R_ICU_IELSR(SCI1_ERI - RA_IRQ_FIRST));
+#endif
+#ifdef CONFIG_RA_SCI2_UART
+ putreg32(EVENT_SCI2_RXI, R_ICU_IELSR(SCI2_RXI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI2_TXI, R_ICU_IELSR(SCI2_TXI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI2_TEI, R_ICU_IELSR(SCI2_TEI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI2_ERI, R_ICU_IELSR(SCI2_ERI - RA_IRQ_FIRST));
+#endif
+#ifdef CONFIG_RA_SCI9_UART
+ putreg32(EVENT_SCI9_RXI, R_ICU_IELSR(SCI9_RXI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI9_TXI, R_ICU_IELSR(SCI9_TXI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI9_TEI, R_ICU_IELSR(SCI9_TEI - RA_IRQ_FIRST));
+ putreg32(EVENT_SCI9_ERI, R_ICU_IELSR(SCI9_ERI - RA_IRQ_FIRST));
+#endif
+}
+
+void ra_clear_ir(int irq)
+{
+ uint32_t regaddr;
+ regaddr = irq - RA_IRQ_FIRST;
+ modifyreg32(R_ICU_IELSR(regaddr), R_ICU_IELSR_IR, 0);
+ getreg32(R_ICU_IELSR(regaddr));
+}
diff --git a/arch/arm/src/ra4/ra_icu.h b/arch/arm/src/ra4/ra_icu.h
new file mode 100644
index 0000000000000..51cd84e08b472
--- /dev/null
+++ b/arch/arm/src/ra4/ra_icu.h
@@ -0,0 +1,37 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_icu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_ICU_H
+#define __ARCH_ARM_SRC_RA_ICU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "hardware/ra_icu.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+void ra_attach_icu(void);
+void ra_clear_ir(int irq);
+
+#endif
diff --git a/arch/arm/src/ra4/ra_irq.c b/arch/arm/src/ra4/ra_irq.c
new file mode 100644
index 0000000000000..a8b0c7007baaa
--- /dev/null
+++ b/arch/arm/src/ra4/ra_irq.c
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "nvic.h"
+#include "arm_internal.h"
+#include "ra_icu.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Get a 32-bit version of the default priority */
+
+#define DEFPRIORITY32 \
+ (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
+ NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
+ NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
+ NVIC_SYSH_PRIORITY_DEFAULT)
+
+#define NVIC_ENA_OFFSET (0)
+#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ra_dumpnvic
+ *
+ * Description:
+ * Dump some interesting NVIC registers
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ra_prioritize_syscall
+ *
+ * Description:
+ * Set the priority of an exception. This function may be needed
+ * internally even if support for prioritized interrupts is not enabled.
+ *
+ ****************************************************************************/
+
+static inline void ra_prioritize_syscall(int priority)
+{
+ uint32_t regval;
+
+ /* SVCALL is system handler 11 */
+
+ regval = getreg32(NVIC_SYSH8_11_PRIORITY);
+ regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
+ regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
+ putreg32(regval, NVIC_SYSH8_11_PRIORITY);
+}
+
+#if defined(CONFIG_DEBUG_IRQ_INFO)
+static void ra_dumpnvic(const char *msg, int irq)
+{
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" INTCTRL: %08x VECTAB: %08x\n", getreg32(
+ NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+ irqinfo(" IRQ ENABLE: %08x %08x %08x\n", getreg32(
+ NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
+ getreg32(NVIC_IRQ64_95_ENABLE));
+ irqinfo(" SYSH_PRIO: %08x %08x %08x\n", getreg32(
+ NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+ getreg32(NVIC_SYSH12_15_PRIORITY));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", getreg32(
+ NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+ getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(
+ NVIC_IRQ20_23_PRIORITY), getreg32(
+ NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(
+ NVIC_IRQ36_39_PRIORITY), getreg32(
+ NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(
+ NVIC_IRQ52_55_PRIORITY), getreg32(
+ NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
+ irqinfo(" %08x\n", getreg32(NVIC_IRQ64_67_PRIORITY));
+
+ leave_critical_section(flags);
+}
+
+#else
+# define ra_dumpnvic(msg, irq)
+#endif
+
+/****************************************************************************
+ * Name: ra_irqinfo
+ *
+ * Description:
+ * Given an IRQ number, provide the register and bit setting to enable or
+ * disable the irq.
+ *
+ ****************************************************************************/
+
+static int ra_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
+ uintptr_t offset)
+{
+ int n;
+
+ DEBUGASSERT(irq >= RA_IRQ_NMI && irq < NR_IRQS);
+
+ /* Check for external interrupt */
+
+ if (irq >= RA_IRQ_FIRST)
+ {
+ n = irq - RA_IRQ_FIRST;
+ *regaddr = NVIC_IRQ_ENABLE(n) + offset;
+ *bit = (uint32_t)1 << (n & 0x1f);
+ }
+
+ /* Handle processor exceptions. Only a few can be disabled */
+
+ else
+ {
+ *regaddr = NVIC_SYSHCON;
+ if (irq == RA_IRQ_MEMFAULT)
+ {
+ *bit = NVIC_SYSHCON_MEMFAULTENA;
+ }
+ else if (irq == RA_IRQ_BUSFAULT)
+ {
+ *bit = NVIC_SYSHCON_BUSFAULTENA;
+ }
+ else if (irq == RA_IRQ_USAGEFAULT)
+ {
+ *bit = NVIC_SYSHCON_USGFAULTENA;
+ }
+ else if (irq == RA_IRQ_SYSTICK)
+ {
+ *regaddr = NVIC_SYSTICK_CTRL;
+ *bit = NVIC_SYSTICK_CTRL_ENABLE;
+ }
+ else
+ {
+ return ERROR; /* Invalid or unsupported exception */
+ }
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+ uint32_t regaddr;
+
+ int num_priority_registers;
+ int i;
+
+ /* Disable all interrupts */
+
+ for (i = 0; i < NR_IRQS - RA_IRQ_FIRST; i += 32)
+ {
+ putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
+ }
+
+ putreg32((uint32_t)_vectors, NVIC_VECTAB);
+
+ /* Set all interrupts (and exceptions) to the default priority */
+
+ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
+ putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
+ putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
+
+ /* The NVIC ICTR register (bits 0-4) holds the number of interrupt
+ * lines that the NVIC supports:
+ *
+ * 0 -> 32 interrupt lines, 8 priority registers
+ * 1 -> 64 " " " ", 16 priority registers
+ * 2 -> 96 " " " ", 32 priority registers
+ * ...
+ */
+
+ num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
+
+ /* Now set all of the interrupt lines to the default priority */
+
+ regaddr = NVIC_IRQ0_3_PRIORITY;
+ while (num_priority_registers--)
+ {
+ putreg32(DEFPRIORITY32, regaddr);
+ regaddr += 4;
+ }
+
+ /* Attach the SVCall and Hard Fault exception handlers. The SVCall
+ * exception is used for performing context switches; The Hard Fault
+ * must also be caught because a SVCall may show up as a Hard Fault
+ * under certain conditions.
+ */
+
+ irq_attach(RA_IRQ_SVCALL, arm_svcall, NULL);
+ irq_attach(RA_IRQ_HARDFAULT, arm_hardfault, NULL);
+
+ /* Attach the ICU events to the IRQ vector table */
+
+ ra_attach_icu();
+
+ ra_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
+
+ ra_dumpnvic("initial", RA_IRQ_FIRST + 32);
+
+ /* And finally, enable interrupts */
+
+ up_irq_enable();
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ * Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+ uintptr_t regaddr;
+ uint32_t regval;
+ uint32_t bit;
+
+ if (ra_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0)
+ {
+ /* Modify the appropriate bit in the register to disable the interrupt.
+ * For normal interrupts, we need to set the bit in the associated
+ * Interrupt Clear Enable register. For other exceptions, we need to
+ * clear the bit in the System Handler Control and State Register.
+ */
+
+ if (irq >= RA_IRQ_FIRST)
+ {
+ putreg32(bit, regaddr);
+ }
+ else
+ {
+ regval = getreg32(regaddr);
+ regval &= ~bit;
+ putreg32(regval, regaddr);
+ }
+ }
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ * Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+ uintptr_t regaddr;
+ uint32_t regval;
+ uint32_t bit;
+
+ if (ra_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0)
+ {
+ /* Modify the appropriate bit in the register to enable the interrupt.
+ * For normal interrupts, we need to set the bit in the associated
+ * Interrupt Set Enable register. For other exceptions, we need to
+ * set the bit in the System Handler Control and State Register.
+ */
+
+ if (irq >= RA_IRQ_FIRST)
+ {
+ putreg32(bit, regaddr);
+ }
+ else
+ {
+ regval = getreg32(regaddr);
+ regval |= bit;
+ putreg32(regval, regaddr);
+ }
+ }
+}
+
+/****************************************************************************
+ * Name: arm_ack_irq
+ *
+ * Description:
+ * Acknowledge the IRQ
+ *
+ ****************************************************************************/
+
+void arm_ack_irq(int irq)
+{
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ * Set the priority of an IRQ.
+ *
+ * Since this API is not supported on all architectures, it should be
+ * avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQPRIO
+int up_prioritize_irq(int irq, int priority)
+{
+ uint32_t regaddr;
+ uint32_t regval;
+ int shift;
+
+ DEBUGASSERT(
+ irq >= RA_IRQ_MEMFAULT && irq < NR_IRQS &&
+ (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
+
+ if (irq < RA_IRQ_FIRST)
+ {
+ /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
+ * registers (0-3 are invalid)
+ */
+
+ regaddr = NVIC_SYSH_PRIORITY(irq);
+ irq -= 4;
+ }
+ else
+ {
+ /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
+
+ irq -= RA_IRQ_FIRST;
+ regaddr = NVIC_IRQ_PRIORITY(irq);
+ }
+
+ regval = getreg32(regaddr);
+ shift = ((irq & 3) << 3);
+ regval &= ~(0xff << shift);
+ regval |= (priority << shift);
+ putreg32(regval, regaddr);
+
+ ra_dumpnvic("prioritize", irq);
+ return OK;
+}
+
+#endif
diff --git a/arch/arm/src/ra4/ra_lowputc.c b/arch/arm/src/ra4/ra_lowputc.c
new file mode 100644
index 0000000000000..044029dc96cad
--- /dev/null
+++ b/arch/arm/src/ra4/ra_lowputc.c
@@ -0,0 +1,243 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+
+#include
+#include
+#include
+
+#include "arm_internal.h"
+#include "ra_lowputc.h"
+#include "ra_gpio.h"
+#include "hardware/ra_sci.h"
+#include "hardware/ra_mstp.h"
+#include "hardware/ra_system.h"
+
+/* The board.h file may redefine pin configurations defined in ra_pinmap.h */
+
+#include
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Is there a serial console? It could be on SCI0-1 or USART0-3 */
+
+#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI0_UART)
+#undef CONFIG_SCI1_SERIAL_CONSOLE
+#undef CONFIG_SCI2_SERIAL_CONSOLE
+#undef CONFIG_SCI9_SERIAL_CONSOLE
+#define HAVE_CONSOLE 1
+#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI1_UART)
+#undef CONFIG_SCI0_SERIAL_CONSOLE
+#undef CONFIG_SCI2_SERIAL_CONSOLE
+#undef CONFIG_SCI9_SERIAL_CONSOLE
+#define HAVE_CONSOLE 1
+#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI2_UART)
+#undef CONFIG_SCI0_SERIAL_CONSOLE
+#undef CONFIG_SCI1_SERIAL_CONSOLE
+#undef CONFIG_SCI9_SERIAL_CONSOLE
+#define HAVE_CONSOLE 1
+#elif defined(CONFIG_SCI9_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI9_UART)
+#undef CONFIG_SCI0_SERIAL_CONSOLE
+#undef CONFIG_SCI1_SERIAL_CONSOLE
+#undef CONFIG_SCI2_SERIAL_CONSOLE
+#define HAVE_CONSOLE 1
+#else
+#ifndef CONFIG_NO_SERIAL_CONSOLE
+#warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting"
+#endif
+
+#undef CONFIG_SCI0_SERIAL_CONSOLE
+#undef CONFIG_SCI1_SERIAL_CONSOLE
+#undef CONFIG_SCI2_SERIAL_CONSOLE
+#undef CONFIG_SCI9_SERIAL_CONSOLE
+#undef HAVE_CONSOLE
+#endif
+
+#if defined(HAVE_CONSOLE)
+
+/* Select USART parameters for the selected console */
+
+# if defined(CONFIG_SCI0_SERIAL_CONSOLE)
+# define RA_CONSOLE_BASE R_SCI0_BASE
+# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_SCI0
+# define RA_CONSOLE_BAUD CONFIG_SCI0_BAUD
+# define RA_CONSOLE_BITS CONFIG_SCI0_BITS
+# define RA_CONSOLE_PARITY CONFIG_SCI0_PARITY
+# define RA_CONSOLE_2STOP CONFIG_SCI0_2STOP
+# elif defined(CONFIG_SCI1_SERIAL_CONSOLE)
+# define RA_CONSOLE_BASE R_SCI1_BASE
+# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_SCI1
+# define RA_CONSOLE_BAUD CONFIG_SCI1_BAUD
+# define RA_CONSOLE_BITS CONFIG_SCI1_BITS
+# define RA_CONSOLE_PARITY CONFIG_SCI1_PARITY
+# define RA_CONSOLE_2STOP CONFIG_SCI1_2STOP
+# elif defined(CONFIG_SCI2_SERIAL_CONSOLE)
+# define RA_CONSOLE_BASE R_SCI2_BASE
+# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_SCI2
+# define RA_CONSOLE_BAUD CONFIG_SCI1_BAUD
+# define RA_CONSOLE_BITS CONFIG_SCI2_BITS
+# define RA_CONSOLE_PARITY CONFIG_SCI2_PARITY
+# define RA_CONSOLE_2STOP CONFIG_SCI2_2STOP
+# elif defined(CONFIG_SCI9_SERIAL_CONSOLE)
+# define RA_CONSOLE_BASE R_SCI9_BASE
+# define RA_CONSOLE_MTSP R_MSTP_MSTPCRB_SCI9
+# define RA_CONSOLE_BAUD CONFIG_SCI9_BAUD
+# define RA_CONSOLE_BITS CONFIG_SCI9_BITS
+# define RA_CONSOLE_PARITY CONFIG_SCI9_PARITY
+# define RA_CONSOLE_2STOP CONFIG_SCI9_2STOP
+# else
+# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
+# endif
+# endif
+
+/* Configuration ************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+#ifdef HAVE_CONSOLE
+static spinlock_t g_ra_lowputc_lock = SP_UNLOCKED;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_lowputc
+ *
+ * Description:
+ * Output one byte on the serial console
+ *
+ ****************************************************************************/
+
+void arm_lowputc(char ch)
+{
+#ifdef HAVE_CONSOLE
+ irqstate_t flags;
+ for (; ; )
+ {
+ while ((getreg8(RA_CONSOLE_BASE + R_SCI_SSR_OFFSET)
+ & R_SCI_SSR_TEND) == 0)
+ {
+ }
+
+ /* Disable interrupts so that the test and the transmission are
+ * atomic.
+ */
+
+ flags = spin_lock_irqsave(&g_ra_lowputc_lock);
+ if ((getreg8(RA_CONSOLE_BASE + R_SCI_SSR_OFFSET)
+ & R_SCI_SSR_TEND) == R_SCI_SSR_TEND)
+ {
+ /* Send the character */
+
+ putreg8((uint32_t)ch, RA_CONSOLE_BASE + R_SCI_TDR_OFFSET);
+
+ spin_unlock_irqrestore(&g_ra_lowputc_lock, flags);
+ return;
+ }
+
+ spin_unlock_irqrestore(&g_ra_lowputc_lock, flags);
+ }
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ * Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+void up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+ arm_lowputc(ch);
+#endif
+}
+
+/****************************************************************************
+ * Name: ra_lowsetup
+ *
+ * Description:
+ * This performs basic initialization of the USART used for the serial
+ * console. Its purpose is to get the console output available as soon
+ * as possible.
+ *
+ ****************************************************************************/
+
+void ra_lowsetup(void)
+{
+ uint32_t regval;
+
+#if defined(CONFIG_RA_SCI0_UART)
+ ra_configgpio(GPIO_SCI0_RX);
+ ra_configgpio(GPIO_SCI0_TX);
+#elif defined(CONFIG_RA_SCI1_UART)
+ ra_configgpio(GPIO_SCI1_RX);
+ ra_configgpio(GPIO_SCI1_TX);
+#elif defined(CONFIG_RA_SCI2_UART)
+ ra_configgpio(GPIO_SCI2_RX);
+ ra_configgpio(GPIO_SCI2_TX);
+#elif defined(CONFIG_RA_SCI9_UART)
+ ra_configgpio(GPIO_SCI9_RX);
+ ra_configgpio(GPIO_SCI9_TX);
+#endif
+
+ putreg16((R_SYSTEM_PRCR_PRKEY_VALUE | R_SYSTEM_PRCR_PRC1), R_SYSTEM_PRCR);
+ modifyreg32(R_MSTP_MSTPCRB, RA_CONSOLE_MTSP, 0);
+ putreg16(R_SYSTEM_PRCR_PRKEY_VALUE, R_SYSTEM_PRCR);
+
+ regval = 0;
+ putreg8(regval, RA_CONSOLE_BASE + R_SCI_SCR_OFFSET);
+
+ regval = 8;
+ putreg8(regval, RA_CONSOLE_BASE + R_SCI_BRR_OFFSET);
+
+ regval = (R_SCI_SCR_TE | R_SCI_SCR_RE);
+ putreg8(regval, RA_CONSOLE_BASE + R_SCI_SCR_OFFSET);
+}
diff --git a/arch/arm/src/ra4/ra_lowputc.h b/arch/arm/src/ra4/ra_lowputc.h
new file mode 100644
index 0000000000000..25e0d743bc338
--- /dev/null
+++ b/arch/arm/src/ra4/ra_lowputc.h
@@ -0,0 +1,88 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_lowputc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M_LOWPUTC_H
+#define __ARCH_ARM_SRC_RA4M_LOWPUTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+
+#include
+#include
+#include
+
+#include "arm_internal.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ra_lowsetup
+ *
+ * Description:
+ * Called at the very beginning of _start.
+ * Performs low level initialization including setup of the console UART.
+ * This UART done early so that the serial console is available for
+ * debugging very early in the boot sequence.
+ *
+ ****************************************************************************/
+
+void ra_lowsetup(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_RA4M_LOWPUTC_H */
diff --git a/arch/arm/src/ra4/ra_serial.c b/arch/arm/src/ra4/ra_serial.c
new file mode 100644
index 0000000000000..3e746850b343c
--- /dev/null
+++ b/arch/arm/src/ra4/ra_serial.c
@@ -0,0 +1,984 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#ifdef CONFIG_SERIAL_TERMIOS
+#include
+#endif
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "arm_internal.h"
+#include "chip.h"
+
+#include "hardware/ra_sci.h"
+#include "hardware/ra_mstp.h"
+#include "hardware/ra_system.h"
+#include "hardware/ra_mstp.h"
+#include "ra_lowputc.h"
+#include "ra_icu.h"
+#include "ra_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Is there a serial console? */
+
+#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI0_UART)
+#undef CONFIG_SCI1_SERIAL_CONSOLE
+#undef CONFIG_SCI2_SERIAL_CONSOLE
+#undef CONFIG_SCI9_SERIAL_CONSOLE
+#define HAVE_CONSOLE 1
+#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI1_UART)
+#undef CONFIG_SCI0_SERIAL_CONSOLE
+#undef CONFIG_SCI2_SERIAL_CONSOLE
+#undef CONFIG_SCI9_SERIAL_CONSOLE
+#define HAVE_CONSOLE 1
+#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI2_UART)
+#undef CONFIG_SCI0_SERIAL_CONSOLE
+#undef CONFIG_SCI1_SERIAL_CONSOLE
+#undef CONFIG_SCI9_SERIAL_CONSOLE
+#define HAVE_CONSOLE 1
+#elif defined(CONFIG_SCI9_SERIAL_CONSOLE) && defined(CONFIG_RA_SCI9_UART)
+#undef CONFIG_SCI0_SERIAL_CONSOLE
+#undef CONFIG_SCI1_SERIAL_CONSOLE
+#undef CONFIG_SCI2_SERIAL_CONSOLE
+#define HAVE_CONSOLE 1
+#else
+#ifndef CONFIG_NO_SERIAL_CONSOLE
+#warning "No valid CONFIG_SCIn_SERIAL_CONSOLE Setting"
+#endif
+
+#undef CONFIG_SCI0_SERIAL_CONSOLE
+#undef CONFIG_SCI1_SERIAL_CONSOLE
+#undef CONFIG_SCI2_SERIAL_CONSOLE
+#undef CONFIG_SCI9_SERIAL_CONSOLE
+#undef HAVE_CONSOLE
+#endif
+
+/* First pick the console and ttys0. */
+
+#if defined(CONFIG_SCI0_SERIAL_CONSOLE)
+#define CONSOLE_DEV g_uart0port /* UART0 is console */
+#define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */
+#define UART0_ASSIGNED 1
+#elif defined(CONFIG_SCI1_SERIAL_CONSOLE)
+#define CONSOLE_DEV g_uart1port /* UART1 is console */
+#define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+#define UART1_ASSIGNED 1
+#elif defined(CONFIG_SCI2_SERIAL_CONSOLE)
+#define CONSOLE_DEV g_uart2port /* UART2 is console */
+#define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */
+#define UART2_ASSIGNED 1
+#elif defined(CONFIG_SCI9_SERIAL_CONSOLE)
+#define CONSOLE_DEV g_uart9port /* UART9 is console */
+#define TTYS0_DEV g_uart9port /* UART9 is ttyS0 */
+#define UART9_ASSIGNED 1
+#else
+#undef CONSOLE_DEV /* No console */
+#if defined(CONFIG_RA_SCI0_UART)
+#define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */
+#define UART0_ASSIGNED 1
+#elif defined(CONFIG_RA_SCI1_UART)
+#define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+#define UART1_ASSIGNED 1
+#elif defined(CONFIG_RA_SCI2_UART)
+#define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */
+#define UART2_ASSIGNED 1
+#elif defined(CONFIG_RA_SCI9_UART)
+#define TTYS0_DEV g_uart9port /* UART9 is ttyS0 */
+#define UART9_ASSIGNED 1
+#endif
+#endif
+
+/* Pick ttys1. */
+
+#if defined(CONFIG_RA_SCI0_UART) && !defined(UART0_ASSIGNED)
+#define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */
+#define UART0_ASSIGNED 1
+#elif defined(CONFIG_RA_SCI1_UART) && !defined(UART1_ASSIGNED)
+#define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */
+#define UART1_ASSIGNED 1
+#elif defined(CONFIG_RA_SCI2_UART) && !defined(UART2_ASSIGNED)
+#define TTYS1_DEV g_usart0port /* UART2 is ttyS1 */
+#define UART2_ASSIGNED 1
+#elif defined(CONFIG_RA_SCI9_UART) && !defined(UART9_ASSIGNED)
+#define TTYS1_DEV g_usart1port /* UART9 is ttyS1 */
+#define UART9_ASSIGNED 1
+#endif
+
+#define SCI_UART_ERR_BITS (R_SCI_SSR_PER | R_SCI_SSR_FER | R_SCI_SSR_ORER)
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int up_setup(struct uart_dev_s *dev);
+static void up_shutdown(struct uart_dev_s *dev);
+static int up_attach(struct uart_dev_s *dev);
+static void up_detach(struct uart_dev_s *dev);
+static int up_rxinterrupt(int irq, void *context, void *arg);
+static int up_txinterrupt(int irq, void *context, void *arg);
+static int up_erinterrupt(int irq, void *context, void *arg);
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int up_receive(struct uart_dev_s *dev, unsigned int *status);
+static void up_rxint(struct uart_dev_s *dev, bool enable);
+static bool up_rxavailable(struct uart_dev_s *dev);
+static void up_send(struct uart_dev_s *dev, int ch);
+static void up_txint(struct uart_dev_s *dev, bool enable);
+static bool up_txready(struct uart_dev_s *dev);
+static bool up_txempty(struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+struct up_dev_s
+{
+ const uint32_t scibase; /* Base address of SCI registers */
+ uint32_t mstp; /* Module Stop Control Register */
+ uint32_t baud; /* Configured baud */
+ uint32_t sr; /* Saved status bits */
+ uint8_t rxirq; /* IRQ associated with this SCI */
+ uint8_t txirq; /* IRQ associated with this SCI */
+ uint8_t teirq; /* IRQ associated with this SCI */
+ uint8_t erirq; /* IRQ associated with this SCI */
+ uint8_t parity; /* 0=none, 1=odd, 2=even */
+ uint8_t bits; /* Number of bits (5-9) */
+ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
+};
+
+static const struct uart_ops_s g_uart_ops =
+{
+ .setup = up_setup,
+ .shutdown = up_shutdown,
+ .attach = up_attach,
+ .detach = up_detach,
+ .ioctl = up_ioctl,
+ .receive = up_receive,
+ .rxint = up_rxint,
+ .rxavailable = up_rxavailable,
+ .send = up_send,
+ .txint = up_txint,
+ .txready = up_txready,
+ .txempty = up_txempty,
+};
+
+/* I/O buffers */
+#if defined(CONFIG_RA_SCI0_UART)
+static char g_uart0rxbuffer[CONFIG_SCI0_RXBUFSIZE];
+static char g_uart0txbuffer[CONFIG_SCI0_TXBUFSIZE];
+#elif defined(CONFIG_RA_SCI1_UART)
+static char g_uart1rxbuffer[CONFIG_SCI1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_SCI1_TXBUFSIZE];
+#elif defined(CONFIG_RA_SCI2_UART)
+static char g_uart2rxbuffer[CONFIG_SCI2_RXBUFSIZE];
+static char g_uart2txbuffer[CONFIG_SCI2_TXBUFSIZE];
+#elif defined(CONFIG_RA_SCI9_UART)
+static char g_uart9rxbuffer[CONFIG_SCI9_RXBUFSIZE];
+static char g_uart9txbuffer[CONFIG_SCI9_TXBUFSIZE];
+#endif
+
+#if defined(CONFIG_RA_SCI0_UART)
+static struct up_dev_s g_uart0priv =
+{
+ .scibase = R_SCI0_BASE,
+ .mstp = R_MSTP_MSTPCRB_SCI0,
+ .rxirq = SCI0_RXI,
+ .txirq = SCI0_TXI,
+ .teirq = SCI0_TEI,
+ .erirq = SCI0_ERI,
+ .baud = CONFIG_SCI0_BAUD,
+ .parity = CONFIG_SCI0_PARITY,
+ .bits = CONFIG_SCI0_BITS,
+ .stopbits2 = CONFIG_SCI0_2STOP,
+};
+
+static uart_dev_t g_uart0port =
+{
+ .recv =
+ {
+ .size = CONFIG_SCI0_RXBUFSIZE,
+ .buffer = g_uart0rxbuffer,
+ },
+ .xmit =
+ {
+ .size = CONFIG_SCI0_TXBUFSIZE,
+ .buffer = g_uart0txbuffer,
+ },
+ .ops = &g_uart_ops,
+ .priv = &g_uart0priv,
+};
+
+#elif defined(CONFIG_RA_SCI1_UART)
+static struct up_dev_s g_uart1priv =
+{
+ .scibase = R_SCI1_BASE,
+ .mstp = R_MSTP_MSTPCRB_SCI2,
+ .rxirq = SCI1_RXI,
+ .txirq = SCI1_TXI,
+ .teirq = SCI1_TEI,
+ .erirq = SCI1_ERI,
+ .baud = CONFIG_SCI1_BAUD,
+ .parity = CONFIG_SCI1_PARITY,
+ .bits = CONFIG_SCI1_BITS,
+ .stopbits2 = CONFIG_SCI1_2STOP,
+};
+
+static uart_dev_t g_uart1port =
+{
+ .recv =
+ {
+ .size = CONFIG_SCI1_RXBUFSIZE,
+ .buffer = g_uart1rxbuffer,
+ },
+ .xmit =
+ {
+ .size = CONFIG_SCI1_TXBUFSIZE,
+ .buffer = g_uart1txbuffer,
+ },
+ .ops = &g_uart_ops,
+ .priv = &g_uart1priv,
+};
+
+#elif defined(CONFIG_RA_SCI2_UART)
+static struct up_dev_s g_uart2priv =
+{
+ .scibase = R_SCI2_BASE,
+ .mstp = R_MSTP_MSTPCRB_SCI2,
+ .rxirq = SCI2_RXI,
+ .txirq = SCI2_TXI,
+ .teirq = SCI2_TEI,
+ .erirq = SCI2_ERI,
+ .baud = CONFIG_SCI2_BAUD,
+ .parity = CONFIG_SCI2_PARITY,
+ .bits = CONFIG_SCI2_BITS,
+ .stopbits2 = CONFIG_SCI2_2STOP,
+};
+
+static uart_dev_t g_uart2port =
+{
+ .recv =
+ {
+ .size = CONFIG_SCI2_RXBUFSIZE,
+ .buffer = g_uart2rxbuffer,
+ },
+ .xmit =
+ {
+ .size = CONFIG_SCI2_TXBUFSIZE,
+ .buffer = g_uart2txbuffer,
+ },
+ .ops = &g_uart_ops,
+ .priv = &g_uart2priv,
+};
+
+#elif defined(CONFIG_RA_SCI9_UART)
+static struct up_dev_s g_uart9priv =
+{
+ .scibase = R_SCI9_BASE,
+ .mstp = R_MSTP_MSTPCRB_SCI9,
+ .rxirq = SCI9_RXI,
+ .txirq = SCI9_TXI,
+ .teirq = SCI9_TEI,
+ .erirq = SCI9_ERI,
+ .baud = CONFIG_SCI9_BAUD,
+ .parity = CONFIG_SCI9_PARITY,
+ .bits = CONFIG_SCI9_BITS,
+ .stopbits2 = CONFIG_SCI9_2STOP,
+};
+
+static uart_dev_t g_uart9port =
+{
+ .recv =
+ {
+ .size = CONFIG_SCI9_RXBUFSIZE,
+ .buffer = g_uart9rxbuffer,
+ },
+ .xmit =
+ {
+ .size = CONFIG_SCI9_TXBUFSIZE,
+ .buffer = g_uart9txbuffer,
+ },
+ .ops = &g_uart_ops, .priv = &g_uart9priv,
+};
+
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialin
+ ****************************************************************************/
+
+static inline uint8_t up_serialin(struct up_dev_s *priv, int offset)
+{
+ return getreg8(priv->scibase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialout
+ ****************************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, int offset,
+ uint8_t value)
+{
+ putreg8(value, priv->scibase + offset);
+}
+
+/****************************************************************************
+ * Name: up_disableallints
+ ****************************************************************************/
+
+static void up_disableallints(struct up_dev_s *priv, uint32_t *ie)
+{
+ irqstate_t flags;
+ uint8_t regval = 0;
+
+ /* The following must be atomic */
+
+ flags = enter_critical_section();
+ if (ie)
+ {
+ /* Return the current interrupt mask */
+
+ *ie = up_serialin(priv, R_SCI_SCR_OFFSET);
+ }
+
+ /* Disable all interrupts */
+
+ regval = up_serialin(priv, R_SCI_SCR_OFFSET) &
+ ~(R_SCI_SCR_TIE | R_SCI_SCR_RIE);
+ up_serialout(priv, R_SCI_SCR_OFFSET, regval);
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_sci_config
+ *
+ * Description:
+ * Configure the SCI baud, bits, parity, etc. This method is called the
+ * first time that the serial port is opened.
+ *
+ ****************************************************************************/
+
+static void up_sci_config(struct up_dev_s *priv)
+{
+ uint8_t div_baud[4] = {
+ 12, 16, 32, 64
+ };
+
+ uint64_t brr = 0;
+ uint32_t reg_brr = 0;
+ uint32_t best_brr = 0;
+ uint32_t actual_baudrate = 0;
+ int32_t error = 0;
+ int32_t min_error = INT32_MAX;
+ uint8_t best_n = 0;
+ uint8_t best_i = 0;
+ uint8_t regval = 0;
+
+ for (uint8_t i = 0; i < 4; i++)
+ {
+ for (uint8_t n = 0; n < 4; n++)
+ {
+ uint32_t div_n = (n == 0) ? 1 : (1U << (2 * n - 1));
+ uint32_t multiplier = (n == 0) ? 2UL : 1UL;
+
+ brr =
+ (((uint64_t)RA_PCKA_FREQUENCY * 100UL * multiplier) /
+ (div_baud[i] * div_n * priv->baud)) - 100;
+ reg_brr = ((brr + 50) / 100);
+
+ if (reg_brr > 255)
+ {
+ continue;
+ }
+
+ actual_baudrate = ((uint32_t)RA_PCKA_FREQUENCY * multiplier) /
+ (div_baud[i] * div_n * (reg_brr + 1));
+
+ error = ((int32_t)(actual_baudrate - priv->baud) * 100000) /
+ (int32_t)priv->baud;
+
+ /* Store the best values if we find a new minimum error */
+
+ if (abs(error) < abs(min_error))
+ {
+ min_error = error;
+ best_n = n;
+ best_i = i;
+ best_brr = reg_brr;
+ }
+ }
+ }
+
+ regval = 0;
+ up_serialout(priv, R_SCI_SCR_OFFSET, regval);
+
+ /* UART character length requires change in two registers - SCMR and SMR
+ * SCMR.CHR1 SMR.CHR
+ * 0 0: Transmit/receive in 9-bit data length
+ * 0 1: Transmit/receive in 9-bit data length
+ * 1 0: Transmit/receive in 8-bit data length (initial value)
+ * 1 1: Transmit/receive in 7-bit data length.
+ */
+
+ regval = up_serialin(priv, R_SCI_SCMR_OFFSET);
+
+ if (priv->bits == 9)
+ {
+ regval &= ~R_SCI_SCMR_CHR1;
+ }
+
+ up_serialout(priv, R_SCI_SCMR_OFFSET, regval);
+
+ regval = 0;
+ if (priv->parity > 0)
+ {
+ regval |= R_SCI_SMR_PE;
+ if (priv->parity == 1)
+ {
+ regval |= R_SCI_SMR_PM;
+ }
+ }
+
+ if (priv->stopbits2 == 1)
+ {
+ regval |= R_SCI_SMR_STOP;
+ }
+
+ if (priv->bits == 7 || priv->bits == 9)
+ {
+ regval |= R_SCI_SMR_CHR;
+ }
+
+ regval |= (best_n << R_SCI_SMR_CKS_SHIFT);
+ up_serialout(priv, R_SCI_SMR_OFFSET, regval);
+ switch (best_i)
+ {
+ case 0:
+ {
+ regval = R_SCI_SEMR_ABCSE;
+ }
+ break;
+
+ case 1:
+ {
+ regval = R_SCI_SEMR_BGDM | R_SCI_SEMR_ABCS;
+ }
+ break;
+
+ case 2:
+ {
+ regval = R_SCI_SEMR_BGDM;
+ }
+ break;
+
+ case 3:
+ {
+ regval = 0;
+ }
+ break;
+ }
+
+ up_serialout(priv, R_SCI_SEMR_OFFSET, regval);
+
+ regval = best_brr;
+
+ up_serialout(priv, R_SCI_BRR_OFFSET, regval);
+
+ regval = (R_SCI_SCR_TE | R_SCI_SCR_RE | R_SCI_SCR_TIE | R_SCI_SCR_RIE);
+ up_serialout(priv, R_SCI_SCR_OFFSET, regval);
+}
+
+static int up_setup(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+#if defined(CONFIG_RA_SCI0_UART)
+ ra_configgpio(GPIO_SCI0_RX);
+ ra_configgpio(GPIO_SCI0_TX);
+#elif defined(CONFIG_RA_SCI1_UART)
+ ra_configgpio(GPIO_SCI1_RX);
+ ra_configgpio(GPIO_SCI1_TX);
+#elif defined(CONFIG_RA_SCI2_UART)
+ ra_configgpio(GPIO_SCI2_RX);
+ ra_configgpio(GPIO_SCI2_TX);
+#elif defined(CONFIG_RA_SCI9_UART)
+ ra_configgpio(GPIO_SCI9_RX);
+ ra_configgpio(GPIO_SCI9_TX);
+#endif
+
+ up_shutdown(dev);
+
+ putreg16((R_SYSTEM_PRCR_PRKEY_VALUE | R_SYSTEM_PRCR_PRC1), R_SYSTEM_PRCR);
+ modifyreg32(R_MSTP_MSTPCRB, priv->mstp, 0);
+ putreg16(R_SYSTEM_PRCR_PRKEY_VALUE, R_SYSTEM_PRCR);
+
+ up_sci_config(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ * Disable the SCI.
+ *
+ ****************************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ /* Reset SCI control */
+
+ up_serialout(priv, R_SCI_SCR_OFFSET, 0);
+
+ /* Stop SCI */
+
+ putreg16((R_SYSTEM_PRCR_PRKEY_VALUE | R_SYSTEM_PRCR_PRC1), R_SYSTEM_PRCR);
+ modifyreg32(R_MSTP_MSTPCRB, priv->mstp, 1);
+ putreg16(R_SYSTEM_PRCR_PRKEY_VALUE, R_SYSTEM_PRCR);
+}
+
+/****************************************************************************
+ * Name: up_attach
+ *
+ * Description:
+ * Configure the SCI to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the setup() method is called, however, the serial console may operate in
+ * a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ ****************************************************************************/
+
+static int up_attach(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ int ret;
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->rxirq, up_rxinterrupt, dev);
+ if (ret < 0)
+ {
+ return ret;
+ }
+
+ ret = irq_attach(priv->txirq, up_txinterrupt, dev);
+ if (ret < 0)
+ {
+ irq_detach(priv->rxirq);
+ return ret;
+ }
+
+ ret = irq_attach(priv->erirq, up_erinterrupt, dev);
+ if (ret < 0)
+ {
+ irq_detach(priv->erirq);
+ return ret;
+ }
+
+ up_enable_irq(priv->rxirq);
+ up_enable_irq(priv->txirq);
+ up_enable_irq(priv->erirq);
+
+ return ret;
+}
+
+static void up_detach(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ up_disable_irq(priv->rxirq);
+ up_disable_irq(priv->txirq);
+ up_disable_irq(priv->erirq);
+ irq_detach(priv->rxirq);
+ irq_detach(priv->txirq);
+ irq_detach(priv->erirq);
+}
+
+/****************************************************************************
+ * Name: up_rxinterrupt
+ *
+ * Description:
+ * This is the common SCI RX interrupt handler.
+ *
+ ****************************************************************************/
+
+static int up_rxinterrupt(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+
+ ra_clear_ir(irq);
+ uart_recvchars(dev);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: up_txinterrupt
+ *
+ * Description:
+ * This is the common SCI TX interrupt handler.
+ *
+ ****************************************************************************/
+
+static int up_txinterrupt(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+
+ ra_clear_ir(irq);
+ uart_xmitchars(dev);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: up_erinterrupt
+ *
+ * Description:
+ * This is the common SCI Error interrupt handler.
+ *
+ ****************************************************************************/
+
+static int up_erinterrupt(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct up_dev_s *priv;
+ uint8_t regval = 0;
+
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
+ priv = (struct up_dev_s *)dev->priv;
+
+ /* Save for error reporting */
+
+ priv->sr = up_serialin(priv, R_SCI_SSR_OFFSET) & SCI_UART_ERR_BITS;
+
+ regval = up_serialin(priv, R_SCI_SSR_OFFSET) & ~(SCI_UART_ERR_BITS);
+
+ up_serialout(priv, R_SCI_SSR_OFFSET, regval);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = -ENOTTY;
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the SCI. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ /* Return the error information in the saved status */
+
+ *status = priv->sr;
+ priv->sr = 0;
+
+ /* Then return the actual received byte */
+
+ return (int)(up_serialin(priv, R_SCI_RDR_OFFSET) & 0xff);
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ uint8_t regval;
+
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+ if (enable)
+ {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ /* Enable the RX interrupt */
+
+ regval = up_serialin(priv, R_SCI_SCR_OFFSET);
+ regval |= (R_SCI_SCR_RIE);
+ up_serialout(priv, R_SCI_SCR_OFFSET, regval);
+
+#endif
+ }
+ else
+ {
+ /* Disable the RX interrupt */
+
+ regval = up_serialin(priv, R_SCI_SCR_OFFSET);
+ regval &= ~(R_SCI_SCR_RIE);
+ up_serialout(priv, R_SCI_SCR_OFFSET, regval);
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_rxavailable
+ *
+ * Description:
+ * Return true if the receive holding register is not empty
+ *
+ ****************************************************************************/
+
+static bool up_rxavailable(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ return (up_serialin(priv,
+ R_SCI_SSR_OFFSET) & R_SCI_SSR_RDRF) ==
+ R_SCI_SSR_RDRF;
+}
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ * This method will send one byte on the SCI
+ *
+ ****************************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ up_serialout(priv, R_SCI_TDR_OFFSET, (uint8_t)ch);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ uint8_t regval;
+
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+ if (enable)
+ {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ /* Enable the TX interrupt */
+
+ regval = up_serialin(priv, R_SCI_SCR_OFFSET);
+ regval |= (R_SCI_SCR_TIE);
+ up_serialout(priv, R_SCI_SCR_OFFSET, regval);
+
+ /* Fake a TX interrupt here by just calling uart_xmitchars() with
+ * interrupts disabled (note this may recurse).
+ */
+
+ uart_xmitchars(dev);
+
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ regval = up_serialin(priv, R_SCI_SCR_OFFSET);
+ regval &= ~(R_SCI_SCR_TIE);
+ up_serialout(priv, R_SCI_SCR_OFFSET, regval);
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ * Return true if the transmit holding register is empty (SSR.TDRE)
+ *
+ ****************************************************************************/
+
+static bool up_txready(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ bool ret =
+ ((up_serialin(priv,
+ R_SCI_SSR_OFFSET) & R_SCI_SSR_TDRE) == R_SCI_SSR_TDRE);
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: up_txempty
+ *
+ * Description:
+ * Return true if the transmit holding and shift registers are empty
+ *
+ ****************************************************************************/
+
+static bool up_txempty(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ bool ret =
+ ((up_serialin(priv,
+ R_SCI_SSR_OFFSET) & R_SCI_SSR_TEND) == R_SCI_SSR_TEND);
+
+ return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_earlyserialinit
+ *
+ * Description:
+ * Performs the low level SCI initialization early in debug so that the
+ * serial console will be available during bootup. This must be called
+ * before arm_serialinit.
+ *
+ ****************************************************************************/
+
+void arm_earlyserialinit(void)
+{
+ /* Disable all SCIS */
+
+#ifdef TTYS0_DEV
+ up_disableallints(TTYS0_DEV.priv, NULL);
+#endif
+#ifdef TTYS1_DEV
+ up_disableallints(TTYS1_DEV.priv, NULL);
+#endif
+#ifdef TTYS2_DEV
+ up_disableallints(TTYS2_DEV.priv, NULL);
+#endif
+#ifdef TTYS3_DEV
+ up_disableallints(TTYS3_DEV.priv, NULL);
+#endif
+#ifdef TTYS4_DEV
+ up_disableallints(TTYS4_DEV.priv, NULL);
+#endif
+#ifdef TTYS5_DEV
+ up_disableallints(TTYS5_DEV.priv, NULL);
+#endif
+
+#ifdef HAVE_CONSOLE
+ /* Configuration whichever one is the console */
+
+ CONSOLE_DEV.isconsole = true;
+
+ up_setup(&CONSOLE_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: arm_serialinit
+ *
+ * Description:
+ * Register serial console and serial ports. This assumes
+ * that arm_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void arm_serialinit(void)
+{
+ /* Register the console */
+
+#ifdef HAVE_CONSOLE
+ uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+
+ /* Register all SCIs */
+#ifdef TTYS0_DEV
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
+#endif
+#ifdef TTYS1_DEV
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
+#endif
+#ifdef TTYS2_DEV
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
+#endif
+#ifdef TTYS3_DEV
+ uart_register("/dev/ttyS3", &TTYS3_DEV);
+#endif
+#ifdef TTYS4_DEV
+ uart_register("/dev/ttyS4", &TTYS4_DEV);
+#endif
+#ifdef TTYS5_DEV
+ uart_register("/dev/ttyS5", &TTYS5_DEV);
+#endif
+}
diff --git a/arch/arm/src/ra4/ra_start.c b/arch/arm/src/ra4/ra_start.c
new file mode 100644
index 0000000000000..98250e2e2c831
--- /dev/null
+++ b/arch/arm/src/ra4/ra_start.c
@@ -0,0 +1,139 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_start.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+
+#include
+#include "arch/board/board.h"
+#include "arm_internal.h"
+#include "nvic.h"
+#include "ra_clockconfig.h"
+#include "ra_lowputc.h"
+#include "ra_start.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define HEAP_BASE ((uint32_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+const uintptr_t g_idle_topstack = HEAP_BASE;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: showprogress
+ *
+ * Description:
+ * Print a character on the CONSOLE USART to show boot status.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_FEATURES
+# define showprogress(c) arm_lowputc(c)
+#else
+# define showprogress(c)
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: __start
+ *
+ * Description:
+ * This is the reset entry point.
+ *
+ ****************************************************************************/
+
+void __start(void)
+{
+ const uint32_t *src;
+ uint32_t *dest;
+
+ /* Configure the uart so that we can get debug output as soon as possible */
+
+ /* Clear .bss. We'll do this inline (vs. calling memset) just to be
+ * certain that there are no issues with the state of global variables.
+ */
+
+ for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; )
+ {
+ *dest++ = 0;
+ }
+
+ /* Move the initialized data section from his temporary holding spot in
+ * FLASH into the correct place in SRAM. The correct place in SRAM is
+ * give by _sdata and _edata. The temporary location is in FLASH at the
+ * end of all of the other read-only data (.text, .rodata) at _eronly.
+ */
+
+ for (src = (const uint32_t *)_eronly, dest = (uint32_t *)_sdata;
+ dest < (uint32_t *)_edata;
+ )
+ {
+ *dest++ = *src++;
+ }
+
+ ra_clockconfig();
+ arm_fpuconfig();
+ ra_lowsetup();
+ showprogress('A');
+
+ /* Perform early serial initialization */
+#ifdef USE_EARLYSERIALINIT
+ arm_earlyserialinit();
+#endif
+ showprogress('B');
+
+ /* Initialize onboard resources */
+
+ ra_boardinitialize();
+
+ showprogress('C');
+
+ /* Then start NuttX */
+
+ showprogress('\r');
+ showprogress('\n');
+
+ nx_start();
+
+ /* Shouldn't get here */
+
+ for (; ; )
+ {
+ }
+}
diff --git a/arch/arm/src/ra4/ra_start.h b/arch/arm/src/ra4/ra_start.h
new file mode 100644
index 0000000000000..fa8a05e1eff0e
--- /dev/null
+++ b/arch/arm/src/ra4/ra_start.h
@@ -0,0 +1,36 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_start.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_START_H
+#define __ARCH_ARM_SRC_RA_START_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void ra_boardinitialize(void);
+
+#endif /* __ARCH_ARM_SRC_RA_START_H */
diff --git a/arch/arm/src/ra4/ra_timerisr.c b/arch/arm/src/ra4/ra_timerisr.c
new file mode 100644
index 0000000000000..929f37cd3adab
--- /dev/null
+++ b/arch/arm/src/ra4/ra_timerisr.c
@@ -0,0 +1,123 @@
+/****************************************************************************
+ * arch/arm/src/ra4/ra_timerisr.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "nvic.h"
+#include "clock/clock.h"
+#include "arm_internal.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define SYSTICK_CLOCK (RA_ICLK_FREQUENCY)
+
+#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1)
+
+/* The size of the reload field is 24 bits. Verify that the reload value
+ * will fit in the reload register.
+ */
+
+#define SYSTICK_MAX 0x00ffffff
+#if SYSTICK_RELOAD > SYSTICK_MAX
+# error SYSTICK_RELOAD exceeds the range of the RELOAD register
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: ra_timerisr
+ *
+ * Description:
+ * The timer ISR will perform a variety of services for various portions
+ * of the systems.
+ *
+ ****************************************************************************/
+
+#if !defined(CONFIG_ARMV7M_SYSTICK) && !defined(CONFIG_TIMER_ARCH)
+static int ra_timerisr(int irq, uint32_t *regs, void *arg)
+{
+ /* Process timer interrupt */
+
+ nxsched_process_timer();
+ return 0;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: up_timer_initialize
+ *
+ * Description:
+ * This function is called during start-up to initialize
+ * the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+ uint32_t regval;
+
+ /* Set the SysTick interrupt to the default priority */
+
+ regval = getreg32(NVIC_SYSH12_15_PRIORITY);
+ regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
+ regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
+ putreg32(regval, NVIC_SYSH12_15_PRIORITY);
+
+ /* Make sure that the SYSTICK clock source is set correctly */
+
+#if defined(CONFIG_ARMV7M_SYSTICK) && defined(CONFIG_TIMER_ARCH)
+ up_timer_set_lowerhalf(systick_initialize(true, SYSTICK_CLOCK, -1));
+#else
+ /* Configure SysTick to interrupt at the requested rate */
+
+ putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
+
+ /* Attach the timer interrupt vector */
+
+ irq_attach(RA_IRQ_SYSTICK, (xcpt_t)ra_timerisr, NULL);
+
+ /* Enable SysTick interrupts */
+
+ putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
+ NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
+
+ /* And enable the timer interrupt */
+
+ up_enable_irq(RA_IRQ_SYSTICK);
+#endif
+}
diff --git a/boards/Kconfig b/boards/Kconfig
index a1e4b603ba5e9..48b22f084b77a 100644
--- a/boards/Kconfig
+++ b/boards/Kconfig
@@ -35,6 +35,14 @@ config ARCH_BOARD_ARDUINO_DUE
This options selects the Arduino DUE board featuring the Atmel
ATSAM3X8E MCU running at 84 MHz.
+config ARCH_BOARD_ARDUINO_R4_MINIMA
+ bool "Arduino R4 Minima"
+ depends on ARCH_CHIP_RA4
+ select ARCH_HAVE_LEDS
+ ---help---
+ This options selects the Arduino R4 Minima board featuring the Renesas
+ R7FA4M1 MCU running at 48 MHz.
+
config ARCH_BOARD_ARDUINO_M0
bool "Arduino M0"
depends on ARCH_CHIP_SAMD21G18A
@@ -3313,6 +3321,7 @@ config ARCH_BOARD
default "amber" if ARCH_BOARD_AMBER
default "arduino-mega2560" if ARCH_BOARD_ARDUINO_MEGA2560
default "arduino-due" if ARCH_BOARD_ARDUINO_DUE
+ default "arduino-r4-minima" if ARCH_BOARD_ARDUINO_R4_MINIMA
default "arduino-m0" if ARCH_BOARD_ARDUINO_M0
default "arduino-nano-33ble" if ARCH_BOARD_ARDUINO_NANO_33BLE
default "arduino-nano-33ble-rev2" if ARCH_BOARD_ARDUINO_NANO_33BLE_REV2
@@ -4000,6 +4009,9 @@ endif
if ARCH_BOARD_ARDUINO_DUE
source "boards/arm/sam34/arduino-due/Kconfig"
endif
+if ARCH_BOARD_ARDUINO_R4_MINIMA
+source "boards/arm/ra4/arduino-r4-minima/Kconfig"
+endif
if ARCH_BOARD_ARDUINO_M0
source "boards/arm/samd2l2/arduino-m0/Kconfig"
endif
diff --git a/boards/arm/ra4/arduino-r4-minima/CMakeLists.txt b/boards/arm/ra4/arduino-r4-minima/CMakeLists.txt
new file mode 100644
index 0000000000000..e37293135ec0e
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/CMakeLists.txt
@@ -0,0 +1,21 @@
+# ##############################################################################
+# boards/arm/nrf52/nrf52-feather/CMakeLists.txt
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements. See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership. The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License. You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+add_subdirectory(src)
diff --git a/boards/arm/ra4/arduino-r4-minima/Kconfig b/boards/arm/ra4/arduino-r4-minima/Kconfig
new file mode 100644
index 0000000000000..5d94625c18c8e
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_ARDUINO_R4_MINIMA
+
+endif
diff --git a/boards/arm/ra4/arduino-r4-minima/configs/nsh-leds/defconfig b/boards/arm/ra4/arduino-r4-minima/configs/nsh-leds/defconfig
new file mode 100644
index 0000000000000..329eeae53abe9
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/configs/nsh-leds/defconfig
@@ -0,0 +1,41 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_LEDS is not set
+# CONFIG_READLINE_ECHO is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="arduino-r4-minima"
+CONFIG_ARCH_BOARD_ARDUINO_R4_MINIMA=y
+CONFIG_ARCH_CHIP="ra4"
+CONFIG_ARCH_CHIP_R7FA4M1ABxxFM=y
+CONFIG_ARCH_CHIP_RA4=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=6965
+CONFIG_BUILTIN=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=32768
+CONFIG_RAM_START=0x20000000
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SCI2_SERIAL_CONSOLE=y
+CONFIG_START_DAY=28
+CONFIG_START_MONTH=6
+CONFIG_START_YEAR=2013
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=32
+CONFIG_USERLED=y
+CONFIG_USERLED_LOWER=y
diff --git a/boards/arm/ra4/arduino-r4-minima/configs/nsh/defconfig b/boards/arm/ra4/arduino-r4-minima/configs/nsh/defconfig
new file mode 100644
index 0000000000000..7ec30433017cd
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/configs/nsh/defconfig
@@ -0,0 +1,40 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="arduino-r4-minima"
+CONFIG_ARCH_BOARD_ARDUINO_R4_MINIMA=y
+CONFIG_ARCH_CHIP="ra4"
+CONFIG_ARCH_CHIP_R7FA4M1ABxxFM=y
+CONFIG_ARCH_CHIP_RA4=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=6965
+CONFIG_BUILTIN=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=32768
+CONFIG_RAM_START=0x20000000
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SCI2_SERIAL_CONSOLE=y
+CONFIG_START_DAY=28
+CONFIG_START_MONTH=6
+CONFIG_START_YEAR=2013
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=32
+CONFIG_TESTING_OSTEST=y
+CONFIG_TESTING_OSTEST_NBARRIER_THREADS=3
+CONFIG_TESTING_OSTEST_STACKSIZE=2048
diff --git a/boards/arm/ra4/arduino-r4-minima/include/board.h b/boards/arm/ra4/arduino-r4-minima/include/board.h
new file mode 100644
index 0000000000000..ca4ecdb06d286
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/include/board.h
@@ -0,0 +1,128 @@
+/****************************************************************************
+ * boards/arm/ra4/arduino-r4-minima/include/board.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_RA_ARDUINO_UNO_R4_INCLUDE_BOARD_H
+#define __BOARDS_ARM_RA_ARDUINO_UNO_R4_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking *****************************************************************/
+
+/* This is the canonical configuration:
+ * System Clock source : HOCO
+ * ICLK(Hz) : 64000000
+ * PCLKA(Hz) : 64000000
+ * PCLKB(Hz) : 64000000
+ * PCLKC(Hz) : 64000000
+ * PCLKD(Hz) : 64000000
+ * FCLK(Hz) : 64000000
+ * USBCLK(Hz) : 0
+ */
+
+/* Clock selection HOCO, MOCO, LOCO, PLL */
+
+#define RA_CKSEL R_SYSTEM_SCKSCR_CKSEL_HOCO
+
+#define RA_HOCOEN !R_OFS1_HOCOEN /* Inverted logic to enable */
+#define RA_HOCO_FREQUENCY R_OFS1_HOCOFRQ1_64MHZ
+
+#define RA_ICK_DIV R_SYSTEM_SCKDIVCR_ICK_DIV_1
+#define RA_ICLK_FREQUENCY 64000000
+#define RA_FCK_DIV R_SYSTEM_SCKDIVCR_FCK_DIV_1
+#define RA_FCK_FREQUENCY 64000000
+#define RA_PCKA_DIV R_SYSTEM_SCKDIVCR_PCKA_DIV_1
+#define RA_PCKA_FREQUENCY 64000000
+#define RA_PCKB_DIV R_SYSTEM_SCKDIVCR_PCKB_DIV_1
+#define RA_PCKB_FREQUENCY 64000000
+#define RA_PCKC_DIV R_SYSTEM_SCKDIVCR_PCKC_DIV_1
+#define RA_PCKC_FREQUENCY 64000000
+#define RA_PCKD_DIV R_SYSTEM_SCKDIVCR_PCKD_DIV_1
+#define RA_PCKD_FREQUENCY 64000000
+
+/* Alternate function pin selections */
+
+#define GPIO_SCI2_RX GPIO_RXD2_MISO2_SCL2_1 /* P301 */
+#define GPIO_SCI2_TX GPIO_TXD2_MOSI2_SDA2_1 /* P302 */
+
+#define GPIO_SCI1_RX GPIO_RXD1_MISO1_SCL1_3 /* P502 */
+#define GPIO_SCI1_TX GPIO_TXD1_MOSI1_SDA1_3 /* P501 */
+
+#define GPIO_SCI9_RX GPIO_RXD9_MISO9_SCL9_1 /* P110 */
+#define GPIO_SCI9_TX GPIO_TXD9_MOSI9_SDA9_1 /* P109 */
+
+/* LED pin selections */
+
+#define GPIO_L_LED (gpio_pinset_t){ PORT1,PIN11, (GPIO_OUPUT | GPIO_LOW_DRIVE | GPIO_OUTPUT_LOW)} /* P111 */
+#define GPIO_TX_LED (gpio_pinset_t){ PORT0,PIN12, (GPIO_OUPUT | GPIO_LOW_DRIVE | GPIO_OUTPUT_HIGH)} /* P012 */
+#define GPIO_RX_LED (gpio_pinset_t){ PORT0,PIN13, (GPIO_OUPUT | GPIO_LOW_DRIVE | GPIO_OUTPUT_HIGH)} /* P013 */
+
+#define LED_DRIVER_PATH "/dev/userleds"
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_LED_L 0
+#define BOARD_LED_RX 1
+#define BOARD_LED_TX 2
+#define BOARD_NLEDS 3
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LED_L_BIT (1 << BOARD_LED_L)
+#define BOARD_LED_RX_BIT (1 << BOARD_LED_RX)
+#define BOARD_LED_TX_BIT (1 << BOARD_LED_TX)
+
+/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+ * defined. In that case, the usage by the board port is defined in
+ * include/board.h and src/ra4m1_leds.c. The LEDs are used to encode
+ * OS-related events as follows:
+ *
+ * SYMBOL MEANING LED STATE
+ * L TX RX
+ * ----------------------- -------------------------- ---- ---- ----
+ */
+
+ #define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
+ #define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF OFF */
+ #define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF OFF */
+ #define LED_STACKCREATED 1 /* Idle stack created ON OFF OFF */
+ #define LED_INIRQ 2 /* In an interrupt N/C GLOW OFF */
+ #define LED_SIGNAL 2 /* In a signal handler N/C GLOW OFF */
+ #define LED_ASSERTION 2 /* An assertion failed N/C GLOW OFF */
+ #define LED_PANIC 3 /* The system has crashed N/C N/C Blinking */
+ #define LED_PANIC 3 /* MCU is is sleep mode ---- Not used ---- */
+
+/* ID_CODE */
+
+#define IDCODE1 0xFFFFFFFF
+#define IDCODE2 0xFFFFFFFF
+#define IDCODE3 0xFFFFFFFF
+#define IDCODE4 0xFFFFFFFF
+
+#endif /* __BOARDS_ARM_RA_ARDUINO_UNO_R4_INCLUDE_BOARD_H */
diff --git a/boards/arm/ra4/arduino-r4-minima/scripts/Make.defs b/boards/arm/ra4/arduino-r4-minima/scripts/Make.defs
new file mode 100644
index 0000000000000..f41aecb839c44
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/scripts/Make.defs
@@ -0,0 +1,38 @@
+############################################################################
+# boards/arm/ra4/arduino-r4-minima/scripts/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/.config
+include $(TOPDIR)/tools/Config.mk
+include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
+
+ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)arduino-r4-minima.ld
+
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
+AFLAGS := $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
diff --git a/boards/arm/ra4/arduino-r4-minima/scripts/arduino-r4-minima.ld b/boards/arm/ra4/arduino-r4-minima/scripts/arduino-r4-minima.ld
new file mode 100644
index 0000000000000..f28ef0b7c3e2b
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/scripts/arduino-r4-minima.ld
@@ -0,0 +1,128 @@
+/****************************************************************************
+ * boards/arm/ra4m1/arduino-r4-minima/scripts/arduino-r4-minima.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* The RA4M1 has 256Kb of FLASH beginning at address 0x0000:0000 and
+ * 32KB SRAM.
+ */
+
+MEMORY
+{
+ flash (rx) : ORIGIN = 0x00000000, LENGTH = 256K
+ sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
+ idcode (rx) : ORIGIN = 0x01010018, LENGTH = 0x20
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+ENTRY(_stext)
+SECTIONS
+{
+ .text :
+ {
+ _stext = ABSOLUTE(.);
+ *(.vectors)
+ . = _stext + 0x400;
+ KEEP(*(.rom_registers*))
+ *(.text .text.*)
+ *(.fixup)
+ *(.gnu.warning)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.got)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ _etext = ABSOLUTE(.);
+ } > flash
+
+ .init_section :
+ {
+ _sinit = ABSOLUTE(.);
+ KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP(*(.init_array .ctors))
+ _einit = ABSOLUTE(.);
+ } > flash
+
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >flash
+
+ .ARM.exidx :
+ {
+ __exidx_start = ABSOLUTE(.);
+ *(.ARM.exidx*)
+ __exidx_end = ABSOLUTE(.);
+ } >flash
+
+ .id_code :
+ {
+ __ID_Code_Start = .;
+ KEEP(*(.id_code*))
+ __ID_Code_End = .;
+ } > idcode
+
+ .data :
+ {
+ _sdata = ABSOLUTE(.);
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ CONSTRUCTORS
+ . = ALIGN(4);
+ _edata = ABSOLUTE(.);
+ } > sram AT > flash
+
+ _eronly = LOADADDR(.data);
+
+ .ramfunc ALIGN(4):
+ {
+ _sramfuncs = ABSOLUTE(.);
+ *(.ramfunc .ramfunc.*)
+ _eramfuncs = ABSOLUTE(.);
+ } > sram AT > flash
+
+ _framfuncs = LOADADDR(.ramfunc);
+
+ .bss :
+ {
+ _sbss = ABSOLUTE(.);
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(8);
+ _ebss = ABSOLUTE(.);
+ } > sram
+
+ /* Stabs debugging sections. */
+
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/boards/arm/ra4/arduino-r4-minima/src/CMakeLists.txt b/boards/arm/ra4/arduino-r4-minima/src/CMakeLists.txt
new file mode 100644
index 0000000000000..e1ca1ca5145eb
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/src/CMakeLists.txt
@@ -0,0 +1,32 @@
+# ##############################################################################
+# boards/arm/nrf52/thingy91-nrf52/src/CMakeLists.txt
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements. See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership. The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License. You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+set(SRCS ra4m1_boot.c ra4m1_bringup.c ra4m1_appinit.c)
+
+if(CONFIG_ARCH_LEDS)
+ list(APPEND SRCS ra4m1_autoleds.c)
+else()
+ list(APPEND SRCS ra4m1_userleds.c)
+endif()
+
+target_sources(board PRIVATE ${SRCS})
+
+set_property(GLOBAL PROPERTY LD_SCRIPT
+ "${NUTTX_BOARD_DIR}/scripts/arduino-r4-minima.ld")
diff --git a/boards/arm/ra4/arduino-r4-minima/src/Makefile b/boards/arm/ra4/arduino-r4-minima/src/Makefile
new file mode 100644
index 0000000000000..e7585e8d2b50b
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/src/Makefile
@@ -0,0 +1,35 @@
+############################################################################
+# boards/arm/ra4/arduino-r4-minima/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+
+CSRCS = ra4m1_boot.c ra4m1_bringup.c
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += ra4m1_autoleds.c
+else
+CSRCS += ra4m1_userleds.c
+endif
+
+ifeq ($(CONFIG_BOARDCTL),y)
+CSRCS += ra4m1_appinit.c
+endif
+
+include $(TOPDIR)/boards/Board.mk
diff --git a/boards/arm/ra4/arduino-r4-minima/src/arduino-r4-minima.h b/boards/arm/ra4/arduino-r4-minima/src/arduino-r4-minima.h
new file mode 100644
index 0000000000000..8662aa4b30542
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/src/arduino-r4-minima.h
@@ -0,0 +1,71 @@
+/****************************************************************************
+ * boards/arm/ra4/arduino-r4-minima/src/arduino-r4-minima.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_RA4M1_ARDUINO_R4_MINIMA_SRC_H
+#define __BOARDS_ARM_RA4M1_ARDUINO_R4_MINIMA_SRC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+
+#include
+
+#include
+#include
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Functions Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ra_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y :
+ * Called from the NSH library
+ *
+ ****************************************************************************/
+
+int ra4m1_bringup(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_ARM_RA4M1_ARDUINO_R4_MINIMA_SRC_H */
diff --git a/boards/arm/ra4/arduino-r4-minima/src/ra4m1_appinit.c b/boards/arm/ra4/arduino-r4-minima/src/ra4m1_appinit.c
new file mode 100644
index 0000000000000..13e39f6aec6fa
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/src/ra4m1_appinit.c
@@ -0,0 +1,76 @@
+/****************************************************************************
+ * boards/arm/ra4/arduino-r4-minima/src/ra4m1_appinit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+
+#include "arduino-r4-minima.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no
+ * meaning to NuttX; the meaning of the argument is a contract
+ * between the board-specific initialization logic and the
+ * matching application logic. The value could be such things as a
+ * mode enumeration value, a set of DIP switch switch settings, a
+ * pointer to configuration data read from a file or serial FLASH,
+ * or whatever you would like to do with it. Every implementation
+ * should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+ /* Board initialization already performed by board_late_initialize() */
+
+ return OK;
+#else
+ /* Perform board-specific initialization */
+
+ return ra4m1_bringup();
+#endif
+}
diff --git a/boards/arm/ra4/arduino-r4-minima/src/ra4m1_autoleds.c b/boards/arm/ra4/arduino-r4-minima/src/ra4m1_autoleds.c
new file mode 100644
index 0000000000000..035e29e01c101
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/src/ra4m1_autoleds.c
@@ -0,0 +1,193 @@
+/****************************************************************************
+ * boards/arm/ra4/arduino-r4-minima/src/ra4m1_autoleds.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "chip.h"
+#include "ra_gpio.h"
+#include "arduino-r4-minima.h"
+
+/* The board.h file may override pin configurations defined in ra_pinmap.h */
+
+#include
+
+#ifdef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* There are three user-controllable LEDs on board the Arduino Due board:
+ *
+ * LED GPIO
+ * ---------------- -----
+ * L Amber LED P111
+ * TX Yellow LED P012
+ * RX Yellow LED P013
+ *
+ * LED L is connected to ground and can be illuminated by driving the PB27
+ * output high. The TX and RX LEDs are pulled high and can be illuminated by
+ * driving the corresponding
+ * GPIO output to low.
+ *
+ * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+ * defined. In that case, the usage by the board port is defined in
+ * include/board.h and src/ra_leds.c. The LEDs are used to encode OS-related
+ * events as follows:
+ *
+ * SYMBOL MEANING LED STATE
+ * L TX RX
+ * ------------------- ----------------------- -------- -------- --------
+ * LED_STARTED NuttX has been started OFF OFF OFF
+ * LED_HEAPALLOCATE Heap has been allocated OFF OFF OFF
+ * LED_IRQSENABLED Interrupts enabled OFF OFF OFF
+ * LED_STACKCREATED Idle stack created ON OFF OFF
+ * LED_INIRQ In an interrupt N/C GLOW OFF
+ * LED_SIGNAL In a signal handler N/C GLOW OFF
+ * LED_ASSERTION An assertion failed N/C GLOW OFF
+ * LED_PANIC The system has crashed N/C N/C Blinking
+ * LED_IDLE MCU is is sleep mode ------ Not used --------
+ *
+ * Thus if LED L is statically on, NuttX has successfully booted and is,
+ * apparently, running normmally. If LED RX is glowing, then NuttX is
+ * handling interrupts (and also signals and assertions). If TX is flashing
+ * at approximately 2Hz, then a fatal error has been detected and the system
+ */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+ /* Configure RX and TX LED GPIOs for output */
+
+ ra_configgpio(GPIO_L_LED);
+ ra_configgpio(GPIO_RX_LED);
+ ra_configgpio(GPIO_TX_LED);
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+ switch (led)
+ {
+ /* 0: LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED: L=OFF TX=OFF
+ * RX=OFF
+ *
+ * Since the LEDs were initially all OFF and since this state only
+ * occurs one time, nothing need be done.
+ */
+
+ default:
+ case 0:
+ break;
+
+ /* 1: LED_STACKCREATED: L=ON TX=OFF RX=OFF
+ *
+ * This case will also occur only once. Note that unlike the other
+ * LEDs, LED L is active high.
+ */
+
+ case 1:
+ ra_gpiowrite(GPIO_L_LED, true);
+ break;
+
+ /* 2: LED_INIRQ, LED_SIGNAL, LED_ASSERTION: L=N/C TX=ON RX=N/C
+ *
+ * This case will occur many times. LED TX is active low.
+ */
+
+ case 2:
+ ra_gpiowrite(GPIO_TX_LED, false);
+ break;
+
+ /* 3: LED_PANIC: L=N/X TX=N/C RX=ON
+ *
+ * This case will also occur many times. LED RX is active low.
+ */
+
+ case 3:
+ ra_gpiowrite(GPIO_RX_LED, false);
+ break;
+ }
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+ switch (led)
+ {
+ /* 0: LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED: L=OFF TX=OFF
+ * RX=OFF
+ * 1: LED_STACKCREATED: L=ON TX=OFF RX=OFF
+ *
+ * These cases should never happen.
+ */
+
+ default:
+ case 1:
+ case 0:
+ break;
+
+ /* 2: LED_INIRQ, LED_SIGNAL, LED_ASSERTION: L=N/C TX=OFF RX=N/C
+ *
+ * This case will occur many times. LED TX is active low.
+ */
+
+ case 2:
+ ra_gpiowrite(GPIO_TX_LED, true);
+ break;
+
+ /* 3: LED_PANIC: L=N/X TX=N/C RX=OFF
+ *
+ * This case will also occur many times. LED RX is active low.
+ */
+
+ case 3:
+ ra_gpiowrite(GPIO_RX_LED, true);
+ break;
+ }
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/boards/arm/ra4/arduino-r4-minima/src/ra4m1_boot.c b/boards/arm/ra4/arduino-r4-minima/src/ra4m1_boot.c
new file mode 100644
index 0000000000000..550f0b1643e3b
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/src/ra4m1_boot.c
@@ -0,0 +1,78 @@
+/****************************************************************************
+ * boards/arm/ra4/arduino-r4-minima/src/ra4m1_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+
+#include
+
+#include "arduino-r4-minima.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ra4m1_boardinitialize
+ *
+ * Description:
+ * All RA4M1 architectures must provide the following entry point. This
+ * entry point is called early in the initialization -- after all memory
+ * has been configured and mapped but before any devices have been
+ * initialized.
+ *
+ ****************************************************************************/
+
+void ra_boardinitialize(void)
+{
+#ifdef CONFIG_ARCH_LEDS
+ /* Configure on-board LEDs if LED support has been selected. */
+
+ board_autoled_initialize();
+#endif
+}
+
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ * initialization call will be performed in the boot-up sequence to a
+ * function called board_late_initialize(). board_late_initialize() will be
+ * called immediately after up_initialize() is called and just before the
+ * initial application is started. This additional initialization phase
+ * may be used, for example, to initialize board-specific device drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+ /* Perform board-specific initialization */
+
+ ra4m1_bringup();
+}
+
+#endif
diff --git a/boards/arm/ra4/arduino-r4-minima/src/ra4m1_bringup.c b/boards/arm/ra4/arduino-r4-minima/src/ra4m1_bringup.c
new file mode 100644
index 0000000000000..84f80e705719f
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/src/ra4m1_bringup.c
@@ -0,0 +1,80 @@
+/****************************************************************************
+ * boards/arm/ra4/arduino-r4-minima/src/ra4m1_bringup.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "arduino-r4-minima.h"
+
+#include
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#undef HAVE_LEDS
+
+#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER)
+# define HAVE_LEDS 1
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ra4m1_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization
+ *
+ *
+ ****************************************************************************/
+
+int ra4m1_bringup(void)
+{
+ int ret;
+
+#ifdef HAVE_LEDS
+ board_userled_initialize();
+
+ /* Register the LED driver */
+
+ ret = userled_lower_initialize(LED_DRIVER_PATH);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
+ return ret;
+ }
+#endif
+
+ UNUSED(ret);
+ return OK;
+}
diff --git a/boards/arm/ra4/arduino-r4-minima/src/ra4m1_userleds.c b/boards/arm/ra4/arduino-r4-minima/src/ra4m1_userleds.c
new file mode 100644
index 0000000000000..60f4dbafe5adc
--- /dev/null
+++ b/boards/arm/ra4/arduino-r4-minima/src/ra4m1_userleds.c
@@ -0,0 +1,108 @@
+/****************************************************************************
+ * boards/arm/ra4/arduino-r4-minima/src/ra4m1_userleds.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+
+#include "chip.h"
+#include "ra_gpio.h"
+#include "arduino-r4-minima.h"
+
+#include
+
+#ifndef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_userled_initialize
+ ****************************************************************************/
+
+uint32_t board_userled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ ra_configgpio(GPIO_L_LED);
+ ra_configgpio(GPIO_RX_LED);
+ ra_configgpio(GPIO_TX_LED);
+ return BOARD_NLEDS;
+}
+
+/****************************************************************************
+ * Name: board_userled
+ ****************************************************************************/
+
+void board_userled(int led, bool ledon)
+{
+ gpio_pinset_t ledcfg;
+
+ if (led == BOARD_LED_L)
+ {
+ ledcfg = GPIO_L_LED;
+ ledon = ledon;
+ }
+ else if (led == BOARD_LED_RX)
+ {
+ ledcfg = GPIO_RX_LED;
+ ledon = !ledon;
+ }
+ else if (led == BOARD_LED_TX)
+ {
+ ledcfg = GPIO_TX_LED;
+ ledon = !ledon;
+ }
+ else
+ {
+ return;
+ }
+
+ ra_gpiowrite(ledcfg, ledon);
+}
+
+/****************************************************************************
+ * Name: board_userled_all
+ ****************************************************************************/
+
+void board_userled_all(uint32_t ledset)
+{
+ bool ledon;
+
+ ledon = ((ledset & BOARD_LED_L_BIT) != 0);
+ ra_gpiowrite(GPIO_L_LED, ledon);
+
+ ledon = ((ledset & BOARD_LED_RX_BIT) != 0);
+ ra_gpiowrite(GPIO_RX_LED, ledon);
+
+ ledon = ((ledset & BOARD_LED_TX_BIT) != 0);
+ ra_gpiowrite(GPIO_TX_LED, ledon);
+}
+
+#endif /* !CONFIG_ARCH_LEDS */