From 6dd28d4e1d3054cb678cbe5e8e4f031d541d25af Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 18 Sep 2024 00:12:41 +0000 Subject: [PATCH] Update revisions ibex 2617c43c [rtl] Fix wrong address in latch RF Cores-VeeR-EL2 ceb5d14c039 Merge pull request #228 from antmicro/63639-use-sis-package-for-coverages 067cc092667 Include documentation 8e86fccc2da Pass project name to doc generator a01e747c536 Bump SiteSpawner 6a815a530f0 Upload documentation and add links c75626c6c95 .github: Remove obsolete coverage related scripts 6f0cd269299 .github: Update workflows to use SIS package fad117bbeb6 tools: Inline SiteSpawner package caliptra-rtl 376eee1 [RTL] Add new AXI modules; standalone module checkin with no integration (#593) --- deps.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps.json b/deps.json index c905676..6e28a6e 100644 --- a/deps.json +++ b/deps.json @@ -1 +1 @@ -{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "53888bcdf4ca3c07e5e715fb6386cb4cc643a61b"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "e2f31eb8019c2e33f4b9b918b33b502be4727bbb"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "0e43b8e7011c1c8761e114bc949fcad6cf30538e"}]} \ No newline at end of file +{"cores": [{"repository_name": "ibex", "repository_url": "https://github.com/lowRISC/ibex", "repository_branch": "master", "repository_revision": "2617c43c0a20cfcd0d9fff86cbd172b8328ae285"}, {"repository_name": "Cores-VeeR-EL2", "repository_url": "https://github.com/chipsalliance/Cores-VeeR-EL2", "repository_branch": "main", "repository_revision": "ceb5d14c039d60fa3f5d4a440113ea7c27608ee2"}, {"repository_name": "caliptra-rtl", "repository_url": "https://github.com/chipsalliance/caliptra-rtl", "repository_branch": "main", "repository_revision": "376eee1debdbc4aa514d20c1d0a43d2ee69d9ba3"}]} \ No newline at end of file