From fe314b4733c23d9ef1524f6ce08333352b365c19 Mon Sep 17 00:00:00 2001 From: Peter Katarzynski Date: Thu, 21 Nov 2024 14:03:38 +0100 Subject: [PATCH] Docs: Update gateware wording Signed-off-by: Peter Katarzynski --- .gitignore | 1 + docs/source/arty.md | 2 +- .../source/build/arty/documentation/index.rst | 37 ----------------- .../documentation/index.rst | 38 ------------------ .../ddr5_test_board/documentation/index.rst | 38 ------------------ .../build/ddr5_tester/documentation/index.rst | 40 ------------------- .../lpddr4_test_board/documentation/index.rst | 37 ----------------- .../build/zcu104/documentation/index.rst | 37 ----------------- docs/source/data_center_rdimm_ddr4_tester.md | 2 +- docs/source/data_center_rdimm_ddr5_tester.md | 2 +- docs/source/general.md | 4 +- docs/source/introduction.md | 2 +- docs/source/lpddr4_test_board.md | 2 +- docs/source/setup.md | 2 +- docs/source/so_dimm_ddr5_tester.md | 2 +- docs/source/zcu104.md | 2 +- 16 files changed, 11 insertions(+), 237 deletions(-) delete mode 100644 docs/source/build/arty/documentation/index.rst delete mode 100644 docs/source/build/ddr4_datacenter_test_board/documentation/index.rst delete mode 100644 docs/source/build/ddr5_test_board/documentation/index.rst delete mode 100644 docs/source/build/ddr5_tester/documentation/index.rst delete mode 100644 docs/source/build/lpddr4_test_board/documentation/index.rst delete mode 100644 docs/source/build/zcu104/documentation/index.rst diff --git a/.gitignore b/.gitignore index 8832510f3..49479b2e0 100644 --- a/.gitignore +++ b/.gitignore @@ -13,3 +13,4 @@ sdram_init.py vivado.* riscv64-unknown-elf-gcc* docs/build +docs/source/build/** diff --git a/docs/source/arty.md b/docs/source/arty.md index 8e8c48efa..07c81a603 100644 --- a/docs/source/arty.md +++ b/docs/source/arty.md @@ -11,7 +11,7 @@ Arty-A7 board The following instructions explain how to set up the board. -For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/arty/documentation/index.rst). +For FPGA digital design documentation for this board, refer to the [Digital design](build/arty/documentation/index.rst) chapter. ## Board configuration diff --git a/docs/source/build/arty/documentation/index.rst b/docs/source/build/arty/documentation/index.rst deleted file mode 100644 index 4c659a2cb..000000000 --- a/docs/source/build/arty/documentation/index.rst +++ /dev/null @@ -1,37 +0,0 @@ -=========================================== -Documentation for Rowhammer Tester Arty-A7 -=========================================== - - - -Modules -======= - -.. toctree:: - :maxdepth: 1 - - interrupts - -Register Groups -=============== - -.. toctree:: - :maxdepth: 1 - - leds - ddrphy - controller_settings - ddrctrl - ethphy - rowhammer - writer - reader - dfi_switch - payload_executor - ctrl - identifier_mem - sdram - sdram_checker - sdram_generator - timer0 - uart diff --git a/docs/source/build/ddr4_datacenter_test_board/documentation/index.rst b/docs/source/build/ddr4_datacenter_test_board/documentation/index.rst deleted file mode 100644 index cc7d73880..000000000 --- a/docs/source/build/ddr4_datacenter_test_board/documentation/index.rst +++ /dev/null @@ -1,38 +0,0 @@ -=========================================================== -Documentation for Rowhammer Tester Data Center DRAM Tester -=========================================================== - - - -Modules -======= - -.. toctree:: - :maxdepth: 1 - - interrupts - -Register Groups -=============== - -.. toctree:: - :maxdepth: 1 - - leds - ddrphy - controller_settings - ddrctrl - rowhammer - writer - reader - dfi_switch - payload_executor - i2c - ctrl - ethphy - identifier_mem - sdram - sdram_checker - sdram_generator - timer0 - uart diff --git a/docs/source/build/ddr5_test_board/documentation/index.rst b/docs/source/build/ddr5_test_board/documentation/index.rst deleted file mode 100644 index fd5ea5432..000000000 --- a/docs/source/build/ddr5_test_board/documentation/index.rst +++ /dev/null @@ -1,38 +0,0 @@ -=================================================== -Documentation for Rowhammer Tester DDR5 Test Board -=================================================== - - - -Modules -======= - -.. toctree:: - :maxdepth: 1 - - interrupts - -Register Groups -=============== - -.. toctree:: - :maxdepth: 1 - - leds - ddrphy - controller_settings - ddrctrl - rowhammer - writer - reader - dfi_switch - payload_executor - ctrl - ethphy - identifier_mem - main - sdram - sdram_checker - sdram_generator - timer0 - uart diff --git a/docs/source/build/ddr5_tester/documentation/index.rst b/docs/source/build/ddr5_tester/documentation/index.rst deleted file mode 100644 index 7882cbf64..000000000 --- a/docs/source/build/ddr5_tester/documentation/index.rst +++ /dev/null @@ -1,40 +0,0 @@ -=============================================== -Documentation for Rowhammer Tester DDR5 Tester -=============================================== - - - -Modules -======= - -.. toctree:: - :maxdepth: 1 - - interrupts - PHYCRG - -Register Groups -=============== - -.. toctree:: - :maxdepth: 1 - - leds - ddrphy - controller_settings - ddrctrl - rowhammer - writer - reader - dfi_switch - payload_executor - i2c - ctrl - ethphy - identifier_mem - main - sdram - sdram_checker - sdram_generator - timer0 - uart diff --git a/docs/source/build/lpddr4_test_board/documentation/index.rst b/docs/source/build/lpddr4_test_board/documentation/index.rst deleted file mode 100644 index e736fac5d..000000000 --- a/docs/source/build/lpddr4_test_board/documentation/index.rst +++ /dev/null @@ -1,37 +0,0 @@ -===================================================== -Documentation for Rowhammer Tester LPDDR4 Test Board -===================================================== - - - -Modules -======= - -.. toctree:: - :maxdepth: 1 - - interrupts - -Register Groups -=============== - -.. toctree:: - :maxdepth: 1 - - leds - ddrphy - controller_settings - ddrctrl - rowhammer - writer - reader - dfi_switch - payload_executor - ctrl - ethphy - identifier_mem - sdram - sdram_checker - sdram_generator - timer0 - uart diff --git a/docs/source/build/zcu104/documentation/index.rst b/docs/source/build/zcu104/documentation/index.rst deleted file mode 100644 index 0335f27c2..000000000 --- a/docs/source/build/zcu104/documentation/index.rst +++ /dev/null @@ -1,37 +0,0 @@ -========================================== -Documentation for Rowhammer Tester ZCU104 -========================================== - - - -Modules -======= - -.. toctree:: - :maxdepth: 1 - - interrupts - -Register Groups -=============== - -.. toctree:: - :maxdepth: 1 - - leds - ddrphy - controller_settings - ddrctrl - rowhammer - writer - reader - dfi_switch - payload_executor - i2c - ctrl - identifier_mem - sdram - sdram_checker - sdram_generator - timer0 - uart diff --git a/docs/source/data_center_rdimm_ddr4_tester.md b/docs/source/data_center_rdimm_ddr4_tester.md index 32dea93f2..52ba9cd63 100644 --- a/docs/source/data_center_rdimm_ddr4_tester.md +++ b/docs/source/data_center_rdimm_ddr4_tester.md @@ -13,7 +13,7 @@ The hardware is open and can be found on GitHub: The following instructions explain how to set up the board. -For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/ddr4_datacenter_test_board/documentation/index.rst). +For FPGA digital design documentation for this board, refer to the [Digital design](build/ddr4_datacenter_test_board/documentation/index.rst) chapter. ## IO map diff --git a/docs/source/data_center_rdimm_ddr5_tester.md b/docs/source/data_center_rdimm_ddr5_tester.md index 3f8f7db91..1fe7c9561 100644 --- a/docs/source/data_center_rdimm_ddr5_tester.md +++ b/docs/source/data_center_rdimm_ddr5_tester.md @@ -9,7 +9,7 @@ The hardware is open and can be found on [GitHub](https://github.com/antmicro/rd The following instructions explain how to set up the board. -For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/ddr5_test_board/documentation/index.rst). +For FPGA digital design documentation for this board, refer to the [Digital design](build/ddr5_test_board/documentation/index.rst) chapter. ## IO map diff --git a/docs/source/general.md b/docs/source/general.md index bdf625695..1e0790eac 100644 --- a/docs/source/general.md +++ b/docs/source/general.md @@ -4,7 +4,7 @@ The aim of this project is to provide a platform for testing [DRAM vulnerability ## Architecture -The setup consists of FPGA gateware and application side software. +The setup consists of FPGA digital design and application side software. The following diagram illustrates the general system architecture. ```{image} ./images/architecture.png @@ -102,7 +102,7 @@ Next time you want to use a bitstream packaged in such way, all you need to do i ## Local documentation build -The gateware part of the documentation is auto-generated from source files. +The digital design part of the documentation is auto-generated from source files. Other files are static and are located in the `doc/` directory. To build the documentation, enter: diff --git a/docs/source/introduction.md b/docs/source/introduction.md index 46ced1fd0..8b32f9c17 100644 --- a/docs/source/introduction.md +++ b/docs/source/introduction.md @@ -69,7 +69,7 @@ The application side consists of a set of Python scripts communicating with the * [Performing attacks (hammering)](hammering.md) - instructions for performing rowhammer attacks, examples, DRAM config guide and Python utility overview * [Result visualization](visualization.md) - instructions for generating plots and visualizations * [Test-writing playbook](playbook.md) - guide for using dedicated Python classes and scripts for writing rowhammer-related tests -* Gateware documentation - FPGA gateware documented per-board: +* Digital design- FPGA digital design documented per-board: * [Arty-A7 board](build/arty/documentation/index.rst) * [LPDDR4 Test Board](build/lpddr4_test_board/documentation/index.rst) * [Data Center RDIMM DDR4 Tester](build/ddr4_datacenter_test_board/documentation/index.rst) diff --git a/docs/source/lpddr4_test_board.md b/docs/source/lpddr4_test_board.md index b97ebe397..ed32d898d 100644 --- a/docs/source/lpddr4_test_board.md +++ b/docs/source/lpddr4_test_board.md @@ -11,7 +11,7 @@ The hardware is open and can be found on GitHub: - Test board: - Testbed: -For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/lpddr4_test_board/documentation/index.rst). +For FPGA digital design documentation for this board, refer to the [Digital design](build/lpddr4_test_board/documentation/index.rst) chapter. ## IO map diff --git a/docs/source/setup.md b/docs/source/setup.md index 46e6b0b8d..752ff2808 100644 --- a/docs/source/setup.md +++ b/docs/source/setup.md @@ -78,7 +78,7 @@ To use a bitstream packaged this way, run `unzip your-bitstream-file.zip`. ## Local documentation build -The gateware part of the documentation is auto-generated from source files. +The part of the documentation related to the ditital design is auto-generated from source files. Other files are static and are located in the `doc/` directory. To build the documentation, enter: diff --git a/docs/source/so_dimm_ddr5_tester.md b/docs/source/so_dimm_ddr5_tester.md index 0af1dd24e..66fef8c50 100644 --- a/docs/source/so_dimm_ddr5_tester.md +++ b/docs/source/so_dimm_ddr5_tester.md @@ -11,7 +11,7 @@ The SO-DIMM DDR5 tester is an open source hardware test platform that enables te The hardware is open and can be found on GitHub: -For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/ddr5_tester/documentation/index.rst). +For FPGA digital design documentation for this board, refer to the [Digital design](build/ddr5_tester/documentation/index.rst) chapter. ## IO map diff --git a/docs/source/zcu104.md b/docs/source/zcu104.md index 429400d6c..a93b822fb 100644 --- a/docs/source/zcu104.md +++ b/docs/source/zcu104.md @@ -15,7 +15,7 @@ A simple EtherBone server is implemented for this purpose (the source code can b The following instructions show how to set up the board for the first time. -For FPGA gateware documentation for this board, refer to the [Gateware Documentation chapter](build/zcu104/documentation/index.rst). +For FPGA design documentation for this board, refer to the [Digital design](build/zcu104/documentation/index.rst) chapter. ## Board configuration