From befa5a083be93565f2e15b7bbb1f56bd0e06c4ab Mon Sep 17 00:00:00 2001 From: Maciej Dudek Date: Tue, 26 Mar 2024 19:34:28 +0100 Subject: [PATCH] Update DDR5 S7CRG Signed-off-by: Maciej Dudek --- rowhammer_tester/targets/ddr5_test_board.py | 14 +++++++++++--- rowhammer_tester/targets/ddr5_tester.py | 14 +++++++++++--- rowhammer_tester/targets/sodimm_ddr5_tester.py | 14 +++++++++++--- third_party/litedram | 2 +- 4 files changed, 34 insertions(+), 10 deletions(-) diff --git a/rowhammer_tester/targets/ddr5_test_board.py b/rowhammer_tester/targets/ddr5_test_board.py index 80d6c27f6..c74e2c85d 100644 --- a/rowhammer_tester/targets/ddr5_test_board.py +++ b/rowhammer_tester/targets/ddr5_test_board.py @@ -135,7 +135,8 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq): # BUFMR to BUFR and BUFIO, "raw" clocks self.clock_domains.cd_sys4x_raw = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_90_raw = ClockDomain(reset_less=True) - # BUFMR reset domain + # BUFMR reset domains + self.clock_domains.cd_sys2x_rst = ClockDomain() self.clock_domains.cd_sys2x_90_rst = ClockDomain() # # # @@ -160,6 +161,13 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq): buf=None, platform=platform ) + mmcm.create_clkout( + self.cd_sys2x_rst, + 2 * sys_clk_freq, + clock_out = 0, + div = 2, + buf = 'bufr', + ) mmcm.create_clkout( self.cd_sys2x_90_rst, 2 * sys_clk_freq, @@ -167,7 +175,6 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq): div = 2, phase = 90, buf = 'bufr', - name = 'rst_domain', ) mmcm.create_clkout(self.cd_sys, sys_clk_freq) @@ -208,7 +215,8 @@ def get_ddr_pin_domains(self): def get_ddrphy(self): PHYCRG = ddr5.S7PHYCRG( - reset_clock_domain = "sys2x_90_rst", + reset_clock_domain = "sys2x_rst", + reset_clock_90_domain = "sys2x_90_rst", source_4x = ClockSignal("sys4x_raw"), source_4x_90 = ClockSignal("sys4x_90_raw"), ) diff --git a/rowhammer_tester/targets/ddr5_tester.py b/rowhammer_tester/targets/ddr5_tester.py index b8da4138f..35ec0340f 100644 --- a/rowhammer_tester/targets/ddr5_tester.py +++ b/rowhammer_tester/targets/ddr5_tester.py @@ -29,7 +29,8 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq): # BUFMR to BUFR and BUFIO, "raw" clocks self.clock_domains.cd_sys4x_raw = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_90_raw = ClockDomain(reset_less=True) - # BUFMR reset domain + # BUFMR reset domains + self.clock_domains.cd_sys2x_rst = ClockDomain() self.clock_domains.cd_sys2x_90_rst = ClockDomain() # # # @@ -53,6 +54,13 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq): with_reset=False, buf=None, ) + mmcm.create_clkout( + self.cd_sys2x_rst, + 2 * sys_clk_freq, + clock_out = 0, + div = 2, + buf = 'bufr', + ) mmcm.create_clkout( self.cd_sys2x_90_rst, 2 * sys_clk_freq, @@ -60,7 +68,6 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq): div = 2, phase = 90, buf = 'bufr', - name = "rst_domain", ) mmcm.create_clkout(self.cd_sys, sys_clk_freq) @@ -128,7 +135,8 @@ def get_ddr_pin_domains(self): def get_ddrphy(self): PHYCRG = ddr5.S7PHYCRG( - reset_clock_domain = "sys2x_90_rst", + reset_clock_domain = "sys2x_rst", + reset_clock_90_domain = "sys2x_90_rst", source_4x = ClockSignal("sys4x_raw"), source_4x_90 = ClockSignal("sys4x_90_raw"), ) diff --git a/rowhammer_tester/targets/sodimm_ddr5_tester.py b/rowhammer_tester/targets/sodimm_ddr5_tester.py index 51acb9974..48dab0078 100644 --- a/rowhammer_tester/targets/sodimm_ddr5_tester.py +++ b/rowhammer_tester/targets/sodimm_ddr5_tester.py @@ -30,7 +30,8 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq): # BUFMR to BUFR and BUFIO, "raw" clocks self.clock_domains.cd_sys4x_raw = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_90_raw = ClockDomain(reset_less=True) - # BUFMR reset domain + # BUFMR reset domains + self.clock_domains.cd_sys2x_rst = ClockDomain() self.clock_domains.cd_sys2x_90_rst = ClockDomain() # # # @@ -54,6 +55,13 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq): with_reset=False, buf=None, ) + mmcm.create_clkout( + self.cd_sys2x_rst, + 2 * sys_clk_freq, + clock_out = 0, + div = 2, + buf = 'bufr', + ) mmcm.create_clkout( self.cd_sys2x_90_rst, 2 * sys_clk_freq, @@ -61,7 +69,6 @@ def __init__(self, platform, sys_clk_freq, iodelay_clk_freq): div = 2, phase = 90, buf = 'bufr', - name = "rst_domain", ) mmcm.create_clkout(self.cd_sys, sys_clk_freq) @@ -217,7 +224,8 @@ def get_ddr_pin_domains(self): def get_ddrphy(self): PHYCRG = ddr5.S7PHYCRG( - reset_clock_domain = "sys2x_90_rst", + reset_clock_domain = "sys2x_rst", + reset_clock_90_domain = "sys2x_90_rst", source_4x = ClockSignal("sys4x_raw"), source_4x_90 = ClockSignal("sys4x_90_raw"), ) diff --git a/third_party/litedram b/third_party/litedram index 08d535ff0..a107d940e 160000 --- a/third_party/litedram +++ b/third_party/litedram @@ -1 +1 @@ -Subproject commit 08d535ff05525a6ee77d2974e83f4ee00c62fcd1 +Subproject commit a107d940e4bab5a0bf6994f06e2c5ffa0acf7508