From 014ca5ea07b7496a1d89fbb7ccb9e74e2050315a Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Mon, 17 Jun 2024 13:49:11 -0700 Subject: [PATCH 1/5] Use global_place_skip_io with HAS_IO_CONSTRAINTS Skipping global_place_skip_io can lead to worse placement. Signed-off-by: Matt Liberty --- flow/scripts/global_place_skip_io.tcl | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/flow/scripts/global_place_skip_io.tcl b/flow/scripts/global_place_skip_io.tcl index 1381de7ee0..93bdee69e3 100644 --- a/flow/scripts/global_place_skip_io.tcl +++ b/flow/scripts/global_place_skip_io.tcl @@ -1,28 +1,8 @@ source $::env(SCRIPTS_DIR)/load.tcl load_design 2_floorplan.odb 2_floorplan.sdc -if { - [info exists ::env(FLOORPLAN_DEF)] || - ( - [info exists ::env(HAS_IO_CONSTRAINTS)] && - $::env(HAS_IO_CONSTRAINTS) == 1 - ) || - ( - [info exists ::env(IO_CONSTRAINTS)] && - ( - [info exists ::env(HAS_IO_CONSTRAINTS)] == 0 || - $::env(HAS_IO_CONSTRAINTS) == 1 - ) - ) || - ( - $::env(PLACE_PINS_ARGS) != "" && - ( - [info exists ::env(HAS_IO_CONSTRAINTS)] == 0 || - $::env(HAS_IO_CONSTRAINTS) == 1 - ) - ) -} { - puts "Has top down IO Constraints. Skip global placement without IOs" +if { [info exists ::env(FLOORPLAN_DEF)] } { + puts "FLOORPLAN_DEF is set. Skipping global placement without IOs" } else { # check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists if {[info exist ::env(PLACE_DENSITY_LB_ADDON)]} { From d0a22433f7823161fc4d591f694b073ca20b918f Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Sun, 21 Jul 2024 19:04:36 -0700 Subject: [PATCH 2/5] update gf180/jpeg for do gpl wtih io constraints | Metric | Old | New | Type | | ------ | --- | --- | ---- | | detailedroute__antenna__violating__nets | 0 | 1 | Failing | | finish__timing__setup__ws | -1.22 | -1.2 | Tighten | Signed-off-by: Matt Liberty --- flow/designs/gf180/jpeg/metadata-base-ok.json | 412 +++++++++--------- flow/designs/gf180/jpeg/rules-base.json | 4 +- 2 files changed, 205 insertions(+), 211 deletions(-) diff --git a/flow/designs/gf180/jpeg/metadata-base-ok.json b/flow/designs/gf180/jpeg/metadata-base-ok.json index 58b3610f1b..5e65d4fb7e 100644 --- a/flow/designs/gf180/jpeg/metadata-base-ok.json +++ b/flow/designs/gf180/jpeg/metadata-base-ok.json @@ -3,283 +3,277 @@ "constraints__clocks__details": [ "clk: 8.0000" ], - "cts__clock__skew__hold": 0.151832, - "cts__clock__skew__setup": 0.151832, - "cts__cpu__total": 50.82, - "cts__design__core__area": 4904090.0, - "cts__design__die__area": 4922830.0, - "cts__design__instance__area": 2290760.0, + "cts__clock__skew__hold": 0.157891, + "cts__clock__skew__setup": 0.157891, + "cts__cpu__total": 35.84, + "cts__design__core__area": 4911530.0, + "cts__design__die__area": 4938640.0, + "cts__design__instance__area": 2317170.0, "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 2290760.0, - "cts__design__instance__count": 55714, + "cts__design__instance__area__stdcell": 2317170.0, + "cts__design__instance__count": 54950, "cts__design__instance__count__hold_buffer": 0, "cts__design__instance__count__macros": 0, "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 55714, + "cts__design__instance__count__stdcell": 54950, "cts__design__instance__displacement__max": 0, "cts__design__instance__displacement__mean": 0, "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.467111, - "cts__design__instance__utilization__stdcell": 0.467111, + "cts__design__instance__utilization": 0.471781, + "cts__design__instance__utilization__stdcell": 0.471781, "cts__design__io": 47, "cts__design__violations": 0, "cts__flow__errors__count": 0, "cts__flow__warnings__count": 0, - "cts__mem__peak": 506156.0, - "cts__power__internal__total": 10.7118, - "cts__power__leakage__total": 1.3233e-05, - "cts__power__switching__total": 4.7395, - "cts__power__total": 15.4513, - "cts__route__wirelength__estimated": 2364700.0, - "cts__runtime__total": "0:51.19", + "cts__mem__peak": 515592.0, + "cts__power__internal__total": 9.90263, + "cts__power__leakage__total": 1.32716e-05, + "cts__power__switching__total": 4.46341, + "cts__power__total": 14.3661, + "cts__route__wirelength__estimated": 2354500.0, + "cts__runtime__total": "0:36.20", "cts__timing__drv__hold_violation_count": 0, "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.896676, + "cts__timing__drv__max_cap_limit": 0.899272, "cts__timing__drv__max_fanout": 0, "cts__timing__drv__max_fanout_limit": 0, "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.425532, + "cts__timing__drv__max_slew_limit": 0.507252, "cts__timing__drv__setup_violation_count": 0, "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 0.23565, - "design__io__hpwl": 105955860, - "detailedplace__cpu__total": 49.28, - "detailedplace__design__core__area": 4904090.0, - "detailedplace__design__die__area": 4922830.0, - "detailedplace__design__instance__area": 2274270.0, + "cts__timing__setup__ws": 0.268551, + "design__io__hpwl": 55546992, + "detailedplace__cpu__total": 37.36, + "detailedplace__design__core__area": 4911530.0, + "detailedplace__design__die__area": 4938640.0, + "detailedplace__design__instance__area": 2300000.0, "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 2274270.0, - "detailedplace__design__instance__count": 55429, + "detailedplace__design__instance__area__stdcell": 2300000.0, + "detailedplace__design__instance__count": 54665, "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 55429, - "detailedplace__design__instance__displacement__max": 49.84, - "detailedplace__design__instance__displacement__mean": 4.325, - "detailedplace__design__instance__displacement__total": 239732, - "detailedplace__design__instance__utilization": 0.463749, - "detailedplace__design__instance__utilization__stdcell": 0.463749, + "detailedplace__design__instance__count__stdcell": 54665, + "detailedplace__design__instance__displacement__max": 34.16, + "detailedplace__design__instance__displacement__mean": 4.472, + "detailedplace__design__instance__displacement__total": 244471, + "detailedplace__design__instance__utilization": 0.468286, + "detailedplace__design__instance__utilization__stdcell": 0.468286, "detailedplace__design__io": 47, "detailedplace__design__violations": 0, "detailedplace__flow__errors__count": 0, "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 471404.0, - "detailedplace__power__internal__total": 10.56, - "detailedplace__power__leakage__total": 1.31326e-05, - "detailedplace__power__switching__total": 4.62433, - "detailedplace__power__total": 15.1843, - "detailedplace__route__wirelength__estimated": 2362740.0, - "detailedplace__runtime__total": "0:49.61", + "detailedplace__mem__peak": 493720.0, + "detailedplace__power__internal__total": 9.74579, + "detailedplace__power__leakage__total": 1.31673e-05, + "detailedplace__power__switching__total": 4.34817, + "detailedplace__power__total": 14.094, + "detailedplace__route__wirelength__estimated": 2353870.0, + "detailedplace__runtime__total": "0:37.68", "detailedplace__timing__drv__hold_violation_count": 0, "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.896676, + "detailedplace__timing__drv__max_cap_limit": 0.899315, "detailedplace__timing__drv__max_fanout": 0, "detailedplace__timing__drv__max_fanout_limit": 0, "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.426487, + "detailedplace__timing__drv__max_slew_limit": 0.507687, "detailedplace__timing__drv__setup_violation_count": 0, "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 0.33684, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__cpu__total": 3616.25, + "detailedplace__timing__setup__ws": 0.368845, + "detailedroute__antenna__violating__nets": 1, + "detailedroute__antenna__violating__pins": 1, + "detailedroute__cpu__total": 1763.7, "detailedroute__flow__errors__count": 0, "detailedroute__flow__warnings__count": 8, - "detailedroute__mem__peak": 3028368.0, + "detailedroute__mem__peak": 3919356.0, "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 14785, - "detailedroute__route__drc_errors__iter:10": 0, - "detailedroute__route__drc_errors__iter:2": 381, - "detailedroute__route__drc_errors__iter:3": 165, - "detailedroute__route__drc_errors__iter:4": 5, - "detailedroute__route__drc_errors__iter:5": 3, - "detailedroute__route__drc_errors__iter:6": 2, - "detailedroute__route__drc_errors__iter:7": 1, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 1, - "detailedroute__route__net": 61332, + "detailedroute__route__drc_errors__iter:1": 8614, + "detailedroute__route__drc_errors__iter:2": 327, + "detailedroute__route__drc_errors__iter:3": 127, + "detailedroute__route__drc_errors__iter:4": 2, + "detailedroute__route__drc_errors__iter:5": 1, + "detailedroute__route__drc_errors__iter:6": 1, + "detailedroute__route__drc_errors__iter:7": 0, + "detailedroute__route__net": 60877, "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 315176, + "detailedroute__route__vias": 313583, "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 315176, - "detailedroute__route__wirelength": 2717236, - "detailedroute__route__wirelength__iter:1": 2733314, - "detailedroute__route__wirelength__iter:10": 2717236, - "detailedroute__route__wirelength__iter:2": 2718257, - "detailedroute__route__wirelength__iter:3": 2717324, - "detailedroute__route__wirelength__iter:4": 2717231, - "detailedroute__route__wirelength__iter:5": 2717235, - "detailedroute__route__wirelength__iter:6": 2717239, - "detailedroute__route__wirelength__iter:7": 2717230, - "detailedroute__route__wirelength__iter:8": 2717232, - "detailedroute__route__wirelength__iter:9": 2717232, - "detailedroute__runtime__total": "3:14.70", - "fillcell__cpu__total": 2.86, - "fillcell__mem__peak": 348024.0, - "fillcell__runtime__total": "0:03.10", - "finish__clock__skew__hold": 0.250193, - "finish__clock__skew__setup": 0.250193, - "finish__cpu__total": 72.68, - "finish__design__core__area": 4904090.0, - "finish__design__die__area": 4922830.0, - "finish__design__instance__area": 2290830.0, + "detailedroute__route__vias__singlecut": 313583, + "detailedroute__route__wirelength": 2702676, + "detailedroute__route__wirelength__iter:1": 2716203, + "detailedroute__route__wirelength__iter:2": 2703040, + "detailedroute__route__wirelength__iter:3": 2702704, + "detailedroute__route__wirelength__iter:4": 2702678, + "detailedroute__route__wirelength__iter:5": 2702671, + "detailedroute__route__wirelength__iter:6": 2702672, + "detailedroute__route__wirelength__iter:7": 2702676, + "detailedroute__runtime__total": "1:36.90", + "fillcell__cpu__total": 1.83, + "fillcell__mem__peak": 371072.0, + "fillcell__runtime__total": "0:02.14", + "finish__clock__skew__hold": 0.182302, + "finish__clock__skew__setup": 0.182302, + "finish__cpu__total": 46.84, + "finish__design__core__area": 4911530.0, + "finish__design__die__area": 4938640.0, + "finish__design__instance__area": 2317220.0, "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 2290830.0, - "finish__design__instance__count": 55726, + "finish__design__instance__area__stdcell": 2317220.0, + "finish__design__instance__count": 54959, "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 55726, - "finish__design__instance__utilization": 0.467125, - "finish__design__instance__utilization__stdcell": 0.467125, + "finish__design__instance__count__stdcell": 54959, + "finish__design__instance__utilization": 0.471792, + "finish__design__instance__utilization__stdcell": 0.471792, "finish__design__io": 47, "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 1763084.0, - "finish__power__internal__total": 10.8294, - "finish__power__leakage__total": 1.84397e-05, - "finish__power__switching__total": 5.90571, - "finish__power__total": 16.7351, - "finish__runtime__total": "1:13.63", - "finish__timing__drv__hold_violation_count": 57, + "finish__flow__warnings__count": 1, + "finish__mem__peak": 915904.0, + "finish__power__internal__total": 10.0046, + "finish__power__leakage__total": 1.84433e-05, + "finish__power__switching__total": 5.76659, + "finish__power__total": 15.7712, + "finish__runtime__total": "0:47.85", + "finish__timing__drv__hold_violation_count": 63, "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.751185, + "finish__timing__drv__max_cap_limit": 0.600497, "finish__timing__drv__max_fanout": 0, "finish__timing__drv__max_fanout_limit": 0, "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.255012, - "finish__timing__drv__setup_violation_count": 171, - "finish__timing__setup__tns": -55.1493, - "finish__timing__setup__ws": -0.84711, - "finish__timing__wns_percent_delay": -8.231624, - "finish_merge__cpu__total": 236.76, - "finish_merge__mem__peak": 821500.0, - "finish_merge__runtime__total": "3:57.48", - "floorplan__cpu__total": 23.86, - "floorplan__design__core__area": 4904090.0, - "floorplan__design__die__area": 4922830.0, - "floorplan__design__instance__area": 2183380.0, + "finish__timing__drv__max_slew_limit": 0.289329, + "finish__timing__drv__setup_violation_count": 123, + "finish__timing__setup__tns": -29.284, + "finish__timing__setup__ws": -0.808829, + "finish__timing__wns_percent_delay": -7.862121, + "finish_merge__cpu__total": 144.4, + "finish_merge__mem__peak": 981372.0, + "finish_merge__runtime__total": "2:25.04", + "floorplan__cpu__total": 15.35, + "floorplan__design__core__area": 4911530.0, + "floorplan__design__die__area": 4938640.0, + "floorplan__design__instance__area": 2190120.0, "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 2183380.0, - "floorplan__design__instance__count": 49523, + "floorplan__design__instance__area__stdcell": 2190120.0, + "floorplan__design__instance__count": 48744, "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 49523, - "floorplan__design__instance__utilization": 0.445215, - "floorplan__design__instance__utilization__stdcell": 0.445215, + "floorplan__design__instance__count__stdcell": 48744, + "floorplan__design__instance__utilization": 0.445914, + "floorplan__design__instance__utilization__stdcell": 0.445914, "floorplan__design__io": 47, "floorplan__flow__errors__count": 0, "floorplan__flow__warnings__count": 1, - "floorplan__mem__peak": 294316.0, - "floorplan__power__internal__total": 11.6359, - "floorplan__power__leakage__total": 1.2459e-05, - "floorplan__power__switching__total": 4.38728, - "floorplan__power__total": 16.0232, - "floorplan__runtime__total": "0:24.02", - "floorplan__timing__setup__tns": -75301, - "floorplan__timing__setup__ws": -52.4731, - "floorplan_io__cpu__total": 1.19, - "floorplan_io__mem__peak": 171316.0, - "floorplan_io__runtime__total": "0:01.30", - "floorplan_macro__cpu__total": 1.22, - "floorplan_macro__mem__peak": 170528.0, - "floorplan_macro__runtime__total": "0:01.34", - "floorplan_pdn__cpu__total": 13.38, - "floorplan_pdn__mem__peak": 252096.0, - "floorplan_pdn__runtime__total": "0:13.55", - "floorplan_tap__cpu__total": 1.45, - "floorplan_tap__mem__peak": 142064.0, - "floorplan_tap__runtime__total": "0:01.53", - "floorplan_tdms__cpu__total": 1.24, - "floorplan_tdms__mem__peak": 169380.0, - "floorplan_tdms__runtime__total": "0:01.34", + "floorplan__mem__peak": 315048.0, + "floorplan__power__internal__total": 11.5019, + "floorplan__power__leakage__total": 1.24065e-05, + "floorplan__power__switching__total": 4.05001, + "floorplan__power__total": 15.5519, + "floorplan__runtime__total": "0:15.55", + "floorplan__timing__setup__tns": -89237.5, + "floorplan__timing__setup__ws": -70.0299, + "floorplan_io__cpu__total": 0.81, + "floorplan_io__mem__peak": 193148.0, + "floorplan_io__runtime__total": "0:00.94", + "floorplan_macro__cpu__total": 0.82, + "floorplan_macro__mem__peak": 192984.0, + "floorplan_macro__runtime__total": "0:00.96", + "floorplan_pdn__cpu__total": 6.38, + "floorplan_pdn__mem__peak": 273620.0, + "floorplan_pdn__runtime__total": "0:06.66", + "floorplan_tap__cpu__total": 1.06, + "floorplan_tap__mem__peak": 164736.0, + "floorplan_tap__runtime__total": "0:01.14", + "floorplan_tdms__cpu__total": 0.86, + "floorplan_tdms__mem__peak": 191612.0, + "floorplan_tdms__runtime__total": "0:00.94", "flow__errors__count": 0, "flow__warnings__count": 0, - "globalplace__cpu__total": 296.07, - "globalplace__design__core__area": 4904090.0, - "globalplace__design__die__area": 4922830.0, - "globalplace__design__instance__area": 2215720.0, + "globalplace__cpu__total": 219.63, + "globalplace__design__core__area": 4911530.0, + "globalplace__design__die__area": 4938640.0, + "globalplace__design__instance__area": 2222460.0, "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 2215720.0, - "globalplace__design__instance__count": 55252, + "globalplace__design__instance__area__stdcell": 2222460.0, + "globalplace__design__instance__count": 54473, "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 55252, - "globalplace__design__instance__utilization": 0.451809, - "globalplace__design__instance__utilization__stdcell": 0.451809, + "globalplace__design__instance__count__stdcell": 54473, + "globalplace__design__instance__utilization": 0.452498, + "globalplace__design__instance__utilization__stdcell": 0.452498, "globalplace__design__io": 47, "globalplace__flow__errors__count": 0, "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 646936.0, - "globalplace__power__internal__total": 12.0069, - "globalplace__power__leakage__total": 1.28076e-05, - "globalplace__power__switching__total": 4.47774, - "globalplace__power__total": 16.4846, - "globalplace__runtime__total": "4:06.80", - "globalplace__timing__setup__tns": -81355.5, - "globalplace__timing__setup__ws": -55.0247, - "globalplace_io__cpu__total": 1.93, - "globalplace_io__mem__peak": 243936.0, - "globalplace_io__runtime__total": "0:02.12", - "globalplace_skip_io__cpu__total": 1.73, - "globalplace_skip_io__mem__peak": 209344.0, - "globalplace_skip_io__runtime__total": "0:01.88", + "globalplace__mem__peak": 670068.0, + "globalplace__power__internal__total": 12.7843, + "globalplace__power__leakage__total": 1.2755e-05, + "globalplace__power__switching__total": 4.15352, + "globalplace__power__total": 16.9379, + "globalplace__runtime__total": "2:52.03", + "globalplace__timing__setup__tns": -78964.1, + "globalplace__timing__setup__ws": -50.2657, + "globalplace_io__cpu__total": 1.34, + "globalplace_io__mem__peak": 266844.0, + "globalplace_io__runtime__total": "0:01.53", + "globalplace_skip_io__cpu__total": 15.82, + "globalplace_skip_io__mem__peak": 345224.0, + "globalplace_skip_io__runtime__total": "0:16.13", "globalroute__antenna__violating__nets": 0, "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.161063, - "globalroute__clock__skew__setup": 0.161063, - "globalroute__cpu__total": 739.22, - "globalroute__design__core__area": 4904090.0, - "globalroute__design__die__area": 4922830.0, - "globalroute__design__instance__area": 2290830.0, + "globalroute__clock__skew__hold": 0.156915, + "globalroute__clock__skew__setup": 0.156915, + "globalroute__cpu__total": 269.21, + "globalroute__design__core__area": 4911530.0, + "globalroute__design__die__area": 4938640.0, + "globalroute__design__instance__area": 2317220.0, "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 2290830.0, - "globalroute__design__instance__count": 55726, + "globalroute__design__instance__area__stdcell": 2317220.0, + "globalroute__design__instance__count": 54959, "globalroute__design__instance__count__hold_buffer": 0, "globalroute__design__instance__count__macros": 0, "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 55726, + "globalroute__design__instance__count__stdcell": 54959, "globalroute__design__instance__displacement__max": 0, "globalroute__design__instance__displacement__mean": 0, "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.467125, - "globalroute__design__instance__utilization__stdcell": 0.467125, + "globalroute__design__instance__utilization": 0.471792, + "globalroute__design__instance__utilization__stdcell": 0.471792, "globalroute__design__io": 47, "globalroute__design__violations": 0, "globalroute__flow__errors__count": 0, "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 1536360.0, - "globalroute__power__internal__total": 10.7175, - "globalroute__power__leakage__total": 1.32349e-05, - "globalroute__power__switching__total": 4.78071, - "globalroute__power__total": 15.4982, - "globalroute__route__wirelength__estimated": 2364700.0, - "globalroute__runtime__total": "1:20.26", - "globalroute__timing__clock__slack": 0.132, + "globalroute__mem__peak": 2192508.0, + "globalroute__power__internal__total": 9.91065, + "globalroute__power__leakage__total": 1.32729e-05, + "globalroute__power__switching__total": 4.50378, + "globalroute__power__total": 14.4144, + "globalroute__route__wirelength__estimated": 2354500.0, + "globalroute__runtime__total": "0:56.10", + "globalroute__timing__clock__slack": 0.183, "globalroute__timing__drv__hold_violation_count": 0, "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.896294, + "globalroute__timing__drv__max_cap_limit": 0.898154, "globalroute__timing__drv__max_fanout": 0, "globalroute__timing__drv__max_fanout_limit": 0, "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.426204, + "globalroute__timing__drv__max_slew_limit": 0.465174, "globalroute__timing__drv__setup_violation_count": 0, "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 0.131652, - "placeopt__cpu__total": 46.98, - "placeopt__design__core__area": 4904090.0, - "placeopt__design__die__area": 4922830.0, - "placeopt__design__instance__area": 2274270.0, + "globalroute__timing__setup__ws": 0.183131, + "placeopt__cpu__total": 35.53, + "placeopt__design__core__area": 4911530.0, + "placeopt__design__die__area": 4938640.0, + "placeopt__design__instance__area": 2300000.0, "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 2274270.0, - "placeopt__design__instance__count": 55429, + "placeopt__design__instance__area__stdcell": 2300000.0, + "placeopt__design__instance__count": 54665, "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 55429, - "placeopt__design__instance__utilization": 0.463749, - "placeopt__design__instance__utilization__stdcell": 0.463749, + "placeopt__design__instance__count__stdcell": 54665, + "placeopt__design__instance__utilization": 0.468286, + "placeopt__design__instance__utilization__stdcell": 0.468286, "placeopt__design__io": 47, "placeopt__flow__errors__count": 0, "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 433500.0, - "placeopt__power__internal__total": 10.5593, - "placeopt__power__leakage__total": 1.31326e-05, - "placeopt__power__switching__total": 4.62025, - "placeopt__power__total": 15.1795, - "placeopt__runtime__total": "0:47.31", + "placeopt__mem__peak": 439424.0, + "placeopt__power__internal__total": 9.74557, + "placeopt__power__leakage__total": 1.31673e-05, + "placeopt__power__switching__total": 4.34332, + "placeopt__power__total": 14.0889, + "placeopt__runtime__total": "0:35.87", "placeopt__timing__drv__floating__nets": 0, "placeopt__timing__drv__floating__pins": 0, "placeopt__timing__drv__hold_violation_count": 0, @@ -288,15 +282,15 @@ "placeopt__timing__drv__max_fanout": 0, "placeopt__timing__drv__max_fanout_limit": 0, "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.427843, + "placeopt__timing__drv__max_slew_limit": 0.508074, "placeopt__timing__drv__setup_violation_count": 0, "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 0.342945, + "placeopt__timing__setup__ws": 0.364101, "run__flow__design": "jpeg", - "run__flow__generate_date": "2024-06-20 21:49", + "run__flow__generate_date": "2024-07-21 23:10", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-14264-g08c19394f", + "run__flow__openroad_version": "v2.0-14670-g55e1e16cc", "run__flow__platform": "gf180", "run__flow__platform__capacitance_units": "1pF", "run__flow__platform__current_units": "1mA", @@ -305,14 +299,14 @@ "run__flow__platform__resistance_units": "1ohm", "run__flow__platform__time_units": "1ns", "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "6f711638d045b4c662d1d39712c6018e7127f3c9", - "run__flow__scripts_commit": "6f711638d045b4c662d1d39712c6018e7127f3c9", - "run__flow__uuid": "b60422cd-669d-4d8f-b4b3-77eb7eacbe63", + "run__flow__platform_commit": "N/A", + "run__flow__scripts_commit": "not a git repo", + "run__flow__uuid": "e9921bb6-47a7-4909-b0ec-2efd94ea7649", "run__flow__variant": "base", - "synth__cpu__total": 212.75, - "synth__design__instance__area__stdcell": 2211282.6624, - "synth__design__instance__count__stdcell": 50756.0, - "synth__mem__peak": 735172.0, - "synth__runtime__total": "3:34.14", - "total_time": "0:20:45.300000" + "synth__cpu__total": 105.63, + "synth__design__instance__area__stdcell": 2218389.4656, + "synth__design__instance__count__stdcell": 49993.0, + "synth__mem__peak": 743840.0, + "synth__runtime__total": "1:46.66", + "total_time": "0:13:00.320000" } \ No newline at end of file diff --git a/flow/designs/gf180/jpeg/rules-base.json b/flow/designs/gf180/jpeg/rules-base.json index fc595d1799..3f9b00ede1 100644 --- a/flow/designs/gf180/jpeg/rules-base.json +++ b/flow/designs/gf180/jpeg/rules-base.json @@ -36,11 +36,11 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 0, + "value": 1, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.22, + "value": -1.2, "compare": ">=" }, "finish__design__instance__area": { From 9d10b78f1e49325cfd59c3b366321aa19d0721a4 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Mon, 29 Jul 2024 06:45:48 -0700 Subject: [PATCH 3/5] update OR Signed-off-by: Matt Liberty --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index 27e1eab05a..d33426ce1e 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 27e1eab05a291dfb6e9e42018e48afe9248c083d +Subproject commit d33426ce1e06bc46f73c881b81ec55099e5540ec From db65df42f49abf54c6f2718bc7d6fb34e7c29f2f Mon Sep 17 00:00:00 2001 From: habibayassin Date: Mon, 29 Jul 2024 20:47:33 +0300 Subject: [PATCH 4/5] gha: trigger update rules manually (#2200) * manual workflow to update rules Signed-off-by: habibayassin Signed-off-by: Vitor Bandeira Co-authored-by: Vitor Bandeira --- .../github-actions-manual-update-rules.yml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 .github/workflows/github-actions-manual-update-rules.yml diff --git a/.github/workflows/github-actions-manual-update-rules.yml b/.github/workflows/github-actions-manual-update-rules.yml new file mode 100644 index 0000000000..fc10dae30d --- /dev/null +++ b/.github/workflows/github-actions-manual-update-rules.yml @@ -0,0 +1,52 @@ +name: Manually Trigger Update Rules +on: + workflow_dispatch: + inputs: + type: + description: 'Type of update (overwrite or normal)' + required: true + default: 'normal' + +jobs: + update: + runs-on: ubuntu-latest + strategy: + fail-fast: false + steps: + - name: Check out repository code recursively + uses: actions/checkout@v3 + with: + fetch-depth: 0 + - uses: actions/setup-python@v4 + with: + python-version: "3.10" + - name: Install Python Packages + run: | + pip install firebase-admin + - name: Execute Python Script Update + env: + CREDS_FILE: ${{ secrets.CREDS_FILE }} + API_BASE_URL: ${{ secrets.API_BASE_URL }} + run: | + if [[ "${{ github.event.inputs.type }}" == "overwrite" ]]; then + python flow/util/updateRules.py --keyFile "${CREDS_FILE}" --apiURL ${API_BASE_URL} --commitSHA $(git rev-parse HEAD) --overwrite + else + python flow/util/updateRules.py --keyFile "${CREDS_FILE}" --apiURL ${API_BASE_URL} --commitSHA $(git rev-parse HEAD) + fi + - name: Push updated rules + id: remote-update + run: | + git config --local user.email "github-actions[bot]@users.noreply.github.com" + git config --local user.name "github-actions[bot]" + if [ -n "$(git status --porcelain)" ]; then + echo "has_update=true" >> "$GITHUB_OUTPUT" + else + echo "has_update=false" >> "$GITHUB_OUTPUT" + fi + git add . + git commit --signoff -m "flow: update rules based on new golden reference" + - if: "steps.remote-update.outputs.has_update == 'true'" + name: update rules pr + id: remote-update-pr + run: | + git push From 396f35447b79e76ef7969caddc72e201bb8ff0fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 30 Jul 2024 07:51:41 +0200 Subject: [PATCH 5/5] sky130ram: delete log files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I think these are log files, the Python syntax is invalid(fails with black .) Signed-off-by: Øyvind Harboe --- .../sky130_sram_1rw1r_128x256_8.log | 160 ----------------- .../sky130_sram_1rw1r_128x256_8_extended.py | 88 ---------- .../sky130_sram_1rw1r_44x64_8.log | 158 ----------------- .../sky130_sram_1rw1r_44x64_8_extended.py | 88 ---------- .../sky130_sram_1rw1r_64x256_8.log | 163 ------------------ .../sky130_sram_1rw1r_64x256_8_extended.py | 88 ---------- .../sky130_sram_1rw1r_80x64_8.log | 158 ----------------- .../sky130_sram_1rw1r_80x64_8_extended.py | 88 ---------- 8 files changed, 991 deletions(-) delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.log delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_extended.py delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.log delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_extended.py delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.log delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_extended.py delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.log delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_extended.py diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.log b/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.log deleted file mode 100644 index 2fdf89c9c8..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.log +++ /dev/null @@ -1,160 +0,0 @@ -[globals/init_openram]: Initializing OpenRAM... -[globals/setup_paths]: Temporary files saved in /tmp/openram_wbduan_23636_temp/ -[globals/read_config]: Configuration file is /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_128x256_8.py -[globals/read_config]: Output saved in /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/ -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/third_party/OpenRAM/technology -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology -[globals/init_paths]: Creating temp directory: /tmp/openram_wbduan_23636_temp/ -[globals/setup_bitcell]: Using bitcell: bitcell_2port -[characterizer/]: Initializing characterizer... -[characterizer/]: Analytical model enabled. -[verify/]: Initializing verify... -[verify/]: LVS/DRC/PEX disabled. -[globals/setup_bitcell]: Using bitcell: bitcell_2port -|==============================================================================| -|========= OpenRAM v1.1.6 =========| -|========= =========| -|========= VLSI Design and Automation Lab =========| -|========= Computer Science and Engineering Department =========| -|========= University of California Santa Cruz =========| -|========= =========| -|========= Usage help: openram-user-group@ucsc.edu =========| -|========= Development help: openram-dev-group@ucsc.edu =========| -|========= Temp dir: /tmp/openram_wbduan_23636_temp/ =========| -|========= See LICENSE for license info =========| -|==============================================================================| -** Start: 11/25/2020 16:57:40 -Technology: sky130 -Total size: 32768 bits -WARNING: file globals.py: line 571: Requesting such a large memory size (32768) will have a large run-time. Consider using multiple smaller banks. - -Word size: 128 -Words: 256 -Banks: 1 -Write size: 8 -RW ports: 1 -R-only ports: 1 -W-only ports: 0 -Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing). -DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). -DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). -Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). -Only generating nominal corner timing. -[sram_config/recompute_sizes]: Recomputing with words per row: 1 -[sram_config/recompute_sizes]: Rows: 256 Cols: 128 -[sram_config/recompute_sizes]: Row addr size: 8 Col addr size: 0 Bank addr size: 8 -Words per row: 1 -Output files are: -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lvs -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.sp -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.v -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lib -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.py -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.html -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.log -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lef -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.gds -[sram/__init__]: Changed OPTS wpr=1 -[sram/__init__]: OPTS wpr=1 -[dff_array/__init__]: Creating row_addr_dff rows=8 cols=1 -[dff_array/__init__]: Creating data_dff rows=1 cols=128 -[dff_array/__init__]: Creating wmask_dff rows=1 cols=16 -[and2_dec/__init__]: Creating and2_dec and2_dec -[and3_dec/__init__]: Creating and3_dec and3_dec -[and4_dec/__init__]: Creating and4_dec and4_dec -[wordline_driver_array/__init__]: Creating wordline_driver_array -[wordline_driver/__init__]: Creating wordline_driver wordline_driver -[pbuf_dec/__init__]: creating pbuf_dec with size of 8 -[bitcell_base_array/__init__]: Creating global_bitcell_array 256 x 128 -[bitcell_base_array/__init__]: Creating local_bitcell_array 256 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array 256 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array 256 x 16 rbls: [1, 1] left_rbl: [0] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array 256 x 16 -[bitcell_array/__init__]: Creating bitcell_array 256 x 16 -[bitcell_base_array/__init__]: Creating replica_column 258 x 1 -[bitcell_base_array/__init__]: Creating dummy_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array 258 x 1 -[bitcell_base_array/__init__]: Creating row_cap_array_0 258 x 1 -[wordline_buffer_array/__init__]: Creating wordline_buffer_array -[bitcell_base_array/__init__]: Creating local_bitcell_array_0 256 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_0 256 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_0 256 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array_0 256 x 16 -[bitcell_array/__init__]: Creating bitcell_array_0 256 x 16 -[bitcell_base_array/__init__]: Creating dummy_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_1 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_2 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array_1 258 x 1 -[bitcell_base_array/__init__]: Creating local_bitcell_array_1 256 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_1 256 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_1 256 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [1] -[bitcell_base_array/__init__]: Creating replica_column_0 258 x 1 -[precharge_array/__init__]: Creating precharge_array -[sense_amp_array/__init__]: Creating sense_amp_array -[write_driver_array/__init__]: Creating write_driver_array -[write_mask_and_array/__init__]: Creating write_mask_and_array -[pand2/__init__]: Creating pand2 pand2 -[pdriver/__init__]: creating pdriver pdriver -[precharge_array/__init__]: Creating precharge_array_0 -[control_logic/__init__]: Creating control_logic_rw -[dff_buf/__init__]: Creating dff_buf -[dff_buf_array/__init__]: Creating dff_buf_array -[dff_buf/__init__]: Creating dff_buf_0 -[pand2/__init__]: Creating pand2 pand2_0 -[pdriver/__init__]: creating pdriver pdriver_0 -[pbuf/__init__]: creating pbuf with size of 128 -[pdriver/__init__]: creating pdriver pdriver_1 -[pdriver/__init__]: creating pdriver pdriver_2 -[pand3/__init__]: Creating pand3 pand3 -[pdriver/__init__]: creating pdriver pdriver_3 -[pand3/__init__]: Creating pand3 pand3_0 -[pdriver/__init__]: creating pdriver pdriver_4 -[pdriver/__init__]: creating pdriver pdriver_5 -[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4] -[control_logic/__init__]: Creating control_logic_r -[dff_buf_array/__init__]: Creating dff_buf_array_0 -[pdriver/__init__]: creating pdriver pdriver_6 -** Submodules: 10.6 seconds -** Placement: 0.7 seconds -** Routing: 0.4 seconds -** Verification: 0.0 seconds -** SRAM creation: 11.8 seconds -GDS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.gds -** GDS: 6.9 seconds -LEF: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lef -** LEF: 166.0 seconds -SP: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.sp -** Spice writing: 1.3 seconds -LVS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lvs.sp -** LVS writing: 0.1 seconds -LIB: Characterizing... -[characterizer.lib/prepare_tables]: Loads: [ 1.7225 6.89 27.56 ] -[characterizer.lib/prepare_tables]: Slews: [0.00125 0.005 0.04 ] -[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 1.8, 25)] -[characterizer.lib/characterize_corners]: Corner: ('TT', 1.8, 25) -[characterizer.lib/characterize_corners]: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_TT_1p8V_25C.lib -[characterizer.delay/analytical_power]: Dynamic Power: 89.54866314460835 mW -[characterizer.delay/analytical_power]: Leakage Power: 0.039892 mW -[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns) -[characterizer.delay/analytical_delay]: 0.00125, 1.7225, 0.36550338539740557, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.00125, 6.89, 0.39457057289740555, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.00125, 27.56, 0.5108393228974055, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.005, 1.7225, 0.36550338539740557, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.005, 6.89, 0.39457057289740555, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.005, 27.56, 0.5108393228974055, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.04, 1.7225, 0.36550338539740557, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.04, 6.89, 0.39457057289740555, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.04, 27.56, 0.5108393228974055, 0.016211249999999996 -** Characterization: 0.8 seconds -Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.py -** Config: 0.0 seconds -Datasheet: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.html -** Datasheet: 0.0 seconds -Verilog: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.v -** Verilog: 0.0 seconds -Extended Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_extended.py -** Extended Config: 0.0 seconds -[globals/cleanup_paths]: Purging temp directory: /tmp/openram_wbduan_23636_temp/ -** End: 187.0 seconds diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_extended.py b/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_extended.py deleted file mode 100644 index ecd722f38c..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_extended.py +++ /dev/null @@ -1,88 +0,0 @@ -accuracy_requirement = 0.75 -analytical_delay = True -auto_delay_chain_sizing = False -bank_select = "bank_select" -bitcell = "bitcell_2port" -bitcell_array = "bitcell_array" -buf_dec = "pbuf" -check_lvsdrc = False -col_cap = "col_cap" -col_cap_array = "col_cap_array" -column_mux_array = "column_mux_array" -config_file = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_128x256_8.py" -control_logic = "control_logic" -coverage = 1 -debug = False -decoder = "hierarchical_decoder" -delay_chain = "delay_chain" -delay_chain_fanout_per_stage = 4 -delay_chain_stages = 9 -dff = "dff" -dff_array = "dff_array" -drc_exe = None -drc_name = "" -dummy_bitcell = "dummy_bitcell_2port" -human_byte_size = "4kbytes" -inline_lvsdrc = False -inv_dec = "pinv" -is_unit_test = False -keep_temp = False -load_scales = [0.25, 1, 4] -local_array_size = 16 -lvs_exe = None -lvs_name = "" -magic_exe = None -nand2_dec = "pnand2" -nand3_dec = "pnand3" -nand4_dec = "pnand4" -netlist_only = False -nominal_corner_only = True -num_banks = 1 -num_r_ports = 1 -num_rw_ports = 1 -num_spare_cols = 0 -num_spare_rows = 0 -num_threads = 2 -num_w_ports = 0 -num_words = 256 -openram_tech = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology/sky130/" -openram_temp = "/tmp/openram_wbduan_23636_temp/" -os = -output_extended_config = True -output_name = "sky130_sram_1rw1r_128x256_8" -output_path = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/" -overridden = {'__name__': True, '__doc__': True, '__package__': True, '__loader__': True, '__spec__': True, '__file__': True, '__cached__': True, '__builtins__': True, 'word_size': True, 'num_words': True, 'human_byte_size': True, 'write_size': True, 'num_rw_ports': True, 'num_r_ports': True, 'num_w_ports': True, 'ports_human': True, 'os': True, '__warningregistry__': True, 'tech_name': True, 'nominal_corner_only': True, 'local_array_size': True, 'route_supplies': True, 'perimeter_pins': True} -perimeter_pins = False -pex_exe = None -pex_name = "" -ports_human = "1rw1r" -precharge_array = "precharge_array" -print_banner = True -process_corners = ['TT'] -ptx = "ptx" -rbl_delay_percentage = 0.5 -replica_bitcell = "replica_bitcell_2port" -replica_bitline = "replica_bitline" -route_supplies = False -row_cap = "row_cap" -row_cap_array = "row_cap_array" -sense_amp = "sense_amp" -sense_amp_array = "sense_amp_array" -slew_scales = [0.25, 1, 8] -spice_exe = "" -spice_name = "" -supply_voltages = [1.8] -tech_name = "sky130" -temperatures = [25] -tri_gate = "tri_gate" -tri_gate_array = "tri_gate_array" -trim_netlist = False -use_pex = False -verbose_level = 1 -word_size = 128 -wordline_driver = "wordline_driver" -words_per_row = 1 -write_driver = "write_driver" -write_driver_array = "write_driver_array" -write_mask_and_array = "write_mask_and_array" -write_size = 8 diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.log b/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.log deleted file mode 100644 index 95ab3df97d..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.log +++ /dev/null @@ -1,158 +0,0 @@ -[globals/init_openram]: Initializing OpenRAM... -[globals/setup_paths]: Temporary files saved in /tmp/openram_wbduan_3846_temp/ -[globals/read_config]: Configuration file is /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_44x64_8.py -[globals/read_config]: Output saved in /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/ -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/third_party/OpenRAM/technology -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology -[globals/init_paths]: Creating temp directory: /tmp/openram_wbduan_3846_temp/ -[globals/setup_bitcell]: Using bitcell: bitcell_2port -[characterizer/]: Initializing characterizer... -[characterizer/]: Analytical model enabled. -[verify/]: Initializing verify... -[verify/]: LVS/DRC/PEX disabled. -[globals/setup_bitcell]: Using bitcell: bitcell_2port -|==============================================================================| -|========= OpenRAM v1.1.6 =========| -|========= =========| -|========= VLSI Design and Automation Lab =========| -|========= Computer Science and Engineering Department =========| -|========= University of California Santa Cruz =========| -|========= =========| -|========= Usage help: openram-user-group@ucsc.edu =========| -|========= Development help: openram-dev-group@ucsc.edu =========| -|========= Temp dir: /tmp/openram_wbduan_3846_temp/ =========| -|========= See LICENSE for license info =========| -|==============================================================================| -** Start: 11/23/2020 21:22:46 -ERROR: file globals.py: line 557: Write size needs to be an integer multiple of word size. - -Technology: sky130 -Total size: 2816 bits -Word size: 44 -Words: 64 -Banks: 1 -Write size: 8 -RW ports: 1 -R-only ports: 1 -W-only ports: 0 -Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing). -DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). -DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). -Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). -Only generating nominal corner timing. -[sram_config/recompute_sizes]: Recomputing with words per row: 1 -[sram_config/recompute_sizes]: Rows: 64 Cols: 44 -[sram_config/recompute_sizes]: Row addr size: 6 Col addr size: 0 Bank addr size: 6 -Words per row: 1 -Output files are: -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lvs -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.sp -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.v -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lib -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.py -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.html -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.log -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lef -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.gds -[sram/__init__]: Changed OPTS wpr=1 -[sram/__init__]: OPTS wpr=1 -[dff_array/__init__]: Creating row_addr_dff rows=6 cols=1 -[dff_array/__init__]: Creating data_dff rows=1 cols=44 -[dff_array/__init__]: Creating wmask_dff rows=1 cols=6 -[and2_dec/__init__]: Creating and2_dec and2_dec -[and3_dec/__init__]: Creating and3_dec and3_dec -[and4_dec/__init__]: Creating and4_dec and4_dec -[wordline_driver_array/__init__]: Creating wordline_driver_array -[wordline_driver/__init__]: Creating wordline_driver wordline_driver -[pbuf_dec/__init__]: creating pbuf_dec with size of 2 -[bitcell_base_array/__init__]: Creating global_bitcell_array 64 x 44 -[bitcell_base_array/__init__]: Creating local_bitcell_array 64 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array 64 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array 64 x 16 rbls: [1, 1] left_rbl: [0] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array 64 x 16 -[bitcell_array/__init__]: Creating bitcell_array 64 x 16 -[bitcell_base_array/__init__]: Creating replica_column 66 x 1 -[bitcell_base_array/__init__]: Creating dummy_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array 66 x 1 -[bitcell_base_array/__init__]: Creating row_cap_array_0 66 x 1 -[wordline_buffer_array/__init__]: Creating wordline_buffer_array -[bitcell_base_array/__init__]: Creating local_bitcell_array_0 64 x 28 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_0 64 x 28 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_0 64 x 28 rbls: [1, 1] left_rbl: [] right_rbl: [1] -[bitcell_base_array/__init__]: Creating bitcell_array_0 64 x 28 -[bitcell_array/__init__]: Creating bitcell_array_0 64 x 28 -[bitcell_base_array/__init__]: Creating replica_column_0 66 x 1 -[bitcell_base_array/__init__]: Creating dummy_array_0 1 x 28 -[bitcell_base_array/__init__]: Creating col_cap_array_1 1 x 28 -[bitcell_base_array/__init__]: Creating col_cap_array_2 1 x 28 -[bitcell_base_array/__init__]: Creating row_cap_array_1 66 x 1 -[wordline_buffer_array/__init__]: Creating wordline_buffer_array_0 -[precharge_array/__init__]: Creating precharge_array -[sense_amp_array/__init__]: Creating sense_amp_array -[write_driver_array/__init__]: Creating write_driver_array -[write_mask_and_array/__init__]: Creating write_mask_and_array -[pand2/__init__]: Creating pand2 pand2 -[pdriver/__init__]: creating pdriver pdriver -[precharge_array/__init__]: Creating precharge_array_0 -[control_logic/__init__]: Creating control_logic_rw -[dff_buf/__init__]: Creating dff_buf -[dff_buf_array/__init__]: Creating dff_buf_array -[dff_buf/__init__]: Creating dff_buf_0 -[pand2/__init__]: Creating pand2 pand2_0 -[pdriver/__init__]: creating pdriver pdriver_0 -[pbuf/__init__]: creating pbuf with size of 44 -[pdriver/__init__]: creating pdriver pdriver_1 -[pdriver/__init__]: creating pdriver pdriver_2 -[pand3/__init__]: Creating pand3 pand3 -[pdriver/__init__]: creating pdriver pdriver_3 -[pand3/__init__]: Creating pand3 pand3_0 -[pdriver/__init__]: creating pdriver pdriver_4 -[pdriver/__init__]: creating pdriver pdriver_5 -[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4] -[control_logic/__init__]: Creating control_logic_r -[dff_buf_array/__init__]: Creating dff_buf_array_0 -[pdriver/__init__]: creating pdriver pdriver_6 -** Submodules: 3.4 seconds -** Placement: 0.1 seconds -** Routing: 0.1 seconds -** Verification: 0.0 seconds -** SRAM creation: 3.6 seconds -GDS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.gds -** GDS: 2.2 seconds -LEF: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lef -** LEF: 15.4 seconds -SP: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.sp -** Spice writing: 0.3 seconds -LVS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lvs.sp -** LVS writing: 0.0 seconds -LIB: Characterizing... -[characterizer.lib/prepare_tables]: Loads: [ 1.7225 6.89 27.56 ] -[characterizer.lib/prepare_tables]: Slews: [0.00125 0.005 0.04 ] -[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 1.8, 25)] -[characterizer.lib/characterize_corners]: Corner: ('TT', 1.8, 25) -[characterizer.lib/characterize_corners]: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_TT_1p8V_25C.lib -[characterizer.delay/analytical_power]: Dynamic Power: 10.353463918847996 mW -[characterizer.delay/analytical_power]: Leakage Power: 0.003998 mW -[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns) -[characterizer.delay/analytical_delay]: 0.00125, 1.7225, 0.31694700077670185, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.00125, 6.89, 0.34601418827670183, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.00125, 27.56, 0.46228293827670175, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.005, 1.7225, 0.31694700077670185, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.005, 6.89, 0.34601418827670183, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.005, 27.56, 0.46228293827670175, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.04, 1.7225, 0.31694700077670185, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.04, 6.89, 0.34601418827670183, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.04, 27.56, 0.46228293827670175, 0.016211249999999996 -** Characterization: 0.2 seconds -Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.py -** Config: 0.0 seconds -Datasheet: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.html -** Datasheet: 0.0 seconds -Verilog: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.v -** Verilog: 0.0 seconds -Extended Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_extended.py -** Extended Config: 0.0 seconds -[globals/cleanup_paths]: Purging temp directory: /tmp/openram_wbduan_3846_temp/ -** End: 21.9 seconds diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_extended.py b/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_extended.py deleted file mode 100644 index ddc8cfa39c..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_extended.py +++ /dev/null @@ -1,88 +0,0 @@ -accuracy_requirement = 0.75 -analytical_delay = True -auto_delay_chain_sizing = False -bank_select = "bank_select" -bitcell = "bitcell_2port" -bitcell_array = "bitcell_array" -buf_dec = "pbuf" -check_lvsdrc = False -col_cap = "col_cap" -col_cap_array = "col_cap_array" -column_mux_array = "column_mux_array" -config_file = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_44x64_8.py" -control_logic = "control_logic" -coverage = 1 -debug = False -decoder = "hierarchical_decoder" -delay_chain = "delay_chain" -delay_chain_fanout_per_stage = 4 -delay_chain_stages = 9 -dff = "dff" -dff_array = "dff_array" -drc_exe = None -drc_name = "" -dummy_bitcell = "dummy_bitcell_2port" -human_byte_size = "0kbytes" -inline_lvsdrc = False -inv_dec = "pinv" -is_unit_test = False -keep_temp = False -load_scales = [0.25, 1, 4] -local_array_size = 16 -lvs_exe = None -lvs_name = "" -magic_exe = None -nand2_dec = "pnand2" -nand3_dec = "pnand3" -nand4_dec = "pnand4" -netlist_only = False -nominal_corner_only = True -num_banks = 1 -num_r_ports = 1 -num_rw_ports = 1 -num_spare_cols = 0 -num_spare_rows = 0 -num_threads = 2 -num_w_ports = 0 -num_words = 64 -openram_tech = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology/sky130/" -openram_temp = "/tmp/openram_wbduan_3846_temp/" -os = -output_extended_config = True -output_name = "sky130_sram_1rw1r_44x64_8" -output_path = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/" -overridden = {'__name__': True, '__doc__': True, '__package__': True, '__loader__': True, '__spec__': True, '__file__': True, '__cached__': True, '__builtins__': True, 'word_size': True, 'num_words': True, 'human_byte_size': True, 'write_size': True, 'num_rw_ports': True, 'num_r_ports': True, 'num_w_ports': True, 'ports_human': True, 'os': True, '__warningregistry__': True, 'tech_name': True, 'nominal_corner_only': True, 'local_array_size': True, 'route_supplies': True, 'perimeter_pins': True} -perimeter_pins = False -pex_exe = None -pex_name = "" -ports_human = "1rw1r" -precharge_array = "precharge_array" -print_banner = True -process_corners = ['TT'] -ptx = "ptx" -rbl_delay_percentage = 0.5 -replica_bitcell = "replica_bitcell_2port" -replica_bitline = "replica_bitline" -route_supplies = False -row_cap = "row_cap" -row_cap_array = "row_cap_array" -sense_amp = "sense_amp" -sense_amp_array = "sense_amp_array" -slew_scales = [0.25, 1, 8] -spice_exe = "" -spice_name = "" -supply_voltages = [1.8] -tech_name = "sky130" -temperatures = [25] -tri_gate = "tri_gate" -tri_gate_array = "tri_gate_array" -trim_netlist = False -use_pex = False -verbose_level = 1 -word_size = 44 -wordline_driver = "wordline_driver" -words_per_row = 1 -write_driver = "write_driver" -write_driver_array = "write_driver_array" -write_mask_and_array = "write_mask_and_array" -write_size = 8 diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.log b/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.log deleted file mode 100644 index e897157892..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.log +++ /dev/null @@ -1,163 +0,0 @@ -[globals/init_openram]: Initializing OpenRAM... -[globals/setup_paths]: Temporary files saved in /tmp/openram_wbduan_3328_temp/ -[globals/read_config]: Configuration file is /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_64x256_8.py -[globals/read_config]: Output saved in /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/ -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/third_party/OpenRAM/technology -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology -[globals/init_paths]: Creating temp directory: /tmp/openram_wbduan_3328_temp/ -[globals/setup_bitcell]: Using bitcell: bitcell_2port -[characterizer/]: Initializing characterizer... -[characterizer/]: Analytical model enabled. -[verify/]: Initializing verify... -[verify/]: LVS/DRC/PEX disabled. -[globals/setup_bitcell]: Using bitcell: bitcell_2port -|==============================================================================| -|========= OpenRAM v1.1.6 =========| -|========= =========| -|========= VLSI Design and Automation Lab =========| -|========= Computer Science and Engineering Department =========| -|========= University of California Santa Cruz =========| -|========= =========| -|========= Usage help: openram-user-group@ucsc.edu =========| -|========= Development help: openram-dev-group@ucsc.edu =========| -|========= Temp dir: /tmp/openram_wbduan_3328_temp/ =========| -|========= See LICENSE for license info =========| -|==============================================================================| -** Start: 11/23/2020 21:16:39 -Technology: sky130 -Total size: 16384 bits -WARNING: file globals.py: line 571: Requesting such a large memory size (16384) will have a large run-time. Consider using multiple smaller banks. - -Word size: 64 -Words: 256 -Banks: 1 -Write size: 8 -RW ports: 1 -R-only ports: 1 -W-only ports: 0 -Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing). -DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). -DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). -Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). -Only generating nominal corner timing. -[sram_config/recompute_sizes]: Recomputing with words per row: 2 -[sram_config/recompute_sizes]: Rows: 128 Cols: 128 -[sram_config/recompute_sizes]: Row addr size: 7 Col addr size: 1 Bank addr size: 8 -Words per row: 2 -Output files are: -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lvs -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.sp -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.v -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lib -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.py -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.html -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.log -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lef -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.gds -[sram/__init__]: Changed OPTS wpr=2 -[sram/__init__]: OPTS wpr=2 -[dff_array/__init__]: Creating row_addr_dff rows=7 cols=1 -[dff_array/__init__]: Creating col_addr_dff rows=1 cols=1 -[dff_array/__init__]: Creating data_dff rows=1 cols=64 -[dff_array/__init__]: Creating wmask_dff rows=1 cols=8 -[and2_dec/__init__]: Creating and2_dec and2_dec -[and3_dec/__init__]: Creating and3_dec and3_dec -[and4_dec/__init__]: Creating and4_dec and4_dec -[wordline_driver_array/__init__]: Creating wordline_driver_array -[wordline_driver/__init__]: Creating wordline_driver wordline_driver -[pbuf_dec/__init__]: creating pbuf_dec with size of 8 -[bitcell_base_array/__init__]: Creating global_bitcell_array 128 x 128 -[bitcell_base_array/__init__]: Creating local_bitcell_array 128 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array 128 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array 128 x 16 rbls: [1, 1] left_rbl: [0] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array 128 x 16 -[bitcell_array/__init__]: Creating bitcell_array 128 x 16 -[bitcell_base_array/__init__]: Creating replica_column 130 x 1 -[bitcell_base_array/__init__]: Creating dummy_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array 130 x 1 -[bitcell_base_array/__init__]: Creating row_cap_array_0 130 x 1 -[wordline_buffer_array/__init__]: Creating wordline_buffer_array -[bitcell_base_array/__init__]: Creating local_bitcell_array_0 128 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_0 128 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_0 128 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array_0 128 x 16 -[bitcell_array/__init__]: Creating bitcell_array_0 128 x 16 -[bitcell_base_array/__init__]: Creating dummy_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_1 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_2 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array_1 130 x 1 -[bitcell_base_array/__init__]: Creating local_bitcell_array_1 128 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_1 128 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_1 128 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [1] -[bitcell_base_array/__init__]: Creating replica_column_0 130 x 1 -[precharge_array/__init__]: Creating precharge_array -[sense_amp_array/__init__]: Creating sense_amp_array -[column_mux_array/__init__]: Creating column_mux_array -[write_driver_array/__init__]: Creating write_driver_array -[write_mask_and_array/__init__]: Creating write_mask_and_array -[pand2/__init__]: Creating pand2 pand2 -[pdriver/__init__]: creating pdriver pdriver -[precharge_array/__init__]: Creating precharge_array_0 -[column_mux_array/__init__]: Creating column_mux_array_0 -[pinvbuf/__init__]: creating pinvbuf pinvbuf -[control_logic/__init__]: Creating control_logic_rw -[dff_buf/__init__]: Creating dff_buf -[dff_buf_array/__init__]: Creating dff_buf_array -[dff_buf/__init__]: Creating dff_buf_0 -[pand2/__init__]: Creating pand2 pand2_0 -[pdriver/__init__]: creating pdriver pdriver_0 -[pbuf/__init__]: creating pbuf with size of 128 -[pdriver/__init__]: creating pdriver pdriver_1 -[pdriver/__init__]: creating pdriver pdriver_2 -[pand3/__init__]: Creating pand3 pand3 -[pdriver/__init__]: creating pdriver pdriver_3 -[pand3/__init__]: Creating pand3 pand3_0 -[pdriver/__init__]: creating pdriver pdriver_4 -[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4] -[control_logic/__init__]: Creating control_logic_r -[dff_buf_array/__init__]: Creating dff_buf_array_0 -[pdriver/__init__]: creating pdriver pdriver_5 -** Submodules: 6.0 seconds -** Placement: 0.4 seconds -** Routing: 0.2 seconds -** Verification: 0.0 seconds -** SRAM creation: 6.6 seconds -GDS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.gds -** GDS: 3.7 seconds -LEF: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lef -** LEF: 84.6 seconds -SP: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.sp -** Spice writing: 0.7 seconds -LVS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lvs.sp -** LVS writing: 0.1 seconds -LIB: Characterizing... -[characterizer.lib/prepare_tables]: Loads: [ 1.7225 6.89 27.56 ] -[characterizer.lib/prepare_tables]: Slews: [0.00125 0.005 0.04 ] -[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 1.8, 25)] -[characterizer.lib/characterize_corners]: Corner: ('TT', 1.8, 25) -[characterizer.lib/characterize_corners]: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_TT_1p8V_25C.lib -[characterizer.delay/analytical_power]: Dynamic Power: 45.61833593692795 mW -[characterizer.delay/analytical_power]: Leakage Power: 0.020078 mW -[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns) -[characterizer.delay/analytical_delay]: 0.00125, 1.7225, 0.3799116424684287, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.00125, 6.89, 0.40897882996842866, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.00125, 27.56, 0.5252475799684286, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.005, 1.7225, 0.3799116424684287, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.005, 6.89, 0.40897882996842866, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.005, 27.56, 0.5252475799684286, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.04, 1.7225, 0.3799116424684287, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.04, 6.89, 0.40897882996842866, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.04, 27.56, 0.5252475799684286, 0.016211249999999996 -** Characterization: 0.5 seconds -Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.py -** Config: 0.0 seconds -Datasheet: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.html -** Datasheet: 0.0 seconds -Verilog: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.v -** Verilog: 0.0 seconds -Extended Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_extended.py -** Extended Config: 0.0 seconds -[globals/cleanup_paths]: Purging temp directory: /tmp/openram_wbduan_3328_temp/ -** End: 96.3 seconds diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_extended.py b/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_extended.py deleted file mode 100644 index 635f5ac42b..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_extended.py +++ /dev/null @@ -1,88 +0,0 @@ -accuracy_requirement = 0.75 -analytical_delay = True -auto_delay_chain_sizing = False -bank_select = "bank_select" -bitcell = "bitcell_2port" -bitcell_array = "bitcell_array" -buf_dec = "pbuf" -check_lvsdrc = False -col_cap = "col_cap" -col_cap_array = "col_cap_array" -column_mux_array = "column_mux_array" -config_file = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_64x256_8.py" -control_logic = "control_logic" -coverage = 1 -debug = False -decoder = "hierarchical_decoder" -delay_chain = "delay_chain" -delay_chain_fanout_per_stage = 4 -delay_chain_stages = 9 -dff = "dff" -dff_array = "dff_array" -drc_exe = None -drc_name = "" -dummy_bitcell = "dummy_bitcell_2port" -human_byte_size = "2kbytes" -inline_lvsdrc = False -inv_dec = "pinv" -is_unit_test = False -keep_temp = False -load_scales = [0.25, 1, 4] -local_array_size = 16 -lvs_exe = None -lvs_name = "" -magic_exe = None -nand2_dec = "pnand2" -nand3_dec = "pnand3" -nand4_dec = "pnand4" -netlist_only = False -nominal_corner_only = True -num_banks = 1 -num_r_ports = 1 -num_rw_ports = 1 -num_spare_cols = 0 -num_spare_rows = 0 -num_threads = 2 -num_w_ports = 0 -num_words = 256 -openram_tech = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology/sky130/" -openram_temp = "/tmp/openram_wbduan_3328_temp/" -os = -output_extended_config = True -output_name = "sky130_sram_1rw1r_64x256_8" -output_path = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/" -overridden = {'__name__': True, '__doc__': True, '__package__': True, '__loader__': True, '__spec__': True, '__file__': True, '__cached__': True, '__builtins__': True, 'word_size': True, 'num_words': True, 'human_byte_size': True, 'write_size': True, 'num_rw_ports': True, 'num_r_ports': True, 'num_w_ports': True, 'ports_human': True, 'os': True, '__warningregistry__': True, 'tech_name': True, 'nominal_corner_only': True, 'local_array_size': True, 'route_supplies': True, 'perimeter_pins': True} -perimeter_pins = False -pex_exe = None -pex_name = "" -ports_human = "1rw1r" -precharge_array = "precharge_array" -print_banner = True -process_corners = ['TT'] -ptx = "ptx" -rbl_delay_percentage = 0.5 -replica_bitcell = "replica_bitcell_2port" -replica_bitline = "replica_bitline" -route_supplies = False -row_cap = "row_cap" -row_cap_array = "row_cap_array" -sense_amp = "sense_amp" -sense_amp_array = "sense_amp_array" -slew_scales = [0.25, 1, 8] -spice_exe = "" -spice_name = "" -supply_voltages = [1.8] -tech_name = "sky130" -temperatures = [25] -tri_gate = "tri_gate" -tri_gate_array = "tri_gate_array" -trim_netlist = False -use_pex = False -verbose_level = 1 -word_size = 64 -wordline_driver = "wordline_driver" -words_per_row = 2 -write_driver = "write_driver" -write_driver_array = "write_driver_array" -write_mask_and_array = "write_mask_and_array" -write_size = 8 diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.log b/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.log deleted file mode 100644 index 5881892e12..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.log +++ /dev/null @@ -1,158 +0,0 @@ -[globals/init_openram]: Initializing OpenRAM... -[globals/setup_paths]: Temporary files saved in /tmp/openram_wbduan_24000_temp/ -[globals/read_config]: Configuration file is /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_80x64_8.py -[globals/read_config]: Output saved in /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/ -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/third_party/OpenRAM/technology -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology -[globals/init_paths]: Creating temp directory: /tmp/openram_wbduan_24000_temp/ -[globals/setup_bitcell]: Using bitcell: bitcell_2port -[characterizer/]: Initializing characterizer... -[characterizer/]: Analytical model enabled. -[verify/]: Initializing verify... -[verify/]: LVS/DRC/PEX disabled. -[globals/setup_bitcell]: Using bitcell: bitcell_2port -|==============================================================================| -|========= OpenRAM v1.1.6 =========| -|========= =========| -|========= VLSI Design and Automation Lab =========| -|========= Computer Science and Engineering Department =========| -|========= University of California Santa Cruz =========| -|========= =========| -|========= Usage help: openram-user-group@ucsc.edu =========| -|========= Development help: openram-dev-group@ucsc.edu =========| -|========= Temp dir: /tmp/openram_wbduan_24000_temp/ =========| -|========= See LICENSE for license info =========| -|==============================================================================| -** Start: 11/25/2020 17:04:12 -Technology: sky130 -Total size: 5120 bits -Word size: 80 -Words: 64 -Banks: 1 -Write size: 8 -RW ports: 1 -R-only ports: 1 -W-only ports: 0 -Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing). -DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). -DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). -Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). -Only generating nominal corner timing. -[sram_config/recompute_sizes]: Recomputing with words per row: 1 -[sram_config/recompute_sizes]: Rows: 64 Cols: 80 -[sram_config/recompute_sizes]: Row addr size: 6 Col addr size: 0 Bank addr size: 6 -Words per row: 1 -Output files are: -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lvs -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.sp -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.v -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lib -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.py -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.html -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.log -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lef -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.gds -[sram/__init__]: Changed OPTS wpr=1 -[sram/__init__]: OPTS wpr=1 -[dff_array/__init__]: Creating row_addr_dff rows=6 cols=1 -[dff_array/__init__]: Creating data_dff rows=1 cols=80 -[dff_array/__init__]: Creating wmask_dff rows=1 cols=10 -[and2_dec/__init__]: Creating and2_dec and2_dec -[and3_dec/__init__]: Creating and3_dec and3_dec -[and4_dec/__init__]: Creating and4_dec and4_dec -[wordline_driver_array/__init__]: Creating wordline_driver_array -[wordline_driver/__init__]: Creating wordline_driver wordline_driver -[pbuf_dec/__init__]: creating pbuf_dec with size of 5 -[bitcell_base_array/__init__]: Creating global_bitcell_array 64 x 80 -[bitcell_base_array/__init__]: Creating local_bitcell_array 64 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array 64 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array 64 x 16 rbls: [1, 1] left_rbl: [0] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array 64 x 16 -[bitcell_array/__init__]: Creating bitcell_array 64 x 16 -[bitcell_base_array/__init__]: Creating replica_column 66 x 1 -[bitcell_base_array/__init__]: Creating dummy_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array 66 x 1 -[bitcell_base_array/__init__]: Creating row_cap_array_0 66 x 1 -[wordline_buffer_array/__init__]: Creating wordline_buffer_array -[bitcell_base_array/__init__]: Creating local_bitcell_array_0 64 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_0 64 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_0 64 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array_0 64 x 16 -[bitcell_array/__init__]: Creating bitcell_array_0 64 x 16 -[bitcell_base_array/__init__]: Creating dummy_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_1 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_2 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array_1 66 x 1 -[bitcell_base_array/__init__]: Creating local_bitcell_array_1 64 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_1 64 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_1 64 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [1] -[bitcell_base_array/__init__]: Creating replica_column_0 66 x 1 -[precharge_array/__init__]: Creating precharge_array -[sense_amp_array/__init__]: Creating sense_amp_array -[write_driver_array/__init__]: Creating write_driver_array -[write_mask_and_array/__init__]: Creating write_mask_and_array -[pand2/__init__]: Creating pand2 pand2 -[pdriver/__init__]: creating pdriver pdriver -[precharge_array/__init__]: Creating precharge_array_0 -[control_logic/__init__]: Creating control_logic_rw -[dff_buf/__init__]: Creating dff_buf -[dff_buf_array/__init__]: Creating dff_buf_array -[dff_buf/__init__]: Creating dff_buf_0 -[pand2/__init__]: Creating pand2 pand2_0 -[pdriver/__init__]: creating pdriver pdriver_0 -[pbuf/__init__]: creating pbuf with size of 80 -[pdriver/__init__]: creating pdriver pdriver_1 -[pdriver/__init__]: creating pdriver pdriver_2 -[pand3/__init__]: Creating pand3 pand3 -[pdriver/__init__]: creating pdriver pdriver_3 -[pand3/__init__]: Creating pand3 pand3_0 -[pdriver/__init__]: creating pdriver pdriver_4 -[pdriver/__init__]: creating pdriver pdriver_5 -[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4] -[control_logic/__init__]: Creating control_logic_r -[dff_buf_array/__init__]: Creating dff_buf_array_0 -[pdriver/__init__]: creating pdriver pdriver_6 -** Submodules: 3.6 seconds -** Placement: 0.4 seconds -** Routing: 0.2 seconds -** Verification: 0.0 seconds -** SRAM creation: 4.2 seconds -GDS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.gds -** GDS: 2.5 seconds -LEF: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lef -** LEF: 28.9 seconds -SP: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.sp -** Spice writing: 0.4 seconds -LVS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lvs.sp -** LVS writing: 0.0 seconds -LIB: Characterizing... -[characterizer.lib/prepare_tables]: Loads: [ 1.7225 6.89 27.56 ] -[characterizer.lib/prepare_tables]: Slews: [0.00125 0.005 0.04 ] -[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 1.8, 25)] -[characterizer.lib/characterize_corners]: Corner: ('TT', 1.8, 25) -[characterizer.lib/characterize_corners]: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_TT_1p8V_25C.lib -[characterizer.delay/analytical_power]: Dynamic Power: 16.77798724780799 mW -[characterizer.delay/analytical_power]: Leakage Power: 0.006744 mW -[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns) -[characterizer.delay/analytical_delay]: 0.00125, 1.7225, 0.32695406418057094, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.00125, 6.89, 0.3560212516805709, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.00125, 27.56, 0.4722900016805709, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.005, 1.7225, 0.32695406418057094, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.005, 6.89, 0.3560212516805709, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.005, 27.56, 0.4722900016805709, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.04, 1.7225, 0.32695406418057094, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.04, 6.89, 0.3560212516805709, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.04, 27.56, 0.4722900016805709, 0.016211249999999996 -** Characterization: 0.3 seconds -Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.py -** Config: 0.0 seconds -Datasheet: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.html -** Datasheet: 0.0 seconds -Verilog: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.v -** Verilog: 0.0 seconds -Extended Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_extended.py -** Extended Config: 0.0 seconds -[globals/cleanup_paths]: Purging temp directory: /tmp/openram_wbduan_24000_temp/ -** End: 36.5 seconds diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_extended.py b/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_extended.py deleted file mode 100644 index 0c05402d34..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_extended.py +++ /dev/null @@ -1,88 +0,0 @@ -accuracy_requirement = 0.75 -analytical_delay = True -auto_delay_chain_sizing = False -bank_select = "bank_select" -bitcell = "bitcell_2port" -bitcell_array = "bitcell_array" -buf_dec = "pbuf" -check_lvsdrc = False -col_cap = "col_cap" -col_cap_array = "col_cap_array" -column_mux_array = "column_mux_array" -config_file = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_80x64_8.py" -control_logic = "control_logic" -coverage = 1 -debug = False -decoder = "hierarchical_decoder" -delay_chain = "delay_chain" -delay_chain_fanout_per_stage = 4 -delay_chain_stages = 9 -dff = "dff" -dff_array = "dff_array" -drc_exe = None -drc_name = "" -dummy_bitcell = "dummy_bitcell_2port" -human_byte_size = "1kbytes" -inline_lvsdrc = False -inv_dec = "pinv" -is_unit_test = False -keep_temp = False -load_scales = [0.25, 1, 4] -local_array_size = 16 -lvs_exe = None -lvs_name = "" -magic_exe = None -nand2_dec = "pnand2" -nand3_dec = "pnand3" -nand4_dec = "pnand4" -netlist_only = False -nominal_corner_only = True -num_banks = 1 -num_r_ports = 1 -num_rw_ports = 1 -num_spare_cols = 0 -num_spare_rows = 0 -num_threads = 2 -num_w_ports = 0 -num_words = 64 -openram_tech = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology/sky130/" -openram_temp = "/tmp/openram_wbduan_24000_temp/" -os = -output_extended_config = True -output_name = "sky130_sram_1rw1r_80x64_8" -output_path = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/" -overridden = {'__name__': True, '__doc__': True, '__package__': True, '__loader__': True, '__spec__': True, '__file__': True, '__cached__': True, '__builtins__': True, 'word_size': True, 'num_words': True, 'human_byte_size': True, 'write_size': True, 'num_rw_ports': True, 'num_r_ports': True, 'num_w_ports': True, 'ports_human': True, 'os': True, '__warningregistry__': True, 'tech_name': True, 'nominal_corner_only': True, 'local_array_size': True, 'route_supplies': True, 'perimeter_pins': True} -perimeter_pins = False -pex_exe = None -pex_name = "" -ports_human = "1rw1r" -precharge_array = "precharge_array" -print_banner = True -process_corners = ['TT'] -ptx = "ptx" -rbl_delay_percentage = 0.5 -replica_bitcell = "replica_bitcell_2port" -replica_bitline = "replica_bitline" -route_supplies = False -row_cap = "row_cap" -row_cap_array = "row_cap_array" -sense_amp = "sense_amp" -sense_amp_array = "sense_amp_array" -slew_scales = [0.25, 1, 8] -spice_exe = "" -spice_name = "" -supply_voltages = [1.8] -tech_name = "sky130" -temperatures = [25] -tri_gate = "tri_gate" -tri_gate_array = "tri_gate_array" -trim_netlist = False -use_pex = False -verbose_level = 1 -word_size = 80 -wordline_driver = "wordline_driver" -words_per_row = 1 -write_driver = "write_driver" -write_driver_array = "write_driver_array" -write_mask_and_array = "write_mask_and_array" -write_size = 8