Low-level HW Digital Systems II

Low-Level HW Digital Systems II

This repository contains the source files for the assignment in the "Low-Level HW Digital Systems II" course. It focuses on the design and verification of an Up-Down Counter and a Simple Synchronous FIFO using SystemVerilog.

Contents

Up-Down Counter

• counter.sv: SystemVerilog module for the Up-Down Counter
• counter_property.sv: SystemVerilog Assertions (SVA) for counter verification
• test_counter.sv: Testbench for the Up-Down Counter

Simple Synchronous FIFO

• fifo.sv: SystemVerilog module for the FIFO
• fifo_property.sv: SystemVerilog Assertions (SVA) for FIFO verification
• test_fifo.sv: Testbench for the FIFO

Simulation Tool

Questa Intel FPGA Starter Edition

Assignment Objectives

The main objectives of this assignment were:

• To familiarize students with the design, testing, and verification of logic circuits using a hardware description language.
• To implement an Up-Down Counter and a FIFO memory using SystemVerilog.
• To use SystemVerilog Assertions (SVA) for formal verification.
• To create testbenches for functional verification through simulation.