roadmap-and-bugs

FPGA Visual Builder Roadmap
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FPGA Builder is a work in progress.


Suggested Implementation:
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- Wires should connect to pins and give the user the option of simply connecting the chip to other components at the center
- Pin Connectivity: Enable users to connect pins between components, ensuring that the connections are valid (e.g., input to output, compatible signal types).


Completed Updates:
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- COMPLETED 8-19-2024: Ability to make more kinds of chips, specifically Square Chips, Double Long Chips, and Half-as-wide Chips
- COMPLETED 8-19-2024: User can add pins on all sides
- COMPLETED 8-19-2024: Ability to create more types of components
- COMPLETED 8-19-2024: Make wires stay visually under all chips and components


Bugs To Fix:
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- Adding chip connections (wires) is buggy, sometimes wwil not add and sometimes complains not to connect a chip to itself with a pop-up
- Rotating chips is finicky, sometimes does not want to when clicked.


Newly Added Features/Functionality:
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- (8-12-2024) The ability to Save and Load .fga files has been added and is tested and working.