From 9bb039cef30dd2e7f301bd406ee27f71905ce57f Mon Sep 17 00:00:00 2001 From: Akos Pasztor Date: Thu, 19 Oct 2017 18:14:12 +0200 Subject: [PATCH 1/2] added app-specific configuration --- EWARM/stm32-bootloader.dep | 832 ++++++++++++++++++------------------- Inc/bootloader.h | 6 +- Inc/main.h | 7 + Src/main.c | 2 +- 4 files changed, 426 insertions(+), 421 deletions(-) diff --git a/EWARM/stm32-bootloader.dep b/EWARM/stm32-bootloader.dep index 17de8b7..10c0d80 100644 --- a/EWARM/stm32-bootloader.dep +++ b/EWARM/stm32-bootloader.dep @@ -22,37 +22,6 @@ $PROJ_DIR$\..\Src\system_stm32l4xx.c $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - $PROJ_DIR$\L476\Obj\ff.__cstat.et - $PROJ_DIR$\L476\List\stm32-bootloader.map - $PROJ_DIR$\L476\Obj\diskio.__cstat.et - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.h - $PROJ_DIR$\L476\Obj\syscall.o - $PROJ_DIR$\L476\Obj\syscall.pbi - $PROJ_DIR$\..\Inc\sd_diskio.h - $PROJ_DIR$\..\Src\sd_diskio.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_cortex.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc_ex.h - $TOOLKIT_DIR$\lib\shb_l.a - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr.h - $TOOLKIT_DIR$\inc\c\DLib_Defaults.h - $TOOLKIT_DIR$\inc\c\DLib_Product.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_sd.h - $TOOLKIT_DIR$\inc\c\DLib_Product_string.h - $TOOLKIT_DIR$\inc\c\string.h - $TOOLKIT_DIR$\inc\c\intrinsics.h - $PROJ_DIR$\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc.h - $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmSimd.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c @@ -71,19 +40,6 @@ $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.c $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.c $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c - $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc_ex.__cstat.et - $PROJ_DIR$\L476\Obj\stm32l4xx_hal_sd.__cstat.et - $PROJ_DIR$\L476\Obj\stm32l4xx_ll_sdmmc.__cstat.et - $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc.pbi - $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc_ex.pbi - $PROJ_DIR$\L476\Obj\stm32l4xx_hal_sd.pbi - $PROJ_DIR$\L476\Obj\stm32l4xx_ll_sdmmc.pbi - $PROJ_DIR$\L476\Obj\diskio.pbi - $PROJ_DIR$\L476\Obj\ff.pbi - $PROJ_DIR$\L476\Obj\ff_gen_drv.pbi - $PROJ_DIR$\L476\Exe\stm32-bootloader.out - $PROJ_DIR$\L476\Exe\stm32-bootloader.bin - $PROJ_DIR$\L476\Obj\ff_gen_drv.__cstat.et $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc_ex.h $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmInstr.h $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h @@ -97,6 +53,7 @@ $PROJ_DIR$\L476\Obj\startup_stm32l496xx.o $PROJ_DIR$\L476\Obj\bsp_driver_sd.__cstat.et $PROJ_DIR$\L476\Obj\syscall.__cstat.et + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h $PROJ_DIR$\L476\Obj\bootloader.__cstat.et $PROJ_DIR$\L476\Obj\fatfs.__cstat.et $PROJ_DIR$\L476\Obj\main.__cstat.et @@ -178,13 +135,56 @@ $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_def.h $TOOLKIT_DIR$\inc\c\ycheck.h $PROJ_DIR$\stm32l476xx_flash.icf + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_cortex.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc_ex.h + $TOOLKIT_DIR$\lib\shb_l.a + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_sd.h + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $TOOLKIT_DIR$\inc\c\string.h + $TOOLKIT_DIR$\inc\c\intrinsics.h + $PROJ_DIR$\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc.h + $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmSimd.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h + $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc_ex.__cstat.et + $PROJ_DIR$\L476\Obj\stm32l4xx_hal_sd.__cstat.et + $PROJ_DIR$\L476\Obj\stm32l4xx_ll_sdmmc.__cstat.et + $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc.pbi + $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc_ex.pbi + $PROJ_DIR$\L476\Obj\stm32l4xx_hal_sd.pbi + $PROJ_DIR$\L476\Obj\stm32l4xx_ll_sdmmc.pbi + $PROJ_DIR$\L476\Obj\diskio.pbi + $PROJ_DIR$\L476\Obj\ff.pbi + $PROJ_DIR$\L476\Obj\ff_gen_drv.pbi + $PROJ_DIR$\L476\Exe\stm32-bootloader.out + $PROJ_DIR$\L476\Exe\stm32-bootloader.bin + $PROJ_DIR$\L476\Obj\ff_gen_drv.__cstat.et + $PROJ_DIR$\L476\Obj\ff.__cstat.et + $PROJ_DIR$\L476\List\stm32-bootloader.map + $PROJ_DIR$\L476\Obj\diskio.__cstat.et + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.h + $PROJ_DIR$\L476\Obj\syscall.o + $PROJ_DIR$\L476\Obj\syscall.pbi + $PROJ_DIR$\..\Inc\sd_diskio.h + $PROJ_DIR$\..\Src\sd_diskio.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h [ROOT_NODE] ILINK - 76 18 + 162 158 @@ -193,7 +193,7 @@ AARM - 144 + 101 @@ -202,7 +202,7 @@ AARM - 89 + 45 @@ -211,25 +211,25 @@ __cstat - 92 + 49 BICOMP - 145 + 102 ICCARM - 119 + 76 BICOMP - 115 170 42 168 112 29 87 169 20 33 171 118 2 113 110 83 116 6 27 30 26 36 40 117 79 81 80 43 34 84 35 39 7 31 47 28 86 44 41 + 72 127 142 125 69 48 43 126 164 133 128 75 2 70 67 39 73 6 171 130 170 136 140 74 35 37 36 143 134 40 135 139 7 131 147 172 42 144 141 ICCARM - 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 29 7 6 27 170 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 2 + 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 48 7 6 171 127 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 2 @@ -238,25 +238,25 @@ __cstat - 90 + 46 BICOMP - 135 + 92 ICCARM - 137 + 94 BICOMP - 116 47 113 83 171 170 7 31 28 86 110 118 29 6 27 20 30 42 26 33 36 40 168 87 169 44 41 3 80 43 34 84 35 39 117 79 81 115 112 + 73 147 70 39 128 127 7 131 172 42 67 75 48 6 171 164 130 142 170 133 136 140 125 43 126 144 141 3 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 3 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 3 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -265,25 +265,25 @@ __cstat - 93 + 50 BICOMP - 146 + 103 ICCARM - 125 + 82 BICOMP - 169 6 83 5 26 45 3 7 27 30 36 170 40 118 41 20 42 33 168 29 87 44 117 131 88 21 114 132 31 47 28 86 113 110 116 171 46 4 80 43 34 84 35 39 79 81 115 112 + 126 6 39 5 170 145 3 7 171 130 136 127 140 75 141 164 142 133 125 48 43 144 74 88 44 165 71 89 131 147 172 42 70 67 73 128 146 4 36 143 134 40 135 139 35 37 72 69 ICCARM - 4 88 114 5 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 3 132 131 45 46 21 + 4 44 71 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 145 146 165 @@ -292,25 +292,25 @@ __cstat - 94 + 51 BICOMP - 147 + 104 ICCARM - 122 + 79 BICOMP - 3 118 83 33 5 110 20 171 170 2 113 43 34 84 39 42 168 115 112 45 117 131 6 4 29 87 80 35 7 27 30 26 36 40 79 81 46 169 116 31 47 28 86 44 41 88 21 114 132 + 3 75 39 133 5 67 164 128 127 2 70 143 134 40 139 142 125 72 69 145 74 88 6 4 48 43 36 135 7 171 130 170 136 140 35 37 146 126 73 131 147 172 42 144 141 44 165 71 89 ICCARM - 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 29 7 6 27 170 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 2 4 88 114 5 3 132 131 45 46 21 + 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 48 7 6 171 127 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 2 4 44 71 5 3 89 88 145 146 165 @@ -319,25 +319,25 @@ __cstat - 96 + 53 BICOMP - 149 + 106 ICCARM - 124 + 81 BICOMP - 170 86 171 31 7 28 110 80 118 47 113 83 35 115 112 8 6 27 20 30 42 26 33 36 40 168 29 87 43 34 84 39 117 79 81 169 116 44 41 + 127 42 128 131 7 172 67 36 75 147 70 39 135 72 69 8 6 171 164 130 142 170 133 136 140 125 48 43 143 134 40 139 74 35 37 126 73 144 141 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 8 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 8 @@ -346,25 +346,25 @@ __cstat - 97 + 54 BICOMP - 150 + 107 ICCARM - 121 + 78 BICOMP - 28 80 7 171 170 29 87 35 118 31 86 113 110 83 43 34 84 39 47 44 41 40 169 116 6 27 20 30 42 26 33 36 168 117 79 81 115 112 + 172 36 7 128 127 48 43 135 75 131 42 70 67 39 143 134 40 139 147 144 141 140 126 73 6 171 164 130 142 170 133 136 125 74 35 37 72 69 ICCARM - 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 29 7 6 27 170 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 48 7 6 171 127 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -373,25 +373,25 @@ __cstat - 98 + 55 BICOMP - 151 + 108 ICCARM - 120 + 77 BICOMP - 26 116 6 27 30 36 170 40 171 20 42 33 168 29 87 83 118 7 31 47 28 86 113 110 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 170 73 6 171 130 136 127 140 128 164 142 133 125 48 43 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -400,52 +400,25 @@ __cstat - 99 - - - BICOMP - 152 - - - ICCARM - 127 - - - - - BICOMP - 47 116 113 83 171 170 7 31 28 86 110 118 6 27 20 30 42 26 33 36 40 168 29 87 169 44 41 80 43 34 84 35 39 117 79 81 115 112 - - - ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 - - - - - $PROJ_DIR$\..\Src\sd_diskio.c - - - __cstat - 95 + 56 BICOMP - 148 + 109 ICCARM - 123 + 84 BICOMP - 118 170 31 113 83 114 28 169 29 88 132 47 86 110 44 115 112 24 46 5 3 7 6 27 20 30 26 33 36 40 168 87 116 171 81 45 80 43 34 84 35 39 117 41 131 + 147 73 70 39 128 127 7 131 172 42 67 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 30 42 79 26 41 81 33 115 36 112 45 46 114 88 5 3 24 38 37 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -454,25 +427,25 @@ __cstat - 100 + 57 BICOMP - 153 + 110 ICCARM - 126 + 83 BICOMP - 33 87 116 20 42 168 29 171 170 7 6 27 30 26 36 40 83 118 31 47 28 86 113 110 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 133 43 73 164 142 125 48 128 127 7 6 171 130 170 136 140 39 75 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -481,25 +454,25 @@ __cstat - 101 + 58 BICOMP - 154 + 111 ICCARM - 163 + 120 BICOMP - 30 170 40 116 27 36 6 26 171 20 42 33 168 29 87 83 118 7 31 47 28 86 113 110 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 130 127 140 73 171 136 6 170 128 164 142 133 125 48 43 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -508,25 +481,25 @@ __cstat - 102 + 59 BICOMP - 155 + 112 ICCARM - 162 + 119 BICOMP - 87 33 116 20 42 168 29 171 170 6 27 30 26 36 40 83 118 7 31 47 28 86 113 110 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 43 133 73 164 142 125 48 128 127 6 171 130 170 136 140 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -535,25 +508,25 @@ __cstat - 103 + 60 BICOMP - 156 + 113 ICCARM - 130 + 87 BICOMP - 26 116 6 27 30 36 170 40 171 20 42 33 168 29 87 83 118 7 31 47 28 86 113 110 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 170 73 6 171 130 136 127 140 128 164 142 133 125 48 43 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -562,25 +535,25 @@ __cstat - 104 + 61 BICOMP - 157 + 114 ICCARM - 129 + 86 BICOMP - 33 87 116 20 42 168 29 171 170 7 6 27 30 26 36 40 83 118 31 47 28 86 113 110 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 133 43 73 164 142 125 48 128 127 7 6 171 130 170 136 140 39 75 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -589,25 +562,25 @@ __cstat - 105 + 62 BICOMP - 158 + 115 ICCARM - 128 + 85 BICOMP - 28 116 7 110 31 86 171 170 47 113 83 118 6 27 20 30 42 26 33 36 40 168 29 87 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 172 73 7 67 131 42 128 127 147 70 39 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -616,25 +589,25 @@ __cstat - 106 + 63 BICOMP - 159 + 116 ICCARM - 167 + 124 BICOMP - 20 116 33 87 42 168 29 171 170 6 27 30 26 36 40 83 118 7 31 47 28 86 113 110 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 164 73 133 43 142 125 48 128 127 6 171 130 170 136 140 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -643,25 +616,25 @@ __cstat - 107 + 64 BICOMP - 160 + 117 ICCARM - 166 + 123 BICOMP - 47 116 113 83 171 170 7 31 28 86 110 118 6 27 20 30 42 26 33 36 40 168 29 87 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 147 73 70 39 128 127 7 131 172 42 67 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -670,25 +643,25 @@ __cstat - 108 + 65 BICOMP - 161 + 118 ICCARM - 165 + 122 BICOMP - 116 113 83 47 171 170 7 31 28 86 110 118 6 27 20 30 42 26 33 36 40 168 29 87 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 73 70 39 147 128 127 7 131 172 42 67 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -697,25 +670,25 @@ __cstat - 109 + 66 BICOMP - 69 + 151 ICCARM - 164 + 121 BICOMP - 42 168 29 116 20 33 87 171 170 6 27 30 26 36 40 83 118 7 31 47 28 86 113 110 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 142 125 48 73 164 133 43 128 127 6 171 130 170 136 140 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -724,25 +697,25 @@ __cstat - 66 + 148 BICOMP - 70 + 152 ICCARM - 138 + 95 BICOMP - 86 116 31 7 28 110 171 170 47 113 83 118 6 27 20 30 42 26 33 36 40 168 29 87 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 42 73 131 7 172 67 128 127 147 70 39 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -751,25 +724,25 @@ __cstat - 67 + 149 BICOMP - 71 + 153 ICCARM - 139 + 96 BICOMP - 33 116 20 110 42 171 170 7 6 27 30 26 36 31 86 83 118 47 28 113 169 44 41 29 40 168 87 80 43 34 84 35 39 117 79 81 115 112 + 133 73 164 67 142 128 127 7 6 171 130 170 136 131 42 39 75 147 172 70 126 144 141 48 140 125 43 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -778,25 +751,25 @@ __cstat - 68 + 150 BICOMP - 72 + 154 ICCARM - 140 + 97 BICOMP - 31 116 86 7 28 110 171 170 47 113 83 118 6 27 20 30 42 26 33 36 40 168 29 87 169 44 41 80 43 34 84 35 39 117 79 81 115 112 + 131 73 42 7 172 67 128 127 147 70 39 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 ICCARM - 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 @@ -805,25 +778,25 @@ __cstat - 95 + 52 BICOMP - 148 + 105 ICCARM - 123 + 80 BICOMP - 132 47 80 118 114 29 113 83 171 170 88 31 28 86 110 35 115 112 21 46 5 3 7 6 27 20 30 42 26 33 36 40 168 87 43 34 84 39 117 79 81 45 169 116 44 41 131 + 89 147 36 75 71 48 70 39 128 127 44 131 172 42 67 135 72 69 165 146 5 3 7 6 171 164 130 142 170 133 136 140 125 43 143 134 40 139 74 35 37 145 126 73 144 141 88 ICCARM - 45 46 114 88 5 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 3 132 131 21 + 145 146 71 44 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 165 @@ -832,25 +805,25 @@ __cstat - 91 + 47 BICOMP - 23 + 167 ICCARM - 22 + 166 BICOMP - 79 29 113 83 114 132 47 31 28 86 110 43 171 34 84 39 117 170 81 5 3 7 6 27 20 30 42 26 33 36 40 168 87 80 35 118 115 112 88 169 116 44 41 131 + 35 48 70 39 71 89 147 131 172 42 67 143 128 134 40 139 74 127 37 5 3 7 6 171 164 130 142 170 133 136 140 125 43 36 135 75 72 69 44 126 73 144 141 88 ICCARM - 88 114 5 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 3 132 131 + 44 71 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 @@ -859,25 +832,25 @@ __cstat - 19 + 163 BICOMP - 73 + 155 ICCARM - 141 + 98 BICOMP - 5 20 79 114 83 33 87 42 168 29 46 3 7 6 27 30 26 36 170 40 43 171 34 84 39 117 81 45 88 132 31 47 28 86 113 110 80 35 118 115 112 169 116 44 41 131 + 5 164 35 71 39 133 43 142 125 48 146 3 7 6 171 130 170 136 127 140 143 128 134 40 139 74 37 145 44 89 131 147 172 42 70 67 36 135 75 72 69 126 73 144 141 88 ICCARM - 46 114 45 88 5 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 3 132 131 + 146 71 145 44 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 @@ -886,25 +859,25 @@ __cstat - 17 + 161 BICOMP - 74 + 156 ICCARM - 142 + 99 BICOMP - 115 29 113 83 35 118 170 132 47 112 114 31 28 86 110 80 171 46 5 3 7 6 27 20 30 42 26 33 36 40 168 87 43 34 84 39 117 79 81 88 169 116 44 41 131 + 72 48 70 39 135 75 127 89 147 69 71 131 172 42 67 36 128 146 5 3 7 6 171 164 130 142 170 133 136 140 125 43 143 134 40 139 74 35 37 44 126 73 144 141 88 ICCARM - 88 114 5 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 3 132 131 46 + 44 71 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 146 @@ -913,63 +886,90 @@ __cstat - 78 + 160 BICOMP - 75 + 157 ICCARM - 143 + 100 BICOMP - 26 79 6 5 3 7 27 30 36 170 40 88 20 42 33 168 29 87 43 171 34 84 39 117 81 46 83 114 132 31 47 28 86 113 110 80 35 118 115 112 45 169 116 44 41 131 + 170 35 6 5 3 7 171 130 136 127 140 44 164 142 133 125 48 43 143 128 134 40 139 74 37 146 39 71 89 131 147 172 42 70 67 36 135 75 72 69 145 126 73 144 141 88 ICCARM - 45 46 114 88 5 29 7 6 27 170 40 113 110 83 171 118 34 84 35 80 116 39 169 43 87 86 168 117 31 47 44 28 20 30 42 79 26 41 81 33 115 36 112 3 132 131 + 145 146 71 44 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 - $PROJ_DIR$\L476\Exe\stm32-bootloader.out + $PROJ_DIR$\..\Src\sd.c - OBJCOPY - 77 - + BICOMP + 90 + + + ICCARM + 91 + + + + + BICOMP + 127 3 172 128 131 70 39 73 75 2 147 42 67 44 4 48 7 6 171 164 130 142 170 133 136 140 125 43 126 144 141 145 5 71 36 143 134 40 135 139 74 35 37 72 69 89 88 146 + + + + + $PROJ_DIR$\L476\Exe\stm32-bootloader.out + ILINK - 18 + 162 + + + OBJCOPY + 159 ILINK - 172 119 137 141 125 142 143 122 123 144 120 127 126 163 162 130 129 128 167 166 165 164 138 139 124 140 22 121 32 111 82 85 + 129 76 94 98 82 99 100 79 80 101 77 84 83 120 119 87 86 85 124 123 122 121 95 96 81 97 166 78 132 68 38 41 - $PROJ_DIR$\..\Src\sd.c + $PROJ_DIR$\..\Src\sd_diskio.c + + __cstat + 52 + BICOMP - 133 + 105 ICCARM - 134 + 80 BICOMP - 170 3 28 171 31 113 83 116 118 2 47 86 110 88 4 29 7 6 27 20 30 42 26 33 36 40 168 87 169 44 41 45 5 114 80 43 34 84 35 39 117 79 81 115 112 132 131 46 + 75 127 131 70 39 71 172 126 48 44 89 147 42 67 144 72 69 168 146 5 3 7 6 171 164 130 170 133 136 140 125 43 73 128 37 145 36 143 134 40 135 139 74 141 88 + + + ICCARM + 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 130 142 35 170 141 37 133 72 136 69 145 146 71 44 5 3 168 138 137 @@ -1002,29 +1002,35 @@ $PROJ_DIR$\..\Src\system_stm32l4xx.c $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\option\syscall.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc_ex.h + $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmInstr.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h + $TOOLKIT_DIR$\lib\m7M_tls.a + $TOOLKIT_DIR$\inc\c\stdint.h + $TOOLKIT_DIR$\inc\c\DLib_Config_Full.h + $TOOLKIT_DIR$\lib\dl7M_tlf.a + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h + $PROJ_DIR$\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\system_stm32l4xx.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.h $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_cortex.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc_ex.h - $TOOLKIT_DIR$\lib\shb_l.a - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr.h - $TOOLKIT_DIR$\inc\c\DLib_Defaults.h - $TOOLKIT_DIR$\inc\c\DLib_Product.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_sd.h - $TOOLKIT_DIR$\inc\c\intrinsics.h - $PROJ_DIR$\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc.h - $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmSimd.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h - $PROJ_DIR$\L496\Obj\stm32l4xx_hal_crc.pbi $PROJ_DIR$\L496\Obj\stm32l4xx_hal_crc_ex.pbi $PROJ_DIR$\L496\Obj\stm32l4xx_hal_dma.pbi $PROJ_DIR$\L496\Obj\stm32l4xx_hal_flash.pbi @@ -1110,34 +1116,7 @@ $PROJ_DIR$\L496\Obj\system_stm32l4xx.pbi $PROJ_DIR$\L496\Obj\stm32l4xx_hal.pbi $PROJ_DIR$\L496\Obj\stm32l4xx_hal_cortex.pbi - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\option\syscall.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc_ex.h - $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmInstr.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h - $TOOLKIT_DIR$\lib\m7M_tls.a - $TOOLKIT_DIR$\inc\c\stdint.h - $TOOLKIT_DIR$\inc\c\DLib_Config_Full.h - $TOOLKIT_DIR$\lib\dl7M_tlf.a - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h - $PROJ_DIR$\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\system_stm32l4xx.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.h + $PROJ_DIR$\L496\Obj\stm32l4xx_hal_crc.pbi $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cm4.h $TOOLKIT_DIR$\lib\rt7M_tl.a $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_sdmmc.h @@ -1152,13 +1131,34 @@ $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmFunc.h $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_def.h $TOOLKIT_DIR$\inc\c\ycheck.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_cortex.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc_ex.h + $TOOLKIT_DIR$\lib\shb_l.a + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_sd.h + $TOOLKIT_DIR$\inc\c\intrinsics.h + $PROJ_DIR$\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc.h + $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmSimd.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h [ROOT_NODE] ILINK - 55 93 + 61 99 @@ -1167,7 +1167,7 @@ AARM - 116 + 122 @@ -1176,7 +1176,7 @@ AARM - 80 + 86 @@ -1185,25 +1185,25 @@ __cstat - 59 + 65 BICOMP - 117 + 123 ICCARM - 77 + 83 BICOMP - 32 24 160 165 147 155 22 153 164 21 2 81 151 158 38 150 166 35 157 31 144 34 27 148 28 30 7 6 20 17 23 33 19 26 29 163 159 143 145 + 136 144 39 156 145 45 132 157 150 40 153 162 149 147 42 158 2 87 43 36 151 139 7 6 165 146 164 152 155 134 154 143 137 161 166 142 138 35 37 ICCARM - 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 22 7 6 20 165 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 2 + 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 45 7 6 165 144 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 2 @@ -1212,25 +1212,25 @@ __cstat - 60 + 66 BICOMP - 73 + 79 ICCARM - 67 + 73 BICOMP - 147 31 33 17 26 28 160 7 6 20 23 19 29 165 163 22 153 144 166 24 38 21 150 81 151 34 27 148 30 159 143 145 3 164 158 35 32 157 155 + 156 162 149 147 42 151 139 7 6 165 146 164 152 87 43 36 145 144 45 161 166 154 142 132 39 157 150 40 153 138 35 37 3 143 137 158 155 136 134 ICCARM - 3 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 3 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1239,25 +1239,25 @@ __cstat - 62 + 68 BICOMP - 118 + 124 ICCARM - 79 + 85 BICOMP - 24 147 5 38 150 165 36 3 7 21 81 151 34 166 27 148 30 159 143 145 161 6 152 18 156 22 162 20 17 23 33 19 26 29 31 163 153 144 28 160 37 4 164 158 35 32 157 155 + 144 39 5 161 132 159 3 7 142 45 147 166 154 157 145 150 40 153 138 35 37 140 6 44 163 135 141 165 162 146 156 164 149 152 42 87 43 36 151 139 160 4 143 137 158 155 136 134 ICCARM - 4 152 156 5 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 3 162 161 36 37 18 + 4 44 135 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 159 160 163 @@ -1266,25 +1266,25 @@ __cstat - 61 + 67 BICOMP - 119 + 125 ICCARM - 78 + 84 BICOMP - 3 165 147 5 21 2 81 151 34 166 27 148 30 24 160 32 155 36 159 161 6 4 22 153 144 28 7 38 150 35 157 37 31 164 158 20 17 23 33 19 26 29 163 143 145 152 18 156 162 + 3 137 147 144 39 149 5 162 42 158 2 87 43 139 156 145 136 159 138 140 6 4 45 132 143 165 146 164 152 155 134 160 154 36 157 150 40 151 153 7 161 166 142 35 37 44 163 135 141 ICCARM - 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 22 7 6 20 165 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 2 4 152 156 5 3 162 161 36 37 18 + 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 45 7 6 165 144 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 2 4 44 135 5 3 141 140 159 160 163 @@ -1293,25 +1293,25 @@ __cstat - 63 + 69 BICOMP - 121 + 127 ICCARM - 96 + 102 BICOMP - 165 20 29 153 23 7 6 19 163 22 17 33 26 31 147 164 160 32 155 8 24 38 21 150 81 151 158 166 35 157 144 34 27 148 28 30 159 143 145 + 144 165 152 146 7 6 164 87 43 162 156 149 147 42 143 139 155 134 8 161 166 154 142 45 132 39 137 145 158 136 36 157 150 40 151 153 138 35 37 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 8 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 8 @@ -1320,25 +1320,25 @@ __cstat - 64 + 70 BICOMP - 122 + 128 ICCARM - 97 + 103 BICOMP - 163 7 6 147 144 19 22 153 28 160 20 23 29 165 166 81 151 34 27 148 30 17 33 26 31 159 143 145 164 158 24 38 21 150 35 32 157 155 + 142 139 137 39 45 132 161 144 145 87 43 143 147 166 154 138 35 37 36 157 150 40 151 153 7 6 165 162 146 156 164 149 152 42 158 155 136 134 ICCARM - 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 22 7 6 20 165 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 45 7 6 165 144 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1347,25 +1347,25 @@ __cstat - 58 + 64 BICOMP - 123 + 129 ICCARM - 98 + 104 BICOMP - 38 150 24 28 160 21 81 151 144 166 165 7 6 20 17 23 33 19 26 29 31 163 22 153 147 34 27 148 30 159 143 145 164 158 35 32 157 155 + 132 161 144 142 45 151 139 147 166 154 39 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1374,44 +1374,25 @@ __cstat - 71 + 77 BICOMP - 124 + 130 ICCARM - 99 + 105 BICOMP - 33 31 147 17 26 28 160 7 6 20 23 19 29 165 163 22 153 144 166 24 38 21 150 81 151 34 27 148 30 159 143 145 164 158 35 32 157 155 + 156 162 149 147 42 151 139 7 6 165 146 164 152 87 43 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 - - - - - $PROJ_DIR$\L496\Exe\stm32-bootloader.out - - - OBJCOPY - 57 - - - ILINK - 93 - - - - - ILINK - 94 77 67 113 79 114 115 78 95 80 98 99 100 101 102 103 104 105 106 107 108 109 110 111 96 112 66 97 25 154 146 149 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1420,25 +1401,25 @@ __cstat - 75 + 81 BICOMP - 39 + 131 ICCARM - 100 + 106 BICOMP - 21 24 81 151 28 160 7 38 150 144 166 165 6 20 17 23 33 19 26 29 31 163 22 153 147 34 27 148 30 159 143 145 164 158 35 32 157 155 + 166 154 39 147 151 139 7 161 144 142 45 132 36 145 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1447,25 +1428,25 @@ __cstat - 65 + 71 BICOMP - 40 + 46 ICCARM - 101 + 107 BICOMP - 38 24 150 28 160 21 81 151 144 166 165 7 6 20 17 23 33 19 26 29 31 163 22 153 147 34 27 148 30 159 143 145 164 158 35 32 157 155 + 142 45 161 144 132 151 139 147 166 154 39 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1474,25 +1455,25 @@ __cstat - 76 + 82 BICOMP - 41 + 47 ICCARM - 102 + 108 BICOMP - 21 24 81 151 28 160 38 150 144 166 165 7 6 20 17 23 33 19 26 29 31 163 22 153 147 34 27 148 30 159 143 145 164 158 35 32 157 155 + 166 154 39 147 151 139 161 144 142 45 132 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1501,25 +1482,25 @@ __cstat - 74 + 80 BICOMP - 42 + 48 ICCARM - 103 + 109 BICOMP - 38 24 150 28 160 21 81 151 144 166 165 7 6 20 17 23 33 19 26 29 31 163 22 153 147 34 27 148 30 159 143 145 164 158 35 32 157 155 + 142 45 161 144 132 151 139 147 166 154 39 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1528,25 +1509,25 @@ __cstat - 68 + 74 BICOMP - 43 + 49 ICCARM - 104 + 110 BICOMP - 19 6 163 22 20 23 29 165 153 28 160 17 33 26 31 147 144 166 7 24 38 21 150 81 151 34 27 148 30 159 143 145 164 158 35 32 157 155 + 164 87 6 43 165 146 152 151 139 162 156 149 147 42 36 145 144 7 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1555,25 +1536,25 @@ __cstat - 70 + 76 BICOMP - 44 + 50 ICCARM - 105 + 111 BICOMP - 19 7 6 163 22 20 23 29 165 153 28 160 17 33 26 31 147 144 166 24 38 21 150 81 151 34 27 148 30 159 143 145 164 158 35 32 157 155 + 164 87 7 6 43 165 146 152 151 139 162 156 149 147 42 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1582,25 +1563,25 @@ __cstat - 69 + 75 BICOMP - 45 + 51 ICCARM - 106 + 112 BICOMP - 7 6 163 22 19 20 23 29 165 153 28 160 17 33 26 31 147 144 166 24 38 21 150 81 151 34 27 148 30 159 143 145 164 158 35 32 157 155 + 43 7 6 164 87 165 146 152 151 139 162 156 149 147 42 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1609,25 +1590,25 @@ __cstat - 84 + 90 BICOMP - 46 + 52 ICCARM - 107 + 113 BICOMP - 33 31 147 17 26 28 160 7 6 20 23 19 29 165 163 22 153 144 166 24 38 21 150 81 151 34 27 148 30 159 143 145 164 158 35 32 157 155 + 156 162 149 147 42 151 139 7 6 165 146 164 152 87 43 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1636,25 +1617,25 @@ __cstat - 83 + 89 BICOMP - 47 + 53 ICCARM - 108 + 114 BICOMP - 19 7 6 163 22 20 23 29 165 153 28 160 17 33 26 31 147 144 166 24 38 21 150 81 151 34 27 148 30 159 143 145 164 158 35 32 157 155 + 164 87 7 6 43 165 146 152 151 139 162 156 149 147 42 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1663,25 +1644,25 @@ __cstat - 88 + 94 BICOMP - 48 + 54 ICCARM - 109 + 115 BICOMP - 24 38 150 28 160 21 81 151 144 166 165 7 6 20 17 23 33 19 26 29 31 163 22 153 147 34 27 148 30 159 143 145 164 158 35 32 157 155 + 144 161 132 142 45 151 139 147 166 154 39 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1690,25 +1671,25 @@ __cstat - 85 + 91 BICOMP - 49 + 55 ICCARM - 110 + 116 BICOMP - 21 24 81 151 28 160 38 150 144 166 165 7 6 20 17 23 33 19 26 29 31 163 22 153 147 34 27 148 30 159 143 145 164 158 35 32 157 155 + 166 154 39 147 151 139 161 144 142 45 132 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1717,25 +1698,25 @@ __cstat - 89 + 95 BICOMP - 50 + 56 ICCARM - 111 + 117 BICOMP - 33 31 147 28 160 17 26 144 166 165 6 20 23 19 29 163 22 153 34 27 148 30 159 143 145 7 24 38 21 150 81 151 164 158 35 32 157 155 + 166 154 39 151 139 147 36 145 144 7 161 142 45 132 157 150 40 153 138 35 37 6 165 162 146 156 164 149 152 42 87 43 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1744,25 +1725,25 @@ __cstat - 92 + 98 BICOMP - 51 + 57 ICCARM - 112 + 118 BICOMP - 23 165 20 29 153 7 6 19 163 22 28 160 17 33 26 31 147 144 166 24 38 21 150 81 151 34 27 148 30 159 143 145 164 158 35 32 157 155 + 146 165 152 7 6 164 87 43 151 139 162 156 149 147 42 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 ICCARM - 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 + 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 @@ -1771,25 +1752,25 @@ __cstat - 90 + 96 BICOMP - 120 + 126 ICCARM - 95 + 101 BICOMP - 162 33 165 31 147 156 22 17 26 152 6 20 23 19 29 163 153 164 160 32 155 18 37 5 3 7 24 38 21 150 81 151 158 166 35 157 36 144 34 27 148 28 30 159 143 145 161 + 141 156 144 135 45 162 149 147 42 44 6 165 146 164 152 87 43 143 139 155 134 163 160 39 5 3 7 161 166 154 142 132 137 145 158 136 159 36 157 150 40 151 153 138 35 37 140 ICCARM - 36 37 156 152 5 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 3 162 161 18 + 159 160 135 44 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 163 @@ -1798,25 +1779,25 @@ __cstat - 87 + 93 BICOMP - 72 + 78 ICCARM - 66 + 72 BICOMP - 26 22 17 147 165 156 162 33 31 160 158 35 6 20 23 19 29 163 153 166 157 5 3 7 24 38 21 150 81 151 164 32 155 152 144 34 27 148 28 30 159 143 145 161 + 149 147 45 162 42 39 144 135 141 156 139 137 158 6 165 146 164 152 87 43 145 136 5 3 7 161 166 154 142 132 143 155 134 44 36 157 150 40 151 153 138 35 37 140 ICCARM - 152 156 5 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 3 162 161 + 44 135 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 @@ -1825,25 +1806,25 @@ __cstat - 82 + 88 BICOMP - 52 + 58 ICCARM - 113 + 119 BICOMP - 5 156 147 21 165 24 81 151 160 158 35 37 3 7 38 150 166 157 36 152 22 162 6 20 17 23 33 19 26 29 31 163 153 164 32 155 144 34 27 148 28 30 159 143 145 161 + 5 135 39 166 154 144 147 139 137 158 160 3 7 161 142 45 132 145 136 159 44 141 6 165 162 146 156 164 149 152 42 87 43 143 155 134 36 157 150 40 151 153 138 35 37 140 ICCARM - 37 156 36 152 5 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 3 162 161 + 160 135 159 44 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 @@ -1852,25 +1833,25 @@ __cstat - 91 + 97 BICOMP - 53 + 59 ICCARM - 114 + 120 BICOMP - 26 32 22 17 160 165 162 33 31 147 164 155 156 6 20 23 19 29 163 153 37 5 3 7 24 38 21 150 81 151 158 166 35 157 152 144 34 27 148 28 30 159 143 145 161 + 147 149 155 45 162 42 139 144 141 156 143 134 135 6 165 146 164 152 87 43 160 5 3 7 161 166 154 142 132 39 137 145 158 136 44 36 157 150 40 151 153 138 35 37 140 ICCARM - 152 156 5 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 3 162 161 37 + 44 135 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 160 @@ -1879,25 +1860,44 @@ __cstat - 86 + 92 BICOMP - 54 + 60 ICCARM - 115 + 121 BICOMP - 38 150 24 147 165 5 3 7 160 158 35 152 21 81 151 166 157 37 156 22 162 6 20 17 23 33 19 26 29 31 163 153 164 32 155 36 144 34 27 148 28 30 159 143 145 161 + 132 161 144 39 5 3 7 142 45 139 137 158 44 147 166 154 145 136 160 135 141 6 165 162 146 156 164 149 152 42 87 43 143 155 134 159 36 157 150 40 151 153 138 35 37 140 ICCARM - 36 37 156 152 5 22 7 6 20 165 31 81 153 147 166 160 27 148 28 144 158 30 164 34 151 150 163 159 24 38 35 21 17 23 33 143 19 32 145 26 157 29 155 3 162 161 + 159 160 135 44 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 + + + + + $PROJ_DIR$\L496\Exe\stm32-bootloader.out + + + ILINK + 99 + + + OBJCOPY + 63 + + + + + ILINK + 100 83 73 119 85 120 121 84 101 86 104 105 106 107 108 109 110 111 112 113 114 115 116 117 102 118 72 103 148 133 38 41 diff --git a/Inc/bootloader.h b/Inc/bootloader.h index b93a3f4..1e66165 100644 --- a/Inc/bootloader.h +++ b/Inc/bootloader.h @@ -16,21 +16,19 @@ #ifndef __BOOTLOADER_H #define __BOOTLOADER_H -/*** Bootloader configuration *************************************************/ -#define USE_SWO_TRACE 1 /* For development/debugging: stdout/stderr via SWO trace */ +/*** Bootloader Configuration *************************************************/ #define USE_CHECKSUM 0 /* Check application checksum on startup */ #define USE_WRITE_PROTECTION 0 /* Enable write protection after performing in-app-programming */ #define SET_VECTOR_TABLE 1 /* Automatically set vector table location before launching application */ #define CLEAR_RESET_FLAGS 1 /* If enabled: bootloader clears reset flags. (This occurs only when OBL RST flag is active.) If disabled: bootloader does not clear reset flags, not even when OBL RST is active. */ -#define APP_FILENAME "image.bin" /* File name of application located on SD card */ #define APP_ADDRESS (uint32_t)0x08008000 /* Start address of application space in flash */ #define END_ADDRESS (uint32_t)0x080FFFFB /* End address of application space (addr. of last byte) */ #define CRC_ADDRESS (uint32_t)0x080FFFFC /* Start address of application checksum in flash */ #define SYSMEM_ADDRESS (uint32_t)0x1FFF0000 /* Address of System Memory (ST Bootloader) */ -/*** End of configuration *****************************************************/ +/******************************************************************************/ /* Defines -------------------------------------------------------------------*/ #define FLASH_PAGE_NBPERBANK 256 /* Number of pages per bank in flash */ diff --git a/Inc/main.h b/Inc/main.h index 4999d5f..243811f 100644 --- a/Inc/main.h +++ b/Inc/main.h @@ -1,6 +1,13 @@ #ifndef __MAIN_H #define __MAIN_H +/*** Application-Specific Configuration ***************************************/ +#define CONF_BUILD "2017-10-19" /* Bootloader build date */ +#define CONF_FILENAME "WGPS2.bin" /* File name of application located on SD card */ + +#define USE_SWO_TRACE 1 /* For development/debugging: stdout/stderr via SWO trace */ +/******************************************************************************/ + /* Hardware Defines ----------------------------------------------------------*/ #define BTN_Port GPIOE #define BTN_Pin GPIO_PIN_0 diff --git a/Src/main.c b/Src/main.c index 9222bd1..97251fc 100644 --- a/Src/main.c +++ b/Src/main.c @@ -177,7 +177,7 @@ void Enter_Bootloader(void) { print("SD mounted."); /* Open file */ - fr = f_open(&fil, APP_FILENAME, FA_READ); + fr = f_open(&fil, CONF_FILENAME, FA_READ); if(fr == FR_OK) { print("Software found on SD."); From 5c29804902ba77839a73c909d393ca9b2aadfa4a Mon Sep 17 00:00:00 2001 From: Akos Pasztor Date: Mon, 30 Oct 2017 11:03:11 +0100 Subject: [PATCH 2/2] update to HAL FW 1.10.0 --- .../Device/ST/STM32L4xx/Include/stm32l4xx.h | 4 +- .../Inc/Legacy/stm32_hal_legacy.h | 444 ++++----- .../Inc/stm32l4xx_hal_def.h | 22 +- .../Inc/stm32l4xx_hal_rcc.h | 2 +- .../Inc/stm32l4xx_hal_rcc_ex.h | 106 ++- .../Inc/stm32l4xx_ll_sdmmc.h | 81 +- .../STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c | 2 +- .../Src/stm32l4xx_hal_dma.c | 16 +- .../Src/stm32l4xx_hal_dma_ex.c | 4 +- .../Src/stm32l4xx_hal_flash_ex.c | 2 +- .../Src/stm32l4xx_hal_rcc_ex.c | 413 ++++---- .../Src/stm32l4xx_hal_sd.c | 83 +- .../Src/stm32l4xx_hal_sd_ex.c | 6 +- .../Src/stm32l4xx_ll_sdmmc.c | 19 +- EWARM/stm32-bootloader.dep | 900 +++++++++--------- EWARM/stm32-bootloader.ewp | 12 + EWARM/stm32-bootloader.ewt | 6 + Inc/main.h | 2 +- Inc/stm32l4xx_hal_conf.h | 150 ++- 19 files changed, 1172 insertions(+), 1102 deletions(-) diff --git a/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h b/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h index 43593a8..2899a67 100644 --- a/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h +++ b/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h @@ -114,11 +114,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number $VERSION$ + * @brief CMSIS Device version number */ #define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 0e03a8b..f58ae44 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @brief This file contains aliases definition for the STM32Cube HAL constants + * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention @@ -58,7 +58,7 @@ /** * @} */ - + /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ @@ -90,10 +90,10 @@ #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 @@ -109,21 +109,21 @@ #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 /** * @} */ - + /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} - */ - + */ + /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ @@ -154,7 +154,7 @@ #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - + #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT @@ -226,7 +226,7 @@ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ - + #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE @@ -255,27 +255,27 @@ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - + + + /** * @} */ @@ -283,7 +283,7 @@ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ - + #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD @@ -359,11 +359,11 @@ /** * @} */ - + /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ - + #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 @@ -376,12 +376,12 @@ /** * @} */ - + /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 @@ -399,7 +399,7 @@ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ - + #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** @@ -432,17 +432,17 @@ #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) @@ -459,7 +459,7 @@ /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose * @{ */ - + #if defined(STM32H7) #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE @@ -468,8 +468,8 @@ #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE - #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 - #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 + #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX @@ -521,13 +521,13 @@ #endif /* STM32H7 */ - - + + /** * @} - */ - - + */ + + /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ @@ -540,7 +540,7 @@ #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - + #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD @@ -613,7 +613,7 @@ #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ @@ -643,7 +643,7 @@ /** * @} */ - + /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ @@ -667,11 +667,11 @@ #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - + #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 @@ -680,14 +680,14 @@ #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + /** * @} */ @@ -696,7 +696,7 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) +#if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** @@ -708,18 +708,18 @@ */ /* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD @@ -732,11 +732,11 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ - + #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD @@ -745,14 +745,14 @@ #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 @@ -760,15 +760,15 @@ #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 /** * @} */ - + /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ @@ -789,7 +789,7 @@ * @} */ - + /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ @@ -807,7 +807,7 @@ /** * @} */ - + /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ @@ -823,13 +823,13 @@ /** * @} */ - + /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - + #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR @@ -930,7 +930,7 @@ * @} */ - + /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ @@ -970,7 +970,7 @@ /** * @} */ - + /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ @@ -995,7 +995,7 @@ #define ETH_MMCRFCECR 0x00000194U #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U - + #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ @@ -1030,7 +1030,7 @@ /** * @} */ - + /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ @@ -1045,39 +1045,39 @@ /** * @} - */ - + */ + #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 /** * @} - */ + */ #endif /* STM32L4 || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1090,11 +1090,11 @@ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} - */ + */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish @@ -1104,12 +1104,12 @@ /*HASH Algorithm Selection*/ -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY @@ -1117,7 +1117,7 @@ /** * @} */ - + /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ @@ -1198,6 +1198,8 @@ #define CR_OFFSET_BB PWR_CR_OFFSET_BB #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB #define DBP_BitNumber DBP_BIT_NUMBER #define PVDE_BitNumber PVDE_BIT_NUMBER @@ -1211,17 +1213,17 @@ #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - + /** * @} - */ - + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ @@ -1232,7 +1234,7 @@ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} - */ + */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ @@ -1244,31 +1246,31 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ - + /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback #define HAL_LTDC_Relaod HAL_LTDC_Reload #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} - */ - - + */ + + /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1283,8 +1285,8 @@ #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} - */ - + */ + /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ @@ -1293,7 +1295,7 @@ #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK @@ -1313,7 +1315,7 @@ * @} */ - + /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ @@ -1409,7 +1411,7 @@ /** * @} */ - + /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ @@ -1482,7 +1484,7 @@ #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK - + #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -1669,7 +1671,7 @@ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ ((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_TRIANGLE)) - + /** * @} */ @@ -1688,11 +1690,11 @@ /** * @} */ - + /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START #if defined(STM32F1) @@ -1715,11 +1717,11 @@ /** * @} */ - + /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ - + #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT @@ -1730,7 +1732,7 @@ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ - + #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE @@ -1739,7 +1741,7 @@ #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** @@ -1768,8 +1770,8 @@ /** * @} */ - - + + /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ @@ -1834,7 +1836,7 @@ #if defined (STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else @@ -1842,17 +1844,17 @@ #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ -/** +/** * @} - */ - - + */ + + /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ - + #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI @@ -1869,8 +1871,8 @@ #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET @@ -2308,13 +2310,13 @@ #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE @@ -2367,111 +2369,111 @@ #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE @@ -2479,28 +2481,28 @@ #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET @@ -2700,7 +2702,7 @@ #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif #if defined(STM32F7) @@ -2904,12 +2906,12 @@ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ @@ -2952,7 +2954,7 @@ #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION @@ -2979,24 +2981,24 @@ #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn @@ -3005,8 +3007,8 @@ #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT @@ -3054,7 +3056,7 @@ #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} @@ -3086,7 +3088,7 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ @@ -3098,8 +3100,8 @@ #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} @@ -3204,7 +3206,7 @@ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG @@ -3213,7 +3215,7 @@ #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** @@ -3254,7 +3256,7 @@ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ - + /** * @} */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h index 72dee3c..bb9816b 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h @@ -83,14 +83,14 @@ typedef enum } while(0) #define UNUSED(x) ((void)(x)) - + /** @brief Reset the Handle's State field. * @param __HANDLE__: specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: + * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function + * Otherwise, "State" field may have any random value and the first time the function * HAL_PPP_Init() is called, the low level hardware initialization will be missed * (i.e. HAL_PPP_MspInit() will not be executed). * - When there is a need to reconfigure the low level hardware: instead of calling @@ -123,7 +123,7 @@ typedef enum }while (0) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -134,7 +134,7 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ @@ -186,14 +186,14 @@ typedef enum #endif -/** +/** * @brief __NOINLINE definition - */ + */ #if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- +/* ARM & GNUCompiler + ---------------- */ -#define __NOINLINE __attribute__ ( (noinline) ) +#define __NOINLINE __attribute__ ( (noinline) ) #elif defined ( __ICCARM__ ) /* ICCARM Compiler diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h index 2bcff3a..bf68dbd 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h @@ -1642,7 +1642,7 @@ typedef struct #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != RESET) #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h index fe7f4d5..d3e3f32 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h @@ -52,7 +52,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ @@ -119,7 +119,7 @@ typedef struct #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock. This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ -#endif +#endif uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ @@ -190,7 +190,7 @@ typedef struct uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ - + #if defined(I2C4) uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. @@ -281,8 +281,8 @@ typedef struct #if defined(CRS) -/** - * @brief RCC_CRS Init structure definition +/** + * @brief RCC_CRS Init structure definition */ typedef struct { @@ -307,8 +307,8 @@ typedef struct }RCC_CRSInitTypeDef; -/** - * @brief RCC_CRS Synchronization structure definition +/** + * @brief RCC_CRS Synchronization structure definition */ typedef struct { @@ -318,12 +318,12 @@ typedef struct uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. This parameter must be a number between 0 and 0x3F */ - uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. This parameter must be a number between 0 and 0xFFFF */ - uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the - frequency error counter latched in the time of the last SYNC event. + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ @@ -512,7 +512,7 @@ typedef struct /** * @} */ - + #if defined(I2C4) /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source * @{ @@ -523,7 +523,7 @@ typedef struct /** * @} */ -#endif /* I2C4 */ +#endif /* I2C4 */ /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source * @{ @@ -555,7 +555,7 @@ typedef struct #define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 -#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 +#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) #define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 #else @@ -595,13 +595,16 @@ typedef struct * @{ */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U) +#define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U) /*!< HSI48 clock selected as SDMMC1 clock */ #else -#define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as SDMMC1 clock */ #endif /* RCC_HSI48_SUPPORT */ -#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 -#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 -#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL +#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ +#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ +#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */ +#if defined(RCC_CCIPR2_SDMMCSEL) +#define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */ +#endif /* RCC_CCIPR2_SDMMCSEL */ /** * @} */ @@ -787,12 +790,12 @@ typedef struct /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault * @{ */ -#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds +#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ /** * @} */ - + /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault * @{ */ @@ -804,9 +807,9 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. +#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value - corresponds to a higher output frequency */ + corresponds to a higher output frequency */ /** * @} */ @@ -834,7 +837,7 @@ typedef struct /** * @} */ - + /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags * @{ */ @@ -914,7 +917,7 @@ typedef struct ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) - + #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ #else @@ -934,7 +937,7 @@ typedef struct (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)) - + #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ @@ -993,7 +996,7 @@ typedef struct #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) - + #else #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ @@ -1119,7 +1122,7 @@ typedef struct ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) -# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ @@ -1147,7 +1150,7 @@ typedef struct ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) -# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ @@ -1160,7 +1163,7 @@ typedef struct WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)) - + # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ @@ -1353,7 +1356,7 @@ typedef struct * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) * - * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 + * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 * clock source when PLLs are disabled for devices without PLLSAI2. * */ @@ -1697,33 +1700,34 @@ typedef struct @if STM32L486xx * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock @endif @if STM32L443xx * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock @endif @if STM32L4S9xx * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock @endif - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock * @retval None */ #if defined(RCC_CCIPR2_SDMMCSEL) #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ do \ { \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \ - if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) \ + if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ { \ SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ } \ else \ { \ CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \ } \ } while(0) #else @@ -1747,12 +1751,13 @@ typedef struct * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock @endif * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock */ #if defined(RCC_CCIPR2_SDMMCSEL) #define __HAL_RCC_GET_SDMMC1_SOURCE() \ - ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLL : ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))) + ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))) #else #define __HAL_RCC_GET_SDMMC1_SOURCE() \ ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) @@ -2118,8 +2123,8 @@ typedef struct do { \ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - + } while(0) + /** * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. * @retval None. @@ -2128,7 +2133,7 @@ typedef struct do { \ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0) /** * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. @@ -2265,7 +2270,7 @@ typedef struct /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features * @{ - */ + */ /** * @brief Enable the oscillator clock for frequency error counter. * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. @@ -2294,8 +2299,8 @@ typedef struct /** * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency - * of the synchronization source after prescaling. It is then decreased by one in order to + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to * reach the expected synchronization on the zero value. The formula is the following: * RELOAD = (fTARGET / fSYNC) -1 * @param __FTARGET__ Target frequency (value in Hz) @@ -2715,7 +2720,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) - + #if defined(I2C4) #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ @@ -2783,7 +2788,16 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) #if defined(SDMMC1) -#if defined(RCC_HSI48_SUPPORT) +#if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL) + +#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) + +#elif defined(RCC_HSI48_SUPPORT) #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ @@ -2971,7 +2985,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) - + #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) diff --git a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h index 744b137..41996af 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h +++ b/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h @@ -623,42 +623,38 @@ typedef struct /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources * @{ */ -#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL -#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL -#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT -#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT -#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR -#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR -#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND -#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT -#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND -#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND -#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE -#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF -#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF -#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF -#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE -#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE -#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT +#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE +#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE +#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE +#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE +#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE +#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE +#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE +#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE +#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE +#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE +#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE +#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE +#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE +#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE +#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define SDMMC_IT_DHOLD SDMMC_STA_DHOLD -#define SDMMC_IT_DABORT SDMMC_STA_DABORT -#define SDMMC_IT_DPSMACT SDMMC_STA_DPSMACT -#define SDMMC_IT_CMDACT SDMMC_STA_CPSMACT -#define SDMMC_IT_BUSYD0 SDMMC_STA_BUSYD0 -#define SDMMC_IT_BUSYD0END SDMMC_STA_BUSYD0END -#define SDMMC_IT_ACKFAIL SDMMC_STA_ACKFAIL -#define SDMMC_IT_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT -#define SDMMC_IT_VSWEND SDMMC_STA_VSWEND -#define SDMMC_IT_CKSTOP SDMMC_STA_CKSTOP -#define SDMMC_IT_IDMATE SDMMC_STA_IDMATE -#define SDMMC_IT_IDMABTC SDMMC_STA_IDMABTC +#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE +#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE +#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE +#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE +#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE +#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE +#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE +#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE #else -#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT -#define SDMMC_IT_TXACT SDMMC_STA_TXACT -#define SDMMC_IT_RXACT SDMMC_STA_RXACT -#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL -#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL +#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE +#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE +#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE +#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE +#define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE +#define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE +#define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} @@ -713,11 +709,26 @@ typedef struct SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) + +#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ + SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) + +#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ + SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ + SDMMC_FLAG_IDMABTC)) + #else #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ - SDMMC_FLAG_DBCKEND)) + SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT)) + +#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ + SDMMC_FLAG_CMDSENT)) + +#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c index 997e988..907a6b7 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c +++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c @@ -69,7 +69,7 @@ */ #define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ -#define __STM32L4xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L4xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\ |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\ diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c index f79737c..9963ae8 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c +++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c @@ -18,17 +18,15 @@ necessary). Please refer to the Reference manual for connection between peripherals and DMA requests. - __HAL_RCC_DMAMUX1_CLK_ENABLE - (#) For a given Channel, program the required configuration through the following parameters: Channel request, Transfer Direction, Source and Destination data formats, Circular or Normal mode, Channel Priority level, Source and Destination Increment mode using HAL_DMA_Init() function. - Prior to HAL_DMA_Init the CLK shall be enabled for both DMA & DMAMUX + Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX thanks to: - DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; - DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); + (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; + (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. @@ -36,6 +34,7 @@ (#) Use HAL_DMA_Abort() function to abort the current transfer -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** ================================= [..] @@ -54,13 +53,12 @@ In this case the DMA interrupt is configured (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e. a member of DMA handle structure). + add his own function to register callbacks with HAL_DMA_RegisterCallback(). *** DMA HAL driver macros list *** ============================================= [..] - Below the list of most used macros in DMA HAL driver. + Below the list of macros in DMA HAL driver. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. @@ -68,7 +66,7 @@ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. [..] (@) You can refer to the DMA HAL driver header file for more useful macros diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c index a694063..50b09d5 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c +++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c @@ -94,8 +94,8 @@ =============================================================================== [..] This section provides functions allowing to: - (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. - (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used to respectively enable/disable the request generator. diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c index 039a561..1ba98a0 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c +++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c @@ -122,7 +122,7 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PC */ /* Exported functions -------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c index 7b4244d..866f5a2 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c +++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c @@ -97,7 +97,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u * @{ */ -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim @@ -325,7 +325,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) { FlagStatus pwrclkchanged = RESET; - + /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); @@ -335,7 +335,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } - + /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); @@ -352,10 +352,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } if(ret == HAL_OK) - { + { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); - + if((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != PeriphClkInit->RTCClockSelection)) { /* Store the content of BDCR register before the reset of Backup Domain */ @@ -383,7 +383,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - + if(ret == HAL_OK) { /* Apply new RTC clock source selection */ @@ -504,7 +504,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } -#if defined(I2C2) +#if defined(I2C2) /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) @@ -528,7 +528,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); } -#if defined(I2C4) +#if defined(I2C4) /*-------------------------- I2C4 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) @@ -561,7 +561,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -580,17 +580,24 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); - - if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) + + if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */ { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } +#if defined(RCC_CCIPR2_SDMMCSEL) + else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */ + { + /* Enable PLLSAI3CLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); + } +#endif else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -616,7 +623,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -633,7 +640,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); - + if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ @@ -652,7 +659,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -728,16 +735,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk break; } } - + if(ret == HAL_OK) { /* Configure the LTDC clock source */ __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection); - + /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); } - + if(ret != HAL_OK) { /* set overall return value */ @@ -762,7 +769,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */ ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -855,7 +862,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ RCC_PERIPHCLK_RTC ; - + #elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ @@ -899,7 +906,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) #endif /* STM32L431xx */ /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ - + PeriphClkInit->PLLSAI1.PLLSAI1Source = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos); #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) PeriphClkInit->PLLSAI1.PLLSAI1M = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U; @@ -949,7 +956,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the UART5 clock source ----------------------------------------------*/ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); #endif /* UART5 */ - + /* Get the LPUART1 clock source --------------------------------------------*/ PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); @@ -1034,7 +1041,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } /** - * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs + * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs * @note Return 0 if peripheral clock identifier not managed by this API * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: @@ -1152,7 +1159,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) else { /* Other external peripheral clock source than RTC */ - + /* Compute PLL clock input */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) /* MSI ? */ { @@ -1208,7 +1215,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(PeriphClk == RCC_PERIPHCLK_SAI1) { srcclk = __HAL_RCC_GET_SAI1_SOURCE(); - + if(srcclk == RCC_SAI1CLKSOURCE_PIN) { frequency = EXTERNAL_SAI1_CLOCK_VALUE; @@ -1218,14 +1225,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) else /* RCC_PERIPHCLK_SAI2 */ { srcclk = __HAL_RCC_GET_SAI2_SOURCE(); - + if(srcclk == RCC_SAI2CLKSOURCE_PIN) { frequency = EXTERNAL_SAI2_CLOCK_VALUE; } /* Else, PLL clock output to check below */ } - + #else case RCC_PERIPHCLK_SAI1: @@ -1233,14 +1240,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(PeriphClk == RCC_PERIPHCLK_SAI1) { srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL); - + if(srcclk == RCC_SAI1CLKSOURCE_PIN) { frequency = EXTERNAL_SAI1_CLOCK_VALUE; } /* Else, PLL clock output to check below */ } - + #endif /* SAI2 */ if(frequency == 0U) @@ -1254,7 +1261,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; #if defined(RCC_PLLP_DIV_2_31_SUPPORT) pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) @@ -1281,7 +1288,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; -#endif +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) @@ -1315,7 +1322,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; #if defined(RCC_PLLP_DIV_2_31_SUPPORT) pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) @@ -1327,7 +1334,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) pllp = 7U; } } - + frequency = (pllvco * plln) / pllp; } else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) @@ -1339,7 +1346,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* No clock source */ frequency = 0U; - } + } } else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1) { @@ -1353,7 +1360,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; -#endif +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) @@ -1365,7 +1372,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) pllp = 7U; } } - + frequency = (pllvco * plln) / pllp; } else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) @@ -1377,7 +1384,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* No clock source */ frequency = 0U; - } + } } #endif /* SAI2 */ @@ -1395,7 +1402,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos; -#endif +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET) @@ -1420,9 +1427,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } } break; - + #if defined(USB_OTG_FS) || defined(USB) - + case RCC_PERIPHCLK_USB: #endif /* USB_OTG_FS || USB */ @@ -1436,7 +1443,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) #endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */ srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); - + if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) @@ -1499,32 +1506,46 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } #endif /* RCC_HSI48_SUPPORT */ break; - + #if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) case RCC_PERIPHCLK_SDMMC1: - if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL ? */ + if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */ { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) { #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* f(PLL Source) / PLLM */ pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ + /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; } else { frequency = 0U; } } - else /* 48MHz from MSI or PLLSAI1Q or HSI48 */ + else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */ { srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); - + if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) @@ -1537,7 +1558,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = 0U; } } - else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL ? */ + else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL "Q" ? */ { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) { @@ -1587,7 +1608,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_USART1: /* Get the current USART1 source */ srcclk = __HAL_RCC_GET_USART1_SOURCE(); - + if(srcclk == RCC_USART1CLKSOURCE_PCLK2) { frequency = HAL_RCC_GetPCLK2Freq(); @@ -1614,7 +1635,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_USART2: /* Get the current USART2 source */ srcclk = __HAL_RCC_GET_USART2_SOURCE(); - + if(srcclk == RCC_USART2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1643,7 +1664,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_USART3: /* Get the current USART3 source */ srcclk = __HAL_RCC_GET_USART3_SOURCE(); - + if(srcclk == RCC_USART3CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1674,7 +1695,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_UART4: /* Get the current UART4 source */ srcclk = __HAL_RCC_GET_UART4_SOURCE(); - + if(srcclk == RCC_UART4CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1705,7 +1726,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_UART5: /* Get the current UART5 source */ srcclk = __HAL_RCC_GET_UART5_SOURCE(); - + if(srcclk == RCC_UART5CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1730,11 +1751,11 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; #endif /* UART5 */ - + case RCC_PERIPHCLK_LPUART1: /* Get the current LPUART1 source */ srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); - + if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1759,9 +1780,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; case RCC_PERIPHCLK_ADC: - + srcclk = __HAL_RCC_GET_ADC_SOURCE(); - + if(srcclk == RCC_ADCCLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); @@ -1806,7 +1827,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_DFSDM1: /* Get the current DFSDM1 source */ srcclk = __HAL_RCC_GET_DFSDM1_SOURCE(); - + if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2) { frequency = HAL_RCC_GetPCLK2Freq(); @@ -1822,7 +1843,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_DFSDM1AUDIO: /* Get the current DFSDM1 audio source */ srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); - + if(srcclk == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) { frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); @@ -1850,7 +1871,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_I2C1: /* Get the current I2C1 source */ srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - + if(srcclk == RCC_I2C1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1875,7 +1896,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_I2C2: /* Get the current I2C2 source */ srcclk = __HAL_RCC_GET_I2C2_SOURCE(); - + if(srcclk == RCC_I2C2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1900,7 +1921,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_I2C3: /* Get the current I2C3 source */ srcclk = __HAL_RCC_GET_I2C3_SOURCE(); - + if(srcclk == RCC_I2C3CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1925,7 +1946,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_I2C4: /* Get the current I2C4 source */ srcclk = __HAL_RCC_GET_I2C4_SOURCE(); - + if(srcclk == RCC_I2C4CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1950,7 +1971,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_LPTIM1: /* Get the current LPTIM1 source */ srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); - + if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1977,7 +1998,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_LPTIM2: /* Get the current LPTIM2 source */ srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); - + if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -2006,7 +2027,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_SWPMI1: /* Get the current SWPMI1 source */ srcclk = __HAL_RCC_GET_SWPMI1_SOURCE(); - + if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -2029,7 +2050,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_OSPI: /* Get the current OctoSPI clock source */ srcclk = __HAL_RCC_GET_OSPI_SOURCE(); - + if(srcclk == RCC_OSPICLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); @@ -2078,12 +2099,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions * @brief Extended Clock management functions * -@verbatim +@verbatim =============================================================================== ##### Extended clock management functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to control the + This subsection provides a set of functions allowing to control the activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS, Low speed clock output and clock after wake-up from STOP mode. @endverbatim @@ -2126,7 +2147,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) } } - if(status == HAL_OK) + if(status == HAL_OK) { #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) /* Configure the PLLSAI1 Multiplication factor N */ @@ -2137,7 +2158,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) /* Configure the PLLSAI1 Division factors P, Q and R */ __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - /* Configure the PLLSAI1 Clock output(s) */ + /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut); /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ @@ -2156,7 +2177,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) } } } - + return status; } @@ -2184,21 +2205,21 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) break; } } - - /* Disable the PLLSAI1 Clock outputs */ + + /* Disable the PLLSAI1 Clock outputs */ __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN); /* Reset PLL source to save power if no PLLs on */ if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) #if defined(RCC_PLLSAI2_SUPPORT) - && + && (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) #endif /* RCC_PLLSAI2_SUPPORT */ ) - { + { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } - + return status; } @@ -2242,7 +2263,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) } } - if(status == HAL_OK) + if(status == HAL_OK) { #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) /* Configure the PLLSAI2 Multiplication factor N */ @@ -2261,7 +2282,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) /* Configure the PLLSAI2 Division factors P and R */ __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ - /* Configure the PLLSAI2 Clock output(s) */ + /* Configure the PLLSAI2 Clock output(s) */ __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut); /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ @@ -2280,7 +2301,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) } } } - + return status; } @@ -2308,8 +2329,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) break; } } - - /* Disable the PLLSAI2 Clock outputs */ + + /* Disable the PLLSAI2 Clock outputs */ #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2QEN|RCC_PLLSAI2CFGR_PLLSAI2REN); #else @@ -2318,13 +2339,13 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) /* Reset PLL source to save power if no PLLs on */ if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) - && + && (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) ) - { + { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } - + return status; } @@ -2332,7 +2353,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) /** * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock. - * @param WakeUpClk Wakeup clock + * @param WakeUpClk Wakeup clock * This parameter can be one of the following values: * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection @@ -2343,14 +2364,14 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) { assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); - + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); } /** * @brief Configure the MSI range after standby mode. * @note After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). - * @param MSIRange MSI range + * @param MSIRange MSI range * This parameter can be one of the following values: * @arg @ref RCC_MSIRANGE_4 Range 4 around 1 MHz * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz @@ -2361,7 +2382,7 @@ void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange) { assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange)); - + __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange); } @@ -2385,7 +2406,7 @@ void HAL_RCCEx_EnableLSECSS(void) void HAL_RCCEx_DisableLSECSS(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; - + /* Disable LSE CSS IT if any */ __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); } @@ -2402,7 +2423,7 @@ void HAL_RCCEx_EnableLSECSS_IT(void) /* Enable LSE CSS IT */ __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); - + /* Enable IT on EXTI Line 19 */ __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); @@ -2423,7 +2444,7 @@ void HAL_RCCEx_LSECSS_IRQHandler(void) /* Clear RCC LSE CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); } -} +} /** * @brief RCCEx LSE Clock Security System interrupt callback. @@ -2449,7 +2470,7 @@ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) GPIO_InitTypeDef GPIO_InitStruct; FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; - + /* Check the parameters */ assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); @@ -2474,9 +2495,9 @@ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) HAL_PWR_EnableBkUpAccess(); backupchanged = SET; } - + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); - + if(backupchanged == SET) { HAL_PWR_DisableBkUpAccess(); @@ -2495,7 +2516,7 @@ void HAL_RCCEx_DisableLSCO(void) { FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; - + /* Update LSCOEN bit in Backup Domain control register */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { @@ -2508,9 +2529,9 @@ void HAL_RCCEx_DisableLSCO(void) HAL_PWR_EnableBkUpAccess(); backupchanged = SET; } - + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); - + /* Restore previous configuration */ if(backupchanged == SET) { @@ -2550,7 +2571,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) #if defined(CRS) -/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions * @brief Extended Clock Recovery System Control functions * @verbatim @@ -2568,11 +2589,11 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (##) Prepare synchronization configuration necessary for HSI48 calibration (+++) Default values can be set for frequency Error Measurement (reload and error limit) and also HSI48 oscillator smooth trimming. - (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate directly reload value with target and sychronization frequencies values (##) Call function HAL_RCCEx_CRSConfig which (+++) Resets CRS registers to their default values. - (+++) Configures CRS registers with synchronization configuration + (+++) Configures CRS registers with synchronization configuration (+++) Enables automatic calibration and frequency error counter feature Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be @@ -2584,23 +2605,23 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (+++) Call function HAL_RCCEx_CRSWaitSynchronization() (+++) According to CRS status, user can decide to adjust again the calibration or continue application if synchronization is OK - + (#) User can retrieve information related to synchronization in calling function HAL_RCCEx_CRSGetSynchronizationInfo() (#) Regarding synchronization status and synchronization information, user can try a new calibration in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. - Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), - it means that the actual frequency is lower than the target (and so, that the TRIM value should be - incremented), while when it is detected during the upcounting phase it means that the actual frequency + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency is higher (and that the TRIM value should be decremented). - (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go through CRS Handler (CRS_IRQn/CRS_IRQHandler) (++) Call function HAL_RCCEx_CRSConfig() (++) Enable CRS_IRQn (thanks to NVIC functions) (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) - (++) Implement CRS status management in the following user callbacks called from + (++) Implement CRS status management in the following user callbacks called from HAL_RCCEx_CRS_IRQHandler(): (+++) HAL_RCCEx_CRS_SyncOkCallback() (+++) HAL_RCCEx_CRS_SyncWarnCallback() @@ -2609,7 +2630,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) - + @endverbatim * @{ */ @@ -2622,7 +2643,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) { uint32_t value = 0; - + /* Check the parameters */ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); @@ -2650,9 +2671,9 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) /* Adjust HSI48 oscillator smooth trimming */ /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); - + /* START AUTOMATIC SYNCHRONIZATION*/ - + /* Enable Automatic trimming & Frequency error counter */ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); } @@ -2667,7 +2688,7 @@ void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) } /** - * @brief Return synchronization info + * @brief Return synchronization info * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure * @retval None */ @@ -2675,10 +2696,10 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo { /* Check the parameter */ assert_param(pSynchroInfo != NULL); - + /* Get the reload value */ pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); - + /* Get HSI48 oscillator smooth trimming */ pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); @@ -2708,10 +2729,10 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { uint32_t crsstatus = RCC_CRS_NONE; uint32_t tickstart = 0U; - + /* Get timeout */ tickstart = HAL_GetTick(); - + /* Wait for CRS flag or timeout detection */ do { @@ -2727,51 +2748,51 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { /* CRS SYNC event OK */ crsstatus |= RCC_CRS_SYNCOK; - + /* Clear CRS SYNC event OK bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); } - + /* Check CRS SYNCWARN flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) { /* CRS SYNC warning */ crsstatus |= RCC_CRS_SYNCWARN; - + /* Clear CRS SYNCWARN bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); } - + /* Check CRS TRIM overflow flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_TRIMOVF; - + /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); } - + /* Check CRS Error flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_SYNCERR; - + /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); } - + /* Check CRS SYNC Missed flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) { /* CRS SYNC Missed */ crsstatus |= RCC_CRS_SYNCMISS; - + /* Clear CRS SYNC Missed bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); } - + /* Check CRS Expected SYNC flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) { @@ -2841,7 +2862,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) /* Clear CRS Error flags */ WRITE_REG(CRS->ICR, CRS_ICR_ERRC); - + /* user error callback */ HAL_RCCEx_CRS_ErrorCallback(crserror); } @@ -2883,7 +2904,7 @@ __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) /** * @brief RCCEx Clock Recovery System Error interrupt callback. - * @param Error Combination of Error status. + * @param Error Combination of Error status. * This parameter can be a combination of the following values: * @arg @ref RCC_CRS_SYNCERR * @arg @ref RCC_CRS_SYNCMISS @@ -2903,7 +2924,7 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) /** * @} */ - + #endif /* CRS */ /** @@ -2935,16 +2956,16 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M)); assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N)); assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut)); - + /* Check that PLLSAI1 clock source and divider M can be applied */ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) { - /* PLL clock source and divider M already set, check that no request for change */ + /* PLL clock source and divider M already set, check that no request for change */ if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) - || + || (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) #if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - || + || (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M) #endif ) @@ -2979,7 +3000,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u status = HAL_ERROR; break; } - + if(status == HAL_OK) { #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) @@ -2991,7 +3012,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u #endif } } - + if(status == HAL_OK) { /* Disable the PLLSAI1 */ @@ -3010,7 +3031,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u } } - if(status == HAL_OK) + if(status == HAL_OK) { if(Divider == DIVIDER_P_UPDATE) { @@ -3019,15 +3040,15 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u /* Configure the PLLSAI1 Division factor M, P and Multiplication factor N*/ #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); #else - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ @@ -3035,14 +3056,14 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u #else /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/ #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)); #else - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)); #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ @@ -3053,16 +3074,16 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q)); #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) /* Configure the PLLSAI1 Division factor M, Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); #else /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)); #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ } @@ -3071,16 +3092,16 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R)); #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) /* Configure the PLLSAI1 Division factor M, R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); #else /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)); #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ } @@ -3101,14 +3122,14 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u } } - if(status == HAL_OK) + if(status == HAL_OK) { /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut); } } } - + return status; } @@ -3135,16 +3156,16 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M)); assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N)); assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut)); - + /* Check that PLLSAI2 clock source and divider M can be applied */ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) { - /* PLL clock source and divider M already set, check that no request for change */ + /* PLL clock source and divider M already set, check that no request for change */ if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source) - || + || (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE) #if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - || + || (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M) #endif ) @@ -3179,7 +3200,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u status = HAL_ERROR; break; } - + if(status == HAL_OK) { #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) @@ -3191,7 +3212,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u #endif } } - + if(status == HAL_OK) { /* Disable the PLLSAI2 */ @@ -3210,7 +3231,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u } } - if(status == HAL_OK) + if(status == HAL_OK) { if(Divider == DIVIDER_P_UPDATE) { @@ -3219,15 +3240,15 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u /* Configure the PLLSAI2 Division factor M, P and Multiplication factor N*/ #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); #else - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ @@ -3235,14 +3256,14 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u #else /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/ #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)); #else - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)); #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ @@ -3254,16 +3275,16 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u assert_param(IS_RCC_PLLSAI2Q_VALUE(PllSai2->PLLSAI2Q)); #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* Configure the PLLSAI2 Division factor M, Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); #else /* Configure the PLLSAI2 Division factor Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)); #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ } @@ -3273,16 +3294,16 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R)); #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* Configure the PLLSAI2 Division factor M, R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); #else /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)); #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ } @@ -3303,14 +3324,14 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u } } - if(status == HAL_OK) + if(status == HAL_OK) { /* Configure the PLLSAI2 Clock output(s) */ __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut); } } } - + return status; } diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c index 5ddebae..d76c738 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c +++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c @@ -716,7 +716,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; @@ -897,7 +897,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint } /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; @@ -1529,11 +1529,12 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ + SDMMC_IT_RXFIFOHF); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - __HAL_SD_DISABLE_IT(hsd, SDMMC_FLAG_IDMATE | SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_RXFIFOHF); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); __SDMMC_CMDTRANS_DISABLE( hsd->Instance); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -1550,7 +1551,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) @@ -1615,15 +1616,11 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET) { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_TXFIFOHE); - SD_Write_IT(hsd); } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET) { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXFIFOHF); - SD_Read_IT(hsd); } @@ -1648,7 +1645,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Disable all interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ @@ -1666,6 +1663,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) if(hsd->ErrorCode != HAL_SD_ERROR_NONE) { /* Disable Internal DMA */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; /* Set the SD state to ready to be able to start again the process */ @@ -1705,16 +1703,6 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMATE) != RESET) - { - __SDMMC_CMDTRANS_DISABLE( hsd->Instance); - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMATE); - - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMATE); - - HAL_SD_ErrorCallback(hsd); - } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMABTC) != RESET) { if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == SD_DMA_BUFFER0) @@ -1741,7 +1729,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(hsd); } } - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_IT_IDMABTC); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } @@ -2310,11 +2298,6 @@ HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) cardstate = (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(hsd->Instance, SDMMC_STATIC_FLAGS); -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - return cardstate; } @@ -2380,14 +2363,17 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) { HAL_SD_CardStateTypedef CardState; - /* DIsable All interrupts */ + /* Disable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* If IDMA Context, disable Internal DMA */ + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) CardState = HAL_SD_GetCardState(hsd); hsd->State = HAL_SD_STATE_READY; @@ -2433,6 +2419,9 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) /* No transfer ongoing on both DMA channels*/ if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + CardState = HAL_SD_GetCardState(hsd); hsd->State = HAL_SD_STATE_READY; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) @@ -2506,7 +2495,7 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; @@ -2563,14 +2552,16 @@ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) /* All DMA channels are aborted */ if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + CardState = HAL_SD_GetCardState(hsd); - hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_READY; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) { HAL_SD_AbortCallback(hsd); } @@ -2600,14 +2591,16 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) /* All DMA channels are aborted */ if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + CardState = HAL_SD_GetCardState(hsd); - hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_READY; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) { HAL_SD_AbortCallback(hsd); } @@ -2874,8 +2867,13 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) return errorstate; } - /* Check to BusyD0 and CKSTOP */ + /* Check to CKSTOP */ while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP); + + /* Clear CKSTOP Flag */ + hsd->Instance->ICR = SDMMC_FLAG_CKSTOP; + + /* Check to BusyD0 */ if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) { /* Error when activate Voltage Switch in SDMMC IP */ @@ -2891,6 +2889,10 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Check VSWEND Flag */ while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND); + + /* Clear VSWEND Flag */ + hsd->Instance->ICR = SDMMC_FLAG_VSWEND; + /* Check BusyD0 status */ if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) { @@ -3016,7 +3018,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE))) + while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT))) #else while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -3031,7 +3033,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } /* Clear all the static status flags*/ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); return HAL_SD_ERROR_NONE; } @@ -3211,7 +3213,6 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) tempscr[0] = SDMMC_ReadFIFO(hsd->Instance); tempscr[1] = SDMMC_ReadFIFO(hsd->Instance); index++; - break; } @@ -3258,8 +3259,8 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { /* No error flag set */ /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + *(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24); diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c index f7d25eb..4ee5298 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c +++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c @@ -188,7 +188,7 @@ uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd) } /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Test if the switch mode HS is ok */ if ((SD_hs[13]& 2) != 2) @@ -333,7 +333,7 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); /* Read Blocks in DMA mode */ hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); @@ -417,7 +417,7 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); /* Write Blocks in DMA mode */ hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); diff --git a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c index ee6db2f..c245cca 100644 --- a/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c +++ b/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c @@ -1221,7 +1221,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); return SDMMC_ERROR_NONE; } @@ -1272,7 +1272,7 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ } /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); /* We have received response, retrieve it for analysis */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); @@ -1395,7 +1395,7 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) { /* No error flag set */ /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); } return SDMMC_ERROR_NONE; @@ -1428,10 +1428,9 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_CMD_RSP_TIMEOUT; } else - { /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); } return SDMMC_ERROR_NONE; @@ -1482,7 +1481,7 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ } /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); /* We have received response, retrieve it. */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); @@ -1535,6 +1534,14 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_CMD_RSP_TIMEOUT; } + else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + /* Card is SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) { /* Card is SD V2.0 compliant */ diff --git a/EWARM/stm32-bootloader.dep b/EWARM/stm32-bootloader.dep index 10c0d80..2ba3c33 100644 --- a/EWARM/stm32-bootloader.dep +++ b/EWARM/stm32-bootloader.dep @@ -1,7 +1,7 @@ 2 - 4144582326 + 808011668 L476 @@ -24,38 +24,36 @@ $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\option\syscall.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc_ex.h - $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmInstr.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h - $TOOLKIT_DIR$\lib\m7M_tls.a - $TOOLKIT_DIR$\inc\c\stdint.h - $TOOLKIT_DIR$\inc\c\DLib_Config_Full.h - $TOOLKIT_DIR$\lib\dl7M_tlf.a - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h - $PROJ_DIR$\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\system_stm32l4xx.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.h - $PROJ_DIR$\L476\Obj\startup_stm32l496xx.o - $PROJ_DIR$\L476\Obj\bsp_driver_sd.__cstat.et - $PROJ_DIR$\L476\Obj\syscall.__cstat.et - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h - $PROJ_DIR$\L476\Obj\bootloader.__cstat.et $PROJ_DIR$\L476\Obj\fatfs.__cstat.et + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h + $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc_ex.__cstat.et + $PROJ_DIR$\L476\Obj\stm32l4xx_hal_sd.__cstat.et + $PROJ_DIR$\L476\Obj\stm32l4xx_ll_sdmmc.__cstat.et + $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc.pbi + $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc_ex.pbi + $PROJ_DIR$\L476\Obj\stm32l4xx_hal_sd.pbi + $PROJ_DIR$\L476\Obj\stm32l4xx_ll_sdmmc.pbi + $PROJ_DIR$\L476\Obj\diskio.pbi + $PROJ_DIR$\L476\Obj\ff.pbi + $PROJ_DIR$\L476\Obj\ff_gen_drv.pbi + $PROJ_DIR$\L476\Exe\stm32-bootloader.out + $PROJ_DIR$\L476\Exe\stm32-bootloader.bin + $PROJ_DIR$\L476\Obj\ff_gen_drv.__cstat.et + $PROJ_DIR$\L476\Obj\ff.__cstat.et + $PROJ_DIR$\L476\List\stm32-bootloader.map + $PROJ_DIR$\L476\Obj\diskio.__cstat.et + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.h + $PROJ_DIR$\L476\Obj\syscall.o + $PROJ_DIR$\L476\Obj\syscall.pbi + $PROJ_DIR$\..\Inc\sd_diskio.h + $PROJ_DIR$\..\Src\sd_diskio.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h $PROJ_DIR$\L476\Obj\main.__cstat.et $PROJ_DIR$\L476\Obj\sd_diskio.__cstat.et $PROJ_DIR$\L476\Obj\stm32l4xx_it.__cstat.et @@ -88,6 +86,38 @@ $PROJ_DIR$\L476\Obj\sd_diskio.o $PROJ_DIR$\L476\Obj\stm32l4xx_it.o $PROJ_DIR$\L476\Obj\fatfs.o + $PROJ_DIR$\stm32l496xx_flash.icf + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\option\syscall.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc_ex.h + $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmInstr.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h + $TOOLKIT_DIR$\lib\m7M_tls.a + $TOOLKIT_DIR$\inc\c\stdint.h + $TOOLKIT_DIR$\inc\c\DLib_Config_Full.h + $TOOLKIT_DIR$\lib\dl7M_tlf.a + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h + $PROJ_DIR$\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\system_stm32l4xx.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.h + $PROJ_DIR$\L476\Obj\startup_stm32l496xx.o + $PROJ_DIR$\L476\Obj\bsp_driver_sd.__cstat.et + $PROJ_DIR$\L476\Obj\syscall.__cstat.et + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h + $PROJ_DIR$\L476\Obj\bootloader.__cstat.et $PROJ_DIR$\L476\Obj\stm32l4xx_hal_crc.o $PROJ_DIR$\L476\Obj\stm32l4xx_hal_cortex.o $PROJ_DIR$\L476\Obj\stm32l4xx_hal_flash_ramfunc.o @@ -149,42 +179,14 @@ $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc.h $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmSimd.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h - $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc_ex.__cstat.et - $PROJ_DIR$\L476\Obj\stm32l4xx_hal_sd.__cstat.et - $PROJ_DIR$\L476\Obj\stm32l4xx_ll_sdmmc.__cstat.et - $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc.pbi - $PROJ_DIR$\L476\Obj\stm32l4xx_hal_rcc_ex.pbi - $PROJ_DIR$\L476\Obj\stm32l4xx_hal_sd.pbi - $PROJ_DIR$\L476\Obj\stm32l4xx_ll_sdmmc.pbi - $PROJ_DIR$\L476\Obj\diskio.pbi - $PROJ_DIR$\L476\Obj\ff.pbi - $PROJ_DIR$\L476\Obj\ff_gen_drv.pbi - $PROJ_DIR$\L476\Exe\stm32-bootloader.out - $PROJ_DIR$\L476\Exe\stm32-bootloader.bin - $PROJ_DIR$\L476\Obj\ff_gen_drv.__cstat.et - $PROJ_DIR$\L476\Obj\ff.__cstat.et - $PROJ_DIR$\L476\List\stm32-bootloader.map - $PROJ_DIR$\L476\Obj\diskio.__cstat.et - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.h - $PROJ_DIR$\L476\Obj\syscall.o - $PROJ_DIR$\L476\Obj\syscall.pbi - $PROJ_DIR$\..\Inc\sd_diskio.h - $PROJ_DIR$\..\Src\sd_diskio.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h + $PROJ_DIR$\L476\Obj\stm32-bootloader.pbd [ROOT_NODE] ILINK - 162 158 + 34 38 @@ -193,7 +195,7 @@ AARM - 101 + 131 @@ -202,7 +204,7 @@ AARM - 45 + 108 @@ -211,25 +213,25 @@ __cstat - 49 + 112 BICOMP - 102 + 132 ICCARM - 76 + 74 BICOMP - 72 127 142 125 69 48 43 126 164 133 128 75 2 70 67 39 73 6 171 130 170 136 140 74 35 37 36 143 134 40 135 139 7 131 147 172 42 144 141 + 70 163 48 157 67 111 106 173 158 164 103 169 47 172 2 68 65 102 99 165 73 7 23 160 46 166 161 105 20 98 100 170 156 71 155 72 171 ICCARM - 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 48 7 6 171 127 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 2 + 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 111 7 47 157 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 2 @@ -238,25 +240,25 @@ __cstat - 46 + 109 BICOMP - 92 + 122 ICCARM - 94 + 124 BICOMP - 73 147 70 39 128 127 7 131 172 42 67 75 48 6 171 164 130 142 170 133 136 140 125 43 126 144 141 3 36 143 134 40 135 139 74 35 37 72 69 + 158 163 164 169 48 171 47 172 68 102 173 103 73 7 23 160 46 166 161 105 65 157 111 170 155 106 99 165 72 3 156 71 20 98 100 70 67 ICCARM - 3 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 3 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 @@ -265,25 +267,25 @@ __cstat - 50 + 19 BICOMP - 103 + 133 ICCARM - 82 + 80 BICOMP - 126 6 39 5 170 145 3 7 171 130 136 127 140 75 141 164 142 133 125 48 43 144 74 88 44 165 71 89 131 147 172 42 70 67 73 128 146 4 36 143 134 40 135 139 35 37 72 69 + 72 5 21 3 7 157 170 165 73 102 155 111 106 99 118 6 107 41 69 119 47 23 48 160 172 46 163 166 161 105 68 65 173 158 164 103 169 171 22 4 156 71 20 98 100 70 67 ICCARM - 4 44 71 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 145 146 165 + 4 107 69 5 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 3 119 118 21 22 41 6 @@ -292,25 +294,25 @@ __cstat - 51 + 49 BICOMP - 104 + 134 ICCARM - 79 + 77 BICOMP - 3 75 39 133 5 67 164 128 127 2 70 143 134 40 139 142 125 72 69 145 74 88 6 4 48 43 36 135 7 171 130 170 136 140 35 37 146 126 73 131 147 172 42 144 141 44 165 71 89 + 3 157 65 47 102 5 71 172 158 2 68 73 48 163 70 67 21 72 118 6 4 111 106 156 23 160 46 166 161 105 20 98 100 22 170 99 173 164 103 165 169 7 155 171 107 41 69 119 ICCARM - 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 48 7 6 171 127 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 2 4 44 71 5 3 89 88 145 146 165 + 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 111 7 47 157 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 6 2 4 107 69 5 3 119 118 21 22 41 @@ -319,25 +321,25 @@ __cstat - 53 + 51 BICOMP - 106 + 136 ICCARM - 81 + 79 BICOMP - 127 42 128 131 7 172 67 36 75 147 70 39 135 72 69 8 6 171 164 130 142 170 133 136 140 125 48 43 143 134 40 139 74 35 37 126 73 144 141 + 161 73 46 157 23 105 71 100 7 160 166 65 102 47 48 172 163 68 20 98 8 170 155 111 106 156 158 70 67 99 173 164 103 165 169 72 171 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 8 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 8 @@ -346,25 +348,25 @@ __cstat - 54 + 52 BICOMP - 107 + 137 ICCARM - 78 + 76 BICOMP - 172 36 7 128 127 48 43 135 75 131 42 70 67 39 143 134 40 139 147 144 141 140 126 73 6 171 164 130 142 170 133 136 125 74 35 37 72 69 + 157 73 170 158 71 171 102 111 106 68 65 156 155 72 99 173 164 103 165 169 7 47 23 48 160 172 46 163 166 161 105 20 98 100 70 67 ICCARM - 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 48 7 6 171 127 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 111 7 47 157 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 @@ -373,25 +375,25 @@ __cstat - 55 + 53 BICOMP - 108 + 138 ICCARM - 77 + 75 BICOMP - 170 73 6 171 130 136 127 140 128 164 142 133 125 48 43 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 158 164 169 171 157 170 173 103 73 155 111 106 7 47 23 48 160 172 46 163 166 161 105 68 65 102 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 @@ -400,25 +402,25 @@ __cstat - 56 + 54 BICOMP - 109 + 139 ICCARM - 84 + 114 BICOMP - 147 73 70 39 128 127 7 131 172 42 67 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 158 48 164 169 163 171 47 172 68 102 173 103 73 7 23 160 46 166 161 105 65 157 170 155 111 106 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 @@ -427,25 +429,25 @@ __cstat - 57 + 55 BICOMP - 110 + 140 ICCARM - 83 + 113 BICOMP - 133 43 73 164 142 125 48 128 127 7 6 171 130 170 136 140 39 75 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 171 106 158 164 169 155 111 173 103 73 7 157 170 47 23 48 160 172 46 163 166 161 105 68 65 102 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 @@ -454,522 +456,522 @@ __cstat - 58 + 56 BICOMP - 111 + 141 ICCARM - 120 + 150 BICOMP - 130 127 140 73 171 136 6 170 128 164 142 133 125 48 43 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 158 164 169 157 170 171 173 103 73 155 111 106 7 47 23 48 160 172 46 163 166 161 105 68 65 102 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + $PROJ_DIR$\L476\Exe\stm32-bootloader.out - __cstat - 59 - - - BICOMP - 112 + ILINK + 38 - ICCARM - 119 + OBJCOPY + 35 - BICOMP - 43 133 73 164 142 125 48 128 127 6 171 130 170 136 140 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 - - - ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + ILINK + 159 74 124 128 80 129 130 77 78 131 75 114 113 150 149 117 116 115 154 153 152 151 125 126 79 127 42 76 162 66 101 104 - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c + $PROJ_DIR$\..\Src\sd_diskio.c __cstat - 60 + 50 BICOMP - 113 + 135 ICCARM - 87 + 78 BICOMP - 170 73 6 171 130 136 127 140 128 164 142 133 125 48 43 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 73 157 161 68 102 69 48 156 111 107 119 23 105 65 20 70 67 44 22 5 3 7 6 47 40 160 46 163 166 170 155 106 71 158 100 21 99 173 164 103 165 169 72 171 118 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 6 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 21 22 69 107 5 3 44 168 167 - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c __cstat - 61 + 57 BICOMP - 114 + 142 ICCARM - 86 + 149 BICOMP - 133 43 73 164 142 125 48 128 127 7 6 171 130 170 136 140 39 75 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 158 164 169 106 171 155 111 173 103 73 157 170 7 47 23 48 160 172 46 163 166 161 105 68 65 102 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c __cstat - 62 + 58 BICOMP - 115 + 143 ICCARM - 85 + 117 BICOMP - 172 73 7 67 131 42 128 127 147 70 39 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 158 164 169 171 157 170 173 103 73 155 111 106 7 47 23 48 160 172 46 163 166 161 105 68 65 102 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c __cstat - 63 + 59 BICOMP - 116 + 144 ICCARM - 124 + 116 BICOMP - 164 73 133 43 142 125 48 128 127 6 171 130 170 136 140 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 171 106 158 164 169 155 111 173 103 73 7 157 170 47 23 48 160 172 46 163 166 161 105 68 65 102 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c __cstat - 64 + 60 BICOMP - 117 + 145 ICCARM - 123 + 115 BICOMP - 147 73 70 39 128 127 7 131 172 42 67 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 158 160 65 164 169 7 166 171 23 46 161 105 173 103 73 47 48 172 163 68 102 157 170 155 111 106 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c __cstat - 65 + 61 BICOMP - 118 + 146 ICCARM - 122 + 154 BICOMP - 73 70 39 147 128 127 7 131 172 42 67 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 158 106 164 169 171 155 111 173 103 73 157 170 7 47 23 48 160 172 46 163 166 161 105 68 65 102 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c __cstat - 66 + 62 BICOMP - 151 + 147 ICCARM - 121 + 153 BICOMP - 142 125 48 73 164 133 43 128 127 6 171 130 170 136 140 39 75 7 131 147 172 42 70 67 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 158 48 164 169 163 171 47 172 68 102 173 103 73 7 23 160 46 166 161 105 65 157 170 155 111 106 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c __cstat - 148 + 63 BICOMP - 152 + 148 ICCARM - 95 + 152 BICOMP - 42 73 131 7 172 67 128 127 147 70 39 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 158 172 68 102 164 169 47 171 48 163 173 103 73 7 23 160 46 166 161 105 65 157 170 155 111 106 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c __cstat - 149 + 64 BICOMP - 153 + 27 ICCARM - 96 + 151 BICOMP - 133 73 164 67 142 128 127 7 6 171 130 170 136 131 42 39 75 147 172 70 126 144 141 48 140 125 43 36 143 134 40 135 139 74 35 37 72 69 + 158 164 169 155 111 171 106 173 103 73 157 170 7 47 23 48 160 172 46 163 166 161 105 68 65 102 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c __cstat - 150 + 24 BICOMP - 154 + 28 ICCARM - 97 + 125 BICOMP - 131 73 42 7 172 67 128 127 147 70 39 75 6 171 164 130 142 170 133 136 140 125 48 43 126 144 141 36 143 134 40 135 139 74 35 37 72 69 + 158 46 161 164 169 23 105 171 7 160 166 65 173 103 73 47 48 172 163 68 102 157 170 155 111 106 99 165 72 156 71 20 98 100 70 67 ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd.c __cstat - 52 + 25 BICOMP - 105 + 29 ICCARM - 80 + 126 BICOMP - 89 147 36 75 71 48 70 39 128 127 44 131 172 42 67 135 72 69 165 146 5 3 7 6 171 164 130 142 170 133 136 140 125 43 143 134 40 139 74 35 37 145 126 73 144 141 88 + 171 158 164 169 7 157 170 173 103 73 47 23 48 160 172 46 163 166 155 111 106 99 165 72 161 105 68 65 102 156 71 20 98 100 70 67 ICCARM - 145 146 71 44 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 165 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\option\syscall.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c __cstat - 47 + 26 BICOMP - 167 + 30 ICCARM - 166 + 127 BICOMP - 35 48 70 39 71 89 147 131 172 42 67 143 128 134 40 139 74 127 37 5 3 7 6 171 164 130 142 170 133 136 140 125 43 36 135 75 72 69 44 126 73 144 141 88 + 158 164 169 171 157 170 173 103 73 155 111 106 7 47 23 48 160 172 46 163 166 161 105 68 65 102 99 165 72 156 71 20 98 100 70 67 ICCARM - 44 71 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 + 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.c __cstat - 163 + 50 BICOMP - 155 + 135 ICCARM - 98 + 78 BICOMP - 5 164 35 71 39 133 43 142 125 48 146 3 7 6 171 130 170 136 127 140 143 128 134 40 139 74 37 145 44 89 131 147 172 42 70 67 36 135 75 72 69 126 73 144 141 88 + 119 157 48 163 102 69 111 47 172 68 73 71 100 107 23 160 46 166 161 105 65 20 98 41 22 5 3 7 170 155 106 156 158 70 67 21 99 173 164 103 165 169 72 171 118 ICCARM - 146 71 145 44 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 + 21 22 69 107 5 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 3 119 118 41 - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\option\syscall.c __cstat - 161 + 110 BICOMP - 156 + 43 ICCARM - 99 + 42 BICOMP - 72 48 70 39 135 75 127 89 147 69 71 131 172 42 67 36 128 146 5 3 7 6 171 164 130 142 170 133 136 140 125 43 143 134 40 139 74 35 37 44 126 73 144 141 88 + 157 68 102 172 156 111 47 158 69 119 48 163 23 160 46 166 161 105 65 70 67 5 3 7 170 155 106 73 71 20 98 100 107 99 173 164 103 165 169 72 171 118 ICCARM - 44 71 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 146 + 107 69 5 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 3 119 118 - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.c __cstat - 160 + 39 BICOMP - 157 + 31 ICCARM - 100 + 128 BICOMP - 170 35 6 5 3 7 171 130 136 127 140 44 164 142 133 125 48 43 143 128 134 40 139 74 37 146 39 71 89 131 147 172 42 70 67 36 135 75 72 69 145 126 73 144 141 88 + 157 5 106 156 69 102 158 155 111 22 3 7 170 70 67 21 107 119 47 23 48 160 172 46 163 166 161 105 68 65 73 71 20 98 100 99 173 164 103 165 169 72 171 118 ICCARM - 145 146 71 44 5 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 164 130 142 35 170 141 37 133 72 136 69 3 89 88 + 22 69 21 107 5 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 3 119 118 - $PROJ_DIR$\..\Src\sd.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.c + + __cstat + 37 + BICOMP - 90 + 32 ICCARM - 91 + 129 BICOMP - 127 3 172 128 131 70 39 73 75 2 147 42 67 44 4 48 7 6 171 164 130 142 170 133 136 140 125 43 126 144 141 145 5 71 36 143 134 40 135 139 74 35 37 72 69 89 88 146 + 172 68 102 71 111 47 20 73 119 48 163 157 98 69 23 160 46 166 161 105 65 100 22 5 3 7 170 155 106 156 158 70 67 107 99 173 164 103 165 169 72 171 118 + + + ICCARM + 107 69 5 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 3 119 118 22 - $PROJ_DIR$\L476\Exe\stm32-bootloader.out + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c - ILINK - 162 + __cstat + 36 - OBJCOPY - 159 + BICOMP + 33 + + + ICCARM + 130 - ILINK - 129 76 94 98 82 99 100 79 80 101 77 84 83 120 119 87 86 85 124 123 122 121 95 96 81 97 166 78 132 68 38 41 + BICOMP + 157 156 158 5 3 7 170 107 155 111 106 70 67 22 102 69 119 47 23 48 160 172 46 163 166 161 105 68 65 73 71 20 98 100 21 99 173 164 103 165 169 72 171 118 + + + ICCARM + 21 22 69 107 5 111 7 47 157 170 68 65 102 158 73 164 103 165 99 71 169 156 173 106 105 155 72 161 23 20 48 160 172 98 46 171 100 163 70 166 67 3 119 118 - $PROJ_DIR$\..\Src\sd_diskio.c + $PROJ_DIR$\..\Src\sd.c - - __cstat - 52 - BICOMP - 105 + 120 ICCARM - 80 + 121 BICOMP - 75 127 131 70 39 71 172 126 48 44 89 147 42 67 144 72 69 168 146 5 3 7 6 171 164 130 170 133 136 140 125 43 73 128 37 145 36 143 134 40 135 139 74 141 88 - - - ICCARM - 48 7 6 171 127 140 70 67 39 128 75 134 40 135 36 73 139 126 143 43 42 125 74 131 147 144 172 130 142 35 170 141 37 133 72 136 69 145 146 71 44 5 3 168 138 137 + 157 3 48 158 161 68 102 71 73 2 23 105 65 107 4 111 7 6 47 40 160 172 46 163 166 170 155 106 156 20 171 21 5 69 99 173 164 103 165 169 72 98 100 70 67 119 118 22 @@ -994,44 +996,32 @@ $PROJ_DIR$\..\Inc\main.h $PROJ_DIR$\..\Inc\stm32l4xx_hal_conf.h $PROJ_DIR$\..\Inc\stm32l4xx_it.h - $PROJ_DIR$\..\Src\bootloader.c - $PROJ_DIR$\..\Src\bsp_driver_sd.c - $PROJ_DIR$\..\Src\fatfs.c - $PROJ_DIR$\..\Src\main.c - $PROJ_DIR$\..\Src\stm32l4xx_it.c - $PROJ_DIR$\..\Src\system_stm32l4xx.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\option\syscall.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.c - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc_ex.h - $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmInstr.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h - $TOOLKIT_DIR$\lib\m7M_tls.a - $TOOLKIT_DIR$\inc\c\stdint.h - $TOOLKIT_DIR$\inc\c\DLib_Config_Full.h - $TOOLKIT_DIR$\lib\dl7M_tlf.a - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h - $PROJ_DIR$\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\system_stm32l4xx.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h - $PROJ_DIR$\L496\Obj\stm32l4xx_hal_crc_ex.pbi + $PROJ_DIR$\..\Src\bootloader.c + $PROJ_DIR$\..\Src\bsp_driver_sd.c + $PROJ_DIR$\..\Src\fatfs.c + $PROJ_DIR$\..\Src\main.c + $PROJ_DIR$\..\Src\stm32l4xx_it.c + $PROJ_DIR$\..\Src\system_stm32l4xx.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h + $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cm4.h + $TOOLKIT_DIR$\lib\rt7M_tl.a + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_sdmmc.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\integer.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr_ex.h + $TOOLKIT_DIR$\inc\c\cmsis_iar.h + $TOOLKIT_DIR$\inc\c\ysizet.h + $TOOLKIT_DIR$\inc\c\yvals.h $PROJ_DIR$\L496\Obj\stm32l4xx_hal_dma.pbi $PROJ_DIR$\L496\Obj\stm32l4xx_hal_flash.pbi $PROJ_DIR$\L496\Obj\stm32l4xx_hal_flash_ex.pbi @@ -1117,20 +1107,40 @@ $PROJ_DIR$\L496\Obj\stm32l4xx_hal.pbi $PROJ_DIR$\L496\Obj\stm32l4xx_hal_cortex.pbi $PROJ_DIR$\L496\Obj\stm32l4xx_hal_crc.pbi - $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cm4.h - $TOOLKIT_DIR$\lib\rt7M_tl.a - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_ll_sdmmc.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\integer.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_pwr_ex.h - $TOOLKIT_DIR$\inc\c\cmsis_iar.h - $TOOLKIT_DIR$\inc\c\ysizet.h - $TOOLKIT_DIR$\inc\c\yvals.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\option\syscall.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.c + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.c + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc_ex.h + $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmInstr.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ramfunc.h + $TOOLKIT_DIR$\lib\m7M_tls.a + $TOOLKIT_DIR$\inc\c\stdint.h + $TOOLKIT_DIR$\inc\c\DLib_Config_Full.h + $TOOLKIT_DIR$\lib\dl7M_tlf.a + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h + $PROJ_DIR$\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\system_stm32l4xx.h + $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff.h + $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal.h $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h $TOOLKIT_DIR$\inc\c\stdlib.h $TOOLKIT_DIR$\inc\c\stdio.h $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmFunc.h $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_def.h $TOOLKIT_DIR$\inc\c\ycheck.h + $PROJ_DIR$\stm32l476xx_flash.icf $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_cortex.h $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc_ex.h $TOOLKIT_DIR$\lib\shb_l.a @@ -1143,22 +1153,14 @@ $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash_ex.h $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_crc.h $PROJ_DIR$\..\Drivers\CMSIS\Include\core_cmSimd.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio_ex.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\ff_gen_drv.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\diskio.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_gpio.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma_ex.h - $PROJ_DIR$\..\Middlewares\Third_Party\FatFs\src\driver\sd_diskio.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_flash.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h - $PROJ_DIR$\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_dma.h + $PROJ_DIR$\L496\Obj\stm32l4xx_hal_crc_ex.pbi [ROOT_NODE] ILINK - 61 99 + 49 87 @@ -1167,7 +1169,7 @@ AARM - 122 + 110 @@ -1176,7 +1178,7 @@ AARM - 86 + 74 @@ -1185,25 +1187,25 @@ __cstat - 65 + 53 BICOMP - 123 + 111 ICCARM - 83 + 71 BICOMP - 136 144 39 156 145 45 132 157 150 40 153 162 149 147 42 158 2 87 43 36 151 139 7 6 165 146 164 152 155 134 154 143 137 161 166 142 138 35 37 + 163 157 143 34 151 140 32 26 155 29 146 27 25 164 2 75 144 150 22 154 24 160 152 31 162 137 165 158 141 159 161 7 149 33 19 136 138 ICCARM - 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 45 7 6 165 144 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 2 + 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 146 7 25 151 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 2 @@ -1212,25 +1214,25 @@ __cstat - 66 + 54 BICOMP - 79 + 67 ICCARM - 73 + 61 BICOMP - 156 162 149 147 42 151 139 7 6 165 146 164 152 87 43 36 145 144 45 161 166 154 142 132 39 157 150 40 153 138 35 37 3 143 137 158 155 136 134 + 137 162 140 151 7 149 146 27 159 34 33 136 138 25 22 26 154 164 24 157 160 155 143 75 144 165 152 158 141 161 19 3 150 32 163 31 29 ICCARM - 3 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 3 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1239,25 +1241,25 @@ __cstat - 68 + 56 BICOMP - 124 + 112 ICCARM - 85 + 73 BICOMP - 144 39 5 161 132 159 3 7 142 45 147 166 154 157 145 150 40 153 138 35 37 140 6 44 163 135 141 165 162 146 156 164 149 152 42 87 43 36 151 139 160 4 143 137 158 155 136 134 + 165 157 143 5 26 155 141 34 151 20 3 7 25 164 152 158 161 140 22 154 24 160 75 144 19 33 147 6 145 23 30 146 148 162 149 27 137 159 136 138 21 4 150 32 163 31 29 ICCARM - 4 44 135 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 159 160 163 + 4 145 30 5 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 3 148 147 20 21 23 6 @@ -1266,25 +1268,25 @@ __cstat - 67 + 55 BICOMP - 125 + 113 ICCARM - 84 + 72 BICOMP - 3 137 147 144 39 149 5 162 42 158 2 87 43 139 156 145 136 159 138 140 6 4 45 132 143 165 146 164 152 155 134 160 154 36 157 150 40 151 153 7 161 166 142 35 37 44 163 135 141 + 3 25 151 140 7 5 137 164 2 75 144 159 34 26 157 155 143 163 29 20 33 147 6 4 146 27 165 152 158 141 161 22 154 24 160 31 21 162 150 32 149 19 136 138 145 23 30 148 ICCARM - 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 45 7 6 165 144 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 2 4 44 135 5 3 141 140 159 160 163 + 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 146 7 25 151 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 6 2 4 145 30 5 3 148 147 20 21 23 @@ -1293,25 +1295,25 @@ __cstat - 69 + 57 BICOMP - 127 + 115 ICCARM - 102 + 90 BICOMP - 144 165 152 146 7 6 164 87 43 162 156 149 147 42 143 139 155 134 8 161 166 154 142 45 132 39 137 145 158 136 36 157 150 40 151 153 138 35 37 + 150 151 27 152 7 149 146 31 162 140 8 25 22 26 154 164 24 157 160 155 143 75 144 34 32 163 29 137 165 158 141 159 161 33 19 136 138 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 8 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 8 @@ -1320,25 +1322,25 @@ __cstat - 70 + 58 BICOMP - 128 + 116 ICCARM - 103 + 91 BICOMP - 142 139 137 39 45 132 161 144 145 87 43 143 147 166 154 138 35 37 36 157 150 40 151 153 7 6 165 162 146 156 164 149 152 42 158 155 136 134 + 151 159 34 140 146 27 137 7 149 33 136 138 75 144 165 152 158 141 161 162 19 150 32 25 22 26 154 164 24 157 160 155 143 163 31 29 ICCARM - 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 45 7 6 165 144 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 146 7 25 151 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1347,25 +1349,25 @@ __cstat - 64 + 52 BICOMP - 129 + 117 ICCARM - 104 + 92 BICOMP - 132 161 144 142 45 151 139 147 166 154 39 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 + 137 26 155 157 143 25 164 151 22 154 24 160 75 144 159 34 33 136 138 7 162 149 146 27 140 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1374,25 +1376,25 @@ __cstat - 77 + 65 BICOMP - 130 + 118 ICCARM - 105 + 93 BICOMP - 156 162 149 147 42 151 139 7 6 165 146 164 152 87 43 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 + 137 140 162 151 7 149 146 27 159 34 33 136 138 25 22 26 154 164 24 157 160 155 143 75 144 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1401,25 +1403,25 @@ __cstat - 81 + 69 BICOMP - 131 + 119 ICCARM - 106 + 94 BICOMP - 166 154 39 147 151 139 7 161 144 142 45 132 36 145 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 + 154 160 137 22 24 75 144 151 7 25 26 164 157 155 143 159 34 33 136 138 162 149 146 27 140 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1428,25 +1430,44 @@ __cstat - 71 + 59 BICOMP - 46 + 166 ICCARM - 107 + 95 BICOMP - 142 45 161 144 132 151 139 147 166 154 39 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 + 137 25 164 26 157 155 143 151 22 154 24 160 75 144 159 34 33 136 138 7 162 149 146 27 140 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 + + + + + $PROJ_DIR$\L496\Exe\stm32-bootloader.out + + + ILINK + 87 + + + OBJCOPY + 51 + + + + + ILINK + 88 71 61 107 73 108 109 72 89 74 92 93 94 95 96 97 98 99 100 101 102 103 104 105 90 106 60 91 156 28 139 142 @@ -1455,25 +1476,25 @@ __cstat - 82 + 70 BICOMP - 47 + 35 ICCARM - 108 + 96 BICOMP - 166 154 39 147 151 139 161 144 142 45 132 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 + 154 137 160 22 24 75 144 151 25 26 164 157 155 143 159 34 33 136 138 7 162 149 146 27 140 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1482,25 +1503,25 @@ __cstat - 80 + 68 BICOMP - 48 + 36 ICCARM - 109 + 97 BICOMP - 142 45 161 144 132 151 139 147 166 154 39 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 + 137 164 25 26 157 155 143 151 22 154 24 160 75 144 159 34 33 136 138 7 162 149 146 27 140 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1509,25 +1530,25 @@ __cstat - 74 + 62 BICOMP - 49 + 37 ICCARM - 110 + 98 BICOMP - 164 87 6 43 165 146 152 151 139 162 156 149 147 42 36 145 144 7 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 + 149 146 137 151 27 162 140 159 34 33 136 138 7 25 22 26 154 164 24 157 160 155 143 75 144 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1536,25 +1557,25 @@ __cstat - 76 + 64 BICOMP - 50 + 38 ICCARM - 111 + 99 BICOMP - 164 87 7 6 43 165 146 152 151 139 162 156 149 147 42 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 + 137 149 146 7 151 27 162 140 159 34 33 136 138 25 22 26 154 164 24 157 160 155 143 75 144 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1563,25 +1584,25 @@ __cstat - 75 + 63 BICOMP - 51 + 39 ICCARM - 112 + 100 BICOMP - 43 7 6 164 87 165 146 152 151 139 162 156 149 147 42 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 + 137 7 149 146 151 27 162 140 159 34 33 136 138 25 22 26 154 164 24 157 160 155 143 75 144 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1590,25 +1611,25 @@ __cstat - 90 + 78 BICOMP - 52 + 40 ICCARM - 113 + 101 BICOMP - 156 162 149 147 42 151 139 7 6 165 146 164 152 87 43 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 + 137 162 140 151 7 149 146 27 159 34 33 136 138 25 22 26 154 164 24 157 160 155 143 75 144 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1617,25 +1638,25 @@ __cstat - 89 + 77 BICOMP - 53 + 41 ICCARM - 114 + 102 BICOMP - 164 87 7 6 43 165 146 152 151 139 162 156 149 147 42 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 + 137 149 146 7 151 27 162 140 159 34 33 136 138 25 22 26 154 164 24 157 160 155 143 75 144 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1644,25 +1665,25 @@ __cstat - 94 + 82 BICOMP - 54 + 42 ICCARM - 115 + 103 BICOMP - 144 161 132 142 45 151 139 147 166 154 39 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 + 143 137 157 26 155 25 164 151 22 154 24 160 75 144 159 34 33 136 138 7 162 149 146 27 140 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1671,25 +1692,25 @@ __cstat - 91 + 79 BICOMP - 55 + 43 ICCARM - 116 + 104 BICOMP - 166 154 39 147 151 139 161 144 142 45 132 36 145 7 6 165 162 146 156 164 149 152 42 87 43 157 150 40 153 138 35 37 143 137 158 155 136 134 + 137 160 154 22 24 75 144 151 25 26 164 157 155 143 159 34 33 136 138 7 162 149 146 27 140 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1698,25 +1719,25 @@ __cstat - 95 + 83 BICOMP - 56 + 44 ICCARM - 117 + 105 BICOMP - 166 154 39 151 139 147 36 145 144 7 161 142 45 132 157 150 40 153 138 35 37 6 165 162 146 156 164 149 152 42 87 43 143 137 158 155 136 134 + 137 151 162 140 159 34 33 136 138 149 146 27 165 152 158 141 161 19 7 25 22 26 154 164 24 157 160 155 143 75 144 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1725,25 +1746,25 @@ __cstat - 98 + 86 BICOMP - 57 + 45 ICCARM - 118 + 106 BICOMP - 146 165 152 7 6 164 87 43 151 139 162 156 149 147 42 36 145 144 161 166 154 142 45 132 39 157 150 40 153 138 35 37 143 137 158 155 136 134 + 137 26 155 157 143 25 164 151 22 154 24 160 75 144 159 34 33 136 138 7 162 149 146 27 140 165 152 158 141 161 19 150 32 163 31 29 ICCARM - 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 + 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 @@ -1752,25 +1773,25 @@ __cstat - 96 + 84 BICOMP - 126 + 114 ICCARM - 101 + 89 BICOMP - 141 156 144 135 45 162 149 147 42 44 6 165 146 164 152 87 43 143 139 155 134 163 160 39 5 3 7 161 166 154 142 132 137 145 158 136 159 36 157 150 40 151 153 138 35 37 140 + 148 162 31 140 151 30 146 150 152 145 149 27 34 23 21 5 3 7 25 22 26 154 164 24 157 160 155 143 75 144 32 163 29 20 137 165 158 141 159 161 33 19 136 138 147 ICCARM - 159 160 135 44 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 163 + 20 21 30 145 5 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 3 148 147 23 @@ -1779,25 +1800,25 @@ __cstat - 93 + 81 BICOMP - 78 + 66 ICCARM - 72 + 60 BICOMP - 149 147 45 162 42 39 144 135 141 156 139 137 158 6 165 146 164 152 87 43 145 136 5 3 7 161 166 154 142 132 143 155 134 44 36 157 150 40 151 153 138 35 37 140 + 32 146 151 30 148 162 140 149 27 34 163 29 5 3 7 25 22 26 154 164 24 157 160 155 143 75 144 150 152 31 145 137 165 158 141 159 161 33 19 136 138 147 ICCARM - 44 135 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 + 145 30 5 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 3 148 147 @@ -1806,25 +1827,25 @@ __cstat - 88 + 76 BICOMP - 58 + 46 ICCARM - 119 + 107 BICOMP - 5 135 39 166 154 144 147 139 137 158 160 3 7 161 142 45 132 145 136 159 44 141 6 165 162 146 156 164 149 152 42 87 43 143 155 134 36 157 150 40 151 153 138 35 37 140 + 32 5 160 30 140 154 151 22 24 75 144 21 3 7 25 26 164 157 155 143 34 163 29 20 145 146 148 162 149 27 150 152 31 137 165 158 141 159 161 33 19 136 138 147 ICCARM - 160 135 159 44 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 + 21 30 20 145 5 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 3 148 147 @@ -1833,25 +1854,25 @@ __cstat - 97 + 85 BICOMP - 59 + 47 ICCARM - 120 + 108 BICOMP - 147 149 155 45 162 42 139 144 141 156 143 134 135 6 165 146 164 152 87 43 160 5 3 7 161 166 154 142 132 39 137 145 158 136 44 36 157 150 40 151 153 138 35 37 140 + 151 146 34 148 162 140 30 149 27 150 152 31 21 5 3 7 25 22 26 154 164 24 157 160 155 143 75 144 32 163 29 145 137 165 158 141 159 161 33 19 136 138 147 ICCARM - 44 135 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 160 + 145 30 5 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 3 148 147 21 @@ -1860,44 +1881,25 @@ __cstat - 92 + 80 BICOMP - 60 + 48 ICCARM - 121 + 109 BICOMP - 132 161 144 39 5 3 7 142 45 139 137 158 44 147 166 154 145 136 160 135 141 6 165 162 146 156 164 149 152 42 87 43 143 155 134 159 36 157 150 40 151 153 138 35 37 140 + 32 26 155 157 143 151 5 3 7 25 164 145 22 154 24 160 75 144 140 34 163 29 21 30 146 148 162 149 27 150 152 31 20 137 165 158 141 159 161 33 19 136 138 147 ICCARM - 159 160 135 44 5 45 7 6 165 144 154 87 132 39 145 139 150 40 151 36 137 153 143 157 43 42 142 138 147 161 158 166 162 146 156 35 164 155 37 149 136 152 134 3 141 140 - - - - - $PROJ_DIR$\L496\Exe\stm32-bootloader.out - - - ILINK - 99 - - - OBJCOPY - 63 - - - - - ILINK - 100 83 73 119 85 120 121 84 101 86 104 105 106 107 108 109 110 111 112 113 114 115 116 117 102 118 72 103 148 133 38 41 + 20 21 30 145 5 146 7 25 151 162 75 27 140 152 34 158 141 159 137 32 161 150 165 144 143 149 33 155 22 19 26 154 164 136 24 163 138 157 31 160 29 3 148 147 diff --git a/EWARM/stm32-bootloader.ewp b/EWARM/stm32-bootloader.ewp index a8e35e1..0a58509 100644 --- a/EWARM/stm32-bootloader.ewp +++ b/EWARM/stm32-bootloader.ewp @@ -2061,6 +2061,18 @@ L476 + + $PROJ_DIR$\stm32l476xx_flash.icf + + L496 + + + + $PROJ_DIR$\stm32l496xx_flash.icf + + L476 + + Inc diff --git a/EWARM/stm32-bootloader.ewt b/EWARM/stm32-bootloader.ewt index 4189951..dce087f 100644 --- a/EWARM/stm32-bootloader.ewt +++ b/EWARM/stm32-bootloader.ewt @@ -2323,6 +2323,12 @@ $PROJ_DIR$\startup_stm32l496xx.s + + $PROJ_DIR$\stm32l476xx_flash.icf + + + $PROJ_DIR$\stm32l496xx_flash.icf + Inc diff --git a/Inc/main.h b/Inc/main.h index 243811f..87d642c 100644 --- a/Inc/main.h +++ b/Inc/main.h @@ -2,7 +2,7 @@ #define __MAIN_H /*** Application-Specific Configuration ***************************************/ -#define CONF_BUILD "2017-10-19" /* Bootloader build date */ +#define CONF_BUILD "2017-10-30" /* Bootloader build date */ #define CONF_FILENAME "WGPS2.bin" /* File name of application located on SD card */ #define USE_SWO_TRACE 1 /* For development/debugging: stdout/stderr via SWO trace */ diff --git a/Inc/stm32l4xx_hal_conf.h b/Inc/stm32l4xx_hal_conf.h index d66af1a..7c88039 100644 --- a/Inc/stm32l4xx_hal_conf.h +++ b/Inc/stm32l4xx_hal_conf.h @@ -1,7 +1,10 @@ /** ****************************************************************************** * @file stm32l4xx_hal_conf.h - * @brief HAL configuration file. + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32l4xx_hal_conf.h. ****************************************************************************** * @attention * @@ -30,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_CONF_H @@ -40,74 +43,69 @@ extern "C" { #endif -#include "main.h" /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ - -#define HAL_MODULE_ENABLED -/*#define HAL_ADC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_CAN_MODULE_ENABLED */ -/*#define HAL_COMP_MODULE_ENABLED */ +#define HAL_MODULE_ENABLED +//#define HAL_ADC_MODULE_ENABLED +//#define HAL_CAN_MODULE_ENABLED +//#define HAL_COMP_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_DAC_MODULE_ENABLED */ -/*#define HAL_DCMI_MODULE_ENABLED */ -/*#define HAL_DMA2D_MODULE_ENABLED */ -/*#define HAL_DFSDM_MODULE_ENABLED */ -/*#define HAL_DSI_MODULE_ENABLED */ -/*#define HAL_FIREWALL_MODULE_ENABLED */ -/*#define HAL_GFXMMU_MODULE_ENABLED */ -/*#define HAL_HCD_MODULE_ENABLED */ -/*#define HAL_HASH_MODULE_ENABLED */ -/*#define HAL_I2S_MODULE_ENABLED */ -/*#define HAL_IRDA_MODULE_ENABLED */ -/*#define HAL_IWDG_MODULE_ENABLED */ -/*#define HAL_LTDC_MODULE_ENABLED */ -/*#define HAL_LCD_MODULE_ENABLED */ -/*#define HAL_LPTIM_MODULE_ENABLED */ -/*#define HAL_NAND_MODULE_ENABLED */ -/*#define HAL_NOR_MODULE_ENABLED */ -/*#define HAL_OPAMP_MODULE_ENABLED */ -/*#define HAL_OSPI_MODULE_ENABLED */ -/*#define HAL_OSPI_MODULE_ENABLED */ -/*#define HAL_PCD_MODULE_ENABLED */ -/*#define HAL_QSPI_MODULE_ENABLED */ -/*#define HAL_QSPI_MODULE_ENABLED */ -/*#define HAL_RNG_MODULE_ENABLED */ -/*#define HAL_RTC_MODULE_ENABLED */ -/*#define HAL_SAI_MODULE_ENABLED */ -#define HAL_SD_MODULE_ENABLED -/*#define HAL_SMBUS_MODULE_ENABLED */ -/*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_SWPMI_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ -/*#define HAL_TSC_MODULE_ENABLED */ -/*#define HAL_UART_MODULE_ENABLED */ -/*#define HAL_USART_MODULE_ENABLED */ -/*#define HAL_WWDG_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/*#define HAL_I2C_MODULE_ENABLED */ +//#define HAL_CRYP_MODULE_ENABLED +//#define HAL_DAC_MODULE_ENABLED +//#define HAL_DCMI_MODULE_ENABLED +//#define HAL_DFSDM_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED +//#define HAL_DMA2D_MODULE_ENABLED +//#define HAL_DSI_MODULE_ENABLED +//#define HAL_FIREWALL_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED +//#define HAL_GFXMMU_MODULE_ENABLED +//#define HAL_HASH_MODULE_ENABLED +//#define HAL_HCD_MODULE_ENABLED +//#define HAL_NAND_MODULE_ENABLED +//#define HAL_NOR_MODULE_ENABLED +//#define HAL_SRAM_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +//#define HAL_I2C_MODULE_ENABLED +//#define HAL_IRDA_MODULE_ENABLED +//#define HAL_IWDG_MODULE_ENABLED +//#define HAL_LCD_MODULE_ENABLED +//#define HAL_LPTIM_MODULE_ENABLED +//#define HAL_LTDC_MODULE_ENABLED +//#define HAL_OPAMP_MODULE_ENABLED +//#define HAL_OSPI_MODULE_ENABLED +//#define HAL_PCD_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED +//#define HAL_QSPI_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +//#define HAL_RNG_MODULE_ENABLED +//#define HAL_RTC_MODULE_ENABLED +//#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +//#define HAL_SMARTCARD_MODULE_ENABLED +//#define HAL_SMBUS_MODULE_ENABLED +//#define HAL_SPI_MODULE_ENABLED +//#define HAL_SWPMI_MODULE_ENABLED +//#define HAL_TIM_MODULE_ENABLED +//#define HAL_TSC_MODULE_ENABLED +//#define HAL_UART_MODULE_ENABLED +//#define HAL_USART_MODULE_ENABLED +//#define HAL_WWDG_MODULE_ENABLED + /* ########################## Oscillator Values adaptation ####################*/ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -122,10 +120,11 @@ #if !defined (MSI_VALUE) #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ + /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ @@ -139,19 +138,18 @@ * which is subject to manufacturing process variations. */ #if !defined (HSI48_VALUE) - #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ + #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ - + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ /** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency @@ -161,7 +159,7 @@ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -170,7 +168,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/ + #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/ #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ /** @@ -179,7 +177,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/ + #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/ #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -188,21 +186,20 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ - -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U + */ +#define VDD_VALUE ((uint32_t)3000U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x00U) /*!< tick interrupt priority */ +#define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define INSTRUCTION_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ -/* #define USE_FULL_ASSERT 1U */ +/* #define USE_FULL_ASSERT 1U */ /* ################## SPI peripheral configuration ########################## */ @@ -211,7 +208,7 @@ * Deactivated: CRC code cleaned from driver */ -#define USE_SPI_CRC 0U +#define USE_SPI_CRC 1U /* Includes ------------------------------------------------------------------*/ /** @@ -220,7 +217,6 @@ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32l4xx_hal_rcc.h" - #include "stm32l4xx_hal_rcc_ex.h" #endif /* HAL_RCC_MODULE_ENABLED */ #ifdef HAL_GPIO_MODULE_ENABLED @@ -229,7 +225,6 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32l4xx_hal_dma.h" - #include "stm32l4xx_hal_dma_ex.h" #endif /* HAL_DMA_MODULE_ENABLED */ #ifdef HAL_DFSDM_MODULE_ENABLED @@ -414,9 +409,9 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); + void assert_failed(char *file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ @@ -427,4 +422,5 @@ #endif /* __STM32L4xx_HAL_CONF_H */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/