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ravenoc.core
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CAPI=2:
name: ravenoc:noc:v1.0.1
description: RaveNoC is a configurable HDL for mesh NoCs topology that allows the user to change parameters and setup new configurations
filesets:
rtl:
files:
- src/include/ravenoc_axi_fnc.svh: {is_include_file: true}
- src/include/ravenoc_defines.svh: {is_include_file: true}
- bus_arch_sv_pkg/amba_axi_pkg.sv
- src/include/ravenoc_structs.svh: {is_include_file: true}
- src/include/ravenoc_pkg.sv
- src/ni/axi_csr.sv
- src/ni/axi_slave_if.sv
- src/ni/router_wrapper.sv
- src/ni/async_gp_fifo.sv
- src/ni/cdc_pkt.sv
- src/ni/pkt_proc.sv
- src/ravenoc.sv
- src/router/fifo.sv
- src/router/output_module.sv
- src/router/router_if.sv
- src/router/router_ravenoc.sv
- src/router/rr_arbiter.sv
- src/router/vc_buffer.sv
- src/router/input_router.sv
- src/router/input_module.sv
- src/router/input_datapath.sv
file_type: systemVerilogSource
tb:
files:
- src/ravenoc_wrapper.sv
file_type: systemVerilogSource
targets:
default: &default
filesets: [rtl]
toplevel: ravenoc
#parameters: [DEBUG=1]
lint:
default_tool: verilator
filesets: [rtl]
tools:
verilator:
mode: lint-only
verilator_options: ["--Wno-UNOPTFLAT"]
toplevel: ravenoc
#sim:
#<<: *default
#default_tool: verilator
#description: Simple verilator sim of the NoC
#filesets_append: [tb]
#tools:
#verilator:
#mode: cc
#verilator_options: ["--trace-fst", "--coverage", "--trace-structs", "--Wno-UNOPTFLAT", "--Wno-REDEFMACRO", "--timescale 1ns/100ps"]
#toplevel: ravenoc_wrapper
parameters:
AXI_CDC_REQ:
datatype : int
description : Add/Remove CDC component from the NoC router
paramtype : vlogparam
DEBUG:
datatype : int
description : --
paramtype : vlogparam
provider:
name : github
user : aignacio
repo : ravenoc
version: v1.0.1