diff --git a/Bender.yml b/Bender.yml
index d4e042b..ebebe20 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -17,7 +17,6 @@ sources:
- rtl/riscv_compressed_decoder.sv
- rtl/riscv_controller.sv
- rtl/riscv_cs_registers.sv
- - rtl/riscv_debug_unit.sv
- rtl/riscv_decoder.sv
- rtl/riscv_int_controller.sv
- rtl/riscv_ex_stage.sv
diff --git a/ci/Jenkinsfile b/ci/Jenkinsfile
new file mode 100644
index 0000000..0833865
--- /dev/null
+++ b/ci/Jenkinsfile
@@ -0,0 +1,64 @@
+node ('centos7' + ' && !vm1-centos7'){
+ try {
+ stage('Preparation') {
+ withEnv(['PATH+WHATEVER=/home/balasr/.local/bin:/home/balasr/.riscv/bin']) {
+ checkout scm
+ sh 'pip install --user junit-xml'
+ sh 'git submodule update --init --recursive'
+ dir("tb/core") {
+ sh 'make fpnew/src/fpnew_pkg.sv'
+ }
+ }
+ }
+ stage('Build Firmware') {
+ withEnv(['PATH+WHATEVER=/home/balasr/.local/bin:/home/balasr/.riscv/bin',
+ 'RISCV=/home/balasr/.riscv']) {
+ dir("tb/core") {
+ sh "make firmware/firmware.hex"
+ }
+ dir("tb/dm") {
+ sh "make prog/test.hex"
+ }
+ }
+ }
+ stage('Build RTL') {
+ dir("tb/core") {
+ sh "make vsim-all"
+ }
+ dir("tb/dm") {
+ sh "make vsim-all"
+ }
+ }
+
+ stage('Run Tests') {
+ dir("tb/core") {
+ sh "make firmware-vsim-run 2>&1 | tee test.log"
+ }
+ sh "./ci/rv32tests-to-junit.py -i tb/core/test.log -o rv32_test_report.xml"
+
+ withEnv(['PATH+WHATEVER=/home/balasr/.local/bin:/home/balasr/.riscv/bin',
+ 'RISCV=/home/balasr/.riscv']) {
+ sh "./ci/run-openocd-compliance.sh"
+ sh "./ci/openocd-to-junit.py -i openocd.log -o openocd_test_report.xml"
+
+ }
+ }
+
+ } catch (e) {
+ currentBuild.result = "FAILED"
+ echo "SENDING E-MAIL"
+ notifyFailed()
+ throw e
+ } finally {
+ junit '*.xml'
+ }
+}
+
+def notifyFailed() {
+ emailext (
+ subject: "FAILED: Job '${env.JOB_NAME} [${env.BUILD_NUMBER}]'",
+ body: """FAILED: Job '${env.JOB_NAME} [${env.BUILD_NUMBER}]':
+ Check console output at "${env.JOB_NAME} [${env.BUILD_NUMBER}]"
""",
+ recipientProviders: [[$class: 'DevelopersRecipientProvider']]
+ )
+}
diff --git a/ci/dummy.csh b/ci/dummy.csh
deleted file mode 100755
index bafa6a9..0000000
--- a/ci/dummy.csh
+++ /dev/null
@@ -1,3 +0,0 @@
-#!/bin/tcsh
-
-echo "New commit triggers PULPino CI"
diff --git a/ci/get-openocd.sh b/ci/get-openocd.sh
index ea7570b..a380a1e 100755
--- a/ci/get-openocd.sh
+++ b/ci/get-openocd.sh
@@ -21,7 +21,7 @@ fi
if ! [ -e $RISCV/bin/openocd ]; then
if ! [ -e $RISCV/riscv-openocd ]; then
- git clone --depth 1 https://github.com/riscv/riscv-openocd.git
+ git clone https://github.com/riscv/riscv-openocd.git
fi
check_version automake 1.14 "OpenOCD build"
check_version autoconf 2.64 "OpenOCD build"
diff --git a/ci/openocd-to-junit.py b/ci/openocd-to-junit.py
new file mode 100755
index 0000000..392fb74
--- /dev/null
+++ b/ci/openocd-to-junit.py
@@ -0,0 +1,62 @@
+#!/usr/bin/env python3
+import sys, getopt
+from junit_xml import *
+
+
+def main(argv):
+ inputfile = ''
+ outputfile = ''
+
+ try:
+ opts, args = getopt.getopt(argv,"hi:o:",["ifile=","ofile="])
+ except getopt.GetoptError:
+ print ('openocd-to-junit.py -i -o ')
+ sys.exit(2)
+ for opt, arg in opts:
+ if opt == '-h':
+ print ('openocd-to-junit.py -i -o ')
+ sys.exit()
+ elif opt in ("-i", "--ifile"):
+ inputfile = arg
+ elif opt in ("-o", "--ofile"):
+ outputfile = arg
+
+ test_strings = defaultdict(list)
+ test_timestamps = {}
+ current_testname = ''
+
+ test_cases = []
+ current_test_case = None
+
+ ocd_stdout = ''
+
+ with open(inputfile, 'r') as infile:
+ for line in infile:
+ if 'Info' in line and 'riscv013_test_compliance()' in line:
+ print(line.split(' '))
+ current_testname = ' '.join(line.split(' ')[7:])
+ test_strings[current_testname].append(line)
+ test_timestamps[current_testname] = line.split(' ')[3]
+
+ ocd_stdout += line
+
+ for k,v in test_strings.items():
+ current_test_case = TestCase(k, stdout=''.join(v),
+ timestamp=test_timestamps[k])
+ error_msg = ""
+ for line in v:
+ if 'FAILED' in line:
+ error_msg += line;
+
+ if error_msg:
+ current_test_case.add_error_info(error_msg)
+
+ test_cases.append(current_test_case)
+
+ ts = TestSuite("openocd-compliance", test_cases, stdout=ocd_stdout)
+ # pretty printing is on by default but can be disabled using prettyprint=False
+ with open(outputfile, 'w') as outfile:
+ TestSuite.to_file(outfile, [ts])
+
+if __name__ == "__main__":
+ main(sys.argv[1:])
diff --git a/ci/run-openocd-compliance.sh b/ci/run-openocd-compliance.sh
index df3fb5f..6d0c713 100755
--- a/ci/run-openocd-compliance.sh
+++ b/ci/run-openocd-compliance.sh
@@ -4,30 +4,44 @@ set -e
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
-vsim_out=$(mktemp)
-openocd_out=$(mktemp)
+if [ -z "${RISCV}" ]
+then
+ echo "RISCV is empty"
+ exit 1
+fi
-function clean_up {
- rm ${vsim_out}
- rm ${openocd_out}
- kill 0
+function cleanup {
+ echo "cleaning up processes and tmp files"
+ sleep 2
+ echo "vsim pid is:${vsim_pid} pgid:${vsim_pgid}"
+ if ps -p "${vsim_pid}" > /dev/null
+ then
+ echo "vsim pid exists, killing it"
+ kill -- -"${vsim_pgid}"
+ fi
+ rm "${vsim_out}"
}
-# kill all children if this script exits
-trap "exit" INT TERM
-trap clean_up EXIT
+trap cleanup EXIT
+
+vsim_out=$(mktemp)
+openocd_out=openocd.log
-make -C ${ROOT}/tb/dm clean
-make -C ${ROOT}/tb/dm tb-all
-make -C ${ROOT}/tb/dm prog/test.hex
-make -C ${ROOT}/tb/dm prog-run &> ${vsim_out}&
+make -C "${ROOT}"/tb/dm vsim-run &> "${vsim_out}"&
+# record vsim pid/pgid to kill it if it survives this script
+vsim_pid=$!
+vsim_pgid=$(ps -o pgid= ${vsim_pid} | grep -o [0-9]*)
-( tail -f -n0 ${vsim_out} & ) | grep -m 1 "Listening on port"
+# block until we get "Listening on port" so that we are safe to connect openocd
+coproc grep -m 1 "Listening on port"
+tail -f -n0 "${vsim_out}" --pid "$COPROC_PID" >&"${COPROC[1]}"
echo "Starting openocd"
-${RISCV}/bin/openocd -f ${ROOT}/tb/dm/pulpissimo_compliance_test.cfg |& tee ${openocd_out}
+"${RISCV}"/bin/openocd -f "${ROOT}"/tb/dm/pulpissimo_compliance_test.cfg |& tee "${openocd_out}"
+
-if grep -q "ALL TESTS PASSED" ${openocd_out}; then
+if grep -q "ALL TESTS PASSED" "${openocd_out}"; then
exit 0
fi
exit 1
+
diff --git a/ci/rv32tests-to-junit.py b/ci/rv32tests-to-junit.py
new file mode 100755
index 0000000..94349b2
--- /dev/null
+++ b/ci/rv32tests-to-junit.py
@@ -0,0 +1,58 @@
+#!/usr/bin/env python3
+import sys, getopt
+from junit_xml import *
+
+
+def main(argv):
+ inputfile = ''
+ outputfile = ''
+
+ try:
+ opts, args = getopt.getopt(argv,"hi:o:",["ifile=","ofile="])
+ except getopt.GetoptError:
+ print ('rv32tests-to-junit.py -i -o ')
+ sys.exit(2)
+ for opt, arg in opts:
+ if opt == '-h':
+ print ('rv32tests-to-junit.py -i -o ')
+ sys.exit()
+ elif opt in ("-i", "--ifile"):
+ inputfile = arg
+ elif opt in ("-o", "--ofile"):
+ outputfile = arg
+
+ test_strings = defaultdict(list)
+ current_testname = ''
+
+ test_cases = []
+ current_test_case = None
+
+ with open(inputfile, 'r') as infile:
+ for line in infile:
+ if 'Test Begin' in line:
+ current_testname = line.split('#')[1]
+ if 'Test End' in line:
+ current_testname = ""
+ if current_testname != "":
+ test_strings[current_testname].append(line)
+
+ for k,v in test_strings.items():
+ #test_cases.append(TestCase('Test1', stdout=''.join(v)))
+ current_test_case = TestCase(k, stdout=''.join(v))
+ error_msg = ""
+ for line in v:
+ if 'Assertion violation' in line:
+ error_msg += line;
+
+ if error_msg:
+ current_test_case.add_error_info(error_msg)
+
+ test_cases.append(current_test_case)
+
+ ts = TestSuite("riscv-compliance", test_cases)
+ # pretty printing is on by default but can be disabled using prettyprint=False
+ with open(outputfile, 'w') as outfile:
+ TestSuite.to_file(outfile, [ts])
+
+if __name__ == "__main__":
+ main(sys.argv[1:])
diff --git a/doc/user_manual.doc b/doc/user_manual.doc
index 4697e40..d2bb56d 100644
Binary files a/doc/user_manual.doc and b/doc/user_manual.doc differ
diff --git a/rtl/include/riscv_defines.sv b/rtl/include/riscv_defines.sv
index 4aa64b5..92d97ba 100644
--- a/rtl/include/riscv_defines.sv
+++ b/rtl/include/riscv_defines.sv
@@ -384,9 +384,9 @@ parameter bit C_RVD = 1'b0; // Is D extension enabled - NOT SUPPORTED CURRENTLY
// Transprecision floating-point extensions configuration
parameter bit C_XF16 = 1'b0; // Is half-precision float extension (Xf16) enabled
-parameter bit C_XF16ALT = 1'b1; // Is alternative half-precision float extension (Xf16alt) enabled
+parameter bit C_XF16ALT = 1'b0; // Is alternative half-precision float extension (Xf16alt) enabled
parameter bit C_XF8 = 1'b0; // Is quarter-precision float extension (Xf8) enabled
-parameter bit C_XFVEC = 1'b1; // Is vectorial float extension (Xfvec) enabled
+parameter bit C_XFVEC = 1'b0; // Is vectorial float extension (Xfvec) enabled
// FPnew configuration
parameter C_FPNEW_OPBITS = fpnew_pkg::OP_BITS;
diff --git a/rtl/riscv_controller.sv b/rtl/riscv_controller.sv
index 577580a..c4db18f 100644
--- a/rtl/riscv_controller.sv
+++ b/rtl/riscv_controller.sv
@@ -199,6 +199,8 @@ module riscv_controller
logic debug_mode_q, debug_mode_n;
logic ebrk_force_debug_mode;
+ logic illegal_insn_q, illegal_insn_n;
+
`ifndef SYNTHESIS
// synopsys translate_off
// make sure we are called later so that we do not generate messages for
@@ -274,6 +276,7 @@ module riscv_controller
debug_cause_o = DBG_CAUSE_EBREAK;
debug_mode_n = debug_mode_q;
+ illegal_insn_n = illegal_insn_q;
// a trap towards the debug unit is generated when one of the
// following conditions are true:
// - ebreak instruction encountered
@@ -463,7 +466,7 @@ module riscv_controller
csr_save_cause_o = 1'b1;
csr_cause_o = EXC_CAUSE_ILLEGAL_INSN;
ctrl_fsm_ns = FLUSH_EX;
-
+ illegal_insn_n = 1'b1;
end else begin
//decoding block
@@ -544,19 +547,32 @@ module riscv_controller
// prevent any more instructions from executing
halt_if_o = 1'b1;
- // make sure the current instruction has been executed
+ // we don't handle dret here because its should be illegal
+ // anyway in this context
+
+ // illegal, ecall, ebrk and xrettransition to later to a DBG
+ // state since we need the return address which is
+ // determined later
+
+ // TODO: handle ebrk_force_debug_mode plus single stepping over ebreak
if (id_ready_i) begin
+ // make sure the current instruction has been executed
unique case(1'b1)
+ illegal_insn_i | ecall_insn_i:
+ ctrl_fsm_ns = FLUSH_EX; // TODO: flush ex
+ (~ebrk_force_debug_mode & ebrk_insn_i):
+ ctrl_fsm_ns = FLUSH_EX;
+ mret_insn_i | uret_insn_i:
+ ctrl_fsm_ns = FLUSH_EX;
branch_in_id:
ctrl_fsm_ns = DBG_WAIT_BRANCH;
default:
+ // regular instruction
ctrl_fsm_ns = DBG_FLUSH;
endcase // unique case (1'b1)
end
-
end
-
end //decoding block
endcase
end //valid block
@@ -584,7 +600,9 @@ module riscv_controller
//no jump in this stage as we have to wait one cycle to go to Machine Mode
csr_cause_o = data_we_ex_i ? EXC_CAUSE_STORE_FAULT : EXC_CAUSE_LOAD_FAULT;
ctrl_fsm_ns = FLUSH_WB;
-
+ //putting illegal to 0 as if it was 1, the core is going to jump to the exception of the EX stage,
+ //so the illegal was never executed
+ illegal_insn_n = 1'b0;
end //data erro
else if (ex_valid_i)
//check done to prevent data harzard in the CSR registers
@@ -729,61 +747,68 @@ module riscv_controller
end
else begin
- unique case(1'b1)
- ebrk_insn_i: begin
- //ebreak
- pc_mux_o = PC_EXCEPTION;
- pc_set_o = 1'b1;
- trap_addr_mux_o = TRAP_MACHINE;
- exc_pc_mux_o = EXC_PC_EXCEPTION;
-
- end
- ecall_insn_i: begin
- //ecall
- pc_mux_o = PC_EXCEPTION;
- pc_set_o = 1'b1;
- trap_addr_mux_o = TRAP_MACHINE;
- exc_pc_mux_o = EXC_PC_EXCEPTION;
- // TODO: why is this here, signal only needed for async exceptions
- exc_cause_o = EXC_CAUSE_ECALL_MMODE;
-
- end
- illegal_insn_i: begin
- //exceptions
- pc_mux_o = PC_EXCEPTION;
- pc_set_o = 1'b1;
- trap_addr_mux_o = TRAP_MACHINE;
- exc_pc_mux_o = EXC_PC_EXCEPTION;
-
- end
- mret_insn_i: begin
- csr_restore_mret_id_o = 1'b1;
- ctrl_fsm_ns = XRET_JUMP;
- end
- uret_insn_i: begin
- csr_restore_uret_id_o = 1'b1;
- ctrl_fsm_ns = XRET_JUMP;
- end
- dret_insn_i: begin
- csr_restore_dret_id_o = 1'b1;
- ctrl_fsm_ns = XRET_JUMP;
- end
-
- csr_status_i: begin
-
- end
- pipe_flush_i: begin
- ctrl_fsm_ns = WAIT_SLEEP;
- end
- fencei_insn_i: begin
- // we just jump to instruction after the fence.i since that
- // forces the instruction cache to refetch
- pc_mux_o = PC_FENCEI;
- pc_set_o = 1'b1;
- end
- default:;
- endcase
+ if(illegal_insn_q) begin
+ //exceptions
+ pc_mux_o = PC_EXCEPTION;
+ pc_set_o = 1'b1;
+ trap_addr_mux_o = TRAP_MACHINE;
+ exc_pc_mux_o = EXC_PC_EXCEPTION;
+ illegal_insn_n = 1'b0;
+ if (debug_single_step_i && ~debug_mode_q)
+ ctrl_fsm_ns = DBG_TAKEN_IF;
+ end else begin
+ unique case(1'b1)
+ ebrk_insn_i: begin
+ //ebreak
+ pc_mux_o = PC_EXCEPTION;
+ pc_set_o = 1'b1;
+ trap_addr_mux_o = TRAP_MACHINE;
+ exc_pc_mux_o = EXC_PC_EXCEPTION;
+
+ if (debug_single_step_i && ~debug_mode_q)
+ ctrl_fsm_ns = DBG_TAKEN_IF;
+ end
+ ecall_insn_i: begin
+ //ecall
+ pc_mux_o = PC_EXCEPTION;
+ pc_set_o = 1'b1;
+ trap_addr_mux_o = TRAP_MACHINE;
+ exc_pc_mux_o = EXC_PC_EXCEPTION;
+ // TODO: why is this here, signal only needed for async exceptions
+ exc_cause_o = EXC_CAUSE_ECALL_MMODE;
+
+ if (debug_single_step_i && ~debug_mode_q)
+ ctrl_fsm_ns = DBG_TAKEN_IF;
+ end
+
+ mret_insn_i: begin
+ csr_restore_mret_id_o = 1'b1;
+ ctrl_fsm_ns = XRET_JUMP;
+ end
+ uret_insn_i: begin
+ csr_restore_uret_id_o = 1'b1;
+ ctrl_fsm_ns = XRET_JUMP;
+ end
+ dret_insn_i: begin
+ csr_restore_dret_id_o = 1'b1;
+ ctrl_fsm_ns = XRET_JUMP;
+ end
+ csr_status_i: begin
+
+ end
+ pipe_flush_i: begin
+ ctrl_fsm_ns = WAIT_SLEEP;
+ end
+ fencei_insn_i: begin
+ // we just jump to instruction after the fence.i since that
+ // forces the instruction cache to refetch
+ pc_mux_o = PC_FENCEI;
+ pc_set_o = 1'b1;
+ end
+ default:;
+ endcase
+ end
end
end
@@ -797,13 +822,11 @@ module riscv_controller
//mret
pc_mux_o = PC_MRET;
pc_set_o = 1'b1;
-
end
uret_dec_i: begin
//uret
pc_mux_o = PC_URET;
pc_set_o = 1'b1;
-
end
dret_dec_i: begin
//dret
@@ -811,10 +834,13 @@ module riscv_controller
pc_mux_o = PC_DRET;
pc_set_o = 1'b1;
debug_mode_n = 1'b0;
-
end
default:;
endcase
+
+ if (debug_single_step_i && ~debug_mode_q) begin
+ ctrl_fsm_ns = DBG_TAKEN_IF;
+ end
end
// a branch was in ID when a trying to go to debug rom wait until we can
@@ -905,8 +931,8 @@ module riscv_controller
ctrl_fsm_ns = DBG_TAKEN_ID;
end else if(data_load_event_i) begin
ctrl_fsm_ns = DBG_TAKEN_ID;
- end else if (debug_single_step_i)begin
- // save the next instruction when single stepping
+ end else if (debug_single_step_i) begin
+ // save the next instruction when single stepping regular insn
ctrl_fsm_ns = DBG_TAKEN_IF;
end else begin
ctrl_fsm_ns = DBG_TAKEN_ID;
@@ -1030,6 +1056,8 @@ module riscv_controller
data_err_q <= 1'b0;
debug_mode_q <= 1'b0;
+ illegal_insn_q <= 1'b0;
+
end
else
begin
@@ -1040,7 +1068,9 @@ module riscv_controller
data_err_q <= data_err_i;
- debug_mode_q <= debug_mode_n;
+ debug_mode_q <= debug_mode_n;
+
+ illegal_insn_q <= illegal_insn_n;
end
end
diff --git a/rtl/riscv_cs_registers.sv b/rtl/riscv_cs_registers.sv
index a63d8f9..e7f72bb 100644
--- a/rtl/riscv_cs_registers.sv
+++ b/rtl/riscv_cs_registers.sv
@@ -238,6 +238,7 @@ module riscv_cs_registers
logic [31:0] depc_q, depc_n;
logic [31:0] dscratch0_q, dscratch0_n;
logic [31:0] dscratch1_q, dscratch1_n;
+ logic [31:0] mscratch_q, mscratch_n;
logic [31:0] exception_pc;
Status_t mstatus_q, mstatus_n;
@@ -312,6 +313,8 @@ if(PULP_SECURE==1) begin
};
// mtvec: machine trap-handler base address
12'h305: csr_rdata_int = {mtvec_q, 6'h0, MTVEC_MODE};
+ // mscratch: machine scratch
+ 12'h340: csr_rdata_int = mscratch_q;
// mepc: exception program counter
12'h341: csr_rdata_int = mepc_q;
// mcause: exception cause
@@ -395,6 +398,8 @@ end else begin //PULP_SECURE == 0
12'h301: csr_rdata_int = 32'h0;
// mtvec: machine trap-handler base address
12'h305: csr_rdata_int = {mtvec_q, 6'h0, MTVEC_MODE};
+ // mscratch: machine scratch
+ 12'h340: csr_rdata_int = mscratch_q;
// mepc: exception program counter
12'h341: csr_rdata_int = mepc_q;
// mcause: exception cause
@@ -436,6 +441,7 @@ if(PULP_SECURE==1) begin
fflags_n = fflags_q;
frm_n = frm_q;
fprec_n = fprec_q;
+ mscratch_n = mscratch_q;
mepc_n = mepc_q;
uepc_n = uepc_q;
depc_n = depc_q;
@@ -484,6 +490,10 @@ if(PULP_SECURE==1) begin
12'h305: if (csr_we_int) begin
mtvec_n = csr_wdata_int[31:8];
end
+ // mscratch: machine scratch
+ 12'h340: if (csr_we_int) begin
+ mscratch_n = csr_wdata_int;
+ end
// mepc: exception program counter
12'h341: if (csr_we_int) begin
mepc_n = csr_wdata_int;
@@ -690,6 +700,7 @@ end else begin //PULP_SECURE == 0
fflags_n = fflags_q;
frm_n = frm_q;
fprec_n = fprec_q;
+ mscratch_n = mscratch_q;
mepc_n = mepc_q;
depc_n = depc_q;
dcsr_n = dcsr_q;
@@ -732,6 +743,10 @@ end else begin //PULP_SECURE == 0
mprv: csr_wdata_int[`MSTATUS_MPRV_BITS]
};
end
+ // mscratch: machine scratch
+ 12'h340: if (csr_we_int) begin
+ mscratch_n = csr_wdata_int;
+ end
// mepc: exception program counter
12'h341: if (csr_we_int) begin
mepc_n = csr_wdata_int;
@@ -975,6 +990,7 @@ end //PULP_SECURE
dcsr_q.prv <= PRIV_LVL_M;
dscratch0_q <= '0;
dscratch1_q <= '0;
+ mscratch_q <= '0;
end
else
begin
@@ -1003,7 +1019,7 @@ end //PULP_SECURE
dcsr_q <= dcsr_n;
dscratch0_q<= dscratch0_n;
dscratch1_q<= dscratch1_n;
-
+ mscratch_q <= mscratch_n;
end
end
diff --git a/rtl/riscv_debug_unit.sv b/rtl/riscv_debug_unit.sv
deleted file mode 100644
index cc72a7e..0000000
--- a/rtl/riscv_debug_unit.sv
+++ /dev/null
@@ -1,562 +0,0 @@
-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-////////////////////////////////////////////////////////////////////////////////
-// Engineer: Andreas Traber - atraber@iis.ee.ethz.ch //
-// //
-// Design Name: Debug Unit //
-// Project Name: RI5CY //
-// Language: SystemVerilog //
-// //
-// Description: Debug controller //
-// //
-////////////////////////////////////////////////////////////////////////////////
-
-
-import riscv_defines::*;
-
-module riscv_debug_unit
-(
- input logic clk,
- input logic rst_n,
-
- // Debug Interface
- input logic debug_req_i,
- output logic debug_gnt_o,
- output logic debug_rvalid_o,
- input logic [14:0] debug_addr_i,
- input logic debug_we_i,
- input logic [31:0] debug_wdata_i,
- output logic [31:0] debug_rdata_o,
-
- output logic debug_halted_o,
- input logic debug_halt_i,
- input logic debug_resume_i,
-
- // signals to core
- output logic [DBG_SETS_W-1:0] settings_o,
-
- input logic trap_i, // trap found, need to stop the core now
- input logic [5:0] exc_cause_i, // if it was a trap, then the exception controller knows more
- output logic stall_o, // after we got control, we control the stall signal
- output logic dbg_req_o,
- input logic dbg_ack_i,
-
- // register file read port
- output logic regfile_rreq_o,
- output logic [ 5:0] regfile_raddr_o,
- input logic [31:0] regfile_rdata_i,
-
- // register file write port
- output logic regfile_wreq_o,
- output logic [ 5:0] regfile_waddr_o,
- output logic [31:0] regfile_wdata_o,
-
- // CSR read/write port
- output logic csr_req_o,
- output logic [11:0] csr_addr_o,
- output logic csr_we_o,
- output logic [31:0] csr_wdata_o,
- input logic [31:0] csr_rdata_i,
-
- // Signals for PPC & NPC register
- input logic [31:0] pc_if_i,
- input logic [31:0] pc_id_i,
- input logic [31:0] pc_ex_i,
-
- input logic data_load_event_i,
- input logic instr_valid_id_i,
-
- input logic sleeping_i,
-
- input logic branch_in_ex_i,
- input logic branch_taken_i,
-
- output logic jump_req_o,
- output logic [31:0] jump_addr_o
-);
-
- enum logic [2:0] {RD_NONE, RD_CSR, RD_GPR, RD_DBGA, RD_DBGS} rdata_sel_q, rdata_sel_n;
-
- enum logic [0:0] {FIRST, SECOND} state_q, state_n;
-
- logic [DBG_SETS_W-1:0] settings_q, settings_n;
-
- // for timing critical register file access we need to keep those in FFs
- logic [14:0] addr_q;
- logic [31:0] wdata_q; // mainly for jumps
- logic regfile_rreq_q, regfile_rreq_n;
- logic regfile_fp_sel_q, regfile_fp_sel_n;
- logic jump_req_q, jump_req_n;
-
- // not timing critical
- logic csr_req_q, csr_req_n;
- logic regfile_wreq;
- logic regfile_fp_wr;
-
-
- enum logic [1:0] {RUNNING, HALT_REQ, HALT} stall_cs, stall_ns;
- logic [31:0] dbg_rdata;
- logic dbg_resume;
- logic dbg_halt;
- logic [5:0] dbg_cause_q, dbg_cause_n;
- logic dbg_ssth_q, dbg_ssth_n;
-
- logic ssth_clear;
-
-
- // ppc/npc tracking
- enum logic [1:0] {IFID, IFEX, IDEX} pc_tracking_fsm_cs, pc_tracking_fsm_ns;
- logic [31:0] ppc_int, npc_int;
-
-
- // address decoding, write and read controller
- always_comb
- begin
- rdata_sel_n = RD_NONE;
- state_n = FIRST;
-
- debug_gnt_o = 1'b0;
-
- regfile_rreq_n = 1'b0;
- regfile_wreq = 1'b0;
- csr_req_n = 1'b0;
- csr_we_o = 1'b0;
- jump_req_n = 1'b0;
-
- dbg_resume = 1'b0;
- dbg_halt = 1'b0;
- settings_n = settings_q;
-
- ssth_clear = 1'b0;
-
- regfile_fp_sel_n = 1'b0;
- regfile_fp_wr = 1'b0;
-
- if (debug_req_i) begin
- if (debug_we_i) begin
- //----------------------------------------------------------------------------
- // write access
- //----------------------------------------------------------------------------
- if (debug_addr_i[14]) begin
- // CSR access
- if (state_q == FIRST) begin
- // only grant in second cycle, address and data have been latched by then
- debug_gnt_o = 1'b0;
- state_n = SECOND;
-
- if (debug_halted_o) begin
- // access to internal registers are only allowed when the core is halted
- csr_req_n = 1'b1;
- end
- end else begin
- debug_gnt_o = 1'b1; // grant it even when invalid access to not block
- state_n = FIRST;
- csr_we_o = 1'b1;
- end
- end else begin
- // non-CSR access
- unique case (debug_addr_i[13:8])
- 6'b00_0000: begin // Debug Registers, always accessible
- debug_gnt_o = 1'b1;
-
- unique case (debug_addr_i[6:2])
- 5'b0_0000: begin // DBG_CTRL
- if (debug_wdata_i[16]) begin
- // HALT set
- if (~debug_halted_o) begin
- // not halt, so STOP
- dbg_halt = 1'b1;
- end
- end else begin
- // RESUME set
- if (debug_halted_o) begin
- dbg_resume = 1'b1;
- end
- end
-
- settings_n[DBG_SETS_SSTE] = debug_wdata_i[0];
- end
- 5'b0_0001: begin // DBG_HIT
- ssth_clear = debug_wdata_i[0];
- end
- 5'b0_0010: begin // DBG_IE
- settings_n[DBG_SETS_ECALL] = debug_wdata_i[11];
- settings_n[DBG_SETS_ELSU] = debug_wdata_i[7] | debug_wdata_i[5];
- settings_n[DBG_SETS_EBRK] = debug_wdata_i[3];
- settings_n[DBG_SETS_EILL] = debug_wdata_i[2];
- end
- default:;
- endcase
- end
-
- 6'b10_0000: begin // Debug Registers, only accessible when in debug
- debug_gnt_o = 1'b1; // grant it even when invalid access to not block
-
- if (debug_halted_o) begin
- unique case (debug_addr_i[6:2])
- 5'b0_0000: jump_req_n = 1'b1; // DNPC
- default:;
- endcase
- end
- end
-
- 6'b00_0100: begin // General-Purpose Registers
- debug_gnt_o = 1'b1; // grant it even when invalid access to not block
-
- if (debug_halted_o) begin
- regfile_wreq = 1'b1;
- end
- end
-
- 6'b00_0101: begin // General-Purpose Floating-Point Registers
- debug_gnt_o = 1'b1; // grant it even when invalid access to not block
-
- if (debug_halted_o) begin
- regfile_wreq = 1'b1;
- regfile_fp_wr = 1'b1;
- end
- end
-
- default: debug_gnt_o = 1'b1; // grant it even when invalid access to not block
- endcase
- end
- end else begin
- //----------------------------------------------------------------------------
- // read access
- //----------------------------------------------------------------------------
- if (debug_addr_i[14]) begin
- debug_gnt_o = 1'b1; // grant it even when invalid access to not block
-
- // CSR access
- if (debug_halted_o) begin
- // access to internal registers are only allowed when the core is halted
- csr_req_n = 1'b1;
- rdata_sel_n = RD_CSR;
- end
- end else begin
- // non-CSR access
- unique case (debug_addr_i[13:8])
- 6'b00_0000: begin // Debug Registers, always accessible
- debug_gnt_o = 1'b1;
-
- rdata_sel_n = RD_DBGA;
- end
-
- 6'b10_0000: begin // Debug Registers, only accessible when in debug
- debug_gnt_o = 1'b1; // grant it even when invalid access to not block
-
- rdata_sel_n = RD_DBGS;
- end
-
- 6'b00_0100: begin // General-Purpose Registers
- debug_gnt_o = 1'b1; // grant it even when invalid access to not block
-
- if (debug_halted_o) begin
- regfile_rreq_n = 1'b1;
- rdata_sel_n = RD_GPR;
- end
- end
-
- 6'b00_0101: begin // General-Purpose Floating-Point Registers
- debug_gnt_o = 1'b1; // grant it even when invalid access to not block
-
- if (debug_halted_o) begin
- regfile_rreq_n = 1'b1;
- regfile_fp_sel_n = 1'b1;
- rdata_sel_n = RD_GPR;
- end
- end
- default: debug_gnt_o = 1'b1; // grant it even when invalid access to not block
- endcase
- end
- end
- end
- end
-
- //----------------------------------------------------------------------------
- // debug register read access
- //
- // Since those are combinational, we can do it in the cycle where we set
- // rvalid. The address has been latched into addr_q
- //----------------------------------------------------------------------------
- always_comb
- begin
- dbg_rdata = '0;
-
- case (rdata_sel_q)
- RD_DBGA: begin
- unique case (addr_q[6:2])
- 5'h00: dbg_rdata[31:0] = {15'b0, debug_halted_o, 15'b0, settings_q[DBG_SETS_SSTE]}; // DBG_CTRL
- 5'h01: dbg_rdata[31:0] = {15'b0, sleeping_i, 15'b0, dbg_ssth_q}; // DBG_HIT
- 5'h02: begin // DBG_IE
- dbg_rdata[31:16] = '0;
- dbg_rdata[15:12] = '0;
- dbg_rdata[11] = settings_q[DBG_SETS_ECALL];
- dbg_rdata[10: 8] = '0;
- dbg_rdata[ 7] = settings_q[DBG_SETS_ELSU];
- dbg_rdata[ 6] = 1'b0;
- dbg_rdata[ 5] = settings_q[DBG_SETS_ELSU];
- dbg_rdata[ 4] = 1'b0;
- dbg_rdata[ 3] = settings_q[DBG_SETS_EBRK];
- dbg_rdata[ 2] = settings_q[DBG_SETS_EILL];
- dbg_rdata[ 1: 0] = '0;
- end
- 5'h03: dbg_rdata = {dbg_cause_q[5], 26'b0, dbg_cause_q[4:0]}; // DBG_CAUSE
- 5'h10: dbg_rdata = '0; // DBG_BPCTRL0
- 5'h12: dbg_rdata = '0; // DBG_BPCTRL1
- 5'h14: dbg_rdata = '0; // DBG_BPCTRL2
- 5'h16: dbg_rdata = '0; // DBG_BPCTRL3
- 5'h18: dbg_rdata = '0; // DBG_BPCTRL4
- 5'h1A: dbg_rdata = '0; // DBG_BPCTRL5
- 5'h1C: dbg_rdata = '0; // DBG_BPCTRL6
- 5'h1E: dbg_rdata = '0; // DBG_BPCTRL7
- default:;
- endcase
- end
-
- RD_DBGS: begin
- unique case (addr_q[2:2])
- 1'b0: dbg_rdata = npc_int; // DBG_NPC
- 1'b1: dbg_rdata = ppc_int; // DBG_PPC
- default:;
- endcase
- end
-
- default:;
- endcase
- end
-
- //----------------------------------------------------------------------------
- // read data mux
- //----------------------------------------------------------------------------
- always_comb
- begin
- debug_rdata_o = '0;
-
- case (rdata_sel_q)
- RD_CSR: debug_rdata_o = csr_rdata_i;
- RD_GPR: debug_rdata_o = regfile_rdata_i;
- RD_DBGA: debug_rdata_o = dbg_rdata;
- RD_DBGS: debug_rdata_o = dbg_rdata;
- endcase
- end
-
- //----------------------------------------------------------------------------
- // rvalid generation
- //----------------------------------------------------------------------------
- always_ff @(posedge clk, negedge rst_n)
- begin
- if (~rst_n) begin
- debug_rvalid_o <= 1'b0;
- end else begin
- debug_rvalid_o <= debug_gnt_o; // always give the rvalid one cycle after gnt
- end
- end
-
- //----------------------------------------------------------------------------
- // stall control
- //----------------------------------------------------------------------------
- always_comb
- begin
- stall_ns = stall_cs;
- dbg_req_o = 1'b0;
- stall_o = 1'b0;
- debug_halted_o = 1'b0;
- dbg_cause_n = dbg_cause_q;
- dbg_ssth_n = dbg_ssth_q;
-
- case (stall_cs)
- RUNNING: begin
- dbg_ssth_n = 1'b0;
-
- if (dbg_halt | debug_halt_i | trap_i) begin
- dbg_req_o = 1'b1;
- stall_ns = HALT_REQ;
-
- if (trap_i) begin
- if (settings_q[DBG_SETS_SSTE])
- dbg_ssth_n = 1'b1;
-
- dbg_cause_n = exc_cause_i;
- end else begin
- dbg_cause_n = DBG_CAUSE_HALT;
- end
- end
- end
-
- HALT_REQ: begin
- dbg_req_o = 1'b1;
-
- if (dbg_ack_i)
- stall_ns = HALT;
-
- if (dbg_resume | debug_resume_i)
- stall_ns = RUNNING;
- end
-
- HALT: begin
- stall_o = 1'b1;
- debug_halted_o = 1'b1;
-
- if (dbg_resume | debug_resume_i) begin
- stall_ns = RUNNING;
- stall_o = 1'b0;
- end
- end
- endcase
-
- if (ssth_clear)
- dbg_ssth_n = 1'b0;
- end
-
- always_ff @(posedge clk, negedge rst_n)
- begin
- if (~rst_n) begin
- stall_cs <= RUNNING;
- dbg_cause_q <= DBG_CAUSE_HALT;
- dbg_ssth_q <= 1'b0;
- end else begin
- stall_cs <= stall_ns;
- dbg_cause_q <= dbg_cause_n;
- dbg_ssth_q <= dbg_ssth_n;
- end
- end
-
- //----------------------------------------------------------------------------
- // NPC/PPC selection
- //----------------------------------------------------------------------------
- always_comb
- begin
- pc_tracking_fsm_ns = pc_tracking_fsm_cs;
-
- ppc_int = pc_id_i;
- npc_int = pc_if_i;
-
- // PPC/NPC mux
- unique case (pc_tracking_fsm_cs)
- IFID: begin
- ppc_int = pc_id_i;
- npc_int = pc_if_i;
- end
-
- IFEX: begin
- ppc_int = pc_ex_i;
- npc_int = pc_if_i;
- end
-
- IDEX: begin
- ppc_int = pc_ex_i;
- npc_int = pc_id_i;
-
- if (jump_req_o)
- pc_tracking_fsm_ns = IFEX;
- end
-
- default: begin
- pc_tracking_fsm_ns = IFID;
- end
- endcase
-
- // set state if trap is encountered
- if (dbg_ack_i) begin
- pc_tracking_fsm_ns = IFID;
-
- if (branch_in_ex_i) begin
- if (branch_taken_i)
- pc_tracking_fsm_ns = IFEX;
- else
- pc_tracking_fsm_ns = IDEX;
- end else if (data_load_event_i) begin
- // for p.elw
- if (instr_valid_id_i)
- pc_tracking_fsm_ns = IDEX;
- else
- pc_tracking_fsm_ns = IFEX;
- end
- end
- end
-
-
- always_ff @(posedge clk, negedge rst_n)
- begin
- if (~rst_n) begin
- pc_tracking_fsm_cs <= IFID;
-
- addr_q <= '0;
- wdata_q <= '0;
- state_q <= FIRST;
- rdata_sel_q <= RD_NONE;
- regfile_rreq_q <= 1'b0;
- regfile_fp_sel_q <= 1'b0;
- csr_req_q <= 1'b0;
- jump_req_q <= 1'b0;
-
- settings_q <= 1'b0;
- end else begin
- pc_tracking_fsm_cs <= pc_tracking_fsm_ns;
-
- // settings
- settings_q <= settings_n;
-
- // for the actual interface
- if (debug_req_i) begin
- addr_q <= debug_addr_i;
- wdata_q <= debug_wdata_i;
- state_q <= state_n;
- end
-
- if (debug_req_i | debug_rvalid_o) begin
- // wait for either req or rvalid to set those FFs
- // This makes sure that they are only triggered once when there is
- // only one request, and the FFs can be properly clock gated otherwise
- regfile_rreq_q <= regfile_rreq_n;
- regfile_fp_sel_q <= regfile_fp_sel_n;
- csr_req_q <= csr_req_n;
- jump_req_q <= jump_req_n;
- rdata_sel_q <= rdata_sel_n;
- end
- end
- end
-
- assign regfile_rreq_o = regfile_rreq_q;
- assign regfile_raddr_o = {regfile_fp_sel_q, addr_q[6:2]};
-
-
- assign regfile_wreq_o = regfile_wreq;
- assign regfile_waddr_o = {regfile_fp_wr,debug_addr_i[6:2]};
- assign regfile_wdata_o = debug_wdata_i;
-
- assign csr_req_o = csr_req_q;
- assign csr_addr_o = addr_q[13:2];
- assign csr_wdata_o = wdata_q;
-
- assign jump_req_o = jump_req_q;
- assign jump_addr_o = wdata_q;
-
- assign settings_o = settings_q;
-
- //----------------------------------------------------------------------------
- // Assertions
- //----------------------------------------------------------------------------
- `ifndef VERILATOR
- // check that no registers are accessed when we are not in debug mode
- assert property (
- @(posedge clk) (debug_req_i) |-> ((debug_halted_o == 1'b1) ||
- ((debug_addr_i[14] != 1'b1) &&
- (debug_addr_i[13:7] != 5'b0_1001) &&
- (debug_addr_i[13:7] != 5'b0_1000)) ) )
- else $warning("Trying to access internal debug registers while core is not stalled");
-
- // check that all accesses are word-aligned
- assert property (
- @(posedge clk) (debug_req_i) |-> (debug_addr_i[1:0] == 2'b00) );
- `endif
-endmodule // debug_unit
diff --git a/rtl/riscv_id_stage.sv b/rtl/riscv_id_stage.sv
index dbd9860..78ada7d 100644
--- a/rtl/riscv_id_stage.sv
+++ b/rtl/riscv_id_stage.sv
@@ -954,7 +954,7 @@ module riscv_id_stage
register_file_test_wrap
#(
.ADDR_WIDTH(6),
- .FPU(0) // forcing the register_file fr FP to be disabled
+ .FPU(FPU)
)
registers_i
(
diff --git a/rtl/riscv_pmp.sv b/rtl/riscv_pmp.sv
index d857e67..8fc42ab 100644
--- a/rtl/riscv_pmp.sv
+++ b/rtl/riscv_pmp.sv
@@ -357,7 +357,7 @@ module riscv_pmp
`ifdef DEBUG_RULE $display(" NAPOT[%d] --> BYTE_ALIGN_32KB: %8h<-- addr --> %8h", i, start_addr[i]<<2, stop_addr[i]<<2 ); `endif
end
`endif
- `ifdef EN_NAPOT_RULE_64KBB
+ `ifdef EN_NAPOT_RULE_64KB
`RULE_13:
begin: BYTE_ALIGN_64KB
mask_addr[i] = 32'hFFFF_C000;
diff --git a/src_files.yml b/src_files.yml
index d5b531c..0698e42 100644
--- a/src_files.yml
+++ b/src_files.yml
@@ -30,7 +30,6 @@ riscv:
./rtl/riscv_compressed_decoder.sv,
./rtl/riscv_controller.sv,
./rtl/riscv_cs_registers.sv,
- ./rtl/riscv_debug_unit.sv,
./rtl/riscv_decoder.sv,
./rtl/riscv_int_controller.sv,
./rtl/riscv_ex_stage.sv,
@@ -119,4 +118,4 @@ tb_riscv:
tb/tb_riscv/riscv_perturbation.sv,
tb/tb_riscv/riscv_random_interrupt_generator.sv,
tb/tb_riscv/riscv_random_stall.sv,
- ]
\ No newline at end of file
+ ]
diff --git a/tb/core/README.md b/tb/core/README.md
index ea17cdf..6d14644 100644
--- a/tb/core/README.md
+++ b/tb/core/README.md
@@ -11,9 +11,9 @@ signal success or failure by writing `12345679` or `1` respectively to
Running the testbench with vsim
----------------------
-Point you environment variable `RISCV` to your RISC-V toolchain.
-Call `make firmware-vsim-run` to build the testbench and the firmware, and run it.
-Use `VSIM_FLAGS` to configure the simulator e.g. `make firmware-run
+Point you environment variable `RISCV` to your RISC-V toolchain. Call `make
+firmware-vsim-run` to build the testbench and the firmware, and run it. Use
+`VSIM_FLAGS` to configure the simulator e.g. `make firmware-vsim-run
VSIM_FLAGS="-gui -debugdb"`.
Running the testbench with vcs
@@ -45,4 +45,4 @@ build and link your own program. Have a look at `picorv_firmware/start.S` and
Examples
-----------------------
Run all riscv-tests to completion and produce a vcd dump:
-`make firmware-run VSIM_FLAGS=+vcd`
\ No newline at end of file
+`make firmware-vsim-run VSIM_FLAGS=+vcd`
diff --git a/tb/core/firmware/start.S b/tb/core/firmware/start.S
index 8dc0d16..f087f62 100644
--- a/tb/core/firmware/start.S
+++ b/tb/core/firmware/start.S
@@ -303,7 +303,7 @@ start:
TEST(I_EBREAK_01)
TEST(I_ECALL_01)
TEST(I_ENDIANESS_01)
- TEST(I_FENCE.I_01) /* fails */
+ TEST(I_FENCE.I_01)
TEST(I_IO)
TEST(I_JAL_01)
@@ -318,7 +318,7 @@ start:
/* bad test: RI5CY supports C extension meaning no exception on
misaligned jumps */
/* TEST(I_MISALIGN_JMP_01) */
- TEST(I_MISALIGN_LDST_01) /* fails */
+ /* TEST(I_MISALIGN_LDST_01) /* fails */
TEST(I_NOP_01)
TEST(I_OR_01)
diff --git a/tb/core/riscv_compliance_tests/I-MISALIGN_LDST-01.S b/tb/core/riscv_compliance_tests/disabled/I-MISALIGN_LDST-01.S
similarity index 100%
rename from tb/core/riscv_compliance_tests/I-MISALIGN_LDST-01.S
rename to tb/core/riscv_compliance_tests/disabled/I-MISALIGN_LDST-01.S
diff --git a/tb/dm/remote_bitbang/remote_bitbang.c b/tb/dm/remote_bitbang/remote_bitbang.c
index f4e790f..e77c00d 100644
--- a/tb/dm/remote_bitbang/remote_bitbang.c
+++ b/tb/dm/remote_bitbang/remote_bitbang.c
@@ -258,7 +258,6 @@ void rbs_execute_command()
}
if (quit) {
- // The remote disconnected.
fprintf(stderr, "Remote end disconnected\n");
close(client_fd);
client_fd = 0;
diff --git a/tb/dm/tb_test_env.sv b/tb/dm/tb_test_env.sv
index fe1676f..ce869a5 100644
--- a/tb/dm/tb_test_env.sv
+++ b/tb/dm/tb_test_env.sv
@@ -317,5 +317,9 @@ module tb_test_env
.jtag_TDO_driven ( 1'b1 ),
.exit ( sim_jtag_exit ));
+ always_comb begin : jtag_exit_handler
+ if (sim_jtag_exit)
+ $finish(2); // print stats too
+ end
endmodule // tb_test_env
diff --git a/tb/dm/tb_top.sv b/tb/dm/tb_top.sv
index 409c36e..1b5941c 100644
--- a/tb/dm/tb_top.sv
+++ b/tb/dm/tb_top.sv
@@ -53,6 +53,9 @@ module tb_top
$dumpfile("riscy_tb.vcd");
$dumpvars(0, tb_top);
end
+ if ($test$plusargs("wlfdump")) begin
+ $wlfdumpvars(0, tb_top);
+ end
end
// we either load the provided firmware or execute a small test program that
diff --git a/verilator-model/Makefile b/verilator-model/Makefile
index 8769b0c..d45beda 100644
--- a/verilator-model/Makefile
+++ b/verilator-model/Makefile
@@ -52,7 +52,6 @@ VSRC = cluster_clock_gating.sv \
../rtl/riscv_compressed_decoder.sv \
../rtl/riscv_controller.sv \
../rtl/riscv_cs_registers.sv \
- ../rtl/riscv_debug_unit.sv \
../rtl/riscv_decoder.sv \
../rtl/riscv_int_controller.sv \
../rtl/riscv_ex_stage.sv \