diff --git a/rtl/include/riscv_defines.sv b/rtl/include/riscv_defines.sv index 71c2213..ee4c793 100644 --- a/rtl/include/riscv_defines.sv +++ b/rtl/include/riscv_defines.sv @@ -416,30 +416,6 @@ parameter EXC_CAUSE_STORE_FAULT = 6'h07; parameter EXC_CAUSE_ECALL_UMODE = 6'h08; parameter EXC_CAUSE_ECALL_MMODE = 6'h0B; - -// Possible irq ids -typedef enum logic [4:0] { - NMI_IRQ_ID = 5'd31, - FAST14_IRQ_ID = 5'd30, - FAST13_IRQ_ID = 5'd29, - FAST12_IRQ_ID = 5'd28, - FAST11_IRQ_ID = 5'd27, - FAST10_IRQ_ID = 5'd26, - FAST9_IRQ_ID = 5'd25, - FAST8_IRQ_ID = 5'd24, - FAST7_IRQ_ID = 5'd23, - FAST6_IRQ_ID = 5'd22, - FAST5_IRQ_ID = 5'd21, - FAST4_IRQ_ID = 5'd20, - FAST3_IRQ_ID = 5'd19, - FAST2_IRQ_ID = 5'd18, - FAST1_IRQ_ID = 5'd17, - FAST0_IRQ_ID = 5'd16, - EXTERNAL_IRQ_ID = 5'd11, - TIMER_IRQ_ID = 5'd07, - SOFTWARE_IRQ_ID = 5'd03 -} irq_id_e; - // Interrupt lines struct typedef struct packed { logic irq_software; diff --git a/rtl/riscv_cs_registers.sv b/rtl/riscv_cs_registers.sv index d5d3769..ad45cbf 100644 --- a/rtl/riscv_cs_registers.sv +++ b/rtl/riscv_cs_registers.sv @@ -277,6 +277,7 @@ module riscv_cs_registers Interrupts_t mip; Masked_Interrupts_t mie_q, mie_n; + logic is_irq; PrivLvl_t priv_lvl_n, priv_lvl_q, priv_lvl_reg_q; Pmp_t pmp_reg_q, pmp_reg_n; @@ -983,36 +984,36 @@ end //PULP_SECURE // TODO abet insert nmi_mode_q? if (mip.irq_nmi) begin // EXC_CAUSE_IRQ_NM - irq_id_o = NMI_IRQ_ID; + irq_id_o = {5'd31}; end else if(mip.irq_fast != '0) begin - if (mip.irq_fast[14]) irq_id_o = FAST14_IRQ_ID; - else if (mip.irq_fast[13]) irq_id_o = FAST13_IRQ_ID; - else if (mip.irq_fast[12]) irq_id_o = FAST12_IRQ_ID; - else if (mip.irq_fast[11]) irq_id_o = FAST11_IRQ_ID; - else if (mip.irq_fast[10]) irq_id_o = FAST10_IRQ_ID; - else if (mip.irq_fast[ 9]) irq_id_o = FAST9_IRQ_ID; - else if (mip.irq_fast[ 8]) irq_id_o = FAST8_IRQ_ID; - else if (mip.irq_fast[ 7]) irq_id_o = FAST7_IRQ_ID; - else if (mip.irq_fast[ 6]) irq_id_o = FAST6_IRQ_ID; - else if (mip.irq_fast[ 5]) irq_id_o = FAST5_IRQ_ID; - else if (mip.irq_fast[ 4]) irq_id_o = FAST4_IRQ_ID; - else if (mip.irq_fast[ 3]) irq_id_o = FAST3_IRQ_ID; - else if (mip.irq_fast[ 2]) irq_id_o = FAST2_IRQ_ID; - else if (mip.irq_fast[ 1]) irq_id_o = FAST1_IRQ_ID; - else irq_id_o = FAST0_IRQ_ID; + if (mip.irq_fast[14]) irq_id_o = 5'd30; + else if (mip.irq_fast[13]) irq_id_o = 5'd29; + else if (mip.irq_fast[12]) irq_id_o = 5'd28; + else if (mip.irq_fast[11]) irq_id_o = 5'd27; + else if (mip.irq_fast[10]) irq_id_o = 5'd26; + else if (mip.irq_fast[ 9]) irq_id_o = 5'd25; + else if (mip.irq_fast[ 8]) irq_id_o = 5'd24; + else if (mip.irq_fast[ 7]) irq_id_o = 5'd23; + else if (mip.irq_fast[ 6]) irq_id_o = 5'd22; + else if (mip.irq_fast[ 5]) irq_id_o = 5'd21; + else if (mip.irq_fast[ 4]) irq_id_o = 5'd20; + else if (mip.irq_fast[ 3]) irq_id_o = 5'd19; + else if (mip.irq_fast[ 2]) irq_id_o = 5'd18; + else if (mip.irq_fast[ 1]) irq_id_o = 5'd17; + else irq_id_o = 5'd16; end else if (mip.irq_external) begin // EXC_CAUSE_IRQ_EXTERNAL_M - irq_id_o = EXTERNAL_IRQ_ID; + irq_id_o = {5'd11}; end else if (mip.irq_software) begin // EXC_CAUSE_IRQ_SOFTWARE_M; - irq_id_o = SOFTWARE_IRQ_ID; + irq_id_o = {5'd03}; end else begin // mip.irq_timer // EXC_CAUSE_IRQ_TIMER_M; - irq_id_o = TIMER_IRQ_ID; + irq_id_o = {5'd07}; end end diff --git a/tb/core/Makefile b/tb/core/Makefile index ae6d3be..3b6ec3d 100644 --- a/tb/core/Makefile +++ b/tb/core/Makefile @@ -249,7 +249,7 @@ interrupt_test/interrupt_test.elf: interrupt_test/interrupt_test.c -T interrupt_test/link.ld \ -static \ interrupt_test/crt0.S \ - $^ interrupt_test/syscalls.c custom/vectors.S \ + $^ interrupt_test/syscalls.c interrupt_test/vectors.S \ -I $(RISCV)/riscv32-unknown-elf/include \ -L $(RISCV)/riscv32-unknown-elf/lib \ -lc -lm -lgcc @@ -452,7 +452,7 @@ csmith-loop: riscv-fesvr/build.ok riscv-isa-sim/build.ok # general targets .PHONY: clean -clean: tb-clean verilate-clean vcs-clean firmware-clean csmith-clean custom-clean +clean: tb-clean verilate-clean vcs-clean firmware-clean csmith-clean custom-clean interrupt-clean .PHONY: distclean distclean: clean diff --git a/tb/core/cobj_dir/Vtb_top_verilator b/tb/core/cobj_dir/Vtb_top_verilator index d316d45..dfc4354 100755 Binary files a/tb/core/cobj_dir/Vtb_top_verilator and b/tb/core/cobj_dir/Vtb_top_verilator differ diff --git a/tb/core/cobj_dir/Vtb_top_verilator.cpp b/tb/core/cobj_dir/Vtb_top_verilator.cpp index ceada9f..dbf3936 100644 --- a/tb/core/cobj_dir/Vtb_top_verilator.cpp +++ b/tb/core/cobj_dir/Vtb_top_verilator.cpp @@ -8730,7 +8730,7 @@ void Vtb_top_verilator::_settle__TOP__2(Vtb_top_verilator__Syms* __restrict vlSy = (3U & ((IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__mulh_active) ? (IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__mulh_subword) : VL_NEGATE_I((IData)((IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__mult_sel_subword_ex))))); - vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT____Vcellout__cs_registers_i__irq_id_o + vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_id = ((1U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip) ? 0x1fU : ((0U != (0x7fffU & (vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip >> 1U))) ? @@ -8786,7 +8786,7 @@ void Vtb_top_verilator::_settle__TOP__2(Vtb_top_verilator__Syms* __restrict vlSy : 0x10U)))))))))))))) : ((0x10000U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip) ? 0xbU : ((0x40000U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip) - ? 7U : 3U)))); + ? 3U : 7U)))); vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_pending = (1U & (((((vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip >> 0x12U) | (vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip @@ -25677,7 +25677,7 @@ VL_INLINE_OPT void Vtb_top_verilator::_sequent__TOP__6(Vtb_top_verilator__Syms* & (IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_pending))) { __Vdly__tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__int_controller_i__DOT__exc_ctrl_cs = 1U; vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__int_controller_i__DOT__irq_id_q - = vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT____Vcellout__cs_registers_i__irq_id_o; + = vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_id; vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__int_controller_i__DOT__irq_sec_q = 0U; } } else { @@ -27878,7 +27878,7 @@ VL_INLINE_OPT void Vtb_top_verilator::_sequent__TOP__6(Vtb_top_verilator__Syms* = (3U & ((IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__mulh_active) ? (IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__mulh_subword) : VL_NEGATE_I((IData)((IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__mult_sel_subword_ex))))); - vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT____Vcellout__cs_registers_i__irq_id_o + vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_id = ((1U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip) ? 0x1fU : ((0U != (0x7fffU & (vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip >> 1U))) ? @@ -27934,7 +27934,7 @@ VL_INLINE_OPT void Vtb_top_verilator::_sequent__TOP__6(Vtb_top_verilator__Syms* : 0x10U)))))))))))))) : ((0x10000U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip) ? 0xbU : ((0x40000U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip) - ? 7U : 3U)))); + ? 3U : 7U)))); vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_pending = (1U & (((((vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip >> 0x12U) | (vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip @@ -51303,8 +51303,8 @@ void Vtb_top_verilator::_ctor_var_reset() { tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__instr_req_pmp = VL_RAND_RESET_I(1); tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__instr_gnt_pmp = VL_RAND_RESET_I(1); tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_pending = VL_RAND_RESET_I(1); + tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_id = VL_RAND_RESET_I(5); tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__clk = VL_RAND_RESET_I(1); - tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT____Vcellout__cs_registers_i__irq_id_o = VL_RAND_RESET_I(5); tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__mult_is_clpx_ex = VL_RAND_RESET_I(1); tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__core_clock_gate_i__DOT__clk_en = VL_RAND_RESET_I(1); tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__offset_fsm_cs = VL_RAND_RESET_I(1); diff --git a/tb/core/cobj_dir/Vtb_top_verilator.h b/tb/core/cobj_dir/Vtb_top_verilator.h index b5a1eff..3a17ec1 100644 --- a/tb/core/cobj_dir/Vtb_top_verilator.h +++ b/tb/core/cobj_dir/Vtb_top_verilator.h @@ -121,6 +121,7 @@ VL_MODULE(Vtb_top_verilator) { CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__instr_req_pmp; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__instr_gnt_pmp; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_pending; + CData/*4:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_id; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__mult_is_clpx_ex; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__core_clock_gate_i__DOT__clk_en; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__offset_fsm_cs; @@ -160,9 +161,9 @@ VL_MODULE(Vtb_top_verilator) { CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__illegal_insn_dec; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__ebrk_insn; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__mret_insn_dec; - CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__uret_insn_dec; }; struct { + CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__uret_insn_dec; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__dret_insn_dec; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__ecall_insn_dec; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__pipe_flush_dec; @@ -226,9 +227,9 @@ VL_MODULE(Vtb_top_verilator) { CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__alu_vec_mode; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__scalar_replication; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_ex_is_reg_a_id; - CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_ex_is_reg_b_id; }; struct { + CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_ex_is_reg_b_id; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_ex_is_reg_c_id; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_wb_is_reg_a_id; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_alu_is_reg_a_id; @@ -292,9 +293,9 @@ VL_MODULE(Vtb_top_verilator) { CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__div_ready; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_op_a_signed; IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_popcnt_i__DOT__cnt_l1; - IData/*23:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_popcnt_i__DOT__cnt_l2; }; struct { + IData/*23:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_popcnt_i__DOT__cnt_l2; SData/*15:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_popcnt_i__DOT__cnt_l3; SData/*9:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_popcnt_i__DOT__cnt_l4; WData/*159:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_ff_i__DOT__index_lut[5]; @@ -358,9 +359,9 @@ VL_MODULE(Vtb_top_verilator) { CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__select_rdata_d; CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__select_rdata_q; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__transaction; - CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__state_valid_n; }; struct { + CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__state_valid_n; CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__state_valid_q; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__data_rvalid_q; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__instr_rvalid_q; @@ -424,9 +425,9 @@ VL_MODULE(Vtb_top_verilator) { IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__rdata_last_q; IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__rdata; IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__rdata_unaligned; - WData/*127:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__L0_buffer_i__DOT__L0_buffer[4]; }; struct { + WData/*127:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__L0_buffer_i__DOT__L0_buffer[4]; IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__L0_buffer_i__DOT__addr_q; IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__L0_buffer_i__DOT__instr_addr_int; IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__imm_i_type; @@ -490,9 +491,9 @@ VL_MODULE(Vtb_top_verilator) { IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__BReg_DP; IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__BReg_DN; IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__AddMux_D; - IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__AddTmp_D; }; struct { + IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__AddTmp_D; IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__OutMux_D; IData/*16:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__short_op_a; IData/*16:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__short_op_b; @@ -556,9 +557,9 @@ VL_MODULE(Vtb_top_verilator) { QData/*36:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__adder_result_expanded; QData/*33:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__short_mac; QData/*33:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__short_result; - QData/*32:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__dot_short_result; }; struct { + QData/*32:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__dot_short_result; WData/*67:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__genblk1__DOT__dot_short_mul[3]; WData/*767:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__pmp_reg_q[24]; WData/*767:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__pmp_reg_n[24]; @@ -568,7 +569,6 @@ VL_MODULE(Vtb_top_verilator) { // LOCAL VARIABLES // Internals; generally not touched by application code - CData/*4:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT____Vcellout__cs_registers_i__irq_id_o; CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT____Vcellinp__hwloop_controller_i__hwlp_dec_cnt_id_i; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT____Vcellinp__L0_buffer_i__hwlp_i; CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT____Vlvbound2; diff --git a/tb/core/cobj_dir/Vtb_top_verilator__ALL.a b/tb/core/cobj_dir/Vtb_top_verilator__ALL.a index 04cb56c..0e8a6a7 100644 Binary files a/tb/core/cobj_dir/Vtb_top_verilator__ALL.a and b/tb/core/cobj_dir/Vtb_top_verilator__ALL.a differ diff --git a/tb/core/cobj_dir/Vtb_top_verilator__verFiles.dat b/tb/core/cobj_dir/Vtb_top_verilator__verFiles.dat index be84063..a3337c6 100644 --- a/tb/core/cobj_dir/Vtb_top_verilator__verFiles.dat +++ b/tb/core/cobj_dir/Vtb_top_verilator__verFiles.dat @@ -1,55 +1,55 @@ # DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. -C "--cc --sv --exe --Wno-lint --Wno-UNOPTFLAT --Wno-MODDUP +incdir+../../rtl/include --top-module tb_top_verilator riscv_wrapper.sv dp_ram.sv cluster_clock_gating.sv tb_top_verilator.sv mm_ram.sv fpnew/src/fpnew_pkg.sv ../../rtl/include/apu_core_package.sv ../../rtl/include/riscv_defines.sv ../../rtl/include/riscv_tracer_defines.sv ../../rtl/include/../../tb/tb_riscv/include/perturbation_defines.sv ../../rtl/riscv_if_stage.sv ../../rtl/riscv_hwloop_controller.sv ../../rtl/riscv_decoder.sv ../../rtl/riscv_tracer.sv ../../rtl/riscv_prefetch_buffer.sv ../../rtl/riscv_L0_buffer.sv ../../rtl/riscv_cs_registers.sv ../../rtl/riscv_register_file.sv ../../rtl/riscv_load_store_unit.sv ../../rtl/riscv_id_stage.sv ../../rtl/riscv_core.sv ../../rtl/riscv_compressed_decoder.sv ../../rtl/riscv_fetch_fifo.sv ../../rtl/riscv_alu_div.sv ../../rtl/riscv_prefetch_L0_buffer.sv ../../rtl/riscv_hwloop_regs.sv ../../rtl/riscv_mult.sv ../../rtl/register_file_test_wrap.sv ../../rtl/riscv_int_controller.sv ../../rtl/riscv_ex_stage.sv ../../rtl/riscv_alu_basic.sv ../../rtl/riscv_pmp.sv ../../rtl/riscv_apu_disp.sv ../../rtl/riscv_alu.sv ../../rtl/riscv_controller.sv ../../tb/tb_riscv/riscv_random_stall.sv ../../tb/tb_riscv/riscv_random_interrupt_generator.sv ../../tb/tb_riscv/riscv_interrupt_demux.sv tb_top_verilator.cpp --Mdir cobj_dir -CFLAGS -std=gnu++11 -O2 -Wno-BLKANDNBLK" -S 2084 48184 1576593753 51823944 1576593753 51823944 "../../rtl/include/../../rtl/include/../../tb/tb_riscv/include/perturbation_defines.sv" -S 2780 47173 1574160277 782111548 1574160277 782111548 "../../rtl/include/../../rtl/include/apu_core_package.sv" -S 19527 62313 1576593713 740820743 1576593713 740820743 "../../rtl/include/../../rtl/include/riscv_defines.sv" -S 13523 47569 1574160277 793174208 1574160277 793174208 "../../rtl/include/../../rtl/include/riscv_tracer_defines.sv" -S 6134 48280 1574160277 796004415 1574160277 796004415 "../../rtl/include/../../rtl/register_file_test_wrap.sv" -S 7700 47303 1574160277 799063839 1574160277 799063839 "../../rtl/include/../../rtl/riscv_L0_buffer.sv" -S 44518 47174 1574160277 802444359 1574160277 802444359 "../../rtl/include/../../rtl/riscv_alu.sv" -S 11612 46965 1574160277 812156756 1574160277 812156756 "../../rtl/include/../../rtl/riscv_alu_basic.sv" -S 7275 46966 1574160277 821771026 1574160277 821771026 "../../rtl/include/../../rtl/riscv_alu_div.sv" -S 9890 48386 1574160277 826800389 1574160277 826800389 "../../rtl/include/../../rtl/riscv_apu_disp.sv" -S 12583 47175 1574160277 830183976 1574160277 830183976 "../../rtl/include/../../rtl/riscv_compressed_decoder.sv" -S 40296 47925 1576077149 672785169 1576077149 672785169 "../../rtl/include/../../rtl/riscv_controller.sv" -S 50069 63147 1576595036 363660012 1576595036 363660012 "../../rtl/include/../../rtl/riscv_core.sv" -S 48394 63016 1576594971 133223626 1576594971 133223626 "../../rtl/include/../../rtl/riscv_cs_registers.sv" -S 103907 46579 1574247876 275911230 1574247876 275911230 "../../rtl/include/../../rtl/riscv_decoder.sv" -S 21941 47570 1574160277 846948743 1574160277 846948743 "../../rtl/include/../../rtl/riscv_ex_stage.sv" -S 9749 47794 1574160277 849078305 1574160277 849078305 "../../rtl/include/../../rtl/riscv_fetch_fifo.sv" -S 3565 48161 1574160277 851101418 1574160277 851101418 "../../rtl/include/../../rtl/riscv_hwloop_controller.sv" -S 5091 46704 1574160277 853134890 1574160277 853134890 "../../rtl/include/../../rtl/riscv_hwloop_regs.sv" -S 64090 55138 1576077082 618507950 1576077082 618507950 "../../rtl/include/../../rtl/riscv_id_stage.sv" -S 14825 48281 1574160277 860039725 1574160277 860039725 "../../rtl/include/../../rtl/riscv_if_stage.sv" -S 4196 62709 1576076887 733812411 1576076887 733812411 "../../rtl/include/../../rtl/riscv_int_controller.sv" -S 17099 48162 1574160277 864973697 1574160277 864973697 "../../rtl/include/../../rtl/riscv_load_store_unit.sv" -S 14336 47926 1574160277 867823509 1574160277 867823509 "../../rtl/include/../../rtl/riscv_mult.sv" -S 34147 48282 1574160277 870484463 1574160277 870484463 "../../rtl/include/../../rtl/riscv_pmp.sv" -S 18126 46705 1574160277 872877332 1574160277 872877332 "../../rtl/include/../../rtl/riscv_prefetch_L0_buffer.sv" -S 13168 47571 1574160277 875141735 1574160277 875141735 "../../rtl/include/../../rtl/riscv_prefetch_buffer.sv" -S 6523 46777 1574160277 877275120 1574160277 877275120 "../../rtl/include/../../rtl/riscv_register_file.sv" -S 38701 46778 1574160277 881914366 1574160277 881914366 "../../rtl/include/../../rtl/riscv_tracer.sv" -S 5631 150053 1575554969 454185163 1575554969 454185163 "../../rtl/include/../../tb/tb_riscv/riscv_interrupt_demux.sv" -S 8994 48185 1576593366 122767767 1576593366 122767767 "../../rtl/include/../../tb/tb_riscv/riscv_random_interrupt_generator.sv" -S 7697 48652 1574160279 106136747 1574160279 106136747 "../../rtl/include/../../tb/tb_riscv/riscv_random_stall.sv" -S 3448 47079 1574160277 784843617 1574160277 784843617 "../../rtl/include/apu_macros.sv" -S 1915 47301 1574160277 787309944 1574160277 787309944 "../../rtl/include/riscv_config.sv" +C "--cc --sv --exe --Wno-lint --Wno-UNOPTFLAT --Wno-MODDUP +incdir+../../rtl/include --top-module tb_top_verilator riscv_wrapper.sv dp_ram.sv cluster_clock_gating.sv tb_top_verilator.sv mm_ram.sv fpnew/src/fpnew_pkg.sv ../../rtl/include/apu_core_package.sv ../../rtl/include/riscv_defines.sv ../../rtl/include/riscv_tracer_defines.sv ../../rtl/include/../../tb/tb_riscv/include/perturbation_defines.sv ../../rtl/riscv_if_stage.sv ../../rtl/riscv_hwloop_controller.sv ../../rtl/riscv_tracer.sv ../../rtl/riscv_prefetch_buffer.sv ../../rtl/riscv_hwloop_regs.sv ../../rtl/riscv_int_controller.sv ../../rtl/riscv_cs_registers.sv ../../rtl/riscv_register_file.sv ../../rtl/riscv_load_store_unit.sv ../../rtl/riscv_id_stage.sv ../../rtl/riscv_core.sv ../../rtl/riscv_compressed_decoder.sv ../../rtl/riscv_fetch_fifo.sv ../../rtl/riscv_alu_div.sv ../../rtl/riscv_prefetch_L0_buffer.sv ../../rtl/riscv_decoder.sv ../../rtl/riscv_mult.sv ../../rtl/register_file_test_wrap.sv ../../rtl/riscv_L0_buffer.sv ../../rtl/riscv_ex_stage.sv ../../rtl/riscv_alu_basic.sv ../../rtl/riscv_pmp.sv ../../rtl/riscv_apu_disp.sv ../../rtl/riscv_alu.sv ../../rtl/riscv_controller.sv ../../tb/tb_riscv/riscv_random_stall.sv ../../tb/tb_riscv/riscv_random_interrupt_generator.sv ../../tb/tb_riscv/riscv_interrupt_demux.sv tb_top_verilator.cpp --Mdir cobj_dir -CFLAGS -std=gnu++11 -O2 -Wno-BLKANDNBLK" +S 2084 15284 1577137252 908611084 1577137252 908611084 "../../rtl/include/../../rtl/include/../../tb/tb_riscv/include/perturbation_defines.sv" +S 2780 13784 1577137249 902213154 1577137249 902213154 "../../rtl/include/../../rtl/include/apu_core_package.sv" +S 18907 14979 1577137735 893860124 1577137735 893860124 "../../rtl/include/../../rtl/include/riscv_defines.sv" +S 13523 14273 1577137249 915057721 1577137249 915057721 "../../rtl/include/../../rtl/include/riscv_tracer_defines.sv" +S 6134 14628 1577137249 918079452 1577137249 918079452 "../../rtl/include/../../rtl/register_file_test_wrap.sv" +S 7700 13684 1577137249 921504612 1577137249 921504612 "../../rtl/include/../../rtl/riscv_L0_buffer.sv" +S 44518 14735 1577137249 925575541 1577137249 925575541 "../../rtl/include/../../rtl/riscv_alu.sv" +S 11612 14035 1577137249 928623085 1577137249 928623085 "../../rtl/include/../../rtl/riscv_alu_basic.sv" +S 7275 13398 1577137249 931622312 1577137249 931622312 "../../rtl/include/../../rtl/riscv_alu_div.sv" +S 9890 14036 1577137249 934697831 1577137249 934697831 "../../rtl/include/../../rtl/riscv_apu_disp.sv" +S 12583 13399 1577137249 937902914 1577137249 937902914 "../../rtl/include/../../rtl/riscv_compressed_decoder.sv" +S 40296 14416 1577137249 942198030 1577137249 942198030 "../../rtl/include/../../rtl/riscv_controller.sv" +S 50069 13307 1577137249 946270633 1577137249 946270633 "../../rtl/include/../../rtl/riscv_core.sv" +S 48246 14980 1577137715 981841548 1577137715 981841548 "../../rtl/include/../../rtl/riscv_cs_registers.sv" +S 103907 14860 1577137249 955730848 1577137249 955730848 "../../rtl/include/../../rtl/riscv_decoder.sv" +S 21941 13400 1577137249 959238276 1577137249 959238276 "../../rtl/include/../../rtl/riscv_ex_stage.sv" +S 9749 13308 1577137249 962329835 1577137249 962329835 "../../rtl/include/../../rtl/riscv_fetch_fifo.sv" +S 3565 14514 1577137249 965737127 1577137249 965737127 "../../rtl/include/../../rtl/riscv_hwloop_controller.sv" +S 5091 13685 1577137249 968708501 1577137249 968708501 "../../rtl/include/../../rtl/riscv_hwloop_regs.sv" +S 64090 13309 1577137249 972914333 1577137249 972914333 "../../rtl/include/../../rtl/riscv_id_stage.sv" +S 14825 14981 1577137249 980635799 1577137249 980635799 "../../rtl/include/../../rtl/riscv_if_stage.sv" +S 4196 13785 1577137249 983684522 1577137249 983684522 "../../rtl/include/../../rtl/riscv_int_controller.sv" +S 17099 13786 1577137249 987016296 1577137249 987016296 "../../rtl/include/../../rtl/riscv_load_store_unit.sv" +S 14336 14861 1577137249 990235785 1577137249 990235785 "../../rtl/include/../../rtl/riscv_mult.sv" +S 34147 14862 1577137249 993597264 1577137249 993597264 "../../rtl/include/../../rtl/riscv_pmp.sv" +S 18126 14863 1577137249 997145517 1577137249 997145517 "../../rtl/include/../../rtl/riscv_prefetch_L0_buffer.sv" +S 13168 13310 1577137250 586774 1577137250 586774 "../../rtl/include/../../rtl/riscv_prefetch_buffer.sv" +S 6523 14120 1577137250 22929748 1577137250 22929748 "../../rtl/include/../../rtl/riscv_register_file.sv" +S 38701 13401 1577137250 30647686 1577137250 30647686 "../../rtl/include/../../rtl/riscv_tracer.sv" +S 5631 15285 1577137252 912043906 1577137252 912043906 "../../rtl/include/../../tb/tb_riscv/riscv_interrupt_demux.sv" +S 25866 14893 1577137494 133945633 1577137494 133945633 "../../rtl/include/../../tb/tb_riscv/riscv_random_interrupt_generator.sv" +S 7697 13937 1577137252 922452478 1577137252 922452478 "../../rtl/include/../../tb/tb_riscv/riscv_random_stall.sv" +S 3448 14859 1577137249 905227197 1577137249 905227197 "../../rtl/include/apu_macros.sv" +S 1915 14978 1577137249 908469255 1577137249 908469255 "../../rtl/include/riscv_config.sv" S 5587304 14809169 1575885756 915085370 1575885756 892865246 "/usr/pack/verilator-4.024-af/linux-x64/bin/verilator_bin" -S 1068 47795 1574160277 897016056 1574160277 897016056 "cluster_clock_gating.sv" -T 5390431 160388 1576595946 269334379 1576595946 269334379 "cobj_dir/Vtb_top_verilator.cpp" -T 73630 158566 1576595946 29681191 1576595946 29681191 "cobj_dir/Vtb_top_verilator.h" -T 1903 159280 1576595946 280031725 1576595946 280031725 "cobj_dir/Vtb_top_verilator.mk" -T 1181 160387 1576595946 23923209 1576595946 23923209 "cobj_dir/Vtb_top_verilator__Dpi.cpp" -T 695 159415 1576595946 21997463 1576595946 21997463 "cobj_dir/Vtb_top_verilator__Dpi.h" -T 1727 159057 1576595946 17918338 1576595946 17918338 "cobj_dir/Vtb_top_verilator__Syms.cpp" -T 1532 158564 1576595946 20012876 1576595946 20012876 "cobj_dir/Vtb_top_verilator__Syms.h" -T 882 158821 1576595946 276251430 1576595946 276251430 "cobj_dir/Vtb_top_verilator___024unit.cpp" -T 1017 159633 1576595946 274445104 1576595946 274445104 "cobj_dir/Vtb_top_verilator___024unit.h" -T 2322 158460 1576595946 282005707 1576595946 282005707 "cobj_dir/Vtb_top_verilator__ver.d" -T 0 0 1576595946 327108119 1576595946 327108119 "cobj_dir/Vtb_top_verilator__verFiles.dat" -T 1349 159634 1576595946 278024907 1576595946 278024907 "cobj_dir/Vtb_top_verilator_classes.mk" -S 3383 47572 1574160277 936770777 1574160277 936770777 "dp_ram.sv" -S 17133 48400 1574162313 646001747 1574162313 646001747 "fpnew/src/fpnew_pkg.sv" -S 25861 78916 1576574311 839315298 1576574311 839315298 "mm_ram.sv" -S 7323 48778 1576161302 940806128 1576161302 940806128 "riscv_wrapper.sv" -S 3845 47952 1574160278 819174233 1574160278 819174233 "tb_top_verilator.sv" +S 1068 13311 1577137250 84169389 1577137250 84169389 "cluster_clock_gating.sv" +T 5390311 15040 1577137791 499513137 1577137791 499513137 "cobj_dir/Vtb_top_verilator.cpp" +T 73604 15181 1577137791 274537724 1577137791 274537724 "cobj_dir/Vtb_top_verilator.h" +T 1903 14942 1577137791 509829064 1577137791 509829064 "cobj_dir/Vtb_top_verilator.mk" +T 1181 14587 1577137791 267688416 1577137791 267688416 "cobj_dir/Vtb_top_verilator__Dpi.cpp" +T 695 14586 1577137791 265389383 1577137791 265389383 "cobj_dir/Vtb_top_verilator__Dpi.h" +T 1727 14939 1577137791 260563338 1577137791 260563338 "cobj_dir/Vtb_top_verilator__Syms.cpp" +T 1532 14709 1577137791 262977912 1577137791 262977912 "cobj_dir/Vtb_top_verilator__Syms.h" +T 882 15408 1577137791 506102384 1577137791 506102384 "cobj_dir/Vtb_top_verilator___024unit.cpp" +T 1017 14940 1577137791 504393177 1577137791 504393177 "cobj_dir/Vtb_top_verilator___024unit.h" +T 2322 16000 1577137791 511798062 1577137791 511798062 "cobj_dir/Vtb_top_verilator__ver.d" +T 0 0 1577137791 560119080 1577137791 560119080 "cobj_dir/Vtb_top_verilator__verFiles.dat" +T 1349 14941 1577137791 508000543 1577137791 508000543 "cobj_dir/Vtb_top_verilator_classes.mk" +S 3383 13508 1577137250 326459789 1577137250 326459789 "dp_ram.sv" +S 17133 15138 1577137567 750078389 1577137567 750078389 "fpnew/src/fpnew_pkg.sv" +S 25866 14418 1577137463 685576625 1577137463 685576625 "mm_ram.sv" +S 7323 13421 1577137251 978335772 1577137251 978335772 "riscv_wrapper.sv" +S 3845 15006 1577137251 990099447 1577137251 990099447 "tb_top_verilator.sv" diff --git a/tb/core/interrupt_test/interrupt_test.c b/tb/core/interrupt_test/interrupt_test.c index bd78d6d..1f92cc4 100644 --- a/tb/core/interrupt_test/interrupt_test.c +++ b/tb/core/interrupt_test/interrupt_test.c @@ -9,7 +9,7 @@ #define ERR_CODE_WRONG_ORDER 2 #define ERR_CODE_WRONG_NUM 3 -#define OUTPORT 0x10000000 +#define OUTPORT 0x10000000 #define RND_STALL_REG_10 0x16000028 #define RND_STALL_REG_11 0x1600002C @@ -17,8 +17,6 @@ #define RND_STALL_REG_13 0x16000034 #define RND_STALL_IRQ_REG 0x16000038 -#define RND_STALL_IRQ_MODE_REG 0x16000028 - #define IRQ_MODE_RND 2 #define IRQ_MODE_SD 4 @@ -56,30 +54,6 @@ volatile uint32_t first_irq_pending = 0; volatile uint32_t rnd_ie_mask = 0; volatile uint32_t mmstatus = 0; - -uint32_t IRQ_ID [IRQ_NUM] = -{ - SOFTWARE_IRQ_ID , // 0 - TIMER_IRQ_ID , // 1 - EXTERNAL_IRQ_ID , // 2 - FAST0_IRQ_ID , // 3 - FAST1_IRQ_ID , // 4 - FAST2_IRQ_ID , // 5 - FAST3_IRQ_ID , // 6 - FAST4_IRQ_ID , // 7 - FAST5_IRQ_ID , // 8 - FAST6_IRQ_ID , // 9 - FAST7_IRQ_ID , // 10 - FAST8_IRQ_ID , // 11 - FAST9_IRQ_ID , // 12 - FAST10_IRQ_ID , // 13 - FAST11_IRQ_ID , // 14 - FAST12_IRQ_ID , // 15 - FAST13_IRQ_ID , // 16 - FAST14_IRQ_ID , // 17 - NMI_IRQ_ID // 18 -}; - uint32_t IRQ_ID_PRIORITY [IRQ_NUM] = { NMI_IRQ_ID , // 0 @@ -254,7 +228,6 @@ uint32_t random_num(uint32_t upper_bound, uint32_t lower_bound) uint32_t num = (rand() % (upper_bound - lower_bound + 1)) + lower_bound; return num; } - void mstatus_enable(uint32_t bit_enabled) { asm volatile("csrr %0, mstatus": "=r" (mmstatus)); @@ -262,10 +235,10 @@ void mstatus_enable(uint32_t bit_enabled) asm volatile("csrw mstatus, %[mmstatus]" : : [mmstatus] "r" (mmstatus)); } -void mstatus_disable(uint32_t bit_enabled) +void mstatus_disable(uint32_t bit_disabled) { asm volatile("csrr %0, mstatus": "=r" (mmstatus)); - mmstatus &= (~(1 << bit_enabled)); + mmstatus &= (~(1 << bit_disabled)); asm volatile("csrw mstatus, %[mmstatus]" : : [mmstatus] "r" (mmstatus)); } @@ -281,11 +254,8 @@ int main(int argc, char *argv[]) uint32_t regVal; volatile uint32_t* baseAddr; - // enable mstatus.mie - asm volatile("csrr %0, mstatus": "=r" (mmstatus)); - mmstatus |= (1 << 3); - asm volatile("csrw mstatus, %[mmstatus]" : : [mmstatus] "r" (mmstatus)); - + // enable mstatus.mie + mstatus_enable(MSTATUS_MIE_BIT); // Enable all mie (need to store) regVal = 0xFFFFFFFF; @@ -293,35 +263,36 @@ int main(int argc, char *argv[]) : : [regVal] "r" (regVal)); // set timer_irq_mask_q[TIMER_IRQ_ID] = 1 - // writew(128,0x15000000); + writew(128,0x15000000); // software defined irq gen mode - writew(IRQ_MODE_SD,RND_STALL_REG_10); + writew(4,0x16000028); // Sequential test (no masking) - // disable mstatus.mie - mstatus_disable(MSTATUS_MIE_BIT); + // disable mstatues.mie + mstatus_disable(MSTATUS_MIE_BIT); + for (int i = 0; i < IRQ_NUM; i++) { // add new pending irq - irq_pending |= (1 << IRQ_ID[i]); + irq_pending |= (1 << IRQ_ID_PRIORITY[i]); prev_irq_pending = irq_pending; writew(irq_pending, RND_STALL_IRQ_REG); // enable mstatus.mie - asm volatile("csrwi mstatus, 0x8"); - + mstatus_enable(MSTATUS_MIE_BIT); + // wait for the irq to be served while(prev_irq_pending == irq_pending); // irq_id sampling and testing - if(IRQ_ID[i] != irq_id) + if(IRQ_ID_PRIORITY[i] != irq_id) { - printf("TEST1: IRQ served in wrong order %d %d\n", IRQ_ID[i], irq_id); + printf("TEST1: IRQ served in wrong order %d %d\n", IRQ_ID_PRIORITY[i], irq_id); return -1; } }; @@ -331,7 +302,7 @@ int main(int argc, char *argv[]) // Multiple interrupts at a time irq_pending |= 0xFFFFFFFF; - // disable mstatus.mie + // disable mstatues.mie mstatus_disable(MSTATUS_MIE_BIT); writew(irq_pending, RND_STALL_IRQ_REG); @@ -342,7 +313,7 @@ int main(int argc, char *argv[]) prev_irq_pending=irq_pending; // enable mstatus.mie - mstatus_enable(MSTATUS_MIE_BIT); + mstatus_enable(MSTATUS_MIE_BIT); // wait for nex irq to be served while(prev_irq_pending==irq_pending); @@ -378,7 +349,7 @@ int main(int argc, char *argv[]) // build ie word randomly for (int i = 0; i < RND_IE_NUM; ++i) { - rnd_ie_mask |= (1 << IRQ_ID[random_num(IRQ_NUM, 0)]) ; + rnd_ie_mask |= (1 << IRQ_ID_PRIORITY[random_num(IRQ_NUM, 0)]) ; } @@ -388,17 +359,16 @@ int main(int argc, char *argv[]) // build irq word randomly for (int i = 0; i < RND_IRQ_NUM; ++i) { - irq_pending |= (1 << IRQ_ID[random_num(IRQ_NUM, 0)]) ; + irq_pending |= (1 << IRQ_ID_PRIORITY[random_num(IRQ_NUM, 0)]) ; } first_irq_pending = irq_pending; - // disable mstatus.mie + // disable mstatues.mie mstatus_disable(MSTATUS_MIE_BIT); writew(irq_pending, RND_STALL_IRQ_REG); - // Scan all interrupt bits following priority order for (int i = 0; i < IRQ_NUM; ++i) { // test if the nmi irq should be served @@ -406,11 +376,11 @@ int main(int argc, char *argv[]) { // sample irq_pending prev_irq_pending=irq_pending; + printf("received irq %d\n", irq_id); // enable mstatus.mie mstatus_enable(MSTATUS_MIE_BIT); - // wait for next irq to be served while(prev_irq_pending==irq_pending); @@ -431,7 +401,6 @@ int main(int argc, char *argv[]) // enable mstatus.mie mstatus_enable(MSTATUS_MIE_BIT); - // wait for next irq to be served while(prev_irq_pending==irq_pending); diff --git a/tb/core/mm_ram.sv b/tb/core/mm_ram.sv index ac66a82..d3912e7 100644 --- a/tb/core/mm_ram.sv +++ b/tb/core/mm_ram.sv @@ -412,10 +412,10 @@ module mm_ram .en_a_i ( ram_instr_req ), .addr_a_i ( ram_instr_addr ), - .wdata_a_i ( '0 ), // Not writing so ignored + .wdata_a_i ( '0 ), // Not writing so ignored .rdata_a_o ( ram_instr_rdata ), .we_a_i ( '0 ), - .be_a_i ( 4'b1111 ), // Always want 32-bits + .be_a_i ( 4'b1111 ), // Always want 32-bits .en_b_i ( ram_data_req ), .addr_b_i ( ram_data_addr ), @@ -689,4 +689,4 @@ assign irq_nmi_o = irq_rnd_lines.irq_nmi; `endif -endmodule // ram +endmodule // ram \ No newline at end of file diff --git a/tb/core/testbench_verilator b/tb/core/testbench_verilator index d316d45..dfc4354 100755 Binary files a/tb/core/testbench_verilator and b/tb/core/testbench_verilator differ diff --git a/tb/core/transcript b/tb/core/transcript index d5080b9..4a3ed2c 100644 --- a/tb/core/transcript +++ b/tb/core/transcript @@ -13,9 +13,9 @@ # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // -# vsim "+firmware=custom/hello_world.hex" -gui -debugdb tb_top_vopt -do "vsim.tcl" -# Start time: 11:12:51 on Dec 19,2019 -# Loading /tmp/bettatia@larain1.ee.ethz.ch_dpi_72577/linux_x86_64_gcc-5.3.0/export_tramp.so +# vsim "+firmware=interrupt_test/interrupt_test.hex" -gui -debugdb tb_top_vopt -do "vsim.tcl" +# Start time: 23:00:17 on Dec 23,2019 +# Loading /tmp/bettatia@larain1.ee.ethz.ch_dpi_26625/linux_x86_64_gcc-5.3.0/export_tramp.so # Loading sv_std.std # Loading work.tb_top(fast) # Loading work.riscv_wrapper(fast) @@ -76,8 +76,8 @@ # Time: 0 ns Iteration: 0 Instance: /tb_top/riscv_wrapper_i/ram_i/data_random_stalls File: mm_ram.sv Line: 634 # ** Warning: (vsim-3015) [PCDPC] - Port size (32) does not match connection size (22) for port 'addr_mem_o'. The port definition is at: ../../tb/tb_riscv/riscv_random_stall.sv(52). # Time: 0 ns Iteration: 0 Instance: /tb_top/riscv_wrapper_i/ram_i/data_random_stalls File: mm_ram.sv Line: 634 -# Compiling /tmp/bettatia@larain1.ee.ethz.ch_dpi_72577/linux_x86_64_gcc-5.3.0/exportwrapper.c -# Loading /tmp/bettatia@larain1.ee.ethz.ch_dpi_72577/linux_x86_64_gcc-5.3.0/vsim_auto_compile.so +# Compiling /tmp/bettatia@larain1.ee.ethz.ch_dpi_26625/linux_x86_64_gcc-5.3.0/exportwrapper.c +# Loading /tmp/bettatia@larain1.ee.ethz.ch_dpi_26625/linux_x86_64_gcc-5.3.0/vsim_auto_compile.so # ** Note: (vsim-8716) Reusing existing debug database vsim.dbg. # do vsim.tcl # 1 @@ -86,13 +86,149 @@ # Time: 0 ns Iteration: 0 Process: /tb_top/riscv_wrapper_i/riscv_core_i/RISCY_PMP/pmp_unit_i/#ALWAYS#673 File: ../../rtl/riscv_pmp.sv Line: 677 # ** Warning: (vsim-8315) No condition is true in the unique/priority if/case statement. # Time: 0 ns Iteration: 1 Process: /tb_top/riscv_wrapper_i/riscv_core_i/RISCY_PMP/pmp_unit_i/#ALWAYS#673 File: ../../rtl/riscv_pmp.sv Line: 677 -# ecall exception handler entered -# -# hello world! -# EXIT SUCCESS -# ** Note: $finish : tb_top.sv(137) -# Time: 38530 ns Iteration: 1 Instance: /tb_top -# 1 -# Break in Module tb_top at tb_top.sv line 137 -# End time: 11:20:54 on Dec 19,2019, Elapsed time: 0:08:03 -# Errors: 0, Warnings: 6 +# TEST 1 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 29 +# IRQ SERVED: irq_ id = 28 +# IRQ SERVED: irq_ id = 27 +# IRQ SERVED: irq_ id = 26 +# IRQ SERVED: irq_ id = 25 +# IRQ SERVED: irq_ id = 24 +# IRQ SERVED: irq_ id = 23 +# IRQ SERVED: irq_ id = 22 +# IRQ SERVED: irq_ id = 21 +# IRQ SERVED: irq_ id = 20 +# IRQ SERVED: irq_ id = 19 +# IRQ SERVED: irq_ id = 18 +# IRQ SERVED: irq_ id = 17 +# IRQ SERVED: irq_ id = 16 +# IRQ SERVED: irq_ id = 11 +# IRQ SERVED: irq_ id = 3 +# IRQ SERVED: irq_ id = 7 +# TEST 2: TRIGGER ALL IRQS AT ONCE +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 29 +# IRQ SERVED: irq_ id = 28 +# IRQ SERVED: irq_ id = 27 +# IRQ SERVED: irq_ id = 26 +# IRQ SERVED: irq_ id = 25 +# IRQ SERVED: irq_ id = 24 +# IRQ SERVED: irq_ id = 23 +# IRQ SERVED: irq_ id = 22 +# IRQ SERVED: irq_ id = 21 +# IRQ SERVED: irq_ id = 20 +# IRQ SERVED: irq_ id = 19 +# IRQ SERVED: irq_ id = 18 +# IRQ SERVED: irq_ id = 17 +# IRQ SERVED: irq_ id = 16 +# IRQ SERVED: irq_ id = 11 +# IRQ SERVED: irq_ id = 3 +# IRQ SERVED: irq_ id = 7 +# STARTING TEST 3: RANDOMIZE +# received irq 0 +# IRQ SERVED: irq_ id = 31 +# received irq 31 +# IRQ SERVED: irq_ id = 30 +# received irq 30 +# IRQ SERVED: irq_ id = 29 +# received irq 29 +# IRQ SERVED: irq_ id = 28 +# received irq 28 +# IRQ SERVED: irq_ id = 27 +# received irq 27 +# IRQ SERVED: irq_ id = 26 +# received irq 26 +# IRQ SERVED: irq_ id = 25 +# received irq 25 +# IRQ SERVED: irq_ id = 24 +# received irq 24 +# IRQ SERVED: irq_ id = 23 +# received irq 23 +# IRQ SERVED: irq_ id = 22 +# received irq 22 +# IRQ SERVED: irq_ id = 21 +# received irq 21 +# IRQ SERVED: irq_ id = 20 +# received irq 20 +# IRQ SERVED: irq_ id = 19 +# received irq 19 +# IRQ SERVED: irq_ id = 18 +# received irq 18 +# IRQ SERVED: irq_ id = 17 +# received irq 17 +# IRQ SERVED: irq_ id = 16 +# received irq 16 +# IRQ SERVED: irq_ id = 11 +# received irq 11 +# IRQ SERVED: irq_ id = 3 +# received irq 3 +# IRQ SERVED: irq_ id = 7 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 29 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 29 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 29 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 29 +# IRQ SERVED: irq_ id = 28 +# IRQ SERVED: irq_ id = 29 +# IRQ SERVED: irq_ id = 26 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 28 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 28 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 28 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 28 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 27 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 29 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 27 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 29 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 27 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 27 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 28 +# IRQ SERVED: irq_ id = 28 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 24 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 28 +# IRQ SERVED: irq_ id = 29 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 29 +# IRQ SERVED: irq_ id = 24 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 31 +# IRQ SERVED: irq_ id = 30 +# IRQ SERVED: irq_ id = 31 diff --git a/tb/core/work/_info b/tb/core/work/_info index bcee00d..2724fea 100644 --- a/tb/core/work/_info +++ b/tb/core/work/_info @@ -11,8 +11,8 @@ Z0 d/home/bettatia/prj/abet/riscv/tb/core valu_ff Z1 DXx6 sv_std 3 std 0 22 >9az<^>2ff9DAl3OFGaAf1 Z2 DXx4 work 9 fpnew_pkg 0 22 aE3G]UFG:kFRG@`QPPLS42 -Z3 DXx4 work 13 riscv_defines 0 22 IC[eY5O?TgclD67z2`51e1 -Z4 DXx4 work 17 riscv_alu_sv_unit 0 22 2jRIL^94Wkg6XnHA[GHXX3 +Z3 DXx4 work 13 riscv_defines 0 22 Pm15?Ca7]`R]V062>=NU`2 +Z4 DXx4 work 17 riscv_alu_sv_unit 0 22 aRDTCD0OS=kYHQejQ2TKP1 Z5 VDg1SIo80bB@j0V0VzS_@n1 r1 !s85 0 @@ -22,15 +22,15 @@ IeZGL;89AP=ZF7=1=8A=Bh2 Z6 !s105 riscv_alu_sv_unit S1 R0 -Z7 w1574160277 +Z7 w1577137249 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-work|work|+incdir+../../rtl/include|-pedanticerrors|-suppress|2577|-suppress|2583|fpnew/src/fpnew_pkg.sv|../../rtl/include/apu_core_package.sv|../../rtl/include/riscv_defines.sv|../../rtl/include/riscv_tracer_defines.sv|../../rtl/include/../../tb/tb_riscv/include/perturbation_defines.sv|../../rtl/riscv_if_stage.sv|../../rtl/riscv_hwloop_controller.sv|../../rtl/riscv_decoder.sv|../../rtl/riscv_tracer.sv|../../rtl/riscv_prefetch_buffer.sv|../../rtl/riscv_L0_buffer.sv|../../rtl/riscv_cs_registers.sv|../../rtl/riscv_register_file.sv|../../rtl/riscv_load_store_unit.sv|../../rtl/riscv_id_stage.sv|../../rtl/riscv_core.sv|../../rtl/riscv_compressed_decoder.sv|../../rtl/riscv_fetch_fifo.sv|../../rtl/riscv_alu_div.sv|../../rtl/riscv_prefetch_L0_buffer.sv|../../rtl/riscv_hwloop_regs.sv|../../rtl/riscv_mult.sv|../../rtl/register_file_test_wrap.sv|../../rtl/riscv_int_controller.sv|../../rtl/riscv_ex_stage.sv|../../rtl/riscv_alu_basic.sv|../../rtl/riscv_pmp.sv|../../rtl/riscv_apu_disp.sv|../../rtl/riscv_alu.sv|../../rtl/riscv_controller.sv|../../tb/tb_riscv/riscv_random_stall.sv|../../tb/tb_riscv/riscv_random_interrupt_generator.sv|../../tb/tb_riscv/riscv_interrupt_demux.sv|riscv_wrapper.sv|dp_ram.sv|cluster_clock_gating.sv|tb_top.sv|mm_ram.sv| +Z11 !s108 1577137870.000000 +Z12 !s107 ../../rtl/include/apu_macros.sv|../../rtl/include/riscv_config.sv|mm_ram.sv|tb_top.sv|cluster_clock_gating.sv|dp_ram.sv|riscv_wrapper.sv|../../tb/tb_riscv/riscv_interrupt_demux.sv|../../tb/tb_riscv/riscv_random_interrupt_generator.sv|../../tb/tb_riscv/riscv_random_stall.sv|../../rtl/riscv_controller.sv|../../rtl/riscv_alu.sv|../../rtl/riscv_apu_disp.sv|../../rtl/riscv_pmp.sv|../../rtl/riscv_alu_basic.sv|../../rtl/riscv_ex_stage.sv|../../rtl/riscv_L0_buffer.sv|../../rtl/register_file_test_wrap.sv|../../rtl/riscv_mult.sv|../../rtl/riscv_decoder.sv|../../rtl/riscv_prefetch_L0_buffer.sv|../../rtl/riscv_alu_div.sv|../../rtl/riscv_fetch_fifo.sv|../../rtl/riscv_compressed_decoder.sv|../../rtl/riscv_core.sv|../../rtl/riscv_id_stage.sv|../../rtl/riscv_load_store_unit.sv|../../rtl/riscv_register_file.sv|../../rtl/riscv_cs_registers.sv|../../rtl/riscv_int_controller.sv|../../rtl/riscv_hwloop_regs.sv|../../rtl/riscv_prefetch_buffer.sv|../../rtl/riscv_tracer.sv|../../rtl/riscv_hwloop_controller.sv|../../rtl/riscv_if_stage.sv|../../rtl/include/../../tb/tb_riscv/include/perturbation_defines.sv|../../rtl/include/riscv_tracer_defines.sv|../../rtl/include/riscv_defines.sv|../../rtl/include/apu_core_package.sv|fpnew/src/fpnew_pkg.sv| +Z13 !s90 -work|work|+incdir+../../rtl/include|-pedanticerrors|-suppress|2577|-suppress|2583|fpnew/src/fpnew_pkg.sv|../../rtl/include/apu_core_package.sv|../../rtl/include/riscv_defines.sv|../../rtl/include/riscv_tracer_defines.sv|../../rtl/include/../../tb/tb_riscv/include/perturbation_defines.sv|../../rtl/riscv_if_stage.sv|../../rtl/riscv_hwloop_controller.sv|../../rtl/riscv_tracer.sv|../../rtl/riscv_prefetch_buffer.sv|../../rtl/riscv_hwloop_regs.sv|../../rtl/riscv_int_controller.sv|../../rtl/riscv_cs_registers.sv|../../rtl/riscv_register_file.sv|../../rtl/riscv_load_store_unit.sv|../../rtl/riscv_id_stage.sv|../../rtl/riscv_core.sv|../../rtl/riscv_compressed_decoder.sv|../../rtl/riscv_fetch_fifo.sv|../../rtl/riscv_alu_div.sv|../../rtl/riscv_prefetch_L0_buffer.sv|../../rtl/riscv_decoder.sv|../../rtl/riscv_mult.sv|../../rtl/register_file_test_wrap.sv|../../rtl/riscv_L0_buffer.sv|../../rtl/riscv_ex_stage.sv|../../rtl/riscv_alu_basic.sv|../../rtl/riscv_pmp.sv|../../rtl/riscv_apu_disp.sv|../../rtl/riscv_alu.sv|../../rtl/riscv_controller.sv|../../tb/tb_riscv/riscv_random_stall.sv|../../tb/tb_riscv/riscv_random_interrupt_generator.sv|../../tb/tb_riscv/riscv_interrupt_demux.sv|riscv_wrapper.sv|dp_ram.sv|cluster_clock_gating.sv|tb_top.sv|mm_ram.sv| !i113 0 Z14 o-suppress 2577 -suppress 2583 -work work -pedanticerrors -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact Z15 !s92 -suppress 2577 -suppress 2583 -work work +incdir+../../rtl/include -pedanticerrors -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact @@ -64,7 +64,7 @@ R15 R16 Xapu_core_package R1 -Z17 !s110 1576749546 +Z17 !s110 1577137870 !i10b 1 !s100 bDiC[h[idlDL[0g5iD6l63 IVm0O1JLWP;3;V41Y9[[=U0 @@ -88,7 +88,7 @@ R15 R16 vcluster_clock_gating R1 -Z18 !s110 1576749547 +R17 !i10b 1 !s100 E90Uk_A8JmH@m@5j7b?Z53 IOiZ:ncgjJc6jH=GNP_Cbg1 @@ -96,7 +96,7 @@ R5 !s105 cluster_clock_gating_sv_unit S1 R0 -R7 +Z18 w1577137250 8cluster_clock_gating.sv Fcluster_clock_gating.sv Z19 L0 11 @@ -113,7 +113,7 @@ R15 R16 vdp_ram R1 -R18 +R17 !i10b 1 !s100 2;gaEMY41`RQB5=_[C_df3 I>@O2XdhTS9Ul:2AobY:b0 IANLIFL9YE[@LJfT3iNYmj2 @@ -170,7 +170,7 @@ R5 !s105 mm_ram_sv_unit S1 R0 -w1576574311 +w1577137463 8mm_ram.sv Fmm_ram.sv L0 18 @@ -194,7 +194,7 @@ I8HnUjcW3:j3IGRL@2 @@ -251,7 +251,7 @@ R0 R7 R8 R9 -Z22 L0 31 +Z23 L0 31 R10 31 R11 @@ -265,7 +265,7 @@ vriscv_alu_basic R1 R2 R3 -DXx4 work 23 riscv_alu_basic_sv_unit 0 22 4ke:0bSe9E@;10X9oGf[k2 +DXx4 work 23 riscv_alu_basic_sv_unit 0 22 H]C]T0MKDm68;BdGBd7N=2 R5 r1 !s85 0 @@ -276,9 +276,9 @@ II]YHkahjZO47UEL``9K>B1 S1 R0 R7 -Z23 8../../rtl/riscv_alu_basic.sv -Z24 F../../rtl/riscv_alu_basic.sv -Z25 L0 30 +Z24 8../../rtl/riscv_alu_basic.sv +Z25 F../../rtl/riscv_alu_basic.sv +Z26 L0 30 R10 31 R11 @@ -292,19 +292,19 @@ Xriscv_alu_basic_sv_unit R1 R2 R3 -V4ke:0bSe9E@;10X9oGf[k2 +VH]C]T0MKDm68;BdGBd7N=2 r1 !s85 0 !i10b 1 !s100 7WGdhceHlP2lV[VA9o_d51 -I4ke:0bSe9E@;10X9oGf[k2 +IH]C]T0MKDm68;BdGBd7N=2 !i103 1 S1 R0 R7 -R23 R24 -Z26 L0 28 +R25 +Z27 L0 28 R10 31 R11 @@ -316,7 +316,7 @@ R15 R16 vriscv_alu_div R1 -R18 +R17 !i10b 1 !s100 39?MUBCc[lAdFcB<29D<50 IZ0bSZf@_cN@icbJVY@A651 @@ -327,7 +327,7 @@ R0 R7 8../../rtl/riscv_alu_div.sv F../../rtl/riscv_alu_div.sv -Z27 L0 26 +Z28 L0 26 R10 r1 !s85 0 @@ -343,19 +343,19 @@ Xriscv_alu_sv_unit R1 R2 R3 -V2jRIL^94Wkg6XnHA[GHXX3 +VaRDTCD0OS=kYHQejQ2TKP1 r1 !s85 0 !i10b 1 !s100 PG@4_72<;`O22:66XVUEb2 -I2jRIL^94Wkg6XnHA[GHXX3 +IaRDTCD0OS=kYHQejQ2TKP1 !i103 1 S1 R0 R7 R8 R9 -Z28 L0 29 +Z29 L0 29 R10 31 R11 @@ -367,7 +367,7 @@ R15 R16 vriscv_apu_disp R1 -Z29 DXx4 work 16 apu_core_package 0 22 Vm0O1JLWP;3;V41Y9[[=U0 +Z30 DXx4 work 16 apu_core_package 0 22 Vm0O1JLWP;3;V41Y9[[=U0 DXx4 work 22 riscv_apu_disp_sv_unit 0 22 KEEMWng8akL1CzbE<=^Tj2 R5 r1 @@ -379,9 +379,9 @@ IE_M17V4HO_]lz5f_O?MG72 S1 R0 R7 -Z30 8../../rtl/riscv_apu_disp.sv -Z31 F../../rtl/riscv_apu_disp.sv -Z32 L0 27 +Z31 8../../rtl/riscv_apu_disp.sv +Z32 F../../rtl/riscv_apu_disp.sv +Z33 L0 27 R10 31 R11 @@ -393,7 +393,7 @@ R15 R16 Xriscv_apu_disp_sv_unit R1 -R29 +R30 VKEEMWng8akL1CzbE<=^Tj2 r1 !s85 0 @@ -404,10 +404,10 @@ IKEEMWng8akL1CzbE<=^Tj2 S1 R0 R7 -R30 R31 -Z33 F../../rtl/include/apu_macros.sv -Z34 L0 15 +R32 +Z34 F../../rtl/include/apu_macros.sv +Z35 L0 15 R10 31 R11 @@ -421,7 +421,7 @@ vriscv_compressed_decoder R1 R2 R3 -DXx4 work 32 riscv_compressed_decoder_sv_unit 0 22 XFKd3f=TNIGES;>Md<3Z@2 +DXx4 work 32 riscv_compressed_decoder_sv_unit 0 22 :MQ?EoP2`?zFKEQPNjMOF0 R5 r1 !s85 0 @@ -432,9 +432,9 @@ IH0 S1 R0 R7 -Z35 8../../rtl/riscv_compressed_decoder.sv -Z36 F../../rtl/riscv_compressed_decoder.sv -R25 +Z36 8../../rtl/riscv_compressed_decoder.sv +Z37 F../../rtl/riscv_compressed_decoder.sv +R26 R10 31 R11 @@ -448,19 +448,19 @@ Xriscv_compressed_decoder_sv_unit R1 R2 R3 -VXFKd3f=TNIGES;>Md<3Z@2 +V:MQ?EoP2`?zFKEQPNjMOF0 r1 !s85 0 !i10b 1 !s100 ]_`YCQO[C@4N7ofB>oK]`1 -IXFKd3f=TNIGES;>Md<3Z@2 +I:MQ?EoP2`?zFKEQPNjMOF0 !i103 1 S1 R0 R7 -R35 R36 -R26 +R37 +R27 R10 31 R11 @@ -474,7 +474,7 @@ vriscv_controller R1 R2 R3 -DXx4 work 24 riscv_controller_sv_unit 0 22 UR;`gl`T7iVG5[zI6BLbc3 +DXx4 work 24 riscv_controller_sv_unit 0 22 ]a:;l3;4E@>j7A9^0aXVf0 R5 r1 !s85 0 @@ -484,7 +484,7 @@ IfzB6e<j7A9^0aXVf0 r1 !s85 0 !i10b 1 !s100 >MM5]XjSVM6RkiSHa8jV<0 -IUR;`gl`T7iVG5[zI6BLbc3 +I]a:;l3;4E@>j7A9^0aXVf0 !i103 1 S1 R0 -R37 +R7 R38 R39 -R25 +R26 R10 31 R11 @@ -525,22 +525,22 @@ R15 R16 vriscv_core R1 -R29 +R30 R2 R3 -DXx4 work 18 riscv_core_sv_unit 0 22 BnkAdBQadKE7;[80b5bf73 +DXx4 work 18 riscv_core_sv_unit 0 22 bn2boj6jCX]YXc7fN[BVG3 R5 r1 !s85 0 !i10b 1 !s100 lOdHD4aY8aQKBhgd9EdJ50 -IBV0o66@>0b8;?7nXgk9hO0 +I5aYh:9;iDl`>AdG9b;FJE3 !s105 riscv_core_sv_unit S1 R0 -Z41 w1576595036 -Z42 8../../rtl/riscv_core.sv -Z43 F../../rtl/riscv_core.sv +R7 +Z41 8../../rtl/riscv_core.sv +Z42 F../../rtl/riscv_core.sv L0 38 R10 31 @@ -553,22 +553,22 @@ R15 R16 Xriscv_core_sv_unit R1 -R29 +R30 R2 R3 -VBnkAdBQadKE7;[80b5bf73 +Vbn2boj6jCX]YXc7fN[BVG3 r1 !s85 0 !i10b 1 !s100 8h>E[;TS0T3Y0lG[GcWXS2 -IBnkAdBQadKE7;[80b5bf73 +Ibn2boj6jCX]YXc7fN[BVG3 !i103 1 S1 R0 +R7 R41 R42 -R43 -Z44 F../../rtl/include/riscv_config.sv +Z43 F../../rtl/include/riscv_config.sv R40 R10 31 @@ -583,20 +583,20 @@ vriscv_cs_registers R1 R2 R3 -DXx4 work 26 riscv_cs_registers_sv_unit 0 22 DDe_S5nT=ie=U@1 +DXx4 work 26 riscv_cs_registers_sv_unit 0 22 RWT_G_X=6i_MJ;bRcP6zK1 R5 r1 !s85 0 !i10b 1 -!s100 l=_GeBP4oL<@o_E8NnJ`W0 -IO=zIQ^zijER?hggG3KUPT3 +!s100 2A5mT@>?1Zd?4MHTCgl113 +IM_S5nT=ie=U@1 +VRWT_G_X=6i_MJ;bRcP6zK1 r1 !s85 0 !i10b 1 -!s100 K1IDa^oNiSb?C4Sol13R@1 -IDDe_S5nT=ie=U@1 +!s100 6Mi:dXbbz[l5G6h^DECSN1 +IRWT_G_X=6i_MJ;bRcP6zK1 !i103 1 S1 R0 +R44 R45 R46 -R47 -R28 +R29 R10 31 R11 @@ -634,10 +634,10 @@ R15 R16 vriscv_decoder R1 -R29 +R30 R2 R3 -DXx4 work 21 riscv_decoder_sv_unit 0 22 7ZkEP3IUKDMjSSR6D0BVobmFe1 R5 r1 !s85 0 @@ -647,9 +647,9 @@ I]NjnT;1B;GoF7@]ZeL_;12 !s105 riscv_decoder_sv_unit S1 R0 -Z49 w1574247876 -Z50 8../../rtl/riscv_decoder.sv -Z51 F../../rtl/riscv_decoder.sv +R7 +Z48 8../../rtl/riscv_decoder.sv +Z49 F../../rtl/riscv_decoder.sv R40 R10 31 @@ -662,23 +662,23 @@ R15 R16 Xriscv_decoder_sv_unit R1 -R29 +R30 R2 R3 -V7ZkEP3IUKDMjSSR6D0BVobmFe1 r1 !s85 0 !i10b 1 !s100 >0zaUKDMjSSR6D0BVobmFe1 !i103 1 S1 R0 +R7 +R48 R49 -R50 -R51 -R33 R34 +R35 R10 31 R11 @@ -693,15 +693,15 @@ R1 R2 R17 !i10b 1 -!s100 7K[L[eYHd8PR1 +IPm15?Ca7]`R]V062>=NU`2 +VPm15?Ca7]`R]V062>=NU`2 S1 R0 -w1576598524 +w1577137735 8../../rtl/include/riscv_defines.sv F../../rtl/include/riscv_defines.sv -R27 +R28 R10 r1 !s85 0 @@ -715,10 +715,10 @@ R15 R16 vriscv_ex_stage R1 -R29 +R30 R2 R3 -DXx4 work 22 riscv_ex_stage_sv_unit 0 22 gE04M4[GeVm4HK1g`f;j40 +DXx4 work 22 riscv_ex_stage_sv_unit 0 22 ?Lzl^[Z4X`V[b:4JRL7ag2 R5 r1 !s85 0 @@ -729,9 +729,9 @@ I]ZkiBjlJCX?aG[59XZTO<1 S1 R0 R7 -Z52 8../../rtl/riscv_ex_stage.sv -Z53 F../../rtl/riscv_ex_stage.sv -Z54 L0 40 +Z50 8../../rtl/riscv_ex_stage.sv +Z51 F../../rtl/riscv_ex_stage.sv +Z52 L0 40 R10 31 R11 @@ -743,23 +743,23 @@ R15 R16 Xriscv_ex_stage_sv_unit R1 -R29 +R30 R2 R3 -VgE04M4[GeVm4HK1g`f;j40 +V?Lzl^[Z4X`V[b:4JRL7ag2 r1 !s85 0 !i10b 1 -!s100 lb`8Gaj@TNIn5eGA[UbXO0 -IgE04M4[GeVm4HK1g`f;j40 +!s100 cSEIHE5W=@J0G=NHbXo@T0 +I?Lzl^[Z4X`V[b:4JRL7ag2 !i103 1 S1 R0 R7 -R52 -R53 -R33 +R50 +R51 R34 +R35 R10 31 R11 @@ -771,7 +771,7 @@ R15 R16 vriscv_fetch_fifo R1 -R18 +R17 !i10b 1 !s100 Nozlk87J6Rbbl<_V9JPWe2 IPkbXzKfeL^VI3YjWKCR`k0 @@ -782,7 +782,7 @@ R0 R7 8../../rtl/riscv_fetch_fifo.sv F../../rtl/riscv_fetch_fifo.sv -Z55 L0 25 +Z53 L0 25 R10 r1 !s85 0 @@ -796,7 +796,7 @@ R15 R16 vriscv_hwloop_controller R1 -R18 +R17 !i10b 1 !s100 g^oj90oXEIBjBJ`BK5TNO0 I4znzNJAFO:zW0 I1`kYO9WnWgazk>2I:ZU^>0 @@ -832,7 +832,7 @@ R0 R7 8../../rtl/riscv_hwloop_regs.sv F../../rtl/riscv_hwloop_regs.sv -R55 +R53 R10 r1 !s85 0 @@ -848,8 +848,8 @@ vriscv_id_stage R1 R2 R3 -R29 -DXx4 work 22 riscv_id_stage_sv_unit 0 22 :7;1Y7:ek=Tj?g`2_Cc>72 +R30 +DXx4 work 22 riscv_id_stage_sv_unit 0 22 Io]nz4N5ZJgSX5]Lhc^:>1 R5 r1 !s85 0 @@ -859,10 +859,10 @@ IcI1zezX6iADHARgfMlWHT2 !s105 riscv_id_stage_sv_unit S1 R0 -Z56 w1576077082 -Z57 8../../rtl/riscv_id_stage.sv -Z58 F../../rtl/riscv_id_stage.sv -R54 +R7 +Z54 8../../rtl/riscv_id_stage.sv +Z55 F../../rtl/riscv_id_stage.sv +R52 R10 31 R11 @@ -876,20 +876,20 @@ Xriscv_id_stage_sv_unit R1 R2 R3 -R29 -V:7;1Y7:ek=Tj?g`2_Cc>72 +R30 +VIo]nz4N5ZJgSX5]Lhc^:>1 r1 !s85 0 !i10b 1 !s100 YIaiKOk72 +IIo]nz4N5ZJgSX5]Lhc^:>1 !i103 1 S1 R0 -R56 -R57 -R58 -R25 +R7 +R54 +R55 +R26 R10 31 R11 @@ -903,7 +903,7 @@ vriscv_if_stage R1 R2 R3 -DXx4 work 22 riscv_if_stage_sv_unit 0 22 FH4dWbnALN33MV5I2Wg@L2 +DXx4 work 22 riscv_if_stage_sv_unit 0 22 Fh8KB3=P@P@T];Vom5`_k3 R5 r1 !s85 0 @@ -914,9 +914,9 @@ II8SK>UScMYiQ_=AzP8l]I3 S1 R0 R7 -Z59 8../../rtl/riscv_if_stage.sv -Z60 F../../rtl/riscv_if_stage.sv -R22 +Z56 8../../rtl/riscv_if_stage.sv +Z57 F../../rtl/riscv_if_stage.sv +R23 R10 31 R11 @@ -930,19 +930,19 @@ Xriscv_if_stage_sv_unit R1 R2 R3 -VFH4dWbnALN33MV5I2Wg@L2 +VFh8KB3=P@P@T];Vom5`_k3 r1 !s85 0 !i10b 1 !s100 nJZd9CW`<1l6i8zW0a]h]0 -IFH4dWbnALN33MV5I2Wg@L2 +IFh8KB3=P@P@T];Vom5`_k3 !i103 1 S1 R0 R7 -R59 -R60 -R28 +R56 +R57 +R29 R10 31 R11 @@ -956,7 +956,7 @@ vriscv_int_controller R1 R2 R3 -DXx4 work 28 riscv_int_controller_sv_unit 0 22 S9ZbT<2 !s105 riscv_interrupt_demux_sv_unit S1 R0 -Z65 w1575554969 -Z66 8../../tb/tb_riscv/riscv_interrupt_demux.sv -Z67 F../../tb/tb_riscv/riscv_interrupt_demux.sv -R25 +R22 +Z61 8../../tb/tb_riscv/riscv_interrupt_demux.sv +Z62 F../../tb/tb_riscv/riscv_interrupt_demux.sv +R26 R10 31 R11 @@ -1037,21 +1037,21 @@ Xriscv_interrupt_demux_sv_unit R1 R2 R3 -R64 -VYiNfBUfEA1I@1XTe@i3Y<3 +R60 +VQT^2beBT]IUZa0:60g6no0 r1 !s85 0 !i10b 1 !s100 8Vg9h^<9OV0=hkYk;gKLR81 @@ -1228,10 +1228,10 @@ R5 !s105 riscv_prefetch_buffer_sv_unit S1 R0 -R7 +R18 8../../rtl/riscv_prefetch_buffer.sv F../../rtl/riscv_prefetch_buffer.sv -R32 +R33 R10 r1 !s85 0 @@ -1245,7 +1245,7 @@ R15 R16 vriscv_prefetch_L0_buffer R1 -R18 +R17 !i10b 1 !s100 <_zaLJX@5QnAQJ9a41IU[1 I6fZT[8J]fn[YhefbAliK61 @@ -1256,7 +1256,7 @@ R0 R7 8../../rtl/riscv_prefetch_L0_buffer.sv F../../rtl/riscv_prefetch_L0_buffer.sv -R27 +R28 R10 r1 !s85 0 @@ -1273,21 +1273,21 @@ vriscv_random_interrupt_generator R1 R2 R3 -R64 -DXx4 work 40 riscv_random_interrupt_generator_sv_unit 0 22 V;NDa`H`oOa8P?7RLdg`<3 +R60 +DXx4 work 40 riscv_random_interrupt_generator_sv_unit 0 22 jVURiU[cXFj_jbM3A38JP0 R5 r1 !s85 0 !i10b 1 -!s100 iSA8;@FL44MjAZ4Oof:mW0 -Il1>6=A]7KfR_>Jzogl6fV0 +!s100 k>bX@bN4::iN57CT=o:UTSg2 !s105 riscv_random_interrupt_generator_sv_unit S1 R0 -Z72 w1576593366 -Z73 8../../tb/tb_riscv/riscv_random_interrupt_generator.sv -Z74 F../../tb/tb_riscv/riscv_random_interrupt_generator.sv -R22 +Z67 w1577137865 +Z68 8../../tb/tb_riscv/riscv_random_interrupt_generator.sv +Z69 F../../tb/tb_riscv/riscv_random_interrupt_generator.sv +R23 R10 31 R11 @@ -1301,21 +1301,21 @@ Xriscv_random_interrupt_generator_sv_unit R1 R2 R3 -R64 -VV;NDa`H`oOa8P?7RLdg`<3 +R60 +VjVURiU[cXFj_jbM3A38JP0 r1 !s85 0 !i10b 1 !s100 ;?WlK0V@K:IA@mM6^P6bW2 -IV;NDa`H`oOa8P?7RLdg`<3 +IjVURiU[cXFj_jbM3A38JP0 !i103 1 S1 R0 -R72 -R73 -R74 -R44 -R32 +R67 +R68 +R69 +R43 +R33 R10 31 R11 @@ -1329,8 +1329,8 @@ vriscv_random_stall R1 R2 R3 -R64 -DXx4 work 26 riscv_random_stall_sv_unit 0 22 4:H:7OMQSKXLUYMcTXD5m0 +R60 +DXx4 work 26 riscv_random_stall_sv_unit 0 22 nY0JQkja6jeI]jznWRJE[1 R5 r1 !s85 0 @@ -1340,10 +1340,10 @@ IA;ID8FKOJoNUbNE72a6A@7RjB`>3 IO_9FRDKRY7LG_>_hHXlhf3 @@ -1391,10 +1391,10 @@ R5 !s105 riscv_register_file_sv_unit S1 R0 -R7 +R18 8../../rtl/riscv_register_file.sv F../../rtl/riscv_register_file.sv -R25 +R26 R10 r1 !s85 0 @@ -1410,8 +1410,8 @@ vriscv_tracer R1 R2 R3 -Z78 DXx4 work 20 riscv_tracer_defines 0 22 D:L4E;^_cJSbJ2ON[4W3L2 -DXx4 work 20 riscv_tracer_sv_unit 0 22 L=CJ:5d6UMAUeKQ_G^<542 +Z72 DXx4 work 20 riscv_tracer_defines 0 22 XA^8nJdS>;X:[L]lDJEPI1 +DXx4 work 20 riscv_tracer_sv_unit 0 22 Kmn09;X:[L]lDJEPI1 +VXA^8nJdS>;X:[L]lDJEPI1 S1 R0 R7 @@ -1464,20 +1464,20 @@ Xriscv_tracer_sv_unit R1 R2 R3 -R78 -VL=CJ:5d6UMAUeKQ_G^<542 +R72 +VKmn09id^3 I7DXOjERo;_gich4XgGg^n1 @@ -1497,7 +1497,7 @@ R5 !s105 riscv_wrapper_sv_unit S1 R0 -w1576161302 +Z75 w1577137251 8riscv_wrapper.sv Friscv_wrapper.sv R21 @@ -1514,7 +1514,7 @@ R15 R16 vtb_top R1 -R18 +R17 !i10b 1 !s100 :0ED7=AgejD7?>@:mn9g3k8af0 @@ -1522,7 +1522,7 @@ R5 !s105 tb_top_sv_unit S1 R0 -w1574160278 +R75 8tb_top.sv Ftb_top.sv L0 16 @@ -1538,8 +1538,8 @@ R14 R15 R16 Ttb_top_vopt -!s110 1576749548 -VO2afVk9lQg6H6=0K4Fe>;3 +!s110 1577137871 +VBO6D5KJV`ZeJJX>PokG563 04 6 4 work tb_top fast 0 o-work work -debugdb -fsmdebug -pedanticerrors +acc R16 diff --git a/tb/core/work/_lib.qdb b/tb/core/work/_lib.qdb index 3b2e083..83cddde 100644 Binary files a/tb/core/work/_lib.qdb and b/tb/core/work/_lib.qdb differ diff --git a/tb/core/work/_lib1_6.qdb b/tb/core/work/_lib1_1.qdb similarity index 82% rename from tb/core/work/_lib1_6.qdb rename to tb/core/work/_lib1_1.qdb index cc1293e..e3bf749 100644 Binary files a/tb/core/work/_lib1_6.qdb and b/tb/core/work/_lib1_1.qdb differ diff --git a/tb/core/work/_lib1_6.qpg b/tb/core/work/_lib1_1.qpg similarity index 84% rename from tb/core/work/_lib1_6.qpg rename to tb/core/work/_lib1_1.qpg index f3a3fe1..c10d7cd 100644 Binary files a/tb/core/work/_lib1_6.qpg and b/tb/core/work/_lib1_1.qpg differ diff --git a/tb/core/work/_lib1_1.qtl b/tb/core/work/_lib1_1.qtl new file mode 100644 index 0000000..c6ac559 Binary files /dev/null and b/tb/core/work/_lib1_1.qtl differ diff --git a/tb/core/work/_lib1_6.qtl b/tb/core/work/_lib1_6.qtl deleted file mode 100644 index 3b71303..0000000 Binary files a/tb/core/work/_lib1_6.qtl and /dev/null differ diff --git a/tb/core/work/tb_top_vopt/_dpi/dpi.tfdb b/tb/core/work/tb_top_vopt/_dpi/dpi.tfdb index 9415416..3ad2b7a 100644 --- a/tb/core/work/tb_top_vopt/_dpi/dpi.tfdb +++ b/tb/core/work/tb_top_vopt/_dpi/dpi.tfdb @@ -17,7 +17,7 @@ TYPEDEF_BEGIN 0 TYPEDEF_END TF_BEGIN 2 0 139 -0 -1 -1 0 1 1 0 0x0 1 0 12 0 4294967295 4 278571 32 0 31 31 0 32 0x1 0 1 0x0 1 0 10 0 4294967295 8 262153 22 32641 21 21 0 22 0x1 1 1 2 72 +0 -1 -1 0 1 1 0 0x0 1 0 12 0 4294967295 4 278571 32 0 31 31 0 32 0x1 0 1 0x0 1 0 10 0 4294967295 8 262153 22 32644 21 21 0 22 0x1 1 1 2 72 3 253 3 -1 -1 1 3 1 0 0x0 1 0 0 0 1 4 0 0 0 2147483648 2147483647 2147483648 0 0x1 0 1 0x0 1 0 10 0 4294967295 8 278539 32 0 31 31 0 32 0x1 1 0 4 0x0 1 0 10 0 4294967295 2 262153 8 0 7 7 0 8 0x1 1 0 5 0x0 1 0 10 0 4294967295 2 262153 8 0 7 7 0 8 0x1 2 1 2 76 TF_END diff --git a/tb/core/work/tb_top_vopt/_lib.qdb b/tb/core/work/tb_top_vopt/_lib.qdb index 50af9cb..552f6e4 100644 Binary files a/tb/core/work/tb_top_vopt/_lib.qdb and b/tb/core/work/tb_top_vopt/_lib.qdb differ diff --git a/tb/core/work/tb_top_vopt/_lib1_0.qdb b/tb/core/work/tb_top_vopt/_lib1_0.qdb index 7c26db3..53036bf 100644 Binary files a/tb/core/work/tb_top_vopt/_lib1_0.qdb and b/tb/core/work/tb_top_vopt/_lib1_0.qdb differ diff --git a/tb/core/work/tb_top_vopt/_lib1_0.qpg b/tb/core/work/tb_top_vopt/_lib1_0.qpg index 66e6981..8d70324 100644 Binary files a/tb/core/work/tb_top_vopt/_lib1_0.qpg and b/tb/core/work/tb_top_vopt/_lib1_0.qpg differ diff --git a/tb/core/work/tb_top_vopt/_lib1_0.qtl b/tb/core/work/tb_top_vopt/_lib1_0.qtl index 7cba809..a13f9f4 100644 Binary files a/tb/core/work/tb_top_vopt/_lib1_0.qtl and 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a/tb/core/work/tb_top_vopt/_lib7_0.qtl and /dev/null differ diff --git a/tb/tb_riscv/riscv_random_interrupt_generator.sv b/tb/tb_riscv/riscv_random_interrupt_generator.sv index 10e5dd5..b8ec14d 100644 --- a/tb/tb_riscv/riscv_random_interrupt_generator.sv +++ b/tb/tb_riscv/riscv_random_interrupt_generator.sv @@ -70,6 +70,7 @@ logic irq_ack_monitor; logic irq_sd; logic [31:0] irq_sd_lines; logic ack_flag; +logic irq_sd_lines_changed; // struct 18bit irq_lines @@ -81,7 +82,7 @@ typedef struct packed { logic irq_nmi; } Interrupts_t; -Interrupts_t irq_lines_q, irq_lines_n, irq_lines_mask; +Interrupts_t irq_lines_q, irq_lines_n; Interrupts_t irq_rnd_lines; @@ -108,39 +109,7 @@ begin // random irq word id stored and updated every time // an interrupt is taken by the core - if (irq_ack_i) begin - case (irq_id_i) - NMI_IRQ_ID: irq_lines_mask.irq_nmi = 1'b1; - FAST14_IRQ_ID: irq_lines_mask.irq_fast[14] = 1'b1; - FAST13_IRQ_ID: irq_lines_mask.irq_fast[13] = 1'b1; - FAST12_IRQ_ID: irq_lines_mask.irq_fast[12] = 1'b1; - FAST11_IRQ_ID: irq_lines_mask.irq_fast[11] = 1'b1; - FAST10_IRQ_ID: irq_lines_mask.irq_fast[10] = 1'b1; - FAST9_IRQ_ID: irq_lines_mask.irq_fast[9] = 1'b1; - FAST8_IRQ_ID: irq_lines_mask.irq_fast[8] = 1'b1; - FAST7_IRQ_ID: irq_lines_mask.irq_fast[7] = 1'b1; - FAST6_IRQ_ID: irq_lines_mask.irq_fast[6] = 1'b1; - FAST5_IRQ_ID: irq_lines_mask.irq_fast[5] = 1'b1; - FAST4_IRQ_ID: irq_lines_mask.irq_fast[4] = 1'b1; - FAST3_IRQ_ID: irq_lines_mask.irq_fast[3] = 1'b1; - FAST2_IRQ_ID: irq_lines_mask.irq_fast[2] = 1'b1; - FAST1_IRQ_ID: irq_lines_mask.irq_fast[1] = 1'b1; - FAST0_IRQ_ID: irq_lines_mask.irq_fast[0] = 1'b1; - EXTERNAL_IRQ_ID: irq_lines_mask.irq_external = 1'b1; - SOFTWARE_IRQ_ID: irq_lines_mask.irq_timer = 1'b1; - TIMER_IRQ_ID: irq_lines_mask.irq_software = 1'b1; - default : /* default */; - endcase - end else begin - irq_lines_mask = '0; - end - - if (irq_random) begin - irq_lines_n = irq_rnd_lines; - end else begin - irq_lines_n = irq_lines_q & (~irq_lines_mask); - end - + irq_lines_n = irq_rnd_lines; end PC_TRIG: @@ -195,10 +164,6 @@ begin n >= min_irq_cycles; n <= max_irq_cycles; }; - while(wait_cycles.n != 0) begin - @(posedge clk_i); - wait_cycles.n--; - end irq_rnd_lines = value.n; irq_random = 1'b1; @@ -207,12 +172,24 @@ begin irq_random = 1'b0; //we don't care about the ack in this mode - for(i=0; i