From b72d00de9bd2d5a947a50e18e2945b832488b471 Mon Sep 17 00:00:00 2001 From: mmrahorovic Date: Sun, 3 Dec 2023 22:56:02 +0000 Subject: [PATCH] [stitched-ip]: minor fixes to creating valid stitched-ip with ap_clk2x interface --- .../fpgadataflow/create_stitched_ip.py | 46 ++++++++++++------- 1 file changed, 30 insertions(+), 16 deletions(-) diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py index 63f98e6156..f797e3d841 100644 --- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py +++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py @@ -110,32 +110,41 @@ def __init__(self, fpgapart, clk_ns, ip_name="finn_design", vitis=False, signatu "axilite": [], } + def _is_double_pumped(self, node): + try: + pumped_compute = getCustomOp(node).get_nodeattr("pumpedCompute") + return pumped_compute==1 + except: + return False + def connect_clk_rst(self, node): inst_name = node.name node_inst = getCustomOp(node) clock_intf_name = node_inst.get_verilog_top_module_intf_names()["clk"][0] - clock2x_intf_name = node_inst.get_verilog_top_module_intf_names()["clk2x"][0] + if self._is_double_pumped(node): + clock2x_intf_name = node_inst.get_verilog_top_module_intf_names()["clk2x"][0] reset_intf_name = node_inst.get_verilog_top_module_intf_names()["rst"][0] # make clock and reset external, if they aren't already if not self.clock_reset_are_external: self.connect_cmds.append( "make_bd_pins_external [get_bd_pins %s/%s]" % (inst_name, clock_intf_name) ) - self.connect_cmds.append( - "make_bd_pins_external [get_bd_pins %s/%s]" % (inst_name, clock2x_intf_name) - ) self.connect_cmds.append("set_property name ap_clk [get_bd_ports ap_clk_0]") - self.connect_cmds.append("set_property name ap_clk2x [get_bd_ports ap_clk2x_0]") self.connect_cmds.append( "make_bd_pins_external [get_bd_pins %s/%s]" % (inst_name, reset_intf_name) ) self.connect_cmds.append("set_property name ap_rst_n [get_bd_ports ap_rst_n_0]") self.clock_reset_are_external = True self.intf_names["clk"] = ["ap_clk"] - self.intf_names["clk2x"] = ["ap_clk2x"] self.intf_names["rst"] = ["ap_rst_n"] - # otherwise connect clock and reset - else: + # make clk2x external, if it isn't already and connect clk and reset + elif self._is_double_pumped(node) and not self.clock2x_is_external: + self.connect_cmds.append( + "make_bd_pins_external [get_bd_pins %s/%s]" % (inst_name, clock2x_intf_name) + ) + self.connect_cmds.append("set_property name ap_clk2x [get_bd_ports ap_clk2x_0]") + self.clock2x_is_external = True + self.intf_names["clk2x"] = ["ap_clk2x"] self.connect_cmds.append( "connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins %s/%s]" % (inst_name, reset_intf_name) @@ -144,10 +153,21 @@ def connect_clk_rst(self, node): "connect_bd_net [get_bd_ports ap_clk] [get_bd_pins %s/%s]" % (inst_name, clock_intf_name) ) + # otherwise connect clock and reset + else: self.connect_cmds.append( - "connect_bd_net [get_bd_ports ap_clk2x] [get_bd_pins %s/%s]" - % (inst_name, clock2x_intf_name) + "connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins %s/%s]" + % (inst_name, reset_intf_name) ) + self.connect_cmds.append( + "connect_bd_net [get_bd_ports ap_clk] [get_bd_pins %s/%s]" + % (inst_name, clock_intf_name) + ) + if self._is_double_pumped(node): + self.connect_cmds.append( + "connect_bd_net [get_bd_ports ap_clk2x] [get_bd_pins %s/%s]" + % (inst_name, clock2x_intf_name) + ) def connect_axi(self, node): inst_name = node.name @@ -388,12 +408,6 @@ def apply(self, model): model.set_metadata_prop("clk_ns", str(self.clk_ns)) tcl.append("set_property CONFIG.FREQ_HZ %d [get_bd_ports /ap_clk]" % round(fclk_hz)) tcl.append("set_property CONFIG.FREQ_HZ %d [get_bd_ports /ap_clk2x]" % round(2*fclk_hz)) - # tcl.append( - # "set_property CONFIG.FREQ_HZ %d [get_bd_intf_pins MatrixVectorActivation_rtl_0/s_axilite_0]" % round(fclk_hz) - # ) - # tcl.append( - # "set_property CONFIG.FREQ_HZ %d [get_bd_intf_pins MatrixVectorActivation_rtl_0/in0_V]" % round(fclk_hz) - # ) tcl.append("validate_bd_design") tcl.append("save_bd_design") # create wrapper hdl (for rtlsim later on)