diff --git a/ucf/AC701/Bus.IIC.xdc b/ucf/AC701/Bus.IIC.xdc new file mode 100644 index 00000000..309c4ca4 --- /dev/null +++ b/ucf/AC701/Bus.IIC.xdc @@ -0,0 +1,53 @@ +## +## I2C-MainBus +## ----------------------------------------------------------------------------- +## Bank: 14 +## VCCO: 3.3V (FPGA_3V3) +## Location: U52 (PCA9548ARGER) +## Vendor: Texas Instruments +## Device: PCA9548A-RGER - 8-Channel I2C Switch with Reset +## I2C-Address: 0x74 (0111 010xb) +## ----------------------------------------------------------------------------- +## Devices: 8 +## Channel 0: Programmable UserClock +## Location: U34 +## Vendor: Silicon Labs +## Device: Si570 +## Address: 0xBA (1011 101xb) +## Channel 1: FMC Connector 1 (HPC) +## Location: +## Channel 2: unused +## Channel 3: EEPROM +## Location: U6 +## Vendor: +## Device: M24C08 +## Address: 0xA8 (1010 100xb) +## Channel 4: SFP cage +## Location: P3 +## Address: 0xA0 (1010 000xb) +## Channel 5: HDMI +## Location: +## Vendor: +## Device: +## Address: 0x72 (0111 001xb) +## Channel 6: DDR3 +## Location: +## Address: 0xA0, 0x30 (1010 000xb, 0011 000xb) +## Channel 7: SI5324 +## Location: U?? (SI5324-C-GM) +## Vendor: Silicon Labs +## Device: SI5324 - Any-Frequency Precision Clock Multiplier/Jitter Attenuator +## Address: 0xD0 (1101 000xb) +## ----------------------------------------------------------------------------- +## {INOUT} U52 - Pin 19 - SerialClock +set_property PACKAGE_PIN N18 [get_ports AC701_IIC_SerialClock] +## {INOUT} U52 - Pin 20 - SerialData +set_property PACKAGE_PIN K25 [get_ports AC701_IIC_SerialData] +## {OUT} #$ U52 - Pin 24 - Reset (low-active) +set_property PACKAGE_PIN R17 [get_ports AC701_IIC_Switch_Reset_n] +# set I/O standard +set_property IOSTANDARD LVCMOS33 [get_ports -regexp {AC701_IIC_.*}] + +# Ignore timings on async I/O pins +set_false_path -to [get_ports -regexp {AC701_IIC_.*}] +set_false_path -from [get_ports -regexp {AC701_IIC_Serial.*}] diff --git a/ucf/AC701/Clock.SystemClock.xdc b/ucf/AC701/Clock.SystemClock.xdc new file mode 100644 index 00000000..5df92b5d --- /dev/null +++ b/ucf/AC701/Clock.SystemClock.xdc @@ -0,0 +1,30 @@ +## ============================================================================================================================================================= +## Xilinx User Constraint File (UCF) +## ============================================================================================================================================================= +## Board: Xilinx - Artix-7 AC701 +## FPGA: Xilinx Artix-7 +## Device: XC7A200T +## Package: FBG676 +## Speedgrade: -2 +## +## Notes: +## AC701: VCCO_VADJ is defaulted to 2.5V (choices: 1.8V, 2.5V, 3.3V) +## +## ============================================================================================================================================================= +## Clock Sources +## ============================================================================================================================================================= +## +## System Clock +## ----------------------------------------------------------------------------- +## Bank: 34 +## VCCO: 2.5V (FPGA_2V5) +## Location: U51 (SIT9102) +## Vendor: SiTime +## Device: SIT9102AI-243N25E200.0000 - 1 to 220 MHz High Performance Oscillator +## Frequency: 200 MHz, 50ppm +set_property PACKAGE_PIN R3 [get_ports AC701_SystemClock_200MHz_p] +set_property PACKAGE_PIN P3 [get_ports AC701_SystemClock_200MHz_n] +# set I/O standard +set_property IOSTANDARD LVDS_25 [get_ports -regexp {AC701_SystemClock_200MHz_[p|n]}] +# specify a 200 MHz clock +create_clock -period 5.000 -name PIN_SystemClock_200MHz [get_ports AC701_SystemClock_200MHz_p] diff --git a/ucf/AC701/FanControl.xdc b/ucf/AC701/FanControl.xdc new file mode 100644 index 00000000..89ffbced --- /dev/null +++ b/ucf/AC701/FanControl.xdc @@ -0,0 +1,19 @@ +## ============================================================================================================================================================= +## General Purpose I/O +## ============================================================================================================================================================= +## +## Fan Control +## ----------------------------------------------------------------------------- +## Bank: 15 +## VCCO: 2.5V (VCC0_VADJ) +## Location: J61, Q17 (NDT3055L) +## ----------------------------------------------------------------------------- +## {OUT} Q17.Gate; external 1k pullup resistor; Q17.Drain connects to J61.1 (GND) +set_property PACKAGE_PIN J26 [get_ports AC701_FanControl_PWM] +## {IN} J61.3; voltage limited by D15 (MM3Z2V7B; 2.7V zener-diode) +set_property PACKAGE_PIN J25 [get_ports AC701_FanControl_Tacho] +# set I/O standard +set_property IOSTANDARD LVCMOS25 [get_ports -regexp {AC701_FanControl_.*}] +# Ignore timings on async I/O pins +set_false_path -to [get_ports AC701_FanControl_PWM] +set_false_path -from [get_ports AC701_FanControl_Tacho] diff --git a/ucf/AC701/GPIO.Button.Special.xdc b/ucf/AC701/GPIO.Button.Special.xdc new file mode 100644 index 00000000..320e56c2 --- /dev/null +++ b/ucf/AC701/GPIO.Button.Special.xdc @@ -0,0 +1,16 @@ +## ============================================================================================================================================================= +## General Purpose I/O +## ============================================================================================================================================================= +## +## Special Buttons +## ----------------------------------------------------------------------------- +## Bank: 34 +## VCCO: 1.5V (FPGA_1V5) +## Location: SW8 +## ----------------------------------------------------------------------------- +## {IN} SW8; high-active; external 4k7 pulldown resistor +set_property PACKAGE_PIN U4 [get_ports AC701_GPIO_Button_CPU_Reset] +# set I/O standard +set_property IOSTANDARD LVCMOS15 [get_ports AC701_GPIO_Button_CPU_Reset] +# Ignore timings on async I/O pins +set_false_path -from [get_ports AC701_GPIO_Button_CPU_Reset] diff --git a/ucf/AC701/GPIO.LED.xdc b/ucf/AC701/GPIO.LED.xdc new file mode 100644 index 00000000..5f5cbcc7 --- /dev/null +++ b/ucf/AC701/GPIO.LED.xdc @@ -0,0 +1,23 @@ +## ============================================================================================================================================================= +## General Purpose I/O +## ============================================================================================================================================================= +## +## LEDs +## ----------------------------------------------------------------------------- +## Bank: 14 +## VCCO: 3.3V (FPGA_3V3) +## Location: DS2, DS3, DS4, DS5 +## ----------------------------------------------------------------------------- +## {OUT} DS2; +set_property PACKAGE_PIN M26 [get_ports AC701_GPIO_LED[0]] +## {OUT} DS3; +set_property PACKAGE_PIN T24 [get_ports AC701_GPIO_LED[1]] +## {OUT} DS4; +set_property PACKAGE_PIN T25 [get_ports AC701_GPIO_LED[2]] +## {OUT} DS5; +set_property PACKAGE_PIN R26 [get_ports AC701_GPIO_LED[3]] +# set I/O standard +set_property IOSTANDARD LVCMOS33 [get_ports -regexp {AC701_GPIO_LED\[[0-3]]}] + +# Ignore timings on async I/O pins +set_false_path -to [get_ports -regexp {AC701_GPIO_LED\[\d\]}] diff --git a/ucf/AC701/USB_UART.xdc b/ucf/AC701/USB_UART.xdc new file mode 100644 index 00000000..2b6b4063 --- /dev/null +++ b/ucf/AC701/USB_UART.xdc @@ -0,0 +1,25 @@ +## +## USB UART +## ----------------------------------------------------------------------------- +## Bank: 13 +## VCCO: 1.8V (FPGA_1V8) +## Location: U44 +## Vendor: Silicon Labs +## Device: CP2103-GM +## Baud-Rate: 300 Bd - 1 MBd +## Note: USB-UART is the master, FPGA is the slave => so TX is an input and RX an output +## {IN} U44.25 {OUT} +set_property PACKAGE_PIN T19 [get_ports AC701_USB_UART_TX] +## {OUT} U44.24 {IN} +set_property PACKAGE_PIN U19 [get_ports AC701_USB_UART_RX] +## {IN} U44.23 {OUT} Ready to Transmit (USB-UART has new data) +set_property PACKAGE_PIN V19 [get_ports AC701_USB_UART_RTS_n] +## {OUT} U44.22 {IN} Clear to Send (FPGA is able to receive data) +set_property PACKAGE_PIN W19 [get_ports AC701_USB_UART_CTS_n] +# set I/O standard +set_property IOSTANDARD LVCMOS25 [get_ports -regexp {AC701_USB_UART_.*}] +# Ignore timings on async I/O pins +set_false_path -from [get_ports AC701_USB_UART_TX] +set_false_path -to [get_ports AC701_USB_UART_RX] +set_false_path -from [get_ports AC701_USB_UART_RTS_n] +set_false_path -to [get_ports AC701_USB_UART_CTS_n]