Clock.UserClock.ucf

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## Xilinx User Constraint File (UCF)
## =============================================================================================================================================================
##	Board:					Xilinx - Virtex 6 ML605
##	FPGA:						Xilinx Virtex 6
##		Device:				XC6VLX240T
##		Package:			FF1156
##		Speedgrade:		-1
## =============================================================================================================================================================
## Clock Sources
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##
## User Clock
## =============================================================================
##		Bank:						24
##			VCCO:					2.5V (VCC2V5)
##		Location:				X5 single-ended clock socket
##		Oscillator:			66 MHz
##			Vendor:				MMD Components
##			Device:				MBH2100H-66.000 MHz
##			Frequency:		66 MHz, 100ppm
NET "ML605_UserClock"								LOC = "U23";						## {IN}			U11.5
NET "ML605_UserClock"								IOSTANDARD = LVCMOS25;
##
NET "ML605_UserClock"								TNM_NET = "TGRP_UserClock";
TIMESPEC "TS_UserClock"	= PERIOD "TGRP_UserClock"		66 MHz	HIGH 40 %;