-
Notifications
You must be signed in to change notification settings - Fork 95
/
Copy pathEthernetPHY.GMII.ucf
42 lines (42 loc) · 2.76 KB
/
EthernetPHY.GMII.ucf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
##
## single-ended, parallel TX path
NET "ML505_EthernetPHY_TX_Valid" LOC = "AJ10"; ## {OUT} U16.16; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_Error" LOC = "AJ9"; ## {OUT} U16.13; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<0>" LOC = "AF11"; ## {OUT} U16.18; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<1>" LOC = "AE11"; ## {OUT} U16.19; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<2>" LOC = "AH9"; ## {OUT} U16.20; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<3>" LOC = "AH10"; ## {OUT} U16.24; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<4>" LOC = "AG8"; ## {OUT} U16.25; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<5>" LOC = "AH8"; ## {OUT} U16.26; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<6>" LOC = "AG10"; ## {OUT} U16.28; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_DATA<7>" LOC = "AG11"; ## {OUT} U16.29; Bank 22; DCI using 49.9 ohm resistor
NET "ML505_EthernetPHY_TX_*" IOSTANDARD = LVCMOS25;
NET "ML505_EthernetPHY_TX_*" SLEW = FAST;
##
## single-ended, parallel RX path
NET "ML505_EthernetPHY_RX_Valid" LOC = "E32"; ## {IN} U16.4; Bank 11
NET "ML505_EthernetPHY_RX_Error" LOC = "E33"; ## {IN} U16.8; Bank 11
NET "ML505_EthernetPHY_RX_DATA<0>" LOC = "A33"; ## {IN} U16.3; Bank 11
NET "ML505_EthernetPHY_RX_DATA<1>" LOC = "B33"; ## {IN} U16.128; Bank 11
NET "ML505_EthernetPHY_RX_DATA<2>" LOC = "C33"; ## {IN} U16.126; Bank 11
NET "ML505_EthernetPHY_RX_DATA<3>" LOC = "C32"; ## {IN} U16.125; Bank 11
NET "ML505_EthernetPHY_RX_DATA<4>" LOC = "D32"; ## {IN} U16.124; Bank 11
NET "ML505_EthernetPHY_RX_DATA<5>" LOC = "C34"; ## {IN} U16.123; Bank 11
NET "ML505_EthernetPHY_RX_DATA<6>" LOC = "D34"; ## {IN} U16.121; Bank 11
NET "ML505_EthernetPHY_RX_DATA<7>" LOC = "F33"; ## {IN} U16.120; Bank 11
NET "ML505_EthernetPHY_RX_*" IOSTANDARD = LVCMOS25;
NET "ML505_EthernetPHY_RX_*" SLEW = FAST;
##
## Timing names
NET "ML505_EthernetPHY_RX_Clock" TNM_NET = "TGRP_EthernetPHY_RX_Clock";
NET "ML505_EthernetPHY_RX_Data[?]" TNM = "EthernetPHY_RX";
NET "ML505_EthernetPHY_RX_Valid" TNM = "EthernetPHY_RX";
NET "ML505_EthernetPHY_RX_Error" TNM = "EthernetPHY_RX";
##
## RX clock frequency
TIMESPEC "TS_EthernetPHY_RX_Clock" = PERIOD "TGRP_EthernetPHY_RX_Clock" 125 MHz HIGH 50%;
##
## according to IEEE 802.3 clause 35.4.2.3:
## t_SETUP(RCVR) = 2.0 ns
## t_HOLD(RCVR) = 0.0 ns
TIMEGRP "EthernetPHY_RX" OFFSET = IN 2.0 VALID 2.0 ns BEFORE "ML505_EthernetPHY_RX_Clock" RISING;