From d12ff8847fa15c947e30fb6be1181aaeaa4b7d3d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mika=C3=ABl=20BRIDAY?= Date: Wed, 28 Feb 2024 16:18:16 +0100 Subject: [PATCH] [FPU] update cortexM0/M3 for tpl_load_context prototype --- machines/cortex-m/armv6m/tpl_ctx_switch.S | 42 +++++++------------ .../cortex-m/armv6m/tpl_ctx_switch_under_it.S | 21 ++++------ machines/cortex-m/armv6m/tpl_regs_offsets.h | 17 ++++++++ machines/cortex-m/armv7m/tpl_ctx_switch.S | 22 +++------- .../cortex-m/armv7m/tpl_ctx_switch_under_it.S | 21 ++++------ machines/cortex-m/armv7m/tpl_regs_offsets.h | 17 ++++++++ 6 files changed, 72 insertions(+), 68 deletions(-) create mode 100644 machines/cortex-m/armv6m/tpl_regs_offsets.h create mode 100644 machines/cortex-m/armv7m/tpl_regs_offsets.h diff --git a/machines/cortex-m/armv6m/tpl_ctx_switch.S b/machines/cortex-m/armv6m/tpl_ctx_switch.S index 2545d4b62..47447f732 100644 --- a/machines/cortex-m/armv6m/tpl_ctx_switch.S +++ b/machines/cortex-m/armv6m/tpl_ctx_switch.S @@ -18,10 +18,6 @@ * * @section infos File informations * - * $Date$ - * $Rev$ - * $Author$ - * $URL$ */ .syntax unified @@ -60,43 +56,32 @@ * The second part is stored in a structure defined in tpl_machine_cortex.h * * with a pointer from the static task descriptor * * +------------------+ * - * | R4 | <- CTX_GPR4 * + * | R4 | <- CTX_GPR4 (0) * * +------------------+ * - * | R5 | <- CTX_GPR5 * + * | R5 | <- CTX_GPR5 (4) * * +------------------+ * - * | R6 | <- CTX_GPR6 * + * | R6 | <- CTX_GPR6 (8) * * +------------------+ * - * | R7 | <- CTX_GPR7 * + * | R7 | <- CTX_GPR7 (12) * * +------------------+ * - * | R8 | <- CTX_GPR8 * + * | R8 | <- CTX_GPR8 (16) * * +------------------+ * - * | R9 | <- CTX_GPR9 * + * | R9 | <- CTX_GPR9 (20) * * +------------------+ * - * | R10 | <- CTX_GPR10 * + * | R10 | <- CTX_GPR10 (24) * * +------------------+ * - * | R11 | <- CTX_GPR11 * + * | R11 | <- CTX_GPR11 (28) * * +------------------+ * - * | PSP (R13) | <- CTX_PSP * + * | PSP (R13) | <- CTX_PSP (32) * * +------------------+ * *----------------------------------------------------------------------------* */ - #define CTX_GPR4 0 - #define CTX_GPR5 4 - #define CTX_GPR6 8 - #define CTX_GPR7 12 - #define CTX_GPR8 16 - #define CTX_GPR9 20 - #define CTX_GPR10 24 - #define CTX_GPR11 28 - #define CTX_PSP 32 - - #define INT_CONTEXT 0 - #define FLOAT_CONTEXT 4 +#include "tpl_regs_offsets.h" /*============================================================================= * tpl_save_context is used to save the context of the running task. - * It is used from the system call handler and from interrupt handlers. + * It is used from the system call handler. * * r0 contains a pointer to the static descriptor of the running task. * r1-r3 are working registers @@ -159,6 +144,9 @@ tpl_save_context: * * r0 contains a pointer to the static descriptor of the running task. * r1-r3 are working registers + * + * ** it SHOULD return LR in r0 ** + * * values to be loaded into r4 and r5 are put in the MSP. */ @@ -210,6 +198,8 @@ tpl_load_context: ldr r2,[r1,#CTX_PSP] msr psp,r2 + /* set LR value in return argument (r0) */ + ldr r0, =0xFFFFFFFD bx lr #define OS_STOP_SEC_CODE diff --git a/machines/cortex-m/armv6m/tpl_ctx_switch_under_it.S b/machines/cortex-m/armv6m/tpl_ctx_switch_under_it.S index b8531e9d6..90b08c0ed 100644 --- a/machines/cortex-m/armv6m/tpl_ctx_switch_under_it.S +++ b/machines/cortex-m/armv6m/tpl_ctx_switch_under_it.S @@ -81,18 +81,7 @@ *----------------------------------------------------------------------------* */ -#define CTX_GPR4 0 -#define CTX_GPR5 4 -#define CTX_GPR6 8 -#define CTX_GPR7 12 -#define CTX_GPR8 16 -#define CTX_GPR9 20 -#define CTX_GPR10 24 -#define CTX_GPR11 28 -#define CTX_PSP 32 - -#define INT_CONTEXT 0 -#define FLOAT_CONTEXT 4 +#include "tpl_regs_offsets.h" /*============================================================================= * tpl_save_context_under_it is used to save the context of the running task. @@ -100,6 +89,7 @@ * * r0 contains a pointer to the static descriptor of the running task. * r1-r3 are working registers + * */ .global tpl_save_context_under_it @@ -149,6 +139,9 @@ tpl_save_context_under_it: * * r0 contains a pointer to the static descriptor of the running task. * r1-r3 are working registers + * + * ** it SHOULD return LR final value in r0 ** + * LR should be 0xFFFFFFFD, as the context does not use any FPU */ .global tpl_load_context_under_it @@ -188,7 +181,9 @@ tpl_load_context_under_it: ldr r2,[r1,#CTX_PSP] msr psp,r2 - bx lr + ldr r0, =0xFFFFFFFD + + bx lr #define OS_STOP_SEC_CODE #include "tpl_as_memmap.h" diff --git a/machines/cortex-m/armv6m/tpl_regs_offsets.h b/machines/cortex-m/armv6m/tpl_regs_offsets.h new file mode 100644 index 000000000..f57d442cb --- /dev/null +++ b/machines/cortex-m/armv6m/tpl_regs_offsets.h @@ -0,0 +1,17 @@ +#ifndef __TPL_REGS_OFFSETS_H__ +#define __TPL_REGS_OFFSETS_H__ + +#define CTX_GPR4 0 +#define CTX_GPR5 4 +#define CTX_GPR6 8 +#define CTX_GPR7 12 +#define CTX_GPR8 16 +#define CTX_GPR9 20 +#define CTX_GPR10 24 +#define CTX_GPR11 28 +#define CTX_PSP 32 + +#define INT_CONTEXT 0 +#define FLOAT_CONTEXT 4 + +#endif \ No newline at end of file diff --git a/machines/cortex-m/armv7m/tpl_ctx_switch.S b/machines/cortex-m/armv7m/tpl_ctx_switch.S index ee3b7d61c..3dcac5e4c 100644 --- a/machines/cortex-m/armv7m/tpl_ctx_switch.S +++ b/machines/cortex-m/armv7m/tpl_ctx_switch.S @@ -18,10 +18,6 @@ * * @section infos File informations * - * $Date$ - * $Rev$ - * $Author$ - * $URL$ */ .syntax unified @@ -81,18 +77,7 @@ *----------------------------------------------------------------------------* */ -#define CTX_GPR4 0 -#define CTX_GPR5 4 -#define CTX_GPR6 8 -#define CTX_GPR7 12 -#define CTX_GPR8 16 -#define CTX_GPR9 20 -#define CTX_GPR10 24 -#define CTX_GPR11 28 -#define CTX_PSP 32 - -#define INT_CONTEXT 0 -#define FLOAT_CONTEXT 4 +#include "tpl_regs_offsets.h" /*============================================================================= * tpl_save_context is used to save the context of the running task. @@ -151,6 +136,9 @@ tpl_save_context: * * r0 contains a pointer to the static descriptor of the running task. * r1-r3 are working registers + * + * ** it SHOULD return LR in r0 ** + * * values to be loaded into r4 and r5 are put in the MSP. */ @@ -194,6 +182,8 @@ tpl_load_context: ldr r2,[r1,#CTX_PSP] msr psp,r2 + /* set LR value in return argument (r0) */ + ldr r0, =0xFFFFFFFD bx lr #define OS_STOP_SEC_CODE diff --git a/machines/cortex-m/armv7m/tpl_ctx_switch_under_it.S b/machines/cortex-m/armv7m/tpl_ctx_switch_under_it.S index 0ad428beb..0be039abf 100644 --- a/machines/cortex-m/armv7m/tpl_ctx_switch_under_it.S +++ b/machines/cortex-m/armv7m/tpl_ctx_switch_under_it.S @@ -81,18 +81,7 @@ *----------------------------------------------------------------------------* */ -#define CTX_GPR4 0 -#define CTX_GPR5 4 -#define CTX_GPR6 8 -#define CTX_GPR7 12 -#define CTX_GPR8 16 -#define CTX_GPR9 20 -#define CTX_GPR10 24 -#define CTX_GPR11 28 -#define CTX_PSP 32 - -#define INT_CONTEXT 0 -#define FLOAT_CONTEXT 4 +#include "tpl_regs_offsets.h" /*============================================================================= * tpl_save_context_under_it is used to save the context of the running task. @@ -100,6 +89,7 @@ * * r0 contains a pointer to the static descriptor of the running task. * r1-r3 are working registers + * */ .global tpl_save_context_under_it @@ -140,6 +130,9 @@ tpl_save_context_under_it: * * r0 contains a pointer to the static descriptor of the running task. * r1-r3 are working registers + * + * ** it SHOULD return LR final value in r0 ** + * LR should be 0xFFFFFFFD, as the context does not use any FPU */ .global tpl_load_context_under_it @@ -170,7 +163,9 @@ tpl_load_context_under_it: ldr r2,[r1,#CTX_PSP] msr psp,r2 - bx lr + ldr r0, =0xFFFFFFFD + + bx lr #define OS_STOP_SEC_CODE #include "tpl_as_memmap.h" diff --git a/machines/cortex-m/armv7m/tpl_regs_offsets.h b/machines/cortex-m/armv7m/tpl_regs_offsets.h new file mode 100644 index 000000000..f57d442cb --- /dev/null +++ b/machines/cortex-m/armv7m/tpl_regs_offsets.h @@ -0,0 +1,17 @@ +#ifndef __TPL_REGS_OFFSETS_H__ +#define __TPL_REGS_OFFSETS_H__ + +#define CTX_GPR4 0 +#define CTX_GPR5 4 +#define CTX_GPR6 8 +#define CTX_GPR7 12 +#define CTX_GPR8 16 +#define CTX_GPR9 20 +#define CTX_GPR10 24 +#define CTX_GPR11 28 +#define CTX_PSP 32 + +#define INT_CONTEXT 0 +#define FLOAT_CONTEXT 4 + +#endif \ No newline at end of file