From 9a38149e184f4e108039083f4c6a11a4ac02c57d Mon Sep 17 00:00:00 2001 From: Pat Deegan Date: Fri, 26 Apr 2024 20:13:45 -0400 Subject: [PATCH] The great renamming: ASIC_ON_BOARD replaced by more clearer ASIC_RP_CONTROL --- src/config.ini | 11 +++++------ src/main.py | 4 ++-- src/test.py | 2 +- src/ttboard/boot/firstboot_operations.py | 2 +- src/ttboard/boot/post.py | 4 ++-- src/ttboard/config/user_config.py | 6 +++--- src/ttboard/demoboard.py | 4 ++-- src/ttboard/mode.py | 12 ++++++------ src/ttboard/pins/pins.py | 8 ++++---- src/ttboard/util/shuttle_tests.py | 4 ++-- 10 files changed, 28 insertions(+), 29 deletions(-) diff --git a/src/config.ini b/src/config.ini index 7bbb082..56ab9cd 100644 --- a/src/config.ini +++ b/src/config.ini @@ -20,10 +20,9 @@ start_in_reset = no # mode can be any of # - SAFE: all RP2040 pins inputs -# - ASIC_ON_BOARD: TT inputs,nrst and clock driven, outputs monitored +# - ASIC_RP_CONTROL: TT inputs,nrst and clock driven, outputs monitored # - ASIC_MANUAL_INPUTS: basically same as safe, but intent is clear -# - STANDALONE: *no* TT ASIC on-board, testing mode, outputs driven, inputs monitored -mode = ASIC_ON_BOARD +mode = ASIC_RP_CONTROL # log_level can be one of # - DEBUG @@ -50,7 +49,7 @@ input_byte = 1 clock_frequency = 4000 # clock config 4k, disp single bits input_byte = 0b11001000 -mode = ASIC_ON_BOARD +mode = ASIC_RP_CONTROL @@ -70,7 +69,7 @@ bidir_byte = 0b110010101 [tt_um_vga_clock] rp_clock_frequency = 126e6 clock_frequency = 31.5e6 -mode = ASIC_ON_BOARD +mode = ASIC_RP_CONTROL [tt_um_urish_simon] @@ -79,7 +78,7 @@ mode = ASIC_MANUAL_INPUTS [tt_um_algofoogle_solo_squash] -mode = ASIC_ON_BOARD +mode = ASIC_RP_CONTROL # start inactive (all ins 0) input_byte = 0 diff --git a/src/main.py b/src/main.py index 6838a84..ce44ee5 100644 --- a/src/main.py +++ b/src/main.py @@ -39,8 +39,8 @@ def startup(): # construct DemoBoard - # either pass an appropriate RPMode, e.g. RPMode.ASIC_ON_BOARD - # or have "mode = ASIC_ON_BOARD" in ini DEFAULT section + # either pass an appropriate RPMode, e.g. RPMode.ASIC_RP_CONTROL + # or have "mode = ASIC_RP_CONTROL" in ini DEFAULT section ttdemoboard = DemoBoard() diff --git a/src/test.py b/src/test.py index 2b8884c..9514348 100644 --- a/src/test.py +++ b/src/test.py @@ -10,7 +10,7 @@ import time from ttboard.demoboard import DemoBoard, RPMode -tt = DemoBoard(RPMode.ASIC_ON_BOARD) +tt = DemoBoard(RPMode.ASIC_RP_CONTROL) def test_design_tnt_counter(): tt.shuttle.tt_um_test.enable() diff --git a/src/ttboard/boot/firstboot_operations.py b/src/ttboard/boot/firstboot_operations.py index eca220f..cef491e 100644 --- a/src/ttboard/boot/firstboot_operations.py +++ b/src/ttboard/boot/firstboot_operations.py @@ -104,7 +104,7 @@ def say_hello(delay_interval_ms:int=100, times:int=1): hello_values = [0x74, 0x79, 0x30, 0x30, 0x5c, 0, 0x50, 0x10, 0x78, 0x77] tt = get_demoboard() tt.shuttle.tt_um_test.enable() - tt.mode = RPMode.ASIC_ON_BOARD # make sure we're controlling everything + tt.mode = RPMode.ASIC_RP_CONTROL # make sure we're controlling everything tt.in0(0) # want this low tt.clock_project_PWM(1e3) # clock it real good diff --git a/src/ttboard/boot/post.py b/src/ttboard/boot/post.py index 14036ae..603d9ad 100644 --- a/src/ttboard/boot/post.py +++ b/src/ttboard/boot/post.py @@ -104,11 +104,11 @@ def test_bidirs(self) -> bool: # select the project from the shuttle update_delay_ms = 2 auto_clock_freq = 1e3 - self.tt.mode = RPMode.ASIC_ON_BOARD # make sure we're controlling everything + self.tt.mode = RPMode.ASIC_RP_CONTROL # make sure we're controlling everything self.tt.shuttle.tt_um_test.enable() curMode = self.tt.mode - self.tt.mode = RPMode.ASIC_ON_BOARD # make sure we're controlling everything + self.tt.mode = RPMode.ASIC_RP_CONTROL # make sure we're controlling everything self.tt.reset_project(False) self.tt.in0(0) # want this low self.tt.clock_project_PWM(auto_clock_freq) # clock it real good diff --git a/src/ttboard/config/user_config.py b/src/ttboard/config/user_config.py index df55fb0..8a766fe 100644 --- a/src/ttboard/config/user_config.py +++ b/src/ttboard/config/user_config.py @@ -21,7 +21,7 @@ class UserProjectConfig: clock_frequency = 4000 # clock config 4k, disp single bits input_byte = 0b11001000 - mode = ASIC_ON_BOARD + mode = ASIC_RP_CONTROL You can use this to set: - mode (str) @@ -98,9 +98,9 @@ class UserConfig(ConfigFile): # mode can be any of # - SAFE: all RP2040 pins inputs - # - ASIC_ON_BOARD: TT inputs,nrst and clock driven, outputs monitored + # - ASIC_RP_CONTROL: TT inputs,nrst and clock driven, outputs monitored # - ASIC_MANUAL_INPUTS: basically same as safe, but intent is clear - mode = ASIC_ON_BOARD + mode = ASIC_RP_CONTROL # log_level can be one of # - DEBUG diff --git a/src/ttboard/demoboard.py b/src/ttboard/demoboard.py index 26a47e6..7c71f17 100644 --- a/src/ttboard/demoboard.py +++ b/src/ttboard/demoboard.py @@ -74,7 +74,7 @@ def __init__(self, * RPMode.SAFE, the default, which has every pin as an INPUT, no pulls - * RPMode.ASIC_ON_BOARD, for use with ASICs, where it watches the OUTn + * RPMode.ASIC_RP_CONTROL, for use with ASICs, where it watches the OUTn (configured as inputs) and can drive the INn and tickle the ASIC inputs (configured as outputs) @@ -248,7 +248,7 @@ def apply_user_config(self, design:Design): log.debug(f'Design "{design.name}" loaded, apply user conf') applyWhenInModeMap = { - RPMode.ASIC_ON_BOARD: True, + RPMode.ASIC_RP_CONTROL: True, RPMode.ASIC_MANUAL_INPUTS: True } if not self.apply_configs: diff --git a/src/ttboard/mode.py b/src/ttboard/mode.py index 8397bca..8e46386 100644 --- a/src/ttboard/mode.py +++ b/src/ttboard/mode.py @@ -6,14 +6,14 @@ ''' class ModeBase: SAFE = 0 - ASIC_ON_BOARD = 1 + ASIC_RP_CONTROL = 1 ASIC_MANUAL_INPUTS = 2 @classmethod def modemap(cls): modeMap = { 'SAFE': cls.SAFE, - 'ASIC_ON_BOARD': cls.ASIC_ON_BOARD, + 'ASIC_RP_CONTROL': cls.ASIC_RP_CONTROL, 'ASIC_MANUAL_INPUTS': cls.ASIC_MANUAL_INPUTS } return modeMap @@ -34,7 +34,7 @@ def from_string(cls, s:str): def namemap(cls): nameMap = { cls.SAFE: 'SAFE', - cls.ASIC_ON_BOARD: 'ASIC_ON_BOARD', + cls.ASIC_RP_CONTROL: 'ASIC_RP_CONTROL', cls.ASIC_MANUAL_INPUTS: 'ASIC_MANUAL_INPUTS', } return nameMap @@ -52,7 +52,7 @@ class RPMode(ModeBase): RPMode.MODE notation and code completion where MODE is one of: SAFE - ASIC_ON_BOARD + ASIC_RP_CONTROL ASIC_MANUAL_INPUTS ''' pass @@ -70,7 +70,7 @@ class RPModeDEVELOPMENT(ModeBase): def modemap(cls): modeMap = { 'SAFE': cls.SAFE, - 'ASIC_ON_BOARD': cls.ASIC_ON_BOARD, + 'ASIC_RP_CONTROL': cls.ASIC_RP_CONTROL, 'ASIC_MANUAL_INPUTS': cls.ASIC_MANUAL_INPUTS, 'STANDALONE': cls.STANDALONE } @@ -80,7 +80,7 @@ def modemap(cls): def namemap(cls): nameMap = { cls.SAFE: 'SAFE', - cls.ASIC_ON_BOARD: 'ASIC_ON_BOARD', + cls.ASIC_RP_CONTROL: 'ASIC_RP_CONTROL', cls.ASIC_MANUAL_INPUTS: 'ASIC_MANUAL_INPUTS', cls.STANDALONE: 'STANDALONE' } diff --git a/src/ttboard/pins/pins.py b/src/ttboard/pins/pins.py index 604a227..ba57f84 100644 --- a/src/ttboard/pins/pins.py +++ b/src/ttboard/pins/pins.py @@ -13,7 +13,7 @@ TLDR 1) get pins - p = Pins(RPMode.ASIC_ON_BOARD) # monitor/control ASIC + p = Pins(RPMode.ASIC_RP_CONTROL) # monitor/control ASIC 2) play with pins print(p.out2()) # read @@ -106,7 +106,7 @@ class Pins: So this class has 3 modes of pin init at startup: * RPMode.SAFE, the default, which has every pin as an INPUT, no pulls - * RPMode.ASIC_ON_BOARD, for use with ASICs, where it watches the OUTn + * RPMode.ASIC_RP_CONTROL, for use with ASICs, where it watches the OUTn (configured as inputs) and can drive the INn and tickle the ASIC inputs (configured as outputs) * RPMode.STANDALONE: where OUTn is an OUTPUT, INn is an input, useful @@ -157,7 +157,7 @@ def mode(self): def mode(self, setTo:int): startupMap = { RPModeDEVELOPMENT.STANDALONE: self.begin_standalone, - RPMode.ASIC_ON_BOARD: self.begin_asiconboard, + RPMode.ASIC_RP_CONTROL: self.begin_asiconboard, RPMode.ASIC_MANUAL_INPUTS: self.begin_asic_manual_inputs, RPMode.SAFE: self.begin_safe } @@ -292,7 +292,7 @@ def begin_safe(self): def begin_asiconboard(self): - log.debug('begin: ASIC_ON_BOARD') + log.debug('begin: ASIC_RP_CONTROL') self.begin_inputs_all() self._begin_alwaysOut() unconfigured_pins = [] diff --git a/src/ttboard/util/shuttle_tests.py b/src/ttboard/util/shuttle_tests.py index c1ea830..3d419ad 100644 --- a/src/ttboard/util/shuttle_tests.py +++ b/src/ttboard/util/shuttle_tests.py @@ -27,7 +27,7 @@ def factory_test_bidirs(tt:DemoBoard, max_idx:int=255, delay_interval_ms:int=1): auto_clock_freq = 1e3 tt.shuttle.tt_um_test.enable() curMode = tt.mode - tt.mode = RPMode.ASIC_ON_BOARD # make sure we're controlling everything + tt.mode = RPMode.ASIC_RP_CONTROL # make sure we're controlling everything tt.in0(0) # want this low tt.clock_project_PWM(auto_clock_freq) # clock it real good @@ -75,7 +75,7 @@ def factory_test_clocking(tt:DemoBoard, max_idx:int=30, delay_interval_ms:int=50 # select the project from the shuttle tt.shuttle.tt_um_test.enable() - tt.mode = RPMode.ASIC_ON_BOARD # make sure we're controlling everything + tt.mode = RPMode.ASIC_RP_CONTROL # make sure we're controlling everything tt.reset_project(True)