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This improves on my previous [tt06-grab-bag](https://github.com/algofoogle/tt06-grab-bag) -- my 1st analog ASIC project, [included](https://tinytapeout.com/runs/tt06/tt_um_algofoogle_tt06_grab_bag) on [TT06](https://tinytapeout.com/runs/tt06/), using 3 RDAC instances instead. + +With these current steering DACs, I'm hoping for an improved slew rate (estimated to be about 60-80nS; still below the target of 40nS, but better than the TT06 version which was estimated to be about 240nS). + +![](./tt08-gds-doco2.png) + +Note that the analog R/G/B outputs (`ua[1:3]`) are expected to be in the range 0.9-1.8V, and high impedance, while VGA requires a 0.0-0.7V range and 75Ω impedance. Thus, external opamps will be required. + + +## How it works + +There is a digital control block which can be [controlled by the state of the `ui_in` pins](https://github.com/algofoogle/journal/blob/master/0215-2024-08-21.md#explanation-of-digital-block-control-inputs) at reset. It has various test modes, and a pass-through mode. + +Here are some of the test patterns it can produce, but note that the image probably won't be this clear because of: (a) poor matching; and (b) slew simulated to be worse than 40nS will lead to a little bit of horizontal smearing: + +![](./tt08-patterns.png) + +The digital control block internally drives 3 (RGB) colour channels, each of which has 8 positive and 8 negative polarity bits. This complementary polarity is required for switching the binary-weighted current steering transistors either one way or the other, maintaining an equal (estimated) current of 500µA per channel. Each channel's internal current sum is then converted to a voltage with a pull-up resistor that is about 2.3kΩ. + +Additionally the first analog output pin (`ua[0]`) is the internal `VbiasR` of the red channel DAC (gate voltage for current mirroring); this is for testing, but could possibly also be pulled up or down a little to see what effect it has on the red channel's output. + + +## How to test + +TBC. + +## External hardware + +Probably an op-amp on each analog output, plus a VGA connector. + +TBC. diff --git a/projects/tt_um_algofoogle_tt08_vga_fun/docs/tt08-gds-doco2.png b/projects/tt_um_algofoogle_tt08_vga_fun/docs/tt08-gds-doco2.png new file mode 100644 index 0000000..2ddb026 Binary files /dev/null and b/projects/tt_um_algofoogle_tt08_vga_fun/docs/tt08-gds-doco2.png differ diff --git a/projects/tt_um_algofoogle_tt08_vga_fun/docs/tt08-patterns.png b/projects/tt_um_algofoogle_tt08_vga_fun/docs/tt08-patterns.png new file mode 100644 index 0000000..ea7143d Binary files /dev/null and b/projects/tt_um_algofoogle_tt08_vga_fun/docs/tt08-patterns.png differ diff --git a/projects/tt_um_algofoogle_tt08_vga_fun/info.yaml b/projects/tt_um_algofoogle_tt08_vga_fun/info.yaml new file mode 100644 index 0000000..4d9b6cd --- /dev/null +++ b/projects/tt_um_algofoogle_tt08_vga_fun/info.yaml @@ -0,0 +1,66 @@ +# Tiny Tapeout project information +project: + title: "TT08 VGA FUN!" + author: "algofoogle (Anton Maurovic)" + discord: "algofoogle" + description: "Rough 24-bit VGA DAC tests with digital control block" + language: "Analog" + clock_hz: 25_000_000 + + # How many tiles your design occupies? A single tile is about 167x108 uM. + tiles: "1x2" # Valid values for analog projects: 1x2, 2x2 + + # How many analog pins does your project use? + analog_pins: 4 # Valid values: 0 to 6 + uses_3v3: true # Set to true if your project uses 3.3V (VAPWR) in addition to 1.8V (VDPWR) + + # Your top module name must start with "tt_um_". Make it unique by including your github username: + top_module: "tt_um_algofoogle_tt08_vga_fun" + + # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line: + source_files: + - "project.v" + +# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. +pinout: + # Inputs + ui[0]: "mode[0] / dac_in[0]" + ui[1]: "mode[1] / dac_in[1]" + ui[2]: "mode[2] / dac_in[2]" + ui[3]: "mode[3] / dac_in[3]" + ui[4]: "mode[4] / dac_in[4]" + ui[5]: "mode[5] / dac_in[5]" + ui[6]: "mode[6] / dac_in[6]" + ui[7]: "mode[7] / dac_in[7]" + + # Outputs + # These are compatible with the RGB222 Tiny VGA PMOD (https://github.com/mole99/tiny-vga) + uo[0]: "r7" + uo[1]: "g7" + uo[2]: "b7" + uo[3]: "vsync" + uo[4]: "r6" + uo[5]: "g6" + uo[6]: "b6" + uo[7]: "hsync" + + # Bidirectional pins + uio[0]: "vblank_out" + uio[1]: "hblank_out" + uio[2]: "" + uio[3]: "" + uio[4]: "" + uio[5]: "" + uio[6]: "" + uio[7]: "" + + # Analog pins - make sure to also set "analog_pins" above, else the pins won't be connected + ua[0]: "VbiasR" + ua[1]: "r" + ua[2]: "g" + ua[3]: "b" + ua[4]: "" + ua[5]: "" + +# Do not change! +yaml_version: 6 diff --git a/projects/tt_um_algofoogle_tt08_vga_fun/tt_um_algofoogle_tt08_vga_fun.gds b/projects/tt_um_algofoogle_tt08_vga_fun/tt_um_algofoogle_tt08_vga_fun.gds new file mode 100644 index 0000000..cdf339e Binary files /dev/null and b/projects/tt_um_algofoogle_tt08_vga_fun/tt_um_algofoogle_tt08_vga_fun.gds differ diff --git a/projects/tt_um_algofoogle_tt08_vga_fun/tt_um_algofoogle_tt08_vga_fun.lef b/projects/tt_um_algofoogle_tt08_vga_fun/tt_um_algofoogle_tt08_vga_fun.lef new file mode 100644 index 0000000..183cf98 --- /dev/null +++ b/projects/tt_um_algofoogle_tt08_vga_fun/tt_um_algofoogle_tt08_vga_fun.lef @@ -0,0 +1,564 @@ +VERSION 5.7 ; + NOWIREEXTENSIONATPIN ON ; + DIVIDERCHAR "/" ; + BUSBITCHARS "[]" ; +MACRO tt_um_algofoogle_tt08_vga_fun + CLASS BLOCK ; + FOREIGN tt_um_algofoogle_tt08_vga_fun ; + ORIGIN 0.000 0.000 ; + SIZE 145.360 BY 225.760 ; + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.852000 ; + PORT + LAYER met4 ; + RECT 128.190 224.760 128.490 225.760 ; + END + END clk + PIN ena + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 130.950 224.760 131.250 225.760 ; + END + END ena + PIN rst_n + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.213000 ; + PORT + LAYER met4 ; + RECT 125.430 224.760 125.730 225.760 ; + END + END rst_n + PIN ua[0] + DIRECTION INOUT ; + USE SIGNAL ; + ANTENNAGATEAREA 21.769999 ; + ANTENNADIFFAREA 0.290000 ; + PORT + LAYER met4 ; + RECT 136.170 0.000 137.070 1.000 ; + END + END ua[0] + PIN ua[1] + DIRECTION INOUT ; + USE SIGNAL ; + ANTENNADIFFAREA 2.465000 ; + PORT + LAYER met4 ; + RECT 116.850 0.000 117.750 1.000 ; + END + END ua[1] + PIN ua[2] + DIRECTION INOUT ; + USE SIGNAL ; + ANTENNADIFFAREA 2.465000 ; + PORT + LAYER met4 ; + RECT 97.530 0.000 98.430 1.000 ; + END + END ua[2] + PIN ua[3] + DIRECTION INOUT ; + USE SIGNAL ; + ANTENNADIFFAREA 2.465000 ; + PORT + LAYER met4 ; + RECT 78.210 0.000 79.110 1.000 ; + END + END ua[3] + PIN ua[4] + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 58.890 0.000 59.790 1.000 ; + END + END ua[4] + PIN ua[5] + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 39.570 0.000 40.470 1.000 ; + END + END ua[5] + PIN ua[6] + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 20.250 0.000 21.150 1.000 ; + END + END ua[6] + PIN ua[7] + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 0.930 0.000 1.830 1.000 ; + END + END ua[7] + PIN ui_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.213000 ; + PORT + LAYER met4 ; + RECT 122.670 224.760 122.970 225.760 ; + END + END ui_in[0] + PIN ui_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.213000 ; + PORT + LAYER met4 ; + RECT 119.910 224.760 120.210 225.760 ; + END + END ui_in[1] + PIN ui_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.213000 ; + PORT + LAYER met4 ; + RECT 117.150 224.760 117.450 225.760 ; + END + END ui_in[2] + PIN ui_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.126000 ; + PORT + LAYER met4 ; + RECT 114.390 224.760 114.690 225.760 ; + END + END ui_in[3] + PIN ui_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.213000 ; + PORT + LAYER met4 ; + RECT 111.630 224.760 111.930 225.760 ; + END + END ui_in[4] + PIN ui_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.213000 ; + PORT + LAYER met4 ; + RECT 108.870 224.760 109.170 225.760 ; + END + END ui_in[5] + PIN ui_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.213000 ; + PORT + LAYER met4 ; + RECT 106.110 224.760 106.410 225.760 ; + END + END ui_in[6] + PIN ui_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.213000 ; + PORT + LAYER met4 ; + RECT 103.350 224.760 103.650 225.760 ; + END + END ui_in[7] + PIN uio_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 100.590 224.760 100.890 225.760 ; + END + END uio_in[0] + PIN uio_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 97.830 224.760 98.130 225.760 ; + END + END uio_in[1] + PIN uio_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 95.070 224.760 95.370 225.760 ; + END + END uio_in[2] + PIN uio_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 92.310 224.760 92.610 225.760 ; + END + END uio_in[3] + PIN uio_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 89.550 224.760 89.850 225.760 ; + END + END uio_in[4] + PIN uio_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 86.790 224.760 87.090 225.760 ; + END + END uio_in[5] + PIN uio_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 84.030 224.760 84.330 225.760 ; + END + END uio_in[6] + PIN uio_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 81.270 224.760 81.570 225.760 ; + END + END uio_in[7] + PIN uio_oe[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 336.264496 ; + ANTENNADIFFAREA 951.944153 ; + PORT + LAYER met4 ; + RECT 34.350 224.760 34.650 225.760 ; + END + END uio_oe[0] + PIN uio_oe[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 336.264496 ; + ANTENNADIFFAREA 951.944153 ; + PORT + LAYER met4 ; + RECT 31.590 224.760 31.890 225.760 ; + END + END uio_oe[1] + PIN uio_oe[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 28.830 224.760 29.130 225.760 ; + END + END uio_oe[2] + PIN uio_oe[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 26.070 224.760 26.370 225.760 ; + END + END uio_oe[3] + PIN uio_oe[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 23.310 224.760 23.610 225.760 ; + END + END uio_oe[4] + PIN uio_oe[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 20.550 224.760 20.850 225.760 ; + END + END uio_oe[5] + PIN uio_oe[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 17.790 224.760 18.090 225.760 ; + END + END uio_oe[6] + PIN uio_oe[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 15.030 224.760 15.330 225.760 ; + END + END uio_oe[7] + PIN uio_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 56.430 224.760 56.730 225.760 ; + END + END uio_out[0] + PIN uio_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 53.670 224.760 53.970 225.760 ; + END + END uio_out[1] + PIN uio_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 50.910 224.760 51.210 225.760 ; + END + END uio_out[2] + PIN uio_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 48.150 224.760 48.450 225.760 ; + END + END uio_out[3] + PIN uio_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 45.390 224.760 45.690 225.760 ; + END + END uio_out[4] + PIN uio_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 42.630 224.760 42.930 225.760 ; + END + END uio_out[5] + PIN uio_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 39.870 224.760 40.170 225.760 ; + END + END uio_out[6] + PIN uio_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 532.134277 ; + ANTENNADIFFAREA 866.461060 ; + PORT + LAYER met4 ; + RECT 37.110 224.760 37.410 225.760 ; + END + END uio_out[7] + PIN uo_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 78.510 224.760 78.810 225.760 ; + END + END uo_out[0] + PIN uo_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 75.750 224.760 76.050 225.760 ; + END + END uo_out[1] + PIN uo_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 72.990 224.760 73.290 225.760 ; + END + END uo_out[2] + PIN uo_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 70.230 224.760 70.530 225.760 ; + END + END uo_out[3] + PIN uo_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 67.470 224.760 67.770 225.760 ; + END + END uo_out[4] + PIN uo_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 64.710 224.760 65.010 225.760 ; + END + END uo_out[5] + PIN uo_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 61.950 224.760 62.250 225.760 ; + END + END uo_out[6] + PIN uo_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 59.190 224.760 59.490 225.760 ; + END + END uo_out[7] + PIN VDPWR + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 134.800 5.000 137.800 220.760 ; + END + END VDPWR + PIN VGND + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 138.800 5.000 141.800 220.760 ; + END + END VGND + PIN VAPWR + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 142.800 5.000 144.800 220.760 ; + END + END VAPWR + OBS + LAYER li1 ; + RECT 8.080 8.650 130.000 212.465 ; + LAYER met1 ; + RECT 8.600 8.550 130.610 214.040 ; + LAYER met2 ; + RECT 8.600 8.315 130.580 224.500 ; + LAYER met3 ; + RECT 5.350 8.370 141.800 224.500 ; + LAYER met4 ; + RECT 3.400 224.360 14.630 225.050 ; + RECT 15.730 224.360 17.390 225.050 ; + RECT 18.490 224.360 20.150 225.050 ; + RECT 21.250 224.360 22.910 225.050 ; + RECT 24.010 224.360 25.670 225.050 ; + RECT 26.770 224.360 28.430 225.050 ; + RECT 29.530 224.360 31.190 225.050 ; + RECT 32.290 224.360 33.950 225.050 ; + RECT 35.050 224.360 36.710 225.050 ; + RECT 37.810 224.360 39.470 225.050 ; + RECT 40.570 224.360 42.230 225.050 ; + RECT 43.330 224.360 44.990 225.050 ; + RECT 46.090 224.360 47.750 225.050 ; + RECT 48.850 224.360 50.510 225.050 ; + RECT 51.610 224.360 53.270 225.050 ; + RECT 54.370 224.360 56.030 225.050 ; + RECT 57.130 224.360 58.790 225.050 ; + RECT 59.890 224.360 61.550 225.050 ; + RECT 62.650 224.360 64.310 225.050 ; + RECT 65.410 224.360 67.070 225.050 ; + RECT 68.170 224.360 69.830 225.050 ; + RECT 70.930 224.360 72.590 225.050 ; + RECT 73.690 224.360 75.350 225.050 ; + RECT 76.450 224.360 78.110 225.050 ; + RECT 79.210 224.360 80.870 225.050 ; + RECT 81.970 224.360 83.630 225.050 ; + RECT 84.730 224.360 86.390 225.050 ; + RECT 87.490 224.360 89.150 225.050 ; + RECT 90.250 224.360 91.910 225.050 ; + RECT 93.010 224.360 94.670 225.050 ; + RECT 95.770 224.360 97.430 225.050 ; + RECT 98.530 224.360 100.190 225.050 ; + RECT 101.290 224.360 102.950 225.050 ; + RECT 104.050 224.360 105.710 225.050 ; + RECT 106.810 224.360 108.470 225.050 ; + RECT 109.570 224.360 111.230 225.050 ; + RECT 112.330 224.360 113.990 225.050 ; + RECT 115.090 224.360 116.750 225.050 ; + RECT 117.850 224.360 119.510 225.050 ; + RECT 120.610 224.360 122.270 225.050 ; + RECT 123.370 224.360 125.030 225.050 ; + RECT 126.130 224.360 127.790 225.050 ; + RECT 128.890 224.360 130.550 225.050 ; + RECT 131.650 224.360 141.800 225.050 ; + RECT 3.400 221.160 141.800 224.360 ; + RECT 3.400 4.600 134.400 221.160 ; + RECT 138.200 4.600 138.400 221.160 ; + RECT 3.400 1.400 141.800 4.600 ; + RECT 3.400 1.000 19.850 1.400 ; + RECT 21.550 1.000 39.170 1.400 ; + RECT 40.870 1.000 58.490 1.400 ; + RECT 60.190 1.000 77.810 1.400 ; + RECT 79.510 1.000 97.130 1.400 ; + RECT 98.830 1.000 116.450 1.400 ; + RECT 118.150 1.000 135.770 1.400 ; + RECT 137.470 1.000 141.800 1.400 ; + END +END tt_um_algofoogle_tt08_vga_fun +END LIBRARY + diff --git a/projects/tt_um_algofoogle_tt08_vga_fun/tt_um_algofoogle_tt08_vga_fun.v b/projects/tt_um_algofoogle_tt08_vga_fun/tt_um_algofoogle_tt08_vga_fun.v new file mode 100644 index 0000000..113c2e8 --- /dev/null +++ b/projects/tt_um_algofoogle_tt08_vga_fun/tt_um_algofoogle_tt08_vga_fun.v @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2024 Anton Maurovic + * SPDX-License-Identifier: Apache-2.0 + */ + +`default_nettype none + +module tt_um_algofoogle_tt08_vga_fun ( + input wire VGND, + input wire VDPWR, // 1.8v power supply + input wire VAPWR, // 3.3v power supply + input wire [7:0] ui_in, // Dedicated inputs + output wire [7:0] uo_out, // Dedicated outputs + input wire [7:0] uio_in, // IOs: Input path + output wire [7:0] uio_out, // IOs: Output path + output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) + inout wire [7:0] ua, // Analog pins, only ua[5:0] can be used + input wire ena, // always 1 when the design is powered, so you can ignore it + input wire clk, // clock + input wire rst_n // reset_n - low to reset +); + + // WARNING: Netget doesn't seem to like a pattern of: + // wire [7:0] r, rn; + // as it incorrectly interprets only `r` as a bus, and `rn` as a single wire. + wire [7:0] r; + wire [7:0] g; + wire [7:0] b; + wire [7:0] rn; + wire [7:0] gn; + wire [7:0] bn; + + controller controller_0 ( + .VPWR (VDPWR), + .VGND (VGND), + .clk (clk), + .rst_n (rst_n), + .ui_in (ui_in), + .vblank (uio_out[0]), + .hblank (uio_out[1]), + .r (r), + .g (g), + .b (b), + .rn (rn), + .gn (gn), + .bn (bn), + .r7 (uo_out[0]), + .g7 (uo_out[1]), + .b7 (uo_out[2]), + .vsync (uo_out[3]), + .r6 (uo_out[4]), + .g6 (uo_out[5]), + .b6 (uo_out[6]), + .hsync (uo_out[7]) + ); + + csdac_nom R_dac ( + .vcc (VDPWR), + .vss (VGND), + .p0 (r[0]), + .n0 (rn[0]), + .p1 (r[1]), + .n1 (rn[1]), + .p2 (r[2]), + .n2 (rn[2]), + .p3 (r[3]), + .n3 (rn[3]), + .p4 (r[4]), + .n4 (rn[4]), + .p5 (r[5]), + .n5 (rn[5]), + .p6 (r[6]), + .n6 (rn[6]), + .p7 (r[7]), + .n7 (rn[7]), + .Vbias (ua[0]), + .Vneg (ua[1]) + // .Vpos (ua[2]) + ); + + csdac_nom G_dac ( + .vcc (VDPWR), + .vss (VGND), + .p0 (g[0]), + .n0 (gn[0]), + .p1 (g[1]), + .n1 (gn[1]), + .p2 (g[2]), + .n2 (gn[2]), + .p3 (g[3]), + .n3 (gn[3]), + .p4 (g[4]), + .n4 (gn[4]), + .p5 (g[5]), + .n5 (gn[5]), + .p6 (g[6]), + .n6 (gn[6]), + .p7 (g[7]), + .n7 (gn[7]), + .Vneg (ua[2]) + // .Vbias (ua[1]), + // .Vpos (ua[2]) + ); + + csdac_nom B_dac ( + .vcc (VDPWR), + .vss (VGND), + .p0 (b[0]), + .n0 (bn[0]), + .p1 (b[1]), + .n1 (bn[1]), + .p2 (b[2]), + .n2 (bn[2]), + .p3 (b[3]), + .n3 (bn[3]), + .p4 (b[4]), + .n4 (bn[4]), + .p5 (b[5]), + .n5 (bn[5]), + .p6 (b[6]), + .n6 (bn[6]), + .p7 (b[7]), + .n7 (bn[7]), + .Vneg (ua[3]) + // .Vbias (ua[1]), + // .Vpos (ua[2]) + ); + + // Configure uio directions... + //NOTE: Using power ports instead of constants, + // because the design is not synthesized, + // but rather laid out by hand: + assign uio_oe[0] = VDPWR; // Output: vblank + assign uio_oe[1] = VDPWR; // Output: hblank + assign uio_oe[2] = VGND; // Input: UNUSED + assign uio_oe[3] = VGND; // Input: UNUSED + assign uio_oe[4] = VGND; // Input: UNUSED + assign uio_oe[5] = VGND; // Input: UNUSED + assign uio_oe[6] = VGND; // Input: UNUSED + assign uio_oe[7] = VGND; // Input: UNUSED + + // Tie unused digital outputs, so they don't float: + // assign uio_out[0] = hblank; + // assign uio_out[1] = vblank; + assign uio_out[2] = VGND; + assign uio_out[3] = VGND; + assign uio_out[4] = VGND; + assign uio_out[5] = VGND; + assign uio_out[6] = VGND; + assign uio_out[7] = VGND; + +endmodule