diff --git a/projects/tt_um_dvxf_dj8v_dac/docs/info.md b/projects/tt_um_dvxf_dj8v_dac/docs/info.md
index 2aa9682..270428d 100644
--- a/projects/tt_um_dvxf_dj8v_dac/docs/info.md
+++ b/projects/tt_um_dvxf_dj8v_dac/docs/info.md
@@ -15,6 +15,12 @@ DJ8 is a 8-bit CPU featuring:
 * 15-bit address bus
 * 8-bit data bus
 * 8-bit DAC based on [Tiny Tapeout Analog R2R DAC](https://github.com/mattvenn/tt06-analog-r2r-dac)
+* Built-in 256-bytes demo ROM with 2 demos
+
+Other implementations:
+
+- [TT06 DJ8 8-bit CPU - VHDL](https://github.com/dvxf/tt06-dj8)
+- [TTIHP0P2 DJ8 8-bit CPU (no DAC) - Verilog](https://github.com/dvxf/ttiph0p2-dj8v)
 
 ## Memory Map
 
@@ -31,8 +37,110 @@ DJ8 is a 8-bit CPU featuring:
 | 0x2000 | 0x3fff | External RAM (32 bytes)
 | 0x4000 | 0x5fff | External Flash ROM (16KB)
 
+## Registers
+
+There are 8 general purposes 8-bit registers (A,B,C,D,E,F,G,H), two flag registers (CF, ZF), and 16-bit PC.
+
+For memory addressing, 16-bit combined registers EF and GH are used.
+
+At reset time, PC is set to 0x4000. All other registers are set to 0x80.
+
+## Instruction Set
+For future compatibility, please set the don't care bits (`?`) to `0`.
+
+### ALU reg, imm8: Immediate ALU operation
+
+| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
+| 1 | 1 | A | A | A | D | D | D | I | I | I | I | I | I | I | I |
+
+- A : ALU operation
+  - `000`: ADD: reg = reg + imm8
+  - `001`: ADC: reg = reg + imm8 + CF
+  - `010`: SUBC: reg = reg - (imm8 + CF)
+  - `011`: MOVR: reg = reg
+  - `100`: XOR: reg = reg ^ imm8
+  - `101`: OR: reg = reg | imm8
+  - `110`: AND: reg = reg & imm8
+  - `111`: MOVI: reg = imm8
+- D : register
+- I : imm8
+
+### ALU dest, src, A {,shift}: ALU operation with src register & register A
+
+| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
+| 1 | 0 | A | A | A | D | D | D | S | S | S | ? | F | F | 0 | 0 |
+
+- A : ALU operation
+  - `000`: ADD: dest = src + A
+  - `001`: ADC: dest = src + A + CF
+  - `010`: SUBC: dest = src - (A + CF)
+  - `011`: MOVR: dest = src
+  - `100`: XOR: dest = src ^ A
+  - `101`: OR: dest = src | A
+  - `110`: AND: dest = src & A
+  - `111`: MOVI: dest = A
+- D : dest register
+- S : src register
+- F : final shift operation
+  - `00`: No shift
+  - `01`: Shift right logical (shr)
+  - `10`: Shift right arithmetic (sar)
+
+### ALU dest, [mem], A {,shift}: ALU operation with memory & register A
+
+| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
+| 1 | 0 | A | A | A | D | D | D | ? | ? | ? | M | F | F | 1 | 0 |
+
+- A : ALU operation
+  - `000`: ADD: dest = [mem] + A
+  - `001`: ADC: dest = [mem] + A + CF
+  - `010`: SUBC: dest = [mem] - (A + CF)
+  - `011`: MOVR: dest = [mem]
+  - `100`: XOR: dest = [mem] ^ A
+  - `101`: OR: dest = [mem] | A
+  - `110`: AND: dest = [mem] & A
+  - `111`: MOVI: dest = A
+- D : dest register
+- M: memory mode
+  - `0`: [GH]
+  - `1`: [EF]  
+- F : final shift operation
+  - `00`: No shift
+  - `01`: Shift right logical (shr)
+  - `10`: Shift right arithmetic (sar)
+  
+### MOVR [mem], reg: Store content of register in memory
+| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
+| 1 | 0 | 0 | 1 | 1 | D | D | D | ? | ? | ? | M | ? | ? | 0 | 1 |
+
+- D: register
+- M: memory mode
+  - `0`: [GH]
+  - `1`: [EF]
+
+### Jxx imm12: Conditional or unconditional jump to absolute address
+| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
+| 0 | 0 | J |  J | I | I | I | I | I | I | I | I | I | I | I | I |
+
+- J: jmpcode
+    - `01`: Jump if zero (JZ)
+    - `10`: Jump if not zero (JNZ)
+    - `11`: Unconditional jump (JMP)
+- I: imm12
+  - PC = (PC & 0xe000) | (imm12 << 1)
+
+### JMP GH: Unconditional jump to address GH
+| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
+| 0 | 1 | ? |  ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | ? | ? |
+
 ## Pinout
-Due to TT07 IO constraints, pins are shared between *Address bus LSB* and *Data bus OUT*. It means that during memory write instructions, the address space is only 64 bytes.
+Due to TT07 IO constraints, pins are shared between *Address bus LSB* and *Data bus OUT*. It means that during memory write instructions, the address space is only 128 bytes.
 
 | Pins | Standard mode | During memory write execute+writeback cycles
 |--|--|--|
@@ -47,12 +155,6 @@ external logic and use uo[6] for RAM OE# and uo[5] for Flash ROM OE#.
 
 To get a bidirectional data bus (needed for SRAM), uio bus must be connected to ui bus with resistors. To be tested!
 
-## Reset
-
-At reset time, PC is set to 0x4000.
-
-All other registers are set to 0x80.
-
 # How to test
 
 An internal test ROM with two demos is included for easy testing. Just select the corresponding DIP switches at reset time to start the demo (technically, a ***jmp GH*** instruction will be seen on the data bus thanks to the DIP switches values, with GH=0x8080 at reset).