From 7af69ade1aa48742dc78258728ba2f29a6c03d1d Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Mon, 30 Dec 2024 02:33:33 -0800 Subject: [PATCH] [hw,i2c,racl] Add RACL support to I2C Signed-off-by: Robert Schilling --- hw/ip/i2c/data/i2c.hjson | 31 +- hw/ip/i2c/doc/interfaces.md | 15 +- hw/ip/i2c/i2c.core | 4 + hw/ip/i2c/lint/i2c.vbl | 6 + hw/ip/i2c/rtl/i2c.sv | 21 +- hw/ip/i2c/rtl/i2c_reg_top.sv | 316 ++++++++++++------ .../data/autogen/top_darjeeling.gen.hjson | 72 ++++ .../rtl/autogen/top_darjeeling.sv | 3 + .../data/autogen/top_earlgrey.gen.hjson | 216 ++++++++++++ hw/top_earlgrey/rtl/autogen/top_earlgrey.sv | 9 + 10 files changed, 584 insertions(+), 109 deletions(-) create mode 100644 hw/ip/i2c/lint/i2c.vbl diff --git a/hw/ip/i2c/data/i2c.hjson b/hw/ip/i2c/data/i2c.hjson index ce9015c936538..7fa7bd47f60e6 100644 --- a/hw/ip/i2c/data/i2c.hjson +++ b/hw/ip/i2c/data/i2c.hjson @@ -30,7 +30,7 @@ ] clocking: [{clock: "clk_i", reset: "rst_ni"}], bus_interfaces: [ - { protocol: "tlul", direction: "device" } + { protocol: "tlul", direction: "device", racl_support: true } ], // INPUT pins available_inout_list: [ @@ -130,6 +130,35 @@ ''' act: "req" } + { struct: "racl_policy_vec", + type: "uni", + name: "racl_policies", + act: "rcv", + package: "top_racl_pkg", + desc: ''' + Policy vector distributed to the subscribing RACL IPs. + ''' + } + { struct: "logic", + type: "uni", + name: "racl_error", + act: "req", + width : "1", + desc: ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + } + { struct: "racl_error_log", + type: "uni", + name: "racl_error_log", + act: "req", + width: "1" + package: "top_racl_pkg", + desc: ''' + RACL error log information of this module. + ''' + } ] param_list: [ { name: "FifoDepth", diff --git a/hw/ip/i2c/doc/interfaces.md b/hw/ip/i2c/doc/interfaces.md index 546c45c828052..d2770813e3b9f 100644 --- a/hw/ip/i2c/doc/interfaces.md +++ b/hw/ip/i2c/doc/interfaces.md @@ -16,12 +16,15 @@ Referring to the [Comportable guideline for peripheral device functionality](htt ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) -| Port Name | Package::Struct | Type | Act | Width | Description | -|:-------------|:--------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------| -| ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | | -| ram_cfg_rsp | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | 1 | | -| lsio_trigger | logic | uni | req | 1 | Self-clearing status trigger for the DMA. Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. | -| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| Port Name | Package::Struct | Type | Act | Width | Description | +|:---------------|:--------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------| +| ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | | +| ram_cfg_rsp | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | 1 | | +| lsio_trigger | logic | uni | req | 1 | Self-clearing status trigger for the DMA. Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. | +| racl_policies | top_racl_pkg::racl_policy_vec | uni | rcv | 1 | Policy vector distributed to the subscribing RACL IPs. | +| racl_error | logic | uni | req | 1 | RACL error indication signal. If 1, the error log contains valid information. | +| racl_error_log | top_racl_pkg::racl_error_log | uni | req | 1 | RACL error log information of this module. | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Interrupts diff --git a/hw/ip/i2c/i2c.core b/hw/ip/i2c/i2c.core index 4ec62eb5fee07..8e07a3b18fc8e 100644 --- a/hw/ip/i2c/i2c.core +++ b/hw/ip/i2c/i2c.core @@ -13,6 +13,7 @@ filesets: - lowrisc:prim:ram_1p_adv - lowrisc:ip:tlul - lowrisc:ip:i2c_pkg + - lowrisc:systems:top_racl_pkg files: - rtl/i2c_reg_pkg.sv - rtl/i2c_reg_top.sv @@ -48,6 +49,9 @@ filesets: # common waivers - lowrisc:lint:common - lowrisc:lint:comportable + files: + - lint/pwm.vbl + file_type: veribleLintWaiver parameters: SYNTHESIS: diff --git a/hw/ip/i2c/lint/i2c.vbl b/hw/ip/i2c/lint/i2c.vbl new file mode 100644 index 0000000000000..895e01a168e9a --- /dev/null +++ b/hw/ip/i2c/lint/i2c.vbl @@ -0,0 +1,6 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# These lines are too long due to generated code +waive --rule=line-length --location="i2c_reg_top.sv" diff --git a/hw/ip/i2c/rtl/i2c.sv b/hw/ip/i2c/rtl/i2c.sv index e29e126867adf..0d931e9a5ebbd 100644 --- a/hw/ip/i2c/rtl/i2c.sv +++ b/hw/ip/i2c/rtl/i2c.sv @@ -9,8 +9,11 @@ module i2c import i2c_reg_pkg::*; #( - parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, - parameter int unsigned InputDelayCycles = 0 + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter int unsigned InputDelayCycles = 0, + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1, + parameter int unsigned RaclPolicySelVec[23] = '{32{0}}, ) ( input clk_i, input rst_ni, @@ -25,6 +28,11 @@ module i2c input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output logic racl_error_o, + output top_racl_pkg::racl_error_log_t racl_error_log_o, + // Generic IO input cio_scl_i, output logic cio_scl_o, @@ -58,13 +66,20 @@ module i2c logic [NumAlerts-1:0] alert_test, alerts; - i2c_reg_top u_reg ( + i2c_reg_top #( + .EnableRacl(EnableRacl), + .RaclErrorRsp(RaclErrorRsp), + .RaclPolicySelVec(RaclPolicySelVec) + ) u_reg ( .clk_i, .rst_ni, .tl_i, .tl_o, .reg2hw, .hw2reg, + .racl_policies_i, + .racl_error_o, + .racl_error_log_o, // SEC_CM: BUS.INTEGRITY .intg_err_o(alerts[0]) ); diff --git a/hw/ip/i2c/rtl/i2c_reg_top.sv b/hw/ip/i2c/rtl/i2c_reg_top.sv index 4de69b9f4fbeb..7b27de692947d 100644 --- a/hw/ip/i2c/rtl/i2c_reg_top.sv +++ b/hw/ip/i2c/rtl/i2c_reg_top.sv @@ -6,7 +6,12 @@ `include "prim_assert.sv" -module i2c_reg_top ( +module i2c_reg_top + # ( + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1, + parameter int unsigned RaclPolicySelVec[32] = '{32{0}} + ) ( input clk_i, input rst_ni, input tlul_pkg::tl_h2d_t tl_i, @@ -15,6 +20,11 @@ module i2c_reg_top ( output i2c_reg_pkg::i2c_reg2hw_t reg2hw, // Write input i2c_reg_pkg::i2c_hw2reg_t hw2reg, // Read + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output logic racl_error_o, + output top_racl_pkg::racl_error_log_t racl_error_log_o, + // Integrity check errors output logic intg_err_o ); @@ -110,7 +120,8 @@ module i2c_reg_top ( .be_o (reg_be), .busy_i (reg_busy), .rdata_i (reg_rdata), - .error_i (reg_error) + // Translate RACL error to TLUL error if enabled + .error_i (reg_error | (RaclErrorRsp & racl_error_o)) ); // cdc oversampling signals @@ -3385,8 +3396,32 @@ module i2c_reg_top ( logic [31:0] addr_hit; + top_racl_pkg::racl_role_vec_t racl_role_vec; + top_racl_pkg::racl_role_t racl_role; + + logic [31:0] racl_addr_hit_read; + logic [31:0] racl_addr_hit_write; + + if (EnableRacl) begin : gen_racl_role_logic + // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap + assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd); + + prim_onehot_enc #( + .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) ) + ) u_racl_role_encode ( + .in_i ( racl_role ), + .en_i ( 1'b1 ), + .out_o( racl_role_vec ) + ); + end else begin : gen_no_racl_role_logic + assign racl_role = '0; + assign racl_role_vec = '0; + end + always_comb begin addr_hit = '0; + racl_addr_hit_read = '0; + racl_addr_hit_write = '0; addr_hit[ 0] = (reg_addr == I2C_INTR_STATE_OFFSET); addr_hit[ 1] = (reg_addr == I2C_INTR_ENABLE_OFFSET); addr_hit[ 2] = (reg_addr == I2C_INTR_TEST_OFFSET); @@ -3419,49 +3454,130 @@ module i2c_reg_top ( addr_hit[29] = (reg_addr == I2C_HOST_NACK_HANDLER_TIMEOUT_OFFSET); addr_hit[30] = (reg_addr == I2C_CONTROLLER_EVENTS_OFFSET); addr_hit[31] = (reg_addr == I2C_TARGET_EVENTS_OFFSET); + + if (EnableRacl) begin : gen_racl_hit + racl_addr_hit_read [ 0] = addr_hit[ 0] & (|(racl_policies_i[RaclPolicySelVec[ 0]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 0] = addr_hit[ 0] & (|(racl_policies_i[RaclPolicySelVec[ 0]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 1] = addr_hit[ 1] & (|(racl_policies_i[RaclPolicySelVec[ 1]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 1] = addr_hit[ 1] & (|(racl_policies_i[RaclPolicySelVec[ 1]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 2] = addr_hit[ 2] & (|(racl_policies_i[RaclPolicySelVec[ 2]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 2] = addr_hit[ 2] & (|(racl_policies_i[RaclPolicySelVec[ 2]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 3] = addr_hit[ 3] & (|(racl_policies_i[RaclPolicySelVec[ 3]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 3] = addr_hit[ 3] & (|(racl_policies_i[RaclPolicySelVec[ 3]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 4] = addr_hit[ 4] & (|(racl_policies_i[RaclPolicySelVec[ 4]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 4] = addr_hit[ 4] & (|(racl_policies_i[RaclPolicySelVec[ 4]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 5] = addr_hit[ 5] & (|(racl_policies_i[RaclPolicySelVec[ 5]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 5] = addr_hit[ 5] & (|(racl_policies_i[RaclPolicySelVec[ 5]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 6] = addr_hit[ 6] & (|(racl_policies_i[RaclPolicySelVec[ 6]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 6] = addr_hit[ 6] & (|(racl_policies_i[RaclPolicySelVec[ 6]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 7] = addr_hit[ 7] & (|(racl_policies_i[RaclPolicySelVec[ 7]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 7] = addr_hit[ 7] & (|(racl_policies_i[RaclPolicySelVec[ 7]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 8] = addr_hit[ 8] & (|(racl_policies_i[RaclPolicySelVec[ 8]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 8] = addr_hit[ 8] & (|(racl_policies_i[RaclPolicySelVec[ 8]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 9] = addr_hit[ 9] & (|(racl_policies_i[RaclPolicySelVec[ 9]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 9] = addr_hit[ 9] & (|(racl_policies_i[RaclPolicySelVec[ 9]].write_perm & racl_role_vec)); + racl_addr_hit_read [10] = addr_hit[10] & (|(racl_policies_i[RaclPolicySelVec[10]].read_perm & racl_role_vec)); + racl_addr_hit_write[10] = addr_hit[10] & (|(racl_policies_i[RaclPolicySelVec[10]].write_perm & racl_role_vec)); + racl_addr_hit_read [11] = addr_hit[11] & (|(racl_policies_i[RaclPolicySelVec[11]].read_perm & racl_role_vec)); + racl_addr_hit_write[11] = addr_hit[11] & (|(racl_policies_i[RaclPolicySelVec[11]].write_perm & racl_role_vec)); + racl_addr_hit_read [12] = addr_hit[12] & (|(racl_policies_i[RaclPolicySelVec[12]].read_perm & racl_role_vec)); + racl_addr_hit_write[12] = addr_hit[12] & (|(racl_policies_i[RaclPolicySelVec[12]].write_perm & racl_role_vec)); + racl_addr_hit_read [13] = addr_hit[13] & (|(racl_policies_i[RaclPolicySelVec[13]].read_perm & racl_role_vec)); + racl_addr_hit_write[13] = addr_hit[13] & (|(racl_policies_i[RaclPolicySelVec[13]].write_perm & racl_role_vec)); + racl_addr_hit_read [14] = addr_hit[14] & (|(racl_policies_i[RaclPolicySelVec[14]].read_perm & racl_role_vec)); + racl_addr_hit_write[14] = addr_hit[14] & (|(racl_policies_i[RaclPolicySelVec[14]].write_perm & racl_role_vec)); + racl_addr_hit_read [15] = addr_hit[15] & (|(racl_policies_i[RaclPolicySelVec[15]].read_perm & racl_role_vec)); + racl_addr_hit_write[15] = addr_hit[15] & (|(racl_policies_i[RaclPolicySelVec[15]].write_perm & racl_role_vec)); + racl_addr_hit_read [16] = addr_hit[16] & (|(racl_policies_i[RaclPolicySelVec[16]].read_perm & racl_role_vec)); + racl_addr_hit_write[16] = addr_hit[16] & (|(racl_policies_i[RaclPolicySelVec[16]].write_perm & racl_role_vec)); + racl_addr_hit_read [17] = addr_hit[17] & (|(racl_policies_i[RaclPolicySelVec[17]].read_perm & racl_role_vec)); + racl_addr_hit_write[17] = addr_hit[17] & (|(racl_policies_i[RaclPolicySelVec[17]].write_perm & racl_role_vec)); + racl_addr_hit_read [18] = addr_hit[18] & (|(racl_policies_i[RaclPolicySelVec[18]].read_perm & racl_role_vec)); + racl_addr_hit_write[18] = addr_hit[18] & (|(racl_policies_i[RaclPolicySelVec[18]].write_perm & racl_role_vec)); + racl_addr_hit_read [19] = addr_hit[19] & (|(racl_policies_i[RaclPolicySelVec[19]].read_perm & racl_role_vec)); + racl_addr_hit_write[19] = addr_hit[19] & (|(racl_policies_i[RaclPolicySelVec[19]].write_perm & racl_role_vec)); + racl_addr_hit_read [20] = addr_hit[20] & (|(racl_policies_i[RaclPolicySelVec[20]].read_perm & racl_role_vec)); + racl_addr_hit_write[20] = addr_hit[20] & (|(racl_policies_i[RaclPolicySelVec[20]].write_perm & racl_role_vec)); + racl_addr_hit_read [21] = addr_hit[21] & (|(racl_policies_i[RaclPolicySelVec[21]].read_perm & racl_role_vec)); + racl_addr_hit_write[21] = addr_hit[21] & (|(racl_policies_i[RaclPolicySelVec[21]].write_perm & racl_role_vec)); + racl_addr_hit_read [22] = addr_hit[22] & (|(racl_policies_i[RaclPolicySelVec[22]].read_perm & racl_role_vec)); + racl_addr_hit_write[22] = addr_hit[22] & (|(racl_policies_i[RaclPolicySelVec[22]].write_perm & racl_role_vec)); + racl_addr_hit_read [23] = addr_hit[23] & (|(racl_policies_i[RaclPolicySelVec[23]].read_perm & racl_role_vec)); + racl_addr_hit_write[23] = addr_hit[23] & (|(racl_policies_i[RaclPolicySelVec[23]].write_perm & racl_role_vec)); + racl_addr_hit_read [24] = addr_hit[24] & (|(racl_policies_i[RaclPolicySelVec[24]].read_perm & racl_role_vec)); + racl_addr_hit_write[24] = addr_hit[24] & (|(racl_policies_i[RaclPolicySelVec[24]].write_perm & racl_role_vec)); + racl_addr_hit_read [25] = addr_hit[25] & (|(racl_policies_i[RaclPolicySelVec[25]].read_perm & racl_role_vec)); + racl_addr_hit_write[25] = addr_hit[25] & (|(racl_policies_i[RaclPolicySelVec[25]].write_perm & racl_role_vec)); + racl_addr_hit_read [26] = addr_hit[26] & (|(racl_policies_i[RaclPolicySelVec[26]].read_perm & racl_role_vec)); + racl_addr_hit_write[26] = addr_hit[26] & (|(racl_policies_i[RaclPolicySelVec[26]].write_perm & racl_role_vec)); + racl_addr_hit_read [27] = addr_hit[27] & (|(racl_policies_i[RaclPolicySelVec[27]].read_perm & racl_role_vec)); + racl_addr_hit_write[27] = addr_hit[27] & (|(racl_policies_i[RaclPolicySelVec[27]].write_perm & racl_role_vec)); + racl_addr_hit_read [28] = addr_hit[28] & (|(racl_policies_i[RaclPolicySelVec[28]].read_perm & racl_role_vec)); + racl_addr_hit_write[28] = addr_hit[28] & (|(racl_policies_i[RaclPolicySelVec[28]].write_perm & racl_role_vec)); + racl_addr_hit_read [29] = addr_hit[29] & (|(racl_policies_i[RaclPolicySelVec[29]].read_perm & racl_role_vec)); + racl_addr_hit_write[29] = addr_hit[29] & (|(racl_policies_i[RaclPolicySelVec[29]].write_perm & racl_role_vec)); + racl_addr_hit_read [30] = addr_hit[30] & (|(racl_policies_i[RaclPolicySelVec[30]].read_perm & racl_role_vec)); + racl_addr_hit_write[30] = addr_hit[30] & (|(racl_policies_i[RaclPolicySelVec[30]].write_perm & racl_role_vec)); + racl_addr_hit_read [31] = addr_hit[31] & (|(racl_policies_i[RaclPolicySelVec[31]].read_perm & racl_role_vec)); + racl_addr_hit_write[31] = addr_hit[31] & (|(racl_policies_i[RaclPolicySelVec[31]].write_perm & racl_role_vec)); + end else begin : gen_no_racl + racl_addr_hit_read = addr_hit; + racl_addr_hit_write = addr_hit; + end end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + // Address hit but failed the RACL check + assign racl_error_o = (|addr_hit) & ~(|(addr_hit & (racl_addr_hit_read | racl_addr_hit_write))); + assign racl_error_log_o.racl_role = racl_role; + + if (EnableRacl) begin : gen_racl_log + assign racl_error_log_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd); + assign racl_error_log_o.read_not_write = tl_i.a_opcode == tlul_pkg::Get; + end else begin : gen_no_racl_log + assign racl_error_log_o.ctn_uid = '0; + assign racl_error_log_o.read_not_write = 1'b0; + end // Check sub-word write is permitted always_comb begin wr_err = (reg_we & - ((addr_hit[ 0] & (|(I2C_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(I2C_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(I2C_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(I2C_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(I2C_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(I2C_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(I2C_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(I2C_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(I2C_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(I2C_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(I2C_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(I2C_PERMIT[11] & ~reg_be))) | - (addr_hit[12] & (|(I2C_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(I2C_PERMIT[13] & ~reg_be))) | - (addr_hit[14] & (|(I2C_PERMIT[14] & ~reg_be))) | - (addr_hit[15] & (|(I2C_PERMIT[15] & ~reg_be))) | - (addr_hit[16] & (|(I2C_PERMIT[16] & ~reg_be))) | - (addr_hit[17] & (|(I2C_PERMIT[17] & ~reg_be))) | - (addr_hit[18] & (|(I2C_PERMIT[18] & ~reg_be))) | - (addr_hit[19] & (|(I2C_PERMIT[19] & ~reg_be))) | - (addr_hit[20] & (|(I2C_PERMIT[20] & ~reg_be))) | - (addr_hit[21] & (|(I2C_PERMIT[21] & ~reg_be))) | - (addr_hit[22] & (|(I2C_PERMIT[22] & ~reg_be))) | - (addr_hit[23] & (|(I2C_PERMIT[23] & ~reg_be))) | - (addr_hit[24] & (|(I2C_PERMIT[24] & ~reg_be))) | - (addr_hit[25] & (|(I2C_PERMIT[25] & ~reg_be))) | - (addr_hit[26] & (|(I2C_PERMIT[26] & ~reg_be))) | - (addr_hit[27] & (|(I2C_PERMIT[27] & ~reg_be))) | - (addr_hit[28] & (|(I2C_PERMIT[28] & ~reg_be))) | - (addr_hit[29] & (|(I2C_PERMIT[29] & ~reg_be))) | - (addr_hit[30] & (|(I2C_PERMIT[30] & ~reg_be))) | - (addr_hit[31] & (|(I2C_PERMIT[31] & ~reg_be))))); + ((racl_addr_hit_write[ 0] & (|(I2C_PERMIT[ 0] & ~reg_be))) | + (racl_addr_hit_write[ 1] & (|(I2C_PERMIT[ 1] & ~reg_be))) | + (racl_addr_hit_write[ 2] & (|(I2C_PERMIT[ 2] & ~reg_be))) | + (racl_addr_hit_write[ 3] & (|(I2C_PERMIT[ 3] & ~reg_be))) | + (racl_addr_hit_write[ 4] & (|(I2C_PERMIT[ 4] & ~reg_be))) | + (racl_addr_hit_write[ 5] & (|(I2C_PERMIT[ 5] & ~reg_be))) | + (racl_addr_hit_write[ 6] & (|(I2C_PERMIT[ 6] & ~reg_be))) | + (racl_addr_hit_write[ 7] & (|(I2C_PERMIT[ 7] & ~reg_be))) | + (racl_addr_hit_write[ 8] & (|(I2C_PERMIT[ 8] & ~reg_be))) | + (racl_addr_hit_write[ 9] & (|(I2C_PERMIT[ 9] & ~reg_be))) | + (racl_addr_hit_write[10] & (|(I2C_PERMIT[10] & ~reg_be))) | + (racl_addr_hit_write[11] & (|(I2C_PERMIT[11] & ~reg_be))) | + (racl_addr_hit_write[12] & (|(I2C_PERMIT[12] & ~reg_be))) | + (racl_addr_hit_write[13] & (|(I2C_PERMIT[13] & ~reg_be))) | + (racl_addr_hit_write[14] & (|(I2C_PERMIT[14] & ~reg_be))) | + (racl_addr_hit_write[15] & (|(I2C_PERMIT[15] & ~reg_be))) | + (racl_addr_hit_write[16] & (|(I2C_PERMIT[16] & ~reg_be))) | + (racl_addr_hit_write[17] & (|(I2C_PERMIT[17] & ~reg_be))) | + (racl_addr_hit_write[18] & (|(I2C_PERMIT[18] & ~reg_be))) | + (racl_addr_hit_write[19] & (|(I2C_PERMIT[19] & ~reg_be))) | + (racl_addr_hit_write[20] & (|(I2C_PERMIT[20] & ~reg_be))) | + (racl_addr_hit_write[21] & (|(I2C_PERMIT[21] & ~reg_be))) | + (racl_addr_hit_write[22] & (|(I2C_PERMIT[22] & ~reg_be))) | + (racl_addr_hit_write[23] & (|(I2C_PERMIT[23] & ~reg_be))) | + (racl_addr_hit_write[24] & (|(I2C_PERMIT[24] & ~reg_be))) | + (racl_addr_hit_write[25] & (|(I2C_PERMIT[25] & ~reg_be))) | + (racl_addr_hit_write[26] & (|(I2C_PERMIT[26] & ~reg_be))) | + (racl_addr_hit_write[27] & (|(I2C_PERMIT[27] & ~reg_be))) | + (racl_addr_hit_write[28] & (|(I2C_PERMIT[28] & ~reg_be))) | + (racl_addr_hit_write[29] & (|(I2C_PERMIT[29] & ~reg_be))) | + (racl_addr_hit_write[30] & (|(I2C_PERMIT[30] & ~reg_be))) | + (racl_addr_hit_write[31] & (|(I2C_PERMIT[31] & ~reg_be))))); end // Generate write-enables - assign intr_state_we = addr_hit[0] & reg_we & !reg_error; + assign intr_state_we = racl_addr_hit_write[0] & reg_we & !reg_error; assign intr_state_rx_overflow_wd = reg_wdata[3]; @@ -3478,7 +3594,7 @@ module i2c_reg_top ( assign intr_state_unexp_stop_wd = reg_wdata[13]; assign intr_state_host_timeout_wd = reg_wdata[14]; - assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; + assign intr_enable_we = racl_addr_hit_write[1] & reg_we & !reg_error; assign intr_enable_fmt_threshold_wd = reg_wdata[0]; @@ -3509,7 +3625,7 @@ module i2c_reg_top ( assign intr_enable_unexp_stop_wd = reg_wdata[13]; assign intr_enable_host_timeout_wd = reg_wdata[14]; - assign intr_test_we = addr_hit[2] & reg_we & !reg_error; + assign intr_test_we = racl_addr_hit_write[2] & reg_we & !reg_error; assign intr_test_fmt_threshold_wd = reg_wdata[0]; @@ -3540,10 +3656,10 @@ module i2c_reg_top ( assign intr_test_unexp_stop_wd = reg_wdata[13]; assign intr_test_host_timeout_wd = reg_wdata[14]; - assign alert_test_we = addr_hit[3] & reg_we & !reg_error; + assign alert_test_we = racl_addr_hit_write[3] & reg_we & !reg_error; assign alert_test_wd = reg_wdata[0]; - assign ctrl_we = addr_hit[4] & reg_we & !reg_error; + assign ctrl_we = racl_addr_hit_write[4] & reg_we & !reg_error; assign ctrl_enablehost_wd = reg_wdata[0]; @@ -3558,9 +3674,9 @@ module i2c_reg_top ( assign ctrl_multi_controller_monitor_en_wd = reg_wdata[5]; assign ctrl_tx_stretch_ctrl_en_wd = reg_wdata[6]; - assign status_re = addr_hit[5] & reg_re & !reg_error; - assign rdata_re = addr_hit[6] & reg_re & !reg_error; - assign fdata_we = addr_hit[7] & reg_we & !reg_error; + assign status_re = racl_addr_hit_write[5] & reg_re & !reg_error; + assign rdata_re = racl_addr_hit_write[6] & reg_re & !reg_error; + assign fdata_we = racl_addr_hit_write[7] & reg_we & !reg_error; assign fdata_fbyte_wd = reg_wdata[7:0]; @@ -3573,7 +3689,7 @@ module i2c_reg_top ( assign fdata_rcont_wd = reg_wdata[11]; assign fdata_nakok_wd = reg_wdata[12]; - assign fifo_ctrl_we = addr_hit[8] & reg_we & !reg_error; + assign fifo_ctrl_we = racl_addr_hit_write[8] & reg_we & !reg_error; assign fifo_ctrl_rxrst_wd = reg_wdata[0]; @@ -3582,59 +3698,59 @@ module i2c_reg_top ( assign fifo_ctrl_acqrst_wd = reg_wdata[7]; assign fifo_ctrl_txrst_wd = reg_wdata[8]; - assign host_fifo_config_we = addr_hit[9] & reg_we & !reg_error; + assign host_fifo_config_we = racl_addr_hit_write[9] & reg_we & !reg_error; assign host_fifo_config_rx_thresh_wd = reg_wdata[11:0]; assign host_fifo_config_fmt_thresh_wd = reg_wdata[27:16]; - assign target_fifo_config_we = addr_hit[10] & reg_we & !reg_error; + assign target_fifo_config_we = racl_addr_hit_write[10] & reg_we & !reg_error; assign target_fifo_config_tx_thresh_wd = reg_wdata[11:0]; assign target_fifo_config_acq_thresh_wd = reg_wdata[27:16]; - assign host_fifo_status_re = addr_hit[11] & reg_re & !reg_error; - assign target_fifo_status_re = addr_hit[12] & reg_re & !reg_error; - assign ovrd_we = addr_hit[13] & reg_we & !reg_error; + assign host_fifo_status_re = racl_addr_hit_write[11] & reg_re & !reg_error; + assign target_fifo_status_re = racl_addr_hit_write[12] & reg_re & !reg_error; + assign ovrd_we = racl_addr_hit_write[13] & reg_we & !reg_error; assign ovrd_txovrden_wd = reg_wdata[0]; assign ovrd_sclval_wd = reg_wdata[1]; assign ovrd_sdaval_wd = reg_wdata[2]; - assign val_re = addr_hit[14] & reg_re & !reg_error; - assign timing0_we = addr_hit[15] & reg_we & !reg_error; + assign val_re = racl_addr_hit_write[14] & reg_re & !reg_error; + assign timing0_we = racl_addr_hit_write[15] & reg_we & !reg_error; assign timing0_thigh_wd = reg_wdata[12:0]; assign timing0_tlow_wd = reg_wdata[28:16]; - assign timing1_we = addr_hit[16] & reg_we & !reg_error; + assign timing1_we = racl_addr_hit_write[16] & reg_we & !reg_error; assign timing1_t_r_wd = reg_wdata[9:0]; assign timing1_t_f_wd = reg_wdata[24:16]; - assign timing2_we = addr_hit[17] & reg_we & !reg_error; + assign timing2_we = racl_addr_hit_write[17] & reg_we & !reg_error; assign timing2_tsu_sta_wd = reg_wdata[12:0]; assign timing2_thd_sta_wd = reg_wdata[28:16]; - assign timing3_we = addr_hit[18] & reg_we & !reg_error; + assign timing3_we = racl_addr_hit_write[18] & reg_we & !reg_error; assign timing3_tsu_dat_wd = reg_wdata[8:0]; assign timing3_thd_dat_wd = reg_wdata[28:16]; - assign timing4_we = addr_hit[19] & reg_we & !reg_error; + assign timing4_we = racl_addr_hit_write[19] & reg_we & !reg_error; assign timing4_tsu_sto_wd = reg_wdata[12:0]; assign timing4_t_buf_wd = reg_wdata[28:16]; - assign timeout_ctrl_we = addr_hit[20] & reg_we & !reg_error; + assign timeout_ctrl_we = racl_addr_hit_write[20] & reg_we & !reg_error; assign timeout_ctrl_val_wd = reg_wdata[29:0]; assign timeout_ctrl_mode_wd = reg_wdata[30]; assign timeout_ctrl_en_wd = reg_wdata[31]; - assign target_id_we = addr_hit[21] & reg_we & !reg_error; + assign target_id_we = racl_addr_hit_write[21] & reg_we & !reg_error; assign target_id_address0_wd = reg_wdata[6:0]; @@ -3643,34 +3759,34 @@ module i2c_reg_top ( assign target_id_address1_wd = reg_wdata[20:14]; assign target_id_mask1_wd = reg_wdata[27:21]; - assign acqdata_re = addr_hit[22] & reg_re & !reg_error; - assign txdata_we = addr_hit[23] & reg_we & !reg_error; + assign acqdata_re = racl_addr_hit_write[22] & reg_re & !reg_error; + assign txdata_we = racl_addr_hit_write[23] & reg_we & !reg_error; assign txdata_wd = reg_wdata[7:0]; - assign host_timeout_ctrl_we = addr_hit[24] & reg_we & !reg_error; + assign host_timeout_ctrl_we = racl_addr_hit_write[24] & reg_we & !reg_error; assign host_timeout_ctrl_wd = reg_wdata[19:0]; - assign target_timeout_ctrl_we = addr_hit[25] & reg_we & !reg_error; + assign target_timeout_ctrl_we = racl_addr_hit_write[25] & reg_we & !reg_error; assign target_timeout_ctrl_val_wd = reg_wdata[30:0]; assign target_timeout_ctrl_en_wd = reg_wdata[31]; - assign target_nack_count_re = addr_hit[26] & reg_re & !reg_error; + assign target_nack_count_re = racl_addr_hit_write[26] & reg_re & !reg_error; assign target_nack_count_wd = '1; - assign target_ack_ctrl_re = addr_hit[27] & reg_re & !reg_error; - assign target_ack_ctrl_we = addr_hit[27] & reg_we & !reg_error; + assign target_ack_ctrl_re = racl_addr_hit_write[27] & reg_re & !reg_error; + assign target_ack_ctrl_we = racl_addr_hit_write[27] & reg_we & !reg_error; assign target_ack_ctrl_nbytes_wd = reg_wdata[8:0]; assign target_ack_ctrl_nack_wd = reg_wdata[31]; - assign acq_fifo_next_data_re = addr_hit[28] & reg_re & !reg_error; - assign host_nack_handler_timeout_we = addr_hit[29] & reg_we & !reg_error; + assign acq_fifo_next_data_re = racl_addr_hit_write[28] & reg_re & !reg_error; + assign host_nack_handler_timeout_we = racl_addr_hit_write[29] & reg_we & !reg_error; assign host_nack_handler_timeout_val_wd = reg_wdata[30:0]; assign host_nack_handler_timeout_en_wd = reg_wdata[31]; - assign controller_events_we = addr_hit[30] & reg_we & !reg_error; + assign controller_events_we = racl_addr_hit_write[30] & reg_we & !reg_error; assign controller_events_nack_wd = reg_wdata[0]; @@ -3679,7 +3795,7 @@ module i2c_reg_top ( assign controller_events_bus_timeout_wd = reg_wdata[2]; assign controller_events_arbitration_lost_wd = reg_wdata[3]; - assign target_events_we = addr_hit[31] & reg_we & !reg_error; + assign target_events_we = racl_addr_hit_write[31] & reg_we & !reg_error; assign target_events_tx_pending_wd = reg_wdata[0]; @@ -3728,7 +3844,7 @@ module i2c_reg_top ( always_comb begin reg_rdata_next = '0; unique case (1'b1) - addr_hit[0]: begin + racl_addr_hit_read[0]: begin reg_rdata_next[0] = intr_state_fmt_threshold_qs; reg_rdata_next[1] = intr_state_rx_threshold_qs; reg_rdata_next[2] = intr_state_acq_threshold_qs; @@ -3746,7 +3862,7 @@ module i2c_reg_top ( reg_rdata_next[14] = intr_state_host_timeout_qs; end - addr_hit[1]: begin + racl_addr_hit_read[1]: begin reg_rdata_next[0] = intr_enable_fmt_threshold_qs; reg_rdata_next[1] = intr_enable_rx_threshold_qs; reg_rdata_next[2] = intr_enable_acq_threshold_qs; @@ -3764,7 +3880,7 @@ module i2c_reg_top ( reg_rdata_next[14] = intr_enable_host_timeout_qs; end - addr_hit[2]: begin + racl_addr_hit_read[2]: begin reg_rdata_next[0] = '0; reg_rdata_next[1] = '0; reg_rdata_next[2] = '0; @@ -3782,11 +3898,11 @@ module i2c_reg_top ( reg_rdata_next[14] = '0; end - addr_hit[3]: begin + racl_addr_hit_read[3]: begin reg_rdata_next[0] = '0; end - addr_hit[4]: begin + racl_addr_hit_read[4]: begin reg_rdata_next[0] = ctrl_enablehost_qs; reg_rdata_next[1] = ctrl_enabletarget_qs; reg_rdata_next[2] = ctrl_llpbk_qs; @@ -3796,7 +3912,7 @@ module i2c_reg_top ( reg_rdata_next[6] = ctrl_tx_stretch_ctrl_en_qs; end - addr_hit[5]: begin + racl_addr_hit_read[5]: begin reg_rdata_next[0] = status_fmtfull_qs; reg_rdata_next[1] = status_rxfull_qs; reg_rdata_next[2] = status_fmtempty_qs; @@ -3810,11 +3926,11 @@ module i2c_reg_top ( reg_rdata_next[10] = status_ack_ctrl_stretch_qs; end - addr_hit[6]: begin + racl_addr_hit_read[6]: begin reg_rdata_next[7:0] = rdata_qs; end - addr_hit[7]: begin + racl_addr_hit_read[7]: begin reg_rdata_next[7:0] = '0; reg_rdata_next[8] = '0; reg_rdata_next[9] = '0; @@ -3823,126 +3939,126 @@ module i2c_reg_top ( reg_rdata_next[12] = '0; end - addr_hit[8]: begin + racl_addr_hit_read[8]: begin reg_rdata_next[0] = '0; reg_rdata_next[1] = '0; reg_rdata_next[7] = '0; reg_rdata_next[8] = '0; end - addr_hit[9]: begin + racl_addr_hit_read[9]: begin reg_rdata_next[11:0] = host_fifo_config_rx_thresh_qs; reg_rdata_next[27:16] = host_fifo_config_fmt_thresh_qs; end - addr_hit[10]: begin + racl_addr_hit_read[10]: begin reg_rdata_next[11:0] = target_fifo_config_tx_thresh_qs; reg_rdata_next[27:16] = target_fifo_config_acq_thresh_qs; end - addr_hit[11]: begin + racl_addr_hit_read[11]: begin reg_rdata_next[11:0] = host_fifo_status_fmtlvl_qs; reg_rdata_next[27:16] = host_fifo_status_rxlvl_qs; end - addr_hit[12]: begin + racl_addr_hit_read[12]: begin reg_rdata_next[11:0] = target_fifo_status_txlvl_qs; reg_rdata_next[27:16] = target_fifo_status_acqlvl_qs; end - addr_hit[13]: begin + racl_addr_hit_read[13]: begin reg_rdata_next[0] = ovrd_txovrden_qs; reg_rdata_next[1] = ovrd_sclval_qs; reg_rdata_next[2] = ovrd_sdaval_qs; end - addr_hit[14]: begin + racl_addr_hit_read[14]: begin reg_rdata_next[15:0] = val_scl_rx_qs; reg_rdata_next[31:16] = val_sda_rx_qs; end - addr_hit[15]: begin + racl_addr_hit_read[15]: begin reg_rdata_next[12:0] = timing0_thigh_qs; reg_rdata_next[28:16] = timing0_tlow_qs; end - addr_hit[16]: begin + racl_addr_hit_read[16]: begin reg_rdata_next[9:0] = timing1_t_r_qs; reg_rdata_next[24:16] = timing1_t_f_qs; end - addr_hit[17]: begin + racl_addr_hit_read[17]: begin reg_rdata_next[12:0] = timing2_tsu_sta_qs; reg_rdata_next[28:16] = timing2_thd_sta_qs; end - addr_hit[18]: begin + racl_addr_hit_read[18]: begin reg_rdata_next[8:0] = timing3_tsu_dat_qs; reg_rdata_next[28:16] = timing3_thd_dat_qs; end - addr_hit[19]: begin + racl_addr_hit_read[19]: begin reg_rdata_next[12:0] = timing4_tsu_sto_qs; reg_rdata_next[28:16] = timing4_t_buf_qs; end - addr_hit[20]: begin + racl_addr_hit_read[20]: begin reg_rdata_next[29:0] = timeout_ctrl_val_qs; reg_rdata_next[30] = timeout_ctrl_mode_qs; reg_rdata_next[31] = timeout_ctrl_en_qs; end - addr_hit[21]: begin + racl_addr_hit_read[21]: begin reg_rdata_next[6:0] = target_id_address0_qs; reg_rdata_next[13:7] = target_id_mask0_qs; reg_rdata_next[20:14] = target_id_address1_qs; reg_rdata_next[27:21] = target_id_mask1_qs; end - addr_hit[22]: begin + racl_addr_hit_read[22]: begin reg_rdata_next[7:0] = acqdata_abyte_qs; reg_rdata_next[10:8] = acqdata_signal_qs; end - addr_hit[23]: begin + racl_addr_hit_read[23]: begin reg_rdata_next[7:0] = '0; end - addr_hit[24]: begin + racl_addr_hit_read[24]: begin reg_rdata_next[19:0] = host_timeout_ctrl_qs; end - addr_hit[25]: begin + racl_addr_hit_read[25]: begin reg_rdata_next[30:0] = target_timeout_ctrl_val_qs; reg_rdata_next[31] = target_timeout_ctrl_en_qs; end - addr_hit[26]: begin + racl_addr_hit_read[26]: begin reg_rdata_next[7:0] = target_nack_count_qs; end - addr_hit[27]: begin + racl_addr_hit_read[27]: begin reg_rdata_next[8:0] = target_ack_ctrl_nbytes_qs; reg_rdata_next[31] = '0; end - addr_hit[28]: begin + racl_addr_hit_read[28]: begin reg_rdata_next[7:0] = acq_fifo_next_data_qs; end - addr_hit[29]: begin + racl_addr_hit_read[29]: begin reg_rdata_next[30:0] = host_nack_handler_timeout_val_qs; reg_rdata_next[31] = host_nack_handler_timeout_en_qs; end - addr_hit[30]: begin + racl_addr_hit_read[30]: begin reg_rdata_next[0] = controller_events_nack_qs; reg_rdata_next[1] = controller_events_unhandled_nack_timeout_qs; reg_rdata_next[2] = controller_events_bus_timeout_qs; reg_rdata_next[3] = controller_events_arbitration_lost_qs; end - addr_hit[31]: begin + racl_addr_hit_read[31]: begin reg_rdata_next[0] = target_events_tx_pending_qs; reg_rdata_next[1] = target_events_bus_timeout_qs; reg_rdata_next[2] = target_events_arbitration_lost_qs; @@ -3969,6 +4085,8 @@ module i2c_reg_top ( logic unused_be; assign unused_wdata = ^reg_wdata; assign unused_be = ^reg_be; + logic unused_policy_sel; + assign unused_policy_sel = ^racl_policies_i; // Assertions for Register Interface `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 03248e64fd9a5..6eb887a580259 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -973,6 +973,42 @@ top_signame: i2c0_lsio_trigger index: -1 } + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: racl_error + desc: + ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: racl_error_log + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: i2c0 + index: -1 + } { name: tl struct: tl @@ -18646,6 +18682,42 @@ top_signame: i2c0_lsio_trigger index: -1 } + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: racl_error + desc: + ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: racl_error_log + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: i2c0 + index: -1 + } { name: tl struct: tl diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv index a76c06cbbf31b..14effa1a36257 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -1113,6 +1113,9 @@ module top_darjeeling #( .ram_cfg_i(prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT), .ram_cfg_rsp_o(i2c_ram_1p_cfg_rsp_o), .lsio_trigger_o(i2c0_lsio_trigger), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .racl_error_log_o(), .tl_i(i2c0_tl_req), .tl_o(i2c0_tl_rsp), diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index c8549874e0757..e4ed11ffd711d 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -1315,6 +1315,42 @@ inst_name: i2c0 index: -1 } + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: racl_error + desc: + ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: racl_error_log + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: i2c0 + index: -1 + } { name: tl struct: tl @@ -1418,6 +1454,42 @@ inst_name: i2c1 index: -1 } + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c1 + index: -1 + } + { + name: racl_error + desc: + ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c1 + index: -1 + } + { + name: racl_error_log + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: i2c1 + index: -1 + } { name: tl struct: tl @@ -1521,6 +1593,42 @@ inst_name: i2c2 index: -1 } + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c2 + index: -1 + } + { + name: racl_error + desc: + ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c2 + index: -1 + } + { + name: racl_error_log + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: i2c2 + index: -1 + } { name: tl struct: tl @@ -17878,6 +17986,42 @@ inst_name: i2c0 index: -1 } + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: racl_error + desc: + ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: racl_error_log + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: i2c0 + index: -1 + } { name: tl struct: tl @@ -17927,6 +18071,42 @@ inst_name: i2c1 index: -1 } + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c1 + index: -1 + } + { + name: racl_error + desc: + ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c1 + index: -1 + } + { + name: racl_error_log + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: i2c1 + index: -1 + } { name: tl struct: tl @@ -17976,6 +18156,42 @@ inst_name: i2c2 index: -1 } + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c2 + index: -1 + } + { + name: racl_error + desc: + ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c2 + index: -1 + } + { + name: racl_error_log + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: i2c2 + index: -1 + } { name: tl struct: tl diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index d883508deaee1..48b5003fd8819 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -1311,6 +1311,9 @@ module top_earlgrey #( .ram_cfg_i(ast_ram_1p_cfg), .ram_cfg_rsp_o(), .lsio_trigger_o(), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .racl_error_log_o(), .tl_i(i2c0_tl_req), .tl_o(i2c0_tl_rsp), @@ -1357,6 +1360,9 @@ module top_earlgrey #( .ram_cfg_i(ast_ram_1p_cfg), .ram_cfg_rsp_o(), .lsio_trigger_o(), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .racl_error_log_o(), .tl_i(i2c1_tl_req), .tl_o(i2c1_tl_rsp), @@ -1403,6 +1409,9 @@ module top_earlgrey #( .ram_cfg_i(ast_ram_1p_cfg), .ram_cfg_rsp_o(), .lsio_trigger_o(), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .racl_error_log_o(), .tl_i(i2c2_tl_req), .tl_o(i2c2_tl_rsp),