diff --git a/Decode_State.sv b/Decode_State.sv index f1a8654..1654b61 100644 --- a/Decode_State.sv +++ b/Decode_State.sv @@ -83,33 +83,40 @@ module Decode_State(REG_CLOCK, REG_RESET, FR_MEM, FR_PC, FR_PC_4, DEC_PC_OUT, DE // 4-bit value: Output from decoder: alu_fun // 2-bit value: Output from decoder: rf_wr_sel - logic [31:0]DECODE_REG_1[0:6]; // 32-bit values - logic DECODE_REG_2[0:2]; // Single-bit values + logic [0:6][31:0]DECODE_REG_1; // 32-bit values + logic [0:2]DECODE_REG_2; // Single-bit values logic [3:0]DECODE_REG_3; // 4-bit value logic [1:0]DECODE_REG_4; // 2-bit value // Save the various outputs on the negative edge of the clock cycle always_ff @ (negedge REG_CLOCK) begin - - // 32-bit values - DECODE_REG_1[0] <= FR_PC_4 ; - DECODE_REG_1[1] <= ALU_A_TO_DR; - DECODE_REG_1[2] <= FR_MEM; - DECODE_REG_1[3] <= ALU_B_TO_DR; - DECODE_REG_1[4] <= J_TYPE; - DECODE_REG_1[5] <= B_TYPE; - DECODE_REG_1[6] <= I_TYPE; - - // Single-bit values - DECODE_REG_2[0] <= REGWRITE_TO_DR; - DECODE_REG_2[1] <= MEMWRITE_TO_DR; - DECODE_REG_2[2] <= MEMREAD2_TO_DR; - - // 4-bit value - DECODE_REG_3 <= ALU_FUN_TO_DR; - - // 2-bit value - DECODE_REG_4 <= RF_WR_SEL_TO_DR; + if (REG_RESET == 1'b1) begin + DECODE_REG_1 <= 0; + DECODE_REG_2 <= 0; + DECODE_REG_3 <= 0; + DECODE_REG_4 <= 0; + end + else begin + // 32-bit values + DECODE_REG_1[0] <= FR_PC_4 ; + DECODE_REG_1[1] <= ALU_A_TO_DR; + DECODE_REG_1[2] <= FR_MEM; + DECODE_REG_1[3] <= ALU_B_TO_DR; + DECODE_REG_1[4] <= J_TYPE; + DECODE_REG_1[5] <= B_TYPE; + DECODE_REG_1[6] <= I_TYPE; + + // Single-bit values + DECODE_REG_2[0] <= REGWRITE_TO_DR; + DECODE_REG_2[1] <= MEMWRITE_TO_DR; + DECODE_REG_2[2] <= MEMREAD2_TO_DR; + + // 4-bit value + DECODE_REG_3 <= ALU_FUN_TO_DR; + + // 2-bit value + DECODE_REG_4 <= RF_WR_SEL_TO_DR; + end end // Reading from the Fetch register should happen on the positive edge of the clock diff --git a/Execute_State.sv b/Execute_State.sv index bb929de..d806591 100644 --- a/Execute_State.sv +++ b/Execute_State.sv @@ -69,45 +69,49 @@ module Execute_State(EXECUTE_CLOCK, EXECUTE_RESET, DR_J_TYPE, DR_B_TYPE, DR_I_TY // 2-bit: rf_wr_sel from Decode register // 1-bit from Decode register: regWrite, memWrite, memRead2 - logic [31:0] EXECUTE_REG_1[0:3]; // 32-bit values + logic [0:3][31:0]EXECUTE_REG_1; // 32-bit values logic [1:0] EXECUTE_REG_2; // 2-bit value - logic EXECUTE_REG_3[0:2]; // 1-bit values + logic [0:2]EXECUTE_REG_3; // 1-bit values // Save the various outputs on the negative edge of the clock cycle always_ff @ (negedge EXECUTE_CLOCK) begin - - // 32-bit values - EXECUTE_REG_1[0] <= DR_PC_4 ; // PC + 4 from Decode register - EXECUTE_REG_1[1] <= DR_PC_MEM; // DOUT 1 from Decode register - EXECUTE_REG_1[2] <= ALU_OUT_TO_REG; // ALU Output - EXECUTE_REG_1[3] <= DR_RS2; // rs2 from Decode register - - // 2- bit value - EXECUTE_REG_2 <= DR_RF_WR_SEL; // RF_WR_SEL from Decode register - - // 1-bit values - EXECUTE_REG_3[0] <= DR_REG_WRITE; // regWrite from Decode register - EXECUTE_REG_3[1] <= DR_MEM_WRITE; // memWrite from Decode register - EXECUTE_REG_3[2] <= DR_MEM_READ2; // memRead2 from Decode register - + if (EXECUTE_RESET == 1'b1) begin + EXECUTE_REG_1 <= 0; + EXECUTE_REG_2 <= 0; + EXECUTE_REG_3 <= 0; + end + else begin + // 32-bit values + EXECUTE_REG_1[0] <= DR_PC_4 ; // PC + 4 from Decode register + EXECUTE_REG_1[1] <= DR_PC_MEM; // DOUT 1 from Decode register + EXECUTE_REG_1[2] <= ALU_OUT_TO_REG; // ALU Output + EXECUTE_REG_1[3] <= DR_RS2; // rs2 from Decode register + + // 2- bit value + EXECUTE_REG_2 <= DR_RF_WR_SEL; // RF_WR_SEL from Decode register + + // 1-bit values + EXECUTE_REG_3[0] <= DR_REG_WRITE; // regWrite from Decode register + EXECUTE_REG_3[1] <= DR_MEM_WRITE; // memWrite from Decode register + EXECUTE_REG_3[2] <= DR_MEM_READ2; // memRead2 from Decode register + end end // Reading from the Fetch register should happen on the positive edge of the clock always_ff @ (posedge EXECUTE_CLOCK) begin - - // 32-bit reads - EXEC_PC_4 = EXECUTE_REG_1[0]; - EXEC_PC_MEM = EXECUTE_REG_1[1]; - EXEC_ALU_RESULT = EXECUTE_REG_1[2]; - EXEC_RS2 = EXECUTE_REG_1[3]; - - // 2-bit reads - EXEC_RF_WR_SEL = EXECUTE_REG_2; - - // 1-bit reads - EXEC_REGWRITE = EXECUTE_REG_3[0]; - EXEC_MEMWRITE = EXECUTE_REG_3[1]; - EXEC_MEMREAD2 = EXECUTE_REG_3[2]; - + + // 32-bit reads + EXEC_PC_4 = EXECUTE_REG_1[0]; + EXEC_PC_MEM = EXECUTE_REG_1[1]; + EXEC_ALU_RESULT = EXECUTE_REG_1[2]; + EXEC_RS2 = EXECUTE_REG_1[3]; + + // 2-bit reads + EXEC_RF_WR_SEL = EXECUTE_REG_2; + + // 1-bit reads + EXEC_REGWRITE = EXECUTE_REG_3[0]; + EXEC_MEMWRITE = EXECUTE_REG_3[1]; + EXEC_MEMREAD2 = EXECUTE_REG_3[2]; end endmodule diff --git a/Fetch_State.sv b/Fetch_State.sv index 3920e69..f6456d4 100644 --- a/Fetch_State.sv +++ b/Fetch_State.sv @@ -33,7 +33,7 @@ FETCH_REG_OUT, FETCH_REG_PC, FETCH_REG_PC_4); // Program Count setup Program_Counter MyCounter (.pc_write(PC_WRITE), .pc_rst(RESET), -.pc_clk(CLOCK), .PC_DIN(MUX_to_PC), .PC_CNT(PC_OUT)); + .pc_clk(CLOCK), .PC_DIN(MUX_to_PC), .PC_CNT(PC_OUT)); // 4 Option MUX PC_MUX Prog_Count_MUX (.MUX_SEL(PC_SOURCE), .PC_4(PC_PLUS_4), .JALR(MUX_JALR), @@ -47,20 +47,25 @@ FETCH_REG_OUT, FETCH_REG_PC, FETCH_REG_PC_4); // Fetch Register for Pipeline Setup (write output of Memory to Fetch Register on negative clock cycle) // Initialize FETCH_REG to hold three values: PC, incremented PC and output of Memory - logic [31:0]FETCH_REG[0:3]; + logic [0:2][31:0]FETCH_REG; // Save the value of the output of the Memory module and PC+4 to the Fetch Register on negative clock cycle always_ff @ (negedge CLOCK) begin - FETCH_REG[0] <= MEM_IR; - FETCH_REG[1] <= PC_OUT; - FETCH_REG[2] <= PC_PLUS_4; - end + FETCH_REG[0] <= MEM_IR; + FETCH_REG[1] <= PC_OUT; + FETCH_REG[2] <= PC_PLUS_4; + end // Reading from the Fetch register should happen on the positive edge of the clock always_ff @ (posedge CLOCK) begin - FETCH_REG_OUT <= FETCH_REG[0]; - FETCH_REG_PC <= FETCH_REG[1]; - FETCH_REG_PC_4 <= FETCH_REG[2]; + if (RESET == 1'b1) begin + FETCH_REG <= 3'b000; + end + else begin + FETCH_REG_OUT <= FETCH_REG[0]; + FETCH_REG_PC <= FETCH_REG[1]; + FETCH_REG_PC_4 <= FETCH_REG[2]; + end end endmodule diff --git a/Memory_State.sv b/Memory_State.sv index bb7f69c..e35dfa3 100644 --- a/Memory_State.sv +++ b/Memory_State.sv @@ -60,39 +60,44 @@ module Memory_State(MEM_CLOCK, MEM_RESET, ER_memWrite, ER_memRead2, ER_REG_WRITE // 2-bit: rf_wr_sel from Execute register // 1-bit: regWrite from Execute register - logic [31:0] MEMORY_REG_1[0:3]; // 32-bit values + logic [0:3][31:0]MEMORY_REG_1; // 32-bit values logic [1:0] MEMORY_REG_2; // 2-bit value logic MEMORY_REG_3; // 1-bit value // Save the various outputs on the negative edge of the clock cycle always_ff @ (negedge MEM_CLOCK) begin - - // 32-bit values - MEMORY_REG_1[0] <= ER_PC_4 ; // PC + 4 from Execute register - MEMORY_REG_1[1] <= DOUT2_TO_MEM_REG; // DOUT2 from Memory module - MEMORY_REG_1[2] <= ER_ALU_OUT; // ALU Output from Execute register - MEMORY_REG_1[3] <= ER_PC_MEM; // Current PC from Execute register - - // 2-bit value - MEMORY_REG_2 <= ER_RF_WR_SEL; - - // 1-bit value - MEMORY_REG_3 <= ER_REG_WRITE; + if(MEM_RESET <= 0) begin + MEMORY_REG_1 <= 0; + MEMORY_REG_2 <= 0; + MEMORY_REG_3 <= 0; + end + else begin + // 32-bit values + MEMORY_REG_1[0] <= ER_PC_4 ; // PC + 4 from Execute register + MEMORY_REG_1[1] <= DOUT2_TO_MEM_REG; // DOUT2 from Memory module + MEMORY_REG_1[2] <= ER_ALU_OUT; // ALU Output from Execute register + MEMORY_REG_1[3] <= ER_PC_MEM; // Current PC from Execute register + + // 2-bit value + MEMORY_REG_2 <= ER_RF_WR_SEL; + + // 1-bit value + MEMORY_REG_3 <= ER_REG_WRITE; + end end // Reading from the Fetch register should happen on the positive edge of the clock always_ff @ (posedge MEM_CLOCK) begin - - // 32-bit reads - MEM_REG_PC_4 <= MEMORY_REG_1[0]; - MEM_REG_DOUT2 <= MEMORY_REG_1[1]; - MEM_REG_ALU_RESULT <= MEMORY_REG_1[2]; - MEM_REG_IR <= MEMORY_REG_1[3]; - - // 2-bit read - MEM_RF_WR_SEL <= MEMORY_REG_2; - - //1-bit read - MEM_REG_WRITE <= MEMORY_REG_3; + // 32-bit reads + MEM_REG_PC_4 <= MEMORY_REG_1[0]; + MEM_REG_DOUT2 <= MEMORY_REG_1[1]; + MEM_REG_ALU_RESULT <= MEMORY_REG_1[2]; + MEM_REG_IR <= MEMORY_REG_1[3]; + + // 2-bit read + MEM_RF_WR_SEL <= MEMORY_REG_2; + + //1-bit read + MEM_REG_WRITE <= MEMORY_REG_3; end endmodule diff --git a/otter_multi.mem b/otter_multi.mem index 12a1dec..4cdb1e1 100644 --- a/otter_multi.mem +++ b/otter_multi.mem @@ -1,2 +1,6 @@ -01e00093 -00007133 +00200413 +00398913 +005a8a13 +008b8b13 +002c8c13 +006d8d13