From 9510b19fbe7350b3e48b2f3a998a8bd7425ce004 Mon Sep 17 00:00:00 2001 From: unknown Date: Sun, 24 Apr 2022 16:55:54 -0700 Subject: [PATCH] fixed problem with rs2 not being properly carried from decode to execute state --- Decode_State.sv | 12 ++++++++---- Execute_State.sv | 22 +++++++++++----------- Memory_State.sv | 4 ++-- Pipelined_MCU.sv | 8 ++++---- otter_multi.mem | 9 ++++----- 5 files changed, 29 insertions(+), 26 deletions(-) diff --git a/Decode_State.sv b/Decode_State.sv index 1654b61..5573606 100644 --- a/Decode_State.sv +++ b/Decode_State.sv @@ -21,7 +21,7 @@ module Decode_State(REG_CLOCK, REG_RESET, FR_MEM, FR_PC, FR_PC_4, DEC_PC_OUT, DEC_ALU_A, DEC_ALU_B, DEC_J_TYPE, DEC_B_TYPE, - DEC_MEM_IR, DEC_ALU_FUN, DEC_REGWRITE, DEC_MEMWRITE, DEC_MEMREAD_2, DEC_RF_WR_SEL, DEC_I_TYPE); + DEC_MEM_IR, DEC_ALU_FUN, DEC_REGWRITE, DEC_MEMWRITE, DEC_MEMREAD_2, DEC_RF_WR_SEL, DEC_I_TYPE, DEC_RS1, DEC_RS2); // Inputs for register file input logic REG_CLOCK, REG_RESET; // 32-bit outputs from Fetch Register @@ -46,7 +46,7 @@ module Decode_State(REG_CLOCK, REG_RESET, FR_MEM, FR_PC, FR_PC_4, DEC_PC_OUT, DE logic [31:0] ALU_A_TO_DR, ALU_B_TO_DR; // Outputs of Decode register - output logic [31:0] DEC_PC_OUT, DEC_ALU_A, DEC_ALU_B, DEC_J_TYPE, DEC_B_TYPE, DEC_I_TYPE, DEC_MEM_IR; + output logic [31:0] DEC_PC_OUT, DEC_ALU_A, DEC_ALU_B, DEC_J_TYPE, DEC_B_TYPE, DEC_I_TYPE, DEC_MEM_IR, DEC_RS1, DEC_RS2; output logic [3:0] DEC_ALU_FUN; output logic DEC_REGWRITE, DEC_MEMWRITE, DEC_MEMREAD_2; output logic [1:0] DEC_RF_WR_SEL; @@ -74,7 +74,7 @@ module Decode_State(REG_CLOCK, REG_RESET, FR_MEM, FR_PC, FR_PC_4, DEC_PC_OUT, DE ALU_MUX_srcB MUX_B (.REG_rs2(REG_FILE_RS2), .IMM_GEN_I_Type(I_TYPE), .IMM_GEN_S_Type(S_TYPE), .PC_OUT(FR_PC), .alu_srcB(ALU_B), .srcB(ALU_B_TO_DR)); - // ----------------------------------- Fetch Register Setup ----------------------------------------------- + // ----------------------------------- Decode Register Setup ----------------------------------------------- // Initialize DECODE_REG to hold ten values: 32-bit: Incremented PC from Fetch register, Output of ALU_A, // Output of Fetch register, Output of ALU_B, J-type output of Immediate Generator, B-Type output of Immediate Generator @@ -83,7 +83,7 @@ module Decode_State(REG_CLOCK, REG_RESET, FR_MEM, FR_PC, FR_PC_4, DEC_PC_OUT, DE // 4-bit value: Output from decoder: alu_fun // 2-bit value: Output from decoder: rf_wr_sel - logic [0:6][31:0]DECODE_REG_1; // 32-bit values + logic [0:8][31:0]DECODE_REG_1; // 32-bit values logic [0:2]DECODE_REG_2; // Single-bit values logic [3:0]DECODE_REG_3; // 4-bit value logic [1:0]DECODE_REG_4; // 2-bit value @@ -105,6 +105,8 @@ module Decode_State(REG_CLOCK, REG_RESET, FR_MEM, FR_PC, FR_PC_4, DEC_PC_OUT, DE DECODE_REG_1[4] <= J_TYPE; DECODE_REG_1[5] <= B_TYPE; DECODE_REG_1[6] <= I_TYPE; + DECODE_REG_1[7] <= REG_FILE_RS1; + DECODE_REG_1[8] <= REG_FILE_RS2; // Single-bit values DECODE_REG_2[0] <= REGWRITE_TO_DR; @@ -130,6 +132,8 @@ module Decode_State(REG_CLOCK, REG_RESET, FR_MEM, FR_PC, FR_PC_4, DEC_PC_OUT, DE DEC_J_TYPE <= DECODE_REG_1[4]; DEC_B_TYPE <= DECODE_REG_1[5]; DEC_I_TYPE <= DECODE_REG_1[6]; + DEC_RS1 <= DECODE_REG_1[7]; + DEC_RS2 <= DECODE_REG_1[8]; // Single-bit reads diff --git a/Execute_State.sv b/Execute_State.sv index d806591..723ff55 100644 --- a/Execute_State.sv +++ b/Execute_State.sv @@ -20,7 +20,7 @@ ////////////////////////////////////////////////////////////////////////////////// -module Execute_State(EXECUTE_CLOCK, EXECUTE_RESET, DR_J_TYPE, DR_B_TYPE, DR_I_TYPE, DR_PC_MEM, DR_RS1, DR_RS2, DR_ALU_FUN, JALR_TO_PC, BRANCH_TO_PC, +module Execute_State(EXECUTE_CLOCK, EXECUTE_RESET, DR_J_TYPE, DR_B_TYPE, DR_I_TYPE, DR_PC_MEM, DR_RS1, DR_RS2, DR_ALU_A, DR_ALU_B, DR_ALU_FUN, JALR_TO_PC, BRANCH_TO_PC, JAL_TO_PC, PCSOURCE_TO_PC, DR_REG_WRITE, DR_MEM_WRITE, DR_MEM_READ2, DR_RF_WR_SEL, DR_PC_4, EXEC_PC_4, EXEC_PC_MEM, EXEC_ALU_RESULT, EXEC_RS2, EXEC_RF_WR_SEL, EXEC_REGWRITE, EXEC_MEMWRITE, EXEC_MEMREAD2); @@ -34,7 +34,7 @@ module Execute_State(EXECUTE_CLOCK, EXECUTE_RESET, DR_J_TYPE, DR_B_TYPE, DR_I_TY // Input for Branch Condition Generator + ALU input logic [31:0] DR_RS2; // Input for ALU - input logic [31:0] DR_ALU_FUN; + input logic [31:0] DR_ALU_FUN, DR_ALU_A, DR_ALU_B; // Inputs to pass directly into Execute register input logic DR_REG_WRITE, DR_MEM_WRITE, DR_MEM_READ2; @@ -61,7 +61,7 @@ module Execute_State(EXECUTE_CLOCK, EXECUTE_RESET, DR_J_TYPE, DR_B_TYPE, DR_I_TY Brand_Cond_Gen BC_Generator (.REG_INPUTA(DR_RS1), .REG_INPUTB(DR_RS2), .DR_MEM_OUT(DR_PC_MEM), .PC_SOURCE_OUT(PCSOURCE_TO_PC)); // ----------------------------------- ALU Setup ----------------------------------------------- - ALU_HW_4 Execute_ALU (.ALU_A(DR_RS1), .ALU_B(DR_RS2), .ALU_FUN(DR_ALU_FUN), .RESULT(ALU_OUT_TO_REG)); + ALU_HW_4 Execute_ALU (.ALU_A(DR_ALU_A), .ALU_B(DR_ALU_B), .ALU_FUN(DR_ALU_FUN), .RESULT(ALU_OUT_TO_REG)); // ----------------------------------- Execute Register Setup ----------------------------------------------- // Initalize Execute Register to hold the following values: @@ -101,17 +101,17 @@ module Execute_State(EXECUTE_CLOCK, EXECUTE_RESET, DR_J_TYPE, DR_B_TYPE, DR_I_TY always_ff @ (posedge EXECUTE_CLOCK) begin // 32-bit reads - EXEC_PC_4 = EXECUTE_REG_1[0]; - EXEC_PC_MEM = EXECUTE_REG_1[1]; - EXEC_ALU_RESULT = EXECUTE_REG_1[2]; - EXEC_RS2 = EXECUTE_REG_1[3]; + EXEC_PC_4 <= EXECUTE_REG_1[0]; + EXEC_PC_MEM <= EXECUTE_REG_1[1]; + EXEC_ALU_RESULT <= EXECUTE_REG_1[2]; + EXEC_RS2 <= EXECUTE_REG_1[3]; // 2-bit reads - EXEC_RF_WR_SEL = EXECUTE_REG_2; + EXEC_RF_WR_SEL <= EXECUTE_REG_2; // 1-bit reads - EXEC_REGWRITE = EXECUTE_REG_3[0]; - EXEC_MEMWRITE = EXECUTE_REG_3[1]; - EXEC_MEMREAD2 = EXECUTE_REG_3[2]; + EXEC_REGWRITE <= EXECUTE_REG_3[0]; + EXEC_MEMWRITE <= EXECUTE_REG_3[1]; + EXEC_MEMREAD2 <= EXECUTE_REG_3[2]; end endmodule diff --git a/Memory_State.sv b/Memory_State.sv index e35dfa3..ed02add 100644 --- a/Memory_State.sv +++ b/Memory_State.sv @@ -54,7 +54,7 @@ module Memory_State(MEM_CLOCK, MEM_RESET, ER_memWrite, ER_memRead2, ER_REG_WRITE assign M_IOBUS_OUT = ER_RS2; // ----------------------------------- Memory Register Setup ----------------------------------------------- - // Initalize Execute Register to hold the following values: + // Initalize Memory Register to hold the following values: // 32-bit: ALU result from Execute register, DOUT2 from Memory module, Current PC from Execute Register, PC + 4 from // Execute register // 2-bit: rf_wr_sel from Execute register @@ -66,7 +66,7 @@ module Memory_State(MEM_CLOCK, MEM_RESET, ER_memWrite, ER_memRead2, ER_REG_WRITE // Save the various outputs on the negative edge of the clock cycle always_ff @ (negedge MEM_CLOCK) begin - if(MEM_RESET <= 0) begin + if(MEM_RESET == 1'b1) begin MEMORY_REG_1 <= 0; MEMORY_REG_2 <= 0; MEMORY_REG_3 <= 0; diff --git a/Pipelined_MCU.sv b/Pipelined_MCU.sv index 115adc5..49010e9 100644 --- a/Pipelined_MCU.sv +++ b/Pipelined_MCU.sv @@ -46,16 +46,16 @@ module Pipelined_MCU(RST, CLK, IOBUS_IN, IOBUS_WR, IOBUS_OUT, IOBUS_ADDR); // --------------------------------- Decode State Setup----------------------------------------------- // Logics to connect outputs of Decode state to Execute State - logic [31:0] Decoder_PC_4, Decoder_rs1, Decoder_rs2, Decoder_J_type, Decoder_B_type, Decoder_I_type, Decoder_dout1; + logic [31:0] Decoder_PC_4, Decoder_rs1, Decoder_rs2, Decoder_J_type, Decoder_B_type, Decoder_I_type, Decoder_dout1, Decoder_ALU_A, Decoder_ALU_B; logic [3:0] Decoder_alu_fun; logic Decoder_regWrite, Decoder_memWrite, Decoder_memRead2; logic [1:0] Decoder_rf_wr_sel; Decode_State DS (.REG_CLOCK(CLK), .REG_RESET(RST), .FR_MEM(Fetch_reg_dout1), .FR_PC(Fetch_reg_pc), .FR_PC_4(Fetch_reg_PC_4), // Inputs - .DEC_PC_OUT(Decoder_PC_4), .DEC_ALU_A(Decoder_rs1), .DEC_ALU_B(Decoder_rs2), .DEC_J_TYPE(Decoder_J_type), // Outputs + .DEC_PC_OUT(Decoder_PC_4), .DEC_ALU_A(Decoder_ALU_A), .DEC_ALU_B(Decoder_ALU_B), .DEC_J_TYPE(Decoder_J_type), // Outputs .DEC_B_TYPE(Decoder_B_type), .DEC_I_TYPE(Decoder_I_type), .DEC_MEM_IR(Decoder_dout1), .DEC_ALU_FUN(Decoder_alu_fun), .DEC_REGWRITE(Decoder_regWrite), .DEC_MEMWRITE(Decoder_memWrite), .DEC_MEMREAD_2(Decoder_memRead2), - .DEC_RF_WR_SEL(Decoder_rf_wr_sel)); + .DEC_RF_WR_SEL(Decoder_rf_wr_sel), .DEC_RS1(Decoder_rs1), .DEC_RS2(Decoder_rs2)); // --------------------------------- Execute State Setup----------------------------------------------- @@ -67,7 +67,7 @@ module Pipelined_MCU(RST, CLK, IOBUS_IN, IOBUS_WR, IOBUS_OUT, IOBUS_ADDR); Execute_State ES (.EXECUTE_CLOCK(CLK), .EXECUTE_RESET(RST), .DR_J_TYPE(Decoder_J_type), .DR_B_TYPE(Decoder_B_type), // Inputs .DR_I_TYPE(Decoder_I_type), .DR_PC_MEM(Decoder_dout1), .DR_RS1(Decoder_rs1), .DR_RS2(Decoder_rs2), - .DR_ALU_FUN(Decoder_alu_fun), .DR_REG_WRITE(Decoder_regWrite), .DR_MEM_WRITE(Decoder_memWrite), + .DR_ALU_A(Decoder_ALU_A), .DR_ALU_B(Decoder_ALU_B), .DR_ALU_FUN(Decoder_alu_fun), .DR_REG_WRITE(Decoder_regWrite), .DR_MEM_WRITE(Decoder_memWrite), .DR_MEM_READ2(Decoder_memRead2), .DR_RF_WR_SEL(Decoder_rf_wr_sel), .DR_PC_4(Decoder_PC_4), .EXEC_PC_4(Execute_PC_4), .EXEC_PC_MEM(Execute_dout1), .EXEC_ALU_RESULT(Execute_alu_out), // Outputs .EXEC_RS2(Execute_rs2), .EXEC_RF_WR_SEL(Execute_rf_wr_sel), .EXEC_REGWRITE(Execute_regWrite), diff --git a/otter_multi.mem b/otter_multi.mem index 4cdb1e1..b2a5846 100644 --- a/otter_multi.mem +++ b/otter_multi.mem @@ -1,6 +1,5 @@ 00200413 -00398913 -005a8a13 -008b8b13 -002c8c13 -006d8d13 +00306493 +00507913 +01600993 +40948433