From 8440d6f1f8cfd1bf0bf198cf01a12987b5880e88 Mon Sep 17 00:00:00 2001 From: Q Date: Thu, 21 Apr 2022 10:32:14 -0700 Subject: [PATCH] unzipped files --- Decode_State.sv | 144 +++++++++++++++++++++++++++++++++++++++++++++ Execute_State.sv | 112 +++++++++++++++++++++++++++++++++++ Fetch_State.sv | 66 +++++++++++++++++++++ Memory_State.sv | 96 ++++++++++++++++++++++++++++++ PC_MUX.sv | 26 ++++++++ Pipelined_MCU.sv | 26 ++++++++ Writeback_State.sv | 46 +++++++++++++++ 7 files changed, 516 insertions(+) create mode 100644 Decode_State.sv create mode 100644 Execute_State.sv create mode 100644 Fetch_State.sv create mode 100644 Memory_State.sv create mode 100644 PC_MUX.sv create mode 100644 Pipelined_MCU.sv create mode 100644 Writeback_State.sv diff --git a/Decode_State.sv b/Decode_State.sv new file mode 100644 index 0000000..8e1d97c --- /dev/null +++ b/Decode_State.sv @@ -0,0 +1,144 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/19/2022 10:13:50 PM +// Design Name: +// Module Name: Decode_State +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Decode_State(REG_CLOCK, REG_RESET, FR_MEM, FR_PC, FR_PC_4, DEC_PC_OUT, DEC_ALU_A, DEC_ALU_B, DEC_J_TYPE, DEC_B_TYPE, + DEC_MEM_IR, DEC_ALU_FUN, DEC_REGWRITE, DEC_MEMWRITE, DEC_MEMREAD_2, DEC_RF_WR_SEL, DEC_I_TYPE); + // Inputs for register file + input logic REG_CLOCK, REG_RESET; + // 32-bit outputs from Fetch Register + input logic [31:0] FR_MEM, FR_PC, FR_PC_4; + + // Wires for outputs of Decoder that go to Decode Register + logic REGWRITE_TO_DR, MEMWRITE_TO_DR, MEMREAD2_TO_DR; + logic [3:0] ALU_FUN_TO_DR; + logic [1:0] RF_WR_SEL_TO_DR; + + // Wires for outputs of Decoder that are used internally in the module + logic ALU_A; + logic [1:0] ALU_B; + + // Wires for outputs of Register File + logic [31:0] REG_FILE_RS1, REG_FILE_RS2; + + // Wires for outptuts of Immediate Generator + logic [31:0] U_TYPE, I_TYPE, S_TYPE, J_TYPE, B_TYPE; + + // Wires for output of MUXes to enter Decoder Register + logic [31:0] ALU_A_TO_DR, ALU_B_TO_DR; + + // Outputs of Decode register + output logic [31:0] DEC_PC_OUT, DEC_ALU_A, DEC_ALU_B, DEC_J_TYPE, DEC_B_TYPE, DEC_I_TYPE, DEC_MEM_IR; + output logic [3:0] DEC_ALU_FUN; + output logic DEC_REGWRITE, DEC_MEMWRITE, DEC_MEMREAD_2; + output logic [1:0] DEC_RF_WR_SEL; + + // ----------------------------------- Decoder Setup ----------------------------------------------- + + cu_decoder Decoder (.IR_FETCH_REG(FR_MEM), .ALU_FUN(ALU_FUN_TO_DR), .ALU_SOURCE_A(ALU_A), .ALU_SOURCE_B(ALU_B), + .RF_WR_SEL(RF_WR_SEL_TO_DR), .REG_WRITE(REGWRITE_TO_DR), .MEM_WRITE(MEMWRITE_TO_DR), .MEM_READ_2(MEMREAD2_TO_DR)); + + // ----------------------------------- Register File Setup ----------------------------------------------- + + Register_File_HW_3 Reg_File (.CLOCK(REG_CLOCK), .WD(FR_MEM), .RF_RS1(REG_FILE_RS1), .RF_RS2(REG_FILE_RS2)); + + // ----------------------------------- Immediate Generator Setup ----------------------------------------------- + + Imm_Gen IG (.IR_INPUT(FR_MEM), .U_TYPE_OUT(U_TYPE), .I_TYPE_OUT(I_TYPE), .S_TYPE_OUT(S_TYPE), .J_TYPE_OUT(J_TYPE), + .B_TYPE_OUT(B_TYPE)); + + // ----------------------------------- ALU_A Setup ----------------------------------------------- + + ALU_MUX_srcA MUX_A (.REG_rs1(REG_FILE_RS1), .IMM_GEN_U_Type(U_TYPE), .alu_srcA(ALU_A), .srcA(ALU_A_TO_DR)); + + // ----------------------------------- ALU_B Setup ----------------------------------------------- + + ALU_MUX_srcB MUX_B (.REG_rs2(REG_FILE_RS2), .IMM_GEN_I_Type(I_TYPE), .IMM_GEN_S_Type(S_TYPE), .PC_OUT(FR_PC), + .alu_srcB(ALU_B), .srcB(ALU_B_TO_DR)); + + // ----------------------------------- Fetch Register Setup ----------------------------------------------- + + // Initialize DECODE_REG to hold ten values: 32-bit: Incremented PC from Fetch register, Output of ALU_A, + // Output of Fetch register, Output of ALU_B, J-type output of Immediate Generator, B-Type output of Immediate Generator + // I-Type output of Immediate Generator + // Single bit values: Outputs from decoder : regWrite, memWrite, memRead2 + // 4-bit value: Output from decoder: alu_fun + // 2-bit value: Output from decoder: rf_wr_sel + + logic [31:0]DECODE_REG_1[0:6]; // 32-bit values + logic DECODE_REG_2[0:2]; // Single-bit values + logic [3:0]DECODE_REG_3; // 4-bit value + logic [1:0]DECODE_REG_4; // 2-bit value + + // Save the various outputs on the negative edge of the clock cycle + always_ff @ (negedge REG_CLOCK) begin + + // 32-bit values + DECODE_REG_1[0] <= FR_PC_4 ; + DECODE_REG_1[1] <= ALU_A_TO_DR; + DECODE_REG_1[2] <= FR_MEM; + DECODE_REG_1[3] <= ALU_B_TO_DR; + DECODE_REG_1[4] <= J_TYPE; + DECODE_REG_1[5] <= B_TYPE; + DECODE_REG_1[6] <= I_TYPE; + + // Single-bit values + DECODE_REG_2[0] <= REGWRITE_TO_DR; + DECODE_REG_2[1] <= MEMWRITE_TO_DR; + DECODE_REG_2[2] <= MEMREAD2_TO_DR; + + // 4-bit value + DECODE_REG_3 <= ALU_FUN_TO_DR; + + // 2-bit value + DECODE_REG_4 <= RF_WR_SEL_TO_DR; + end + + // Reading from the Fetch register should happen on the positive edge of the clock + always_ff @ (posedge REG_CLOCK) begin + + // 32-bit reads + DEC_PC_OUT <= DECODE_REG_1[0]; + DEC_ALU_A <= DECODE_REG_1[1]; + DEC_MEM_IR <= DECODE_REG_1[2]; + DEC_ALU_B <= DECODE_REG_1[3]; + DEC_J_TYPE <= DECODE_REG_1[4]; + DEC_B_TYPE <= DECODE_REG_1[5]; + DEC_I_TYPE <= DECODE_REG_1[6]; + + + // Single-bit reads + DEC_REGWRITE <= DECODE_REG_2[0]; + DEC_MEMWRITE <= DECODE_REG_2[1]; + DEC_MEMREAD_2 <= DECODE_REG_2[2]; + + // 4-bit read + DEC_ALU_FUN <= DECODE_REG_3; + + // 2-bit read + DEC_RF_WR_SEL <= DECODE_REG_4; + + end + + + +endmodule + diff --git a/Execute_State.sv b/Execute_State.sv new file mode 100644 index 0000000..2c88361 --- /dev/null +++ b/Execute_State.sv @@ -0,0 +1,112 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/20/2022 07:21:22 PM +// Design Name: +// Module Name: Execute_State +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Execute_State(EXECUTE_CLOCK, EXECUTE_RESET, DR_J_TYPE, DR_B_TYPE, DR_I_TYPE, DR_PC_MEM, DR_RS1, DR_RS2, DR_ALU_FUN, JALR_TO_PC, BRANCH_TO_PC, + JAL_TO_PC, PCSOURCE_TO_PC, DR_REG_WRITE, DR_MEM_WRITE, DR_MEM_READ2, DR_RF_WR_SEL, DR_PC_4); + +// Inputs for clock and reset signals + input EXECUTE_CLOCK, EXECUTE_RESET; +// Inputs for Branch Address Generator + input logic [31:0] DR_J_TYPE, DR_B_TYPE, DR_I_TYPE; +// Inputs for Target Gen and Branch Condition Generator + ALU + input logic [31:0] DR_PC_MEM; //(Current PC) + input logic [31:0] DR_RS1; +// Input for Branch Condition Generator + ALU + input logic [31:0] DR_RS2; +// Input for ALU + input logic [31:0] DR_ALU_FUN; + +// Inputs to pass directly into Execute register + input logic DR_REG_WRITE, DR_MEM_WRITE, DR_MEM_READ2; + input logic [1:0] DR_RF_WR_SEL; + input logic [31:0] DR_PC_4; + +// Logics for outputs of ALU and rs2 + logic [31:0] ALU_OUT_TO_REG; + +// Outputs for Target Gen + Branch Condititon Generator + output logic [31:0] JALR_TO_PC, BRANCH_TO_PC, JAL_TO_PC; + output logic [1:0] PCSOURCE_TO_PC; + +// Outputs of Execute register + output logic [31:0] EXEC_PC_4, EXEC_PC_MEM, EXEC_ALU_RESULT, EXEC_RS2; + output logic [1:0] EXEC_RF_WR_SEL; + output logic EXEC_REGWRITE, EXEC_MEMWRITE, EXEC_MEMREAD2; + + // ----------------------------------- Target Gen Setup ----------------------------------------------- + Branch_Addr_Gen_HW_5 Target_Gen (.PC_COUNT(DR_PC_MEM), .J_INPUT(DR_J_TYPE), .B_INPUT(DR_B_TYPE), .I_INPUT(DR_I_TYPE), + .RS1_INPUT(DR_RS1), .JALR_OUT(JALR_TO_PC), .BRANCH_OUT(BRANCH_TO_PC), .JAL_OUT(JAL_TO_PC)); + + // ----------------------------------- Branch Cond. Gen Setup ----------------------------------------------- + Brand_Cond_Gen BC_Generator (.REG_INPUTA(DR_RS1), .REG_INPUTB(DR_RS2), .DR_MEM_OUT(DR_PC_MEM), .PC_SOURCE_OUT(PCSOURCE_TO_PC)); + + // ----------------------------------- ALU Setup ----------------------------------------------- + ALU_HW_4 Execute_ALU (.ALU_A(DR_RS1), .ALU_B(DR_RS2), .ALU_FUN(DR_ALU_FUN), .RESULT(ALU_OUT_TO_REG)); + + // ----------------------------------- Execute Register Setup ----------------------------------------------- + // Initalize Execute Register to hold the following values: + // 32-bit: PC+4 from Decode register, DOUT1 from Decode register, ALU output, rs2 from Decode register + // 2-bit: rf_wr_sel from Decode register + // 1-bit from Decode register: regWrite, memWrite, memRead2 + + logic [31:0] EXECUTE_REG1[0:3]; // 32-bit values + logic [1:0] EXECUTE_REG2; // 2-bit value + logic EXECUTE_REG3[0:2]; // 1-bit values + + // Save the various outputs on the negative edge of the clock cycle + always_ff @ (negedge EXECUTE_CLOCK) begin + + // 32-bit values + EXECUTE_REG_1[0] <= DR_PC_4 ; // PC + 4 from Decode register + EXECUTE_REG_1[1] <= DR_PC_MEM; // DOUT 1 from Decode register + EXECUTE_REG_1[2] <= ALU_OUT_TO_REG; // ALU Output + EXECUTE_REG_1[3] <= DR_RS2; // rs2 from Decode register + + // 2- bit value + EXECUTE_REG2 <= DR_RF_WR_SEL; // RF_WR_SEL from Decode register + + // 1-bit values + EXECUTE_REG3[0] <= DR_REG_WRITE; // regWrite from Decode register + EXECUTE_REG3[1] <= DR_MEM_WRITE; // memWrite from Decode register + EXECUTE_REG3[2] <= DR_MEM_READ2; // memRead2 from Decode register + + end + + // Reading from the Fetch register should happen on the positive edge of the clock + always_ff @ (posedge EXECUTE_CLOCK) begin + + // 32-bit reads + EXEC_PC_4 = EXECUTE_REG_1[0]; + EXEC_PC_MEM = EXECUTE_REG_1[1]; + EXEC_ALU_RESULT = EXECUTE_REG_1[2]; + EXEC_RS2 = EXECUTE_REG_1[3]; + + // 2-bit reads + EXEC_RF_WR_SEL = EXECUTE_REG_2; + + // 1-bit reads + EXEC_REGWRITE = EXECUTE_REG_3[0]; + EXEC_MEMWRITE = EXECUTE_REG_3[1]; + EXEC_MEMREAD2 = EXECUTE_REG_3[2]; + + end + endmodule diff --git a/Fetch_State.sv b/Fetch_State.sv new file mode 100644 index 0000000..3920e69 --- /dev/null +++ b/Fetch_State.sv @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps + +module Fetch_State(CLOCK, RESET, PC_WRITE, PC_SOURCE, MUX_JALR, MUX_JAL, MUX_BRANCH, PC_OUT, PC_PLUS_4, MEM_READ_1, MEM_IR, +FETCH_REG_OUT, FETCH_REG_PC, FETCH_REG_PC_4); + + // Inputs for PC and MEM + input CLOCK, RESET; + + // Inputs for PC and MUX + input logic PC_WRITE; + input logic [1:0]PC_SOURCE; + input logic [31:0] MUX_JALR, MUX_BRANCH, MUX_JAL; + // Logic for MUX to PC + logic [31:0] MUX_to_PC; + + // Output of PC, and incremented PC + output logic [31:0] PC_OUT, PC_PLUS_4; + + // Output of Memory + output logic [31:0] MEM_IR; + + // Input for MEM + input logic MEM_READ_1; + // Set MEM_READ_1 as high + assign MEM_READ_1 = 1'b1; + + // Outputs of Fetch register + output logic [31:0] FETCH_REG_OUT, FETCH_REG_PC, FETCH_REG_PC_4; + + // --------------------------------- Program Counter Setup---------------------------------------- + // Incrementer for Program Count (PC + 4) + PC_4 PC_Increment (.Program_count(PC_OUT), .PC_4(PC_PLUS_4)); + + // Program Count setup + Program_Counter MyCounter (.pc_write(PC_WRITE), .pc_rst(RESET), +.pc_clk(CLOCK), .PC_DIN(MUX_to_PC), .PC_CNT(PC_OUT)); + + // 4 Option MUX + PC_MUX Prog_Count_MUX (.MUX_SEL(PC_SOURCE), .PC_4(PC_PLUS_4), .JALR(MUX_JALR), + .BRANCH(MUX_BRANCH), .JAL(MUX_JAL), .MUX_OUT(MUX_to_PC)); + + //----------------------------------- Memory Setup ----------------------------------------------- + + // Memory Module setup (only look at bits [15:2] of the output for PC + Memory Mem_Module (.MEM_CLK(CLOCK), .MEM_ADDR1(PC_OUT[15:2]), .MEM_RDEN1(MEM_READ_1), .MEM_DOUT1(MEM_IR)); + + // Fetch Register for Pipeline Setup (write output of Memory to Fetch Register on negative clock cycle) + + // Initialize FETCH_REG to hold three values: PC, incremented PC and output of Memory + logic [31:0]FETCH_REG[0:3]; + + // Save the value of the output of the Memory module and PC+4 to the Fetch Register on negative clock cycle + always_ff @ (negedge CLOCK) begin + FETCH_REG[0] <= MEM_IR; + FETCH_REG[1] <= PC_OUT; + FETCH_REG[2] <= PC_PLUS_4; + end + + // Reading from the Fetch register should happen on the positive edge of the clock + always_ff @ (posedge CLOCK) begin + FETCH_REG_OUT <= FETCH_REG[0]; + FETCH_REG_PC <= FETCH_REG[1]; + FETCH_REG_PC_4 <= FETCH_REG[2]; + end + +endmodule diff --git a/Memory_State.sv b/Memory_State.sv new file mode 100644 index 0000000..81508a1 --- /dev/null +++ b/Memory_State.sv @@ -0,0 +1,96 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/20/2022 11:25:19 PM +// Design Name: +// Module Name: Memory_State +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Memory_State(); + +// Inputs for Memory register + input MEM_CLOCK, MEM_RESET; +// Inputs from Execute register + input logic ER_memWrite, ER_memRead2, ER_MEM_REG_WRITE; + input logic [31:0] ER_PC_MEM, ER_PC_4, ER_ALU_OUT, ER_RS2; + input logic [1:0] ER_RF_WR_SEL; + +// Output for IOBUS_ADDR, IOBUS_OUT, IOBUS_WR + output logic [31:0] IOBUS_ADDR, IOBUS_OUT, IOBUS_WR; + +// Wire for Memory dout2 + logic [31:0] DOUT2_TO_MEM_REG; + +// Outputs of Memory register + output logic [31:0] MEM_REG_DOUT2, MEM_REG_ALU_RESULT, MEM_REG_IR, MEM_REG_PC_4; + output logic [1:0] MEM_RF_WR_SEL; + output logic MEM_REG_WRITE; + + //----------------------------------- Memory Setup ----------------------------------------------- + + // Memory Module setup + Memory Mem_Module (.MEM_ADDR2(ER_ALU_OUT), .MEM_DIN2(ER_RS2), .MEM_WE2(ER_memWrite), .MEM_RDEN2(ER_memRead2), + .MEM_SIZE(ER_PC_MEM[14:12]), .IO_WR(IOBUS_WR), .MEM_DOUT2(DOUT2_TO_MEM_REG)); + // Still need to assign IOBUS_IN + + // Taking care of IOBUS..... + assign IOBUS_ADDR = ER_ALU_OUT; + assign IOBUS_OUT = ER_RS2; + + // ----------------------------------- Memory Register Setup ----------------------------------------------- + // Initalize Execute Register to hold the following values: + // 32-bit: ALU result from Execute register, DOUT2 from Memory module, Current PC from Execute Register, PC + 4 from + // Execute register + // 2-bit: rf_wr_sel from Execute register + // 1-bit: regWrite from Execute register + + logic [31:0] MEMORY_REG_1[0:3]; // 32-bit values + logic [1:0] MEMORY_REG_2; // 2-bit value + logic MEMORY_REG_3; // 1-bit value + + // Save the various outputs on the negative edge of the clock cycle + always_ff @ (negedge MEM_CLOCK) begin + + // 32-bit values + MEMORY_REG_1[0] <= ER_PC_4 ; // PC + 4 from Execute register + MEMORY_REG_1[1] <= DOUT2_TO_MEM_REG; // DOUT2 from Memory module + MEMORY_REG_1[2] <= ER_ALU_OUT; // ALU Output from Execute register + MEMORY_REG_1[3] <= ER_PC_MEM; // Current PC from Execute register + + // 2-bit value + MEMORY_REG_2 <= ER_RF_WR_SEL; + + // 1-bit value + MEMORY_REG_3 <= ER_PC_MEM; + end + + // Reading from the Fetch register should happen on the positive edge of the clock + always_ff @ (posedge EXECUTE_CLOCK) begin + + // 32-bit reads + MEM_REG_PC_4 <= MEMORY_REG_1[0]; + MEM_REG_DOUT2 <= MEMORY_REG_1[1]; + MEM_REG_ALU_RESULT <= MEMORY_REG_1[2]; + MEM_REG_IR <= MEMORY_REG_1[3]; + + // 2-bit read + MEM_RF_WR_SEL <= MEMORY_REG_2; + + //1-bit read + MEM_REG_WRITE <= MEMORY_REG_3; + end +endmodule diff --git a/PC_MUX.sv b/PC_MUX.sv new file mode 100644 index 0000000..5db1c03 --- /dev/null +++ b/PC_MUX.sv @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/19/2022 09:22:48 PM +// Design Name: +// Module Name: PC_MUX +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module PC_MUX( + + ); +endmodule diff --git a/Pipelined_MCU.sv b/Pipelined_MCU.sv new file mode 100644 index 0000000..221fc4e --- /dev/null +++ b/Pipelined_MCU.sv @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/21/2022 09:30:06 AM +// Design Name: +// Module Name: Pipelined_MCU +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Pipelined_MCU( + + ); +endmodule diff --git a/Writeback_State.sv b/Writeback_State.sv new file mode 100644 index 0000000..166b068 --- /dev/null +++ b/Writeback_State.sv @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/21/2022 12:15:10 AM +// Design Name: +// Module Name: Writeback_State +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Writeback_State(MR_dout2, MR_alu_result, MR_ir, MR_PC_4, MR_rf_wr_sel, MR_regWrite); + + // Inputs from Memory register + input logic [31:0] MR_dout2, MR_alu_result, MR_ir, MR_PC_4; + input logic [1:0] MR_rf_wr_sel; + input logic MR_regWrite; + + // For now, assign CSR register to 0 + logic CSR_temp; + assign CSR_temp = 1'b0; + + // Wire for MUX Output + logic [31:0] MUX_OUT_TO_REG_FILE; + + // ----------------------------------- Register File MUX ----------------------------------------------- + Reg_file_MUX Reg_MUX (.ALU_OUT(MR_alu_result), .MEM_DOUT_2(MR_dout2), .CSR_RD(CSR_temp), .PC_OUT(MR_PC_4), + .RF_WR_SEL(MR_rf_wr_sel)); + + + // ----------------------------------- Register File Setup ----------------------------------------------- + + Register_File_HW_3 Reg_File (.WD(MUX_OUT_TO_REG_FILE), .wa(MR_ir[11:7]), .ENABLE(MR_regWrite)); + +endmodule