From 3d3b2a64d7903d443dc4ee0931a83534f2595935 Mon Sep 17 00:00:00 2001
From: SamuelM <84934037+MateaSamuel@users.noreply.github.com>
Date: Fri, 30 Aug 2024 23:36:13 +0300
Subject: [PATCH] Update info.md

---
 docs/info.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/info.md b/docs/info.md
index 1f6dbca..31115b7 100644
--- a/docs/info.md
+++ b/docs/info.md
@@ -9,7 +9,8 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-The documentation will be updated after the competiton has concluded.
+This design intend to be used like a PWM generator. It contains two 12-bit registers: one for duty cycle(duty_reg) respectively one for period(period_reg). When sel signal is set to "0" the duty_reg will be selected and when sel is "1" the period_reg is selected. If values for duty/period is set at the input, the value is written in the regs only after wr_en is set to "1". For duty cycle, will be used only 7 bits(from 0 to 6) the rest of the bits beeing 0 hardcoded.
+the value for period_rescan be set between 2-4095(on 12 bits).
 
 ## How to test