From d5acd42cb7cdaa5d0f2c5f739208eeeed395f491 Mon Sep 17 00:00:00 2001 From: Dmitry Sidorov Date: Wed, 6 Dec 2023 17:54:06 +0100 Subject: [PATCH] Update SPV_INTEL_long_composites tokens (#375) Signed-off-by: Sidorov, Dmitry --- include/spirv/unified1/spirv.bf | 3 ++- .../spirv/unified1/spirv.core.grammar.json | 22 ++++++++++++++----- include/spirv/unified1/spirv.cs | 3 ++- include/spirv/unified1/spirv.h | 4 +++- include/spirv/unified1/spirv.hpp | 4 +++- include/spirv/unified1/spirv.hpp11 | 4 +++- include/spirv/unified1/spirv.json | 3 ++- include/spirv/unified1/spirv.lua | 3 ++- include/spirv/unified1/spirv.py | 3 ++- include/spirv/unified1/spv.d | 3 ++- 10 files changed, 38 insertions(+), 14 deletions(-) diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf index a4ce964c6..9193fe311 100644 --- a/include/spirv/unified1/spirv.bf +++ b/include/spirv/unified1/spirv.bf @@ -1197,7 +1197,7 @@ namespace Spv GroupNonUniformRotateKHR = 6026, AtomicFloat32AddEXT = 6033, AtomicFloat64AddEXT = 6034, - LongConstantCompositeINTEL = 6089, + LongCompositesINTEL = 6089, OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, @@ -2094,6 +2094,7 @@ namespace Spv OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpCompositeConstructContinuedINTEL = 6096, OpConvertFToBF16INTEL = 6116, OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json index 4dc955ef5..2aa05329f 100644 --- a/include/spirv/unified1/spirv.core.grammar.json +++ b/include/spirv/unified1/spirv.core.grammar.json @@ -9564,7 +9564,7 @@ "operands" : [ { "kind" : "IdRef", "quantifier" : "*", "name" : "'Member 0 type', +\n'member 1 type', +\n..." } ], - "capabilities" : [ "LongConstantCompositeINTEL" ], + "capabilities" : [ "LongCompositesINTEL" ], "version" : "None" }, { @@ -9574,7 +9574,7 @@ "operands" : [ { "kind" : "IdRef", "quantifier" : "*", "name" : "'Constituents'" } ], - "capabilities" : [ "LongConstantCompositeINTEL" ], + "capabilities" : [ "LongCompositesINTEL" ], "version" : "None" }, { @@ -9584,9 +9584,21 @@ "operands" : [ { "kind" : "IdRef", "quantifier" : "*", "name" : "'Constituents'" } ], - "capabilities" : [ "LongConstantCompositeINTEL" ], + "capabilities" : [ "LongCompositesINTEL" ], "version" : "None" }, + { + "opname" : "OpCompositeConstructContinuedINTEL", + "class" : "Composite", + "opcode" : 6096, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "quantifier" : "*", "name" : "'Constituents'" } + ], + "capabilities" : [ "LongCompositesINTEL" ], + "version": "None" + }, { "opname" : "OpConvertFToBF16INTEL", "class" : "Conversion", @@ -16224,9 +16236,9 @@ "version" : "None" }, { - "enumerant" : "LongConstantCompositeINTEL", + "enumerant" : "LongCompositesINTEL", "value" : 6089, - "extensions" : [ "SPV_INTEL_long_constant_composite" ], + "extensions" : [ "SPV_INTEL_long_composites" ], "version" : "None" }, { diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs index 446562826..1d0d6e95a 100644 --- a/include/spirv/unified1/spirv.cs +++ b/include/spirv/unified1/spirv.cs @@ -1196,7 +1196,7 @@ public enum Capability GroupNonUniformRotateKHR = 6026, AtomicFloat32AddEXT = 6033, AtomicFloat64AddEXT = 6034, - LongConstantCompositeINTEL = 6089, + LongCompositesINTEL = 6089, OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, @@ -2093,6 +2093,7 @@ public enum Op OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpCompositeConstructContinuedINTEL = 6096, OpConvertFToBF16INTEL = 6116, OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h index a1718715d..684999df8 100644 --- a/include/spirv/unified1/spirv.h +++ b/include/spirv/unified1/spirv.h @@ -1196,7 +1196,7 @@ typedef enum SpvCapability_ { SpvCapabilityGroupNonUniformRotateKHR = 6026, SpvCapabilityAtomicFloat32AddEXT = 6033, SpvCapabilityAtomicFloat64AddEXT = 6034, - SpvCapabilityLongConstantCompositeINTEL = 6089, + SpvCapabilityLongCompositesINTEL = 6089, SpvCapabilityOptNoneINTEL = 6094, SpvCapabilityAtomicFloat16AddEXT = 6095, SpvCapabilityDebugInfoModuleINTEL = 6114, @@ -2090,6 +2090,7 @@ typedef enum SpvOp_ { SpvOpTypeStructContinuedINTEL = 6090, SpvOpConstantCompositeContinuedINTEL = 6091, SpvOpSpecConstantCompositeContinuedINTEL = 6092, + SpvOpCompositeConstructContinuedINTEL = 6096, SpvOpConvertFToBF16INTEL = 6116, SpvOpConvertBF16ToFINTEL = 6117, SpvOpControlBarrierArriveINTEL = 6142, @@ -2813,6 +2814,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp index 5507f47b8..e85f942dc 100644 --- a/include/spirv/unified1/spirv.hpp +++ b/include/spirv/unified1/spirv.hpp @@ -1192,7 +1192,7 @@ enum Capability { CapabilityGroupNonUniformRotateKHR = 6026, CapabilityAtomicFloat32AddEXT = 6033, CapabilityAtomicFloat64AddEXT = 6034, - CapabilityLongConstantCompositeINTEL = 6089, + CapabilityLongCompositesINTEL = 6089, CapabilityOptNoneINTEL = 6094, CapabilityAtomicFloat16AddEXT = 6095, CapabilityDebugInfoModuleINTEL = 6114, @@ -2086,6 +2086,7 @@ enum Op { OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpCompositeConstructContinuedINTEL = 6096, OpConvertFToBF16INTEL = 6116, OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, @@ -2809,6 +2810,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case OpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break; case OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 index e49e491e3..2a52ddf15 100644 --- a/include/spirv/unified1/spirv.hpp11 +++ b/include/spirv/unified1/spirv.hpp11 @@ -1192,7 +1192,7 @@ enum class Capability : unsigned { GroupNonUniformRotateKHR = 6026, AtomicFloat32AddEXT = 6033, AtomicFloat64AddEXT = 6034, - LongConstantCompositeINTEL = 6089, + LongCompositesINTEL = 6089, OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, @@ -2086,6 +2086,7 @@ enum class Op : unsigned { OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpCompositeConstructContinuedINTEL = 6096, OpConvertFToBF16INTEL = 6116, OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, @@ -2809,6 +2810,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json index f1ad055aa..660d6f359 100644 --- a/include/spirv/unified1/spirv.json +++ b/include/spirv/unified1/spirv.json @@ -1172,7 +1172,7 @@ "GroupNonUniformRotateKHR": 6026, "AtomicFloat32AddEXT": 6033, "AtomicFloat64AddEXT": 6034, - "LongConstantCompositeINTEL": 6089, + "LongCompositesINTEL": 6089, "OptNoneINTEL": 6094, "AtomicFloat16AddEXT": 6095, "DebugInfoModuleINTEL": 6114, @@ -2088,6 +2088,7 @@ "OpTypeStructContinuedINTEL": 6090, "OpConstantCompositeContinuedINTEL": 6091, "OpSpecConstantCompositeContinuedINTEL": 6092, + "OpCompositeConstructContinuedINTEL": 6096, "OpConvertFToBF16INTEL": 6116, "OpConvertBF16ToFINTEL": 6117, "OpControlBarrierArriveINTEL": 6142, diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua index d4ca2fa98..69c3d65f3 100644 --- a/include/spirv/unified1/spirv.lua +++ b/include/spirv/unified1/spirv.lua @@ -1154,7 +1154,7 @@ spv = { GroupNonUniformRotateKHR = 6026, AtomicFloat32AddEXT = 6033, AtomicFloat64AddEXT = 6034, - LongConstantCompositeINTEL = 6089, + LongCompositesINTEL = 6089, OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, @@ -2030,6 +2030,7 @@ spv = { OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpCompositeConstructContinuedINTEL = 6096, OpConvertFToBF16INTEL = 6116, OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py index c842bbfd1..179e9b27b 100644 --- a/include/spirv/unified1/spirv.py +++ b/include/spirv/unified1/spirv.py @@ -1154,7 +1154,7 @@ 'GroupNonUniformRotateKHR' : 6026, 'AtomicFloat32AddEXT' : 6033, 'AtomicFloat64AddEXT' : 6034, - 'LongConstantCompositeINTEL' : 6089, + 'LongCompositesINTEL' : 6089, 'OptNoneINTEL' : 6094, 'AtomicFloat16AddEXT' : 6095, 'DebugInfoModuleINTEL' : 6114, @@ -2030,6 +2030,7 @@ 'OpTypeStructContinuedINTEL' : 6090, 'OpConstantCompositeContinuedINTEL' : 6091, 'OpSpecConstantCompositeContinuedINTEL' : 6092, + 'OpCompositeConstructContinuedINTEL' : 6096, 'OpConvertFToBF16INTEL' : 6116, 'OpConvertBF16ToFINTEL' : 6117, 'OpControlBarrierArriveINTEL' : 6142, diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d index 238caacbd..b570d6e28 100644 --- a/include/spirv/unified1/spv.d +++ b/include/spirv/unified1/spv.d @@ -1199,7 +1199,7 @@ enum Capability : uint GroupNonUniformRotateKHR = 6026, AtomicFloat32AddEXT = 6033, AtomicFloat64AddEXT = 6034, - LongConstantCompositeINTEL = 6089, + LongCompositesINTEL = 6089, OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, @@ -2096,6 +2096,7 @@ enum Op : uint OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpCompositeConstructContinuedINTEL = 6096, OpConvertFToBF16INTEL = 6116, OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142,