load-switch.stanza

#use-added-syntax(jitx)
defpackage load-switch :
  import core
  import collections
  import math
  import jitx
  import jitx/commands
  import ocdb/utils/defaults
  import ocdb/utils/generic-components
  import ocdb/utils/generator-utils
  import ocdb/utils/checks
  ; import ocdb/utils/bundles

  import ocdb/utils/property-structs

  import jsl/bundles

; Generated by GPT4 (then corrected). RDS ON ~= 5ohms @600ma
; Normally off design for minimal leakage.
; High-side power switch configuration. 
public pcb-module high-side-mosfet-switch (PFET:InstantiableType) :
  ; Active High Enable with respect to 
  port control
  ; I'm using the 'power' bundle here to make it easier 
  ;   to connect the input and output rails.
  ;   Note that this isn't an isolated two power design.
  port vin : power
  port vout : power

  net gnd (vin.V- vout.V-)

  ; Declare the components
  ; Power Switch MOSFET as a PMOS switch
  ; 
  inst Psw : PFET
  inst Nctl : components/Changjiang-Electronics-Tech--CJ-/BSS138/component ; database-part(["mpn" => "BSS138", "manufacturer" => "Changjiang Electronics Tech (CJ)"])
  ; Gate voltage as function of drain current
  property(Nctl.VGID) = PWL([[0.0 0.0] [1.0e-6 1.0] [0.08 2.0] [0.4 3.0] [1.0 4.0]])

  ; Connect the P-channel MOSFET
  net (Psw.S, vin.V+)
  net (Psw.D, vout.V+)

  ; Connect the N-channel MOSFET
  net (Nctl.D, Psw.G)
  net (Nctl.S, gnd)
  net (Nctl.G, control)

  ; Connect the pull-up resistor between the power pin and the P-channel MOSFET gate
  ;   This will make sure that the VDDA power domain is OFF by default.
  res-strap(vin.V+, Psw.G, ["resistance" => min-max(900.0e3, 1.5e6), "tolerance" => 0.05])

  ; Add a bit of ESD protection to the Source by adding a capacitor.
  ;  In a more industrial application we might add a MOV or TVS here. 
  bypass-cap-strap(Psw.S, vin.V-, min-max(0.1e-6, 1.0e-6), 0.20)

  eval-when has-property?(Psw.S.voltage) :
    val vdd = property(Psw.S.voltage) 
    ; TODO Look at SPICE computations for this threshold voltage
    property(Nctl.G.digital-input) = DigitalInput(typ(0.5), vdd - property(Psw.Vgs-th), vin.V+, vin.V-, 10.0e-9)

  schematic-group(self) = load-sw
  layout-group(self) = load-sw