From 8053a18f99d808884c7d877aecf8d11064027d1c Mon Sep 17 00:00:00 2001 From: Manikandan Nair Date: Mon, 30 Dec 2024 13:07:14 +0000 Subject: [PATCH] Base commit --- ADC.Opt | 52 + ADC.Uv2 | 107 ++ ADC.axf | Bin 0 -> 33412 bytes ADC.hex | 517 ++++++++ ADC.htm | 643 +++++++++ ADC.lnp | 5 + ADC.map | 841 ++++++++++++ ADC.plg | 102 ++ ADC.sct | 15 + ADC.tra | 26 + ADC_Opt.Bak | 53 + ADC_Target 1.dep | 24 + ADC_Uv2.Bak | 108 ++ Abstract.txt | 27 + Blinky.Opt | 72 ++ ExtDll.iex | 2 + IRQ.c | 22 + LCD.h | 19 + LCD_4bit.c | 308 +++++ LPC2300.d | 1 + LPC2300.lst | 2805 ++++++++++++++++++++++++++++++++++++++++ LPC2300.o | Bin 0 -> 2960 bytes LPC2300.s | 885 +++++++++++++ PN532_SPI.cpp | 210 +++ RFID_PN532.c | 251 ++++ RTC.c | 79 ++ Retarget.c | 42 + Serial.c | 65 + Servo_MG995.c | 42 + Sim.ini | 135 ++ Ultrasonic_HC_SR04.c | 110 ++ irq.crf | Bin 0 -> 29646 bytes irq.d | 2 + irq.o | Bin 0 -> 67580 bytes lcd_4bit.crf | Bin 0 -> 35755 bytes lcd_4bit.d | 3 + lcd_4bit.o | Bin 0 -> 74024 bytes main.c | 96 ++ main.crf | Bin 0 -> 35156 bytes main.d | 4 + main.o | Bin 0 -> 71568 bytes mg995_servo.__i | 5 + mg995_servo.d | 0 rfid_pn532.crf | Bin 0 -> 39494 bytes rfid_pn532.d | 5 + rfid_pn532.o | Bin 0 -> 75568 bytes rtc.crf | Bin 0 -> 34634 bytes rtc.d | 4 + rtc.o | Bin 0 -> 72088 bytes servo_mg995.crf | Bin 0 -> 38322 bytes servo_mg995.d | 5 + servo_mg995.o | Bin 0 -> 72844 bytes ultrasonic_hc_sr04.crf | Bin 0 -> 35184 bytes ultrasonic_hc_sr04.d | 4 + ultrasonic_hc_sr04.o | Bin 0 -> 74172 bytes 55 files changed, 7696 insertions(+) create mode 100644 ADC.Opt create mode 100644 ADC.Uv2 create mode 100644 ADC.axf create mode 100644 ADC.hex create mode 100644 ADC.htm create mode 100644 ADC.lnp create mode 100644 ADC.map create mode 100644 ADC.plg create mode 100644 ADC.sct create mode 100644 ADC.tra create mode 100644 ADC_Opt.Bak create mode 100644 ADC_Target 1.dep create mode 100644 ADC_Uv2.Bak create mode 100644 Abstract.txt create mode 100644 Blinky.Opt create mode 100644 ExtDll.iex create mode 100644 IRQ.c create mode 100644 LCD.h create mode 100644 LCD_4bit.c create mode 100644 LPC2300.d create mode 100644 LPC2300.lst create mode 100644 LPC2300.o create mode 100644 LPC2300.s create mode 100644 PN532_SPI.cpp create mode 100644 RFID_PN532.c create mode 100644 RTC.c create mode 100644 Retarget.c create mode 100644 Serial.c create mode 100644 Servo_MG995.c create mode 100644 Sim.ini create mode 100644 Ultrasonic_HC_SR04.c create mode 100644 irq.crf create mode 100644 irq.d create mode 100644 irq.o create mode 100644 lcd_4bit.crf create mode 100644 lcd_4bit.d create mode 100644 lcd_4bit.o create mode 100644 main.c create mode 100644 main.crf create mode 100644 main.d create mode 100644 main.o create mode 100644 mg995_servo.__i create mode 100644 mg995_servo.d create mode 100644 rfid_pn532.crf create mode 100644 rfid_pn532.d create mode 100644 rfid_pn532.o create mode 100644 rtc.crf create mode 100644 rtc.d create mode 100644 rtc.o create mode 100644 servo_mg995.crf create mode 100644 servo_mg995.d create mode 100644 servo_mg995.o create mode 100644 ultrasonic_hc_sr04.crf create mode 100644 ultrasonic_hc_sr04.d create mode 100644 ultrasonic_hc_sr04.o diff --git a/ADC.Opt b/ADC.Opt new file mode 100644 index 0000000..b8cd864 --- /dev/null +++ b/ADC.Opt @@ -0,0 +1,52 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (Target 1), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Source Group 1),1,0,0 +GRPOPT 2,(System Calls),1,0,0 + +OPTFFF 1,1,1,285212673,0,10,6,0,<.\Servo_MG995.c> +OPTFFF 1,2,1,1,0,1,1,0,<.\LCD_4bit.c> +OPTFFF 1,3,1,301989889,0,0,0,0,<.\IRQ.c> +OPTFFF 1,4,1,385875969,0,40,16,0,<.\RTC.c> +OPTFFF 1,5,1,838860801,0,70,107,0,<.\Ultrasonic_HC_SR04.c> +OPTFFF 1,6,1,436207616,0,64,77,0,<.\main.c> +OPTFFF 2,7,2,738197504,0,0,0,0,<.\LPC2300.s> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,22,0,0,0,29,0,0,0,247,2,0,0,60,1,0,0 } + + +TARGOPT 1, (Target 1) + ADSCLK=12000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTAX 8 + OPTBL 0,(Data Sheet) + OPTBL 1,(User Manual) + OPTDL (SARM.DLL)(-cLPC237x)(DARMP.DLL)(-pLPC2378)(SARM.DLL)()(TARMP.DLL)(-pLPC2378) + OPTDBG 180222,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() + OPTKEY 0,(DLGDARM)((135=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(145=-1,-1,-1,-1,0)(147=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(155=-1,-1,-1,-1,0)(177=-1,-1,-1,-1,0)(134=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(156=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(176=-1,-1,-1,-1,0)(178=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(169=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(137=-1,-1,-1,-1,0)(138=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(165=-1,-1,-1,-1,0)(166=-1,-1,-1,-1,0)(168=-1,-1,-1,-1,0)(141=191,61,623,629,0)(144=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) + OPTKEY 0,(DLGTARM)((135=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(145=-1,-1,-1,-1,0)(147=-1,-1,-1,-1,0)(150=83,115,386,293,0)(152=90,124,444,426,0)(151=98,132,350,574,0)(155=-1,-1,-1,-1,0)(177=-1,-1,-1,-1,0)(134=75,107,270,293,0)(80=-1,-1,-1,-1,0)(156=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(176=-1,-1,-1,-1,0)(178=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(169=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(137=-1,-1,-1,-1,0)(138=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(165=-1,-1,-1,-1,0)(166=-1,-1,-1,-1,0)(168=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(144=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)(-T5F) + OPTKEY 0,(UL2ARM)(-UV0812UAE -O39 -S2 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07D000) + OPTWA 0,1,(AD_last,0x10) + OPTWA 0,2,(A_value,0x0A) + OPTMM 1,262,(0xE0034010) + OPTDF 0x1000086 + OPTLE <> + OPTLC <> + OPTLA 0,(((PORT1 & 0x00040000) >> 18 & 0x40000) >> 18)(FF00000000000000000000000000E0FFFFFFEF410100000000000000000000000000000028504F5254312026203078303030343030303029203E3E2031380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F120000000000000000000000000000000000000010030000) +EndOpt + diff --git a/ADC.Uv2 b/ADC.Uv2 new file mode 100644 index 0000000..b72fc23 --- /dev/null +++ b/ADC.Uv2 @@ -0,0 +1,107 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (Target 1), 0x0004 // Tools: 'ARM-ADS' + +Group (Source Group 1) +Group (System Calls) + +File 1,1,<.\Servo_MG995.c> +File 1,1,<.\LCD_4bit.c> +File 1,1,<.\IRQ.c> +File 1,1,<.\RTC.c> +File 1,1,<.\Ultrasonic_HC_SR04.c> +File 1,1,<.\main.c> +File 2,2,<.\LPC2300.s> + + +Options 1,0,0 // Target 'Target 1' + Device (LPC2378) + Vendor (NXP (founded by Philips)) + Cpu (IRAM(0x40000000-0x40007FFF) IRAM2(0x7FE00000-0x7FE03FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI)) + FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 38400 1)) + StupF ("STARTUP\Philips\LPC2300.s" ("Philips LPC2300 Startup Code")) + FlashDR (UL2ARM(-U268761108 -O7 -S0 -C0 -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07D000)) + DevID (4153) + Rgf (LPC23xx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (˙Philips\) + OrgReg (˙Philips\) + TgStat=16 + OutDir (.\) + OutName (ADC) + GenApp=1 + GenLib=0 + GenHex=1 + Debug=1 + Browse=1 + LstDir (.\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + CrunUsr 0 0 <> + CrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP (ARM7TDMI) + RVDEV () + ADSTFLGA { 0,12,16,18,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,64,0,128,0,0 } + OCMADSIROM { 1,0,0,0,0,0,0,8,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,128,0,0,0,0,0,224,127,0,64,0,0 } + RV_STAVEC () + ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN () + ADSCUDEF () + ADSCINCD () + ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x00000000) + ADSLDDA (0x40000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC () + ADSLDIF () + ADSLDDW () + OPTDL (SARM.DLL)(-cLPC237x)(DARMP.DLL)(-pLPC2378)(SARM.DLL)()(TARMP.DLL)(-pLPC2378) + OPTDBG 180222,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() + FLASH1 { 9,0,0,0,1,0,0,0,0,16,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\UL2ARM.DLL) + FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 38400 1)) + FLASH4 () +EndOpt + diff --git a/ADC.axf b/ADC.axf new file mode 100644 index 0000000000000000000000000000000000000000..6c4fb578ff64419504890378a6326bd0a10025aa GIT binary patch literal 33412 zcmdUY4SZD9nfEz!=gv&N$m9bULcp64U=WBCq>73%lOcgfkQf5SN;`yPLPjUam`pHK zD}hC8yS66E+5~Bht=p=#Z)q2|ZcBGTaYbwUP88o-pzVZ^#Z|kFtroP_y#MFiduDEi z&~>}DzhAH1ob!L4=RD^*=RD`*-gEA_qoTT!bI#;tVQxlfk%h6-I~cR}FovkQlxd*5 znUiHR*Vx0OsW)ST!`j;y33@%!dvUMCy&88lZn|o4*WvzfeEf~c?tT2>(I=dPBOA2A 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zOyDJ^l_Xy*a-{j;&L|dL75E&WcHP=CR(k^?K152z92#iYvZW)qO`_(G2K?Tc!J>7K zjECuGKnyy5N=HUp8yd}0k*+OmP=MFdScXL#wjhjlh_J0aiuCltnO;?tcD5J{m_~aM z*h5HM^jrUn=Hjp-$9=hd`1JWt?Vn_$AN9m%y3X(I90(p)9w*axkWtOA- zNsjh7sx|DzU@uu-(l$DdL;B=Jaz{*Zl2-%)87EoiJnSt=B_hJp`D@ zEK-ZTRO}tnGr_;&rh3L+m-u4KbS#S<+KN4H>?6rb=G6m&>9_KJFUh+P1arQtcj#XSq{{t&j + +Static Call Graph - [C:\Users\Lenovo\Documents\Keil uVision4\PetFeeder\ADC.axf] +
+

Static Call Graph for image C:\Users\Lenovo\Documents\Keil uVision4\PetFeeder\ADC.axf

+

#<CALLGRAPH># ARM Linker, 5.03 [Build 69]: Last Updated: Fri Dec 13 11:46:53 2024 +

+

Maximum Stack Usage = 188 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+main ⇒ calDistance ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ _double_round +

+

+Functions with no stack information +

+ +

+

+Mutually Recursive functions +

  • Undef_Handler   ⇒   Undef_Handler
    +
  • SWI_Handler   ⇒   SWI_Handler
    +
  • PAbt_Handler   ⇒   PAbt_Handler
    +
  • DAbt_Handler   ⇒   DAbt_Handler
    +
  • IRQ_Handler   ⇒   IRQ_Handler
    +
  • FIQ_Handler   ⇒   FIQ_Handler
    + +

    +

    +Function Pointers +

      +
    • DAbt_Handler from lpc2300.o(RESET) referenced from lpc2300.o(RESET) +
    • FIQ_Handler from lpc2300.o(RESET) referenced from lpc2300.o(RESET) +
    • IRQ_Handler from lpc2300.o(RESET) referenced from lpc2300.o(RESET) +
    • PAbt_Handler from lpc2300.o(RESET) referenced from lpc2300.o(RESET) +
    • Reset_Handler from lpc2300.o(RESET) referenced from lpc2300.o(RESET) +
    • SWI_Handler from lpc2300.o(RESET) referenced from lpc2300.o(RESET) +
    • T0_IRQHandler from irq.o(.text) referenced from rtc.o(.text) +
    • Undef_Handler from lpc2300.o(RESET) referenced from lpc2300.o(RESET) +
    • __main from entry.o(.ARM.Collect$$$$00000000) referenced from lpc2300.o(RESET) +
    • _sputc from printfa.o(i._sputc) referenced from printfa.o(i.__0sprintf) +
    • main from main.o(.text) referenced from entry9a.o(.ARM.Collect$$$$0000000B) +
    +

    +

    +Global Symbols +

    +

    Reset_Handler (ARM, 0 bytes, Stack size unknown bytes, lpc2300.o(RESET)) +
    [Address Reference Count : 1]

    • lpc2300.o(RESET) +
    +

    __main (ARM, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000)) + +

    _main_stk (ARM, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) + +

    _main_scatterload (ARM, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Calls]

    • >>   __scatterload (via Veneer) +
    + +

    __main_after_scatterload (ARM, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Called By]

    • >>   __scatterload (via Veneer) +
    + +

    _main_clock (ARM, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008)) + +

    _main_cpp_init (ARM, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A)) + +

    _main_init (ARM, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B)) + +

    __rt_final_cpp (ARM, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D)) + +

    __rt_final_exit (ARM, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F)) + +

    PWM_Init (ARM, 60 bytes, Stack size 0 bytes, servo_mg995.o(.text)) +

    [Called By]

    • >>   main +
    • >>   trial_run_servo +
    + +

    WaitTime (ARM, 56 bytes, Stack size 0 bytes, servo_mg995.o(.text), UNUSED) + +

    PWM_SetDutyCycle (ARM, 52 bytes, Stack size 8 bytes, servo_mg995.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = PWM_SetDutyCycle ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod (via Veneer) +
    +
    [Called By]
    • >>   main +
    • >>   trial_run_servo +
    + +

    trial_run_servo (ARM, 28 bytes, Stack size 0 bytes, servo_mg995.o(.text), UNUSED) +

    [Calls]

    • >>   lcd_init +
    • >>   lcd_clear +
    • >>   PWM_SetDutyCycle +
    • >>   PWM_Init +
    + +

    lcd_write_4bit (ARM, 84 bytes, Stack size 8 bytes, lcd_4bit.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = lcd_write_4bit +
    +
    [Calls]
    • >>   delay +
    +
    [Called By]
    • >>   lcd_write_cmd +
    • >>   lcd_write_data +
    • >>   lcd_init +
    + +

    lcd_write_cmd (ARM, 48 bytes, Stack size 8 bytes, lcd_4bit.o(.text)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = lcd_write_cmd ⇒ wait_while_busy ⇒ lcd_read_status +
    +
    [Calls]
    • >>   lcd_write_4bit +
    • >>   wait_while_busy +
    +
    [Called By]
    • >>   set_cursor +
    • >>   lcd_init +
    • >>   lcd_clear +
    + +

    lcd_putchar (ARM, 24 bytes, Stack size 8 bytes, lcd_4bit.o(.text)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = lcd_putchar ⇒ lcd_write_data ⇒ wait_while_busy ⇒ lcd_read_status +
    +
    [Calls]
    • >>   lcd_write_data +
    +
    [Called By]
    • >>   updateRTCTimer +
    • >>   lcd_print +
    • >>   lcd_init +
    + +

    lcd_init (ARM, 176 bytes, Stack size 16 bytes, lcd_4bit.o(.text)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = lcd_init ⇒ lcd_putchar ⇒ lcd_write_data ⇒ wait_while_busy ⇒ lcd_read_status +
    +
    [Calls]
    • >>   lcd_putchar +
    • >>   lcd_write_cmd +
    • >>   lcd_write_4bit +
    • >>   delay +
    +
    [Called By]
    • >>   main +
    • >>   setupTimer +
    • >>   trial_run_rtc +
    • >>   trial_run_servo +
    + +

    set_cursor (ARM, 52 bytes, Stack size 16 bytes, lcd_4bit.o(.text)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = set_cursor ⇒ lcd_write_cmd ⇒ wait_while_busy ⇒ lcd_read_status +
    +
    [Calls]
    • >>   lcd_write_cmd +
    +
    [Called By]
    • >>   main +
    • >>   trial_run_ultrasonic +
    • >>   trial_run_rtc +
    • >>   updateRTCTimer +
    • >>   lcd_clear +
    + +

    lcd_clear (ARM, 32 bytes, Stack size 8 bytes, lcd_4bit.o(.text)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = lcd_clear ⇒ set_cursor ⇒ lcd_write_cmd ⇒ wait_while_busy ⇒ lcd_read_status +
    +
    [Calls]
    • >>   set_cursor +
    • >>   lcd_write_cmd +
    +
    [Called By]
    • >>   main +
    • >>   trial_run_ultrasonic +
    • >>   setupTimer +
    • >>   trial_run_rtc +
    • >>   trial_run_servo +
    + +

    lcd_print (ARM, 40 bytes, Stack size 8 bytes, lcd_4bit.o(.text)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = lcd_print ⇒ lcd_putchar ⇒ lcd_write_data ⇒ wait_while_busy ⇒ lcd_read_status +
    +
    [Calls]
    • >>   lcd_putchar +
    +
    [Called By]
    • >>   main +
    • >>   trial_run_ultrasonic +
    • >>   trial_run_rtc +
    • >>   updateRTCTimer +
    + +

    T0_IRQHandler (ARM, 88 bytes, Stack size 8 bytes, irq.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = T0_IRQHandler +
    +
    [Address Reference Count : 1]
    • rtc.o(.text) +
    +

    RTCTimerEnable (ARM, 60 bytes, Stack size 0 bytes, rtc.o(.text)) +

    [Called By]

    • >>   main +
    • >>   trial_run_rtc +
    + +

    updateRTCTimer (ARM, 524 bytes, Stack size 8 bytes, rtc.o(.text)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = updateRTCTimer ⇒ lcd_print ⇒ lcd_putchar ⇒ lcd_write_data ⇒ wait_while_busy ⇒ lcd_read_status +
    +
    [Calls]
    • >>   __2sprintf (via Veneer) +
    • >>   lcd_print +
    • >>   set_cursor +
    • >>   lcd_putchar +
    +
    [Called By]
    • >>   main +
    • >>   trial_run_rtc +
    + +

    trial_run_rtc (ARM, 44 bytes, Stack size 0 bytes, rtc.o(.text), UNUSED) +

    [Calls]

    • >>   updateRTCTimer +
    • >>   RTCTimerEnable +
    • >>   lcd_print +
    • >>   set_cursor +
    • >>   lcd_init +
    • >>   lcd_clear +
    + +

    delayUS (ARM, 56 bytes, Stack size 0 bytes, ultrasonic_hc_sr04.o(.text)) +

    [Called By]

    • >>   sendPulse +
    • >>   delayMS +
    + +

    initTimer0 (ARM, 52 bytes, Stack size 0 bytes, ultrasonic_hc_sr04.o(.text)) +

    [Called By]

    • >>   setupTimer +
    + +

    startTimer0 (ARM, 24 bytes, Stack size 0 bytes, ultrasonic_hc_sr04.o(.text)) +

    [Called By]

    • >>   calDistance +
    + +

    stopTimer0 (ARM, 24 bytes, Stack size 0 bytes, ultrasonic_hc_sr04.o(.text)) +

    [Called By]

    • >>   calDistance +
    + +

    delayMS (ARM, 28 bytes, Stack size 4 bytes, ultrasonic_hc_sr04.o(.text)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = delayMS +
    +
    [Calls]
    • >>   delayUS +
    +
    [Called By]
    • >>   main +
    • >>   trial_run_ultrasonic +
    + +

    setPins (ARM, 76 bytes, Stack size 0 bytes, ultrasonic_hc_sr04.o(.text)) +

    [Called By]

    • >>   setupTimer +
    + +

    setupTimer (ARM, 44 bytes, Stack size 16 bytes, ultrasonic_hc_sr04.o(.text)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = setupTimer ⇒ lcd_init ⇒ lcd_putchar ⇒ lcd_write_data ⇒ wait_while_busy ⇒ lcd_read_status +
    +
    [Calls]
    • >>   setPins +
    • >>   initTimer0 +
    • >>   lcd_init +
    • >>   lcd_clear +
    +
    [Called By]
    • >>   main +
    • >>   trial_run_ultrasonic +
    + +

    calDistance (ARM, 160 bytes, Stack size 32 bytes, ultrasonic_hc_sr04.o(.text)) +

    [Stack]

    • Max Depth = 156
    • Call Chain = calDistance ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ _double_round +
    +
    [Calls]
    • >>   __aeabi_i2d (via Veneer) +
    • >>   __aeabi_dmul (via Veneer) +
    • >>   __aeabi_ddiv (via Veneer) +
    • >>   __aeabi_d2f (via Veneer) +
    • >>   stopTimer0 +
    • >>   startTimer0 +
    +
    [Called By]
    • >>   main +
    • >>   trial_run_ultrasonic +
    + +

    sendPulse (ARM, 72 bytes, Stack size 4 bytes, ultrasonic_hc_sr04.o(.text)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = sendPulse +
    +
    [Calls]
    • >>   delayUS +
    +
    [Called By]
    • >>   main +
    • >>   trial_run_ultrasonic +
    + +

    trial_run_ultrasonic (ARM, 240 bytes, Stack size 0 bytes, ultrasonic_hc_sr04.o(.text), UNUSED) +

    [Calls]

    • >>   __2sprintf (via Veneer) +
    • >>   __aeabi_f2d (via Veneer) +
    • >>   __aeabi_cfcmple (via Veneer) +
    • >>   sendPulse +
    • >>   calDistance +
    • >>   setupTimer +
    • >>   delayMS +
    • >>   lcd_print +
    • >>   set_cursor +
    • >>   lcd_clear +
    + +

    main (ARM, 540 bytes, Stack size 32 bytes, main.o(.text)) +

    [Stack]

    • Max Depth = 188
    • Call Chain = main ⇒ calDistance ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ _double_round +
    +
    [Calls]
    • >>   __2sprintf (via Veneer) +
    • >>   __aeabi_idivmod (via Veneer) +
    • >>   __aeabi_f2d (via Veneer) +
    • >>   __aeabi_cfcmple (via Veneer) +
    • >>   sendPulse +
    • >>   calDistance +
    • >>   setupTimer +
    • >>   delayMS +
    • >>   updateRTCTimer +
    • >>   RTCTimerEnable +
    • >>   lcd_print +
    • >>   set_cursor +
    • >>   lcd_init +
    • >>   lcd_clear +
    • >>   PWM_SetDutyCycle +
    • >>   PWM_Init +
    +
    [Address Reference Count : 1]
    • entry9a.o(.ARM.Collect$$$$0000000B) +
    +

    __aeabi_uidiv (Thumb, 0 bytes, Stack size 8 bytes, uidiv.o(.text), UNUSED) + +

    __aeabi_uidivmod (Thumb, 46 bytes, Stack size 8 bytes, uidiv.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_uidivmod +
    +
    [Called By]
    • >>   _printf_core +
    • >>   __aeabi_idivmod +
    • >>   PWM_SetDutyCycle (via Veneer) +
    + +

    __aeabi_idiv (Thumb, 0 bytes, Stack size 16 bytes, idiv.o(.text), UNUSED) + +

    __aeabi_idivmod (Thumb, 44 bytes, Stack size 16 bytes, idiv.o(.text)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = __aeabi_idivmod ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   main (via Veneer) +
    + +

    __aeabi_dmul (Thumb, 206 bytes, Stack size 72 bytes, dmul.o(.text)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = __aeabi_dmul ⇒ _double_epilogue ⇒ _double_round +
    +
    [Calls]
    • >>   _double_epilogue +
    +
    [Called By]
    • >>   _fp_digits +
    • >>   calDistance (via Veneer) +
    + +

    __aeabi_ddiv (Thumb, 238 bytes, Stack size 40 bytes, ddiv.o(.text)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = __aeabi_ddiv ⇒ _double_round +
    +
    [Calls]
    • >>   _double_round +
    +
    [Called By]
    • >>   _fp_digits +
    • >>   calDistance (via Veneer) +
    + +

    __aeabi_i2d (Thumb, 36 bytes, Stack size 16 bytes, dflti.o(.text)) +

    [Stack]

    • Max Depth = 68
    • Call Chain = __aeabi_i2d ⇒ _double_epilogue ⇒ _double_round +
    +
    [Calls]
    • >>   _double_epilogue +
    +
    [Called By]
    • >>   calDistance (via Veneer) +
    + +

    __aeabi_f2d (Thumb, 40 bytes, Stack size 0 bytes, f2d.o(.text)) +

    [Called By]

    • >>   main (via Veneer) +
    • >>   trial_run_ultrasonic (via Veneer) +
    + +

    __aeabi_d2f (Thumb, 60 bytes, Stack size 8 bytes, d2f.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_d2f +
    +
    [Calls]
    • >>   _float_round +
    +
    [Called By]
    • >>   calDistance (via Veneer) +
    + +

    __aeabi_cfcmpeq (Thumb, 0 bytes, Stack size 0 bytes, cfcmple.o(.text), UNUSED) + +

    __aeabi_cfcmple (Thumb, 20 bytes, Stack size 0 bytes, cfcmple.o(.text)) +

    [Called By]

    • >>   main (via Veneer) +
    • >>   trial_run_ultrasonic (via Veneer) +
    + +

    __aeabi_uldivmod (Thumb, 104 bytes, Stack size 48 bytes, uldiv.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_llsr +
    • >>   __aeabi_llsl +
    +
    [Called By]
    • >>   _printf_core +
    • >>   _fp_digits +
    + +

    __I$use$fp (ARM, 0 bytes, Stack size 0 bytes, iusefp.o(.text), UNUSED) + +

    _float_round (Thumb, 16 bytes, Stack size 0 bytes, fepilogue.o(.text)) +

    [Called By]

    • >>   __aeabi_d2f +
    + +

    _float_epilogue (Thumb, 116 bytes, Stack size 12 bytes, fepilogue.o(.text), UNUSED) + +

    _double_round (Thumb, 28 bytes, Stack size 4 bytes, depilogue.o(.text)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = _double_round +
    +
    [Called By]
    • >>   _double_epilogue +
    • >>   __aeabi_dadd +
    • >>   __aeabi_ddiv +
    + +

    _double_epilogue (Thumb, 170 bytes, Stack size 48 bytes, depilogue.o(.text)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = _double_epilogue ⇒ _double_round +
    +
    [Calls]
    • >>   __ARM_clz +
    • >>   _double_round +
    • >>   __aeabi_llsr +
    • >>   __aeabi_llsl +
    +
    [Called By]
    • >>   __aeabi_dadd +
    • >>   __aeabi_i2d +
    • >>   __aeabi_dmul +
    + +

    __aeabi_dadd (Thumb, 330 bytes, Stack size 48 bytes, dadd.o(.text), UNUSED) +

    [Calls]

    • >>   _double_round +
    • >>   _double_epilogue +
    • >>   __aeabi_lasr +
    • >>   __aeabi_llsl +
    +
    [Called By]
    • >>   __aeabi_drsub +
    • >>   __aeabi_dsub +
    • >>   _fp_digits +
    + +

    __aeabi_dsub (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_dadd +
    + +

    __aeabi_drsub (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_dadd +
    + +

    __aeabi_d2ulz (Thumb, 58 bytes, Stack size 8 bytes, dfixul.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_llsr +
    • >>   __aeabi_llsl +
    +
    [Called By]
    • >>   _fp_digits +
    + +

    __aeabi_cdrcmple (Thumb, 40 bytes, Stack size 0 bytes, cdrcmple.o(.text), UNUSED) +

    [Called By]

    • >>   _fp_digits +
    + +

    __scatterload (Thumb, 24 bytes, Stack size 0 bytes, init.o(.text)) +

    [Calls]

    • >>   __main_after_scatterload (via Veneer) +
    • >>   __ARM_common_call_via_r3 +
    +
    [Called By]
    • >>   _main_scatterload (via Veneer) +
    + +

    __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED) + +

    __aeabi_llsl (Thumb, 34 bytes, Stack size 4 bytes, llshl.o(.text)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = __aeabi_llsl +
    +
    [Called By]
    • >>   __aeabi_uldivmod +
    • >>   _double_epilogue +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2ulz +
    + +

    _ll_shift_l (Thumb, 0 bytes, Stack size 4 bytes, llshl.o(.text), UNUSED) + +

    __aeabi_llsr (Thumb, 36 bytes, Stack size 4 bytes, llushr.o(.text)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = __aeabi_llsr +
    +
    [Called By]
    • >>   __aeabi_uldivmod +
    • >>   _double_epilogue +
    • >>   __aeabi_d2ulz +
    + +

    _ll_ushift_r (Thumb, 0 bytes, Stack size 4 bytes, llushr.o(.text), UNUSED) + +

    __aeabi_lasr (Thumb, 40 bytes, Stack size 4 bytes, llsshr.o(.text), UNUSED) +

    [Called By]

    • >>   __aeabi_dadd +
    + +

    _ll_sshift_r (Thumb, 0 bytes, Stack size 4 bytes, llsshr.o(.text), UNUSED) + +

    __0sprintf (Thumb, 36 bytes, Stack size 24 bytes, printfa.o(i.__0sprintf), UNUSED) +

    [Calls]

    • >>   _sputc +
    • >>   _printf_core +
    + +

    __1sprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0sprintf), UNUSED) + +

    __2sprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0sprintf)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = __2sprintf +
    +
    [Called By]
    • >>   main (via Veneer) +
    • >>   trial_run_ultrasonic (via Veneer) +
    • >>   updateRTCTimer (via Veneer) +
    + +

    __c89sprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0sprintf), UNUSED) + +

    sprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0sprintf), UNUSED) + +

    __ARM_clz (Thumb, 46 bytes, Stack size 0 bytes, depilogue.o(i.__ARM_clz)) +

    [Called By]

    • >>   _double_epilogue +
    + +

    __ARM_common_call_via_r2 (Thumb, 2 bytes, Stack size 0 bytes, printf1.o(i.__ARM_common_call_via_r2), UNUSED) +

    [Called By]

    • >>   _printf_core +
    + +

    __ARM_common_call_via_r3 (Thumb, 2 bytes, Stack size 0 bytes, init.o(i.__ARM_common_call_via_r3)) +

    [Called By]

    • >>   __scatterload +
    + +

    __ARM_common_call_via_r6 (Thumb, 2 bytes, Stack size 0 bytes, printfb.o(i.__ARM_common_call_via_r6), UNUSED) +

    [Called By]

    • >>   _printf_pre_padding +
    • >>   _printf_post_padding +
    + +

    __scatterload_copy (ARM, 28 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED) + +

    __scatterload_null (ARM, 4 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED) + +

    __scatterload_zeroinit (ARM, 24 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED) +

    +

    +Local Symbols +

    +

    delay (ARM, 24 bytes, Stack size 0 bytes, lcd_4bit.o(.text)) +

    [Called By]

    • >>   lcd_write_4bit +
    • >>   lcd_read_status +
    • >>   lcd_init +
    + +

    lcd_read_status (ARM, 188 bytes, Stack size 8 bytes, lcd_4bit.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = lcd_read_status +
    +
    [Calls]
    • >>   delay +
    +
    [Called By]
    • >>   wait_while_busy +
    + +

    wait_while_busy (ARM, 28 bytes, Stack size 8 bytes, lcd_4bit.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = wait_while_busy ⇒ lcd_read_status +
    +
    [Calls]
    • >>   lcd_read_status +
    +
    [Called By]
    • >>   lcd_write_cmd +
    • >>   lcd_write_data +
    + +

    lcd_write_data (ARM, 48 bytes, Stack size 8 bytes, lcd_4bit.o(.text)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = lcd_write_data ⇒ wait_while_busy ⇒ lcd_read_status +
    +
    [Calls]
    • >>   lcd_write_4bit +
    • >>   wait_while_busy +
    +
    [Called By]
    • >>   lcd_putchar +
    + +

    Undef_Handler (ARM, 4 bytes, Stack size unknown bytes, lpc2300.o(RESET)) +

    [Calls]

    • >>   Undef_Handler +
    +
    [Called By]
    • >>   Undef_Handler +
    +
    [Address Reference Count : 1]
    • lpc2300.o(RESET) +
    +

    SWI_Handler (ARM, 4 bytes, Stack size unknown bytes, lpc2300.o(RESET)) +

    [Calls]

    • >>   SWI_Handler +
    +
    [Called By]
    • >>   SWI_Handler +
    +
    [Address Reference Count : 1]
    • lpc2300.o(RESET) +
    +

    PAbt_Handler (ARM, 4 bytes, Stack size unknown bytes, lpc2300.o(RESET)) +

    [Calls]

    • >>   PAbt_Handler +
    +
    [Called By]
    • >>   PAbt_Handler +
    +
    [Address Reference Count : 1]
    • lpc2300.o(RESET) +
    +

    DAbt_Handler (ARM, 4 bytes, Stack size unknown bytes, lpc2300.o(RESET)) +

    [Calls]

    • >>   DAbt_Handler +
    +
    [Called By]
    • >>   DAbt_Handler +
    +
    [Address Reference Count : 1]
    • lpc2300.o(RESET) +
    +

    IRQ_Handler (ARM, 4 bytes, Stack size unknown bytes, lpc2300.o(RESET)) +

    [Calls]

    • >>   IRQ_Handler +
    +
    [Called By]
    • >>   IRQ_Handler +
    +
    [Address Reference Count : 1]
    • lpc2300.o(RESET) +
    +

    FIQ_Handler (ARM, 4 bytes, Stack size unknown bytes, lpc2300.o(RESET)) +

    [Calls]

    • >>   FIQ_Handler +
    +
    [Called By]
    • >>   FIQ_Handler +
    +
    [Address Reference Count : 1]
    • lpc2300.o(RESET) +
    +

    _fp_digits (Thumb, 318 bytes, Stack size 56 bytes, printfa.o(i._fp_digits), UNUSED) +

    [Calls]

    • >>   __aeabi_uldivmod +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2ulz +
    • >>   __aeabi_cdrcmple +
    • >>   __aeabi_dmul +
    • >>   __aeabi_ddiv +
    +
    [Called By]
    • >>   _printf_core +
    + +

    _printf_core (Thumb, 1800 bytes, Stack size 128 bytes, printfa.o(i._printf_core), UNUSED) +

    [Calls]

    • >>   __aeabi_uldivmod +
    • >>   _printf_pre_padding +
    • >>   _printf_post_padding +
    • >>   _fp_digits +
    • >>   __ARM_common_call_via_r2 +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   __0sprintf +
    + +

    _printf_post_padding (Thumb, 38 bytes, Stack size 24 bytes, printfa.o(i._printf_post_padding), UNUSED) +

    [Calls]

    • >>   __ARM_common_call_via_r6 +
    +
    [Called By]
    • >>   _printf_core +
    + +

    _printf_pre_padding (Thumb, 50 bytes, Stack size 40 bytes, printfa.o(i._printf_pre_padding), UNUSED) +

    [Calls]

    • >>   __ARM_common_call_via_r6 +
    +
    [Called By]
    • >>   _printf_core +
    + +

    _sputc (Thumb, 10 bytes, Stack size 0 bytes, printfa.o(i._sputc)) +

    [Called By]

    • >>   __0sprintf +
    +
    [Address Reference Count : 1]
    • printfa.o(i.__0sprintf) +

    +

    +Undefined Global Symbols +

    diff --git a/ADC.lnp b/ADC.lnp new file mode 100644 index 0000000..58c0d00 --- /dev/null +++ b/ADC.lnp @@ -0,0 +1,5 @@ +--cpu ARM7TDMI "servo_mg995.o" "lcd_4bit.o" "irq.o" "rtc.o" "ultrasonic_hc_sr04.o" "main.o" "lpc2300.o" +--library_type=microlib --strict --scatter "ADC.sct" +--summary_stderr --info summarysizes --map --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers + --list ".\ADC.map" -o ADC.axf \ No newline at end of file diff --git a/ADC.map b/ADC.map new file mode 100644 index 0000000..e025630 --- /dev/null +++ b/ADC.map @@ -0,0 +1,841 @@ +ARM Linker, 5.03 [Build 69] [MDK-ARM Lite] + +============================================================================== + +Section Cross References + + servo_mg995.o(.text) refers to uidiv.o(.text) for __aeabi_uidivmod + servo_mg995.o(.text) refers to lcd_4bit.o(.text) for lcd_init + servo_mg995.o(.text) refers to servo_mg995.o(.data) for i + lcd_4bit.o(.text) refers to lcd_4bit.o(.constdata) for UserFont + irq.o(.text) refers to irq.o(.data) for clk_cntr + irq.o(.text) refers to rtc.o(.data) for clock_1s + rtc.o(.text) refers to printfa.o(i.__0sprintf) for __2sprintf + rtc.o(.text) refers to lcd_4bit.o(.text) for set_cursor + rtc.o(.text) refers to irq.o(.text) for T0_IRQHandler + rtc.o(.text) refers to rtc.o(.data) for clock_1s + ultrasonic_hc_sr04.o(.text) refers to lcd_4bit.o(.text) for lcd_init + ultrasonic_hc_sr04.o(.text) refers to dflti.o(.text) for __aeabi_i2d + ultrasonic_hc_sr04.o(.text) refers to dmul.o(.text) for __aeabi_dmul + ultrasonic_hc_sr04.o(.text) refers to ddiv.o(.text) for __aeabi_ddiv + ultrasonic_hc_sr04.o(.text) refers to d2f.o(.text) for __aeabi_d2f + ultrasonic_hc_sr04.o(.text) refers to cfcmple.o(.text) for __aeabi_cfcmple + ultrasonic_hc_sr04.o(.text) refers to f2d.o(.text) for __aeabi_f2d + ultrasonic_hc_sr04.o(.text) refers to printfa.o(i.__0sprintf) for __2sprintf + ultrasonic_hc_sr04.o(.text) refers to ultrasonic_hc_sr04.o(.data) for echoTime + ultrasonic_hc_sr04.o(.text) refers to ultrasonic_hc_sr04.o(.bss) for cVal + main.o(.text) refers to ultrasonic_hc_sr04.o(.text) for setupTimer + main.o(.text) refers to rtc.o(.text) for RTCTimerEnable + main.o(.text) refers to servo_mg995.o(.text) for PWM_Init + main.o(.text) refers to lcd_4bit.o(.text) for lcd_init + main.o(.text) refers to cfcmple.o(.text) for __aeabi_cfcmple + main.o(.text) refers to f2d.o(.text) for __aeabi_f2d + main.o(.text) refers to printfa.o(i.__0sprintf) for __2sprintf + main.o(.text) refers to idiv.o(.text) for __aeabi_idivmod + main.o(.text) refers to rtc.o(.data) for min + lpc2300.o(RESET) refers to lpc2300.o(STACK) for Stack_Top + lpc2300.o(RESET) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk + idiv.o(.text) refers to uidiv.o(.text) for __aeabi_uidivmod + printfb.o(i.__0fprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0fprintf$bare) refers to fputc.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0printf$bare) refers to fputc.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._sputc) for _sputc + printfb.o(i.__0vfprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vfprintf$bare) refers to fputc.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vprintf$bare) refers to fputc.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._sputc) for _sputc + printfb.o(i._printf_core) refers to printfb.o(i.__ARM_common_call_via_r6) for __ARM_common_call_via_r6 + printf0.o(i.__0fprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0fprintf$0) refers to fputc.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0printf$0) refers to fputc.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0snprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0snprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0sprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0sprintf$0) refers to printf0.o(i._sputc) for _sputc + printf0.o(i.__0vfprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vfprintf$0) refers to fputc.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vprintf$0) refers to fputc.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._sputc) for _sputc + printf0.o(i._printf_core) refers to printfb.o(i.__ARM_common_call_via_r6) for __ARM_common_call_via_r6 + printf1.o(i.__0fprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0fprintf$1) refers to fputc.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0printf$1) refers to fputc.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0snprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0snprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0sprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0sprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i.__0vfprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vfprintf$1) refers to fputc.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vprintf$1) refers to fputc.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i._printf_core) refers to printf1.o(i.__ARM_common_call_via_r2) for __ARM_common_call_via_r2 + printf1.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf2.o(i.__0fprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0fprintf$2) refers to fputc.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0printf$2) refers to fputc.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0snprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0snprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0sprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0sprintf$2) refers to printf2.o(i._sputc) for _sputc + printf2.o(i.__0vfprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vfprintf$2) refers to fputc.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vprintf$2) refers to fputc.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._sputc) for _sputc + printf2.o(i._printf_core) refers to printf1.o(i.__ARM_common_call_via_r2) for __ARM_common_call_via_r2 + printf3.o(i.__0fprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0fprintf$3) refers to fputc.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0printf$3) refers to fputc.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0snprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0snprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0sprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0sprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i.__0vfprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vfprintf$3) refers to fputc.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vprintf$3) refers to fputc.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i._printf_core) refers to printf1.o(i.__ARM_common_call_via_r2) for __ARM_common_call_via_r2 + printf3.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf4.o(i.__0fprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0fprintf$4) refers to fputc.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0printf$4) refers to fputc.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0snprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0snprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0sprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0sprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i.__0vfprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vfprintf$4) refers to fputc.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vprintf$4) refers to fputc.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i._printf_core) refers to printf1.o(i.__ARM_common_call_via_r2) for __ARM_common_call_via_r2 + printf4.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf5.o(i.__0fprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0fprintf$5) refers to fputc.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0printf$5) refers to fputc.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0snprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0snprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0sprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0sprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i.__0vfprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vfprintf$5) refers to fputc.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vprintf$5) refers to fputc.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i._printf_core) refers to printf1.o(i.__ARM_common_call_via_r2) for __ARM_common_call_via_r2 + printf5.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf6.o(i.__0fprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0fprintf$6) refers to fputc.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0printf$6) refers to fputc.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0snprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0snprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0sprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0sprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i.__0vfprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vfprintf$6) refers to fputc.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vprintf$6) refers to fputc.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i._printf_core) refers to printf1.o(i.__ARM_common_call_via_r2) for __ARM_common_call_via_r2 + printf6.o(i._printf_core) refers to printf6.o(i._printf_pre_padding) for _printf_pre_padding + printf6.o(i._printf_core) refers to printf6.o(i._printf_post_padding) for _printf_post_padding + printf6.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf6.o(i._printf_post_padding) refers to printfb.o(i.__ARM_common_call_via_r6) for __ARM_common_call_via_r6 + printf6.o(i._printf_pre_padding) refers to printfb.o(i.__ARM_common_call_via_r6) for __ARM_common_call_via_r6 + printf7.o(i.__0fprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0fprintf$7) refers to fputc.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0printf$7) refers to fputc.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0snprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0snprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0sprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0sprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i.__0vfprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vfprintf$7) refers to fputc.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vprintf$7) refers to fputc.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i._printf_core) refers to printf1.o(i.__ARM_common_call_via_r2) for __ARM_common_call_via_r2 + printf7.o(i._printf_core) refers to printf7.o(i._printf_pre_padding) for _printf_pre_padding + printf7.o(i._printf_core) refers to printf7.o(i._printf_post_padding) for _printf_post_padding + printf7.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf7.o(i._printf_post_padding) refers to printfb.o(i.__ARM_common_call_via_r6) for __ARM_common_call_via_r6 + printf7.o(i._printf_pre_padding) refers to printfb.o(i.__ARM_common_call_via_r6) for __ARM_common_call_via_r6 + printf8.o(i.__0fprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0fprintf$8) refers to fputc.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0printf$8) refers to fputc.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0snprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0snprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0sprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0sprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i.__0vfprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vfprintf$8) refers to fputc.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vprintf$8) refers to fputc.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i._printf_core) refers to printf1.o(i.__ARM_common_call_via_r2) for __ARM_common_call_via_r2 + printf8.o(i._printf_core) refers to printf8.o(i._printf_pre_padding) for _printf_pre_padding + printf8.o(i._printf_core) refers to printf8.o(i._printf_post_padding) for _printf_post_padding + printf8.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf8.o(i._printf_post_padding) refers to printfb.o(i.__ARM_common_call_via_r6) for __ARM_common_call_via_r6 + printf8.o(i._printf_pre_padding) refers to printfb.o(i.__ARM_common_call_via_r6) for __ARM_common_call_via_r6 + printfa.o(i.__0fprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0fprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0fprintf) refers to fputc.o(i.fputc) for fputc + printfa.o(i.__0printf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0printf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0printf) refers to fputc.o(i.fputc) for fputc + printfa.o(i.__0printf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0snprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0snprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0snprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0sprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0sprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0sprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i.__0vfprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vfprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vfprintf) refers to fputc.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vprintf) refers to fputc.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0vsnprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsnprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsnprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0vsprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i._fp_digits) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._fp_digits) refers to dmul.o(.text) for __aeabi_dmul + printfa.o(i._fp_digits) refers to ddiv.o(.text) for __aeabi_ddiv + printfa.o(i._fp_digits) refers to cdrcmple.o(.text) for __aeabi_cdrcmple + printfa.o(i._fp_digits) refers to dadd.o(.text) for __aeabi_dadd + printfa.o(i._fp_digits) refers to dfixul.o(.text) for __aeabi_d2ulz + printfa.o(i._fp_digits) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_core) refers to printf1.o(i.__ARM_common_call_via_r2) for __ARM_common_call_via_r2 + printfa.o(i._printf_core) refers to printfa.o(i._printf_pre_padding) for _printf_pre_padding + printfa.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers to printfa.o(i._printf_post_padding) for _printf_post_padding + printfa.o(i._printf_core) refers to printfa.o(i._fp_digits) for _fp_digits + printfa.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printfa.o(i._printf_post_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_post_padding) refers to printfb.o(i.__ARM_common_call_via_r6) for __ARM_common_call_via_r6 + printfa.o(i._printf_pre_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_pre_padding) refers to printfb.o(i.__ARM_common_call_via_r6) for __ARM_common_call_via_r6 + printfa.o(i._snputc) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._sputc) refers (Special) to iusefp.o(.text) for __I$use$fp + dmul.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dmul.o(.text) refers to depilogue.o(.text) for _double_epilogue + ddiv.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + ddiv.o(.text) refers to depilogue.o(.text) for _double_round + dflti.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dflti.o(.text) refers to depilogue.o(.text) for _double_epilogue + f2d.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + d2f.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + d2f.o(.text) refers to fepilogue.o(.text) for _float_round + cfcmple.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000 + entry2.o(.ARM.Collect$$$$00002712) refers to lpc2300.o(STACK) for __initial_sp + entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload + entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(.text) for main + entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(.text) for main + fputc.o(i.fputc) refers (Special) to iusesemip.o(.text) for __I$use$semihosting$fputc + fputc.o(i.fputc) refers (Special) to semi.o(.text) for __semihosting_library_function + uldiv.o(.text) refers to llushr.o(.text) for __aeabi_llsr + uldiv.o(.text) refers to llshl.o(.text) for __aeabi_llsl + depilogue.o(.text) refers to depilogue.o(i.__ARM_clz) for __ARM_clz + depilogue.o(.text) refers to llshl.o(.text) for __aeabi_llsl + depilogue.o(.text) refers to llushr.o(.text) for __aeabi_llsr + dadd.o(.text) refers to llshl.o(.text) for __aeabi_llsl + dadd.o(.text) refers to llsshr.o(.text) for __aeabi_lasr + dadd.o(.text) refers to depilogue.o(.text) for _double_epilogue + dfixul.o(.text) refers to llushr.o(.text) for __aeabi_llsr + dfixul.o(.text) refers to llshl.o(.text) for __aeabi_llsl + init.o(.text) refers to init.o(i.__ARM_common_call_via_r3) for __ARM_common_call_via_r3 + init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload + + +============================================================================== + +Removing Unused input sections from the image. + + Removing lpc2300.o(HEAP), (0 bytes). + +1 unused section(s) (total 0 bytes) removed from the image. + +============================================================================== + +Adding Veneers to the image + + Adding AT veneer (8 bytes, Inline) for call to '__aeabi_uidivmod' from servo_mg995.o(.text). + Adding AT veneer (8 bytes, Inline) for call to '__aeabi_idivmod' from main.o(.text). + Adding AT veneer (8 bytes, Inline) for call to '__aeabi_dmul' from ultrasonic_hc_sr04.o(.text). + Adding AT veneer (8 bytes, Inline) for call to '__aeabi_ddiv' from ultrasonic_hc_sr04.o(.text). + Adding AT veneer (8 bytes, Inline) for call to '__aeabi_i2d' from ultrasonic_hc_sr04.o(.text). + Adding AT veneer (8 bytes, Inline) for call to '__aeabi_f2d' from ultrasonic_hc_sr04.o(.text). + Adding AT veneer (8 bytes, Inline) for call to '__aeabi_d2f' from ultrasonic_hc_sr04.o(.text). + Adding AT veneer (8 bytes, Inline) for call to '__aeabi_cfcmple' from ultrasonic_hc_sr04.o(.text). + Adding AT veneer (8 bytes, Inline) for call to '__scatterload' from entry5.o(.ARM.Collect$$$$00000004). + Adding TA veneer (8 bytes, Short) for call to '__main_after_scatterload' from init.o(.text). + Adding AT veneer (8 bytes, Inline) for call to '__2sprintf' from rtc.o(.text). + +11 Veneer(s) (total 88 bytes) added to the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + RESET 0x00000000 Section 556 lpc2300.o(RESET) + ../clib/microlib/division.c 0x00000000 Number 0 uldiv.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 idiv.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 uidiv.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llushr.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llsshr.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llshl.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfa.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf4.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf5.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf7.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf8.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf6.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf2.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfb.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf0.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf1.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf3.o ABSOLUTE + ../clib/microlib/printf/stubs.s 0x00000000 Number 0 stubs.o ABSOLUTE + ../clib/microlib/stdio/fputc.c 0x00000000 Number 0 fputc.o ABSOLUTE + ../clib/microlib/stdio/semi.s 0x00000000 Number 0 semi.o ABSOLUTE + ../clib/microlib/stdio/streams.c 0x00000000 Number 0 stdout.o ABSOLUTE + ../clib/microlib/stubs.s 0x00000000 Number 0 iusesemip.o ABSOLUTE + ../clib/microlib/stubs.s 0x00000000 Number 0 iusefp.o ABSOLUTE + ../fplib/microlib/d2f.c 0x00000000 Number 0 d2f.o ABSOLUTE + ../fplib/microlib/f2d.c 0x00000000 Number 0 f2d.o ABSOLUTE + ../fplib/microlib/fpadd.c 0x00000000 Number 0 dadd.o ABSOLUTE + ../fplib/microlib/fpdiv.c 0x00000000 Number 0 ddiv.o ABSOLUTE + ../fplib/microlib/fpepilogue.c 0x00000000 Number 0 depilogue.o ABSOLUTE + ../fplib/microlib/fpepilogue.c 0x00000000 Number 0 fepilogue.o ABSOLUTE + ../fplib/microlib/fpfix.c 0x00000000 Number 0 dfixul.o ABSOLUTE + ../fplib/microlib/fpflt.c 0x00000000 Number 0 dflti.o ABSOLUTE + ../fplib/microlib/fpmul.c 0x00000000 Number 0 dmul.o ABSOLUTE + IRQ.c 0x00000000 Number 0 irq.o ABSOLUTE + LCD_4bit.c 0x00000000 Number 0 lcd_4bit.o ABSOLUTE + LPC2300.s 0x00000000 Number 0 lpc2300.o ABSOLUTE + RTC.c 0x00000000 Number 0 rtc.o ABSOLUTE + Servo_MG995.c 0x00000000 Number 0 servo_mg995.o ABSOLUTE + Ultrasonic_HC_SR04.c 0x00000000 Number 0 ultrasonic_hc_sr04.o ABSOLUTE + cdrcmple.s 0x00000000 Number 0 cdrcmple.o ABSOLUTE + cfcmple.s 0x00000000 Number 0 cfcmple.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE + init.s 0x00000000 Number 0 init.o ABSOLUTE + main.c 0x00000000 Number 0 main.o ABSOLUTE + Undef_Handler 0x00000040 ARM Code 4 lpc2300.o(RESET) + SWI_Handler 0x00000044 ARM Code 4 lpc2300.o(RESET) + PAbt_Handler 0x00000048 ARM Code 4 lpc2300.o(RESET) + DAbt_Handler 0x0000004c ARM Code 4 lpc2300.o(RESET) + IRQ_Handler 0x00000050 ARM Code 4 lpc2300.o(RESET) + FIQ_Handler 0x00000054 ARM Code 4 lpc2300.o(RESET) + .ARM.Collect$$$$00000000 0x0000022c Section 0 entry.o(.ARM.Collect$$$$00000000) + .ARM.Collect$$$$00000001 0x0000022c Section 4 entry2.o(.ARM.Collect$$$$00000001) + .ARM.Collect$$$$00000004 0x00000230 Section 4 entry5.o(.ARM.Collect$$$$00000004) + .ARM.Collect$$$$00000008 0x00000234 Section 0 entry7b.o(.ARM.Collect$$$$00000008) + .ARM.Collect$$$$0000000A 0x00000234 Section 0 entry8b.o(.ARM.Collect$$$$0000000A) + .ARM.Collect$$$$0000000B 0x00000234 Section 12 entry9a.o(.ARM.Collect$$$$0000000B) + .ARM.Collect$$$$0000000D 0x00000240 Section 0 entry10a.o(.ARM.Collect$$$$0000000D) + .ARM.Collect$$$$0000000F 0x00000240 Section 0 entry11a.o(.ARM.Collect$$$$0000000F) + .ARM.Collect$$$$00002712 0x00000240 Section 4 entry2.o(.ARM.Collect$$$$00002712) + __lit__00000000 0x00000240 Data 4 entry2.o(.ARM.Collect$$$$00002712) + .text 0x00000244 Section 0 servo_mg995.o(.text) + .text 0x00000318 Section 0 lcd_4bit.o(.text) + delay 0x00000318 ARM Code 24 lcd_4bit.o(.text) + lcd_read_status 0x00000330 ARM Code 188 lcd_4bit.o(.text) + wait_while_busy 0x000003ec ARM Code 28 lcd_4bit.o(.text) + lcd_write_data 0x0000048c ARM Code 48 lcd_4bit.o(.text) + .text 0x00000610 Section 0 irq.o(.text) + .text 0x00000674 Section 0 rtc.o(.text) + .text 0x0000092c Section 0 ultrasonic_hc_sr04.o(.text) + .text 0x00000c84 Section 0 main.o(.text) + .text 0x00000eec Section 0 uidiv.o(.text) + .text 0x00000f24 Section 0 idiv.o(.text) + .text 0x00000f58 Section 0 dmul.o(.text) + .text 0x00001034 Section 0 ddiv.o(.text) + .text 0x00001130 Section 0 dflti.o(.text) + .text 0x00001160 Section 0 f2d.o(.text) + .text 0x00001190 Section 0 d2f.o(.text) + .text 0x000011d4 Section 20 cfcmple.o(.text) + .text 0x000011e8 Section 0 uldiv.o(.text) + .text 0x00001250 Section 0 iusefp.o(.text) + .text 0x00001250 Section 0 fepilogue.o(.text) + .text 0x000012d4 Section 0 depilogue.o(.text) + .text 0x0000139c Section 0 dadd.o(.text) + .text 0x00001504 Section 0 dfixul.o(.text) + .text 0x00001548 Section 40 cdrcmple.o(.text) + .text 0x00001578 Section 32 init.o(.text) + .text 0x00001598 Section 0 llshl.o(.text) + .text 0x000015ba Section 0 llushr.o(.text) + .text 0x000015de Section 0 llsshr.o(.text) + i.__0sprintf 0x00001618 Section 0 printfa.o(i.__0sprintf) + i.__ARM_clz 0x00001640 Section 0 depilogue.o(i.__ARM_clz) + i.__ARM_common_call_via_r2 0x0000166e Section 0 printf1.o(i.__ARM_common_call_via_r2) + i.__ARM_common_call_via_r3 0x00001670 Section 2 init.o(i.__ARM_common_call_via_r3) + i.__ARM_common_call_via_r6 0x00001672 Section 0 printfb.o(i.__ARM_common_call_via_r6) + i.__scatterload_copy 0x00001674 Section 28 handlers.o(i.__scatterload_copy) + i.__scatterload_null 0x00001690 Section 4 handlers.o(i.__scatterload_null) + i.__scatterload_zeroinit 0x00001694 Section 24 handlers.o(i.__scatterload_zeroinit) + i._fp_digits 0x000016ac Section 0 printfa.o(i._fp_digits) + _fp_digits 0x000016ad Thumb Code 318 printfa.o(i._fp_digits) + i._printf_core 0x00001808 Section 0 printfa.o(i._printf_core) + _printf_core 0x00001809 Thumb Code 1800 printfa.o(i._printf_core) + i._printf_post_padding 0x00001f20 Section 0 printfa.o(i._printf_post_padding) + _printf_post_padding 0x00001f21 Thumb Code 38 printfa.o(i._printf_post_padding) + i._printf_pre_padding 0x00001f46 Section 0 printfa.o(i._printf_pre_padding) + _printf_pre_padding 0x00001f47 Thumb Code 50 printfa.o(i._printf_pre_padding) + i._sputc 0x00001f78 Section 0 printfa.o(i._sputc) + _sputc 0x00001f79 Thumb Code 10 printfa.o(i._sputc) + .constdata 0x00001f82 Section 64 lcd_4bit.o(.constdata) + .data 0x40000000 Section 8 servo_mg995.o(.data) + .data 0x40000008 Section 4 irq.o(.data) + clk_cntr 0x40000008 Data 4 irq.o(.data) + .data 0x4000000c Section 23 rtc.o(.data) + .data 0x40000024 Section 16 ultrasonic_hc_sr04.o(.data) + .bss 0x40000034 Section 10 ultrasonic_hc_sr04.o(.bss) + STACK 0x40000040 Section 1288 lpc2300.o(STACK) + Stack_Top 0x40000548 Data 0 lpc2300.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv1$ARM_ISAv4$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$EBA8$MICROLIB$REQ8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + _printf_a 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_c 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_charcount 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_d 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_e 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_f 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_flags 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_fp_dec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_fp_hex 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_g 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_i 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_int_dec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_l 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_lc 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_ll 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_lld 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_lli 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_llo 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_llu 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_llx 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_longlong_dec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_longlong_hex 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_longlong_oct 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_ls 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_mbtowc 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_n 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_o 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_p 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_percent 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_pre_padding 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_return_value 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_s 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_sizespec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_str 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_truncate_signed 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_truncate_unsigned 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_u 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_wc 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_wctomb 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_widthprec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_x 0x00000000 Number 0 stubs.o ABSOLUTE + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __decompress - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _microlib_exit - Undefined Weak Reference + Reset_Handler 0x00000058 ARM Code 0 lpc2300.o(RESET) + __main 0x0000022c ARM Code 0 entry.o(.ARM.Collect$$$$00000000) + _main_stk 0x0000022c ARM Code 0 entry2.o(.ARM.Collect$$$$00000001) + _main_scatterload 0x00000230 ARM Code 0 entry5.o(.ARM.Collect$$$$00000004) + __main_after_scatterload 0x00000234 ARM Code 0 entry5.o(.ARM.Collect$$$$00000004) + _main_clock 0x00000234 ARM Code 0 entry7b.o(.ARM.Collect$$$$00000008) + _main_cpp_init 0x00000234 ARM Code 0 entry8b.o(.ARM.Collect$$$$0000000A) + _main_init 0x00000234 ARM Code 0 entry9a.o(.ARM.Collect$$$$0000000B) + __rt_final_cpp 0x00000240 ARM Code 0 entry10a.o(.ARM.Collect$$$$0000000D) + __rt_final_exit 0x00000240 ARM Code 0 entry11a.o(.ARM.Collect$$$$0000000F) + PWM_Init 0x00000244 ARM Code 60 servo_mg995.o(.text) + WaitTime 0x00000280 ARM Code 56 servo_mg995.o(.text) + PWM_SetDutyCycle 0x000002b8 ARM Code 52 servo_mg995.o(.text) + trial_run_servo 0x000002ec ARM Code 28 servo_mg995.o(.text) + lcd_write_4bit 0x00000408 ARM Code 84 lcd_4bit.o(.text) + lcd_write_cmd 0x0000045c ARM Code 48 lcd_4bit.o(.text) + lcd_putchar 0x000004bc ARM Code 24 lcd_4bit.o(.text) + lcd_init 0x000004d4 ARM Code 176 lcd_4bit.o(.text) + set_cursor 0x00000584 ARM Code 52 lcd_4bit.o(.text) + lcd_clear 0x000005b8 ARM Code 32 lcd_4bit.o(.text) + lcd_print 0x000005d8 ARM Code 40 lcd_4bit.o(.text) + T0_IRQHandler 0x00000610 ARM Code 88 irq.o(.text) + RTCTimerEnable 0x00000674 ARM Code 60 rtc.o(.text) + updateRTCTimer 0x000006b0 ARM Code 524 rtc.o(.text) + trial_run_rtc 0x000008bc ARM Code 44 rtc.o(.text) + delayUS 0x0000092c ARM Code 56 ultrasonic_hc_sr04.o(.text) + initTimer0 0x00000964 ARM Code 52 ultrasonic_hc_sr04.o(.text) + startTimer0 0x00000998 ARM Code 24 ultrasonic_hc_sr04.o(.text) + stopTimer0 0x000009b0 ARM Code 24 ultrasonic_hc_sr04.o(.text) + delayMS 0x000009c8 ARM Code 28 ultrasonic_hc_sr04.o(.text) + setPins 0x000009e4 ARM Code 76 ultrasonic_hc_sr04.o(.text) + setupTimer 0x00000a30 ARM Code 44 ultrasonic_hc_sr04.o(.text) + calDistance 0x00000a5c ARM Code 160 ultrasonic_hc_sr04.o(.text) + sendPulse 0x00000afc ARM Code 72 ultrasonic_hc_sr04.o(.text) + trial_run_ultrasonic 0x00000b44 ARM Code 240 ultrasonic_hc_sr04.o(.text) + main 0x00000c84 ARM Code 540 main.o(.text) + Inline ARM to Thumb Veneer to __aeabi_uidivmod 0x00000ee4 ARM Code 8 uidiv.o(.text) + __aeabi_uidiv 0x00000eed Thumb Code 0 uidiv.o(.text) + __aeabi_uidivmod 0x00000eed Thumb Code 46 uidiv.o(.text) + Inline ARM to Thumb Veneer to __aeabi_idivmod 0x00000f1c ARM Code 8 idiv.o(.text) + __aeabi_idiv 0x00000f25 Thumb Code 0 idiv.o(.text) + __aeabi_idivmod 0x00000f25 Thumb Code 44 idiv.o(.text) + Inline ARM to Thumb Veneer to __aeabi_dmul 0x00000f50 ARM Code 8 dmul.o(.text) + __aeabi_dmul 0x00000f59 Thumb Code 206 dmul.o(.text) + Inline ARM to Thumb Veneer to __aeabi_ddiv 0x0000102c ARM Code 8 ddiv.o(.text) + __aeabi_ddiv 0x00001035 Thumb Code 238 ddiv.o(.text) + Inline ARM to Thumb Veneer to __aeabi_i2d 0x00001128 ARM Code 8 dflti.o(.text) + __aeabi_i2d 0x00001131 Thumb Code 36 dflti.o(.text) + Inline ARM to Thumb Veneer to __aeabi_f2d 0x00001158 ARM Code 8 f2d.o(.text) + __aeabi_f2d 0x00001161 Thumb Code 40 f2d.o(.text) + Inline ARM to Thumb Veneer to __aeabi_d2f 0x00001188 ARM Code 8 d2f.o(.text) + __aeabi_d2f 0x00001191 Thumb Code 60 d2f.o(.text) + Inline ARM to Thumb Veneer to __aeabi_cfcmple 0x000011cc ARM Code 8 cfcmple.o(.text) + __aeabi_cfcmpeq 0x000011d5 Thumb Code 0 cfcmple.o(.text) + __aeabi_cfcmple 0x000011d5 Thumb Code 20 cfcmple.o(.text) + __aeabi_uldivmod 0x000011e9 Thumb Code 104 uldiv.o(.text) + __I$use$fp 0x00001250 ARM Code 0 iusefp.o(.text) + _float_round 0x00001251 Thumb Code 16 fepilogue.o(.text) + _float_epilogue 0x00001261 Thumb Code 116 fepilogue.o(.text) + _double_round 0x000012d5 Thumb Code 28 depilogue.o(.text) + _double_epilogue 0x000012f1 Thumb Code 170 depilogue.o(.text) + __aeabi_dadd 0x0000139d Thumb Code 330 dadd.o(.text) + __aeabi_dsub 0x000014e7 Thumb Code 12 dadd.o(.text) + __aeabi_drsub 0x000014f3 Thumb Code 12 dadd.o(.text) + __aeabi_d2ulz 0x00001505 Thumb Code 58 dfixul.o(.text) + __aeabi_cdrcmple 0x00001549 Thumb Code 40 cdrcmple.o(.text) + Inline ARM to Thumb Veneer to __scatterload 0x00001570 ARM Code 8 init.o(.text) + __scatterload 0x00001579 Thumb Code 24 init.o(.text) + __scatterload_rt2 0x00001579 Thumb Code 0 init.o(.text) + __aeabi_llsl 0x00001599 Thumb Code 34 llshl.o(.text) + _ll_shift_l 0x00001599 Thumb Code 0 llshl.o(.text) + __aeabi_llsr 0x000015bb Thumb Code 36 llushr.o(.text) + _ll_ushift_r 0x000015bb Thumb Code 0 llushr.o(.text) + __aeabi_lasr 0x000015df Thumb Code 40 llsshr.o(.text) + _ll_sshift_r 0x000015df Thumb Code 0 llsshr.o(.text) + Short Thumb to ARM Veneer to __main_after_scatterload 0x00001609 Thumb Code 8 anon$$obj.o(Veneer$$Code) + Inline ARM to Thumb Veneer to __2sprintf 0x00001610 ARM Code 8 printfa.o(i.__0sprintf) + __0sprintf 0x00001619 Thumb Code 36 printfa.o(i.__0sprintf) + __1sprintf 0x00001619 Thumb Code 0 printfa.o(i.__0sprintf) + __2sprintf 0x00001619 Thumb Code 0 printfa.o(i.__0sprintf) + __c89sprintf 0x00001619 Thumb Code 0 printfa.o(i.__0sprintf) + sprintf 0x00001619 Thumb Code 0 printfa.o(i.__0sprintf) + __ARM_clz 0x00001641 Thumb Code 46 depilogue.o(i.__ARM_clz) + __ARM_common_call_via_r2 0x0000166f Thumb Code 2 printf1.o(i.__ARM_common_call_via_r2) + __ARM_common_call_via_r3 0x00001671 Thumb Code 2 init.o(i.__ARM_common_call_via_r3) + __ARM_common_call_via_r6 0x00001673 Thumb Code 2 printfb.o(i.__ARM_common_call_via_r6) + __scatterload_copy 0x00001674 ARM Code 28 handlers.o(i.__scatterload_copy) + __scatterload_null 0x00001690 ARM Code 4 handlers.o(i.__scatterload_null) + __scatterload_zeroinit 0x00001694 ARM Code 24 handlers.o(i.__scatterload_zeroinit) + UserFont 0x00001f82 Data 64 lcd_4bit.o(.constdata) + Region$$Table$$Base 0x00001fc4 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x00001fe4 Number 0 anon$$obj.o(Region$$Table) + i 0x40000000 Data 4 servo_mg995.o(.data) + dutyCycle 0x40000004 Data 4 servo_mg995.o(.data) + j 0x4000000c Data 4 rtc.o(.data) + hr 0x40000010 Data 4 rtc.o(.data) + min 0x40000014 Data 4 rtc.o(.data) + sec 0x40000018 Data 4 rtc.o(.data) + hrVal 0x4000001c Data 2 rtc.o(.data) + minVal 0x4000001e Data 2 rtc.o(.data) + secV 0x40000020 Data 2 rtc.o(.data) + clock_1s 0x40000022 Data 1 rtc.o(.data) + echoTime 0x40000024 Data 4 ultrasonic_hc_sr04.o(.data) + distance 0x40000028 Data 4 ultrasonic_hc_sr04.o(.data) + k 0x4000002c Data 4 ultrasonic_hc_sr04.o(.data) + pulsecnt 0x40000030 Data 4 ultrasonic_hc_sr04.o(.data) + cVal 0x40000034 Data 10 ultrasonic_hc_sr04.o(.bss) + __initial_sp 0x40000440 Data 264 lpc2300.o(STACK) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x0000022c + + Load Region LR_IROM1 (Base: 0x00000000, Size: 0x00002018, Max: 0x00080000, ABSOLUTE) + + Execution Region ER_IROM1 (Base: 0x00000000, Size: 0x00001fe4, Max: 0x00080000, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x00000000 0x0000022c Code RO 112 RESET lpc2300.o + 0x0000022c 0x00000000 Code RO 116 * .ARM.Collect$$$$00000000 mc_t.l(entry.o) + 0x0000022c 0x00000004 Code RO 400 .ARM.Collect$$$$00000001 mc_t.l(entry2.o) + 0x00000230 0x00000004 Code RO 402 .ARM.Collect$$$$00000004 mc_t.l(entry5.o) + 0x00000234 0x00000000 Code RO 404 .ARM.Collect$$$$00000008 mc_t.l(entry7b.o) + 0x00000234 0x00000000 Code RO 406 .ARM.Collect$$$$0000000A mc_t.l(entry8b.o) + 0x00000234 0x0000000c Code RO 407 .ARM.Collect$$$$0000000B mc_t.l(entry9a.o) + 0x00000240 0x00000000 Code RO 409 .ARM.Collect$$$$0000000D mc_t.l(entry10a.o) + 0x00000240 0x00000000 Code RO 411 .ARM.Collect$$$$0000000F mc_t.l(entry11a.o) + 0x00000240 0x00000004 Code RO 401 .ARM.Collect$$$$00002712 mc_t.l(entry2.o) + 0x00000244 0x000000d4 Code RO 1 .text servo_mg995.o + 0x00000318 0x000002f8 Code RO 28 .text lcd_4bit.o + 0x00000610 0x00000064 Code RO 49 .text irq.o + 0x00000674 0x000002b8 Code RO 63 .text rtc.o + 0x0000092c 0x00000358 Code RO 78 .text ultrasonic_hc_sr04.o + 0x00000c84 0x00000260 Code RO 97 .text main.o + 0x00000ee4 0x00000008 Ven RO 119 .text mc_t.l(uidiv.o) + 0x00000eec 0x0000002e Code RO 119 .text mc_t.l(uidiv.o) + 0x00000f1a 0x00000002 PAD + 0x00000f1c 0x00000008 Ven RO 121 .text mc_t.l(idiv.o) + 0x00000f24 0x0000002c Code RO 121 .text mc_t.l(idiv.o) + 0x00000f50 0x00000008 Ven RO 388 .text mf_t.l(dmul.o) + 0x00000f58 0x000000d4 Code RO 388 .text mf_t.l(dmul.o) + 0x0000102c 0x00000008 Ven RO 390 .text mf_t.l(ddiv.o) + 0x00001034 0x000000f4 Code RO 390 .text mf_t.l(ddiv.o) + 0x00001128 0x00000008 Ven RO 392 .text mf_t.l(dflti.o) + 0x00001130 0x00000028 Code RO 392 .text mf_t.l(dflti.o) + 0x00001158 0x00000008 Ven RO 394 .text mf_t.l(f2d.o) + 0x00001160 0x00000028 Code RO 394 .text mf_t.l(f2d.o) + 0x00001188 0x00000008 Ven RO 396 .text mf_t.l(d2f.o) + 0x00001190 0x0000003c Code RO 396 .text mf_t.l(d2f.o) + 0x000011cc 0x00000008 Ven RO 398 .text mf_t.l(cfcmple.o) + 0x000011d4 0x00000014 Code RO 398 .text mf_t.l(cfcmple.o) + 0x000011e8 0x00000068 Code RO 416 .text mc_t.l(uldiv.o) + 0x00001250 0x00000000 Code RO 418 .text mc_t.l(iusefp.o) + 0x00001250 0x00000084 Code RO 419 .text mf_t.l(fepilogue.o) + 0x000012d4 0x000000c6 Code RO 421 .text mf_t.l(depilogue.o) + 0x0000139a 0x00000002 PAD + 0x0000139c 0x00000168 Code RO 425 .text mf_t.l(dadd.o) + 0x00001504 0x00000044 Code RO 427 .text mf_t.l(dfixul.o) + 0x00001548 0x00000028 Code RO 429 .text mf_t.l(cdrcmple.o) + 0x00001570 0x00000008 Ven RO 431 .text mc_t.l(init.o) + 0x00001578 0x00000020 Code RO 431 .text mc_t.l(init.o) + 0x00001598 0x00000022 Code RO 436 .text mc_t.l(llshl.o) + 0x000015ba 0x00000024 Code RO 438 .text mc_t.l(llushr.o) + 0x000015de 0x00000028 Code RO 440 .text mc_t.l(llsshr.o) + 0x00001606 0x00000002 PAD + 0x00001608 0x00000008 Ven RO 461 Veneer$$Code anon$$obj.o + 0x00001610 0x00000008 Ven RO 362 i.__0sprintf mc_t.l(printfa.o) + 0x00001618 0x00000028 Code RO 362 i.__0sprintf mc_t.l(printfa.o) + 0x00001640 0x0000002e Code RO 423 i.__ARM_clz mf_t.l(depilogue.o) + 0x0000166e 0x00000002 Code RO 191 i.__ARM_common_call_via_r2 mc_t.l(printf1.o) + 0x00001670 0x00000002 Code RO 433 i.__ARM_common_call_via_r3 mc_t.l(init.o) + 0x00001672 0x00000002 Code RO 145 i.__ARM_common_call_via_r6 mc_t.l(printfb.o) + 0x00001674 0x0000001c Code RO 445 i.__scatterload_copy mc_t.l(handlers.o) + 0x00001690 0x00000004 Code RO 446 i.__scatterload_null mc_t.l(handlers.o) + 0x00001694 0x00000018 Code RO 447 i.__scatterload_zeroinit mc_t.l(handlers.o) + 0x000016ac 0x0000015c Code RO 367 i._fp_digits mc_t.l(printfa.o) + 0x00001808 0x00000718 Code RO 368 i._printf_core mc_t.l(printfa.o) + 0x00001f20 0x00000026 Code RO 369 i._printf_post_padding mc_t.l(printfa.o) + 0x00001f46 0x00000032 Code RO 370 i._printf_pre_padding mc_t.l(printfa.o) + 0x00001f78 0x0000000a Code RO 372 i._sputc mc_t.l(printfa.o) + 0x00001f82 0x00000040 Data RO 29 .constdata lcd_4bit.o + 0x00001fc2 0x00000002 PAD + 0x00001fc4 0x00000020 Data RO 443 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Base: 0x40000000, Size: 0x00000548, Max: 0x00008000, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x40000000 0x00000008 Data RW 2 .data servo_mg995.o + 0x40000008 0x00000004 Data RW 50 .data irq.o + 0x4000000c 0x00000017 Data RW 64 .data rtc.o + 0x40000023 0x00000001 PAD + 0x40000024 0x00000010 Data RW 80 .data ultrasonic_hc_sr04.o + 0x40000034 0x0000000a Zero RW 79 .bss ultrasonic_hc_sr04.o + 0x4000003e 0x00000002 PAD + 0x40000040 0x00000508 Zero RW 110 STACK lpc2300.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 100 12 0 4 0 432 irq.o + 760 16 64 0 0 3398 lcd_4bit.o + 556 80 0 0 1288 356 lpc2300.o + 608 68 0 0 0 811 main.o + 696 68 0 23 0 1588 rtc.o + 212 16 0 8 0 2571 servo_mg995.o + 856 80 0 16 10 2806 ultrasonic_hc_sr04.o + + ---------------------------------------------------------------------- + 3796 340 98 52 1300 11962 Object Totals + 8 0 32 0 0 0 (incl. Generated) + 0 0 2 1 2 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 0 0 0 0 0 0 entry.o + 0 0 0 0 0 0 entry10a.o + 0 0 0 0 0 0 entry11a.o + 8 4 0 0 0 0 entry2.o + 4 0 0 0 0 0 entry5.o + 0 0 0 0 0 0 entry7b.o + 0 0 0 0 0 0 entry8b.o + 12 4 0 0 0 0 entry9a.o + 56 0 0 0 0 0 handlers.o + 52 0 0 0 0 84 idiv.o + 42 8 0 0 0 136 init.o + 0 0 0 0 0 0 iusefp.o + 34 0 0 0 0 72 llshl.o + 40 0 0 0 0 72 llsshr.o + 36 0 0 0 0 72 llushr.o + 2 0 0 0 0 60 printf1.o + 2310 96 0 0 0 524 printfa.o + 2 0 0 0 0 60 printfb.o + 54 0 0 0 0 72 uidiv.o + 104 0 0 0 0 96 uldiv.o + 40 0 0 0 0 68 cdrcmple.o + 28 0 0 0 0 68 cfcmple.o + 68 0 0 0 0 80 d2f.o + 360 6 0 0 0 152 dadd.o + 252 6 0 0 0 96 ddiv.o + 244 0 0 0 0 232 depilogue.o + 68 10 0 0 0 80 dfixul.o + 48 4 0 0 0 76 dflti.o + 220 6 0 0 0 100 dmul.o + 48 0 0 0 0 60 f2d.o + 132 0 0 0 0 144 fepilogue.o + + ---------------------------------------------------------------------- + 4270 144 0 0 0 2404 Library Totals + 6 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 2756 112 0 0 0 1248 mc_t.l + 1508 32 0 0 0 1156 mf_t.l + + ---------------------------------------------------------------------- + 4270 144 0 0 0 2404 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 8066 484 98 52 1300 12834 Grand Totals + 8066 484 98 52 1300 12834 ELF Image Totals + 8066 484 98 52 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 8164 ( 7.97kB) + Total RW Size (RW Data + ZI Data) 1352 ( 1.32kB) + Total ROM Size (Code + RO Data + RW Data) 8216 ( 8.02kB) + +============================================================================== + diff --git a/ADC.plg b/ADC.plg new file mode 100644 index 0000000..e45f0c3 --- /dev/null +++ b/ADC.plg @@ -0,0 +1,102 @@ + + +
    +
    µVision Build Log
    
+
    Project:
    
+C:\Users\Lenovo\Documents\Keil uVision4\PetFeeder\ADC.uvproj
+Project File Date:  
+
+
    Output:
    
+Rebuild target 'Target 1'
+compiling Servo_MG995.c...
+compiling LCD_4bit.c...
+compiling IRQ.c...
+compiling RTC.c...
+RTC.c(12): warning:  #1295-D: Deprecated declaration PWM_SetDutyCycle - give arg types
+RTC.c(13): warning:  #1295-D: Deprecated declaration PWM_Init - give arg types
+compiling Ultrasonic_HC_SR04.c...
+Ultrasonic_HC_SR04.c(95): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+Ultrasonic_HC_SR04.c(102): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+Ultrasonic_HC_SR04.c(110): warning:  #1-D: last line of file ends without a newline
+compiling main.c...
+main.c(12): warning:  #1295-D: Deprecated declaration PWM_SetDutyCycle - give arg types
+main.c(13): warning:  #1295-D: Deprecated declaration PWM_Init - give arg types
+main.c(14): warning:  #1295-D: Deprecated declaration updateRTCTimer - give arg types
+main.c(15): warning:  #1295-D: Deprecated declaration RTCTimerEnable - give arg types
+main.c(16): warning:  #1295-D: Deprecated declaration setupTimer - give arg types
+main.c(17): warning:  #1295-D: Deprecated declaration sendPulse - give arg types
+main.c(18): warning:  #1295-D: Deprecated declaration delayMS - give arg types
+main.c(19): warning:  #1295-D: Deprecated declaration calDistance - give arg types
+main.c(54): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+main.c(63): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+main.c(79): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+main.c(31): warning:  #550-D: variable "fed" was set but never used
+main.c(33): warning:  #177-D: variable "feeding_time_flag" was declared but never referenced
+main.c(33): warning:  #177-D: variable "pet_presence_flag" was declared but never referenced
+assembling LPC2300.s...
+linking...
+Program Size: Code=8066 RO-data=98 RW-data=52 ZI-data=1300  
+FromELF: creating hex file...
+"ADC.axf" - 0 Error(s), 19 Warning(s).
+Rebuild target 'Target 1'
+compiling Servo_MG995.c...
+compiling LCD_4bit.c...
+compiling IRQ.c...
+compiling RTC.c...
+RTC.c(12): warning:  #1295-D: Deprecated declaration PWM_SetDutyCycle - give arg types
+RTC.c(13): warning:  #1295-D: Deprecated declaration PWM_Init - give arg types
+compiling Ultrasonic_HC_SR04.c...
+Ultrasonic_HC_SR04.c(95): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+Ultrasonic_HC_SR04.c(102): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+Ultrasonic_HC_SR04.c(110): warning:  #1-D: last line of file ends without a newline
+compiling main.c...
+main.c(12): warning:  #1295-D: Deprecated declaration PWM_SetDutyCycle - give arg types
+main.c(13): warning:  #1295-D: Deprecated declaration PWM_Init - give arg types
+main.c(14): warning:  #1295-D: Deprecated declaration updateRTCTimer - give arg types
+main.c(15): warning:  #1295-D: Deprecated declaration RTCTimerEnable - give arg types
+main.c(16): warning:  #1295-D: Deprecated declaration setupTimer - give arg types
+main.c(17): warning:  #1295-D: Deprecated declaration sendPulse - give arg types
+main.c(18): warning:  #1295-D: Deprecated declaration delayMS - give arg types
+main.c(19): warning:  #1295-D: Deprecated declaration calDistance - give arg types
+main.c(54): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+main.c(63): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+main.c(79): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+main.c(31): warning:  #550-D: variable "fed" was set but never used
+main.c(33): warning:  #177-D: variable "feeding_time_flag" was declared but never referenced
+main.c(33): warning:  #177-D: variable "pet_presence_flag" was declared but never referenced
+assembling LPC2300.s...
+linking...
+Program Size: Code=8066 RO-data=98 RW-data=52 ZI-data=1300  
+FromELF: creating hex file...
+"ADC.axf" - 0 Error(s), 19 Warning(s).
+Rebuild target 'Target 1'
+compiling Servo_MG995.c...
+compiling LCD_4bit.c...
+compiling IRQ.c...
+compiling RTC.c...
+RTC.c(12): warning:  #1295-D: Deprecated declaration PWM_SetDutyCycle - give arg types
+RTC.c(13): warning:  #1295-D: Deprecated declaration PWM_Init - give arg types
+compiling Ultrasonic_HC_SR04.c...
+Ultrasonic_HC_SR04.c(95): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+Ultrasonic_HC_SR04.c(102): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+Ultrasonic_HC_SR04.c(110): warning:  #1-D: last line of file ends without a newline
+compiling main.c...
+main.c(12): warning:  #1295-D: Deprecated declaration PWM_SetDutyCycle - give arg types
+main.c(13): warning:  #1295-D: Deprecated declaration PWM_Init - give arg types
+main.c(14): warning:  #1295-D: Deprecated declaration updateRTCTimer - give arg types
+main.c(15): warning:  #1295-D: Deprecated declaration RTCTimerEnable - give arg types
+main.c(16): warning:  #1295-D: Deprecated declaration setupTimer - give arg types
+main.c(17): warning:  #1295-D: Deprecated declaration sendPulse - give arg types
+main.c(18): warning:  #1295-D: Deprecated declaration delayMS - give arg types
+main.c(19): warning:  #1295-D: Deprecated declaration calDistance - give arg types
+main.c(54): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+main.c(63): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+main.c(79): warning:  #167-D: argument of type "char *" is incompatible with parameter of type "const unsigned char *"
+main.c(31): warning:  #550-D: variable "fed" was set but never used
+main.c(33): warning:  #177-D: variable "feeding_time_flag" was declared but never referenced
+main.c(33): warning:  #177-D: variable "pet_presence_flag" was declared but never referenced
+assembling LPC2300.s...
+linking...
+Program Size: Code=8066 RO-data=98 RW-data=52 ZI-data=1300  
+FromELF: creating hex file...
+"ADC.axf" - 0 Error(s), 19 Warning(s).
diff --git a/ADC.sct b/ADC.sct
new file mode 100644
index 0000000..1ba2f83
--- /dev/null
+++ b/ADC.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x40000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/ADC.tra b/ADC.tra
new file mode 100644
index 0000000..64e3d41
--- /dev/null
+++ b/ADC.tra
@@ -0,0 +1,26 @@
+*** Creating Trace Output File 'ADC.tra' Ok.
+### Preparing for ADS-LD.
+### Creating ADS-LD Command Line
+### List of Objects: adding '"servo_mg995.o"'
+### List of Objects: adding '"lcd_4bit.o"'
+### List of Objects: adding '"irq.o"'
+### List of Objects: adding '"rtc.o"'
+### List of Objects: adding '"ultrasonic_hc_sr04.o"'
+### List of Objects: adding '"main.o"'
+### List of Objects: adding '"lpc2300.o"'
+### ADS-LD Command completed:
+--cpu ARM7TDMI "servo_mg995.o" "lcd_4bit.o" "irq.o" "rtc.o" "ultrasonic_hc_sr04.o" "main.o" "lpc2300.o" 

+--library_type=microlib --strict --scatter "ADC.sct" 

+--summary_stderr --info summarysizes --map --xref --callgraph --symbols 

+--info sizes --info totals --info unused --info veneers 

+ --list ".\ADC.map" -o ADC.axf### Preparing Environment (PrepEnvAds)
+### ADS-LD Output File: 'ADC.axf'
+### ADS-LD Command File: 'ADC.lnp'
+### Checking for dirty Components...
+### Creating CmdFile 'ADC.lnp', Handle=0x0000073C
+### Writing '.lnp' file
+### ADS-LD Command file 'ADC.lnp' is ready.
+### ADS-LD: About to start ADS-LD Thread.
+### ADS-LD: executed with 0 errors
+### Updating obj list
+### LDADS_file() completed.
diff --git a/ADC_Opt.Bak b/ADC_Opt.Bak
new file mode 100644
index 0000000..243a54c
--- /dev/null
+++ b/ADC_Opt.Bak
@@ -0,0 +1,53 @@
+### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+ cExt (*.c)
+ aExt (*.s*; *.src; *.a*)
+ oExt (*.obj)
+ lExt (*.lib)
+ tExt (*.txt; *.h; *.inc)
+ pExt (*.plm)
+ CppX (*.cpp)
+ DaveTm { 0,0,0,0,0,0,0,0 }
+
+Target (Target 1), 0x0004 // Tools: 'ARM-ADS'
+GRPOPT 1,(Source Group 1),1,0,0
+GRPOPT 2,(System Calls),1,0,0
+
+OPTFFF 1,1,1,503316481,0,11,41,0,<.\Servo_MG995.c> 
+OPTFFF 1,2,1,268435457,0,0,0,0,<.\LCD_4bit.c> 
+OPTFFF 1,3,1,0,0,1,1,0,<.\RFID_PN532.c> 
+OPTFFF 1,4,1,301989889,0,0,0,0,<.\IRQ.c> 
+OPTFFF 1,5,1,318767105,0,1,70,0,<.\RTC.c> 
+OPTFFF 1,6,1,369098753,0,204,219,0,<.\Ultrasonic_HC_SR04.c> 
+OPTFFF 1,7,1,536870912,0,0,0,0,<.\main.c> 
+OPTFFF 2,8,2,738197504,0,0,0,0,<.\LPC2300.s> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,22,0,0,0,29,0,0,0,247,2,0,0,60,1,0,0 }
+
+
+TARGOPT 1, (Target 1)
+ ADSCLK=12000000
+  OPTTT 1,1,1,0
+  OPTHX 1,65535,0,0,0
+  OPTLX 79,66,8,<.\>
+  OPTOX 16
+  OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
+  OPTXL 1,1,1,1,1,1,1,0,0
+  OPTFL 1,0,1
+  OPTAX 8
+  OPTBL 0,(Data Sheet)
+  OPTBL 1,(User Manual)
+  OPTDL (SARM.DLL)(-cLPC237x)(DARMP.DLL)(-pLPC2378)(SARM.DLL)()(TARMP.DLL)(-pLPC2378)
+  OPTDBG 180222,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
+  OPTKEY 0,(DLGDARM)((135=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(145=-1,-1,-1,-1,0)(147=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(155=-1,-1,-1,-1,0)(177=-1,-1,-1,-1,0)(134=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(156=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(176=-1,-1,-1,-1,0)(178=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(169=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(137=-1,-1,-1,-1,0)(138=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(165=-1,-1,-1,-1,0)(166=-1,-1,-1,-1,0)(168=-1,-1,-1,-1,0)(141=191,61,623,629,0)(144=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
+  OPTKEY 0,(DLGTARM)((135=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(145=-1,-1,-1,-1,0)(147=-1,-1,-1,-1,0)(150=83,115,386,293,0)(152=90,124,444,426,0)(151=98,132,350,574,0)(155=-1,-1,-1,-1,0)(177=-1,-1,-1,-1,0)(134=75,107,270,293,0)(80=-1,-1,-1,-1,0)(156=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(176=-1,-1,-1,-1,0)(178=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(169=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(137=-1,-1,-1,-1,0)(138=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(165=-1,-1,-1,-1,0)(166=-1,-1,-1,-1,0)(168=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(144=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
+  OPTKEY 0,(ARMDBGFLAGS)(-T5F)
+  OPTKEY 0,(UL2ARM)(-UV0812UAE -O39 -S2 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07D000)
+  OPTWA 0,1,(AD_last,0x10)
+  OPTWA 0,2,(A_value,0x0A)
+  OPTMM 1,262,(0xE0034010)
+  OPTDF 0x1000086
+  OPTLE <>
+  OPTLC <>
+  OPTLA 0,(((PORT1 & 0x00040000) >> 18 & 0x40000) >> 18)(FF00000000000000000000000000E0FFFFFFEF410100000000000000000000000000000028504F5254312026203078303030343030303029203E3E2031380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000000000000000F03F120000000000000000000000000000000000000010030000)
+EndOpt
+
diff --git a/ADC_Target 1.dep b/ADC_Target 1.dep
new file mode 100644
index 0000000..76cc3d0
--- /dev/null
+++ b/ADC_Target 1.dep	
@@ -0,0 +1,24 @@
+Dependencies for Project 'ADC', Target 'Target 1': (DO NOT MODIFY !)
+F (.\Servo_MG995.c)(0x675BD0B4)(-c --cpu ARM7TDMI -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork 

-I C:\Universidad\Keil\ARM\RV31\INC 

-I C:\Universidad\Keil\ARM\CMSIS\Include 

-I C:\Universidad\Keil\ARM\Inc\Philips 

-o "servo_mg995.o" --omf_browse "servo_mg995.crf" --depend "servo_mg995.d")
+I (C:\Universidad\Keil\ARM\Inc\Philips\LPC23xx.h)(0x5086BE16)
+I (C:\Universidad\Keil\ARM\ARMCC\bin\..\include\stdio.h)(0x516EA50E)
+I (C:\Universidad\Keil\ARM\ARMCC\bin\..\include\stdlib.h)(0x516EA50E)
+I (LCD.h)(0x66E532C3)
+F (.\LCD_4bit.c)(0x6736D45A)(-c --cpu ARM7TDMI -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork 

-I C:\Universidad\Keil\ARM\RV31\INC 

-I C:\Universidad\Keil\ARM\CMSIS\Include 

-I C:\Universidad\Keil\ARM\Inc\Philips 

-o "lcd_4bit.o" --omf_browse "lcd_4bit.crf" --depend "lcd_4bit.d")
+I (C:\Universidad\Keil\ARM\Inc\Philips\LPC23xx.H)(0x5086BE16)
+I (C:\Universidad\Keil\ARM\ARMCC\bin\..\include\stdlib.h)(0x516EA50E)
+F (.\IRQ.c)(0x673716E8)(-c --cpu ARM7TDMI -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork 

-I C:\Universidad\Keil\ARM\RV31\INC 

-I C:\Universidad\Keil\ARM\CMSIS\Include 

-I C:\Universidad\Keil\ARM\Inc\Philips 

-o "irq.o" --omf_browse "irq.crf" --depend "irq.d")
+I (C:\Universidad\Keil\ARM\Inc\Philips\LPC23xx.H)(0x5086BE16)
+F (.\RTC.c)(0x675BD0C4)(-c --cpu ARM7TDMI -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork 

-I C:\Universidad\Keil\ARM\RV31\INC 

-I C:\Universidad\Keil\ARM\CMSIS\Include 

-I C:\Universidad\Keil\ARM\Inc\Philips 

-o "rtc.o" --omf_browse "rtc.crf" --depend "rtc.d")
+I (C:\Universidad\Keil\ARM\ARMCC\bin\..\include\stdio.h)(0x516EA50E)
+I (C:\Universidad\Keil\ARM\Inc\Philips\LPC23xx.H)(0x5086BE16)
+I (LCD.h)(0x66E532C3)
+F (.\Ultrasonic_HC_SR04.c)(0x675BD110)(-c --cpu ARM7TDMI -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork 

-I C:\Universidad\Keil\ARM\RV31\INC 

-I C:\Universidad\Keil\ARM\CMSIS\Include 

-I C:\Universidad\Keil\ARM\Inc\Philips 

-o "ultrasonic_hc_sr04.o" --omf_browse "ultrasonic_hc_sr04.crf" --depend "ultrasonic_hc_sr04.d")
+I (C:\Universidad\Keil\ARM\Inc\Philips\LPC23XX.H)(0x5086BE16)
+I (C:\Universidad\Keil\ARM\ARMCC\bin\..\include\stdio.h)(0x516EA50E)
+I (LCD.h)(0x66E532C3)
+F (.\main.c)(0x675BD147)(-c --cpu ARM7TDMI -D__EVAL -D__MICROLIB -g -O0 --apcs=interwork 

-I C:\Universidad\Keil\ARM\RV31\INC 

-I C:\Universidad\Keil\ARM\CMSIS\Include 

-I C:\Universidad\Keil\ARM\Inc\Philips 

-o "main.o" --omf_browse "main.crf" --depend "main.d")
+I (C:\Universidad\Keil\ARM\ARMCC\bin\..\include\stdio.h)(0x516EA50E)
+I (C:\Universidad\Keil\ARM\Inc\Philips\LPC23xx.H)(0x5086BE16)
+I (LCD.h)(0x66E532C3)
+F (.\LPC2300.s)(0x66E532C3)(--cpu ARM7TDMI --pd "__EVAL SETA 1" -g --apcs=interwork --pd "__MICROLIB SETA 1" 

-I C:\Universidad\Keil\ARM\RV31\INC 

-I C:\Universidad\Keil\ARM\CMSIS\Include 

-I C:\Universidad\Keil\ARM\Inc\Philips 

--list "LPC2300.lst" --xref -o "LPC2300.o" --depend "LPC2300.d")
diff --git a/ADC_Uv2.Bak b/ADC_Uv2.Bak
new file mode 100644
index 0000000..0768a65
--- /dev/null
+++ b/ADC_Uv2.Bak
@@ -0,0 +1,108 @@
+### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+Target (Target 1), 0x0004 // Tools: 'ARM-ADS'
+
+Group (Source Group 1)
+Group (System Calls)
+
+File 1,1,<.\Servo_MG995.c>
+File 1,1,<.\LCD_4bit.c>
+File 1,1,<.\RFID_PN532.c>
+File 1,1,<.\IRQ.c>
+File 1,1,<.\RTC.c>
+File 1,1,<.\Ultrasonic_HC_SR04.c>
+File 1,1,<.\main.c>
+File 2,2,<.\LPC2300.s>
+
+
+Options 1,0,0  // Target 'Target 1'
+ Device (LPC2378)
+ Vendor (NXP (founded by Philips))
+ Cpu (IRAM(0x40000000-0x40007FFF) IRAM2(0x7FE00000-0x7FE03FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))
+ FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 38400 1))
+ StupF ("STARTUP\Philips\LPC2300.s" ("Philips LPC2300 Startup Code"))
+ FlashDR (UL2ARM(-U268761108 -O7 -S0 -C0 -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07D000))
+ DevID (4153)
+ Rgf (LPC23xx.H)
+ Mem ()
+ C ()
+ A ()
+ RL ()
+ OH ()
+ DBC_IFX ()
+ DBC_CMS ()
+ DBC_AMS ()
+ DBC_LMS ()
+ UseEnv=0
+ EnvBin ()
+ EnvInc ()
+ EnvLib ()
+ EnvReg (˙Philips\)
+ OrgReg (˙Philips\)
+ TgStat=16
+ OutDir (.\)
+ OutName (ADC)
+ GenApp=1
+ GenLib=0
+ GenHex=1
+ Debug=1
+ Browse=1
+ LstDir (.\)
+ HexSel=1
+ MG32K=0
+ TGMORE=0
+ RunUsr 0 0 <>
+ RunUsr 1 0 <>
+ BrunUsr 0 0 <>
+ BrunUsr 1 0 <>
+ CrunUsr 0 0 <>
+ CrunUsr 1 0 <>
+ SVCSID <>
+ GLFLAGS=1790
+ ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ACPUTYP (ARM7TDMI)
+ RVDEV ()
+ ADSTFLGA { 0,12,16,18,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSIRAM { 0,0,0,0,64,0,128,0,0 }
+ OCMADSIROM { 1,0,0,0,0,0,0,8,0 }
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,128,0,0,0,0,0,224,127,0,64,0,0 }
+ RV_STAVEC ()
+ ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCMISC ()
+ ADSCDEFN ()
+ ADSCUDEF ()
+ ADSCINCD ()
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSAMISC ()
+ ADSADEFN ()
+ ADSAUDEF ()
+ ADSAINCD ()
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ IncBld=1
+ AlwaysBuild=0
+ GenAsm=0
+ AsmAsm=0
+ PublicsOnly=0
+ StopCode=3
+ CustArgs ()
+ LibMods ()
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSLDTA (0x00000000)
+ ADSLDDA (0x40000000)
+ ADSLDSC ()
+ ADSLDIB ()
+ ADSLDIC ()
+ ADSLDMC ()
+ ADSLDIF ()
+ ADSLDDW ()
+  OPTDL (SARM.DLL)(-cLPC237x)(DARMP.DLL)(-pLPC2378)(SARM.DLL)()(TARMP.DLL)(-pLPC2378)
+  OPTDBG 180222,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
+ FLASH1 { 9,0,0,0,1,0,0,0,0,16,0,0,0,0,0,0,0,0,0,0 }
+ FLASH2 (BIN\UL2ARM.DLL)
+ FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 38400 1))
+ FLASH4 ()
+EndOpt
+
diff --git a/Abstract.txt b/Abstract.txt
new file mode 100644
index 0000000..b838182
--- /dev/null
+++ b/Abstract.txt
@@ -0,0 +1,27 @@
+The Blinky project is a simple program for the LPC2378
+using Keil 'MCB2300' Evaluation Board and demonstrating 
+interrupt functionality.
+
+Example functionality:                                                   
+ - Clock Settings:
+   - XTAL             = 12   MHz
+   - PLL              = 288  MHz
+   - processor clock  = 48   MHz
+   - USB clock        = 48   MHz
+   - peripheral clock = 12   MHz
+ - UART1 settings
+   (baudrate = 9600, 8 data bits, 1 stop bits, no parity)
+ - Timer0 timer is activating clock_1s every 1 second, 
+   starting AD conversion (every 1 ms) and displaying 
+   bargraph on 8 LEDs, it works in interrupt mode
+ - AD conversion is done in interrupt mode
+ - AD value is sent every 1 second on UART1
+ - text is displayed to textual LCD
+ - bargraph is displayed to textual LCD, according to 
+   potentiometer position
+ - 8 LEDs state represent the potentiometer position
+ 
+The Blinky program is available in different targets:
+  Simulator:       configured for software Simulator
+  MCB2300 Flash:   runs from Internal Flash located on chip
+                   (used for production or target debugging)
diff --git a/Blinky.Opt b/Blinky.Opt
new file mode 100644
index 0000000..49f5229
--- /dev/null
+++ b/Blinky.Opt
@@ -0,0 +1,72 @@
+### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+ cExt (*.c)
+ aExt (*.s*; *.src; *.a*)
+ oExt (*.obj)
+ lExt (*.lib)
+ tExt (*.txt; *.h; *.inc)
+ pExt (*.plm)
+ CppX (*.cpp)
+ DaveTm { 0,0,0,0,0,0,0,0 }
+
+Target (Simulator), 0x0004 // Tools: 'ARM-ADS'
+Target (LPC2378 Flash), 0x0004 // Tools: 'ARM-ADS'
+GRPOPT 1,(Startup Code),1,0,0
+GRPOPT 2,(Source Code),1,0,0
+GRPOPT 3,(Documentation),1,0,0
+
+OPTFFF 1,1,2,0,0,0,0,0,<.\LPC2300.s> 
+OPTFFF 2,2,1,0,0,0,0,0,<.\Blinky.c> { 44,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,170,1,0,0,255,255,255,255,255,255,255,255,44,0,0,0,58,0,0,0,248,3,0,0,114,1,0,0 }
+OPTFFF 2,3,1,0,0,0,0,0,<.\LCD_4bit.c> { 44,0,0,0,0,0,0,0,2,0,0,0,160,0,0,0,170,1,0,0,255,255,255,255,255,255,255,255,22,0,0,0,29,0,0,0,226,3,0,0,85,1,0,0 }
+OPTFFF 2,4,1,0,0,0,0,0,<.\IRQ.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,0,0,0,204,3,0,0,56,1,0,0 }
+OPTFFF 3,5,5,16777216,0,0,0,0,<.\Abstract.txt> 
+
+
+TARGOPT 1, (Simulator)
+ ADSCLK=12000000
+  OPTTT 1,1,1,0
+  OPTHX 1,65535,0,0,0
+  OPTLX 79,66,8,<.\Flash\>
+  OPTOX 16
+  OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
+  OPTXL 1,1,1,1,1,1,1,0,0
+  OPTFL 1,0,0
+  OPTAX 8
+  OPTBL 0,(Data Sheet)
+  OPTBL 1,(User Manual)
+  OPTDL (SARM.DLL)(-cLPC237x)(DARMP.DLL)(-pLPC2378)(SARM.DLL)()(TARMP.DLL)(-pLPC2378)
+  OPTDBG 45053,0,()()()()(.\Sim.ini)()()()()() (BIN\UL2ARM.DLL)()()()
+  OPTKEY 0,(ARMDBGFLAGS)(-T5F)
+  OPTKEY 0,(DLGDARM)((135=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(145=-1,-1,-1,-1,0)(147=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(155=-1,-1,-1,-1,0)(134=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(156=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=2404,663,2992,861,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(137=-1,-1,-1,-1,0)(138=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(146=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(165=-1,-1,-1,-1,0)(166=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(143=-1,-1,-1,-1,0)(144=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
+  OPTKEY 0,(DLGTARM)((107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
+  OPTKEY 0,(UL2ARM)(-U268761108 -O7 -S0 -C0 -FO15 -FD40000000 -FC800 -FN0)
+  OPTBT 0,(Analog Input)(analog0(3.3))
+  OPTDF 0xA2
+  OPTLE <>
+  OPTLC <>
+EndOpt
+
+TARGOPT 2, (LPC2378 Flash)
+ ADSCLK=12000000
+  OPTTT 1,1,1,0
+  OPTHX 1,65535,0,0,0
+  OPTLX 79,66,8,<.\Flash\>
+  OPTOX 16
+  OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
+  OPTXL 1,1,1,1,1,1,1,0,0
+  OPTFL 1,0,1
+  OPTAX 8
+  OPTBL 0,(Data Sheet)
+  OPTBL 1,(User Manual)
+  OPTDL (SARM.DLL)(-cLPC237x)(DARMP.DLL)(-pLPC2378)(SARM.DLL)()(TARMP.DLL)(-pLPC2378)
+  OPTDBG 49150,16,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
+  OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
+  OPTKEY 0,(ARMDBGFLAGS)()
+  OPTKEY 0,(UL2ARM)(-UV1234567 -O7 -S2 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07D000)
+  OPTWA 0,1,(AD_last)
+  OPTDF 0x82
+  OPTLE <>
+  OPTLC <>
+EndOpt
+
diff --git a/ExtDll.iex b/ExtDll.iex
new file mode 100644
index 0000000..b661f48
--- /dev/null
+++ b/ExtDll.iex
@@ -0,0 +1,2 @@
+[EXTDLL]
+Count=0
diff --git a/IRQ.c b/IRQ.c
new file mode 100644
index 0000000..9509620
--- /dev/null
+++ b/IRQ.c
@@ -0,0 +1,22 @@
+#include                     /* LPC23xx definitions                */
+
+extern unsigned char clock_1s;                 /* Flag activated each second         */
+
+//int x;
+//int flag = 0;
+/* Timer0 IRQ: Executed periodically                                          */
+__irq void T0_IRQHandler (void) {
+  static int clk_cntr;
+  
+
+  clk_cntr++;
+  if (clk_cntr >= 1000) {
+    clk_cntr = 0;
+    clock_1s = 1;                       /* Activate flag every 1 second       */
+  }
+
+ T0IR        = 1;                      /* Clear interrupt flag               */
+  VICVectAddr = 0;                      /* Acknowledge Interrupt              */
+}
+
+
diff --git a/LCD.h b/LCD.h
new file mode 100644
index 0000000..2fae44c
--- /dev/null
+++ b/LCD.h
@@ -0,0 +1,19 @@
+/******************************************************************************/
+/* LCD.h Text LCD function prototypes                                         */
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2005-2006 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+
+extern void lcd_init    (void);
+extern void lcd_clear   (void);
+extern void lcd_putchar (char c);
+extern void set_cursor  (unsigned char column, unsigned char line);
+extern void lcd_print   (unsigned char const *string);
+//extern void lcd_string (char data[34]);
+/******************************************************************************/
+
diff --git a/LCD_4bit.c b/LCD_4bit.c
new file mode 100644
index 0000000..ac547ba
--- /dev/null
+++ b/LCD_4bit.c
@@ -0,0 +1,308 @@
+/******************************************************************************/
+/* LCD.c: Functions for 2 line 16 character Text LCD, with 4-bit interface    */
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2005-2006 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+#include     
+#include                  /* LPC23xx definitions               */
+
+
+/*********************** Hardware specific configuration **********************/
+
+/*------------------------- Speed dependant settings -------------------------*/
+
+/* If processor works on high frequency delay has to be increased, it can be 
+   increased by factor 2^N by this constant                                   */
+#define DELAY_2N     0
+
+/*------------------------- Text LCD size definitions ------------------------*/
+
+#define LineLen     16                  /* Width (in characters)              */
+#define NumLines     2                  /* Hight (in lines)                   */
+
+/*-------------------- LCD interface hardware definitions --------------------*/
+
+/* PINS: 
+   - DB4 = P1.24
+   - DB5 = P1.25
+   - DB6 = P1.26
+   - DB7 = P1.27
+   - E   = P1.31 (for V1 P1.30)
+   - RW  = P1.29
+   - RS  = P1.28                                                              */
+
+
+#define MCB2300_V1                      /* First version of MCB2300          */
+
+#define PIN_E                 0x80000000
+#define PIN_RW                0x20000000
+#define PIN_RS                0x10000000
+#define PINS_CTRL             0xB0000000
+#define PINS_DATA             0x0F000000
+
+#ifdef  MCB2300_V1
+  #undef  PIN_E
+  #define PIN_E               0xC0000000
+  #undef  PINS_CTRL
+  #define PINS_CTRL           0xF0000000
+#endif
+
+/* pin E  setting to 0 or 1                                                   */
+#define LCD_E(x)              ((x) ? (IOSET1 = PIN_E)  : (IOCLR1 = PIN_E) );
+
+/* pin RW setting to 0 or 1                                                   */
+#define LCD_RW(x)             ((x) ? (IOSET1 = PIN_RW) : (IOCLR1 = PIN_RW));
+
+/* pin RS setting to 0 or 1                                                   */
+#define LCD_RS(x)             ((x) ? (IOSET1 = PIN_RS) : (IOCLR1 = PIN_RS));
+
+/* Reading DATA pins                                                          */
+#define LCD_DATA_IN           ((IOPIN1 >> 24) & 0xF)
+
+/* Writing value to DATA pins                                                 */
+#define LCD_DATA_OUT(x)       IOCLR1 = PINS_DATA; IOSET1 = (x & 0xF) << 24;
+
+/* Setting all pins to output mode                                            */
+#define LCD_ALL_DIR_OUT       IODIR1  |=  PINS_CTRL | PINS_DATA;
+
+/* Setting DATA pins to input mode                                            */
+#define LCD_DATA_DIR_IN       IODIR1 &= ~PINS_DATA;
+
+/* Setting DATA pins to output mode                                           */
+#define LCD_DATA_DIR_OUT      IODIR1 |=  PINS_DATA;
+
+/******************************************************************************/
+
+
+/* 8 user defined characters to be loaded into CGRAM (used for bargraph)      */
+const unsigned char UserFont[8][8] = {
+  { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
+  { 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10 },
+  { 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18 },
+  { 0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C },
+  { 0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E },
+  { 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F },
+  { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
+  { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }
+};
+
+
+/************************ Global function definitions *************************/
+
+
+/*******************************************************************************
+* Delay in while loop cycles                                                   *
+*   Parameter:    cnt:    number of while cycles to delay                      *
+*   Return:                                                                    *
+*******************************************************************************/
+
+static void delay (int cnt)
+{
+  cnt <<= DELAY_2N;
+
+  while (cnt--);
+}
+
+
+/*******************************************************************************
+* Read status of LCD controller                                                *
+*   Parameter:    none                                                         *
+*   Return:       Status byte contains busy flag and address pointer           *
+*******************************************************************************/
+
+static unsigned char lcd_read_status (void)
+{
+  unsigned char status;
+
+  LCD_DATA_DIR_IN
+  LCD_RS(0)
+  LCD_RW(1)
+  delay(10);
+  LCD_E(1)
+  delay(10);
+  status  = LCD_DATA_IN << 4;
+  LCD_E(0)
+  delay(10);
+  LCD_E(1)
+  delay(10);
+  status |= LCD_DATA_IN;
+  LCD_E(0)
+  LCD_DATA_DIR_OUT
+  return (status);
+}
+
+
+/*******************************************************************************
+* Wait until LCD controller busy flag is 0                                     *
+*   Parameter:                                                                 *
+*   Return:       Status byte of LCD controller (busy + address)               *
+*******************************************************************************/
+
+static unsigned char wait_while_busy (void)
+{
+ unsigned char status;
+
+  do  {
+    status = lcd_read_status();
+  }  while (status & 0x80);             /* Wait for busy flag                 */
+
+  return (status);
+}
+
+
+/*******************************************************************************
+* Write 4-bits to LCD controller                                               *
+*   Parameter:    c:      command to be written                                *
+*   Return:                                                                    *
+*******************************************************************************/
+
+void lcd_write_4bit (unsigned char c)
+{
+  LCD_RW(0)
+  LCD_E(1)
+  LCD_DATA_OUT(c&0x0F)
+  delay(10);
+  LCD_E(0)
+  delay(10);
+}
+
+
+/*******************************************************************************
+* Write command to LCD controller                                              *
+*   Parameter:    c:      command to be written                                *
+*   Return:                                                                    *
+*******************************************************************************/
+
+void lcd_write_cmd (unsigned char c)
+{
+  wait_while_busy();
+
+  LCD_RS(0)
+  lcd_write_4bit (c>>4);
+  lcd_write_4bit (c);
+}
+
+
+/*******************************************************************************
+* Write data to LCD controller                                                 *
+*   Parameter:    c:      data to be written                                   *
+*   Return:                                                                    *
+*******************************************************************************/
+
+static void lcd_write_data (unsigned char c)
+{
+  wait_while_busy();
+
+  LCD_RS(1)
+  lcd_write_4bit (c>>4);
+  lcd_write_4bit (c);
+}
+
+
+/*******************************************************************************
+* Print Character to current cursor position                                   *
+*   Parameter:    c:      character to be printed                              *
+*   Return:                                                                    *
+*******************************************************************************/
+
+void lcd_putchar (char c)
+{ 
+  lcd_write_data (c);
+}
+
+
+/*******************************************************************************
+* Initialize the LCD controller                                                *
+*   Parameter:                                                                 *
+*   Return:                                                                    *
+*******************************************************************************/
+
+void lcd_init (void)
+{ 
+  int i;
+  unsigned char const *p;
+
+  /* Set all pins for LCD as outputs                                          */
+  LCD_ALL_DIR_OUT
+
+  delay (15000);
+  LCD_RS(0)
+  lcd_write_4bit (0x3);                 /* Select 4-bit interface             */
+  delay (4100);
+  lcd_write_4bit (0x3);
+  delay (100);
+  lcd_write_4bit (0x3);
+  lcd_write_4bit (0x2);
+
+  lcd_write_cmd (0x28);                 /* 2 lines, 5x8 character matrix      */
+  lcd_write_cmd (0x0C);                 /* Display ctrl:Disp=ON,Curs/Blnk=OFF */
+  lcd_write_cmd (0x06);                 /* Entry mode: Move right, no shift   */
+
+  /* Load user-specific characters into CGRAM                                 */
+  lcd_write_cmd(0x40);                  /* Set CGRAM address counter to 0     */
+  p = &UserFont[0][0];
+  for (i = 0; i < sizeof(UserFont); i++, p++)
+    lcd_putchar (*p);
+
+  lcd_write_cmd(0x80);                  /* Set DDRAM address counter to 0     */
+}
+
+
+
+/*******************************************************************************
+* Set cursor position on LCD display                                           *
+*   Parameter:    column: column position                                      *
+*                 line:   line position                                        *
+*   Return:                                                                    *
+*******************************************************************************/
+
+void set_cursor (unsigned char column, unsigned char line)
+{
+  unsigned char address;
+
+  address = (line * 40) + column;
+  address = 0x80 + (address & 0x7F);
+  lcd_write_cmd(address);               /* Set DDRAM address counter to 0     */
+}
+
+/*******************************************************************************
+* Clear the LCD display                                                        *
+*   Parameter:                                                                 *
+*   Return:                                                                    *
+*******************************************************************************/
+
+void lcd_clear (void)
+{
+  lcd_write_cmd(0x01);                  /* Display clear                      */
+  set_cursor (0, 0);
+}
+
+
+/*******************************************************************************
+* Print sting to LCD display                                                   *
+*   Parameter:    string: pointer to output string                             *
+*   Return:                                                                    *
+*******************************************************************************/
+
+void lcd_print (char *string)
+{
+  while (*string)  {
+    lcd_putchar (*string++);
+  }
+}
+
+/******************************************************************************/
+
+/*void lcd_string (char data[34])
+{
+	int i =0;
+  while (data[i])  {
+    lcd_putchar (data[i]);
+	i++;
+  }
+}*/
diff --git a/LPC2300.d b/LPC2300.d
new file mode 100644
index 0000000..918d88f
--- /dev/null
+++ b/LPC2300.d
@@ -0,0 +1 @@
+LPC2300.o: LPC2300.s
diff --git a/LPC2300.lst b/LPC2300.lst
new file mode 100644
index 0000000..195daad
--- /dev/null
+++ b/LPC2300.lst
@@ -0,0 +1,2805 @@
+
+
+
+ARM Macro Assembler    Page 1 
+
+
+    1 00000000         ;/******************************************************
+                       ***********************/
+    2 00000000         ;/* LPC2300.S: Startup file for Philips LPC2300 device s
+                       eries                 */
+    3 00000000         ;/******************************************************
+                       ***********************/
+    4 00000000         ;/* <<< Use Configuration Wizard in Context Menu >>>    
+                                             */
+    5 00000000         ;/******************************************************
+                       ***********************/
+    6 00000000         ;/* This file is part of the uVision/ARM development too
+                       ls.                   */
+    7 00000000         ;/* Copyright (c) 2007 Keil - An ARM Company. All rights
+                        reserved.            */
+    8 00000000         ;/* This software may only be used under the terms of a 
+                       valid, current,       */
+    9 00000000         ;/* end user licence from KEIL for a compatible version 
+                       of KEIL software      */
+   10 00000000         ;/* development tools. Nothing else gives you the right 
+                       to use this software. */
+   11 00000000         ;/******************************************************
+                       ***********************/
+   12 00000000         
+   13 00000000         
+   14 00000000         ;/*
+   15 00000000         ; *  The LPC2300.S code is executed after CPU Reset. Thi
+                       s file may be 
+   16 00000000         ; *  translated with the following SET symbols. In uVisi
+                       on these SET 
+   17 00000000         ; *  symbols are entered under Options - ASM - Define.
+   18 00000000         ; *
+   19 00000000         ; *  NO_CLOCK_SETUP: when set the startup code will not 
+                       initialize Clock 
+   20 00000000         ; *  (used mostly when clock is already initialized from
+                        script .ini 
+   21 00000000         ; *  file).
+   22 00000000         ; *
+   23 00000000         ; *  NO_EMC_SETUP: when set the startup code will not in
+                       itializes External 
+   24 00000000         ; *  Memory Controller (used mostly when external memory
+                        is already initialized 
+   25 00000000         ; *  and loaded from script .ini file).
+   26 00000000         ; *
+   27 00000000         ; *  RAM_INTVEC: when set the startup code copies except
+                       ion vectors 
+   28 00000000         ; *  from on-chip Flash to on-chip RAM.
+   29 00000000         ; *
+   30 00000000         ; *  REMAP: when set the startup code initializes the re
+                       gister MEMMAP 
+   31 00000000         ; *  which overwrites the settings of the CPU configurat
+                       ion pins. The 
+   32 00000000         ; *  startup and interrupt vectors are remapped from:
+   33 00000000         ; *     0x00000000  default setting (not remapped)
+   34 00000000         ; *     0x40000000  when RAM_MODE is used
+   35 00000000         ; *     0x80000000  when EXTMEM_MODE is used
+   36 00000000         ; *
+   37 00000000         ; *  EXTMEM_MODE: when set the device is configured for 
+                       code execution
+   38 00000000         ; *  from external memory starting at address 0x80000000
+
+
+
+ARM Macro Assembler    Page 2 
+
+
+                       .
+   39 00000000         ; *
+   40 00000000         ; *  RAM_MODE: when set the device is configured for cod
+                       e execution
+   41 00000000         ; *  from on-chip RAM starting at address 0x40000000. 
+   42 00000000         ; */
+   43 00000000         
+   44 00000000         
+   45 00000000         ; Standard definitions of Mode bits and Interrupt (I & F
+                       ) flags in PSRs
+   46 00000000         
+   47 00000000 00000010 
+                       Mode_USR
+                               EQU              0x10
+   48 00000000 00000011 
+                       Mode_FIQ
+                               EQU              0x11
+   49 00000000 00000012 
+                       Mode_IRQ
+                               EQU              0x12
+   50 00000000 00000013 
+                       Mode_SVC
+                               EQU              0x13
+   51 00000000 00000017 
+                       Mode_ABT
+                               EQU              0x17
+   52 00000000 0000001B 
+                       Mode_UND
+                               EQU              0x1B
+   53 00000000 0000001F 
+                       Mode_SYS
+                               EQU              0x1F
+   54 00000000         
+   55 00000000 00000080 
+                       I_Bit   EQU              0x80        ; when I bit is set
+                                                            , IRQ is disabled
+   56 00000000 00000040 
+                       F_Bit   EQU              0x40        ; when F bit is set
+                                                            , FIQ is disabled
+   57 00000000         
+   58 00000000         
+   59 00000000         ;----------------------- Memory Definitions ------------
+                       ------------------------
+   60 00000000         
+   61 00000000         ; Internal Memory Base Addresses
+   62 00000000 00000000 
+                       FLASH_BASE
+                               EQU              0x00000000
+   63 00000000 40000000 
+                       RAM_BASE
+                               EQU              0x40000000
+   64 00000000 80000000 
+                       EXTMEM_BASE
+                               EQU              0x80000000
+   65 00000000         
+   66 00000000         ; External Memory Base Addresses
+   67 00000000 80000000 
+                       STA_MEM0_BASE
+                               EQU              0x80000000
+
+
+
+ARM Macro Assembler    Page 3 
+
+
+   68 00000000 81000000 
+                       STA_MEM1_BASE
+                               EQU              0x81000000
+   69 00000000         
+   70 00000000         
+   71 00000000         ;----------------------- Stack and Heap Definitions ----
+                       ------------------------
+   72 00000000         
+   73 00000000         ;//  Stack Configuration (Stack Sizes in Bytes)
+   74 00000000         ;//    Undefined Mode      <0x0-0xFFFFFFFF:8>
+   75 00000000         ;//    Supervisor Mode     <0x0-0xFFFFFFFF:8>
+   76 00000000         ;//    Abort Mode          <0x0-0xFFFFFFFF:8>
+   77 00000000         ;//    Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
+   78 00000000         ;//    Interrupt Mode      <0x0-0xFFFFFFFF:8>
+   79 00000000         ;//    User/System Mode    <0x0-0xFFFFFFFF:8>
+   80 00000000         ;// 
+   81 00000000         
+   82 00000000 00000000 
+                       UND_Stack_Size
+                               EQU              0x00000000
+   83 00000000 00000008 
+                       SVC_Stack_Size
+                               EQU              0x00000008
+   84 00000000 00000000 
+                       ABT_Stack_Size
+                               EQU              0x00000000
+   85 00000000 00000000 
+                       FIQ_Stack_Size
+                               EQU              0x00000000
+   86 00000000 00000100 
+                       IRQ_Stack_Size
+                               EQU              0x00000100
+   87 00000000 00000400 
+                       USR_Stack_Size
+                               EQU              0x00000400
+   88 00000000         
+   90 00000000 00000108 
+                       ISR_Stack_Size
+                               EQU              (UND_Stack_Size + SVC_Stack_Siz
+e + ABT_Stack_Size +                           FIQ_Stack_Size + IRQ_Stack_Size
+)
+   91 00000000         
+   92 00000000                 AREA             STACK, NOINIT, READWRITE, ALIGN
+=3
+   93 00000000         
+   94 00000000         Stack_Mem
+                               SPACE            USR_Stack_Size
+   95 00000400         __initial_sp
+                               SPACE            ISR_Stack_Size
+   96 00000508         
+   97 00000508         Stack_Top
+   98 00000508         
+   99 00000508         
+  100 00000508         ;//  Heap Configuration
+  101 00000508         ;//     Heap Size (in Bytes) <0x0-0xFFFFFFFF>
+  102 00000508         ;// 
+  103 00000508         
+  104 00000508 00000000 
+                       Heap_Size
+
+
+
+ARM Macro Assembler    Page 4 
+
+
+                               EQU              0x00000000
+  105 00000508         
+  106 00000508                 AREA             HEAP, NOINIT, READWRITE, ALIGN=
+3
+  107 00000000         __heap_base
+  108 00000000         Heap_Mem
+                               SPACE            Heap_Size
+  109 00000000         __heap_limit
+  110 00000000         
+  111 00000000         
+  112 00000000         ;----------------------- System Control Block (SCB) Modu
+                       le Definitions ---------
+  113 00000000         
+  114 00000000 E01FC000 
+                       SCB_BASE
+                               EQU              0xE01FC000  ; SCB Base Address
+  115 00000000 00000080 
+                       PLLCON_OFS
+                               EQU              0x80        ; PLL Control Offse
+                                                            t
+  116 00000000 00000084 
+                       PLLCFG_OFS
+                               EQU              0x84        ; PLL Configuration
+                                                             Offset
+  117 00000000 00000088 
+                       PLLSTAT_OFS
+                               EQU              0x88        ; PLL Status Offset
+                                                            
+  118 00000000 0000008C 
+                       PLLFEED_OFS
+                               EQU              0x8C        ; PLL Feed Offset
+  119 00000000 00000104 
+                       CCLKCFG_OFS
+                               EQU              0x104       ; CPU Clock Divider
+                                                             Reg Offset
+  120 00000000 00000108 
+                       USBCLKCFG_OFS
+                               EQU              0x108       ; USB Clock Divider
+                                                             Reg Offset
+  121 00000000 0000010C 
+                       CLKSRCSEL_OFS
+                               EQU              0x10C       ; Clock Source Sele
+                                                            ct Reg Offset
+  122 00000000 000001A0 
+                       SCS_OFS EQU              0x1A0       ; System Control an
+                                                            d Status Reg Offset
+                                                            
+  123 00000000 000001A8 
+                       PCLKSEL0_OFS
+                               EQU              0x1A8       ; Peripheral Clock 
+                                                            Select Reg 0 Offset
+                                                            
+  124 00000000 000001AC 
+                       PCLKSEL1_OFS
+                               EQU              0x1AC       ; Peripheral Clock 
+                                                            Select Reg 1 Offset
+                                                            
+  125 00000000         
+  126 00000000 000000C0 
+
+
+
+ARM Macro Assembler    Page 5 
+
+
+                       PCON_OFS
+                               EQU              0x0C0       ; Power Mode Contro
+                                                            l Reg Offset
+  127 00000000 000000C4 
+                       PCONP_OFS
+                               EQU              0x0C4       ; Power Control for
+                                                             Periphs Reg Offset
+                                                            
+  128 00000000         
+  129 00000000         ; Constants
+  130 00000000 00000010 
+                       OSCRANGE
+                               EQU              (1<<4)      ; Oscillator Range 
+                                                            Select
+  131 00000000 00000020 
+                       OSCEN   EQU              (1<<5)      ; Main oscillator E
+                                                            nable
+  132 00000000 00000040 
+                       OSCSTAT EQU              (1<<6)      ; Main Oscillator S
+                                                            tatus
+  133 00000000 00000001 
+                       PLLCON_PLLE
+                               EQU              (1<<0)      ; PLL Enable
+  134 00000000 00000002 
+                       PLLCON_PLLC
+                               EQU              (1<<1)      ; PLL Connect
+  135 00000000 00007FFF 
+                       PLLSTAT_M
+                               EQU              (0x7FFF<<0) ; PLL M Value
+  136 00000000 00FF0000 
+                       PLLSTAT_N
+                               EQU              (0xFF<<16)  ; PLL N Value
+  137 00000000 04000000 
+                       PLLSTAT_PLOCK
+                               EQU              (1<<26)     ; PLL Lock Status
+  138 00000000         
+  139 00000000         ;//  Clock Setup
+  140 00000000         ;//    System Controls and Status Register (SCS)
+  141 00000000         ;//         OSCRANGE: Main Oscillator Range Select
+                       
+  142 00000000         ;//                     <0=>  1 MHz to 20 MHz
+  143 00000000         ;//                     <1=> 15 MHz to 24 MHz
+  144 00000000         ;//            OSCEN: Main Oscillator Enable
+  145 00000000         ;//     
+  146 00000000         ;//   
+  147 00000000         ;//
+  148 00000000         ;//    Clock Source Select Register (CLKSRCSEL)
+  149 00000000         ;//        CLKSRC: PLL Clock Source Selection
+  150 00000000         ;//                     <0=> Internal RC oscillator
+  151 00000000         ;//                     <1=> Main oscillator
+  152 00000000         ;//                     <1=> RTC oscillator
+  153 00000000         ;//   
+  154 00000000         ;//
+  155 00000000         ;//    PLL Configuration Register (PLLCFG)
+  156 00000000         ;//                      PLL_clk = (2* M * PLL_clk_sr
+                       c) / N
+  157 00000000         ;//         MSEL: PLL Multiplier Selection
+  158 00000000         ;//                     <1-32768><#-1>
+  159 00000000         ;//                      M Value
+
+
+
+ARM Macro Assembler    Page 6 
+
+
+  160 00000000         ;//        NSEL: PLL Divider Selection
+  161 00000000         ;//                     <1-256><#-1>
+  162 00000000         ;//                      N Value
+  163 00000000         ;//   
+  164 00000000         ;//
+  165 00000000         ;//    CPU Clock Configuration Register (CCLKCFG)
+  166 00000000         ;//       CCLKSEL: Divide Value for CPU Clock f
+                       rom PLL
+  167 00000000         ;//                     <1-256><#-1>
+  168 00000000         ;//   
+  169 00000000         ;//
+  170 00000000         ;//    USB Clock Configuration Register (USBCLKCFG)
+  171 00000000         ;//        USBSEL: Divide Value for USB Clock f
+                       rom PLL
+  172 00000000         ;//                     <1-16><#-1>
+  173 00000000         ;//   
+  174 00000000         ;//
+  175 00000000         ;//    Peripheral Clock Selection Register 0 (PCLKSEL
+                       0)
+  176 00000000         ;//           PCLK_WDT: Peripheral Clock Select
+                       ion for WDT
+  177 00000000         ;//                     <0=> Pclk = Cclk / 4
+  178 00000000         ;//                     <1=> Pclk = Cclk
+  179 00000000         ;//                     <2=> Pclk = Cclk / 2
+  180 00000000         ;//                     <3=> Pclk = Hclk / 8
+  181 00000000         ;//        PCLK_TIMER0: Peripheral Clock Select
+                       ion for TIMER0
+  182 00000000         ;//                     <0=> Pclk = Cclk / 4
+  183 00000000         ;//                     <1=> Pclk = Cclk
+  184 00000000         ;//                     <2=> Pclk = Cclk / 2
+  185 00000000         ;//                     <3=> Pclk = Hclk / 8
+  186 00000000         ;//        PCLK_TIMER1: Peripheral Clock Select
+                       ion for TIMER1
+  187 00000000         ;//                     <0=> Pclk = Cclk / 4
+  188 00000000         ;//                     <1=> Pclk = Cclk
+  189 00000000         ;//                     <2=> Pclk = Cclk / 2
+  190 00000000         ;//                     <3=> Pclk = Hclk / 8
+  191 00000000         ;//         PCLK_UART0: Peripheral Clock Select
+                       ion for UART0
+  192 00000000         ;//                     <0=> Pclk = Cclk / 4
+  193 00000000         ;//                     <1=> Pclk = Cclk
+  194 00000000         ;//                     <2=> Pclk = Cclk / 2
+  195 00000000         ;//                     <3=> Pclk = Hclk / 8
+  196 00000000         ;//         PCLK_UART1: Peripheral Clock Select
+                       ion for UART1
+  197 00000000         ;//                     <0=> Pclk = Cclk / 4
+  198 00000000         ;//                     <1=> Pclk = Cclk
+  199 00000000         ;//                     <2=> Pclk = Cclk / 2
+  200 00000000         ;//                     <3=> Pclk = Hclk / 8
+  201 00000000         ;//        PCLK_PWM0: Peripheral Clock Select
+                       ion for PWM0
+  202 00000000         ;//                     <0=> Pclk = Cclk / 4
+  203 00000000         ;//                     <1=> Pclk = Cclk
+  204 00000000         ;//                     <2=> Pclk = Cclk / 2
+  205 00000000         ;//                     <3=> Pclk = Hclk / 8
+  206 00000000         ;//        PCLK_PWM1: Peripheral Clock Select
+                       ion for PWM1
+  207 00000000         ;//                     <0=> Pclk = Cclk / 4
+  208 00000000         ;//                     <1=> Pclk = Cclk
+
+
+
+ARM Macro Assembler    Page 7 
+
+
+  209 00000000         ;//                     <2=> Pclk = Cclk / 2
+  210 00000000         ;//                     <3=> Pclk = Hclk / 8
+  211 00000000         ;//        PCLK_I2C0: Peripheral Clock Select
+                       ion for I2C0
+  212 00000000         ;//                     <0=> Pclk = Cclk / 4
+  213 00000000         ;//                     <1=> Pclk = Cclk
+  214 00000000         ;//                     <2=> Pclk = Cclk / 2
+  215 00000000         ;//                     <3=> Pclk = Hclk / 8
+  216 00000000         ;//         PCLK_SPI: Peripheral Clock Select
+                       ion for SPI
+  217 00000000         ;//                     <0=> Pclk = Cclk / 4
+  218 00000000         ;//                     <1=> Pclk = Cclk
+  219 00000000         ;//                     <2=> Pclk = Cclk / 2
+  220 00000000         ;//                     <3=> Pclk = Hclk / 8
+  221 00000000         ;//         PCLK_RTC: Peripheral Clock Select
+                       ion for RTC
+  222 00000000         ;//                     <0=> Pclk = Cclk / 4
+  223 00000000         ;//                     <1=> Pclk = Cclk
+  224 00000000         ;//                     <2=> Pclk = Cclk / 2
+  225 00000000         ;//                     <3=> Pclk = Hclk / 8
+  226 00000000         ;//        PCLK_SSP1: Peripheral Clock Select
+                       ion for SSP1
+  227 00000000         ;//                     <0=> Pclk = Cclk / 4
+  228 00000000         ;//                     <1=> Pclk = Cclk
+  229 00000000         ;//                     <2=> Pclk = Cclk / 2
+  230 00000000         ;//                     <3=> Pclk = Hclk / 8
+  231 00000000         ;//         PCLK_DAC: Peripheral Clock Select
+                       ion for DAC
+  232 00000000         ;//                     <0=> Pclk = Cclk / 4
+  233 00000000         ;//                     <1=> Pclk = Cclk
+  234 00000000         ;//                     <2=> Pclk = Cclk / 2
+  235 00000000         ;//                     <3=> Pclk = Hclk / 8
+  236 00000000         ;//         PCLK_ADC: Peripheral Clock Select
+                       ion for ADC
+  237 00000000         ;//                     <0=> Pclk = Cclk / 4
+  238 00000000         ;//                     <1=> Pclk = Cclk
+  239 00000000         ;//                     <2=> Pclk = Cclk / 2
+  240 00000000         ;//                     <3=> Pclk = Hclk / 8
+  241 00000000         ;//        PCLK_CAN1: Peripheral Clock Select
+                       ion for CAN1
+  242 00000000         ;//                     <0=> Pclk = Cclk / 4
+  243 00000000         ;//                     <1=> Pclk = Cclk
+  244 00000000         ;//                     <2=> Pclk = Cclk / 2
+  245 00000000         ;//                     <3=> Pclk = Hclk / 6
+  246 00000000         ;//        PCLK_CAN2: Peripheral Clock Select
+                       ion for CAN2
+  247 00000000         ;//                     <0=> Pclk = Cclk / 4
+  248 00000000         ;//                     <1=> Pclk = Cclk
+  249 00000000         ;//                     <2=> Pclk = Cclk / 2
+  250 00000000         ;//                     <3=> Pclk = Hclk / 6
+  251 00000000         ;//         PCLK_ACF: Peripheral Clock Select
+                       ion for ACF
+  252 00000000         ;//                     <0=> Pclk = Cclk / 4
+  253 00000000         ;//                     <1=> Pclk = Cclk
+  254 00000000         ;//                     <2=> Pclk = Cclk / 2
+  255 00000000         ;//                     <3=> Pclk = Hclk / 6
+  256 00000000         ;//   
+  257 00000000         ;//
+  258 00000000         ;//    Peripheral Clock Selection Register 1 (PCLKSEL
+
+
+
+ARM Macro Assembler    Page 8 
+
+
+                       1)
+  259 00000000         ;//       PCLK_BAT_RAM: Peripheral Clock Select
+                       ion for the Battery Supported RAM
+  260 00000000         ;//                     <0=> Pclk = Cclk / 4
+  261 00000000         ;//                     <1=> Pclk = Cclk
+  262 00000000         ;//                     <2=> Pclk = Cclk / 2
+  263 00000000         ;//                     <3=> Pclk = Hclk / 8
+  264 00000000         ;//          PCLK_GPIO: Peripheral Clock Select
+                       ion for GPIOs
+  265 00000000         ;//                     <0=> Pclk = Cclk / 4
+  266 00000000         ;//                     <1=> Pclk = Cclk
+  267 00000000         ;//                     <2=> Pclk = Cclk / 2
+  268 00000000         ;//                     <3=> Pclk = Hclk / 8
+  269 00000000         ;//           PCLK_PCB: Peripheral Clock Select
+                       ion for Pin Connect Block
+  270 00000000         ;//                     <0=> Pclk = Cclk / 4
+  271 00000000         ;//                     <1=> Pclk = Cclk
+  272 00000000         ;//                     <2=> Pclk = Cclk / 2
+  273 00000000         ;//                     <3=> Pclk = Hclk / 8
+  274 00000000         ;//          PCLK_I2C1: Peripheral Clock Select
+                       ion for I2C1
+  275 00000000         ;//                     <0=> Pclk = Cclk / 4
+  276 00000000         ;//                     <1=> Pclk = Cclk
+  277 00000000         ;//                     <2=> Pclk = Cclk / 2
+  278 00000000         ;//                     <3=> Pclk = Hclk / 8
+  279 00000000         ;//        PCLK_SSP0: Peripheral Clock Select
+                       ion for SSP0
+  280 00000000         ;//                     <0=> Pclk = Cclk / 4
+  281 00000000         ;//                     <1=> Pclk = Cclk
+  282 00000000         ;//                     <2=> Pclk = Cclk / 2
+  283 00000000         ;//                     <3=> Pclk = Hclk / 8
+  284 00000000         ;//      PCLK_TIMER2: Peripheral Clock Select
+                       ion for TIMER2
+  285 00000000         ;//                     <0=> Pclk = Cclk / 4
+  286 00000000         ;//                     <1=> Pclk = Cclk
+  287 00000000         ;//                     <2=> Pclk = Cclk / 2
+  288 00000000         ;//                     <3=> Pclk = Hclk / 8
+  289 00000000         ;//      PCLK_TIMER3: Peripheral Clock Select
+                       ion for TIMER3
+  290 00000000         ;//                     <0=> Pclk = Cclk / 4
+  291 00000000         ;//                     <1=> Pclk = Cclk
+  292 00000000         ;//                     <2=> Pclk = Cclk / 2
+  293 00000000         ;//                     <3=> Pclk = Hclk / 8
+  294 00000000         ;//       PCLK_UART2: Peripheral Clock Select
+                       ion for UART2
+  295 00000000         ;//                     <0=> Pclk = Cclk / 4
+  296 00000000         ;//                     <1=> Pclk = Cclk
+  297 00000000         ;//                     <2=> Pclk = Cclk / 2
+  298 00000000         ;//                     <3=> Pclk = Hclk / 8
+  299 00000000         ;//       PCLK_UART3: Peripheral Clock Select
+                       ion for UART3
+  300 00000000         ;//                     <0=> Pclk = Cclk / 4
+  301 00000000         ;//                     <1=> Pclk = Cclk
+  302 00000000         ;//                     <2=> Pclk = Cclk / 2
+  303 00000000         ;//                     <3=> Pclk = Hclk / 8
+  304 00000000         ;//        PCLK_I2C2: Peripheral Clock Select
+                       ion for I2C2
+  305 00000000         ;//                     <0=> Pclk = Cclk / 4
+  306 00000000         ;//                     <1=> Pclk = Cclk
+
+
+
+ARM Macro Assembler    Page 9 
+
+
+  307 00000000         ;//                     <2=> Pclk = Cclk / 2
+  308 00000000         ;//                     <3=> Pclk = Hclk / 8
+  309 00000000         ;//         PCLK_I2S: Peripheral Clock Select
+                       ion for I2S
+  310 00000000         ;//                     <0=> Pclk = Cclk / 4
+  311 00000000         ;//                     <1=> Pclk = Cclk
+  312 00000000         ;//                     <2=> Pclk = Cclk / 2
+  313 00000000         ;//                     <3=> Pclk = Hclk / 8
+  314 00000000         ;//         PCLK_MCI: Peripheral Clock Select
+                       ion for MCI
+  315 00000000         ;//                     <0=> Pclk = Cclk / 4
+  316 00000000         ;//                     <1=> Pclk = Cclk
+  317 00000000         ;//                     <2=> Pclk = Cclk / 2
+  318 00000000         ;//                     <3=> Pclk = Hclk / 8
+  319 00000000         ;//      PCLK_SYSCON: Peripheral Clock Select
+                       ion for System Control Block
+  320 00000000         ;//                     <0=> Pclk = Cclk / 4
+  321 00000000         ;//                     <1=> Pclk = Cclk
+  322 00000000         ;//                     <2=> Pclk = Cclk / 2
+  323 00000000         ;//                     <3=> Pclk = Hclk / 8
+  324 00000000         ;//   
+  325 00000000         ;//    Power Control for Peripherals Register (PCONP)
+                       
+  326 00000000         ;//          PCUSB: USB interface power/clock ena
+                       ble
+  327 00000000         ;//          PCENET: Ethernet block power/clock e
+                       nable
+  328 00000000         ;//          PCGPDMA: GP DMA function power/clock
+                        enable
+  329 00000000         ;//          PCSDC: SD card interface power/clock
+                        enable
+  330 00000000         ;//          PCI2S: I2S interface power/clock ena
+                       ble
+  331 00000000         ;//          PCI2C2: I2C interface 2 power/clock 
+                       enable
+  332 00000000         ;//          PCUART3: UART 3 power/clock enable
+  333 00000000         ;//          PCUART2: UART 2 power/clock enable
+  334 00000000         ;//          PCTIM3: Timer 3 power/clock enable
+  335 00000000         ;//          PCTIM2: Timer 2 power/clock enable
+  336 00000000         ;//          PCSSP0: SSP interface 0 power/clock 
+                       enable
+  337 00000000         ;//          PCI2C1: I2C interface 1 power/clock 
+                       enable
+  338 00000000         ;//          PCAN2: CAN controller 2 power/clock 
+                       enable
+  339 00000000         ;//          PCAN1: CAN controller 1 power/clock 
+                       enable
+  340 00000000         ;//          PCAD: A/D converter power/clock enab
+                       le
+  341 00000000         ;//          PCEMC: External memory controller po
+                       wer/clock enable
+  342 00000000         ;//          PCSSP1: SSP interface 1 power/clock 
+                       enable
+  343 00000000         ;//           PCRTC: RTC power/clock enable
+  344 00000000         ;//           PCSPI: SPI interface power/clock ena
+                       ble
+  345 00000000         ;//           PCI2C0: I2C interface 0 power/clock 
+                       enable
+  346 00000000         ;//           PCPWM1: PWM 1 power/clock enable
+
+
+
+ARM Macro Assembler    Page 10 
+
+
+  347 00000000         ;//           PCUART1: UART 1 power/clock enable
+  348 00000000         ;//           PCUART0: UART 0 power/clock enable
+  349 00000000         ;//           PCTIM1: Timer/Counter 1 power/clock 
+                       enable
+  350 00000000         ;//           PCTIM0: Timer/Counter 0 power/clock 
+                       enable
+  351 00000000         ;//   
+  352 00000000         ;// 
+  353 00000000 00000001 
+                       CLOCK_SETUP
+                               EQU              1
+  354 00000000 00000020 
+                       SCS_Val EQU              0x00000020
+  355 00000000 00000001 
+                       CLKSRCSEL_Val
+                               EQU              0x00000001
+  356 00000000 0000000B 
+                       PLLCFG_Val
+                               EQU              0x0000000B
+  357 00000000 00000005 
+                       CCLKCFG_Val
+                               EQU              0x00000005
+  358 00000000 00000005 
+                       USBCLKCFG_Val
+                               EQU              0x00000005
+  359 00000000 00000000 
+                       PCLKSEL0_Val
+                               EQU              0x00000000
+  360 00000000 00000000 
+                       PCLKSEL1_Val
+                               EQU              0x00000000
+  361 00000000 04280FDE 
+                       PCONP_Val
+                               EQU              0x04280FDE
+  362 00000000         
+  363 00000000         ;----------------------- Memory Accelerator Module (MAM)
+                        Definitions -----------
+  364 00000000         
+  365 00000000 E01FC000 
+                       MAM_BASE
+                               EQU              0xE01FC000  ; MAM Base Address
+  366 00000000 00000000 
+                       MAMCR_OFS
+                               EQU              0x00        ; MAM Control Offse
+                                                            t
+  367 00000000 00000004 
+                       MAMTIM_OFS
+                               EQU              0x04        ; MAM Timing Offset
+                                                            
+  368 00000000         
+  369 00000000         ;//  MAM Setup
+  370 00000000         ;//      MAM Control
+  371 00000000         ;//               <0=> Disabled
+  372 00000000         ;//               <1=> Partially Enabled
+  373 00000000         ;//               <2=> Fully Enabled
+  374 00000000         ;//                Mode
+  375 00000000         ;//      MAM Timing
+  376 00000000         ;//               <0=> Reserved  <1=> 1   <2=> 2   <3=> 
+                       3
+
+
+
+ARM Macro Assembler    Page 11 
+
+
+  377 00000000         ;//               <4=> 4         <5=> 5   <6=> 6   <7=> 
+                       7
+  378 00000000         ;//                Fetch Cycles
+  379 00000000         ;// 
+  380 00000000 00000001 
+                       MAM_SETUP
+                               EQU              1
+  381 00000000 00000002 
+                       MAMCR_Val
+                               EQU              0x00000002
+  382 00000000 00000004 
+                       MAMTIM_Val
+                               EQU              0x00000004
+  383 00000000         
+  384 00000000         
+  385 00000000         ;----------------------- Pin Connect Block Definitions -
+                       ------------------------
+  386 00000000         
+  387 00000000 E002C000 
+                       PCB_BASE
+                               EQU              0xE002C000  ; PCB Base Address
+  388 00000000 00000000 
+                       PINSEL0_OFS
+                               EQU              0x00        ; PINSEL0  Address 
+                                                            Offset
+  389 00000000 00000004 
+                       PINSEL1_OFS
+                               EQU              0x04        ; PINSEL1  Address 
+                                                            Offset
+  390 00000000 00000008 
+                       PINSEL2_OFS
+                               EQU              0x08        ; PINSEL2  Address 
+                                                            Offset
+  391 00000000 0000000C 
+                       PINSEL3_OFS
+                               EQU              0x0C        ; PINSEL3  Address 
+                                                            Offset
+  392 00000000 00000010 
+                       PINSEL4_OFS
+                               EQU              0x10        ; PINSEL4  Address 
+                                                            Offset
+  393 00000000 00000014 
+                       PINSEL5_OFS
+                               EQU              0x14        ; PINSEL5  Address 
+                                                            Offset
+  394 00000000 00000018 
+                       PINSEL6_OFS
+                               EQU              0x18        ; PINSEL6  Address 
+                                                            Offset
+  395 00000000 0000001C 
+                       PINSEL7_OFS
+                               EQU              0x1C        ; PINSEL7  Address 
+                                                            Offset
+  396 00000000 00000020 
+                       PINSEL8_OFS
+                               EQU              0x20        ; PINSEL8  Address 
+                                                            Offset
+  397 00000000 00000024 
+                       PINSEL9_OFS
+
+
+
+ARM Macro Assembler    Page 12 
+
+
+                               EQU              0x24        ; PINSEL9  Address 
+                                                            Offset
+  398 00000000 00000028 
+                       PINSEL10_OFS
+                               EQU              0x28        ; PINSEL10 Address 
+                                                            Offset
+  399 00000000         
+  400 00000000         
+  401 00000000         ;----------------------- External Memory Controller (EMC
+                       ) Definitons -----------
+  402 00000000         
+  403 00000000 FFE08000 
+                       EMC_BASE
+                               EQU              0xFFE08000  ; EMC Base Address
+  404 00000000         
+  405 00000000 00000000 
+                       EMC_CTRL_OFS
+                               EQU              0x000       ; EMCControl
+  406 00000000 00000004 
+                       EMC_STAT_OFS
+                               EQU              0x004       ; EMCStatus
+  407 00000000 00000008 
+                       EMC_CONFIG_OFS
+                               EQU              0x008       ; EMCConfig
+  408 00000000 00000200 
+                       EMC_STA_CFG0_OFS
+                               EQU              0x200       ; EMCStaticConfig0
+  409 00000000 00000204 
+                       EMC_STA_WWEN0_OFS
+                               EQU              0x204       ; EMCStaticWaitWen0
+                                                            
+  410 00000000 00000208 
+                       EMC_STA_WOEN0_OFS
+                               EQU              0x208       ; EMCStaticWaitOen0
+                                                            
+  411 00000000 0000020C 
+                       EMC_STA_WRD0_OFS
+                               EQU              0x20C       ; EMCStaticWaitRd0
+  412 00000000 00000210 
+                       EMC_STA_WPAGE0_OFS
+                               EQU              0x210       ; EMCStaticWaitPage
+                                                            0
+  413 00000000 00000214 
+                       EMC_STA_WWR0_OFS
+                               EQU              0x214       ; EMCStaticWaitWr0
+  414 00000000 00000218 
+                       EMC_STA_WTURN0_OFS
+                               EQU              0x218       ; EMCStaticWaitTurn
+                                                            0
+  415 00000000 00000220 
+                       EMC_STA_CFG1_OFS
+                               EQU              0x220       ; EMCStaticConfig1
+  416 00000000 00000224 
+                       EMC_STA_WWEN1_OFS
+                               EQU              0x224       ; EMCStaticWaitWen1
+                                                            
+  417 00000000 00000228 
+                       EMC_STA_WOEN1_OFS
+                               EQU              0x228       ; EMCStaticWaitOen1
+
+
+
+ARM Macro Assembler    Page 13 
+
+
+                                                            
+  418 00000000 0000022C 
+                       EMC_STA_WRD1_OFS
+                               EQU              0x22C       ; EMCStaticWaitRd1
+  419 00000000 00000230 
+                       EMC_STA_WPAGE1_OFS
+                               EQU              0x230       ; EMCStaticWaitPage
+                                                            1
+  420 00000000 00000234 
+                       EMC_STA_WWR1_OFS
+                               EQU              0x234       ; EMCStaticWaitWr1
+  421 00000000 00000238 
+                       EMC_STA_WTURN1_OFS
+                               EQU              0x238       ; EMCStaticWaitTurn
+                                                            1
+  422 00000000 00000880 
+                       EMC_STA_EXT_W_OFS
+                               EQU              0x880       ; EMCStaticExtended
+                                                            Wait
+  423 00000000         
+  424 00000000 00080000 
+                       BUFEN_Const
+                               EQU              (1 << 19)   ; Buffer enable bit
+                                                            
+  425 00000000 00000800 
+                       EMC_PCONP_Const
+                               EQU              (1 << 11)   ; PCONP val to enab
+                                                            le power for EMC
+  426 00000000         
+  427 00000000         ; External Memory Pins definitions
+  428 00000000         ; pin functions for external memory interfacing
+  429 00000000 00005555 
+                       EMC_PINSEL6_Val
+                               EQU              0x00005555  ; D0 .. D7
+  430 00000000 55555555 
+                       EMC_PINSEL8_Val
+                               EQU              0x55555555  ; A0 .. A15
+  431 00000000 50090000 
+                       EMC_PINSEL9_Val
+                               EQU              0x50090000  ;     ; !OE, !WE (B
+                                                            LS0 because of erra
+                                                            ta), !CS0, !CS1
+  432 00000000         
+  433 00000000         ;//     External Memory Controller Setup (EMC) ---------
+                       ------------------------
+  434 00000000         ;//  External Memory Controller Setup (EMC)
+  435 00000000 00000001 
+                       EMC_SETUP
+                               EQU              1
+  436 00000000         
+  437 00000000         ;//    EMC Control Register (EMCControl)
+  438 00000000         ;//      Controls operation of the memory controller
+  439 00000000         ;//      L: Low-power mode enable
+  440 00000000         ;//      M: Address mirror enable
+  441 00000000         ;//      E: EMC enable
+  442 00000000         ;//   
+  443 00000000 00000001 
+                       EMC_CTRL_Val
+                               EQU              0x00000001
+
+
+
+ARM Macro Assembler    Page 14 
+
+
+  444 00000000         
+  445 00000000         ;//    EMC Configuration Register (EMCConfig)
+  446 00000000         ;//      Endian mode
+  447 00000000         ;//       <0=> Little-endian
+  448 00000000         ;//       <1=> Big-endian
+  449 00000000         ;//   
+  450 00000000 00000000 
+                       EMC_CONFIG_Val
+                               EQU              0x00000000
+  451 00000000         
+  452 00000000         ;//       Configure External Bus Behaviour for Static CS
+                       0 Area -----------------
+  453 00000000         ;//    Configure External Bus Behaviour for Static CS
+                       0 Area
+  454 00000000 00000001 
+                       EMC_STACS0_SETUP
+                               EQU              1
+  455 00000000         
+  456 00000000         ;//      Static Memory Configuration Register (EMCSta
+                       ticConfig0)
+  457 00000000         ;//        Defines the configuration information for 
+                       the static memory CS0
+  458 00000000         ;//        WP: Write protect
+  459 00000000         ;//        B: Write buffer enable
+  460 00000000         ;//        EW: Extended wait enable
+  461 00000000         ;//        PC: Chip select polarity
+  462 00000000         ;//         <0=> Active LOW chip select
+  463 00000000         ;//         <1=> Active HIGH chip select
+  464 00000000         ;//        PM: Async page mode enable
+  465 00000000         ;//        MW: Memory width
+  466 00000000         ;//         <0=> 8 bit
+  467 00000000         ;//         <1=> 16 bit
+  468 00000000         ;//         <2=> 32 bit
+  469 00000000         ;//     
+  470 00000000 00000000 
+                       EMC_STA_CFG0_Val
+                               EQU              0x00000000
+  471 00000000         
+  472 00000000         ;//      Static Memory Write Enable Delay Register (E
+                       MCStaticWaitWen0)
+  473 00000000         ;//        Selects the delay from CS0 to write enable
+                       
+  474 00000000         ;//        WAITWEN: Wait write enable <1-16> <#-
+                       1>
+  475 00000000         ;//          The delay is in CCLK cycles
+  476 00000000         ;//     
+  477 00000000 00000002 
+                       EMC_STA_WWEN0_Val
+                               EQU              0x00000002
+  478 00000000         
+  479 00000000         ;//      Static Memory Output Enable Delay register (
+                       EMCStaticWaitOen0)
+  480 00000000         ;//        Selects the delay from CS0 or address chan
+                       ge, whichever is later, to output enable
+  481 00000000         ;//        WAITOEN: Wait output enable <0-15>
+  482 00000000         ;//          The delay is in CCLK cycles
+  483 00000000         ;//     
+  484 00000000 00000002 
+                       EMC_STA_WOEN0_Val
+
+
+
+ARM Macro Assembler    Page 15 
+
+
+                               EQU              0x00000002
+  485 00000000         
+  486 00000000         ;//      Static Memory Read Delay Register (EMCStatic
+                       WaitRd0)
+  487 00000000         ;//        Selects the delay from CS0 to a read acces
+                       s
+  488 00000000         ;//        WAITRD: Non-page mode read wait state
+                       s or asynchronous page mode read first access wait state
+                       s <1-32> <#-1>
+  489 00000000         ;//          The delay is in CCLK cycles
+  490 00000000         ;//     
+  491 00000000 0000001F 
+                       EMC_STA_WRD0_Val
+                               EQU              0x0000001F
+  492 00000000         
+  493 00000000         ;//      Static Memory Page Mode Read Delay Register 
+                       (EMCStaticWaitPage0)
+  494 00000000         ;//        Selects the delay for asynchronous page mo
+                       de sequential accesses for CS0
+  495 00000000         ;//        WAITPAGE: Asynchronous page mode read
+                        after the first read wait states <1-32> <#-1>
+  496 00000000         ;//          The delay is in CCLK cycles
+  497 00000000         ;//     
+  498 00000000 0000001F 
+                       EMC_STA_WPAGE0_Val
+                               EQU              0x0000001F
+  499 00000000         
+  500 00000000         ;//      Static Memory Write Delay Register (EMCStati
+                       cWaitWr0)
+  501 00000000         ;//        Selects the delay from CS0 to a write acce
+                       ss
+  502 00000000         ;//        WAITWR: Write wait states <2-33> <#-2
+                       >
+  503 00000000         ;//          The delay is in CCLK cycles
+  504 00000000         ;//     
+  505 00000000 0000001F 
+                       EMC_STA_WWR0_Val
+                               EQU              0x0000001F
+  506 00000000         
+  507 00000000         ;//      Static Memory Turn Round Delay Register (EMC
+                       StaticWaitTurn0)
+  508 00000000         ;//        Selects the number of bus turnaround cycle
+                       s for CS0
+  509 00000000         ;//        WAITTURN: Bus turnaround cycles <1-16
+                       > <#-1>
+  510 00000000         ;//          The delay is in CCLK cycles
+  511 00000000         ;//     
+  512 00000000 0000000F 
+                       EMC_STA_WTURN0_Val
+                               EQU              0x0000000F
+  513 00000000         
+  514 00000000         ;//    End of Static Setup for Static CS0 Area
+  515 00000000         
+  516 00000000         ;//       Configure External Bus Behaviour for Static CS
+                       1 Area -----------------
+  517 00000000         ;//    Configure External Bus Behaviour for Static CS
+                       1 Area
+  518 00000000 00000000 
+                       EMC_STACS1_SETUP
+
+
+
+ARM Macro Assembler    Page 16 
+
+
+                               EQU              0
+  519 00000000         
+  520 00000000         ;//      Static Memory Configuration Register (EMCSta
+                       ticConfig1)
+  521 00000000         ;//        Defines the configuration information for 
+                       the static memory CS1
+  522 00000000         ;//        WP: Write protect
+  523 00000000         ;//        B: Write buffer enable
+  524 00000000         ;//        EW: Extended wait enable
+  525 00000000         ;//        PC: Chip select polarity
+  526 00000000         ;//         <0=> Active LOW chip select
+  527 00000000         ;//         <1=> Active HIGH chip select
+  528 00000000         ;//        PM: Async page mode enable
+  529 00000000         ;//        MW: Memory width
+  530 00000000         ;//         <0=> 8 bit
+  531 00000000         ;//         <1=> 16 bit
+  532 00000000         ;//         <2=> 32 bit
+  533 00000000         ;//     
+  534 00000000 00000000 
+                       EMC_STA_CFG1_Val
+                               EQU              0x00000000
+  535 00000000         
+  536 00000000         ;//      Static Memory Write Enable Delay Register (E
+                       MCStaticWaitWen1)
+  537 00000000         ;//        Selects the delay from CS1 to write enable
+                       
+  538 00000000         ;//        WAITWEN: Wait write enable <1-16> <#-
+                       1>
+  539 00000000         ;//          The delay is in CCLK cycles
+  540 00000000         ;//     
+  541 00000000 00000000 
+                       EMC_STA_WWEN1_Val
+                               EQU              0x00000000
+  542 00000000         
+  543 00000000         ;//      Static Memory Output Enable Delay register (
+                       EMCStaticWaitOen1)
+  544 00000000         ;//        Selects the delay from CS1 or address chan
+                       ge, whichever is later, to output enable
+  545 00000000         ;//        WAITOEN: Wait output enable <0-15>
+  546 00000000         ;//          The delay is in CCLK cycles
+  547 00000000         ;//     
+  548 00000000 00000000 
+                       EMC_STA_WOEN1_Val
+                               EQU              0x00000000
+  549 00000000         
+  550 00000000         ;//      Static Memory Read Delay Register (EMCStatic
+                       WaitRd1)
+  551 00000000         ;//        Selects the delay from CS1 to a read acces
+                       s
+  552 00000000         ;//        WAITRD: Non-page mode read wait state
+                       s or asynchronous page mode read first access wait state
+                       s <1-32> <#-1>
+  553 00000000         ;//          The delay is in CCLK cycles
+  554 00000000         ;//     
+  555 00000000 0000001F 
+                       EMC_STA_WRD1_Val
+                               EQU              0x0000001F
+  556 00000000         
+  557 00000000         ;//      Static Memory Page Mode Read Delay Register 
+
+
+
+ARM Macro Assembler    Page 17 
+
+
+                       (EMCStaticWaitPage0)
+  558 00000000         ;//        Selects the delay for asynchronous page mo
+                       de sequential accesses for CS1
+  559 00000000         ;//        WAITPAGE: Asynchronous page mode read
+                        after the first read wait states <1-32> <#-1>
+  560 00000000         ;//          The delay is in CCLK cycles
+  561 00000000         ;//     
+  562 00000000 0000001F 
+                       EMC_STA_WPAGE1_Val
+                               EQU              0x0000001F
+  563 00000000         
+  564 00000000         ;//      Static Memory Write Delay Register (EMCStati
+                       cWaitWr1)
+  565 00000000         ;//        Selects the delay from CS1 to a write acce
+                       ss
+  566 00000000         ;//        WAITWR: Write wait states <2-33> <#-2
+                       >
+  567 00000000         ;//          The delay is in CCLK cycles
+  568 00000000         ;//     
+  569 00000000 0000001F 
+                       EMC_STA_WWR1_Val
+                               EQU              0x0000001F
+  570 00000000         
+  571 00000000         ;//      Static Memory Turn Round Delay Register (EMC
+                       StaticWaitTurn1)
+  572 00000000         ;//        Selects the number of bus turnaround cycle
+                       s for CS1
+  573 00000000         ;//        WAITTURN: Bus turnaround cycles <1-16
+                       > <#-1>
+  574 00000000         ;//          The delay is in CCLK cycles
+  575 00000000         ;//     
+  576 00000000 0000000F 
+                       EMC_STA_WTURN1_Val
+                               EQU              0x0000000F
+  577 00000000         
+  578 00000000         ;//    End of Static Setup for Static CS1 Area
+  579 00000000         
+  580 00000000         ;//    Static Memory Extended Wait Register (EMCStati
+                       cExtendedWait)
+  581 00000000         ;//      Time long static memory read and write trans
+                       fers
+  582 00000000         ;//      EXTENDEDWAIT: Extended wait time out <1
+                       -64><#-1>
+  583 00000000         ;//        The delay is in (16 * CCLK) cycles
+  584 00000000         ;//   
+  585 00000000 00000000 
+                       EMC_STA_EXT_W_Val
+                               EQU              0x00000000
+  586 00000000         
+  587 00000000         ;//  End of EMC Setup
+  588 00000000         
+  589 00000000         
+  590 00000000         ; Area Definition and Entry Point
+  591 00000000         ;  Startup Code must be linked first at Address at which
+                        it expects to run.
+  592 00000000         
+  593 00000000                 AREA             RESET, CODE, READONLY
+  594 00000000                 ARM
+  595 00000000         
+
+
+
+ARM Macro Assembler    Page 18 
+
+
+  596 00000000         
+  597 00000000         ; Exception Vectors
+  598 00000000         ;  Mapped to Address 0.
+  599 00000000         ;  Absolute addressing mode must be used.
+  600 00000000         ;  Dummy Handlers are implemented as infinite loops whic
+                       h can be modified.
+  601 00000000         
+  602 00000000 E59FF018 
+                       Vectors LDR              PC, Reset_Addr
+  603 00000004 E59FF018        LDR              PC, Undef_Addr
+  604 00000008 E59FF018        LDR              PC, SWI_Addr
+  605 0000000C E59FF018        LDR              PC, PAbt_Addr
+  606 00000010 E59FF018        LDR              PC, DAbt_Addr
+  607 00000014 E1A00000        NOP                          ; Reserved Vector 
+  608 00000018         ;               LDR     PC, IRQ_Addr
+  609 00000018 E51FF120        LDR              PC, [PC, #-0x0120] ; Vector fro
+                                                            m VicVectAddr
+  610 0000001C E59FF018        LDR              PC, FIQ_Addr
+  611 00000020         
+  612 00000020 00000000 
+                       Reset_Addr
+                               DCD              Reset_Handler
+  613 00000024 00000000 
+                       Undef_Addr
+                               DCD              Undef_Handler
+  614 00000028 00000000 
+                       SWI_Addr
+                               DCD              SWI_Handler
+  615 0000002C 00000000 
+                       PAbt_Addr
+                               DCD              PAbt_Handler
+  616 00000030 00000000 
+                       DAbt_Addr
+                               DCD              DAbt_Handler
+  617 00000034 00000000        DCD              0           ; Reserved Address 
+                                                            
+  618 00000038 00000000 
+                       IRQ_Addr
+                               DCD              IRQ_Handler
+  619 0000003C 00000000 
+                       FIQ_Addr
+                               DCD              FIQ_Handler
+  620 00000040         
+  621 00000040 EAFFFFFE 
+                       Undef_Handler
+                               B                Undef_Handler
+  622 00000044 EAFFFFFE 
+                       SWI_Handler
+                               B                SWI_Handler
+  623 00000048 EAFFFFFE 
+                       PAbt_Handler
+                               B                PAbt_Handler
+  624 0000004C EAFFFFFE 
+                       DAbt_Handler
+                               B                DAbt_Handler
+  625 00000050 EAFFFFFE 
+                       IRQ_Handler
+                               B                IRQ_Handler
+  626 00000054 EAFFFFFE 
+
+
+
+ARM Macro Assembler    Page 19 
+
+
+                       FIQ_Handler
+                               B                FIQ_Handler
+  627 00000058         
+  628 00000058         
+  629 00000058         ; Reset Handler
+  630 00000058         
+  631 00000058                 EXPORT           Reset_Handler
+  632 00000058         Reset_Handler
+  633 00000058         
+  634 00000058         
+  635 00000058         
+  636 00000058         ; Clock Setup ------------------------------------------
+                       ------------------------
+  637 00000058         
+  638 00000058                 IF               (:LNOT:(:DEF:NO_CLOCK_SETUP)):L
+AND:(CLOCK_SETUP != 0)
+  639 00000058 E59F019C        LDR              R0, =SCB_BASE
+  640 0000005C E3A010AA        MOV              R1, #0xAA
+  641 00000060 E3A02055        MOV              R2, #0x55
+  642 00000064         
+  643 00000064         ;  Configure and Enable PLL
+  644 00000064 E3A03020        LDR              R3, =SCS_Val ; Enable main osci
+                                                            llator
+  645 00000068 E58031A0        STR              R3, [R0, #SCS_OFS]
+  646 0000006C         
+  647 0000006C                 IF               (SCS_Val:AND:OSCEN) != 0
+  648 0000006C E59031A0 
+                       OSC_Loop
+                               LDR              R3, [R0, #SCS_OFS] ; Wait for m
+                                                            ain osc stabilize
+  649 00000070 E2133040        ANDS             R3, R3, #OSCSTAT
+  650 00000074 0AFFFFFC        BEQ              OSC_Loop
+  651 00000078                 ENDIF
+  652 00000078         
+  653 00000078 E3A03001        LDR              R3, =CLKSRCSEL_Val ; Select PLL
+                                                             source clock
+  654 0000007C E580310C        STR              R3, [R0, #CLKSRCSEL_OFS]
+  655 00000080 E3A0300B        LDR              R3, =PLLCFG_Val
+  656 00000084 E5803084        STR              R3, [R0, #PLLCFG_OFS]
+  657 00000088 E580108C        STR              R1, [R0, #PLLFEED_OFS]
+  658 0000008C E580208C        STR              R2, [R0, #PLLFEED_OFS]
+  659 00000090 E3A03001        MOV              R3, #PLLCON_PLLE
+  660 00000094 E5803080        STR              R3, [R0, #PLLCON_OFS]
+  661 00000098 E580108C        STR              R1, [R0, #PLLFEED_OFS]
+  662 0000009C E580208C        STR              R2, [R0, #PLLFEED_OFS]
+  663 000000A0         
+  664 000000A0         ;  Wait until PLL Locked
+  665 000000A0 E5903088 
+                       PLL_Loop
+                               LDR              R3, [R0, #PLLSTAT_OFS]
+  666 000000A4 E2133301        ANDS             R3, R3, #PLLSTAT_PLOCK
+  667 000000A8 0AFFFFFC        BEQ              PLL_Loop
+  668 000000AC         
+  669 000000AC E5903088 
+                       M_N_Lock
+                               LDR              R3, [R0, #PLLSTAT_OFS]
+  670 000000B0 E59F4148        LDR              R4, =(PLLSTAT_M:OR:PLLSTAT_N)
+  671 000000B4 E0033004        AND              R3, R3, R4
+  672 000000B8 E3A0400B        LDR              R4, =PLLCFG_Val
+
+
+
+ARM Macro Assembler    Page 20 
+
+
+  673 000000BC E0333004        EORS             R3, R3, R4
+  674 000000C0 1AFFFFF9        BNE              M_N_Lock
+  675 000000C4         
+  676 000000C4         ;  Setup CPU clock divider
+  677 000000C4 E3A03005        MOV              R3, #CCLKCFG_Val
+  678 000000C8 E5803104        STR              R3, [R0, #CCLKCFG_OFS]
+  679 000000CC         
+  680 000000CC         ;  Setup USB clock divider
+  681 000000CC E3A03005        LDR              R3, =USBCLKCFG_Val
+  682 000000D0 E5803108        STR              R3, [R0, #USBCLKCFG_OFS]
+  683 000000D4         
+  684 000000D4         ;  Setup Peripheral Clock
+  685 000000D4 E3A03000        LDR              R3, =PCLKSEL0_Val
+  686 000000D8 E58031A8        STR              R3, [R0, #PCLKSEL0_OFS]
+  687 000000DC E3A03000        LDR              R3, =PCLKSEL1_Val
+  688 000000E0 E58031AC        STR              R3, [R0, #PCLKSEL1_OFS]
+  689 000000E4         
+  690 000000E4         ;  Switch to PLL Clock
+  691 000000E4 E3A03003        MOV              R3, #(PLLCON_PLLE:OR:PLLCON_PLL
+C)
+  692 000000E8 E5803080        STR              R3, [R0, #PLLCON_OFS]
+  693 000000EC E580108C        STR              R1, [R0, #PLLFEED_OFS]
+  694 000000F0 E580208C        STR              R2, [R0, #PLLFEED_OFS]
+  695 000000F4         
+  696 000000F4 E59F4108        LDR              R4, =PCONP_Val ; Enable Periphe
+                                                            ral Clocks
+  697 000000F8 E58040C4        STR              R4, [R0, #PCONP_OFS]
+  698 000000FC                 ENDIF                        ; CLOCK_SETUP
+  699 000000FC         
+  700 000000FC         
+  701 000000FC         ; Setup Memory Accelerator Module ----------------------
+                       ------------------------
+  702 000000FC         
+  703 000000FC                 IF               MAM_SETUP != 0
+  704 000000FC E59F00F8        LDR              R0, =MAM_BASE
+  705 00000100 E3A01004        MOV              R1, #MAMTIM_Val
+  706 00000104 E5801004        STR              R1, [R0, #MAMTIM_OFS]
+  707 00000108 E3A01002        MOV              R1, #MAMCR_Val
+  708 0000010C E5801000        STR              R1, [R0, #MAMCR_OFS]
+  709 00000110                 ENDIF                        ; MAM_SETUP
+  710 00000110         
+  711 00000110         
+  712 00000110         ; Setup External Memory Controller ---------------------
+                       ------------------------
+  713 00000110         
+  714 00000110                 IF               (:DEF:NO_EMC_SETUP):LOR:(EMC_SE
+TUP != 0)
+  715 00000110 E59F00F0        LDR              R0, =EMC_BASE
+  716 00000114 E59F10E0        LDR              R1, =SCB_BASE
+  717 00000118 E59F20EC        LDR              R2, =PCB_BASE
+  718 0000011C         
+  719 0000011C E59140C4        LDR              R4, [R1, #PCONP_OFS]
+  720 00000120 E3844B02        ORR              R4, R4, #EMC_PCONP_Const 
+                                                            ; Enable EMC clock
+  721 00000124 E58140C4        STR              R4, [R1, #PCONP_OFS]
+  722 00000128         
+  723 00000128 E3A04001        LDR              R4, =EMC_CTRL_Val
+  724 0000012C E5804000        STR              R4, [R0, #EMC_CTRL_OFS]
+  725 00000130 E3A04000        LDR              R4, =EMC_CONFIG_Val
+
+
+
+ARM Macro Assembler    Page 21 
+
+
+  726 00000134 E5804008        STR              R4, [R0, #EMC_CONFIG_OFS]
+  727 00000138         
+  728 00000138         ;  Setup pin functions for External Bus functionality
+  729 00000138 E59F40D0        LDR              R4, =EMC_PINSEL6_Val
+  730 0000013C E5824018        STR              R4, [R2, #PINSEL6_OFS]
+  731 00000140 E59F40CC        LDR              R4, =EMC_PINSEL8_Val
+  732 00000144 E5824020        STR              R4, [R2, #PINSEL8_OFS]
+  733 00000148 E59F40C8        LDR              R4, =EMC_PINSEL9_Val
+  734 0000014C E5824024        STR              R4, [R2, #PINSEL9_OFS]
+  735 00000150         
+  736 00000150 E59F60C4        LDR              R6, =1200000 ; Number of cycles
+                                                             to delay
+  737 00000154 E2566001 
+                       Wait_0  SUBS             R6, R6, #1  ; Delay ~100 ms @ p
+                                                            roc clk 48 MHz
+  738 00000158 1AFFFFFD        BNE              Wait_0
+  739 0000015C         
+  740 0000015C                 IF               (EMC_STACS0_SETUP != 0)
+  741 0000015C E3A04000        LDR              R4, =EMC_STA_CFG0_Val
+  742 00000160 E5804200        STR              R4, [R0, #EMC_STA_CFG0_OFS]
+  743 00000164 E3A04002        LDR              R4, =EMC_STA_WWEN0_Val
+  744 00000168 E5804204        STR              R4, [R0, #EMC_STA_WWEN0_OFS]
+  745 0000016C E3A04002        LDR              R4, =EMC_STA_WOEN0_Val
+  746 00000170 E5804208        STR              R4, [R0, #EMC_STA_WOEN0_OFS]
+  747 00000174 E3A0401F        LDR              R4, =EMC_STA_WRD0_Val
+  748 00000178 E580420C        STR              R4, [R0, #EMC_STA_WRD0_OFS]
+  749 0000017C E3A0401F        LDR              R4, =EMC_STA_WPAGE0_Val
+  750 00000180 E5804210        STR              R4, [R0, #EMC_STA_WPAGE0_OFS]
+  751 00000184 E3A0401F        LDR              R4, =EMC_STA_WWR0_Val
+  752 00000188 E5804214        STR              R4, [R0, #EMC_STA_WWR0_OFS]
+  753 0000018C E3A0400F        LDR              R4, =EMC_STA_WTURN0_Val
+  754 00000190 E5804218        STR              R4, [R0, #EMC_STA_WTURN0_OFS]
+  755 00000194                 ENDIF
+  756 00000194         
+  757 00000194                 IF               (EMC_STACS1_SETUP != 0)
+  772                          ENDIF
+  773 00000194         
+  774 00000194 E59F6084        LDR              R6, =120000 ; Number of cycles 
+                                                            to delay
+  775 00000198 E2566001 
+                       Wait_1  SUBS             R6, R6, #1  ; Delay ~10 ms @ pr
+                                                            oc clk 48 MHz
+  776 0000019C 1AFFFFFD        BNE              Wait_1
+  777 000001A0         
+  778 000001A0 E3A04000        LDR              R4, =EMC_STA_EXT_W_Val
+  779 000001A4 E3A05D22        LDR              R5, =EMC_STA_EXT_W_OFS
+  780 000001A8 E0855000        ADD              R5, R5, R0
+  781 000001AC E5854000        STR              R4, [R5, #0]
+  782 000001B0         
+  783 000001B0                 ENDIF                        ; EMC_SETUP
+  784 000001B0         
+  785 000001B0         
+  786 000001B0         ; Copy Exception Vectors to Internal RAM ---------------
+                       ------------------------
+  787 000001B0         
+  788 000001B0                 IF               :DEF:RAM_INTVEC
+  795                          ENDIF
+  796 000001B0         
+  797 000001B0         
+
+
+
+ARM Macro Assembler    Page 22 
+
+
+  798 000001B0         ; Memory Mapping (when Interrupt Vectors are in RAM) ---
+                       ------------------------
+  799 000001B0         
+  800 000001B0 E01FC040 
+                       MEMMAP  EQU              0xE01FC040  ; Memory Mapping Co
+                                                            ntrol
+  801 000001B0                 IF               :DEF:REMAP
+  811                          ENDIF
+  812 000001B0         
+  813 000001B0         
+  814 000001B0         ; Setup Stack for each mode ----------------------------
+                       ------------------------
+  815 000001B0         
+  816 000001B0 E59F006C        LDR              R0, =Stack_Top
+  817 000001B4         
+  818 000001B4         ;  Enter Undefined Instruction Mode and set its Stack Po
+                       inter
+  819 000001B4 E321F0DB        MSR              CPSR_c, #Mode_UND:OR:I_Bit:OR:F
+_Bit
+  820 000001B8 E1A0D000        MOV              SP, R0
+  821 000001BC E2400000        SUB              R0, R0, #UND_Stack_Size
+  822 000001C0         
+  823 000001C0         ;  Enter Abort Mode and set its Stack Pointer
+  824 000001C0 E321F0D7        MSR              CPSR_c, #Mode_ABT:OR:I_Bit:OR:F
+_Bit
+  825 000001C4 E1A0D000        MOV              SP, R0
+  826 000001C8 E2400000        SUB              R0, R0, #ABT_Stack_Size
+  827 000001CC         
+  828 000001CC         ;  Enter FIQ Mode and set its Stack Pointer
+  829 000001CC E321F0D1        MSR              CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F
+_Bit
+  830 000001D0 E1A0D000        MOV              SP, R0
+  831 000001D4 E2400000        SUB              R0, R0, #FIQ_Stack_Size
+  832 000001D8         
+  833 000001D8         ;  Enter IRQ Mode and set its Stack Pointer
+  834 000001D8 E321F0D2        MSR              CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F
+_Bit
+  835 000001DC E1A0D000        MOV              SP, R0
+  836 000001E0 E2400C01        SUB              R0, R0, #IRQ_Stack_Size
+  837 000001E4         
+  838 000001E4         ;  Enter Supervisor Mode and set its Stack Pointer
+  839 000001E4 E321F0D3        MSR              CPSR_c, #Mode_SVC:OR:I_Bit:OR:F
+_Bit
+  840 000001E8 E1A0D000        MOV              SP, R0
+  841 000001EC E2400008        SUB              R0, R0, #SVC_Stack_Size
+  842 000001F0         
+  843 000001F0         ;  Enter User Mode and set its Stack Pointer
+  844 000001F0 E321F010        MSR              CPSR_c, #Mode_USR
+  845 000001F4                 IF               :DEF:__MICROLIB
+  846 000001F4         
+  847 000001F4                 EXPORT           __initial_sp
+  848 000001F4         
+  849 000001F4                 ELSE
+  854                          ENDIF
+  855 000001F4         
+  856 000001F4         
+  857 000001F4         ; Enter the C code -------------------------------------
+                       ------------------------
+  858 000001F4         
+
+
+
+ARM Macro Assembler    Page 23 
+
+
+  859 000001F4                 IMPORT           __main
+  860 000001F4 E59F002C        LDR              R0, =__main
+  861 000001F8 E12FFF10        BX               R0
+  862 000001FC         
+  863 000001FC         
+  864 000001FC                 IF               :DEF:__MICROLIB
+  865 000001FC         
+  866 000001FC                 EXPORT           __heap_base
+  867 000001FC                 EXPORT           __heap_limit
+  868 000001FC         
+  869 000001FC                 ELSE
+  882                          ENDIF
+  883 000001FC         
+  884 000001FC         
+  885 000001FC                 END
+              E01FC000 
+              00FF7FFF 
+              04280FDE 
+              FFE08000 
+              E002C000 
+              00005555 
+              55555555 
+              50090000 
+              00124F80 
+              0001D4C0 
+              00000000 
+              00000000 
+Command Line: --debug --xref --apcs=interwork --depend=LPC2300.d -oLPC2300.o -I
+C:\Universidad\Keil\ARM\RV31\INC -IC:\Universidad\Keil\ARM\CMSIS\Include -IC:\U
+niversidad\Keil\ARM\Inc\Philips --predefine="__EVAL SETA 1" --predefine="__MICR
+OLIB SETA 1" --list=LPC2300.lst LPC2300.s
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+STACK 00000000
+
+Symbol: STACK
+   Definitions
+      At line 92 in file LPC2300.s
+   Uses
+      None
+Comment: STACK unused
+Stack_Mem 00000000
+
+Symbol: Stack_Mem
+   Definitions
+      At line 94 in file LPC2300.s
+   Uses
+      None
+Comment: Stack_Mem unused
+Stack_Top 00000508
+
+Symbol: Stack_Top
+   Definitions
+      At line 97 in file LPC2300.s
+   Uses
+      At line 816 in file LPC2300.s
+Comment: Stack_Top used once
+__initial_sp 00000400
+
+Symbol: __initial_sp
+   Definitions
+      At line 95 in file LPC2300.s
+   Uses
+      At line 847 in file LPC2300.s
+Comment: __initial_sp used once
+4 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+HEAP 00000000
+
+Symbol: HEAP
+   Definitions
+      At line 106 in file LPC2300.s
+   Uses
+      None
+Comment: HEAP unused
+Heap_Mem 00000000
+
+Symbol: Heap_Mem
+   Definitions
+      At line 108 in file LPC2300.s
+   Uses
+      None
+Comment: Heap_Mem unused
+__heap_base 00000000
+
+Symbol: __heap_base
+   Definitions
+      At line 107 in file LPC2300.s
+   Uses
+      At line 866 in file LPC2300.s
+Comment: __heap_base used once
+__heap_limit 00000000
+
+Symbol: __heap_limit
+   Definitions
+      At line 109 in file LPC2300.s
+   Uses
+      At line 867 in file LPC2300.s
+Comment: __heap_limit used once
+4 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+DAbt_Addr 00000030
+
+Symbol: DAbt_Addr
+   Definitions
+      At line 616 in file LPC2300.s
+   Uses
+      At line 606 in file LPC2300.s
+Comment: DAbt_Addr used once
+DAbt_Handler 0000004C
+
+Symbol: DAbt_Handler
+   Definitions
+      At line 624 in file LPC2300.s
+   Uses
+      At line 616 in file LPC2300.s
+      At line 624 in file LPC2300.s
+
+FIQ_Addr 0000003C
+
+Symbol: FIQ_Addr
+   Definitions
+      At line 619 in file LPC2300.s
+   Uses
+      At line 610 in file LPC2300.s
+Comment: FIQ_Addr used once
+FIQ_Handler 00000054
+
+Symbol: FIQ_Handler
+   Definitions
+      At line 626 in file LPC2300.s
+   Uses
+      At line 619 in file LPC2300.s
+      At line 626 in file LPC2300.s
+
+IRQ_Addr 00000038
+
+Symbol: IRQ_Addr
+   Definitions
+      At line 618 in file LPC2300.s
+   Uses
+      None
+Comment: IRQ_Addr unused
+IRQ_Handler 00000050
+
+Symbol: IRQ_Handler
+   Definitions
+      At line 625 in file LPC2300.s
+   Uses
+      At line 618 in file LPC2300.s
+      At line 625 in file LPC2300.s
+
+M_N_Lock 000000AC
+
+Symbol: M_N_Lock
+   Definitions
+      At line 669 in file LPC2300.s
+   Uses
+      At line 674 in file LPC2300.s
+Comment: M_N_Lock used once
+
+
+
+ARM Macro Assembler    Page 2 Alphabetic symbol ordering
+Relocatable symbols
+
+OSC_Loop 0000006C
+
+Symbol: OSC_Loop
+   Definitions
+      At line 648 in file LPC2300.s
+   Uses
+      At line 650 in file LPC2300.s
+Comment: OSC_Loop used once
+PAbt_Addr 0000002C
+
+Symbol: PAbt_Addr
+   Definitions
+      At line 615 in file LPC2300.s
+   Uses
+      At line 605 in file LPC2300.s
+Comment: PAbt_Addr used once
+PAbt_Handler 00000048
+
+Symbol: PAbt_Handler
+   Definitions
+      At line 623 in file LPC2300.s
+   Uses
+      At line 615 in file LPC2300.s
+      At line 623 in file LPC2300.s
+
+PLL_Loop 000000A0
+
+Symbol: PLL_Loop
+   Definitions
+      At line 665 in file LPC2300.s
+   Uses
+      At line 667 in file LPC2300.s
+Comment: PLL_Loop used once
+RESET 00000000
+
+Symbol: RESET
+   Definitions
+      At line 593 in file LPC2300.s
+   Uses
+      None
+Comment: RESET unused
+Reset_Addr 00000020
+
+Symbol: Reset_Addr
+   Definitions
+      At line 612 in file LPC2300.s
+   Uses
+      At line 602 in file LPC2300.s
+Comment: Reset_Addr used once
+Reset_Handler 00000058
+
+Symbol: Reset_Handler
+   Definitions
+      At line 632 in file LPC2300.s
+   Uses
+      At line 612 in file LPC2300.s
+      At line 631 in file LPC2300.s
+
+SWI_Addr 00000028
+
+
+
+ARM Macro Assembler    Page 3 Alphabetic symbol ordering
+Relocatable symbols
+
+
+Symbol: SWI_Addr
+   Definitions
+      At line 614 in file LPC2300.s
+   Uses
+      At line 604 in file LPC2300.s
+Comment: SWI_Addr used once
+SWI_Handler 00000044
+
+Symbol: SWI_Handler
+   Definitions
+      At line 622 in file LPC2300.s
+   Uses
+      At line 614 in file LPC2300.s
+      At line 622 in file LPC2300.s
+
+Undef_Addr 00000024
+
+Symbol: Undef_Addr
+   Definitions
+      At line 613 in file LPC2300.s
+   Uses
+      At line 603 in file LPC2300.s
+Comment: Undef_Addr used once
+Undef_Handler 00000040
+
+Symbol: Undef_Handler
+   Definitions
+      At line 621 in file LPC2300.s
+   Uses
+      At line 613 in file LPC2300.s
+      At line 621 in file LPC2300.s
+
+Vectors 00000000
+
+Symbol: Vectors
+   Definitions
+      At line 602 in file LPC2300.s
+   Uses
+      None
+Comment: Vectors unused
+Wait_0 00000154
+
+Symbol: Wait_0
+   Definitions
+      At line 737 in file LPC2300.s
+   Uses
+      At line 738 in file LPC2300.s
+Comment: Wait_0 used once
+Wait_1 00000198
+
+Symbol: Wait_1
+   Definitions
+      At line 775 in file LPC2300.s
+   Uses
+      At line 776 in file LPC2300.s
+Comment: Wait_1 used once
+21 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+Absolute symbols
+
+ABT_Stack_Size 00000000
+
+Symbol: ABT_Stack_Size
+   Definitions
+      At line 84 in file LPC2300.s
+   Uses
+      At line 90 in file LPC2300.s
+      At line 826 in file LPC2300.s
+
+BUFEN_Const 00080000
+
+Symbol: BUFEN_Const
+   Definitions
+      At line 424 in file LPC2300.s
+   Uses
+      None
+Comment: BUFEN_Const unused
+CCLKCFG_OFS 00000104
+
+Symbol: CCLKCFG_OFS
+   Definitions
+      At line 119 in file LPC2300.s
+   Uses
+      At line 678 in file LPC2300.s
+Comment: CCLKCFG_OFS used once
+CCLKCFG_Val 00000005
+
+Symbol: CCLKCFG_Val
+   Definitions
+      At line 357 in file LPC2300.s
+   Uses
+      At line 677 in file LPC2300.s
+Comment: CCLKCFG_Val used once
+CLKSRCSEL_OFS 0000010C
+
+Symbol: CLKSRCSEL_OFS
+   Definitions
+      At line 121 in file LPC2300.s
+   Uses
+      At line 654 in file LPC2300.s
+Comment: CLKSRCSEL_OFS used once
+CLKSRCSEL_Val 00000001
+
+Symbol: CLKSRCSEL_Val
+   Definitions
+      At line 355 in file LPC2300.s
+   Uses
+      At line 653 in file LPC2300.s
+Comment: CLKSRCSEL_Val used once
+CLOCK_SETUP 00000001
+
+Symbol: CLOCK_SETUP
+   Definitions
+      At line 353 in file LPC2300.s
+   Uses
+      At line 638 in file LPC2300.s
+Comment: CLOCK_SETUP used once
+EMC_BASE FFE08000
+
+
+
+
+ARM Macro Assembler    Page 2 Alphabetic symbol ordering
+Absolute symbols
+
+Symbol: EMC_BASE
+   Definitions
+      At line 403 in file LPC2300.s
+   Uses
+      At line 715 in file LPC2300.s
+Comment: EMC_BASE used once
+EMC_CONFIG_OFS 00000008
+
+Symbol: EMC_CONFIG_OFS
+   Definitions
+      At line 407 in file LPC2300.s
+   Uses
+      At line 726 in file LPC2300.s
+Comment: EMC_CONFIG_OFS used once
+EMC_CONFIG_Val 00000000
+
+Symbol: EMC_CONFIG_Val
+   Definitions
+      At line 450 in file LPC2300.s
+   Uses
+      At line 725 in file LPC2300.s
+Comment: EMC_CONFIG_Val used once
+EMC_CTRL_OFS 00000000
+
+Symbol: EMC_CTRL_OFS
+   Definitions
+      At line 405 in file LPC2300.s
+   Uses
+      At line 724 in file LPC2300.s
+Comment: EMC_CTRL_OFS used once
+EMC_CTRL_Val 00000001
+
+Symbol: EMC_CTRL_Val
+   Definitions
+      At line 443 in file LPC2300.s
+   Uses
+      At line 723 in file LPC2300.s
+Comment: EMC_CTRL_Val used once
+EMC_PCONP_Const 00000800
+
+Symbol: EMC_PCONP_Const
+   Definitions
+      At line 425 in file LPC2300.s
+   Uses
+      At line 720 in file LPC2300.s
+Comment: EMC_PCONP_Const used once
+EMC_PINSEL6_Val 00005555
+
+Symbol: EMC_PINSEL6_Val
+   Definitions
+      At line 429 in file LPC2300.s
+   Uses
+      At line 729 in file LPC2300.s
+Comment: EMC_PINSEL6_Val used once
+EMC_PINSEL8_Val 55555555
+
+Symbol: EMC_PINSEL8_Val
+   Definitions
+      At line 430 in file LPC2300.s
+
+
+
+ARM Macro Assembler    Page 3 Alphabetic symbol ordering
+Absolute symbols
+
+   Uses
+      At line 731 in file LPC2300.s
+Comment: EMC_PINSEL8_Val used once
+EMC_PINSEL9_Val 50090000
+
+Symbol: EMC_PINSEL9_Val
+   Definitions
+      At line 431 in file LPC2300.s
+   Uses
+      At line 733 in file LPC2300.s
+Comment: EMC_PINSEL9_Val used once
+EMC_SETUP 00000001
+
+Symbol: EMC_SETUP
+   Definitions
+      At line 435 in file LPC2300.s
+   Uses
+      At line 714 in file LPC2300.s
+Comment: EMC_SETUP used once
+EMC_STACS0_SETUP 00000001
+
+Symbol: EMC_STACS0_SETUP
+   Definitions
+      At line 454 in file LPC2300.s
+   Uses
+      At line 740 in file LPC2300.s
+Comment: EMC_STACS0_SETUP used once
+EMC_STACS1_SETUP 00000000
+
+Symbol: EMC_STACS1_SETUP
+   Definitions
+      At line 518 in file LPC2300.s
+   Uses
+      At line 757 in file LPC2300.s
+Comment: EMC_STACS1_SETUP used once
+EMC_STAT_OFS 00000004
+
+Symbol: EMC_STAT_OFS
+   Definitions
+      At line 406 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STAT_OFS unused
+EMC_STA_CFG0_OFS 00000200
+
+Symbol: EMC_STA_CFG0_OFS
+   Definitions
+      At line 408 in file LPC2300.s
+   Uses
+      At line 742 in file LPC2300.s
+Comment: EMC_STA_CFG0_OFS used once
+EMC_STA_CFG0_Val 00000000
+
+Symbol: EMC_STA_CFG0_Val
+   Definitions
+      At line 470 in file LPC2300.s
+   Uses
+      At line 741 in file LPC2300.s
+Comment: EMC_STA_CFG0_Val used once
+
+
+
+ARM Macro Assembler    Page 4 Alphabetic symbol ordering
+Absolute symbols
+
+EMC_STA_CFG1_OFS 00000220
+
+Symbol: EMC_STA_CFG1_OFS
+   Definitions
+      At line 415 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_CFG1_OFS unused
+EMC_STA_CFG1_Val 00000000
+
+Symbol: EMC_STA_CFG1_Val
+   Definitions
+      At line 534 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_CFG1_Val unused
+EMC_STA_EXT_W_OFS 00000880
+
+Symbol: EMC_STA_EXT_W_OFS
+   Definitions
+      At line 422 in file LPC2300.s
+   Uses
+      At line 779 in file LPC2300.s
+Comment: EMC_STA_EXT_W_OFS used once
+EMC_STA_EXT_W_Val 00000000
+
+Symbol: EMC_STA_EXT_W_Val
+   Definitions
+      At line 585 in file LPC2300.s
+   Uses
+      At line 778 in file LPC2300.s
+Comment: EMC_STA_EXT_W_Val used once
+EMC_STA_WOEN0_OFS 00000208
+
+Symbol: EMC_STA_WOEN0_OFS
+   Definitions
+      At line 410 in file LPC2300.s
+   Uses
+      At line 746 in file LPC2300.s
+Comment: EMC_STA_WOEN0_OFS used once
+EMC_STA_WOEN0_Val 00000002
+
+Symbol: EMC_STA_WOEN0_Val
+   Definitions
+      At line 484 in file LPC2300.s
+   Uses
+      At line 745 in file LPC2300.s
+Comment: EMC_STA_WOEN0_Val used once
+EMC_STA_WOEN1_OFS 00000228
+
+Symbol: EMC_STA_WOEN1_OFS
+   Definitions
+      At line 417 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_WOEN1_OFS unused
+EMC_STA_WOEN1_Val 00000000
+
+Symbol: EMC_STA_WOEN1_Val
+
+
+
+ARM Macro Assembler    Page 5 Alphabetic symbol ordering
+Absolute symbols
+
+   Definitions
+      At line 548 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_WOEN1_Val unused
+EMC_STA_WPAGE0_OFS 00000210
+
+Symbol: EMC_STA_WPAGE0_OFS
+   Definitions
+      At line 412 in file LPC2300.s
+   Uses
+      At line 750 in file LPC2300.s
+Comment: EMC_STA_WPAGE0_OFS used once
+EMC_STA_WPAGE0_Val 0000001F
+
+Symbol: EMC_STA_WPAGE0_Val
+   Definitions
+      At line 498 in file LPC2300.s
+   Uses
+      At line 749 in file LPC2300.s
+Comment: EMC_STA_WPAGE0_Val used once
+EMC_STA_WPAGE1_OFS 00000230
+
+Symbol: EMC_STA_WPAGE1_OFS
+   Definitions
+      At line 419 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_WPAGE1_OFS unused
+EMC_STA_WPAGE1_Val 0000001F
+
+Symbol: EMC_STA_WPAGE1_Val
+   Definitions
+      At line 562 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_WPAGE1_Val unused
+EMC_STA_WRD0_OFS 0000020C
+
+Symbol: EMC_STA_WRD0_OFS
+   Definitions
+      At line 411 in file LPC2300.s
+   Uses
+      At line 748 in file LPC2300.s
+Comment: EMC_STA_WRD0_OFS used once
+EMC_STA_WRD0_Val 0000001F
+
+Symbol: EMC_STA_WRD0_Val
+   Definitions
+      At line 491 in file LPC2300.s
+   Uses
+      At line 747 in file LPC2300.s
+Comment: EMC_STA_WRD0_Val used once
+EMC_STA_WRD1_OFS 0000022C
+
+Symbol: EMC_STA_WRD1_OFS
+   Definitions
+      At line 418 in file LPC2300.s
+   Uses
+
+
+
+ARM Macro Assembler    Page 6 Alphabetic symbol ordering
+Absolute symbols
+
+      None
+Comment: EMC_STA_WRD1_OFS unused
+EMC_STA_WRD1_Val 0000001F
+
+Symbol: EMC_STA_WRD1_Val
+   Definitions
+      At line 555 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_WRD1_Val unused
+EMC_STA_WTURN0_OFS 00000218
+
+Symbol: EMC_STA_WTURN0_OFS
+   Definitions
+      At line 414 in file LPC2300.s
+   Uses
+      At line 754 in file LPC2300.s
+Comment: EMC_STA_WTURN0_OFS used once
+EMC_STA_WTURN0_Val 0000000F
+
+Symbol: EMC_STA_WTURN0_Val
+   Definitions
+      At line 512 in file LPC2300.s
+   Uses
+      At line 753 in file LPC2300.s
+Comment: EMC_STA_WTURN0_Val used once
+EMC_STA_WTURN1_OFS 00000238
+
+Symbol: EMC_STA_WTURN1_OFS
+   Definitions
+      At line 421 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_WTURN1_OFS unused
+EMC_STA_WTURN1_Val 0000000F
+
+Symbol: EMC_STA_WTURN1_Val
+   Definitions
+      At line 576 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_WTURN1_Val unused
+EMC_STA_WWEN0_OFS 00000204
+
+Symbol: EMC_STA_WWEN0_OFS
+   Definitions
+      At line 409 in file LPC2300.s
+   Uses
+      At line 744 in file LPC2300.s
+Comment: EMC_STA_WWEN0_OFS used once
+EMC_STA_WWEN0_Val 00000002
+
+Symbol: EMC_STA_WWEN0_Val
+   Definitions
+      At line 477 in file LPC2300.s
+   Uses
+      At line 743 in file LPC2300.s
+Comment: EMC_STA_WWEN0_Val used once
+EMC_STA_WWEN1_OFS 00000224
+
+
+
+ARM Macro Assembler    Page 7 Alphabetic symbol ordering
+Absolute symbols
+
+
+Symbol: EMC_STA_WWEN1_OFS
+   Definitions
+      At line 416 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_WWEN1_OFS unused
+EMC_STA_WWEN1_Val 00000000
+
+Symbol: EMC_STA_WWEN1_Val
+   Definitions
+      At line 541 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_WWEN1_Val unused
+EMC_STA_WWR0_OFS 00000214
+
+Symbol: EMC_STA_WWR0_OFS
+   Definitions
+      At line 413 in file LPC2300.s
+   Uses
+      At line 752 in file LPC2300.s
+Comment: EMC_STA_WWR0_OFS used once
+EMC_STA_WWR0_Val 0000001F
+
+Symbol: EMC_STA_WWR0_Val
+   Definitions
+      At line 505 in file LPC2300.s
+   Uses
+      At line 751 in file LPC2300.s
+Comment: EMC_STA_WWR0_Val used once
+EMC_STA_WWR1_OFS 00000234
+
+Symbol: EMC_STA_WWR1_OFS
+   Definitions
+      At line 420 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_WWR1_OFS unused
+EMC_STA_WWR1_Val 0000001F
+
+Symbol: EMC_STA_WWR1_Val
+   Definitions
+      At line 569 in file LPC2300.s
+   Uses
+      None
+Comment: EMC_STA_WWR1_Val unused
+EXTMEM_BASE 80000000
+
+Symbol: EXTMEM_BASE
+   Definitions
+      At line 64 in file LPC2300.s
+   Uses
+      None
+Comment: EXTMEM_BASE unused
+FIQ_Stack_Size 00000000
+
+Symbol: FIQ_Stack_Size
+   Definitions
+
+
+
+ARM Macro Assembler    Page 8 Alphabetic symbol ordering
+Absolute symbols
+
+      At line 85 in file LPC2300.s
+   Uses
+      At line 90 in file LPC2300.s
+      At line 831 in file LPC2300.s
+
+FLASH_BASE 00000000
+
+Symbol: FLASH_BASE
+   Definitions
+      At line 62 in file LPC2300.s
+   Uses
+      None
+Comment: FLASH_BASE unused
+F_Bit 00000040
+
+Symbol: F_Bit
+   Definitions
+      At line 56 in file LPC2300.s
+   Uses
+      At line 819 in file LPC2300.s
+      At line 824 in file LPC2300.s
+      At line 829 in file LPC2300.s
+      At line 834 in file LPC2300.s
+      At line 839 in file LPC2300.s
+
+Heap_Size 00000000
+
+Symbol: Heap_Size
+   Definitions
+      At line 104 in file LPC2300.s
+   Uses
+      At line 108 in file LPC2300.s
+Comment: Heap_Size used once
+IRQ_Stack_Size 00000100
+
+Symbol: IRQ_Stack_Size
+   Definitions
+      At line 86 in file LPC2300.s
+   Uses
+      At line 90 in file LPC2300.s
+      At line 836 in file LPC2300.s
+
+ISR_Stack_Size 00000108
+
+Symbol: ISR_Stack_Size
+   Definitions
+      At line 90 in file LPC2300.s
+   Uses
+      At line 95 in file LPC2300.s
+Comment: ISR_Stack_Size used once
+I_Bit 00000080
+
+Symbol: I_Bit
+   Definitions
+      At line 55 in file LPC2300.s
+   Uses
+      At line 819 in file LPC2300.s
+      At line 824 in file LPC2300.s
+      At line 829 in file LPC2300.s
+
+
+
+ARM Macro Assembler    Page 9 Alphabetic symbol ordering
+Absolute symbols
+
+      At line 834 in file LPC2300.s
+      At line 839 in file LPC2300.s
+
+MAMCR_OFS 00000000
+
+Symbol: MAMCR_OFS
+   Definitions
+      At line 366 in file LPC2300.s
+   Uses
+      At line 708 in file LPC2300.s
+Comment: MAMCR_OFS used once
+MAMCR_Val 00000002
+
+Symbol: MAMCR_Val
+   Definitions
+      At line 381 in file LPC2300.s
+   Uses
+      At line 707 in file LPC2300.s
+Comment: MAMCR_Val used once
+MAMTIM_OFS 00000004
+
+Symbol: MAMTIM_OFS
+   Definitions
+      At line 367 in file LPC2300.s
+   Uses
+      At line 706 in file LPC2300.s
+Comment: MAMTIM_OFS used once
+MAMTIM_Val 00000004
+
+Symbol: MAMTIM_Val
+   Definitions
+      At line 382 in file LPC2300.s
+   Uses
+      At line 705 in file LPC2300.s
+Comment: MAMTIM_Val used once
+MAM_BASE E01FC000
+
+Symbol: MAM_BASE
+   Definitions
+      At line 365 in file LPC2300.s
+   Uses
+      At line 704 in file LPC2300.s
+Comment: MAM_BASE used once
+MAM_SETUP 00000001
+
+Symbol: MAM_SETUP
+   Definitions
+      At line 380 in file LPC2300.s
+   Uses
+      At line 703 in file LPC2300.s
+Comment: MAM_SETUP used once
+MEMMAP E01FC040
+
+Symbol: MEMMAP
+   Definitions
+      At line 800 in file LPC2300.s
+   Uses
+      None
+Comment: MEMMAP unused
+
+
+
+ARM Macro Assembler    Page 10 Alphabetic symbol ordering
+Absolute symbols
+
+Mode_ABT 00000017
+
+Symbol: Mode_ABT
+   Definitions
+      At line 51 in file LPC2300.s
+   Uses
+      At line 824 in file LPC2300.s
+Comment: Mode_ABT used once
+Mode_FIQ 00000011
+
+Symbol: Mode_FIQ
+   Definitions
+      At line 48 in file LPC2300.s
+   Uses
+      At line 829 in file LPC2300.s
+Comment: Mode_FIQ used once
+Mode_IRQ 00000012
+
+Symbol: Mode_IRQ
+   Definitions
+      At line 49 in file LPC2300.s
+   Uses
+      At line 834 in file LPC2300.s
+Comment: Mode_IRQ used once
+Mode_SVC 00000013
+
+Symbol: Mode_SVC
+   Definitions
+      At line 50 in file LPC2300.s
+   Uses
+      At line 839 in file LPC2300.s
+Comment: Mode_SVC used once
+Mode_SYS 0000001F
+
+Symbol: Mode_SYS
+   Definitions
+      At line 53 in file LPC2300.s
+   Uses
+      None
+Comment: Mode_SYS unused
+Mode_UND 0000001B
+
+Symbol: Mode_UND
+   Definitions
+      At line 52 in file LPC2300.s
+   Uses
+      At line 819 in file LPC2300.s
+Comment: Mode_UND used once
+Mode_USR 00000010
+
+Symbol: Mode_USR
+   Definitions
+      At line 47 in file LPC2300.s
+   Uses
+      At line 844 in file LPC2300.s
+Comment: Mode_USR used once
+OSCEN 00000020
+
+Symbol: OSCEN
+
+
+
+ARM Macro Assembler    Page 11 Alphabetic symbol ordering
+Absolute symbols
+
+   Definitions
+      At line 131 in file LPC2300.s
+   Uses
+      At line 647 in file LPC2300.s
+Comment: OSCEN used once
+OSCRANGE 00000010
+
+Symbol: OSCRANGE
+   Definitions
+      At line 130 in file LPC2300.s
+   Uses
+      None
+Comment: OSCRANGE unused
+OSCSTAT 00000040
+
+Symbol: OSCSTAT
+   Definitions
+      At line 132 in file LPC2300.s
+   Uses
+      At line 649 in file LPC2300.s
+Comment: OSCSTAT used once
+PCB_BASE E002C000
+
+Symbol: PCB_BASE
+   Definitions
+      At line 387 in file LPC2300.s
+   Uses
+      At line 717 in file LPC2300.s
+Comment: PCB_BASE used once
+PCLKSEL0_OFS 000001A8
+
+Symbol: PCLKSEL0_OFS
+   Definitions
+      At line 123 in file LPC2300.s
+   Uses
+      At line 686 in file LPC2300.s
+Comment: PCLKSEL0_OFS used once
+PCLKSEL0_Val 00000000
+
+Symbol: PCLKSEL0_Val
+   Definitions
+      At line 359 in file LPC2300.s
+   Uses
+      At line 685 in file LPC2300.s
+Comment: PCLKSEL0_Val used once
+PCLKSEL1_OFS 000001AC
+
+Symbol: PCLKSEL1_OFS
+   Definitions
+      At line 124 in file LPC2300.s
+   Uses
+      At line 688 in file LPC2300.s
+Comment: PCLKSEL1_OFS used once
+PCLKSEL1_Val 00000000
+
+Symbol: PCLKSEL1_Val
+   Definitions
+      At line 360 in file LPC2300.s
+   Uses
+
+
+
+ARM Macro Assembler    Page 12 Alphabetic symbol ordering
+Absolute symbols
+
+      At line 687 in file LPC2300.s
+Comment: PCLKSEL1_Val used once
+PCONP_OFS 000000C4
+
+Symbol: PCONP_OFS
+   Definitions
+      At line 127 in file LPC2300.s
+   Uses
+      At line 697 in file LPC2300.s
+      At line 719 in file LPC2300.s
+      At line 721 in file LPC2300.s
+
+PCONP_Val 04280FDE
+
+Symbol: PCONP_Val
+   Definitions
+      At line 361 in file LPC2300.s
+   Uses
+      At line 696 in file LPC2300.s
+Comment: PCONP_Val used once
+PCON_OFS 000000C0
+
+Symbol: PCON_OFS
+   Definitions
+      At line 126 in file LPC2300.s
+   Uses
+      None
+Comment: PCON_OFS unused
+PINSEL0_OFS 00000000
+
+Symbol: PINSEL0_OFS
+   Definitions
+      At line 388 in file LPC2300.s
+   Uses
+      None
+Comment: PINSEL0_OFS unused
+PINSEL10_OFS 00000028
+
+Symbol: PINSEL10_OFS
+   Definitions
+      At line 398 in file LPC2300.s
+   Uses
+      None
+Comment: PINSEL10_OFS unused
+PINSEL1_OFS 00000004
+
+Symbol: PINSEL1_OFS
+   Definitions
+      At line 389 in file LPC2300.s
+   Uses
+      None
+Comment: PINSEL1_OFS unused
+PINSEL2_OFS 00000008
+
+Symbol: PINSEL2_OFS
+   Definitions
+      At line 390 in file LPC2300.s
+   Uses
+      None
+
+
+
+ARM Macro Assembler    Page 13 Alphabetic symbol ordering
+Absolute symbols
+
+Comment: PINSEL2_OFS unused
+PINSEL3_OFS 0000000C
+
+Symbol: PINSEL3_OFS
+   Definitions
+      At line 391 in file LPC2300.s
+   Uses
+      None
+Comment: PINSEL3_OFS unused
+PINSEL4_OFS 00000010
+
+Symbol: PINSEL4_OFS
+   Definitions
+      At line 392 in file LPC2300.s
+   Uses
+      None
+Comment: PINSEL4_OFS unused
+PINSEL5_OFS 00000014
+
+Symbol: PINSEL5_OFS
+   Definitions
+      At line 393 in file LPC2300.s
+   Uses
+      None
+Comment: PINSEL5_OFS unused
+PINSEL6_OFS 00000018
+
+Symbol: PINSEL6_OFS
+   Definitions
+      At line 394 in file LPC2300.s
+   Uses
+      At line 730 in file LPC2300.s
+Comment: PINSEL6_OFS used once
+PINSEL7_OFS 0000001C
+
+Symbol: PINSEL7_OFS
+   Definitions
+      At line 395 in file LPC2300.s
+   Uses
+      None
+Comment: PINSEL7_OFS unused
+PINSEL8_OFS 00000020
+
+Symbol: PINSEL8_OFS
+   Definitions
+      At line 396 in file LPC2300.s
+   Uses
+      At line 732 in file LPC2300.s
+Comment: PINSEL8_OFS used once
+PINSEL9_OFS 00000024
+
+Symbol: PINSEL9_OFS
+   Definitions
+      At line 397 in file LPC2300.s
+   Uses
+      At line 734 in file LPC2300.s
+Comment: PINSEL9_OFS used once
+PLLCFG_OFS 00000084
+
+
+
+
+ARM Macro Assembler    Page 14 Alphabetic symbol ordering
+Absolute symbols
+
+Symbol: PLLCFG_OFS
+   Definitions
+      At line 116 in file LPC2300.s
+   Uses
+      At line 656 in file LPC2300.s
+Comment: PLLCFG_OFS used once
+PLLCFG_Val 0000000B
+
+Symbol: PLLCFG_Val
+   Definitions
+      At line 356 in file LPC2300.s
+   Uses
+      At line 655 in file LPC2300.s
+      At line 672 in file LPC2300.s
+
+PLLCON_OFS 00000080
+
+Symbol: PLLCON_OFS
+   Definitions
+      At line 115 in file LPC2300.s
+   Uses
+      At line 660 in file LPC2300.s
+      At line 692 in file LPC2300.s
+
+PLLCON_PLLC 00000002
+
+Symbol: PLLCON_PLLC
+   Definitions
+      At line 134 in file LPC2300.s
+   Uses
+      At line 691 in file LPC2300.s
+Comment: PLLCON_PLLC used once
+PLLCON_PLLE 00000001
+
+Symbol: PLLCON_PLLE
+   Definitions
+      At line 133 in file LPC2300.s
+   Uses
+      At line 659 in file LPC2300.s
+      At line 691 in file LPC2300.s
+
+PLLFEED_OFS 0000008C
+
+Symbol: PLLFEED_OFS
+   Definitions
+      At line 118 in file LPC2300.s
+   Uses
+      At line 657 in file LPC2300.s
+      At line 658 in file LPC2300.s
+      At line 661 in file LPC2300.s
+      At line 662 in file LPC2300.s
+      At line 693 in file LPC2300.s
+      At line 694 in file LPC2300.s
+
+PLLSTAT_M 00007FFF
+
+Symbol: PLLSTAT_M
+   Definitions
+      At line 135 in file LPC2300.s
+
+
+
+ARM Macro Assembler    Page 15 Alphabetic symbol ordering
+Absolute symbols
+
+   Uses
+      At line 670 in file LPC2300.s
+Comment: PLLSTAT_M used once
+PLLSTAT_N 00FF0000
+
+Symbol: PLLSTAT_N
+   Definitions
+      At line 136 in file LPC2300.s
+   Uses
+      At line 670 in file LPC2300.s
+Comment: PLLSTAT_N used once
+PLLSTAT_OFS 00000088
+
+Symbol: PLLSTAT_OFS
+   Definitions
+      At line 117 in file LPC2300.s
+   Uses
+      At line 665 in file LPC2300.s
+      At line 669 in file LPC2300.s
+
+PLLSTAT_PLOCK 04000000
+
+Symbol: PLLSTAT_PLOCK
+   Definitions
+      At line 137 in file LPC2300.s
+   Uses
+      At line 666 in file LPC2300.s
+Comment: PLLSTAT_PLOCK used once
+RAM_BASE 40000000
+
+Symbol: RAM_BASE
+   Definitions
+      At line 63 in file LPC2300.s
+   Uses
+      None
+Comment: RAM_BASE unused
+SCB_BASE E01FC000
+
+Symbol: SCB_BASE
+   Definitions
+      At line 114 in file LPC2300.s
+   Uses
+      At line 639 in file LPC2300.s
+      At line 716 in file LPC2300.s
+
+SCS_OFS 000001A0
+
+Symbol: SCS_OFS
+   Definitions
+      At line 122 in file LPC2300.s
+   Uses
+      At line 645 in file LPC2300.s
+      At line 648 in file LPC2300.s
+
+SCS_Val 00000020
+
+Symbol: SCS_Val
+   Definitions
+      At line 354 in file LPC2300.s
+
+
+
+ARM Macro Assembler    Page 16 Alphabetic symbol ordering
+Absolute symbols
+
+   Uses
+      At line 644 in file LPC2300.s
+      At line 647 in file LPC2300.s
+
+STA_MEM0_BASE 80000000
+
+Symbol: STA_MEM0_BASE
+   Definitions
+      At line 67 in file LPC2300.s
+   Uses
+      None
+Comment: STA_MEM0_BASE unused
+STA_MEM1_BASE 81000000
+
+Symbol: STA_MEM1_BASE
+   Definitions
+      At line 68 in file LPC2300.s
+   Uses
+      None
+Comment: STA_MEM1_BASE unused
+SVC_Stack_Size 00000008
+
+Symbol: SVC_Stack_Size
+   Definitions
+      At line 83 in file LPC2300.s
+   Uses
+      At line 90 in file LPC2300.s
+      At line 841 in file LPC2300.s
+
+UND_Stack_Size 00000000
+
+Symbol: UND_Stack_Size
+   Definitions
+      At line 82 in file LPC2300.s
+   Uses
+      At line 90 in file LPC2300.s
+      At line 821 in file LPC2300.s
+
+USBCLKCFG_OFS 00000108
+
+Symbol: USBCLKCFG_OFS
+   Definitions
+      At line 120 in file LPC2300.s
+   Uses
+      At line 682 in file LPC2300.s
+Comment: USBCLKCFG_OFS used once
+USBCLKCFG_Val 00000005
+
+Symbol: USBCLKCFG_Val
+   Definitions
+      At line 358 in file LPC2300.s
+   Uses
+      At line 681 in file LPC2300.s
+Comment: USBCLKCFG_Val used once
+USR_Stack_Size 00000400
+
+Symbol: USR_Stack_Size
+   Definitions
+      At line 87 in file LPC2300.s
+
+
+
+ARM Macro Assembler    Page 17 Alphabetic symbol ordering
+Absolute symbols
+
+   Uses
+      At line 94 in file LPC2300.s
+Comment: USR_Stack_Size used once
+115 symbols
+
+
+
+ARM Macro Assembler    Page 1 Alphabetic symbol ordering
+External symbols
+
+__main 00000000
+
+Symbol: __main
+   Definitions
+      At line 859 in file LPC2300.s
+   Uses
+      At line 860 in file LPC2300.s
+Comment: __main used once
+1 symbol
+489 symbols in table
diff --git a/LPC2300.o b/LPC2300.o
new file mode 100644
index 0000000000000000000000000000000000000000..83ffaeccd81ad777c05931d1d03edaf335033f3c
GIT binary patch
literal 2960
zcmb7G&2Jk;6o2b=61PbkCk<+$QnR$1G)RfDlhBrmO5QkzSaFDnleAJ@xpus1R`r*>
zPFjT229!z&acJ+L_=tc5e?kvE^w2~3kPt#bZlb-Q9@-Ni70mC=uI(i%MLc`v_r7N4
z&Fs9l``i3NM3N+Gl0-ggOGN&C!qPD*V1)eCOCIn(v?EWpt-Xz?_DFd;DD+~;3%b7=
zjbESFK9jbsFa5RMC8f5j1Z%ss(56)j-L}HPLp#qJjr|gIJLw`3UhO;4*GzDkb4~TJ2(LBh5iU|YtJ0VFJYdYWazx0lHX|vv-yPo>e
z644TfXkTJ;zMt;?(7s6u?t$kpk;-_0XoT?~(I{gtQIOG3bcV5y=q<*6_~Wv94#A)C
zWuhwdG8&OriYFrD6Tx7>ByC|%(M(e>Wb=AuRCyy1oKP-KtsD8Aa_Y@X6git(GWCj?
zitEMFMkzI2T3IjX#j2T_)s4KezHFFAsW_QR=+(D%J*QX10?*pf6Lmu686djCxS!~%
zgC#~J!+oGk3VI|{=K=K1q>`u|C(J}0oIfQ0tblmro4A@{hmlA3`XIWDH^O9-|KO
zIY1<-Pm+B@zN5ZAsbBKrL_7hKg#hDo=rz{?dg*Cn*d_C6oq(*g#>vF?uuEop`ytp*
zoy`iGEFxlw=sKEA9fIfXfsniC7{)hAM%6mv$fI}wGJgGz?88tQRqv~&v%sf~&w*hy
zFPaA)cYxC_c?gRDA-KGk<#fx#wY@eqER(6`LtQ41>MxE>6uJ1htz>-
zP0y6md81%dn?g2Y>fn)M>5N$j_zp5GAXbm88H;g&DjFLoQARG46ICgNrBe&b6QNY>-N*}EB6G=DG8HSX)hO!cj;GVnWi77Y2s9;he6MXT7Fn2&$EIBNykS;bJIR|>1@}uE
zLYL7qS%ajbU^@`~>BZ@}71n#;Wj?Er1`#$=>
z(Gh(kI4+P)5;adE55KrqWaF*~ad+i|sC|or)LjloLp6ib)~`K3LmXoj)Bwc4?y?;mGCJCR+`q
zSPs6mfo9Yy(FB~DVn>q^1I0ETx2=L3vFGfvfqTB>gJNKr#napg>gIWQvkuAh4s)$F
P_ycN

literal 0
HcmV?d00001

diff --git a/LPC2300.s b/LPC2300.s
new file mode 100644
index 0000000..37a4b79
--- /dev/null
+++ b/LPC2300.s
@@ -0,0 +1,885 @@
+;/*****************************************************************************/
+;/* LPC2300.S: Startup file for Philips LPC2300 device series                 */
+;/*****************************************************************************/
+;/* <<< Use Configuration Wizard in Context Menu >>>                          */
+;/*****************************************************************************/
+;/* This file is part of the uVision/ARM development tools.                   */
+;/* Copyright (c) 2007 Keil - An ARM Company. All rights reserved.            */
+;/* This software may only be used under the terms of a valid, current,       */
+;/* end user licence from KEIL for a compatible version of KEIL software      */
+;/* development tools. Nothing else gives you the right to use this software. */
+;/*****************************************************************************/
+
+
+;/*
+; *  The LPC2300.S code is executed after CPU Reset. This file may be 
+; *  translated with the following SET symbols. In uVision these SET 
+; *  symbols are entered under Options - ASM - Define.
+; *
+; *  NO_CLOCK_SETUP: when set the startup code will not initialize Clock 
+; *  (used mostly when clock is already initialized from script .ini 
+; *  file).
+; *
+; *  NO_EMC_SETUP: when set the startup code will not initializes External 
+; *  Memory Controller (used mostly when external memory is already initialized 
+; *  and loaded from script .ini file).
+; *
+; *  RAM_INTVEC: when set the startup code copies exception vectors 
+; *  from on-chip Flash to on-chip RAM.
+; *
+; *  REMAP: when set the startup code initializes the register MEMMAP 
+; *  which overwrites the settings of the CPU configuration pins. The 
+; *  startup and interrupt vectors are remapped from:
+; *     0x00000000  default setting (not remapped)
+; *     0x40000000  when RAM_MODE is used
+; *     0x80000000  when EXTMEM_MODE is used
+; *
+; *  EXTMEM_MODE: when set the device is configured for code execution
+; *  from external memory starting at address 0x80000000.
+; *
+; *  RAM_MODE: when set the device is configured for code execution
+; *  from on-chip RAM starting at address 0x40000000. 
+; */
+
+
+; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
+
+Mode_USR        EQU     0x10
+Mode_FIQ        EQU     0x11
+Mode_IRQ        EQU     0x12
+Mode_SVC        EQU     0x13
+Mode_ABT        EQU     0x17
+Mode_UND        EQU     0x1B
+Mode_SYS        EQU     0x1F
+
+I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
+F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled
+
+
+;----------------------- Memory Definitions ------------------------------------
+
+; Internal Memory Base Addresses
+FLASH_BASE      EQU     0x00000000   
+RAM_BASE        EQU     0x40000000
+EXTMEM_BASE     EQU     0x80000000
+
+; External Memory Base Addresses
+STA_MEM0_BASE   EQU     0x80000000
+STA_MEM1_BASE   EQU     0x81000000
+
+
+;----------------------- Stack and Heap Definitions ----------------------------
+
+;//  Stack Configuration (Stack Sizes in Bytes)
+;//    Undefined Mode      <0x0-0xFFFFFFFF:8>
+;//    Supervisor Mode     <0x0-0xFFFFFFFF:8>
+;//    Abort Mode          <0x0-0xFFFFFFFF:8>
+;//    Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
+;//    Interrupt Mode      <0x0-0xFFFFFFFF:8>
+;//    User/System Mode    <0x0-0xFFFFFFFF:8>
+;// 
+
+UND_Stack_Size  EQU     0x00000000
+SVC_Stack_Size  EQU     0x00000008
+ABT_Stack_Size  EQU     0x00000000
+FIQ_Stack_Size  EQU     0x00000000
+IRQ_Stack_Size  EQU     0x00000100
+USR_Stack_Size  EQU     0x00000400
+
+ISR_Stack_Size  EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                         FIQ_Stack_Size + IRQ_Stack_Size)
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+
+Stack_Mem       SPACE   USR_Stack_Size
+__initial_sp    SPACE   ISR_Stack_Size
+
+Stack_Top
+
+
+;//  Heap Configuration
+;//     Heap Size (in Bytes) <0x0-0xFFFFFFFF>
+;// 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+;----------------------- System Control Block (SCB) Module Definitions ---------
+
+SCB_BASE        EQU     0xE01FC000      ; SCB Base Address
+PLLCON_OFS      EQU     0x80            ; PLL Control Offset
+PLLCFG_OFS      EQU     0x84            ; PLL Configuration Offset
+PLLSTAT_OFS     EQU     0x88            ; PLL Status Offset
+PLLFEED_OFS     EQU     0x8C            ; PLL Feed Offset
+CCLKCFG_OFS     EQU     0x104           ; CPU Clock Divider Reg Offset
+USBCLKCFG_OFS   EQU     0x108           ; USB Clock Divider Reg Offset
+CLKSRCSEL_OFS   EQU     0x10C           ; Clock Source Select Reg Offset
+SCS_OFS         EQU     0x1A0           ; System Control and Status Reg Offset
+PCLKSEL0_OFS    EQU     0x1A8           ; Peripheral Clock Select Reg 0 Offset
+PCLKSEL1_OFS    EQU     0x1AC           ; Peripheral Clock Select Reg 1 Offset
+
+PCON_OFS        EQU     0x0C0           ; Power Mode Control Reg Offset
+PCONP_OFS       EQU     0x0C4           ; Power Control for Periphs Reg Offset
+
+; Constants
+OSCRANGE        EQU     (1<<4)          ; Oscillator Range Select
+OSCEN           EQU     (1<<5)          ; Main oscillator Enable
+OSCSTAT         EQU     (1<<6)          ; Main Oscillator Status
+PLLCON_PLLE     EQU     (1<<0)          ; PLL Enable
+PLLCON_PLLC     EQU     (1<<1)          ; PLL Connect
+PLLSTAT_M       EQU     (0x7FFF<<0)     ; PLL M Value
+PLLSTAT_N       EQU     (0xFF<<16)      ; PLL N Value
+PLLSTAT_PLOCK   EQU     (1<<26)         ; PLL Lock Status
+
+;//  Clock Setup
+;//    System Controls and Status Register (SCS)
+;//         OSCRANGE: Main Oscillator Range Select
+;//                     <0=>  1 MHz to 20 MHz
+;//                     <1=> 15 MHz to 24 MHz
+;//            OSCEN: Main Oscillator Enable
+;//     
+;//   
+;//
+;//    Clock Source Select Register (CLKSRCSEL)
+;//        CLKSRC: PLL Clock Source Selection
+;//                     <0=> Internal RC oscillator
+;//                     <1=> Main oscillator
+;//                     <1=> RTC oscillator
+;//   
+;//
+;//    PLL Configuration Register (PLLCFG)
+;//                      PLL_clk = (2* M * PLL_clk_src) / N
+;//         MSEL: PLL Multiplier Selection
+;//                     <1-32768><#-1>
+;//                      M Value
+;//        NSEL: PLL Divider Selection
+;//                     <1-256><#-1>
+;//                      N Value
+;//   
+;//
+;//    CPU Clock Configuration Register (CCLKCFG)
+;//       CCLKSEL: Divide Value for CPU Clock from PLL
+;//                     <1-256><#-1>
+;//   
+;//
+;//    USB Clock Configuration Register (USBCLKCFG)
+;//        USBSEL: Divide Value for USB Clock from PLL
+;//                     <1-16><#-1>
+;//   
+;//
+;//    Peripheral Clock Selection Register 0 (PCLKSEL0)
+;//           PCLK_WDT: Peripheral Clock Selection for WDT
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//        PCLK_TIMER0: Peripheral Clock Selection for TIMER0
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//        PCLK_TIMER1: Peripheral Clock Selection for TIMER1
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//         PCLK_UART0: Peripheral Clock Selection for UART0
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//         PCLK_UART1: Peripheral Clock Selection for UART1
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//        PCLK_PWM0: Peripheral Clock Selection for PWM0
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//        PCLK_PWM1: Peripheral Clock Selection for PWM1
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//        PCLK_I2C0: Peripheral Clock Selection for I2C0
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//         PCLK_SPI: Peripheral Clock Selection for SPI
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//         PCLK_RTC: Peripheral Clock Selection for RTC
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//        PCLK_SSP1: Peripheral Clock Selection for SSP1
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//         PCLK_DAC: Peripheral Clock Selection for DAC
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//         PCLK_ADC: Peripheral Clock Selection for ADC
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//        PCLK_CAN1: Peripheral Clock Selection for CAN1
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 6
+;//        PCLK_CAN2: Peripheral Clock Selection for CAN2
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 6
+;//         PCLK_ACF: Peripheral Clock Selection for ACF
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 6
+;//   
+;//
+;//    Peripheral Clock Selection Register 1 (PCLKSEL1)
+;//       PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//          PCLK_GPIO: Peripheral Clock Selection for GPIOs
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//           PCLK_PCB: Peripheral Clock Selection for Pin Connect Block
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//          PCLK_I2C1: Peripheral Clock Selection for I2C1
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//        PCLK_SSP0: Peripheral Clock Selection for SSP0
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//      PCLK_TIMER2: Peripheral Clock Selection for TIMER2
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//      PCLK_TIMER3: Peripheral Clock Selection for TIMER3
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//       PCLK_UART2: Peripheral Clock Selection for UART2
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//       PCLK_UART3: Peripheral Clock Selection for UART3
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//        PCLK_I2C2: Peripheral Clock Selection for I2C2
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//         PCLK_I2S: Peripheral Clock Selection for I2S
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//         PCLK_MCI: Peripheral Clock Selection for MCI
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//      PCLK_SYSCON: Peripheral Clock Selection for System Control Block
+;//                     <0=> Pclk = Cclk / 4
+;//                     <1=> Pclk = Cclk
+;//                     <2=> Pclk = Cclk / 2
+;//                     <3=> Pclk = Hclk / 8
+;//   
+;//    Power Control for Peripherals Register (PCONP)
+;//          PCUSB: USB interface power/clock enable
+;//          PCENET: Ethernet block power/clock enable
+;//          PCGPDMA: GP DMA function power/clock enable
+;//          PCSDC: SD card interface power/clock enable
+;//          PCI2S: I2S interface power/clock enable
+;//          PCI2C2: I2C interface 2 power/clock enable
+;//          PCUART3: UART 3 power/clock enable
+;//          PCUART2: UART 2 power/clock enable
+;//          PCTIM3: Timer 3 power/clock enable
+;//          PCTIM2: Timer 2 power/clock enable
+;//          PCSSP0: SSP interface 0 power/clock enable
+;//          PCI2C1: I2C interface 1 power/clock enable
+;//          PCAN2: CAN controller 2 power/clock enable
+;//          PCAN1: CAN controller 1 power/clock enable
+;//          PCAD: A/D converter power/clock enable
+;//          PCEMC: External memory controller power/clock enable
+;//          PCSSP1: SSP interface 1 power/clock enable
+;//           PCRTC: RTC power/clock enable
+;//           PCSPI: SPI interface power/clock enable
+;//           PCI2C0: I2C interface 0 power/clock enable
+;//           PCPWM1: PWM 1 power/clock enable
+;//           PCUART1: UART 1 power/clock enable
+;//           PCUART0: UART 0 power/clock enable
+;//           PCTIM1: Timer/Counter 1 power/clock enable
+;//           PCTIM0: Timer/Counter 0 power/clock enable
+;//   
+;// 
+CLOCK_SETUP     EQU     1
+SCS_Val         EQU     0x00000020
+CLKSRCSEL_Val   EQU     0x00000001
+PLLCFG_Val      EQU     0x0000000B
+CCLKCFG_Val     EQU     0x00000005
+USBCLKCFG_Val   EQU     0x00000005
+PCLKSEL0_Val    EQU     0x00000000
+PCLKSEL1_Val    EQU     0x00000000
+PCONP_Val       EQU     0x04280FDE
+
+;----------------------- Memory Accelerator Module (MAM) Definitions -----------
+
+MAM_BASE        EQU     0xE01FC000      ; MAM Base Address
+MAMCR_OFS       EQU     0x00            ; MAM Control Offset
+MAMTIM_OFS      EQU     0x04            ; MAM Timing Offset
+
+;//  MAM Setup
+;//      MAM Control
+;//               <0=> Disabled
+;//               <1=> Partially Enabled
+;//               <2=> Fully Enabled
+;//                Mode
+;//      MAM Timing
+;//               <0=> Reserved  <1=> 1   <2=> 2   <3=> 3
+;//               <4=> 4         <5=> 5   <6=> 6   <7=> 7
+;//                Fetch Cycles
+;// 
+MAM_SETUP       EQU     1
+MAMCR_Val       EQU     0x00000002
+MAMTIM_Val      EQU     0x00000004
+
+
+;----------------------- Pin Connect Block Definitions -------------------------
+
+PCB_BASE            EQU 0xE002C000      ; PCB Base Address
+PINSEL0_OFS         EQU 0x00            ; PINSEL0  Address Offset
+PINSEL1_OFS         EQU 0x04            ; PINSEL1  Address Offset
+PINSEL2_OFS         EQU 0x08            ; PINSEL2  Address Offset
+PINSEL3_OFS         EQU 0x0C            ; PINSEL3  Address Offset
+PINSEL4_OFS         EQU 0x10            ; PINSEL4  Address Offset
+PINSEL5_OFS         EQU 0x14            ; PINSEL5  Address Offset
+PINSEL6_OFS         EQU 0x18            ; PINSEL6  Address Offset
+PINSEL7_OFS         EQU 0x1C            ; PINSEL7  Address Offset
+PINSEL8_OFS         EQU 0x20            ; PINSEL8  Address Offset
+PINSEL9_OFS         EQU 0x24            ; PINSEL9  Address Offset
+PINSEL10_OFS        EQU 0x28            ; PINSEL10 Address Offset
+
+
+;----------------------- External Memory Controller (EMC) Definitons -----------
+
+EMC_BASE            EQU 0xFFE08000      ; EMC Base Address
+
+EMC_CTRL_OFS        EQU 0x000           ; EMCControl
+EMC_STAT_OFS        EQU 0x004           ; EMCStatus
+EMC_CONFIG_OFS      EQU 0x008           ; EMCConfig
+EMC_STA_CFG0_OFS    EQU 0x200           ; EMCStaticConfig0
+EMC_STA_WWEN0_OFS   EQU 0x204           ; EMCStaticWaitWen0
+EMC_STA_WOEN0_OFS   EQU 0x208           ; EMCStaticWaitOen0
+EMC_STA_WRD0_OFS    EQU 0x20C           ; EMCStaticWaitRd0
+EMC_STA_WPAGE0_OFS  EQU 0x210           ; EMCStaticWaitPage0
+EMC_STA_WWR0_OFS    EQU 0x214           ; EMCStaticWaitWr0
+EMC_STA_WTURN0_OFS  EQU 0x218           ; EMCStaticWaitTurn0
+EMC_STA_CFG1_OFS    EQU 0x220           ; EMCStaticConfig1
+EMC_STA_WWEN1_OFS   EQU 0x224           ; EMCStaticWaitWen1
+EMC_STA_WOEN1_OFS   EQU 0x228           ; EMCStaticWaitOen1
+EMC_STA_WRD1_OFS    EQU 0x22C           ; EMCStaticWaitRd1
+EMC_STA_WPAGE1_OFS  EQU 0x230           ; EMCStaticWaitPage1
+EMC_STA_WWR1_OFS    EQU 0x234           ; EMCStaticWaitWr1
+EMC_STA_WTURN1_OFS  EQU 0x238           ; EMCStaticWaitTurn1
+EMC_STA_EXT_W_OFS   EQU 0x880           ; EMCStaticExtendedWait
+
+BUFEN_Const         EQU (1 << 19)       ; Buffer enable bit
+EMC_PCONP_Const     EQU (1 << 11)       ; PCONP val to enable power for EMC
+
+; External Memory Pins definitions
+; pin functions for external memory interfacing
+EMC_PINSEL6_Val     EQU 0x00005555      ; D0 .. D7
+EMC_PINSEL8_Val     EQU 0x55555555      ; A0 .. A15
+EMC_PINSEL9_Val     EQU 0x50090000;     ; !OE, !WE (BLS0 because of errata), !CS0, !CS1
+
+;//     External Memory Controller Setup (EMC) ---------------------------------
+;//  External Memory Controller Setup (EMC)
+EMC_SETUP           EQU 1
+
+;//    EMC Control Register (EMCControl)
+;//      Controls operation of the memory controller
+;//      L: Low-power mode enable
+;//      M: Address mirror enable
+;//      E: EMC enable
+;//   
+EMC_CTRL_Val        EQU 0x00000001
+
+;//    EMC Configuration Register (EMCConfig)
+;//      Endian mode
+;//       <0=> Little-endian
+;//       <1=> Big-endian
+;//   
+EMC_CONFIG_Val      EQU 0x00000000
+
+;//       Configure External Bus Behaviour for Static CS0 Area -----------------
+;//    Configure External Bus Behaviour for Static CS0 Area
+EMC_STACS0_SETUP    EQU 1
+
+;//      Static Memory Configuration Register (EMCStaticConfig0)
+;//        Defines the configuration information for the static memory CS0
+;//        WP: Write protect
+;//        B: Write buffer enable
+;//        EW: Extended wait enable
+;//        PC: Chip select polarity
+;//         <0=> Active LOW chip select
+;//         <1=> Active HIGH chip select
+;//        PM: Async page mode enable
+;//        MW: Memory width
+;//         <0=> 8 bit
+;//         <1=> 16 bit
+;//         <2=> 32 bit
+;//     
+EMC_STA_CFG0_Val    EQU 0x00000000
+
+;//      Static Memory Write Enable Delay Register (EMCStaticWaitWen0)
+;//        Selects the delay from CS0 to write enable
+;//        WAITWEN: Wait write enable <1-16> <#-1>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WWEN0_Val   EQU 0x00000002
+
+;//      Static Memory Output Enable Delay register (EMCStaticWaitOen0)
+;//        Selects the delay from CS0 or address change, whichever is later, to output enable
+;//        WAITOEN: Wait output enable <0-15>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WOEN0_Val   EQU 0x00000002
+                                      
+;//      Static Memory Read Delay Register (EMCStaticWaitRd0)
+;//        Selects the delay from CS0 to a read access
+;//        WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WRD0_Val    EQU 0x0000001F
+
+;//      Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0)
+;//        Selects the delay for asynchronous page mode sequential accesses for CS0
+;//        WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WPAGE0_Val  EQU 0x0000001F
+
+;//      Static Memory Write Delay Register (EMCStaticWaitWr0)
+;//        Selects the delay from CS0 to a write access
+;//        WAITWR: Write wait states <2-33> <#-2>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WWR0_Val    EQU 0x0000001F
+
+;//      Static Memory Turn Round Delay Register (EMCStaticWaitTurn0)
+;//        Selects the number of bus turnaround cycles for CS0
+;//        WAITTURN: Bus turnaround cycles <1-16> <#-1>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WTURN0_Val  EQU 0x0000000F
+
+;//    End of Static Setup for Static CS0 Area
+
+;//       Configure External Bus Behaviour for Static CS1 Area -----------------
+;//    Configure External Bus Behaviour for Static CS1 Area
+EMC_STACS1_SETUP    EQU 0
+
+;//      Static Memory Configuration Register (EMCStaticConfig1)
+;//        Defines the configuration information for the static memory CS1
+;//        WP: Write protect
+;//        B: Write buffer enable
+;//        EW: Extended wait enable
+;//        PC: Chip select polarity
+;//         <0=> Active LOW chip select
+;//         <1=> Active HIGH chip select
+;//        PM: Async page mode enable
+;//        MW: Memory width
+;//         <0=> 8 bit
+;//         <1=> 16 bit
+;//         <2=> 32 bit
+;//     
+EMC_STA_CFG1_Val    EQU 0x00000000
+
+;//      Static Memory Write Enable Delay Register (EMCStaticWaitWen1)
+;//        Selects the delay from CS1 to write enable
+;//        WAITWEN: Wait write enable <1-16> <#-1>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WWEN1_Val   EQU 0x00000000
+
+;//      Static Memory Output Enable Delay register (EMCStaticWaitOen1)
+;//        Selects the delay from CS1 or address change, whichever is later, to output enable
+;//        WAITOEN: Wait output enable <0-15>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WOEN1_Val   EQU 0x00000000
+                                      
+;//      Static Memory Read Delay Register (EMCStaticWaitRd1)
+;//        Selects the delay from CS1 to a read access
+;//        WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WRD1_Val    EQU 0x0000001F
+
+;//      Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0)
+;//        Selects the delay for asynchronous page mode sequential accesses for CS1
+;//        WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WPAGE1_Val  EQU 0x0000001F
+
+;//      Static Memory Write Delay Register (EMCStaticWaitWr1)
+;//        Selects the delay from CS1 to a write access
+;//        WAITWR: Write wait states <2-33> <#-2>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WWR1_Val    EQU  0x0000001F
+
+;//      Static Memory Turn Round Delay Register (EMCStaticWaitTurn1)
+;//        Selects the number of bus turnaround cycles for CS1
+;//        WAITTURN: Bus turnaround cycles <1-16> <#-1>
+;//          The delay is in CCLK cycles
+;//     
+EMC_STA_WTURN1_Val  EQU 0x0000000F
+
+;//    End of Static Setup for Static CS1 Area
+
+;//    Static Memory Extended Wait Register (EMCStaticExtendedWait)
+;//      Time long static memory read and write transfers
+;//      EXTENDEDWAIT: Extended wait time out <1-64><#-1>
+;//        The delay is in (16 * CCLK) cycles
+;//   
+EMC_STA_EXT_W_Val   EQU 0x00000000
+
+;//  End of EMC Setup
+
+
+; Area Definition and Entry Point
+;  Startup Code must be linked first at Address at which it expects to run.
+
+                AREA    RESET, CODE, READONLY
+                ARM
+
+
+; Exception Vectors
+;  Mapped to Address 0.
+;  Absolute addressing mode must be used.
+;  Dummy Handlers are implemented as infinite loops which can be modified.
+
+Vectors         LDR     PC, Reset_Addr         
+                LDR     PC, Undef_Addr
+                LDR     PC, SWI_Addr
+                LDR     PC, PAbt_Addr
+                LDR     PC, DAbt_Addr
+                NOP                            ; Reserved Vector 
+;               LDR     PC, IRQ_Addr
+                LDR     PC, [PC, #-0x0120]     ; Vector from VicVectAddr
+                LDR     PC, FIQ_Addr
+
+Reset_Addr      DCD     Reset_Handler
+Undef_Addr      DCD     Undef_Handler
+SWI_Addr        DCD     SWI_Handler
+PAbt_Addr       DCD     PAbt_Handler
+DAbt_Addr       DCD     DAbt_Handler
+                DCD     0                      ; Reserved Address 
+IRQ_Addr        DCD     IRQ_Handler
+FIQ_Addr        DCD     FIQ_Handler
+
+Undef_Handler   B       Undef_Handler
+SWI_Handler     B       SWI_Handler
+PAbt_Handler    B       PAbt_Handler
+DAbt_Handler    B       DAbt_Handler
+IRQ_Handler     B       IRQ_Handler
+FIQ_Handler     B       FIQ_Handler
+
+
+; Reset Handler
+
+                EXPORT  Reset_Handler
+Reset_Handler   
+
+
+
+; Clock Setup ------------------------------------------------------------------
+
+                IF      (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0)
+                LDR     R0, =SCB_BASE
+                MOV     R1, #0xAA
+                MOV     R2, #0x55
+
+;  Configure and Enable PLL
+                LDR     R3, =SCS_Val          ; Enable main oscillator
+                STR     R3, [R0, #SCS_OFS] 
+
+                IF      (SCS_Val:AND:OSCEN) != 0  
+OSC_Loop        LDR     R3, [R0, #SCS_OFS]    ; Wait for main osc stabilize
+                ANDS    R3, R3, #OSCSTAT
+                BEQ     OSC_Loop
+                ENDIF
+
+                LDR     R3, =CLKSRCSEL_Val    ; Select PLL source clock
+                STR     R3, [R0, #CLKSRCSEL_OFS] 
+                LDR     R3, =PLLCFG_Val
+                STR     R3, [R0, #PLLCFG_OFS] 
+                STR     R1, [R0, #PLLFEED_OFS]
+                STR     R2, [R0, #PLLFEED_OFS]
+                MOV     R3, #PLLCON_PLLE
+                STR     R3, [R0, #PLLCON_OFS]
+                STR     R1, [R0, #PLLFEED_OFS]
+                STR     R2, [R0, #PLLFEED_OFS]
+
+;  Wait until PLL Locked
+PLL_Loop        LDR     R3, [R0, #PLLSTAT_OFS]
+                ANDS    R3, R3, #PLLSTAT_PLOCK
+                BEQ     PLL_Loop
+
+M_N_Lock        LDR     R3, [R0, #PLLSTAT_OFS]
+                LDR     R4, =(PLLSTAT_M:OR:PLLSTAT_N)
+                AND     R3, R3, R4
+                LDR     R4, =PLLCFG_Val
+                EORS    R3, R3, R4
+                BNE     M_N_Lock
+
+;  Setup CPU clock divider
+                MOV     R3, #CCLKCFG_Val
+                STR     R3, [R0, #CCLKCFG_OFS]
+
+;  Setup USB clock divider
+                LDR     R3, =USBCLKCFG_Val
+                STR     R3, [R0, #USBCLKCFG_OFS]
+
+;  Setup Peripheral Clock
+                LDR     R3, =PCLKSEL0_Val
+                STR     R3, [R0, #PCLKSEL0_OFS]
+                LDR     R3, =PCLKSEL1_Val
+                STR     R3, [R0, #PCLKSEL1_OFS]
+
+;  Switch to PLL Clock
+                MOV     R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
+                STR     R3, [R0, #PLLCON_OFS]
+                STR     R1, [R0, #PLLFEED_OFS]
+                STR     R2, [R0, #PLLFEED_OFS]
+
+                LDR     R4, =PCONP_Val        ; Enable Peripheral Clocks
+                STR     R4, [R0, #PCONP_OFS]
+                ENDIF   ; CLOCK_SETUP
+
+
+; Setup Memory Accelerator Module ----------------------------------------------
+
+                IF      MAM_SETUP != 0
+                LDR     R0, =MAM_BASE
+                MOV     R1, #MAMTIM_Val
+                STR     R1, [R0, #MAMTIM_OFS] 
+                MOV     R1, #MAMCR_Val
+                STR     R1, [R0, #MAMCR_OFS] 
+                ENDIF   ; MAM_SETUP
+
+
+; Setup External Memory Controller ---------------------------------------------
+
+                IF      (:DEF:NO_EMC_SETUP):LOR:(EMC_SETUP != 0)
+                LDR     R0, =EMC_BASE
+                LDR     R1, =SCB_BASE
+                LDR     R2, =PCB_BASE
+
+                LDR     R4, [R1, #PCONP_OFS]
+                ORR     R4, R4, #EMC_PCONP_Const  ; Enable EMC clock
+                STR     R4, [R1, #PCONP_OFS]
+
+                LDR     R4, =EMC_CTRL_Val
+                STR     R4, [R0, #EMC_CTRL_OFS]
+                LDR     R4, =EMC_CONFIG_Val
+                STR     R4, [R0, #EMC_CONFIG_OFS]
+
+;  Setup pin functions for External Bus functionality
+                LDR     R4, =EMC_PINSEL6_Val
+                STR     R4, [R2, #PINSEL6_OFS]
+                LDR     R4, =EMC_PINSEL8_Val
+                STR     R4, [R2, #PINSEL8_OFS]
+                LDR     R4, =EMC_PINSEL9_Val
+                STR     R4, [R2, #PINSEL9_OFS]
+
+                LDR     R6, =1200000              ; Number of cycles to delay
+Wait_0          SUBS    R6, R6, #1                ; Delay ~100 ms @ proc clk 48 MHz
+                BNE     Wait_0
+
+                IF      (EMC_STACS0_SETUP != 0)
+                LDR     R4, =EMC_STA_CFG0_Val
+                STR     R4, [R0, #EMC_STA_CFG0_OFS]
+                LDR     R4, =EMC_STA_WWEN0_Val
+                STR     R4, [R0, #EMC_STA_WWEN0_OFS]
+                LDR     R4, =EMC_STA_WOEN0_Val
+                STR     R4, [R0, #EMC_STA_WOEN0_OFS]
+                LDR     R4, =EMC_STA_WRD0_Val
+                STR     R4, [R0, #EMC_STA_WRD0_OFS]
+                LDR     R4, =EMC_STA_WPAGE0_Val
+                STR     R4, [R0, #EMC_STA_WPAGE0_OFS]
+                LDR     R4, =EMC_STA_WWR0_Val
+                STR     R4, [R0, #EMC_STA_WWR0_OFS]
+                LDR     R4, =EMC_STA_WTURN0_Val
+                STR     R4, [R0, #EMC_STA_WTURN0_OFS]
+                ENDIF
+
+                IF      (EMC_STACS1_SETUP != 0)
+                LDR     R4, =EMC_STA_CFG1_Val
+                STR     R4, [R0, #EMC_STA_CFG1_OFS]
+                LDR     R4, =EMC_STA_WWEN1_Val
+                STR     R4, [R0, #EMC_STA_WWEN1_OFS]
+                LDR     R4, =EMC_STA_WOEN1_Val
+                STR     R4, [R0, #EMC_STA_WOEN1_OFS]
+                LDR     R4, =EMC_STA_WRD1_Val
+                STR     R4, [R0, #EMC_STA_WRD1_OFS]
+                LDR     R4, =EMC_STA_WPAGE1_Val
+                STR     R4, [R0, #EMC_STA_WPAGE1_OFS]
+                LDR     R4, =EMC_STA_WWR1_Val
+                STR     R4, [R0, #EMC_STA_WWR1_OFS]
+                LDR     R4, =EMC_STA_WTURN1_Val
+                STR     R4, [R0, #EMC_STA_WTURN1_OFS]
+                ENDIF
+
+                LDR     R6, =120000               ; Number of cycles to delay
+Wait_1          SUBS    R6, R6, #1                ; Delay ~10 ms @ proc clk 48 MHz
+                BNE     Wait_1
+
+                LDR     R4, =EMC_STA_EXT_W_Val
+                LDR     R5, =EMC_STA_EXT_W_OFS
+                ADD     R5, R5, R0
+                STR     R4, [R5, #0]
+
+                ENDIF   ; EMC_SETUP
+
+
+; Copy Exception Vectors to Internal RAM ---------------------------------------
+
+                IF      :DEF:RAM_INTVEC
+                ADR     R8, Vectors         ; Source
+                LDR     R9, =RAM_BASE       ; Destination
+                LDMIA   R8!, {R0-R7}        ; Load Vectors 
+                STMIA   R9!, {R0-R7}        ; Store Vectors 
+                LDMIA   R8!, {R0-R7}        ; Load Handler Addresses 
+                STMIA   R9!, {R0-R7}        ; Store Handler Addresses
+                ENDIF
+
+
+; Memory Mapping (when Interrupt Vectors are in RAM) ---------------------------
+
+MEMMAP          EQU     0xE01FC040          ; Memory Mapping Control
+                IF      :DEF:REMAP
+                LDR     R0, =MEMMAP
+                IF      :DEF:EXTMEM_MODE
+                MOV     R1, #3
+                ELIF    :DEF:RAM_MODE
+                MOV     R1, #2
+                ELSE
+                MOV     R1, #1
+                ENDIF
+                STR     R1, [R0]
+                ENDIF
+
+
+; Setup Stack for each mode ----------------------------------------------------
+
+                LDR     R0, =Stack_Top
+
+;  Enter Undefined Instruction Mode and set its Stack Pointer
+                MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
+                MOV     SP, R0
+                SUB     R0, R0, #UND_Stack_Size
+
+;  Enter Abort Mode and set its Stack Pointer
+                MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
+                MOV     SP, R0
+                SUB     R0, R0, #ABT_Stack_Size
+
+;  Enter FIQ Mode and set its Stack Pointer
+                MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
+                MOV     SP, R0
+                SUB     R0, R0, #FIQ_Stack_Size
+
+;  Enter IRQ Mode and set its Stack Pointer
+                MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
+                MOV     SP, R0
+                SUB     R0, R0, #IRQ_Stack_Size
+
+;  Enter Supervisor Mode and set its Stack Pointer
+                MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
+                MOV     SP, R0
+                SUB     R0, R0, #SVC_Stack_Size
+
+;  Enter User Mode and set its Stack Pointer
+                MSR     CPSR_c, #Mode_USR
+                IF      :DEF:__MICROLIB
+
+                EXPORT __initial_sp
+
+                ELSE
+
+                MOV     SP, R0
+                SUB     SL, SP, #USR_Stack_Size
+
+                ENDIF
+
+
+; Enter the C code -------------------------------------------------------------
+
+                IMPORT  __main
+                LDR     R0, =__main
+                BX      R0
+
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+; User Initial Stack & Heap
+                AREA    |.text|, CODE, READONLY
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + USR_Stack_Size)
+                LDR     R2, = (Heap_Mem +      Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDIF
+
+
+                END
diff --git a/PN532_SPI.cpp b/PN532_SPI.cpp
new file mode 100644
index 0000000..1b3468c
--- /dev/null
+++ b/PN532_SPI.cpp
@@ -0,0 +1,210 @@
+
+#include "PN532_SPI.h"
+#include "PN532_debug.h"
+#include "Arduino.h"
+
+#define STATUS_READ     2
+#define DATA_WRITE      1
+#define DATA_READ       3
+
+PN532_SPI::PN532_SPI(SPIClass &spi, uint8_t ss)
+{
+    command = 0;
+    _spi = &spi;
+    _ss  = ss;
+}
+
+void PN532_SPI::begin()
+{
+    pinMode(_ss, OUTPUT);
+
+    _spi->begin();
+    _spi->setDataMode(SPI_MODE0);  // PN532 only supports mode0
+    _spi->setBitOrder(LSBFIRST);
+#ifndef __SAM3X8E__
+    _spi->setClockDivider(SPI_CLOCK_DIV8); // set clock 2MHz(max: 5MHz)
+#else
+    /** DUE spi library does not support SPI_CLOCK_DIV8 macro */
+    _spi->setClockDivider(42);             // set clock 2MHz(max: 5MHz)
+#endif
+
+}
+
+void PN532_SPI::wakeup()
+{
+    digitalWrite(_ss, LOW);
+    delay(2);
+    digitalWrite(_ss, HIGH);
+}
+
+
+
+int8_t PN532_SPI::writeCommand(const uint8_t *header, uint8_t hlen, const uint8_t *body, uint8_t blen)
+{
+    command = header[0];
+    writeFrame(header, hlen, body, blen);
+    
+    uint8_t timeout = PN532_ACK_WAIT_TIME;
+    while (!isReady()) {
+        delay(1);
+        timeout--;
+        if (0 == timeout) {
+            DMSG("Time out when waiting for ACK\n");
+            return -2;
+        }
+    }
+    if (readAckFrame()) {
+        DMSG("Invalid ACK\n");
+        return PN532_INVALID_ACK;
+    }
+    return 0;
+}
+
+int16_t PN532_SPI::readResponse(uint8_t buf[], uint8_t len, uint16_t timeout)
+{
+    uint16_t time = 0;
+    while (!isReady()) {
+        delay(1);
+        time++;
+        if (timeout > 0 && time > timeout) {
+            return PN532_TIMEOUT;
+        }
+    }
+
+    digitalWrite(_ss, LOW);
+    delay(1);
+
+    int16_t result;
+    do {
+        write(DATA_READ);
+
+        if (0x00 != read()      ||       // PREAMBLE
+                0x00 != read()  ||       // STARTCODE1
+                0xFF != read()           // STARTCODE2
+           ) {
+
+            result = PN532_INVALID_FRAME;
+            break;
+        }
+
+        uint8_t length = read();
+        if (0 != (uint8_t)(length + read())) {   // checksum of length
+            result = PN532_INVALID_FRAME;
+            break;
+        }
+
+        uint8_t cmd = command + 1;               // response command
+        if (PN532_PN532TOHOST != read() || (cmd) != read()) {
+            result = PN532_INVALID_FRAME;
+            break;
+        }
+
+        DMSG("read:  ");
+        DMSG_HEX(cmd);
+
+        length -= 2;
+        if (length > len) {
+            for (uint8_t i = 0; i < length; i++) {
+                DMSG_HEX(read());                 // dump message
+            }
+            DMSG("\nNot enough space\n");
+            read();
+            read();
+            result = PN532_NO_SPACE;  // not enough space
+            break;
+        }
+
+        uint8_t sum = PN532_PN532TOHOST + cmd;
+        for (uint8_t i = 0; i < length; i++) {
+            buf[i] = read();
+            sum += buf[i];
+
+            DMSG_HEX(buf[i]);
+        }
+        DMSG('\n');
+
+        uint8_t checksum = read();
+        if (0 != (uint8_t)(sum + checksum)) {
+            DMSG("checksum is not ok\n");
+            result = PN532_INVALID_FRAME;
+            break;
+        }
+        read();         // POSTAMBLE
+
+        result = length;
+    } while (0);
+
+    digitalWrite(_ss, HIGH);
+
+    return result;
+}
+
+boolean PN532_SPI::isReady()
+{
+    digitalWrite(_ss, LOW);
+
+    write(STATUS_READ);
+    uint8_t status = read() & 1;
+    digitalWrite(_ss, HIGH);
+    return status;
+}
+
+void PN532_SPI::writeFrame(const uint8_t *header, uint8_t hlen, const uint8_t *body, uint8_t blen)
+{
+    digitalWrite(_ss, LOW);
+    delay(2);               // wake up PN532
+
+    write(DATA_WRITE);
+    write(PN532_PREAMBLE);
+    write(PN532_STARTCODE1);
+    write(PN532_STARTCODE2);
+
+    uint8_t length = hlen + blen + 1;   // length of data field: TFI + DATA
+    write(length);
+    write(~length + 1);         // checksum of length
+
+    write(PN532_HOSTTOPN532);
+    uint8_t sum = PN532_HOSTTOPN532;    // sum of TFI + DATA
+
+    DMSG("write: ");
+
+    for (uint8_t i = 0; i < hlen; i++) {
+        write(header[i]);
+        sum += header[i];
+
+        DMSG_HEX(header[i]);
+    }
+    for (uint8_t i = 0; i < blen; i++) {
+        write(body[i]);
+        sum += body[i];
+
+        DMSG_HEX(body[i]);
+    }
+
+    uint8_t checksum = ~sum + 1;        // checksum of TFI + DATA
+    write(checksum);
+    write(PN532_POSTAMBLE);
+
+    digitalWrite(_ss, HIGH);
+
+    DMSG('\n');
+}
+
+int8_t PN532_SPI::readAckFrame()
+{
+    const uint8_t PN532_ACK[] = {0, 0, 0xFF, 0, 0xFF, 0};
+
+    uint8_t ackBuf[sizeof(PN532_ACK)];
+
+    digitalWrite(_ss, LOW);
+    delay(1);
+    write(DATA_READ);
+
+    for (uint8_t i = 0; i < sizeof(PN532_ACK); i++) {
+        ackBuf[i] = read();
+    }
+
+    digitalWrite(_ss, HIGH);
+
+    return memcmp(ackBuf, PN532_ACK, sizeof(PN532_ACK));
+}
diff --git a/RFID_PN532.c b/RFID_PN532.c
new file mode 100644
index 0000000..9a4e01c
--- /dev/null
+++ b/RFID_PN532.c
@@ -0,0 +1,251 @@
+// #include  // LPC2378 microcontroller register definitions
+
+
+// FIODIR2 = 0xFF;
+// 		FIOPIN2 = 0x9;
+// 		FIODIR1 = 0x1;
+// 		//FIO0SET = 0XFFFEFFFF;
+// 		FIOMASK1 = 0XFFFFFFFE;
+// 		FIOPIN1 = 0x1;
+// 		
+// 		
+// // Function to transfer one byte of data over SPI and receive a byte back
+// int SPI0_Transfer(int data) {
+//     S0SPDR = data;                  // Write data to SPI Data Register
+//     while (!(S0SPSR & (1 << 7)));   // Wait for transfer to complete (SPIF flag)
+//     return S0SPDR;                  // Return received data
+// }
+
+// // Function to select the PN532 by pulling SS (chip select) low
+// void PN532_Select(void) {
+//     FIOCLR0 = (1 << PN532_SSEL_PIN); // Pull SSEL low to select PN532
+// }
+
+// // Function to deselect the PN532 by pulling SS (chip select) high
+// void PN532_Deselect(void) {
+//     FIOSET0 = (1 << PN532_SSEL_PIN); // Pull SSEL high to deselect PN532
+// }
+
+// // Function to write a command to the PN532
+// void PN532_WriteCommand(int *cmd, int cmd_len) {
+//     PN532_Select();
+
+//     SPI0_Transfer(0x01);         // Preamble
+//     SPI0_Transfer(0x00);         // Start Code
+//     SPI0_Transfer(0xFF);         // Start Code
+//     SPI0_Transfer(cmd_len + 1);  // Length byte
+//     SPI0_Transfer(~(cmd_len + 1) + 1); // Checksum for length
+
+//     int checksum = 0;
+//     SPI0_Transfer(0xD4);         // Host to PN532 Command Code
+//     checksum += 0xD4;
+
+//     for (int i = 0; i < cmd_len; i++) {
+//         SPI0_Transfer(cmd[i]);  // Send each byte of the command
+//         checksum += cmd[i];
+//     }
+
+//     SPI0_Transfer(~checksum + 1); // Checksum byte
+//     SPI0_Transfer(0x00);          // Postamble
+
+//     PN532_Deselect();
+// }
+
+// // Function to read a response from the PN532
+// int PN532_ReadResponse(int *response, int response_len) {
+//     PN532_Select();
+
+//     // Wait for Preamble byte (0x01), retry until found or timeout
+//     if (SPI0_Transfer(0x00) != 0x01) {  
+//         PN532_Deselect();
+//         return 0; // Error or no response
+//     }
+//     SPI0_Transfer(0x00); // Start Code
+//     SPI0_Transfer(0xFF); // Start Code
+
+//     int len = SPI0_Transfer(0x00);     // Length byte
+//     SPI0_Transfer(0xFF - len + 1);         // Checksum for length
+
+//     int checksum = 0;
+//     for (int i = 0; i < len - 1; i++) {
+//         response[i] = SPI0_Transfer(0x00); // Read each byte of the response
+//         checksum += response[i];
+//     }
+
+//     int response_checksum = SPI0_Transfer(0x00);
+//     PN532_Deselect();
+
+//     if (((checksum + response_checksum) & 0xFF) != 0) {
+//         return 0; // Checksum error
+//     }
+//     return len - 1; // Return length of valid data
+// }
+
+// // Function to send the "Get Firmware Version" command to the PN532
+// void PN532_GetFirmwareVersion(void) {
+//     int cmd[] = {0x02}; // Command code for Get Firmware Version
+//     PN532_WriteCommand(cmd, sizeof(cmd));
+
+//     int response[12];   // Buffer to hold the response
+//     if (PN532_ReadResponse(response, sizeof(response))) {
+//         // Process firmware version from response
+//         // Example: response[0] = IC Version, response[1] = Version, etc.
+//     } else {
+//         // Handle error: no response or incorrect response
+//     }
+// }
+
+// //  function to initialize SPI and test PN532 communication
+// int main(void) {
+//     //FIO0DIR |= (1 << PN532_SSEL_PIN);  // Set PN532 SSEL pin as output
+//     //SPI0_Init();                       // Initialize SPI0
+
+//     while (1) {
+//         PN532_GetFirmwareVersion();    // Send Get Firmware Version command
+//         // Add delay if needed, process response
+//     }
+// }
+
+#include 
+#include                     /* LPC23xx definitions                */
+#include "LCD.h"                        /* Graphic LCD function prototypes    */
+#include 
+
+#define PN532_CS_PIN     (1 << 10)  // Example: P0.10 used for CS
+#define PN532_MOSI_PIN   (1 << 18)  // Example: P0.18 for MOSI
+#define PN532_MISO_PIN   (1 << 17)  // Example: P0.17 for MISO
+#define PN532_SCK_PIN    (1 << 15)  // Example: P0.15 for SCK
+
+// SPI command definitions
+#define PN532_SPI_STAT_READ      0x02  // SPI status read command
+#define PN532_SPI_DATA_WRITE     0x01  // SPI data write command
+#define PN532_SPI_DATA_READ      0x03  // SPI data read command
+char val[10];
+// Function prototypes
+void SPI_Init(void);
+void PN532_WriteCommand(int *cmd, int len);
+void PN532_ReadData(int *buffer, int len);
+int SPI_Transfer(int data);
+extern int i;
+void delay_ms(int ms);
+void detect_rfid_card(void);
+int checksum ;
+int mainrww(void) {
+  lcd_print("HHHE");
+			delay_ms(100000);  
+	SPI_Init();  // Initialize SPI
+
+    while (1) {
+			lcd_print("HHHE");
+			delay_ms(100000);
+        detect_rfid_card();  // Continuously check for RFID cards
+        delay_ms(500);       // Delay between detections
+    }
+}
+
+// Function to detect RFID card
+void detect_rfid_card(void) {
+    // InListPassiveTarget command: Poll for one ISO14443A card
+    int command[] = {0x4A, 0x01, 0x00};  // InListPassiveTarget, MaxTargets = 1, Baudrate = 106 kbps
+    int response[64];                    // Buffer for response data
+
+    // Send command to PN532
+    PN532_WriteCommand(command, sizeof(command));
+
+    // Wait for response
+    delay_ms(50);  // Allow PN532 to process
+
+    // Read response from PN532
+    PN532_ReadData(response, sizeof(response));
+
+    // Parse and print results
+    if (response[6] == 0x00 && response[7] == 0x01) {  // Success, 1 card detected
+        int uid_length = response[12];             // Length of UID
+        int *uid = &response[13];                 // Pointer to UID bytes
+        // Print UID (for debugging, replace with actual handling logic)
+        for ( i = 0; i < uid_length; i++) {
+            // Replace with actual code to display UID, e.g., UART print
+					lcd_clear();
+					sprintf(val, "%d",*uid);
+					lcd_print ( val);
+        }
+    }
+}
+
+void SPI_Init(void) {
+    // Configure SPI pins
+    PINSEL0 &= ~(0x3 << 30); // Clear bits for P0.15 (SCK)
+    PINSEL0 |= (0x3 << 30);  // Set SCK0
+    PINSEL1 &= ~((0x3 << 2) | (0x3 << 4)); // Clear bits for P0.17 (MISO) and P0.18 (MOSI)
+    PINSEL1 |= ((0x3 << 2) | (0x3 << 4));  // Set MISO0 and MOSI0
+
+    // Configure CS pin as GPIO
+    FIO0DIR |= PN532_CS_PIN;
+    FIO0SET = PN532_CS_PIN; // Set CS high initially
+
+    // Configure SPI
+    S0SPCCR = 8;           // SPI clock = PCLK / 8
+    S0SPCR = (1 << 5) |    // Enable SPI
+             (1 << 3) |    // Master mode
+             (1 << 2);     // CPOL = 0, CPHA = 0
+}
+
+void PN532_WriteCommand(int *cmd, int len) {
+    FIO0CLR = PN532_CS_PIN; // Pull CS low
+
+    // Send preamble and start code
+    SPI_Transfer(0x00);
+    SPI_Transfer(0x00);
+    SPI_Transfer(0xFF);
+
+    // Send length and length checksum
+    SPI_Transfer(len + 1);         // Length (Data + TFI)
+    SPI_Transfer(~(len + 1) + 1);  // Length checksum
+
+    // Send TFI and data
+    SPI_Transfer(0xD4);  // TFI (Host to PN532)
+     checksum = 0xD4;
+    for ( i = 0; i < len; i++) {
+        SPI_Transfer(cmd[i]);
+        checksum += cmd[i];
+    }
+
+    // Send checksum and postamble
+    SPI_Transfer(~checksum + 1);
+    SPI_Transfer(0x00);
+
+    FIO0SET = PN532_CS_PIN; // Pull CS high
+    delay_ms(2);            // Delay to let PN532 process the command
+}
+
+void PN532_ReadData(int *buffer, int len) {
+    FIO0CLR = PN532_CS_PIN; // Pull CS low
+
+    // Send SPI read status command
+    SPI_Transfer(PN532_SPI_STAT_READ);
+
+    // Wait for ready status
+    while (SPI_Transfer(0x00) != 0x01);
+
+    // Send data read command
+    SPI_Transfer(PN532_SPI_DATA_READ);
+
+    // Read data
+    for ( i = 0; i < len; i++) {
+        buffer[i] = SPI_Transfer(0x00);
+    }
+
+    FIO0SET = PN532_CS_PIN; // Pull CS high
+}
+
+int SPI_Transfer(int data) {
+    S0SPDR = data;                 // Load data into SPI data register
+    while (!(S0SPSR & (1 << 7)));  // Wait for transfer to complete
+    return S0SPDR;                 // Return received data
+}
+
+void delay_ms(int ms) {
+    for ( i = 0; i < ms * 1000; i++) {
+        __asm("NOP");
+    }
+}
\ No newline at end of file
diff --git a/RTC.c b/RTC.c
new file mode 100644
index 0000000..e9f681b
--- /dev/null
+++ b/RTC.c
@@ -0,0 +1,79 @@
+#include 
+#include                     /* LPC23xx definitions                */
+#include "LCD.h"                        /* Graphic LCD function prototypes    */
+
+int j,hr,min,sec;
+char hrVal[2];
+char minVal[2];
+char secV[2];
+
+/* Import external IRQ handlers from IRQ.c file                               */
+extern __irq void T0_IRQHandler  (void);
+extern void PWM_SetDutyCycle();
+extern void PWM_Init();
+
+/* Import external variables from IRQ.c file                                  */
+unsigned char clock_1s;
+
+void RTCTimerEnable(){
+	/* Enable and setup timer interrupt, start timer                            */
+  T0MR0         = 11999;                       /* 1msec = 12000-1 at 12.0 MHz */
+  T0MCR         = 3;                           /* Interrupt and Reset on MR0  */
+  T0TCR         = 1;                           /* Timer0 Enable               */
+  VICVectAddr4  = (unsigned long)T0_IRQHandler;/* Set Interrupt Vector        */
+  VICVectCntl4  = 15;                          /* use it for Timer0 Interrupt */
+  VICIntEnable  = (1  << 4);                   /* Enable Timer0 Interrupt     */
+}
+
+void updateRTCTimer(){
+	if (clock_1s) {
+      clock_1s = 0;
+			sec++	;
+			if (sec==60){
+				sec = 0;
+				min++;
+				if(min==60){
+					min = 0;
+					hr++ ;
+					if (hr==24){
+						hr = 0;
+					}
+				}
+			}
+		sprintf(hrVal, "%02i",hr);
+		sprintf(minVal, "%02i", min);
+		sprintf(secV, "%02i", sec);
+		set_cursor(0,1);
+		
+		for (j = 0; j < 2; j++) {
+	 				lcd_putchar(hrVal[j]);
+	 	} 
+		set_cursor(2,1);
+		lcd_print ( ":"); 
+		set_cursor(3,1);
+	
+		for (j = 0; j < 2; j++){
+					lcd_putchar(minVal[j]);
+		} 
+		set_cursor(5,1);
+		lcd_print ( ":");
+		set_cursor(6,1);
+		for (j = 0; j < 2; j++) {
+	 				lcd_putchar(secV[j]);
+	 	} 
+  }
+}
+int trial_run_rtc(void) {
+	
+	RTCTimerEnable();
+  lcd_init();
+  lcd_clear();
+  //lcd_print ("Local Time");
+  set_cursor (0, 1);
+  lcd_print ("00:00:00");
+  
+	while (1) {                           /* Loop forever                       */
+		updateRTCTimer();
+	}
+		
+}
diff --git a/Retarget.c b/Retarget.c
new file mode 100644
index 0000000..e1f0ffc
--- /dev/null
+++ b/Retarget.c
@@ -0,0 +1,42 @@
+/******************************************************************************/
+/* RETARGET.C: 'Retarget' layer for target-dependent low level functions      */
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2005-2006 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+#include 
+#include 
+
+#pragma import(__use_no_semihosting_swi)
+
+
+extern int  sendchar(int ch);  /* in serial.c */
+
+
+struct __FILE { int handle; /* Add whatever you need here */ };
+FILE __stdout;
+
+
+int fputc(int ch, FILE *f) {
+  return (sendchar(ch));
+}
+
+
+int ferror(FILE *f) {
+  /* Your implementation of ferror */
+  return EOF;
+}
+
+
+void _ttywrch(int ch) {
+  sendchar(ch);
+}
+
+
+void _sys_exit(int return_code) {
+label:  goto label;  /* endless loop */
+}
diff --git a/Serial.c b/Serial.c
new file mode 100644
index 0000000..e303e7c
--- /dev/null
+++ b/Serial.c
@@ -0,0 +1,65 @@
+/******************************************************************************/
+/* SERIAL.C: Low Level Serial Routines                                        */
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2005-2006 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+#include                      /* LPC23xx definitions               */
+
+#define UART1                            /* Use UART 0 for printf             */
+
+/* If UART 0 is used for printf                                               */
+#ifdef UART0
+  #define UxFDR  U0FDR
+  #define UxLCR  U0LCR
+  #define UxDLL  U0DLL
+  #define UxDLM  U0DLM
+  #define UxLSR  U0LSR
+  #define UxTHR  U0THR
+  #define UxRBR  U0RBR
+/* If UART 1 is used for printf                                               */
+#elif defined(UART1)
+  #define UxFDR  U1FDR
+  #define UxLCR  U1LCR
+  #define UxDLL  U1DLL
+  #define UxDLM  U1DLM
+  #define UxLSR  U1LSR
+  #define UxTHR  U1THR
+  #define UxRBR  U1RBR
+#endif
+
+
+void init_serial (void)  {               /* Initialize Serial Interface       */
+  #ifdef UART0
+    PINSEL0 |= 0x00000050;               /* Enable TxD0 and RxD0              */
+  #elif defined (UART1)
+    PINSEL0 |= 0x40000000;               /* Enable TxD1                       */
+    PINSEL1 |= 0x00000001;               /* Enable RxD1                       */
+  #endif
+  UxFDR    = 0;                          /* Fractional divider not used       */
+  UxLCR    = 0x83;                       /* 8 bits, no Parity, 1 Stop bit     */
+  UxDLL    = 78;                         /* 9600 Baud Rate @ 12.0 MHZ PCLK    */
+  UxDLM    = 0;                          /* High divisor latch = 0            */
+  UxLCR    = 0x03;                       /* DLAB = 0                          */
+}
+
+
+/* Implementation of putchar (also used by printf function to output data)    */
+int sendchar (int ch)  {                 /* Write character to Serial Port    */
+
+  while (!(UxLSR & 0x20));
+
+  return (UxTHR = ch);
+}
+
+
+int getkey (void)  {                     /* Read character from Serial Port   */
+
+  while (!(UxLSR & 0x01));
+
+  return (UxRBR);
+}
diff --git a/Servo_MG995.c b/Servo_MG995.c
new file mode 100644
index 0000000..d405855
--- /dev/null
+++ b/Servo_MG995.c
@@ -0,0 +1,42 @@
+#include 
+#include  
+#include  
+#include "LCD.h"
+
+int i, dutyCycle;
+
+void PWM_Init() 											// Set pin function for P1.18 as PWM1
+{    	
+	
+    PINSEL3 |= (2 << 4); 							// Set bits 4-5 to 10 (AF2) for PWM1.1
+
+    // Set PWM mode for PWM1
+    PWM1PCR = (1 << 9); 							// Enable PWM1 output (PWM1.1). Set bit 9 = 1
+    PWM1MCR = (1 << 1); 							// Reset counter on matching value in PWM1MR0
+    
+    // Set PWM frequency
+    PWM1MR0 = 240000; 								// Set period to 20 ms (assuming 1 MHz clock)
+    PWM1TCR = (1 << 0) | (1 << 3); 		// Enable PWM and counter. 0th bit to enable counter and 3rd bit to enable PWM
+
+}
+
+void WaitTime(int wait_time)
+{
+		for (i = 0; i < wait_time; i++);				// Approx 4-5s
+}
+void PWM_SetDutyCycle(int dutyCycle) 				// MG995 duty cycle mapping: 1ms = 0° (5%), 1.5ms = 90° (7.5%), 2ms = 180° (10%)
+{
+    PWM1MR1 = (dutyCycle * PWM1MR0) / 100; 	// Set duty cycle to value set as 1 time period
+    PWM1LER = (1 << 1); 										// Enable PWM1.1 latch, ensures new value for PWM1MR1 is applied at next update of PWM signal
+}
+
+ int trial_run_servo() 
+ {
+	 lcd_init();
+	 lcd_clear();
+     PWM_Init();
+			while (1) 
+			{
+				PWM_SetDutyCycle(7.5);
+			}
+	}
diff --git a/Sim.ini b/Sim.ini
new file mode 100644
index 0000000..9261a63
--- /dev/null
+++ b/Sim.ini
@@ -0,0 +1,135 @@
+/******************************************************************************/
+/* SIM.INI: Simulator Initialization File                                     */
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2005-2007 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+
+/*-------------------------------------------------------------------*/
+/* Analog0() simulates analog input values given to channel-0 (AD00) */
+/*-------------------------------------------------------------------*/
+Signal void analog0 (float limit)  {
+  float volts;
+
+  printf ("Analog0 (%f) entered.\n", limit);
+  while (1)  {          /* forever */
+    volts = 0;
+    while (volts <= limit)  {
+      ad00 = volts;     /* analog input-0 */
+      twatch (500000);  /* 500000 Cycles Time-Break */
+      volts += 0.1;     /* increase voltage */
+    }
+    volts = limit;
+    while (volts >= 0.0)  {
+      ad00 = volts;
+      twatch (500000);  /* 500000 Cycles Time-Break */
+      volts -= 0.1;     /* decrease voltage */
+    }
+  }
+}
+
+
+/*
+ *  Simulate LCD Display (2 line 40 character Text LCD with 4-bit Interface)
+ *    Pins:
+ *      - DB4..DB7 = P1.24..P1.27
+ *      - RS       = P1.28
+ *      - RW       = P1.29
+ *      - E        = P1.31
+ */
+
+define unsigned long oldPORT1;
+define unsigned char Cursor;
+define unsigned char bitpos;
+define unsigned char Cmd;
+
+define unsigned long _E;
+define unsigned long _RW;
+define unsigned long _RS;
+define unsigned long _CTRL;
+define unsigned long _DATA;
+
+MAP 0x10000000, 0x1000004F READ WRITE   // LCD Memory
+
+oldPORT1 = PORT1;
+Cursor   = 0;
+bitpos   = 0;
+
+_E    = 0x80000000;
+_RW   = 0x20000000;
+_RS   = 0x10000000;
+_CTRL = 0xB0000000;
+_DATA = 0x0F000000;
+
+// Clear Display Function
+Func void LCD_Clear (void) {
+  unsigned char i;
+
+  for (i = 0; i < 80; i++) {
+    _WBYTE(0x10000000 + i, 0x20);
+  }
+  Cursor = 0;
+}
+
+// LCD Display Signal Function
+Signal void LCD_Display (void) {
+  unsigned char val;
+
+  while (1) {
+    wwatch(PORT1);  // Wait for write to PORT1
+    if ((PORT1 & _RW) == 0) {
+      // Write to Display
+      if (((oldPORT1 & _E) != 0) && ((PORT1 & _E) == 0)) {
+        // E: 1->0
+        if ((PORT1 & _RS) == 0) {
+          // Write Command
+          val  = ((PORT1 & _DATA) >> 24);
+          if (val == 3) {
+            bitpos = 4;
+          }
+          Cmd &= 0xF0 >> bitpos;
+          Cmd |= val << bitpos;
+          if (bitpos == 0) {
+            if (Cmd == 0x01) {
+              // Clear Display
+              LCD_Clear();
+            } else if (Cmd & 0x80) {
+              // Set Cursor Position
+              Cursor = Cmd & 0x7F;
+            }
+          }
+        } else {
+          // Write Data
+          val  = _RBYTE(0x10000000 + Cursor);
+          val &= 0xF0 >> bitpos;
+          val |= ((PORT1 & _DATA) >> 24) << bitpos;
+          _WBYTE(0x10000000 + Cursor, val);
+          if (bitpos == 0) Cursor++;
+        }
+        bitpos ^= 4;
+      }
+    } else {
+      // Read from Display
+      if (((oldPORT1 & _E) == 0) && ((PORT1 & _E) != 0)) {
+        // E: 0->1
+        if ((PORT1 & _RS) == 0) {
+          // Read Status
+          val = (0x7F >> bitpos) & 0x0F;
+        } else {
+          // Read Pointer
+          val = ((Cursor & 0x7F) >> bitpos) & 0x0F;
+        }
+        PORT1 &= ~_DATA;
+        PORT1 |=  val << 24;
+        bitpos ^= 4;
+      }
+    }
+    oldPORT1 = PORT1;
+  }
+}
+
+LCD_Display()
diff --git a/Ultrasonic_HC_SR04.c b/Ultrasonic_HC_SR04.c
new file mode 100644
index 0000000..4886dd6
--- /dev/null
+++ b/Ultrasonic_HC_SR04.c
@@ -0,0 +1,110 @@
+#include 
+#include 
+#include "LCD.h"
+
+	int echoTime=0;
+	float distance=0;
+	char cVal[10];
+	int k;
+	int pulsecnt;
+	
+void delayUS(unsigned long microseconds) //Using Timer0
+{
+	T1TCR = 0x02; //Reset Timer
+	T1TCR = 0x01; //Enable timer
+	while(T1TC < microseconds); //wait until timer counter reaches the desired delay
+	T1TCR = 0x00; //Disable timer
+}
+void initTimer0(void)
+{
+	PCONP |= (1<< 2);
+	//Assuming PCLK = 60Mhz
+	T1CTCR = 0x0;
+	T1PR = 11; //60 clock cycles @60Mhz = 1 us
+	T1TCR = 0x02; //Reset Timer
+}
+
+void startTimer0(void)
+{
+	T1TCR = 0x02; //Reset Timer
+	T1TCR = 0x01; //Enable timer
+}
+
+unsigned int stopTimer0(void)
+{
+	T1TCR = 0x00; //Disable timer
+	return T1TC;
+}
+
+void delayMS(unsigned int milliseconds)
+{
+	delayUS(milliseconds * 1000);
+}
+void setPins(int n, int m) {
+	#define ECHO (1<16)MU!7LbkD$q9%k&GaWF9<#w9TlOpqjIXBAM{
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diff --git a/lcd_4bit.crf b/lcd_4bit.crf
new file mode 100644
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diff --git a/lcd_4bit.d b/lcd_4bit.d
new file mode 100644
index 0000000..6e4a8ec
--- /dev/null
+++ b/lcd_4bit.d
@@ -0,0 +1,3 @@
+lcd_4bit.o: LCD_4bit.c
+lcd_4bit.o: C:\Universidad\Keil\ARM\Inc\Philips\LPC23xx.H
+lcd_4bit.o: C:\Universidad\Keil\ARM\ARMCC\bin\..\include\stdlib.h
diff --git a/lcd_4bit.o b/lcd_4bit.o
new file mode 100644
index 0000000000000000000000000000000000000000..a16d9defd407137b47c77437d6ca4f3a3a5be755
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HcmV?d00001

diff --git a/main.c b/main.c
new file mode 100644
index 0000000..7f0ba53
--- /dev/null
+++ b/main.c
@@ -0,0 +1,96 @@
+	#include 
+	#include                     /* LPC23xx definitions                */
+	#include "LCD.h"                        /* Graphic LCD function prototypes    */
+
+	extern int j,hr,min,sec;
+	extern char hrVal[2];
+	extern char minVal[2];
+	extern char secV[2];
+	
+	/* Import external IRQ handlers from IRQ.c file                               */
+	extern __irq void T0_IRQHandler  (void);
+	extern void PWM_SetDutyCycle();
+	extern void PWM_Init();
+	extern void updateRTCTimer();
+	extern void RTCTimerEnable();
+	extern void setupTimer();
+	extern void sendPulse();
+	extern void delayMS();
+	extern float calDistance();
+
+	/* Import external variables from IRQ.c file                                  */
+	extern unsigned char clock_1s;
+
+	int main(void) 
+	{
+			char cVal[20];
+			int n=2, m=3;
+			float distance=0.0;
+			int release_time_min = 0;		//mins
+			int release_time_max = 30 ;  //secs
+			int petPresence = 0, fed = 0, capTime=0;
+	
+		int feeding_time_flag = 0, pet_presence_flag = 0, isClosed = 1;
+		setupTimer(n, m);
+	
+		RTCTimerEnable();
+		PWM_Init();
+		lcd_init();
+		lcd_clear();
+		//lcd_print ("Local Time");
+		set_cursor (0, 1);
+		lcd_print ("00:00:00");
+		PWM_SetDutyCycle(5);
+		
+		while (1) {                           /* Loop forever                       */
+			updateRTCTimer();
+			sendPulse(n);
+			distance = calDistance(m);
+			
+			if(distance < 30) {
+				set_cursor(0,0);
+				sprintf(cVal, "Dis:%.2f %d", distance, release_time_min);
+				set_cursor(0,0);
+				lcd_print(cVal);
+				petPresence = 1;
+			} else if (distance < 1 ) {
+				set_cursor(0,0);
+				lcd_print("Dis too less");
+			}else {
+				petPresence = 0;
+				set_cursor(0,0);
+				sprintf(cVal, "Dis too far");
+				lcd_print(cVal);
+			}
+			
+			if(min == release_time_min && sec < release_time_max)
+			{
+				set_cursor(0, 10);
+				lcd_print("");
+				if(petPresence && !capTime) {
+						capTime = sec;
+						PWM_SetDutyCycle(10); //7
+						isClosed = 0;
+						fed = 1;
+						
+				}
+				set_cursor(12, 0);
+				sprintf(cVal, "%d", capTime);
+				lcd_print(cVal);
+				
+			}
+			if(sec ==(capTime + 2) && !isClosed) {
+							PWM_SetDutyCycle(5);
+							isClosed = 1;
+				}	
+				if(sec == release_time_max) {
+					release_time_min = (release_time_min + 1) % 60 ;
+					fed = 0; 
+					if(isClosed) capTime = 0;		
+			}
+
+			delayMS(1000); //wait 1 second for next update
+
+			lcd_clear();
+		}
+}
diff --git a/main.crf b/main.crf
new file mode 100644
index 0000000000000000000000000000000000000000..65ba35b46d2680fab6cac3b8e06d273b2e71e2c2
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diff --git a/main.d b/main.d
new file mode 100644
index 0000000..bb12f26
--- /dev/null
+++ b/main.d
@@ -0,0 +1,4 @@
+main.o: main.c
+main.o: C:\Universidad\Keil\ARM\ARMCC\bin\..\include\stdio.h
+main.o: C:\Universidad\Keil\ARM\Inc\Philips\LPC23xx.H
+main.o: LCD.h
diff --git a/main.o b/main.o
new file mode 100644
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diff --git a/servo_mg995.d b/servo_mg995.d
new file mode 100644
index 0000000..c43ae21
--- /dev/null
+++ b/servo_mg995.d
@@ -0,0 +1,5 @@
+servo_mg995.o: Servo_MG995.c
+servo_mg995.o: C:\Universidad\Keil\ARM\Inc\Philips\LPC23xx.h
+servo_mg995.o: C:\Universidad\Keil\ARM\ARMCC\bin\..\include\stdio.h
+servo_mg995.o: C:\Universidad\Keil\ARM\ARMCC\bin\..\include\stdlib.h
+servo_mg995.o: LCD.h
diff --git a/servo_mg995.o b/servo_mg995.o
new file mode 100644
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diff --git a/ultrasonic_hc_sr04.crf b/ultrasonic_hc_sr04.crf
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