diff --git a/README.md b/README.md new file mode 100644 index 00000000..d800886d --- /dev/null +++ b/README.md @@ -0,0 +1 @@ +123 \ No newline at end of file diff --git a/boards.txt b/boards.txt new file mode 100644 index 00000000..d1e32629 --- /dev/null +++ b/boards.txt @@ -0,0 +1,140 @@ +menu.LORAWAN_REGION=LORAWAN_REGION +menu.LORAWAN_MODE=LORAWAN_MODE +menu.LORAWAN_RGB=LORAWAN_RGB +############################################################## + +CubeCell-Board.name=CubeCell-Board + +CubeCell-Board.upload.tool=CubeCellflash +CubeCell-Board.upload.maximum_size=131072 +CubeCell-Board.upload.maximum_data_size=131072 +CubeCell-Board.upload.wait_for_upload_port=true + +CubeCell-Board.build.board=CubeCell-Board +CubeCell-Board.build.core=asr650x + +CubeCell-Board.menu.LORAWAN_REGION.923AS=REGION_AS923 +CubeCell-Board.menu.LORAWAN_REGION.923AS.build.band=REGION_AS923 +CubeCell-Board.menu.LORAWAN_REGION.915AU=REGION_AU915 +CubeCell-Board.menu.LORAWAN_REGION.915AU.build.band=REGION_AU915 +CubeCell-Board.menu.LORAWAN_REGION.470CN=REGION_CN470 +CubeCell-Board.menu.LORAWAN_REGION.470CN.build.band=REGION_CN470 +CubeCell-Board.menu.LORAWAN_REGION.779CN=REGION_CN779 +CubeCell-Board.menu.LORAWAN_REGION.779CN.build.band=REGION_CN779 +CubeCell-Board.menu.LORAWAN_REGION.433EU=REGION_EU433 +CubeCell-Board.menu.LORAWAN_REGION.433EU.build.band=REGION_EU433 +CubeCell-Board.menu.LORAWAN_REGION.868EU=REGION_EU868 +CubeCell-Board.menu.LORAWAN_REGION.868EU.build.band=REGION_EU868 +CubeCell-Board.menu.LORAWAN_REGION.920KR=REGION_KR920 +CubeCell-Board.menu.LORAWAN_REGION.920KR.build.band=REGION_KR920 +CubeCell-Board.menu.LORAWAN_REGION.865IN=REGION_IN865 +CubeCell-Board.menu.LORAWAN_REGION.865IN.build.band=REGION_IN865 +CubeCell-Board.menu.LORAWAN_REGION.915US=REGION_US915 +CubeCell-Board.menu.LORAWAN_REGION.915US.build.band=REGION_US915 +CubeCell-Board.menu.LORAWAN_REGION.915_HYBRID=REGION_US915_HYBRID +CubeCell-Board.menu.LORAWAN_REGION.915_HYBRID.build.band=REGION_US915_HYBRID +CubeCell-Board.menu.LORAWAN_REGION.470ACN=REGION_CN470A +CubeCell-Board.menu.LORAWAN_REGION.470ACN.build.band=REGION_CN470A + +CubeCell-Board.menu.LORAWAN_MODE.0=CLASS_A +CubeCell-Board.menu.LORAWAN_MODE.0.build.LORAWAN_MODE=CLASS_A +##CubeCell-Board.menu.LORAWAN_MODE.1=CLASS_B +##CubeCell-Board.menu.LORAWAN_MODE.1.build.LORAWAN_MODE=CLASS_B +CubeCell-Board.menu.LORAWAN_MODE.2=CLASS_C +CubeCell-Board.menu.LORAWAN_MODE.2.build.LORAWAN_MODE=CLASS_C + +CubeCell-Board.menu.LORAWAN_RGB.1=ACTIVE +CubeCell-Board.menu.LORAWAN_RGB.1.build.RGB=1 +CubeCell-Board.menu.LORAWAN_RGB.0=DEACTIVE +CubeCell-Board.menu.LORAWAN_RGB.0.build.RGB=0 +############################################################## + +CubeCell-Capsule.name=CubeCell-Capsule + +CubeCell-Capsule.upload.tool=CubeCellflash +CubeCell-Capsule.upload.maximum_size=131072 +CubeCell-Capsule.upload.maximum_data_size=131072 +CubeCell-Capsule.upload.wait_for_upload_port=true + +CubeCell-Capsule.build.board=CubeCell-Capsule +CubeCell-Capsule.build.core=asr650x + +CubeCell-Capsule.menu.LORAWAN_REGION.923AS=REGION_AS923 +CubeCell-Capsule.menu.LORAWAN_REGION.923AS.build.band=REGION_AS923 +CubeCell-Capsule.menu.LORAWAN_REGION.915AU=REGION_AU915 +CubeCell-Capsule.menu.LORAWAN_REGION.915AU.build.band=REGION_AU915 +CubeCell-Capsule.menu.LORAWAN_REGION.470CN=REGION_CN470 +CubeCell-Capsule.menu.LORAWAN_REGION.470CN.build.band=REGION_CN470 +CubeCell-Capsule.menu.LORAWAN_REGION.779CN=REGION_CN779 +CubeCell-Capsule.menu.LORAWAN_REGION.779CN.build.band=REGION_CN779 +CubeCell-Capsule.menu.LORAWAN_REGION.433EU=REGION_EU433 +CubeCell-Capsule.menu.LORAWAN_REGION.433EU.build.band=REGION_EU433 +CubeCell-Capsule.menu.LORAWAN_REGION.868EU=REGION_EU868 +CubeCell-Capsule.menu.LORAWAN_REGION.868EU.build.band=REGION_EU868 +CubeCell-Capsule.menu.LORAWAN_REGION.920KR=REGION_KR920 +CubeCell-Capsule.menu.LORAWAN_REGION.920KR.build.band=REGION_KR920 +CubeCell-Capsule.menu.LORAWAN_REGION.865IN=REGION_IN865 +CubeCell-Capsule.menu.LORAWAN_REGION.865IN.build.band=REGION_IN865 +CubeCell-Capsule.menu.LORAWAN_REGION.915US=REGION_US915 +CubeCell-Capsule.menu.LORAWAN_REGION.915US.build.band=REGION_US915 +CubeCell-Capsule.menu.LORAWAN_REGION.915_HYBRID=REGION_US915_HYBRID +CubeCell-Capsule.menu.LORAWAN_REGION.915_HYBRID.build.band=REGION_US915_HYBRID +CubeCell-Capsule.menu.LORAWAN_REGION.470ACN=REGION_CN470A +CubeCell-Capsule.menu.LORAWAN_REGION.470ACN.build.band=REGION_CN470A + +CubeCell-Capsule.menu.LORAWAN_MODE.0=CLASS_A +CubeCell-Capsule.menu.LORAWAN_MODE.0.build.LORAWAN_MODE=CLASS_A +##CubeCell-Capsule.menu.LORAWAN_MODE.1=CLASS_B +##CubeCell-Capsule.menu.LORAWAN_MODE.1.build.LORAWAN_MODE=CLASS_B +CubeCell-Capsule.menu.LORAWAN_MODE.2=CLASS_C +CubeCell-Capsule.menu.LORAWAN_MODE.2.build.LORAWAN_MODE=CLASS_C + +CubeCell-Capsule.menu.LORAWAN_RGB.1=ACTIVE +CubeCell-Capsule.menu.LORAWAN_RGB.1.build.RGB=1 +CubeCell-Capsule.menu.LORAWAN_RGB.0=DEACTIVE +CubeCell-Capsule.menu.LORAWAN_RGB.0.build.RGB=0 + +############################################################## + +CubeCell-Module.name=CubeCell-Module + +CubeCell-Module.upload.tool=CubeCellflash +CubeCell-Module.upload.maximum_size=131072 +CubeCell-Module.upload.maximum_data_size=131072 +CubeCell-Module.upload.wait_for_upload_port=true + +CubeCell-Module.build.board=CubeCell-Module +CubeCell-Module.build.core=asr650x + +CubeCell-Module.menu.LORAWAN_REGION.923AS=REGION_AS923 +CubeCell-Module.menu.LORAWAN_REGION.923AS.build.band=REGION_AS923 +CubeCell-Module.menu.LORAWAN_REGION.915AU=REGION_AU915 +CubeCell-Module.menu.LORAWAN_REGION.915AU.build.band=REGION_AU915 +CubeCell-Module.menu.LORAWAN_REGION.470CN=REGION_CN470 +CubeCell-Module.menu.LORAWAN_REGION.470CN.build.band=REGION_CN470 +CubeCell-Module.menu.LORAWAN_REGION.779CN=REGION_CN779 +CubeCell-Module.menu.LORAWAN_REGION.779CN.build.band=REGION_CN779 +CubeCell-Module.menu.LORAWAN_REGION.433EU=REGION_EU433 +CubeCell-Module.menu.LORAWAN_REGION.433EU.build.band=REGION_EU433 +CubeCell-Module.menu.LORAWAN_REGION.868EU=REGION_EU868 +CubeCell-Module.menu.LORAWAN_REGION.868EU.build.band=REGION_EU868 +CubeCell-Module.menu.LORAWAN_REGION.920KR=REGION_KR920 +CubeCell-Module.menu.LORAWAN_REGION.920KR.build.band=REGION_KR920 +CubeCell-Module.menu.LORAWAN_REGION.865IN=REGION_IN865 +CubeCell-Module.menu.LORAWAN_REGION.865IN.build.band=REGION_IN865 +CubeCell-Module.menu.LORAWAN_REGION.915US=REGION_US915 +CubeCell-Module.menu.LORAWAN_REGION.915US.build.band=REGION_US915 +CubeCell-Module.menu.LORAWAN_REGION.915_HYBRID=REGION_US915_HYBRID +CubeCell-Module.menu.LORAWAN_REGION.915_HYBRID.build.band=REGION_US915_HYBRID +CubeCell-Module.menu.LORAWAN_REGION.470ACN=REGION_CN470A +CubeCell-Module.menu.LORAWAN_REGION.470ACN.build.band=REGION_CN470A + +CubeCell-Module.menu.LORAWAN_MODE.0=CLASS_A +CubeCell-Module.menu.LORAWAN_MODE.0.build.LORAWAN_MODE=CLASS_A +##CubeCell-Module.menu.LORAWAN_MODE.1=CLASS_B +##CubeCell-Module.menu.LORAWAN_MODE.1.build.LORAWAN_MODE=CLASS_B +CubeCell-Module.menu.LORAWAN_MODE.2=CLASS_C +CubeCell-Module.menu.LORAWAN_MODE.2.build.LORAWAN_MODE=CLASS_C + +CubeCell-Module.menu.LORAWAN_RGB.0=DEACTIVE +CubeCell-Module.menu.LORAWAN_RGB.0.build.RGB=0 \ No newline at end of file diff --git a/cores/asr650x/Arduino.h b/cores/asr650x/Arduino.h new file mode 100644 index 00000000..a6acd149 --- /dev/null +++ b/cores/asr650x/Arduino.h @@ -0,0 +1,85 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2014 Arduino LLC. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef Arduino_h +#define Arduino_h + +#include +#include +#include +#include +#include +#include +#include +#include + + +//extern HardwareSerial Serial; + +#define PI 3.1415926535897932384626433832795 +#define HALF_PI 1.5707963267948966192313216916398 +#define TWO_PI 6.283185307179586476925286766559 +#define DEG_TO_RAD 0.017453292519943295769236907684886 +#define RAD_TO_DEG 57.295779513082320876798154814105 +#define EULER 2.718281828459045235360287471352 + + +#define lowByte(w) ((w) & 0xff) +#define highByte(w) ((w) >> 8) +#define bitRead(value, bit) (((value) >> (bit)) & 0x01) +#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : bitClear(value, bit)) +#define bitSet(value, bit) ((value) |= (1UL << (bit))) +#define bitClear(value, bit) ((value) &= ~(1UL << (bit))) +#define bit(b) (1 << (b)) + +#define min(a, b) ((a)<(b)?(a):(b)) +#define max(a, b) ((a)>(b)?(a):(b)) +#define abs(x) ((x)>0?(x):-(x)) +#define constrain(amt, low, high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt))) +#define _min(a,b) ((a)<(b)?(a):(b)) +#define _max(a,b) ((a)>(b)?(a):(b)) +#define noInterrupts() CyGlobalIntDisable +#define interrupts() CyGlobalIntEnable + + + + +typedef bool boolean; +typedef uint8_t byte; +typedef uint16_t word; + +// some libraries and sketches depend on this AVR stuff, +// assuming Arduino.h or WProgram.h automatically includes it... +// + + +// Include Atmel headers + +void yield( void ) ; + +/* system functions */ +int main( void ); +void init( void ); + +/* sketch */ +void setup( void ) ; +void loop( void ) ; + + +#endif // Arduino_h diff --git a/cores/asr650x/SPI/SPI.cpp b/cores/asr650x/SPI/SPI.cpp new file mode 100644 index 00000000..06a1d342 --- /dev/null +++ b/cores/asr650x/SPI/SPI.cpp @@ -0,0 +1,100 @@ +/* + SPI.cpp - SPI library for esp8266 + + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "SPI.h" +#include "project.h" + + +#define spi_TIMEOUT 500 + + +SPIClass::SPIClass(uint8_t ss):_ss(ss),_inTransaction(false){} + + +void SPIClass::begin(uint8_t ss) +{ + _ss = ss; + pinMode(_ss,OUTPUT); + SPI_1_Start(); +} + +void SPIClass::end() +{ + SPI_1_Stop(); +} + + +void SPIClass::beginTransaction(void) +{ + _inTransaction = true; + digitalWrite(_ss,LOW); +} + +void SPIClass::endTransaction() +{ + if(_inTransaction){ + _inTransaction = false; +// spiEndTransaction(_spi); + } + digitalWrite(_ss,HIGH); +} + + + +uint32_t SPIClass::transfer(uint32_t data) +{ + uint32 rxdata; + uint32 timeout = 0; + + while(SPI_1_SpiUartGetTxBufferSize() != 0); + SPI_1_SpiUartWriteTxData(data); + + while(SPI_1_SpiUartGetRxBufferSize() == 0) + { + timeout++; + if(timeout > spi_TIMEOUT )break; + } + if(timeout > spi_TIMEOUT ){} +// DBG_PRINTF("Receive Data timeout!.\r\n"); + else + { + rxdata = SPI_1_SpiUartReadRxData(); + return rxdata; + } +} + +void SPIClass::transfer(uint8_t * data, uint32_t size) +{ + //transferBytes(data, data, size); +} + + +/* @param data uint8_t * data buffer. can be NULL for Read Only operation + * @param out uint8_t * output buffer. can be NULL for Write Only operation + * @param size uint32_t + */ +void SPIClass::transferBytes(uint8_t * data, uint8_t * out, uint32_t size) +{ + +} + + +SPIClass SPI(-1); diff --git a/cores/asr650x/SPI/SPI.h b/cores/asr650x/SPI/SPI.h new file mode 100644 index 00000000..4b0fd845 --- /dev/null +++ b/cores/asr650x/SPI/SPI.h @@ -0,0 +1,50 @@ +/* + SPI.h - SPI library for esp8266 + + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + + +#include +#include +#include +#include + + +class SPIClass +{ +private: + int8_t _ss; + bool _inTransaction; + +public: + SPIClass(uint8_t ss=-1); + void begin(uint8_t ss=-1); + void end(); + void beginTransaction(void); + void endTransaction(void); + void transfer(uint8_t * data, uint32_t size); + uint32_t transfer(uint32_t data); + + void transferBytes(uint8_t * data, uint8_t * out, uint32_t size); +}; +typedef SPIClass SPIC; + +extern SPIClass SPI; + + diff --git a/cores/asr650x/Serial/HardwareSerial.cpp b/cores/asr650x/Serial/HardwareSerial.cpp new file mode 100644 index 00000000..d6b83bc4 --- /dev/null +++ b/cores/asr650x/Serial/HardwareSerial.cpp @@ -0,0 +1,120 @@ +#include +#include +#include +#include + + +#include "HardwareSerial.h" +#include "project.h" + + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_SERIAL) +HardwareSerial Serial(0); +#endif + +HardwareSerial::HardwareSerial(int uart_nr) : _uart_nr(uart_nr) {} + +void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, int8_t txPin, bool invert, unsigned long timeout_ms) +{ + uint32_t div = (float)CYDEV_BCLK__HFCLK__HZ/baud/UART_1_UART_OVS_FACTOR + 0.5 - 1; + UART_1_SCBCLK_DIV_REG = div<<8; + UART_1_SCBCLK_CMD_REG = 0x8000FF41u; + if(digitalRead(UART_RX)==UART_RX_LEVEL)//uart start when uart chip powered + { + UART_1_Start(); + } +} + +void HardwareSerial::updateBaudRate(unsigned long baud) +{ + uint32_t div = (float)CYDEV_BCLK__HFCLK__HZ/baud/UART_1_UART_OVS_FACTOR + 0.5 - 1; + UART_1_SCBCLK_DIV_REG = div<<8; + UART_1_SCBCLK_CMD_REG = 0x8000FF41u; +} + +void HardwareSerial::end() +{ + UART_1_Stop(); +} + +size_t HardwareSerial::setRxBufferSize(size_t new_size) { + // return uartResizeRxBuffer(_uart, new_size); + return 0; +} + +void HardwareSerial::setDebugOutput(bool en) +{ + /* if(_uart == 0) { + return; + } + if(en) { + uartSetDebug(_uart); + } else { + if(uartGetDebug() == _uart_nr) { + uartSetDebug(0); + } + }*/ +} + +int HardwareSerial::available(void) +{ + return UART_1_SpiUartGetRxBufferSize(); + +} +int HardwareSerial::availableForWrite(void) +{ + // return uartAvailableForWrite(_uart); + return 0; +} + +int HardwareSerial::peek(void) +{ + // if (available()) { + // return uartPeek(_uart); + // } + // return -1; + return 0; +} + +uint32 HardwareSerial::read(void) +{ + if(available()) { + return UART_1_UartGetByte(); + } + return (uint32)(-1); +} + +void HardwareSerial::flush() +{ + UART_1_SpiUartClearRxBuffer(); + UART_1_SpiUartClearTxBuffer(); +} + +size_t HardwareSerial::write(uint8_t c) +{ + UART_1_UartPutChar(c); + return 1; +} + +size_t HardwareSerial::write(const uint8_t *buffer, size_t size) +{ + uint32 bufIndex; + bufIndex = 0u; + + while(bufIndex < size) + { + UART_1_UartPutChar( buffer[bufIndex] ); + bufIndex++; + } + return size; +} +uint32_t HardwareSerial::baudRate() +{ + //return uartGetBaudRate(_uart); + return 0; +} +HardwareSerial::operator bool() const +{ + //return true; + return 0; +} diff --git a/cores/asr650x/Serial/HardwareSerial.h b/cores/asr650x/Serial/HardwareSerial.h new file mode 100644 index 00000000..d695d531 --- /dev/null +++ b/cores/asr650x/Serial/HardwareSerial.h @@ -0,0 +1,105 @@ +/* + HardwareSerial.h - Hardware serial library for Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 28 September 2010 by Mark Sproul + Modified 14 August 2012 by Alarus + Modified 3 December 2013 by Matthijs Kooijman + Modified 18 December 2014 by Ivan Grokhotkov (esp8266 platform support) + Modified 31 March 2015 by Markus Sattler (rewrite the code for UART0 + UART1 support in ESP8266) + Modified 25 April 2015 by Thomas Flayols (add configuration different from 8N1 in ESP8266) + Modified 13 October 2018 by Jeroen D枚ll (add baudrate detection) + Baudrate detection example usage (detection on Serial1): + void setup() { + Serial.begin(115200); + delay(100); + Serial.println(); + + Serial1.begin(0, SERIAL_8N1, -1, -1, true, 11000UL); // Passing 0 for baudrate to detect it, the last parameter is a timeout in ms + + unsigned long detectedBaudRate = Serial1.baudRate(); + if(detectedBaudRate) { + Serial.printf("Detected baudrate is %lu\n", detectedBaudRate); + } else { + Serial.println("No baudrate detected, Serial1 will not work!"); + } + } + + Pay attention: the baudrate returned by baudRate() may be rounded, eg 115200 returns 115201 + */ + +#ifndef HardwareSerial_h +#define HardwareSerial_h + +#include +#include +#include "Stream.h" +#include "cytypes.h" + + +class HardwareSerial: public Stream +{ +public: + HardwareSerial(int uart_nr); + + void begin(unsigned long baud, uint32_t config=-1, int8_t rxPin=-1, int8_t txPin=-1, bool invert=false, unsigned long timeout_ms = 20000UL); + void end(); + void updateBaudRate(unsigned long baud); + int available(void); + int availableForWrite(void); + int peek(void); + uint32 read(void); + void flush(void); + size_t write(uint8_t); + size_t write(const uint8_t *buffer, size_t size); + + inline size_t write(const char * s) + { + return write((uint8_t*) s, strlen(s)); + } + inline size_t write(unsigned long n) + { + return write((uint8_t) n); + } + inline size_t write(long n) + { + return write((uint8_t) n); + } + inline size_t write(unsigned int n) + { + return write((uint8_t) n); + } + inline size_t write(int n) + { + return write((uint8_t) n); + } + uint32_t baudRate(); + operator bool() const; + + size_t setRxBufferSize(size_t); + void setDebugOutput(bool); + +protected: + int _uart_nr; + //uart_t* _uart; +}; + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_SERIAL) +extern HardwareSerial Serial; +#endif + +#endif diff --git a/cores/asr650x/Wire/Wire.cpp b/cores/asr650x/Wire/Wire.cpp new file mode 100644 index 00000000..32868f0b --- /dev/null +++ b/cores/asr650x/Wire/Wire.cpp @@ -0,0 +1,386 @@ +/* + TwoWire.cpp - TWI/I2C library for Arduino & Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support + Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support + Modified Nov 2017 by Chuck Todd (ctodd@cableone.net) - ESP32 ISR Support + */ + +extern "C" { +#include +#include +#include +} + +#include "Wire.h" +#include "project.h" +#include "HardwareSerial.h" +#include "Arduino.h" + + + +TwoWire::TwoWire(uint8_t bus_num) + :num(bus_num & 1) + ,sda(-1) + ,scl(-1) + ,rxIndex(0) + ,rxLength(0) + ,rxQueued(0) + ,txIndex(0) + ,txLength(0) + ,txAddress(0) + ,txQueued(0) + ,last_error(I2C_ERROR_OK) + ,transmitting(0) + ,_timeOutMillis(50) +{} + +TwoWire::~TwoWire() +{ +} + +bool TwoWire::begin(int sdaPin, int sclPin, uint32_t frequency) +{ + delay(100); + I2C_Start(); + return true; +} + +void TwoWire::end() +{ + I2C_Stop(); +} + + +void TwoWire::setTimeOut(uint16_t timeOutMillis) +{ + _timeOutMillis = timeOutMillis; +} + +uint16_t TwoWire::getTimeOut() +{ + return _timeOutMillis; +} + +void TwoWire::setClock(uint32_t frequency) +{ +// i2cSetFrequency(i2c, frequency); +} + +size_t TwoWire::getClock() +{ +// return i2cGetFrequency(i2c); +} + +/* stickBreaker Nov 2017 ISR, and bigblock 64k-1 + */ +i2c_err_t TwoWire::writeTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop) +{ + uint8_t Status=0; + uint16_t i; + flush(); + I2C_I2CMasterClearStatus(); //清除I2C状态数据 + Status =I2C_I2CMasterSendStart(address, I2C_I2C_WRITE_XFER_MODE,I2CTIMEOUT); //发送读数据命令 + + if(Status == I2C_I2C_MSTR_NO_ERROR) + { + for(i=0;i= I2C_BUFFER_LENGTH) { + last_error = I2C_ERROR_MEMORY; + return 0; + } + txBuffer[txIndex] = data; + ++txIndex; + txLength = txIndex; + return 1; + } + last_error = I2C_ERROR_NO_BEGIN; // no begin, not transmitting + return 0; +} + +size_t TwoWire::write(const uint8_t *data, size_t quantity) +{ + for(size_t i = 0; i < quantity; ++i) { + if(!write(data[i])) { + return i; + } + } + return quantity; + +} + +int TwoWire::available(void) +{ + int result = rxLength - rxIndex; + return result; +} + +uint32 TwoWire::read(void) +{ + int value = -1; + if(rxIndex < rxLength) { + value = rxBuffer[rxIndex]; + ++rxIndex; + } + return value; +} + +int TwoWire::peek(void) +{ + int value = -1; + if(rxIndex < rxLength) { + value = rxBuffer[rxIndex]; + } + return value; +} + +void TwoWire::flush(void) +{ + rxIndex = 0; + rxLength = 0; + txIndex = 0; + txLength = 0; + rxQueued = 0; + txQueued = 0; + I2C_I2CMasterClearReadBuf(); + I2C_I2CMasterClearWriteBuf(); + I2C_RX_FIFO_CTRL_REG=I2C_RX_FIFO_CTRL_REG|I2C_RX_FIFO_CTRL_CLEAR; + I2C_RX_FIFO_CTRL_REG=I2C_RX_FIFO_CTRL_REG&(~I2C_RX_FIFO_CTRL_CLEAR); + I2C_TX_FIFO_CTRL_REG=I2C_TX_FIFO_CTRL_REG|I2C_TX_FIFO_CTRL_CLEAR; + I2C_TX_FIFO_CTRL_REG=I2C_TX_FIFO_CTRL_REG&(~I2C_TX_FIFO_CTRL_CLEAR); +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop) +{ + return requestFrom(static_cast(address), static_cast(quantity), static_cast(sendStop)); +} + +uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity, uint8_t sendStop) +{ + return requestFrom(address, static_cast(quantity), static_cast(sendStop)); +} + +uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) +{ + return requestFrom(static_cast(address), static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity) +{ + return requestFrom(address, static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity) +{ + return requestFrom(static_cast(address), static_cast(quantity), true); +} + +uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop) +{ + return static_cast(requestFrom(static_cast(address), static_cast(quantity), static_cast(sendStop))); +} + +void TwoWire::beginTransmission(int address) +{ + beginTransmission(static_cast(address)); +} + +void TwoWire::beginTransmission(uint8_t address) +{ + beginTransmission(static_cast(address)); +} + +uint8_t TwoWire::endTransmission(void) +{ + return endTransmission(true); +} + +/* stickbreaker Nov2017 better error reporting + */ +uint8_t TwoWire::lastError() +{ +// return (uint8_t)last_error; +} + +const char ERRORTEXT[] = + "OK\0" + "DEVICE\0" + "ACK\0" + "TIMEOUT\0" + "BUS\0" + "BUSY\0" + "MEMORY\0" + "CONTINUE\0" + "NO_BEGIN\0" + "\0"; + + +char * TwoWire::getErrorText(uint8_t err) +{ +/* uint8_t t = 0; + bool found = false; + char * message = (char*)&ERRORTEXT; + + while(!found && message[0]) { + found = t == err; + if(!found) { + message = message + strlen(message) + 1; + t++; + } + } + if(!found) { + return NULL; + } else { + return message; + }*/ +} + +/*stickbreaker Dump i2c Interrupt buffer, i2c isr Debugging + */ + +uint32_t TwoWire::setDebugFlags( uint32_t setBits, uint32_t resetBits){ +// return i2cDebug(i2c,setBits,resetBits); +} + +bool TwoWire::busy(void){ +// return ((i2cGetStatus(i2c) & 16 )==16); +} + +TwoWire Wire = TwoWire(0); +TwoWire Wire1 = TwoWire(1); diff --git a/cores/asr650x/Wire/Wire.h b/cores/asr650x/Wire/Wire.h new file mode 100644 index 00000000..c3008f8f --- /dev/null +++ b/cores/asr650x/Wire/Wire.h @@ -0,0 +1,163 @@ +/* + TwoWire.h - TWI/I2C library for Arduino & Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support + Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support + Modified November 2017 by Chuck Todd to use ISR and increase stability. +*/ + +#ifndef TwoWire_h +#define TwoWire_h + + +#include "Stream.h" + + +#define STICKBREAKER 'V1.1.0' +#define I2C_BUFFER_LENGTH 128 +#define I2CTIMEOUT 10 + +typedef void(*user_onRequest)(void); +typedef void(*user_onReceive)(uint8_t*, int); + +typedef enum { + I2C_ERROR_OK=0, + I2C_ERROR_DEV, + I2C_ERROR_ACK, + I2C_ERROR_TIMEOUT, + I2C_ERROR_BUS, + I2C_ERROR_BUSY, + I2C_ERROR_MEMORY, + I2C_ERROR_CONTINUE, + I2C_ERROR_NO_BEGIN +} i2c_err_t; + + + +class TwoWire: public Stream +{ +protected: + uint8_t num; + int8_t sda; + int8_t scl; + + uint8_t rxBuffer[I2C_BUFFER_LENGTH]; + uint16_t rxIndex; + uint16_t rxLength; + uint16_t rxQueued; //@stickBreaker + + uint8_t txBuffer[I2C_BUFFER_LENGTH]; + uint16_t txIndex; + uint16_t txLength; + uint16_t txAddress; + uint16_t txQueued; //@stickbreaker + i2c_err_t last_error; + uint8_t transmitting; + /* slave Mode, not yet Stickbreaker + static user_onRequest uReq[2]; + static user_onReceive uRcv[2]; + void onRequestService(void); + void onReceiveService(uint8_t*, int); + */ + + uint16_t _timeOutMillis; + +public: + TwoWire(uint8_t bus_num); + ~TwoWire(); + bool begin(int sda=-1, int scl=-1, uint32_t frequency=0); // returns true, if successful init of i2c bus + // calling will attemp to recover hung bus + void end(); + void setClock(uint32_t frequency); // change bus clock without initing hardware + size_t getClock(); // current bus clock rate in hz + + void setTimeOut(uint16_t timeOutMillis); // default timeout of i2c transactions is 50ms + uint16_t getTimeOut(); + + uint8_t lastError(); + char * getErrorText(uint8_t err); + + //@stickBreaker for big blocks and ISR model + i2c_err_t writeTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true); + i2c_err_t readTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true, uint32_t *readCount=NULL); + + void beginTransmission(uint16_t address); + void beginTransmission(uint8_t address); + void beginTransmission(int address); + + uint8_t endTransmission(bool sendStop); + uint8_t endTransmission(void); + + uint8_t requestFrom(uint16_t address, uint8_t size, bool sendStop); + uint8_t requestFrom(uint16_t address, uint8_t size, uint8_t sendStop); + uint8_t requestFrom(uint16_t address, uint8_t size); + uint8_t requestFrom(uint8_t address, uint8_t size, uint8_t sendStop); + uint8_t requestFrom(uint8_t address, uint8_t size); + uint8_t requestFrom(int address, int size, int sendStop); + uint8_t requestFrom(int address, int size); + + size_t write(uint8_t); + size_t write(const uint8_t *, size_t); + int available(void); + uint32 read(void); + int peek(void); + void flush(void); + + inline size_t write(const char * s) + { + return write((uint8_t*) s, strlen(s)); + } + inline size_t write(unsigned long n) + { + return write((uint8_t)n); + } + inline size_t write(long n) + { + return write((uint8_t)n); + } + inline size_t write(unsigned int n) + { + return write((uint8_t)n); + } + inline size_t write(int n) + { + return write((uint8_t)n); + } + + void onReceive( void (*)(int) ); + void onRequest( void (*)(void) ); + + uint32_t setDebugFlags( uint32_t setBits, uint32_t resetBits); + bool busy(); +}; + +extern TwoWire Wire; +extern TwoWire Wire1; + + +/* +V1.1.0 08JAN2019 Support CPU Clock frequency changes +V1.0.2 30NOV2018 stop returning I2C_ERROR_CONTINUE on ReSTART operations, regain compatibility with Arduino libs +V1.0.1 02AUG2018 First Fix after release, Correct ReSTART handling, change Debug control, change begin() + to a function, this allow reporting if bus cannot be initialized, Wire.begin() can be used to recover + a hung bus busy condition. +V0.2.2 13APR2018 preserve custom SCL,SDA,Frequency when no parameters passed to begin() +V0.2.1 15MAR2018 Hardware reset, Glitch prevention, adding destructor for second i2c testing +*/ +#endif diff --git a/cores/asr650x/board/board.c b/cores/asr650x/board/board.c new file mode 100644 index 00000000..671d1975 --- /dev/null +++ b/cores/asr650x/board/board.c @@ -0,0 +1,38 @@ +#include "hal/soc/soc.h" +#include + +/* Logic partition on flash devices */ +hal_logic_partition_t hal_partitions[HAL_PARTITION_MAX]; + +void board_init(void) +{ + hal_partitions[HAL_PARTITION_APPLICATION].partition_owner = HAL_FLASH_EMBEDDED; + hal_partitions[HAL_PARTITION_APPLICATION].partition_description = "Application"; + hal_partitions[HAL_PARTITION_APPLICATION].partition_start_addr = 0x00000000; + hal_partitions[HAL_PARTITION_APPLICATION].partition_length = 0x1C000; //112k bytes + hal_partitions[HAL_PARTITION_APPLICATION].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN; + + hal_partitions[HAL_PARTITION_PARAMETER_1].partition_owner = HAL_FLASH_EMBEDDED; + hal_partitions[HAL_PARTITION_PARAMETER_1].partition_description = "PARAMETER1"; + hal_partitions[HAL_PARTITION_PARAMETER_1].partition_start_addr = 0x0001C000; + hal_partitions[HAL_PARTITION_PARAMETER_1].partition_length = 0x1000; // 4k bytes + hal_partitions[HAL_PARTITION_PARAMETER_1].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN; + + hal_partitions[HAL_PARTITION_PARAMETER_2].partition_owner = HAL_FLASH_EMBEDDED; + hal_partitions[HAL_PARTITION_PARAMETER_2].partition_description = "PARAMETER2"; + hal_partitions[HAL_PARTITION_PARAMETER_2].partition_start_addr = 0x0001D000; + hal_partitions[HAL_PARTITION_PARAMETER_2].partition_length = 0x1000; //4k bytes + hal_partitions[HAL_PARTITION_PARAMETER_2].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN; + + hal_partitions[HAL_PARTITION_PARAMETER_3].partition_owner = HAL_FLASH_EMBEDDED; + hal_partitions[HAL_PARTITION_PARAMETER_3].partition_description = "PARAMETER3"; + hal_partitions[HAL_PARTITION_PARAMETER_3].partition_start_addr = 0x0001E000; + hal_partitions[HAL_PARTITION_PARAMETER_3].partition_length = 0x1000; //4k bytes + hal_partitions[HAL_PARTITION_PARAMETER_3].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN; + + hal_partitions[HAL_PARTITION_PARAMETER_4].partition_owner = HAL_FLASH_EMBEDDED; + hal_partitions[HAL_PARTITION_PARAMETER_4].partition_description = "PARAMETER4"; + hal_partitions[HAL_PARTITION_PARAMETER_4].partition_start_addr = 0x0001F000; + hal_partitions[HAL_PARTITION_PARAMETER_4].partition_length = 0x1000; //4k bytes + hal_partitions[HAL_PARTITION_PARAMETER_4].partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN; +} diff --git a/cores/asr650x/board/board.h b/cores/asr650x/board/board.h new file mode 100644 index 00000000..5577a730 --- /dev/null +++ b/cores/asr650x/board/board.h @@ -0,0 +1,157 @@ +/*! + * \file board.h + * + * \brief Target board general functions implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#ifdef BOOTLOADER +#define STDIO_UART 0 +#define STDIO_UART_BAUDRATE 115200 +#else +#define STDIO_UART 0 +#define STDIO_UART_BAUDRATE 115200 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Possible power sources + */ +enum BoardPowerSources +{ + USB_POWER = 0, + BATTERY_POWER, +}; + +/*! + * Board Version + */ +typedef union BoardVersion_u +{ + struct BoardVersion_s + { + uint8_t Rfu; + uint8_t Revision; + uint8_t Minor; + uint8_t Major; + }Fields; + uint32_t Value; +}BoardVersion_t; + +/*! + * \brief Disable interrupts + * + * \remark IRQ nesting is managed + */ +void BoardDisableIrq( void ); + +/*! + * \brief Enable interrupts + * + * \remark IRQ nesting is managed + */ +void BoardEnableIrq( void ); + +/*! + * \brief Initializes the mcu. + */ +void BoardInitMcu( void ); + +/*! + * \brief Resets the mcu. + */ +void BoardResetMcu( void ); + +/*! + * \brief Initializes the boards peripherals. + */ +void BoardInitPeriph( void ); + +/*! + * \brief De-initializes the target board peripherals to decrease power + * consumption. + */ +void BoardDeInitMcu( void ); + +/*! + * \brief Gets the current potentiometer level value + * + * \retval value Potentiometer level ( value in percent ) + */ +uint8_t BoardGetPotiLevel( void ); + +/*! + * \brief Measure the Battery voltage + * + * \retval value battery voltage in volts + */ +uint32_t BoardGetBatteryVoltage( void ); + +/*! + * \brief Get the current battery level + * + * \retval value battery level [ 0: USB, + * 1: Min level, + * x: level + * 254: fully charged, + * 255: Error] + */ +uint8_t BoardGetBatteryLevel( void ); + +/*! + * Returns a pseudo random seed generated using the MCU Unique ID + * + * \retval seed Generated pseudo random seed + */ +uint32_t BoardGetRandomSeed( void ); + +/*! + * \brief Gets the board 64 bits unique ID + * + * \param [IN] id Pointer to an array that will contain the Unique ID + */ +void BoardGetUniqueId( uint8_t *id ); + +/*! + * \brief Get the board power source + * + * \retval value power source [0: USB_POWER, 1: BATTERY_POWER] + */ +uint8_t GetBoardPowerSource( void ); + +/*! + * \brief Get the board version + * + * \retval value Version + */ +BoardVersion_t BoardGetVersion( void ); + +#ifdef __cplusplus +} +#endif + +#endif // __BOARD_H__ + diff --git a/cores/asr650x/board/inc/asr_timer.h b/cores/asr650x/board/inc/asr_timer.h new file mode 100644 index 00000000..15870462 --- /dev/null +++ b/cores/asr650x/board/inc/asr_timer.h @@ -0,0 +1,38 @@ + + + +#ifndef __ASR_TIMER_H__ +#define __ASR_TIMER_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Callback function prototype for alarm callback */ +typedef void (*asr_timer_alarm_callback_t) (void); + +/* Initialize the Timer settings */ +void Asr_Timer_Init(void); + +/* Disable the RTC and stop alarm */ +void Asr_Timer_Disable(void); + +/* Set timeout alarm */ +void Asr_SetTimeout(uint32 timeout); + +/*Get cuurent count*/ +uint32 Asr_GetCount(); + +/* Register the alarm callback function */ +bool Asr_Timer_RegisterAlarmCallback(asr_timer_alarm_callback_t alarmCallback); + +#ifdef __cplusplus +} +#endif + +#endif /* ASR_TIMER_H */ + + diff --git a/cores/asr650x/board/inc/board-config.h b/cores/asr650x/board/inc/board-config.h new file mode 100644 index 00000000..54c7e0f3 --- /dev/null +++ b/cores/asr650x/board/inc/board-config.h @@ -0,0 +1,63 @@ +/*! + * \file board-config.h + * + * \brief Board configuration + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \author Johannes Bruder ( STACKFORCE ) + */ +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ +#include "gpio.h" +#include "ASR_Arduino.h" +/*! + * Defines the time required for the TCXO to wakeup [ms]. + */ +#define BOARD_TCXO_WAKEUP_TIME 5 +/*! + * Board MCU pins definitions + */ +#define RADIO_NSS P4_3 +#define RADIO_BUSY P4_7 +#define RADIO_DIO_1 P4_6 + +#define RADIO_RESET P5_7 + +#define RADIO_MOSI P4_0 +#define RADIO_MISO P4_1 +#define RADIO_SCLK P4_2 + +#define RADIO_ANT_SWITCH_POWER P6_1 + +//#define RADIO_DEVICE_SEL DEVICE_SEL_PIN + + +// Debug pins definition. +#define RADIO_DBG_PIN_TX NC +#define RADIO_DBG_PIN_RX NC + +#endif // __BOARD_CONFIG_H__ diff --git a/cores/asr650x/board/inc/debug.h b/cores/asr650x/board/inc/debug.h new file mode 100644 index 00000000..8784aca9 --- /dev/null +++ b/cores/asr650x/board/inc/debug.h @@ -0,0 +1,144 @@ +/****************************************************************************** + * @file debug.h + * @author MCD Application Team + * @version V1.1.1 + * @date 01-June-2017 + * @brief Header for driver debug.c module + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics International N.V. + * All rights reserved.

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include "hw_conf.h" +#include "timeServer.h" +#include "utilities.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* External variables --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +typedef enum LOG_LEVEL_E { + LL_NONE, + LL_ERR, + LL_WARN, + LL_DEBUG, + LL_VDEBUG, + LL_ALL +} LOG_LEVEL; + +#ifdef CONFIG_DEBUG_LINKWAN + extern LOG_LEVEL g_log_level; + #define ERR_PRINTF(format, ...) do { \ + if(g_log_level>=LL_ERR) { \ + TimerTime_t ts = TimerGetCurrentTime(); \ + printf("[%llu]", ts); \ + printf(format, ##__VA_ARGS__); \ + } \ + }while(0) + + #define WARN_PRINTF(format, ...) do { \ + if(g_log_level>=LL_WARN) { \ + TimerTime_t ts = TimerGetCurrentTime(); \ + printf("[%llu]", ts); \ + printf(format, ##__VA_ARGS__); \ + } \ + }while(0) + + #define DBG_PRINTF(format, ...) do { \ + if(g_log_level>=LL_DEBUG) { \ + TimerTime_t ts = TimerGetCurrentTime(); \ + printf("[%llu]", ts); \ + printf(format, ##__VA_ARGS__); \ + } \ + }while(0) + + #define VDBG_PRINTF(format, ...) do { \ + if(g_log_level>=LL_VDEBUG) { \ + TimerTime_t ts = TimerGetCurrentTime(); \ + printf("[%llu]", ts); \ + printf(format, ##__VA_ARGS__); \ + } \ + }while(0) + + #define PRINTF_RAW(...) do { \ + if(g_log_level>=LL_DEBUG) printf(__VA_ARGS__); \ + }while(0) + + #define PRINTF_AT(...) printf(__VA_ARGS__) + + #define DBG_PRINTF_CRITICAL(p) +#else + #define ERR_PRINTF(format, ...) do {}while(0) + #define WARN_PRINTF(format, ...) do {}while(0) + #define DBG_PRINTF(format, ...) do {}while(0) + #define VDBG_PRINTF(format, ...) do {}while(0) + #define PRINTF_RAW(...) + #define PRINTF_AT(...) printf(__VA_ARGS__) + #define DBG_PRINTF_CRITICAL(p) +#endif + + +/* Exported functions ------------------------------------------------------- */ + +/** + * @brief Initializes the debug + * @param None + * @retval None + */ +void DBG_Init(void); +int DBG_LogLevelGet(); +void DBG_LogLevelSet(int level); + +#ifdef __cplusplus +} +#endif + +#endif /* __DEBUG_H__*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cores/asr650x/board/inc/delay-board.h b/cores/asr650x/board/inc/delay-board.h new file mode 100644 index 00000000..8ac41ef5 --- /dev/null +++ b/cores/asr650x/board/inc/delay-board.h @@ -0,0 +1,37 @@ +/*! + * \file delay-board.h + * + * \brief Target board delay implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Johannes Bruder ( STACKFORCE ) + */ +#ifndef __DELAY_BOARD_H__ +#define __DELAY_BOARD_H__ + +#include + +/*! + * \brief Blocking delay of "ms" milliseconds + * + * \param [IN] ms delay in milliseconds + */ +void DelayMsMcu( uint32_t ms ); + +#endif // __DELAY_BOARD_H__ diff --git a/cores/asr650x/board/inc/gpio-board.h b/cores/asr650x/board/inc/gpio-board.h new file mode 100644 index 00000000..ceba2dc4 --- /dev/null +++ b/cores/asr650x/board/inc/gpio-board.h @@ -0,0 +1,85 @@ +/*! + * \file gpio-board.h + * + * \brief Target board GPIO driver implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +#ifndef __GPIO_BOARD_H__ +#define __GPIO_BOARD_H__ + +#include "gpio.h" + +/*! + * \brief Initializes the given GPIO object + * + * \param [IN] obj Pointer to the GPIO object + * \param [IN] pin Pin name ( please look in pinName-board.h file ) + * \param [IN] mode Pin mode [PIN_INPUT, PIN_OUTPUT, + * PIN_ALTERNATE_FCT, PIN_ANALOGIC] + * \param [IN] config Pin config [PIN_PUSH_PULL, PIN_OPEN_DRAIN] + * \param [IN] type Pin type [PIN_NO_PULL, PIN_PULL_UP, PIN_PULL_DOWN] + * \param [IN] value Default output value at initialization + */ +void GpioMcuInit( Gpio_t *obj, PinNames pin, PINMODE mode, PinConfigs config, PinTypes type, uint32_t value ); + +/*! + * \brief GPIO IRQ Initialization + * + * \param [IN] obj Pointer to the GPIO object + * \param [IN] irqMode IRQ mode [NO_IRQ, IRQ_RISING_EDGE, + * IRQ_FALLING_EDGE, IRQ_RISING_FALLING_EDGE] + * \param [IN] irqPriority IRQ priority [IRQ_VERY_LOW_PRIORITY, IRQ_LOW_PRIORITY + * IRQ_MEDIUM_PRIORITY, IRQ_HIGH_PRIORITY + * IRQ_VERY_HIGH_PRIORITY] + * \param [IN] irqHandler Callback function pointer + */ +void GpioMcuSetInterrupt( Gpio_t *obj, IrqModes irqMode, IrqPriorities irqPriority, GpioIrqHandler irqHandler ); + +/*! + * \brief Removes the interrupt from the object + * + * \param [IN] obj Pointer to the GPIO object + */ +void GpioMcuRemoveInterrupt( Gpio_t *obj ); + +/*! + * \brief Writes the given value to the GPIO output + * + * \param [IN] obj Pointer to the GPIO object + * \param [IN] value New GPIO output value + */ +void GpioMcuWrite( Gpio_t *obj, uint32_t value ); + +/*! + * \brief Toggle the value to the GPIO output + * + * \param [IN] obj Pointer to the GPIO object + */ +void GpioMcuToggle( Gpio_t *obj ); + +/*! + * \brief Reads the current GPIO input value + * + * \param [IN] obj Pointer to the GPIO object + * \retval value Current GPIO input value + */ +uint32_t GpioMcuRead( Gpio_t *obj ); + + +#endif // __GPIO_BOARD_H__ diff --git a/cores/asr650x/board/inc/gpio.h b/cores/asr650x/board/inc/gpio.h new file mode 100644 index 00000000..db5bad17 --- /dev/null +++ b/cores/asr650x/board/inc/gpio.h @@ -0,0 +1,131 @@ +/*! + * \file gpio.h + * + * \brief GPIO driver implementation + * + * \remark: Relies on the specific board GPIO implementation as well as on + * IO expander driver implementation if one is available on the target + * board. + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#include +#include "ASR_Arduino.h" + +/*! + * Add a pull-up, a pull-down or nothing on the GPIO line + */ +typedef enum +{ + PIN_NO_PULL = 0, + PIN_PULL_UP, + PIN_PULL_DOWN +}PinTypes; + +/*! + * Define the GPIO as Push-pull type or Open Drain + */ +typedef enum +{ + PIN_PUSH_PULL = 0, + PIN_OPEN_DRAIN +}PinConfigs; + +/*! + * Define the IRQ priority on the GPIO + */ +typedef enum +{ + IRQ_VERY_LOW_PRIORITY = 0, + IRQ_LOW_PRIORITY, + IRQ_MEDIUM_PRIORITY, + IRQ_HIGH_PRIORITY, + IRQ_VERY_HIGH_PRIORITY +}IrqPriorities; + +/*! + * Structure for the GPIO + */ +typedef struct +{ + PinNames pin; + uint16_t pinIndex; + void *port; + uint16_t portIndex; + PinTypes pull; +}Gpio_t; + +/*! + * \brief Initializes the given GPIO object + * + * \param [IN] obj Pointer to the GPIO object + * \param [IN] pin Pin name ( please look in pinName-board.h file ) + * \param [IN] mode Pin mode [PIN_INPUT, PIN_OUTPUT, + * PIN_ALTERNATE_FCT, PIN_ANALOGIC] + * \param [IN] config Pin config [PIN_PUSH_PULL, PIN_OPEN_DRAIN] + * \param [IN] type Pin type [PIN_NO_PULL, PIN_PULL_UP, PIN_PULL_DOWN] + * \param [IN] value Default output value at initialization + */ +void GpioInit( Gpio_t *obj, PinNames pin, PINMODE mode, PinConfigs config, PinTypes type, uint32_t value ); + +/*! + * \brief GPIO IRQ Initialization + * + * \param [IN] obj Pointer to the GPIO object + * \param [IN] irqMode IRQ mode [NO_IRQ, IRQ_RISING_EDGE, + * IRQ_FALLING_EDGE, IRQ_RISING_FALLING_EDGE] + * \param [IN] irqPriority IRQ priority [IRQ_VERY_LOW_PRIORITY, IRQ_LOW_PRIORITY + * IRQ_MEDIUM_PRIORITY, IRQ_HIGH_PRIORITY + * IRQ_VERY_HIGH_PRIORITY] + * \param [IN] irqHandler Callback function pointer + */ +void GpioSetInterrupt( Gpio_t *obj, IrqModes irqMode, IrqPriorities irqPriority, GpioIrqHandler irqHandler ); + +/*! + * \brief Removes the interrupt from the object + * + * \param [IN] obj Pointer to the GPIO object + */ +void GpioRemoveInterrupt( Gpio_t *obj ); + +/*! + * \brief Writes the given value to the GPIO output + * + * \param [IN] obj Pointer to the GPIO object + * \param [IN] value New GPIO output value + */ +void GpioWrite( Gpio_t *obj, uint32_t value ); + +/*! + * \brief Toggle the value to the GPIO output + * + * \param [IN] obj Pointer to the GPIO object + */ +void GpioToggle( Gpio_t *obj ); + +/*! + * \brief Reads the current GPIO input value + * + * \param [IN] obj Pointer to the GPIO object + * \retval value Current GPIO input value + */ +uint32_t GpioRead( Gpio_t *obj ); +#endif // __GPIO_H__ diff --git a/cores/asr650x/board/inc/hw.h b/cores/asr650x/board/inc/hw.h new file mode 100644 index 00000000..5cdc8e8b --- /dev/null +++ b/cores/asr650x/board/inc/hw.h @@ -0,0 +1,32 @@ +#ifndef __HW_H__ +#define __HW_H__ + +#include "debug.h" +#include "hw_conf.h" + + +typedef enum +{ + e_LOW_POWER_RTC = (1 << 0), + e_LOW_POWER_GPS = (1 << 1), + e_LOW_POWER_UART = (1 << 2), /* can be used to forbid stop mode in case of uart Xfer*/ +} e_LOW_POWER_State_Id_t; + +#ifdef __cplusplus +extern "C" { +#endif +void HW_Reset(int mode); +char *HW_Get_MFT_ID(void); +uint32_t HW_Get_MFT_Baud(void); +bool HW_Set_MFT_Baud(uint32_t baud); +char *HW_Get_MFT_SN(void); +char *HW_Get_MFT_Rev(void); +char *HW_Get_MFT_Model(void); +uint8_t HW_GetBatteryLevel( void ); +void HW_GetUniqueId( uint8_t *id ); +uint32_t HW_GetRandomSeed( void ); +void BoardDriverInit(void); +#ifdef __cplusplus +} +#endif +#endif diff --git a/cores/asr650x/board/inc/hw_conf.h b/cores/asr650x/board/inc/hw_conf.h new file mode 100644 index 00000000..952bb3cd --- /dev/null +++ b/cores/asr650x/board/inc/hw_conf.h @@ -0,0 +1,86 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + +Description: contains hardaware configuration Macros and Constants + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian +*/ +/****************************************************************************** + * @file hw_conf.h + * @author MCD Application Team + * @version V1.1.1 + * @date 01-June-2017 + * @brief contains hardware configuration Macros and Constants + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics International N.V. + * All rights reserved.

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HW_CONF_H__ +#define __HW_CONF_H__ +#include +#include +#include +#include "debug.h" +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; + +#ifdef __cplusplus +extern "C" { +#endif + + + +#ifdef __cplusplus +} +#endif + +#endif /* __HW_CONF_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cores/asr650x/board/inc/lorawan_port.h b/cores/asr650x/board/inc/lorawan_port.h new file mode 100644 index 00000000..bfc3a606 --- /dev/null +++ b/cores/asr650x/board/inc/lorawan_port.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LORAWAN_PORT_H__ +#define __LORAWAN_PORT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include +#include "port.h" +#include "hal/lorawan.h" +#include "utilities.h" + + +typedef uint32_t time_ms_t; +typedef uint32_t time_tick_t; + + +extern hal_lrwan_dev_chg_mode_t aos_lrwan_chg_mode; +extern hal_lrwan_time_itf_t aos_lrwan_time_itf; +extern hal_manufactory_itf_t aos_mft_itf; +extern hal_lrwan_radio_ctrl_t aos_lrwan_radio_ctrl; + + +#ifdef __cplusplus +} +#endif + +#endif /* lorawan_port.h */ diff --git a/cores/asr650x/board/inc/rtc-board.h b/cores/asr650x/board/inc/rtc-board.h new file mode 100644 index 00000000..d0d411b4 --- /dev/null +++ b/cores/asr650x/board/inc/rtc-board.h @@ -0,0 +1,48 @@ +/*! + * \file rtc-board.h + * + * \brief Target board RTC timer and low power modes management + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ + + +#ifndef __RTC_BOARD_H__ +#define __RTC_BOARD_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * \brief Initializes the RTC timer + * + * \remark The timer is based on the RTC + */ +void RtcInit( void ); + +#ifdef __cplusplus +} +#endif + +#endif // __RTC_BOARD_H__ + + diff --git a/cores/asr650x/board/inc/spi-board.h b/cores/asr650x/board/inc/spi-board.h new file mode 100644 index 00000000..18d84488 --- /dev/null +++ b/cores/asr650x/board/inc/spi-board.h @@ -0,0 +1,113 @@ +/*! + * \file spi-board.h + * + * \brief Target board SPI driver implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ + + +#ifndef __SPI_BOARD_H__ +#define __SPI_BOARD_H__ + +#include "gpio.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * SPI peripheral ID + */ +typedef enum +{ + SPI_1, + SPI_2, +}SpiId_t; + +/*! + * SPI object type definition + */ +typedef struct Spi_s +{ + SpiId_t SpiId; + Gpio_t Mosi; + Gpio_t Miso; + Gpio_t Sclk; + Gpio_t Nss; +}Spi_t; + +/*! + * \brief Initializes the SPI object and MCU peripheral + * + * \remark When NSS pin is software controlled set the pin name to NC otherwise + * set the pin name to be used. + * + * \param [IN] obj SPI object + * \param [IN] mosi SPI MOSI pin name to be used + * \param [IN] miso SPI MISO pin name to be used + * \param [IN] sclk SPI SCLK pin name to be used + * \param [IN] nss SPI NSS pin name to be used + */ +void SpiInit(); + +/*! + * \brief De-initializes the SPI object and MCU peripheral + * + * \param [IN] obj SPI object + */ +void SpiDeInit( Spi_t *obj ); + +/*! + * \brief Configures the SPI peripheral + * + * \remark Slave mode isn't currently handled + * + * \param [IN] obj SPI object + * \param [IN] bits Number of bits to be used. [8 or 16] + * \param [IN] cpol Clock polarity + * \param [IN] cpha Clock phase + * \param [IN] slave When set the peripheral acts in slave mode + */ +void SpiFormat( Spi_t *obj, int8_t bits, int8_t cpol, int8_t cpha, int8_t slave ); + +/*! + * \brief Sets the SPI speed + * + * \param [IN] obj SPI object + * \param [IN] hz SPI clock frequency in hz + */ +void SpiFrequency( Spi_t *obj, uint32_t hz ); + +/*! + * \brief Sends outData and receives inData + * + * \param [IN] obj SPI object + * \param [IN] outData Byte to be sent + * \retval inData Received byte. + */ +uint16_t SpiInOut( Spi_t *obj, uint16_t outData ); + +#ifdef __cplusplus +} +#endif + +#endif // __SPI_BOARD_H__ + + diff --git a/cores/asr650x/board/inc/sx126x-board.h b/cores/asr650x/board/inc/sx126x-board.h new file mode 100644 index 00000000..2e13f5ac --- /dev/null +++ b/cores/asr650x/board/inc/sx126x-board.h @@ -0,0 +1,152 @@ +/*! + * \file sx126x-board.h + * + * \brief Target board SX126x driver implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +#ifndef __SX126x_BOARD_H__ +#define __SX126x_BOARD_H__ + +#include +#include +#include "sx126x.h" + +/*! + * \brief Initializes the radio I/Os pins interface + */ +void SX126xIoInit( void ); + +/*! + * \brief Initializes DIO IRQ handlers + * + * \param [IN] irqHandlers Array containing the IRQ callback functions + */ +void SX126xIoIrqInit( DioIrqHandler dioIrq ); + +/*! + * \brief De-initializes the radio I/Os pins interface. + * + * \remark Useful when going in MCU low power modes + */ +void SX126xIoDeInit( void ); + +/*! + * \brief HW Reset of the radio + */ +void SX126xReset( void ); + +/*! + * \brief Blocking loop to wait while the Busy pin in high + */ +void SX126xWaitOnBusy( void ); + +/*! + * \brief Wakes up the radio + */ +void SX126xWakeup( void ); + +/*! + * \brief Send a command that write data to the radio + * + * \param [in] opcode Opcode of the command + * \param [in] buffer Buffer to be send to the radio + * \param [in] size Size of the buffer to send + */ +void SX126xWriteCommand( RadioCommands_t opcode, uint8_t *buffer, uint16_t size ); + +/*! + * \brief Send a command that read data from the radio + * + * \param [in] opcode Opcode of the command + * \param [out] buffer Buffer holding data from the radio + * \param [in] size Size of the buffer + */ +void SX126xReadCommand( RadioCommands_t opcode, uint8_t *buffer, uint16_t size ); + +/*! + * \brief Write a single byte of data to the radio memory + * + * \param [in] address The address of the first byte to write in the radio + * \param [in] value The data to be written in radio's memory + */ +void SX126xWriteRegister( uint16_t address, uint8_t value ); + +/*! + * \brief Read a single byte of data from the radio memory + * + * \param [in] address The address of the first byte to write in the radio + * + * \retval value The value of the byte at the given address in radio's memory + */ +uint8_t SX126xReadRegister( uint16_t address ); + +/*! + * \brief Sets the radio output power. + * + * \param [IN] power Sets the RF output power + */ +void SX126xSetRfTxPower( int8_t power ); + +/*! + * \brief Gets the board PA selection configuration + * + * \param [IN] channel Channel frequency in Hz + * \retval PaSelect RegPaConfig PaSelect value + */ +uint8_t SX126xGetPaSelect( uint32_t channel ); + +/*! + * \brief Initializes the RF Switch I/Os pins interface + */ +void SX126xAntSwOn( void ); + +/*! + * \brief De-initializes the RF Switch I/Os pins interface + * + * \remark Needed to decrease the power consumption in MCU low power modes + */ +void SX126xAntSwOff( void ); + +/*! + * \brief Checks if the given RF frequency is supported by the hardware + * + * \param [IN] frequency RF frequency to be checked + * \retval isSupported [true: supported, false: unsupported] + */ +bool SX126xCheckRfFrequency( uint32_t frequency ); + +/*! + * \brief Gets the Defines the time required for the TCXO to wakeup [ms]. + * + * \retval time Board TCXO wakeup time in ms. + */ +uint32_t SX126xGetBoardTcxoWakeupTime( void ); + + +uint8_t SX126xGetPaOpt( void ); + +void SX126xSetPaOpt( uint8_t opt ); + + +/*! + * Radio hardware and global parameters + */ +extern SX126x_t SX126x; + +#endif // __SX126x_BOARD_H__ diff --git a/cores/asr650x/board/inc/uart-board.h b/cores/asr650x/board/inc/uart-board.h new file mode 100644 index 00000000..e554c4c2 --- /dev/null +++ b/cores/asr650x/board/inc/uart-board.h @@ -0,0 +1,77 @@ +#ifndef __UART_BOARD_H__ +#define __UART_BOARD_H__ + +#include +#include "uart.h" + +/*! + * \brief Initializes the UART object and MCU peripheral + * + * \param [IN] obj UART object + * \param [IN] tx UART Tx pin name to be used + * \param [IN] rx UART Rx pin name to be used + */ +void UartMcuInit( Uart_t *obj, UartId_t uartId, PinNames tx, PinNames rx ); + +/*! + * \brief Configures the UART object and MCU peripheral + * + * \remark UartInit function must be called first. + * + * \param [IN] obj UART object + * \param [IN] mode Mode of operation for the UART + * \param [IN] baudrate UART baudrate + * \param [IN] wordLength packet length + * \param [IN] stopBits stop bits setup + * \param [IN] parity packet parity + * \param [IN] flowCtrl UART flow control + */ +void UartMcuConfig( Uart_t *obj, UartMode_t mode, uint32_t baudrate, WordLength_t wordLength, StopBits_t stopBits, Parity_t parity, FlowCtrl_t flowCtrl ); + +/*! + * \brief DeInitializes the UART object and MCU pins + * + * \param [IN] obj UART object + */ +void UartMcuDeInit( Uart_t *obj ); + +/*! + * \brief Sends a character to the UART + * + * \param [IN] obj UART object + * \param [IN] data Character to be sent + * \retval status [0: OK, 1: Busy] + */ +uint8_t UartMcuPutChar( Uart_t *obj, uint8_t data ); + +/*! + * \brief Sends a buffer to the UART + * + * \param [IN] obj UART object + * \param [IN] buffer Buffer to be sent + * \param [IN] size Buffer size + * \retval status [0: OK, 1: Busy] + */ +uint8_t UartMcuPutBuffer( Uart_t *obj, uint8_t *buffer, uint16_t size ); + +/*! + * \brief Gets a character from the UART + * + * \param [IN] obj UART object + * \param [IN] data Received character + * \retval status [0: OK, 1: Busy] + */ +uint8_t UartMcuGetChar( Uart_t *obj, uint8_t *data ); + +/*! + * \brief Gets a character from the UART + * + * \param [IN] obj UART object + * \param [IN] buffer Received buffer + * \param [IN] size Number of bytes to be received + * \param [OUT] nbReadBytes Number of bytes really read + * \retval status [0: OK, 1: Busy] + */ +uint8_t UartMcuGetBuffer( Uart_t *obj, uint8_t *buffer, uint16_t size, uint16_t *nbReadBytes ); + +#endif // __UART_BOARD_H__ diff --git a/cores/asr650x/board/k_config.h b/cores/asr650x/board/k_config.h new file mode 100644 index 00000000..81972604 --- /dev/null +++ b/cores/asr650x/board/k_config.h @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef K_CONFIG_H +#define K_CONFIG_H + +/* chip level conf */ +#ifndef RHINO_CONFIG_LITTLE_ENDIAN +#define RHINO_CONFIG_LITTLE_ENDIAN 1 +#endif +#ifndef RHINO_CONFIG_CPU_STACK_DOWN +#define RHINO_CONFIG_CPU_STACK_DOWN 1 +#endif + +/* kernel feature conf */ +#ifndef RHINO_CONFIG_SEM +#define RHINO_CONFIG_SEM 1 +#endif +#ifndef RHINO_CONFIG_QUEUE +#define RHINO_CONFIG_QUEUE 1 +#endif +#ifndef RHINO_CONFIG_TASK_SEM +#define RHINO_CONFIG_TASK_SEM 1 +#endif +#ifndef RHINO_CONFIG_EVENT_FLAG +#define RHINO_CONFIG_EVENT_FLAG 1 +#endif +#ifndef RHINO_CONFIG_TIMER +#define RHINO_CONFIG_TIMER 1 +#endif +#ifndef RHINO_CONFIG_BUF_QUEUE +#define RHINO_CONFIG_BUF_QUEUE 1 +#endif +#ifndef RHINO_CONFIG_MM_BLK +#define RHINO_CONFIG_MM_BLK 1 +#endif +#ifndef RHINO_CONFIG_MM_DEBUG +#define RHINO_CONFIG_MM_DEBUG 0 +#endif +#ifndef RHINO_CONFIG_MM_TLF +#define RHINO_CONFIG_MM_TLF 1 +#endif +#ifndef RHINO_CONFIG_GCC_RETADDR +#define RHINO_CONFIG_GCC_RETADDR 1 +#endif +#ifndef RHINO_CONFIG_MM_LEAKCHECK +#define RHINO_CONFIG_MM_LEAKCHECK 0 +#endif +#define K_MM_STATISTIC 0 +#ifndef RHINO_CONFIG_KOBJ_SET +#define RHINO_CONFIG_KOBJ_SET 1 +#endif +#ifndef RHINO_CONFIG_RINGBUF_VENDOR +#define RHINO_CONFIG_RINGBUF_VENDOR 1 +#endif + +/* kernel task conf */ +#ifndef RHINO_CONFIG_TASK_SUSPEND +#define RHINO_CONFIG_TASK_SUSPEND 1 +#endif +#ifndef RHINO_CONFIG_TASK_INFO +#define RHINO_CONFIG_TASK_INFO 10 +#endif +#ifndef RHINO_CONFIG_TASK_DEL +#define RHINO_CONFIG_TASK_DEL 1 +#endif +#ifndef RHINO_CONFIG_TASK_WAIT_ABORT +#define RHINO_CONFIG_TASK_WAIT_ABORT 1 +#endif +#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK +#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1 +#endif +#ifndef RHINO_CONFIG_SCHED_RR +#define RHINO_CONFIG_SCHED_RR 1 +#endif +#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT +#define RHINO_CONFIG_TIME_SLICE_DEFAULT 10 +#endif +#ifndef RHINO_CONFIG_PRI_MAX +#define RHINO_CONFIG_PRI_MAX 64 +#endif +#ifndef RHINO_CONFIG_USER_PRI_MAX +#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2) +#endif + +/* kernel workqueue conf */ +#ifndef RHINO_CONFIG_WORKQUEUE +#define RHINO_CONFIG_WORKQUEUE 0 +#endif + +/* kernel mm_region conf */ +#ifndef RHINO_CONFIG_MM_REGION_MUTEX +#define RHINO_CONFIG_MM_REGION_MUTEX 0 +#endif + +/* kernel timer&tick conf */ +#ifndef RHINO_CONFIG_HW_COUNT +#define RHINO_CONFIG_HW_COUNT 0 +#endif +#ifndef RHINO_CONFIG_TICK_TASK +#define RHINO_CONFIG_TICK_TASK 0 +#endif +#if (RHINO_CONFIG_TICK_TASK > 0) +#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE +#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 48 +#endif +#ifndef RHINO_CONFIG_TICK_TASK_PRI +#define RHINO_CONFIG_TICK_TASK_PRI 1 +#endif +#endif +#ifndef RHINO_CONFIG_TICKLESS +#define RHINO_CONFIG_TICKLESS 0 +#endif +#ifndef RHINO_CONFIG_TICKS_PER_SECOND +#define RHINO_CONFIG_TICKS_PER_SECOND 1000 +#endif +/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */ +#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY +#define RHINO_CONFIG_TICK_HEAD_ARRAY 8 +#endif +#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE +#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 128 +#endif +#ifndef RHINO_CONFIG_TIMER_RATE +#define RHINO_CONFIG_TIMER_RATE 1 +#endif +#ifndef RHINO_CONFIG_TIMER_TASK_PRI +#define RHINO_CONFIG_TIMER_TASK_PRI 5 +#endif + +/* kernel intrpt conf */ +#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET +#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0 +#endif +#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK +#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0 +#endif +#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL +#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 8u +#endif +#ifndef RHINO_CONFIG_INTRPT_GUARD +#define RHINO_CONFIG_INTRPT_GUARD 0 +#endif + +#define RHINO_CONFIG_MM_TLF_BLK_SIZE 1024 +#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1 +/* kernel dyn alloc conf */ +#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC +#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1 +#endif +#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0) +#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG +#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30 +#endif +#ifndef RHINO_CONFIG_K_DYN_TASK_STACK +#define RHINO_CONFIG_K_DYN_TASK_STACK 64 +#endif +#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI +#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 5 +#endif +#endif + +/* kernel idle conf */ +#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE +#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 40 +#endif + +/* kernel hook conf */ +#ifndef RHINO_CONFIG_USER_HOOK +#define RHINO_CONFIG_USER_HOOK 0 +#endif + +/* kernel stats conf */ +#ifndef RHINO_CONFIG_SYSTEM_STATS +#define RHINO_CONFIG_SYSTEM_STATS 1 +#endif +#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS +#define RHINO_CONFIG_DISABLE_SCHED_STATS 0 +#endif +#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS +#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0 +#endif +#ifndef RHINO_CONFIG_CPU_USAGE_STATS +#define RHINO_CONFIG_CPU_USAGE_STATS 0 +#endif +#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI +#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2) +#endif +#ifndef RHINO_CONFIG_TASK_SCHED_STATS +#define RHINO_CONFIG_TASK_SCHED_STATS 0 +#endif +#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK +#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 64 +#endif + +/* kernel trace conf */ +#ifndef RHINO_CONFIG_TRACE +#define RHINO_CONFIG_TRACE 0 +#endif + +#ifndef RHINO_CONFIG_CPU_NUM +#define RHINO_CONFIG_CPU_NUM 1 +#endif + +#endif /* K_CONFIG_H */ + diff --git a/cores/asr650x/board/src/asr_board.c b/cores/asr650x/board/src/asr_board.c new file mode 100644 index 00000000..c7b2e289 --- /dev/null +++ b/cores/asr650x/board/src/asr_board.c @@ -0,0 +1,529 @@ +/*! + * \file sx1261dvk1bas-board.c + * + * \brief Target board SX1261DVK1BAS shield driver implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +#include +//#include "asr_project.h" +#include +#include "utilities.h" +#include "board-config.h" +#include "board.h" +#include "delay.h" +#include "radio.h" +#include "timer.h" +#include "sx126x-board.h" +#include "debug.h" + +/*! + * Antenna switch GPIO pins objects + */ +Gpio_t AntPow; +Gpio_t DeviceSel; +LOG_LEVEL g_log_level = LL_DEBUG; + +#ifdef CONFIG_LORA_USE_TCXO +bool UseTCXO = true; +#else +bool UseTCXO = false; +#endif +uint8_t gPaOptSetting = 0; +static uint32_t gBaudRate = STDIO_UART_BAUDRATE; +char gChipId[17]; + +void SX126xIoInit( void ) +{ + GpioInit( &SX126x.Spi.Nss, RADIO_NSS, OUTPUT, PIN_PUSH_PULL, PIN_PULL_UP, 1 ); + GpioInit( &SX126x.BUSY, RADIO_BUSY, INPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 ); + GpioInit( &SX126x.DIO1, RADIO_DIO_1, INPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 ); +} + +void SX126xIoIrqInit( DioIrqHandler dioIrq ) +{ + GpioSetInterrupt( &SX126x.DIO1, RISING, IRQ_HIGH_PRIORITY, dioIrq ); +} + +void SX126xIoDeInit( void ) +{ + GpioInit( &SX126x.Spi.Nss, RADIO_NSS, ANALOG, PIN_PUSH_PULL, PIN_PULL_UP, 1 ); + GpioInit( &SX126x.BUSY, RADIO_BUSY, ANALOG, PIN_PUSH_PULL, PIN_NO_PULL, 0 ); + GpioInit( &SX126x.DIO1, RADIO_DIO_1, ANALOG, PIN_PUSH_PULL, PIN_NO_PULL, 0 ); +} + +uint32_t SX126xGetBoardTcxoWakeupTime( void ) +{ + return BOARD_TCXO_WAKEUP_TIME; +} + +void SX126xReset( void ) +{ + pinMode(SX126x.Reset.pin,OUTPUT); + DelayMs( 20 ); + GpioInit( &SX126x.Reset, RADIO_RESET, OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 ); + DelayMs( 40 ); + GpioInit( &SX126x.Reset, RADIO_RESET, OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 1 ); // internal pull-up + DelayMs( 20 ); + pinMode(SX126x.Reset.pin,ANALOG); +} + +void SX126xWaitOnBusy( void ) +{ + while( GpioRead( &SX126x.BUSY ) == 1 ); +} + +void SX126xWakeup( void ) +{ + BoardDisableIrq( ); + + GpioWrite( &SX126x.Spi.Nss, 0 ); + SpiInOut( &SX126x.Spi, RADIO_GET_STATUS ); + SpiInOut( &SX126x.Spi, 0x00 ); + + GpioWrite( &SX126x.Spi.Nss, 1 ); + + // Wait for chip to be ready. + SX126xWaitOnBusy( ); + + BoardEnableIrq( ); +} + +void SX126xWriteCommand( RadioCommands_t command, uint8_t *buffer, uint16_t size ) +{ + + SX126xCheckDeviceReady( ); + GpioWrite( &SX126x.Spi.Nss, 0 ); + + SpiInOut( &SX126x.Spi, ( uint8_t )command ); + + for( uint16_t i = 0; i < size; i++ ) + { + SpiInOut( &SX126x.Spi, buffer[i] ); + } + + GpioWrite( &SX126x.Spi.Nss, 1 ); + + if( command != RADIO_SET_SLEEP ) + { + SX126xWaitOnBusy( ); + } +} + +void SX126xReadCommand( RadioCommands_t command, uint8_t *buffer, uint16_t size ) +{ + + SX126xCheckDeviceReady( ); + GpioWrite( &SX126x.Spi.Nss, 0 ); + + SpiInOut( &SX126x.Spi, ( uint8_t )command ); + SpiInOut( &SX126x.Spi, 0x00 ); + for( uint16_t i = 0; i < size; i++ ) + { + buffer[i] = SpiInOut( &SX126x.Spi, 0 ); + } + + GpioWrite( &SX126x.Spi.Nss, 1 ); + + SX126xWaitOnBusy( ); +} + +void SX126xWriteRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) +{ + SX126xCheckDeviceReady( ); + + GpioWrite( &SX126x.Spi.Nss, 0 ); + + SpiInOut( &SX126x.Spi, RADIO_WRITE_REGISTER ); + SpiInOut( &SX126x.Spi, ( address & 0xFF00 ) >> 8 ); + SpiInOut( &SX126x.Spi, address & 0x00FF ); + + for( uint16_t i = 0; i < size; i++ ) + { + SpiInOut( &SX126x.Spi, buffer[i] ); + } + + GpioWrite( &SX126x.Spi.Nss, 1 ); + + SX126xWaitOnBusy( ); +} + +void SX126xWriteRegister( uint16_t address, uint8_t value ) +{ + SX126xWriteRegisters( address, &value, 1 ); +} + +void SX126xReadRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) +{ + SX126xCheckDeviceReady( ); + + GpioWrite( &SX126x.Spi.Nss, 0 ); + + SpiInOut( &SX126x.Spi, RADIO_READ_REGISTER ); + SpiInOut( &SX126x.Spi, ( address & 0xFF00 ) >> 8 ); + SpiInOut( &SX126x.Spi, address & 0x00FF ); + SpiInOut( &SX126x.Spi, 0 ); + for( uint16_t i = 0; i < size; i++ ) + { + buffer[i] = SpiInOut( &SX126x.Spi, 0 ); + } + GpioWrite( &SX126x.Spi.Nss, 1 ); + + SX126xWaitOnBusy( ); + +} + +uint8_t SX126xReadRegister( uint16_t address ) +{ + uint8_t data; + SX126xReadRegisters( address, &data, 1 ); + return data; +} + +void SX126xWriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) +{ + + SX126xCheckDeviceReady( ); + + GpioWrite( &SX126x.Spi.Nss, 0 ); + + SpiInOut( &SX126x.Spi, RADIO_WRITE_BUFFER ); + SpiInOut( &SX126x.Spi, offset ); + for( uint16_t i = 0; i < size; i++ ) + { + SpiInOut( &SX126x.Spi, buffer[i] ); + } + GpioWrite( &SX126x.Spi.Nss, 1 ); + + SX126xWaitOnBusy( ); +} + +void SX126xReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) +{ + SX126xCheckDeviceReady( ); + + GpioWrite( &SX126x.Spi.Nss, 0 ); + + SpiInOut( &SX126x.Spi, RADIO_READ_BUFFER ); + SpiInOut( &SX126x.Spi, offset ); + SpiInOut( &SX126x.Spi, 0 ); + for( uint16_t i = 0; i < size; i++ ) + { + buffer[i] = SpiInOut( &SX126x.Spi, 0 ); + } + GpioWrite( &SX126x.Spi.Nss, 1 ); + + SX126xWaitOnBusy( ); + +} + +void SX126xSetRfTxPower( int8_t power ) +{ + SX126xSetTxParams( power, RADIO_RAMP_200_US ); +} + +uint8_t SX126xGetPaSelect( uint32_t channel ) +{ + (void)channel; + return SX1262; +} + +uint8_t SX126xGetPaOpt( ) +{ + return gPaOptSetting; +} + +void SX126xSetPaOpt( uint8_t opt ) +{ + if(opt>3) return; + + gPaOptSetting = opt; +} + +void SX126xAntSwOn( void ) +{ + //GpioInit( &AntPow, RADIO_ANT_SWITCH_POWER, OUTPUT, PIN_PUSH_PULL, PIN_PULL_UP, 1 ); +} + +void SX126xAntSwOff( void ) +{ + //GpioInit( &AntPow, RADIO_ANT_SWITCH_POWER, ANALOG, PIN_PUSH_PULL, PIN_NO_PULL, 0 ); +} + +bool SX126xCheckRfFrequency( uint32_t frequency ) +{ + (void)frequency; + // Implement check. Currently all frequencies are supported + return true; +} + + +void BoardDisableIrq( void ) +{ + CyGlobalIntDisable; +} + +void BoardEnableIrq( void ) +{ + CyGlobalIntEnable; +} + +void DelayMsMcu( uint32_t ms ) +{ + CyDelay(ms); +} + +static char *olds = NULL; +extern void *rawmemchr (__const void *__s, int __c); +char * strtok_l (char *s, const char *delim) +{ + char *token; + + if (s == NULL) s = olds; + + s += strspn (s, delim); + if (*s == '\0') { + olds = s; + return NULL; + } + + token = s; + s = strpbrk (token, delim); + if (s == NULL) + olds = rawmemchr (token, '\0'); + else { + *s = '\0'; + olds = s + 1; + } + return token; +} + + +static const double huge = 1.0e300; +#define __HI(x) *(1+(int*)&x) +#define __LO(x) *(int*)&x +double floor(double x) +{ + int i0,i1,j0; + unsigned i,j; + i0 = __HI(x); + i1 = __LO(x); + j0 = ((i0>>20)&0x7ff)-0x3ff; + if(j0<20) { + if(j0<0) { /* raise inexact if x != 0 */ + if(huge+x>0.0) {/* return 0*sign(x) if |x|<1 */ + if(i0>=0) {i0=i1=0;} + else if(((i0&0x7fffffff)|i1)!=0) + { i0=0xbff00000;i1=0;} + } + } else { + i = (0x000fffff)>>j0; + if(((i0&i)|i1)==0) return x; /* x is integral */ + if(huge+x>0.0) { /* raise inexact flag */ + if(i0<0) i0 += (0x00100000)>>j0; + i0 &= (~i); i1=0; + } + } + } else if (j0>51) { + if(j0==0x400) return x+x; /* inf or NaN */ + else return x; /* x is integral */ + } else { + i = ((unsigned)(0xffffffff))>>(j0-20); + if((i1&i)==0) return x; /* x is integral */ + if(huge+x>0.0) { /* raise inexact flag */ + if(i0<0) { + if(j0==20) i0+=1; + else { + j = i1+(1<<(52-j0)); + if(j>20)&0x7ff)-0x3ff; +// if(j0<20) { +// if(j0<0) { /* raise inexact if x != 0 */ +// if(huge+x>0.0) {/* return 0*sign(x) if |x|<1 */ +// if(i0<0) {i0=0x80000000;i1=0;} +// else if((i0|i1)!=0) { i0=0x3ff00000;i1=0;} +// } +// } else { +// i = (0x000fffff)>>j0; +// if(((i0&i)|i1)==0) return x; /* x is integral */ +// if(huge+x>0.0) { /* raise inexact flag */ +// if(i0>0) i0 += (0x00100000)>>j0; +// i0 &= (~i); i1=0; +// } +// } +// } else if (j0>51) { +// if(j0==0x400) return x+x; /* inf or NaN */ +// else return x; /* x is integral */ +// } else { +// i = ((unsigned)(0xffffffff))>>(j0-20); +// if((i1&i)==0) return x; /* x is integral */ +// if(huge+x>0.0) { /* raise inexact flag */ +// if(i0>0) { +// if(j0==20) i0+=1; +// else { +// j = i1 + (1<<(52-j0)); +// if(j>31)&1; + i1 = __LO(x); + j0 = ((i0>>20)&0x7ff)-0x3ff; + if(j0<20) { + if(j0<0) { + if(((i0&0x7fffffff)|i1)==0) return x; + i1 |= (i0&0x0fffff); + i0 &= 0xfffe0000; + i0 |= ((i1|-i1)>>12)&0x80000; + __HI(x)=i0; + w = TWO52[sx]+x; + t = w-TWO52[sx]; + i0 = __HI(t); + __HI(t) = (i0&0x7fffffff)|(sx<<31); + return t; + } else { + i = (0x000fffff)>>j0; + if(((i0&i)|i1)==0) return x; /* x is integral */ + i>>=1; + if(((i0&i)|i1)!=0) { + if(j0==19) i1 = 0x40000000; else + i0 = (i0&(~i))|((0x20000)>>j0); + } + } + } else if (j0>51) { + if(j0==0x400) return x+x; /* inf or NaN */ + else return x; /* x is integral */ + } else { + i = ((unsigned)(0xffffffff))>>(j0-20); + if((i1&i)==0) return x; /* x is integral */ + i>>=1; + if((i1&i)!=0) i1 = (i1&(~i))|((0x40000000)>>(j0-20)); + } + __HI(x) = i0; + __LO(x) = i1; + w = TWO52[sx]+x; + return w-TWO52[sx]; +} + + + +void BoardInitMcu( void ) +{ + SpiInit(); + Asr_Timer_Init(); + RtcInit(); + + pinMode(Vext,OUTPUT); + digitalWrite(Vext,HIGH); + pinMode(ADC_CTL,OUTPUT); + digitalWrite(ADC_CTL,HIGH); + SX126xIoInit(); +} + +void DBG_LogLevelSet(int level) +{ + g_log_level = level; +} + +int DBG_LogLevelGet() +{ + return g_log_level; +} + +char *HW_Get_MFT_ID(void) +{ + return CONFIG_MANUFACTURER; +} + +char *HW_Get_MFT_Model(void) +{ + return CONFIG_DEVICE_MODEL; +} + +char *HW_Get_MFT_Rev(void) +{ + return CONFIG_VERSION; +} + +char *HW_Get_MFT_SN(void) +{ + uint32_t id[2]; + CyGetUniqueId(id); + sprintf(gChipId, "%08X%08X", (unsigned int)id[0], (unsigned int)id[1]); + return gChipId; +} + +bool HW_Set_MFT_Baud(uint32_t baud) +{ + uint32_t div = (float)CYDEV_BCLK__HFCLK__HZ/baud/UART_1_UART_OVS_FACTOR + 0.5 - 1; + UART_1_SCBCLK_DIV_REG = div<<8; + UART_1_SCBCLK_CMD_REG = 0x8000FF41u; + + gBaudRate = baud; + return true; +} + +uint32_t HW_Get_MFT_Baud(void) +{ + return gBaudRate; +} + +void HW_Reset(int mode) +{ + if (mode == 0) { + CySoftwareReset(); + } else if (mode == 1) { + Bootloadable_1_Load(); + } +} diff --git a/cores/asr650x/board/src/gpio-board.c b/cores/asr650x/board/src/gpio-board.c new file mode 100644 index 00000000..fcd3cd99 --- /dev/null +++ b/cores/asr650x/board/src/gpio-board.c @@ -0,0 +1,112 @@ +/*! + * \file gpio-board.c + * + * \brief Target board GPIO driver implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +#include +//#include "asr_project.h" +#include "utilities.h" +#include "board-config.h" +#include "rtc-board.h" +#include "gpio-board.h" +#include "debug.h" +#include "ASR_Arduino.h" + +void hal_gpio_write(int pin, int value) +{ + digitalWrite(pin,value); +} + +int hal_gpio_read(int pin) +{ + return digitalRead(pin); +} + +void GpioMcuInit( Gpio_t *obj, PinNames pin, PINMODE mode, PinConfigs config, PinTypes type, uint32_t value ) +{ + obj->pin = pin; + + if( pin == NC ) + { + return; + } + + obj->pin = pin; + // Sets initial output value + pinMode(pin,mode); + GpioMcuWrite( obj, value ); + +} + +void GpioMcuSetInterrupt( Gpio_t *obj, IrqModes irqMode, IrqPriorities irqPriority, GpioIrqHandler irqHandler ) +{ + attachInterrupt(obj->pin,irqHandler,irqMode); +} + +void GpioMcuRemoveInterrupt( Gpio_t *obj ) +{ + detachInterrupt(obj->pin); +} + +void GpioMcuWrite( Gpio_t *obj, uint32_t value ) +{ + if(obj == NULL) + { + DBG_PRINTF("write gpio faild!\r\n"); + } + + // Check if pin is not connected + if( obj->pin == NC ) + { + return; + } + + hal_gpio_write(obj->pin, value); +} + +void GpioMcuToggle( Gpio_t *obj ) +{ + if(obj == NULL) + { + DBG_PRINTF("toggle gpio faild!\r\n"); + } + + // Check if pin is not connected + if( obj->pin == NC ) + { + return; + } + hal_gpio_write(obj->pin, hal_gpio_read(obj->pin) == 0 ? 1 : 0); +} + +uint32_t GpioMcuRead( Gpio_t *obj ) +{ + if( obj == NULL ) + { + DBG_PRINTF("gpio read faild!\r\n"); + } + // Check if pin is not connected + if( obj->pin == NC ) + { + return 0; + } + + return hal_gpio_read(obj->pin); +} diff --git a/cores/asr650x/board/src/gpio.c b/cores/asr650x/board/src/gpio.c new file mode 100644 index 00000000..5abb8337 --- /dev/null +++ b/cores/asr650x/board/src/gpio.c @@ -0,0 +1,57 @@ +/*! + * \file gpio.c + * + * \brief GPIO driver implementation + * + * \remark: Relies on the specific board GPIO implementation as well as on + * IO expander driver implementation if one is available on the target + * board. + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +#include "gpio-board.h" + +void GpioInit( Gpio_t *obj, PinNames pin, PINMODE mode, PinConfigs config, PinTypes type, uint32_t value ) +{ + GpioMcuInit( obj, pin, mode, config, type, value ); +} + +void GpioSetInterrupt( Gpio_t *obj, IrqModes irqMode, IrqPriorities irqPriority, GpioIrqHandler irqHandler ) +{ + GpioMcuSetInterrupt( obj, irqMode, irqPriority, irqHandler ); +} + +void GpioRemoveInterrupt( Gpio_t *obj ) +{ + GpioMcuRemoveInterrupt( obj ); +} + +void GpioWrite( Gpio_t *obj, uint32_t value ) +{ + GpioMcuWrite( obj, value ); +} + +void GpioToggle( Gpio_t *obj ) +{ + GpioMcuToggle( obj ); +} + +uint32_t GpioRead( Gpio_t *obj ) +{ + return GpioMcuRead( obj ); +} diff --git a/cores/asr650x/board/src/spi-board.c b/cores/asr650x/board/src/spi-board.c new file mode 100644 index 00000000..4e82a13c --- /dev/null +++ b/cores/asr650x/board/src/spi-board.c @@ -0,0 +1,76 @@ +/*! + * \file spi-board.c + * + * \brief Target board SPI driver implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +#include +#include "utilities.h" +#include "board.h" +#include "debug.h" +#include "gpio.h" +#include "spi-board.h" + +//#include "asr_project.h" + +void SpiInit( ) +{ + SPI_1_Start(); +} + +void SpiDeInit( Spi_t *obj ) +{ + SPI_1_Stop(); +} + +void SpiFormat( Spi_t *obj, int8_t bits, int8_t cpol, int8_t cpha, int8_t slave ) +{ + +} + +void SpiFrequency( Spi_t *obj, uint32_t hz ) +{ +} + +#define SPI_RX_TIMEOUT 500 +uint16_t SpiInOut( Spi_t *obj, uint16_t outData ) +{ + uint32 data; + uint32 timeout = 0; + + while(SPI_1_SpiUartGetTxBufferSize() != 0); + SPI_1_SpiUartWriteTxData(outData); +// trace("Send Data 0x%x...\n", outData); + + while(SPI_1_SpiUartGetRxBufferSize() == 0) + { + timeout++; + if(timeout > SPI_RX_TIMEOUT )break; + } + if(timeout > SPI_RX_TIMEOUT ) + DBG_PRINTF("Receive Data timeout!.\r\n"); + else + { + data = SPI_1_SpiUartReadRxData(); +// trace("Receive Data:0x%x.\n", data); + return data; + } + + return -1; +} diff --git a/cores/asr650x/cores/ADC_SAR_Seq.c b/cores/asr650x/cores/ADC_SAR_Seq.c new file mode 100644 index 00000000..3cdc7b9a --- /dev/null +++ b/cores/asr650x/cores/ADC_SAR_Seq.c @@ -0,0 +1,883 @@ +/******************************************************************************* +* File Name: ADC_SAR_Seq.c +* Version 2.50 +* +* Description: +* This file provides the source code to the API for the Sequencing Successive +* Approximation ADC Component Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ADC_SAR_Seq.h" +#include "ASR_Arduino.h" +#include "debug.h" +/*************************************** +* Global data allocation +***************************************/ +uint8 ADC_SAR_Seq_initVar = 0u; +volatile int16 ADC_SAR_Seq_offset[ADC_SAR_Seq_TOTAL_CHANNELS_NUM]; +volatile int32 ADC_SAR_Seq_countsPer10Volt[ADC_SAR_Seq_TOTAL_CHANNELS_NUM]; /* Gain compensation */ + + +/*************************************** +* Local data allocation +***************************************/ +/* Channels configuration generated by customiser */ +static const uint32 CYCODE ADC_SAR_Seq_channelsConfig[] = { 0x00000400u }; + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_Start +******************************************************************************** +* +* Summary: +* Performs all required initialization for this component +* and enables the power. The power will be set to the appropriate +* power based on the clock frequency. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* The ADC_SAR_Seq_initVar variable is used to indicate when/if initial +* configuration of this component has happened. The variable is initialized to +* zero and set to 1 the first time ADC_Start() is called. This allows for +* component Re-Start without re-initialization in all subsequent calls to the +* ADC_SAR_Seq_Start() routine. +* If re-initialization of the component is required the variable should be set +* to zero before call of ADC_SAR_Seq_Start() routine, or the user may call +* ADC_SAR_Seq_Init() and ADC_SAR_Seq_Enable() as done in the +* ADC_SAR_Seq_Start() routine. +* +*******************************************************************************/ +void ADC_SAR_Seq_Start(void) +{ + /* If not Initialized then initialize all required hardware and software */ + if(ADC_SAR_Seq_initVar == 0u) + { + ADC_SAR_Seq_Init(); + ADC_SAR_Seq_initVar = 1u; + } + ADC_SAR_Seq_Enable(); +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_Init +******************************************************************************** +* +* Summary: +* Initialize component's parameters to the parameters set by user in the +* customizer of the component placed onto schematic. Usually called in +* ADC_SAR_Seq_Start(). +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* The ADC_SAR_Seq_offset variable is initialized. +* +*******************************************************************************/ +void ADC_SAR_Seq_Init(void) +{ + uint32 chNum; + uint32 tmpRegVal; + int32 counts; + + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 1u) + static const uint8 CYCODE ADC_SAR_Seq_InputsPlacement[] = + { + (uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_0_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_0_PIN + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_1_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_1_PIN + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 2u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_2_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_2_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 2u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 3u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_3_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_3_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 3u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 4u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_4_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_4_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 4u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 5u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_5_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_5_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 5u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 6u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_6_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_6_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 6u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 7u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_7_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_7_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 7u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 8u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_8_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_8_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 8u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 9u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_9_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_9_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 9u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 10u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_10_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_10_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 10u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 11u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_11_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_11_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 11u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 12u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_12_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_12_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 12u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 13u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_13_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_13_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 13u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 14u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_14_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_14_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 14u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 15u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_15_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_15_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 15u */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 16u) + ,(uint8)(ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_16_PORT << 4u) | + (uint8)ADC_SAR_Seq_cy_psoc4_sarmux_8__CH_16_PIN + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 16u */ + }; + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 1u */ + + #if(ADC_SAR_Seq_IRQ_REMOVE == 0u) + /* Start and set interrupt vector */ + CyIntSetPriority(ADC_SAR_Seq_INTC_NUMBER, ADC_SAR_Seq_INTC_PRIOR_NUMBER); + (void)CyIntSetVector(ADC_SAR_Seq_INTC_NUMBER, &ADC_SAR_Seq_ISR); + #endif /* End ADC_SAR_Seq_IRQ_REMOVE */ + + /* Init SAR and MUX registers */ + ADC_SAR_Seq_SAR_CHAN_EN_REG = ADC_SAR_Seq_DEFAULT_EN_CHANNELS; + ADC_SAR_Seq_SAR_CTRL_REG |= ADC_SAR_Seq_DEFAULT_CTRL_REG_CFG | + /* Enable the SAR internal pump when global pump is enabled */ + (((ADC_SAR_Seq_PUMP_CTRL_REG & ADC_SAR_Seq_PUMP_CTRL_ENABLED) != 0u) ? + ADC_SAR_Seq_BOOSTPUMP_EN : 0u); + ADC_SAR_Seq_SAR_SAMPLE_CTRL_REG = ADC_SAR_Seq_DEFAULT_SAMPLE_CTRL_REG_CFG; + ADC_SAR_Seq_SAR_RANGE_THRES_REG = ADC_SAR_Seq_DEFAULT_RANGE_THRES_REG_CFG; + ADC_SAR_Seq_SAR_RANGE_COND_REG = ADC_SAR_Seq_COMPARE_MODE; + ADC_SAR_Seq_SAR_SAMPLE_TIME01_REG = ADC_SAR_Seq_DEFAULT_SAMPLE_TIME01_REG_CFG; + ADC_SAR_Seq_SAR_SAMPLE_TIME23_REG = ADC_SAR_Seq_DEFAULT_SAMPLE_TIME23_REG_CFG; + + /* Connect Vm to VSSA when even one channel is single-ended or multiple channels configured */ + #if(ADC_SAR_Seq_DEFAULT_MUX_SWITCH0 != 0u) + ADC_SAR_Seq_MUX_SWITCH0_REG |= ADC_SAR_Seq_DEFAULT_MUX_SWITCH0; + /* Set MUX_HW_CTRL_VSSA in MUX_SWITCH_HW_CTRL when multiple channels enabled */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 1u) + ADC_SAR_Seq_MUX_SWITCH_HW_CTRL_REG |= ADC_SAR_Seq_DEFAULT_MUX_SWITCH0; + #endif /* ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 1u */ + #endif /*ADC_SAR_Seq_CHANNELS_MODE !=0 */ + + ADC_SAR_Seq_SAR_SATURATE_INTR_MASK_REG = 0u; + ADC_SAR_Seq_SAR_RANGE_INTR_MASK_REG = 0u; + ADC_SAR_Seq_SAR_INTR_MASK_REG = ADC_SAR_Seq_SAR_INTR_MASK; + + #if(ADC_SAR_Seq_CY_SAR_IP_VER == ADC_SAR_Seq_CY_SAR_IP_VER0) + ADC_SAR_Seq_ANA_TRIM_REG = ADC_SAR_Seq_TRIM_COEF; + #endif /* (ADC_SAR_Seq_CY_SAR_IP_VER == ADC_SAR_Seq_CY_SAR_IP_VER0) */ + + /* Read and modify default configuration based on characterization */ + tmpRegVal = ADC_SAR_Seq_SAR_DFT_CTRL_REG; + tmpRegVal &= (uint32)~ADC_SAR_Seq_DCEN; + + #if(ADC_SAR_Seq_CY_SAR_IP_VER == ADC_SAR_Seq_CY_SAR_IP_VER0) + #if(ADC_SAR_Seq_NOMINAL_CLOCK_FREQ > (ADC_SAR_Seq_MAX_FREQUENCY / 2)) + tmpRegVal |= ADC_SAR_Seq_SEL_CSEL_DFT_CHAR; + #else /* clock speed < 9 Mhz */ + tmpRegVal |= ADC_SAR_Seq_DLY_INC; + #endif /* clock speed > 9 Mhz */ + #else + #if ((ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__INTERNAL1024) || \ + (ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__INTERNALVREF)) + tmpRegVal |= ADC_SAR_Seq_DLY_INC; + #else + tmpRegVal |= ADC_SAR_Seq_DCEN; + tmpRegVal &= (uint32)~ADC_SAR_Seq_DLY_INC; + #endif /* ((ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__INTERNAL1024) || \ + (ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__INTERNALVREF)) */ + #endif /* (ADC_SAR_Seq_CY_SAR_IP_VER == ADC_SAR_Seq_CY_SAR_IP_VER0) */ + + ADC_SAR_Seq_SAR_DFT_CTRL_REG = tmpRegVal; + + #if(ADC_SAR_Seq_MAX_RESOLUTION != ADC_SAR_Seq_RESOLUTION_12) + ADC_SAR_Seq_WOUNDING_REG = ADC_SAR_Seq_ALT_WOUNDING; + #endif /* ADC_SAR_Seq_MAX_RESOLUTION != ADC_SAR_Seq_RESOLUTION_12 */ + + for(chNum = 0u; chNum < ADC_SAR_Seq_TOTAL_CHANNELS_NUM; chNum++) + { + tmpRegVal = (ADC_SAR_Seq_channelsConfig[chNum] & ADC_SAR_Seq_CHANNEL_CONFIG_MASK); + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 1u) + tmpRegVal |= ADC_SAR_Seq_InputsPlacement[chNum]; + #endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 1u */ + + + /* When the part is limited to 10-bit then the SUB_RESOLUTION bit + * will be ignored and the RESOLUTION bit selects between 10-bit + * (0) and 8-bit (1) resolution. + */ + #if((ADC_SAR_Seq_MAX_RESOLUTION != ADC_SAR_Seq_RESOLUTION_12) && \ + (ADC_SAR_Seq_ALT_WOUNDING == ADC_SAR_Seq_WOUNDING_10BIT)) + tmpRegVal &= (uint32)(~ADC_SAR_Seq_ALT_RESOLUTION_ON); + #endif /* ADC_SAR_Seq_MAX_RESOLUTION != ADC_SAR_Seq_RESOLUTION_12 */ + + #if(ADC_SAR_Seq_INJ_CHANNEL_ENABLED) + if(chNum < ADC_SAR_Seq_SEQUENCED_CHANNELS_NUM) + #endif /* ADC_SAR_Seq_INJ_CHANNEL_ENABLED */ + { + CY_SET_REG32((reg32 *)(ADC_SAR_Seq_SAR_CHAN_CONFIG_IND + (uint32)(chNum << 2)), tmpRegVal); + + if((ADC_SAR_Seq_channelsConfig[chNum] & ADC_SAR_Seq_IS_SATURATE_EN_MASK) != 0u) + { + ADC_SAR_Seq_SAR_SATURATE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum); + } + + if((ADC_SAR_Seq_channelsConfig[chNum] & ADC_SAR_Seq_IS_RANGE_CTRL_EN_MASK) != 0u) + { + ADC_SAR_Seq_SAR_RANGE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum); + } + } + #if(ADC_SAR_Seq_INJ_CHANNEL_ENABLED) + else + { + CY_SET_REG32(ADC_SAR_Seq_SAR_INJ_CHAN_CONFIG_PTR, tmpRegVal | ADC_SAR_Seq_INJ_TAILGATING); + + if((ADC_SAR_Seq_channelsConfig[chNum] & ADC_SAR_Seq_IS_SATURATE_EN_MASK) != 0u) + { + ADC_SAR_Seq_SAR_INTR_MASK_REG |= ADC_SAR_Seq_INJ_SATURATE_MASK; + } + + if((ADC_SAR_Seq_channelsConfig[chNum] & ADC_SAR_Seq_IS_RANGE_CTRL_EN_MASK) != 0u) + { + ADC_SAR_Seq_SAR_INTR_MASK_REG |= ADC_SAR_Seq_INJ_RANGE_MASK; + } + } + #endif /* ADC_SAR_Seq_INJ_CHANNEL_ENABLED */ + + if((ADC_SAR_Seq_channelsConfig[chNum] & ADC_SAR_Seq_ALT_RESOLUTION_ON) != 0u) + { + counts = (int32)ADC_SAR_Seq_DEFAULT_MAX_WRK_ALT; + } + else + { + counts = (int32)ADC_SAR_Seq_SAR_WRK_MAX_12BIT; + } + + if((ADC_SAR_Seq_channelsConfig[chNum] & ADC_SAR_Seq_DIFFERENTIAL_EN) == 0u) + { + #if((ADC_SAR_Seq_DEFAULT_SE_RESULT_FORMAT_SEL == ADC_SAR_Seq__FSIGNED) && \ + (ADC_SAR_Seq_DEFAULT_NEG_INPUT_SEL == ADC_SAR_Seq__VREF)) + /* Set offset to the minus half scale to convert results to unsigned format */ + ADC_SAR_Seq_offset[chNum] = (int16)(counts / -2); + #else + ADC_SAR_Seq_offset[chNum] = 0; + #endif /* end DEFAULT_SE_RESULT_FORMAT_SEL == ADC_SAR_Seq__FSIGNED */ + } + else /* Differential channel */ + { + #if(ADC_SAR_Seq_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC_SAR_Seq__FUNSIGNED) + /* Set offset to the half scale to convert results to signed format */ + ADC_SAR_Seq_offset[chNum] = (int16)(counts / 2); + #else + ADC_SAR_Seq_offset[chNum] = 0; + #endif /* end ADC_SAR_Seq_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC_SAR_Seq__FUNSIGNED */ + } + /* Calculate gain in counts per 10 volts with rounding */ + ADC_SAR_Seq_countsPer10Volt[chNum] = (int16)(((counts * ADC_SAR_Seq_10MV_COUNTS) + + ADC_SAR_Seq_DEFAULT_VREF_MV_VALUE) / (ADC_SAR_Seq_DEFAULT_VREF_MV_VALUE * 2)); + } +} + +/******************************************************************************* +* Function Name: ADC_SAR_1_Enable +******************************************************************************** +* +* Summary: +* Enables the clock and analog power for SAR ADC. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SAR_Seq_Enable(void) +{ + if (0u == (ADC_SAR_Seq_SAR_CTRL_REG & ADC_SAR_Seq_ENABLE)) + { + #if(ADC_SAR_Seq_CY_SAR_IP_VER != ADC_SAR_Seq_CY_SAR_IP_VER0) + + while (0u != (ADC_SAR_Seq_SAR_STATUS_REG & ADC_SAR_Seq_STATUS_BUSY)) + { + /* wait for SAR to go idle to avoid deadlock */ + } + #endif /* (ADC_SAR_Seq_CY_SAR_IP_VER != ADC_SAR_Seq_CY_SAR_IP_VER0) */ + + ADC_SAR_Seq_SAR_CTRL_REG |= ADC_SAR_Seq_ENABLE; + + /* The block is ready to use 10 us after the enable signal is set high. */ + CyDelayUs(ADC_SAR_Seq_10US_DELAY); + } +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_Stop +******************************************************************************** +* +* Summary: +* This function stops ADC conversions and puts the ADC into its lowest power +* mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SAR_Seq_Stop(void) +{ + ADC_SAR_Seq_SAR_CTRL_REG &= (uint32)~ADC_SAR_Seq_ENABLE; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_StartConvert +******************************************************************************** +* +* Summary: +* Description: +* For free running mode, this API starts the conversion process and it +* runs continuously. +* +* In a triggered mode, this routine triggers every conversion by +* writing into the FW_TRIGGER bit in SAR_START_CTRL reg. In triggered mode, +* every conversion has to start by this API. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SAR_Seq_StartConvert(void) +{ + #if(ADC_SAR_Seq_DEFAULT_SAMPLE_MODE_SEL == ADC_SAR_Seq__FREERUNNING) + ADC_SAR_Seq_SAR_SAMPLE_CTRL_REG |= ADC_SAR_Seq_CONTINUOUS_EN; + #else /* Firmware trigger */ + ADC_SAR_Seq_SAR_START_CTRL_REG = ADC_SAR_Seq_FW_TRIGGER; + #endif /* End ADC_SAR_Seq_DEFAULT_SAMPLE_MODE == ADC_SAR_Seq__FREERUNNING */ + +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_StopConvert +******************************************************************************** +* +* Summary: +* Forces the ADC to stop all conversions. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SAR_Seq_StopConvert(void) +{ + #if(ADC_SAR_Seq_DEFAULT_SAMPLE_MODE_SEL == ADC_SAR_Seq__FREERUNNING) + ADC_SAR_Seq_SAR_SAMPLE_CTRL_REG &= (uint32)(~ADC_SAR_Seq_CONTINUOUS_EN); + #endif /* ADC_SAR_Seq_DEFAULT_SAMPLE_MODE == ADC_SAR_Seq__FREERUNNING */ +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IsEndConversion +******************************************************************************** +* +* Summary: +* Description: Checks for ADC end of conversion for the case one +* channel and end of scan for the case of multiple channels. It acts +* as a software version of the EOC. This function provides the +* programmer with two options. In one mode this function +* immediately returns with the conversion status. In the other mode, +* the function does not return (blocking) until the conversion has +* completed. +* +* Parameters: +* ADC_RETURN_STATUS -> Immediately returns conversion result status +* ADC_WAIT_FOR_RESULT -> Does not return until ADC complete +* ADC_RETURN_STATUS_INJ -> Immediately returns conversion result status +* for injection channel +* ADC_WAIT_FOR_RESULT_INJ -> Does not return until ADC completes injection +* channel conversion +* +* Return: +* If a non-zero value is returned, the last conversion or scan has completed. +* If the returned value is zero, the ADC is still in the process of a scan. +* +*******************************************************************************/ +uint32 ADC_SAR_Seq_IsEndConversion(uint32 retMode) +{ + uint32 status = 0u; + + if((retMode & (ADC_SAR_Seq_RETURN_STATUS | ADC_SAR_Seq_WAIT_FOR_RESULT)) != 0u) + { + do + { + status = ADC_SAR_Seq_SAR_INTR_REG & ADC_SAR_Seq_EOS_MASK; + }while((status == 0u) && ((retMode & ADC_SAR_Seq_WAIT_FOR_RESULT) != 0u)); + + if(status != 0u) + { + /* Clear EOS bit */ + ADC_SAR_Seq_SAR_INTR_REG = ADC_SAR_Seq_EOS_MASK; + } + } + + #if(ADC_SAR_Seq_INJ_CHANNEL_ENABLED) + if((retMode & (ADC_SAR_Seq_RETURN_STATUS_INJ | ADC_SAR_Seq_WAIT_FOR_RESULT_INJ)) != 0u) + { + do + { + status |= ADC_SAR_Seq_SAR_INTR_REG & ADC_SAR_Seq_INJ_EOC_MASK; + }while(((status & ADC_SAR_Seq_INJ_EOC_MASK) == 0u) && + ((retMode & ADC_SAR_Seq_WAIT_FOR_RESULT_INJ) != 0u)); + + if((status & ADC_SAR_Seq_INJ_EOC_MASK) != 0u) + { + /* Clear Injection EOS bit */ + ADC_SAR_Seq_SAR_INTR_REG = ADC_SAR_Seq_INJ_EOC_MASK; + } + } + #endif /* ADC_SAR_Seq_INJ_CHANNEL_ENABLED */ + + return (status); +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_GetResult16 +******************************************************************************** +* +* Summary: +* Gets the data available in the SAR DATA register. +* +* Parameters: +* chan: The ADC channel in which to return the result. The first channel +* is 0 and the injection channel if enabled is the number of valid channels. +* +* Return: +* Returns converted data as a signed 16-bit integer +* +*******************************************************************************/ +int16 ADC_SAR_Seq_GetResult16(uint32 chan) +{ + uint32 result; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_SAR_Seq_TOTAL_CHANNELS_NUM); + + if(chan < ADC_SAR_Seq_SEQUENCED_CHANNELS_NUM) + { + result = (CY_GET_REG32((reg32 *)(ADC_SAR_Seq_SAR_CHAN_RESULT_IND + (uint32)(chan << 2u))) & + ADC_SAR_Seq_RESULT_MASK)+1 ; + } + else + { + #if(ADC_SAR_Seq_INJ_CHANNEL_ENABLED) + result = ADC_SAR_Seq_SAR_INJ_RESULT_REG & ADC_SAR_Seq_RESULT_MASK; + #else + result = 0u; + #endif /* ADC_SAR_Seq_INJ_CHANNEL_ENABLED */ + } + + return ( (int16)result ); +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_SetChanMask +******************************************************************************** +* +* Summary: +* Sets the channel enable mask. +* +* Parameters: +* mask: Sets which channels that will be +* scanned. Setting bits for channels that do not exist will have no +* effect. For example, if only 6 channels were enabled, setting a +* mask of 0x0103 would only enable the last two channels (0 and 1). +* This API will not enable the injection channel. +* Examples: If the component is setup to sequence through 8 +* channels, a mask of 0x000F would enable channels 0, 1, 2, and 3. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SAR_Seq_SetChanMask(uint32 mask) +{ + ADC_SAR_Seq_SAR_CHAN_EN_REG = mask & ADC_SAR_Seq_MAX_CHANNELS_EN_MASK; +} + +#if(ADC_SAR_Seq_INJ_CHANNEL_ENABLED) + + + /******************************************************************************* + * Function Name: ADC_SAR_Seq_EnableInjection + ******************************************************************************** + * + * Summary: + * Enables the injection channel for the next scan only. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void ADC_SAR_Seq_EnableInjection(void) + { + ADC_SAR_Seq_SAR_INJ_CHAN_CONFIG_REG |= ADC_SAR_Seq_INJ_CHAN_EN; + } + +#endif /* ADC_SAR_Seq_INJ_CHANNEL_ENABLED */ + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_SetLowLimit +******************************************************************************** +* +* Summary: +* Sets the low limit parameter for a limit condition. +* +* Parameters: +* lowLimit: The low limit for a limit condition. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SAR_Seq_SetLowLimit(uint32 lowLimit) +{ + ADC_SAR_Seq_SAR_RANGE_THRES_REG &= (uint32)(~ADC_SAR_Seq_RANGE_LOW_MASK); + ADC_SAR_Seq_SAR_RANGE_THRES_REG |= lowLimit & ADC_SAR_Seq_RANGE_LOW_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_SetHighLimit +******************************************************************************** +* +* Summary: +* Sets the low limit parameter for a limit condition. +* +* Parameters: +* highLimit: The high limit for a limit condition. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SAR_Seq_SetHighLimit(uint32 highLimit) +{ + ADC_SAR_Seq_SAR_RANGE_THRES_REG &= (uint32)(~ADC_SAR_Seq_RANGE_HIGH_MASK); + ADC_SAR_Seq_SAR_RANGE_THRES_REG |= (uint32)(highLimit << ADC_SAR_Seq_RANGE_HIGH_OFFSET); +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_SetLimitMask +******************************************************************************** +* +* Summary: +* Sets the channel limit condition mask. +* +* Parameters: +* mask: Sets which channels that may cause a +* limit condition interrupt. Setting bits for channels that do not exist +* will have no effect. For example, if only 6 channels were enabled, +* setting a mask of 0x0103 would only enable the last two channels (0 and 1). +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SAR_Seq_SetLimitMask(uint32 mask) +{ + ADC_SAR_Seq_SAR_RANGE_INTR_MASK_REG = mask & ADC_SAR_Seq_MAX_CHANNELS_EN_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_SetSatMask +******************************************************************************** +* +* Summary: +* Sets the channel saturation event mask. +* +* Parameters: +* mask: Sets which channels that may cause a +* saturation event interrupt. Setting bits for channels that do not exist +* will have no effect. For example, if only 8 channels were enabled, +* setting a mask of 0x01C0 would only enable two channels (6 and 7). +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SAR_Seq_SetSatMask(uint32 mask) +{ + ADC_SAR_Seq_SAR_SATURATE_INTR_MASK_REG = mask & ADC_SAR_Seq_MAX_CHANNELS_EN_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_SetOffset +******************************************************************************** +* +* Summary: +* Description: Sets the ADC offset which is used by the functions +* ADC_CountsTo_uVolts, ADC_CountsTo_mVolts and ADC_CountsTo_Volts +* to substract the offset from the given reading +* before calculating the voltage conversion. +* +* Parameters: +* chan: ADC channel number. +* offset: This value is a measured value when the +* inputs are shorted or connected to the same input voltage. +* +* Return: +* None. +* +* Global variables: +* ADC_SAR_Seq_Offset: Modified to set the user provided offset. +* +*******************************************************************************/ +void ADC_SAR_Seq_SetOffset(uint32 chan, int16 offset) +{ + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_SAR_Seq_TOTAL_CHANNELS_NUM); + + ADC_SAR_Seq_offset[chan] = offset; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_SetGain +******************************************************************************** +* +* Summary: +* Description: Sets the ADC gain in counts per 10 volt for the voltage +* conversion functions below. This value is set by default by the +* reference and input range settings. It should only be used to further +* calibrate the ADC with a known input or if an external reference is +* used. Affects the ADC_CountsTo_uVolts, ADC_CountsTo_mVolts +* and ADC_CountsTo_Volts functions by supplying the correct +* conversion between ADC counts and voltage. +* +* Parameters: +* chan: ADC channel number. +* adcGain: ADC gain in counts per 10 volts. +* +* Return: +* None. +* +* Global variables: +* ADC_SAR_Seq_CountsPer10Volt: modified to set the ADC gain in counts +* per 10 volt. +* +*******************************************************************************/ +void ADC_SAR_Seq_SetGain(uint32 chan, int32 adcGain) +{ + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_SAR_Seq_TOTAL_CHANNELS_NUM); + + ADC_SAR_Seq_countsPer10Volt[chan] = adcGain; +} + + +#if(ADC_SAR_Seq_DEFAULT_JUSTIFICATION_SEL == ADC_SAR_Seq__RIGHT) + + + /******************************************************************************* + * Function Name: ADC_SAR_Seq_CountsTo_mVolts + ******************************************************************************** + * + * Summary: + * This function converts ADC counts to mVolts + * This function is not available when left data format justification selected. + * + * Parameters: + * chan: The ADC channel number. + * adcCounts: Result from the ADC conversion + * + * Return: + * Results in mVolts + * + * Global variables: + * ADC_SAR_Seq_countsPer10Volt: used to convert ADC counts to mVolts. + * ADC_SAR_Seq_Offset: Used as the offset while converting ADC counts + * to mVolts. + * + *******************************************************************************/ + int16 ADC_SAR_Seq_CountsTo_mVolts(uint32 chan, int16 adcCounts) + { + int16 mVolts; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_SAR_Seq_TOTAL_CHANNELS_NUM); + + /* Divide the adcCount when accumulate averaging mode selected */ + #if(ADC_SAR_Seq_DEFAULT_AVG_MODE == ADC_SAR_Seq__ACCUMULATE) + if((ADC_SAR_Seq_channelsConfig[chan] & ADC_SAR_Seq_AVERAGING_EN) != 0u) + { + adcCounts /= ADC_SAR_Seq_DEFAULT_AVG_SAMPLES_DIV; + } + #endif /* ADC_SAR_Seq_DEFAULT_AVG_MODE == ADC_SAR_Seq__ACCUMULATE */ + + /* Subtract ADC offset */ + adcCounts -= ADC_SAR_Seq_offset[chan]; + + mVolts = (int16)((((int32)adcCounts * ADC_SAR_Seq_10MV_COUNTS) + ( (adcCounts > 0) ? + (ADC_SAR_Seq_countsPer10Volt[chan] / 2) : (-(ADC_SAR_Seq_countsPer10Volt[chan] / 2)) )) + / ADC_SAR_Seq_countsPer10Volt[chan]); + //DebugPrintf("ADC_SAR_Seq_countsPer10Volt[chan]:%d\r\n",ADC_SAR_Seq_countsPer10Volt[chan]); + return( mVolts ); + } + + + /******************************************************************************* + * Function Name: ADC_SAR_Seq_CountsTo_uVolts + ******************************************************************************** + * + * Summary: + * This function converts ADC counts to micro Volts + * This function is not available when left data format justification selected. + * + * Parameters: + * chan: The ADC channel number. + * adcCounts: Result from the ADC conversion + * + * Return: + * Results in uVolts + * + * Global variables: + * ADC_SAR_Seq_countsPer10Volt: used to convert ADC counts to uVolts. + * ADC_SAR_Seq_Offset: Used as the offset while converting ADC counts + * to mVolts. + * + * Theory: + * Care must be taken to not exceed the maximum value for a 31 bit signed + * number in the conversion to uVolts and at the same time not loose + * resolution. + * To convert adcCounts to microVolts it is required to be multiplied + * on 10 million and later divide on gain in counts per 10V. + * + *******************************************************************************/ + int32 ADC_SAR_Seq_CountsTo_uVolts(uint32 chan, int16 adcCounts) + { + int64 uVolts; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_SAR_Seq_TOTAL_CHANNELS_NUM); + + /* Divide the adcCount when accumulate averaging mode selected */ + #if(ADC_SAR_Seq_DEFAULT_AVG_MODE == ADC_SAR_Seq__ACCUMULATE) + if((ADC_SAR_Seq_channelsConfig[chan] & ADC_SAR_Seq_AVERAGING_EN) != 0u) + { + adcCounts /= ADC_SAR_Seq_DEFAULT_AVG_SAMPLES_DIV; + } + #endif /* ADC_SAR_Seq_DEFAULT_AVG_MODE == ADC_SAR_Seq__ACCUMULATE */ + + /* Subtract ADC offset */ + adcCounts -= ADC_SAR_Seq_offset[chan]; + + uVolts = ((int64)adcCounts * ADC_SAR_Seq_10UV_COUNTS) / ADC_SAR_Seq_countsPer10Volt[chan]; + + return( (int32)uVolts ); + } + + + /******************************************************************************* + * Function Name: ADC_SAR_Seq_CountsTo_Volts + ******************************************************************************** + * + * Summary: + * Converts the ADC output to Volts as a floating point number. + * This function is not available when left data format justification selected. + * + * Parameters: + * chan: The ADC channel number. + * Result from the ADC conversion + * + * Return: + * Results in Volts + * + * Global variables: + * ADC_SAR_Seq_countsPer10Volt: used to convert ADC counts to Volts. + * ADC_SAR_Seq_Offset: Used as the offset while converting ADC counts + * to mVolts. + * + *******************************************************************************/ + float32 ADC_SAR_Seq_CountsTo_Volts(uint32 chan, int16 adcCounts) + { + float32 volts; + + /* Halt CPU in debug mode if channel is out of valid range */ + CYASSERT(chan < ADC_SAR_Seq_TOTAL_CHANNELS_NUM); + + /* Divide the adcCount when accumulate averaging mode selected */ + #if(ADC_SAR_Seq_DEFAULT_AVG_MODE == ADC_SAR_Seq__ACCUMULATE) + if((ADC_SAR_Seq_channelsConfig[chan] & ADC_SAR_Seq_AVERAGING_EN) != 0u) + { + adcCounts /= ADC_SAR_Seq_DEFAULT_AVG_SAMPLES_DIV; + } + #endif /* ADC_SAR_Seq_DEFAULT_AVG_MODE == ADC_SAR_Seq__ACCUMULATE */ + + /* Subtract ADC offset */ + adcCounts -= ADC_SAR_Seq_offset[chan]; + + volts = ((float32)adcCounts * ADC_SAR_Seq_10V_COUNTS) / (float32)ADC_SAR_Seq_countsPer10Volt[chan]; + + return( volts ); + } + + + +#endif /* End ADC_SAR_Seq_DEFAULT_JUSTIFICATION_SEL == ADC_SAR_Seq__RIGHT */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/ADC_SAR_Seq.h b/cores/asr650x/cores/ADC_SAR_Seq.h new file mode 100644 index 00000000..9922dbfc --- /dev/null +++ b/cores/asr650x/cores/ADC_SAR_Seq.h @@ -0,0 +1,808 @@ +/******************************************************************************* +* File Name: ADC_SAR_Seq.h +* Version 2.50 +* +* Description: +* This file contains the function prototypes and constants used in +* the Sequencing Successive Approximation ADC Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifdef __cplusplus + extern "C" { +#endif + + + +#if !defined(CY_ADC_SAR_SEQ_ADC_SAR_Seq_H) +#define CY_ADC_SAR_SEQ_ADC_SAR_Seq_H + +#include "cytypes.h" +#include "CyLib.h" +#include "ADC_SAR_Seq_IRQ.h" + +#define ADC_SAR_Seq_cy_psoc4_sar__CLOCK_DIV_ID 0x00000045u +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_ANA_TRIM CYREG_SAR_ANA_TRIM +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_AVG_STAT CYREG_SAR_AVG_STAT +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG00 CYREG_SAR_CHAN_CONFIG0 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG01 CYREG_SAR_CHAN_CONFIG1 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG02 CYREG_SAR_CHAN_CONFIG2 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG03 CYREG_SAR_CHAN_CONFIG3 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG04 CYREG_SAR_CHAN_CONFIG4 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG05 CYREG_SAR_CHAN_CONFIG5 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG06 CYREG_SAR_CHAN_CONFIG6 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG07 CYREG_SAR_CHAN_CONFIG7 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG08 CYREG_SAR_CHAN_CONFIG8 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG09 CYREG_SAR_CHAN_CONFIG9 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG10 CYREG_SAR_CHAN_CONFIG10 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG11 CYREG_SAR_CHAN_CONFIG11 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG12 CYREG_SAR_CHAN_CONFIG12 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG13 CYREG_SAR_CHAN_CONFIG13 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG14 CYREG_SAR_CHAN_CONFIG14 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG15 CYREG_SAR_CHAN_CONFIG15 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_EN CYREG_SAR_CHAN_EN +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT_VALID CYREG_SAR_CHAN_RESULT_VALID +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT00 CYREG_SAR_CHAN_RESULT0 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT01 CYREG_SAR_CHAN_RESULT1 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT02 CYREG_SAR_CHAN_RESULT2 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT03 CYREG_SAR_CHAN_RESULT3 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT04 CYREG_SAR_CHAN_RESULT4 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT05 CYREG_SAR_CHAN_RESULT5 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT06 CYREG_SAR_CHAN_RESULT6 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT07 CYREG_SAR_CHAN_RESULT7 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT08 CYREG_SAR_CHAN_RESULT8 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT09 CYREG_SAR_CHAN_RESULT9 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT10 CYREG_SAR_CHAN_RESULT10 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT11 CYREG_SAR_CHAN_RESULT11 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT12 CYREG_SAR_CHAN_RESULT12 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT13 CYREG_SAR_CHAN_RESULT13 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT14 CYREG_SAR_CHAN_RESULT14 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT15 CYREG_SAR_CHAN_RESULT15 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK_VALID CYREG_SAR_CHAN_WORK_VALID +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK00 CYREG_SAR_CHAN_WORK0 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK01 CYREG_SAR_CHAN_WORK1 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK02 CYREG_SAR_CHAN_WORK2 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK03 CYREG_SAR_CHAN_WORK3 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK04 CYREG_SAR_CHAN_WORK4 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK05 CYREG_SAR_CHAN_WORK5 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK06 CYREG_SAR_CHAN_WORK6 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK07 CYREG_SAR_CHAN_WORK7 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK08 CYREG_SAR_CHAN_WORK8 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK09 CYREG_SAR_CHAN_WORK9 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK10 CYREG_SAR_CHAN_WORK10 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK11 CYREG_SAR_CHAN_WORK11 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK12 CYREG_SAR_CHAN_WORK12 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK13 CYREG_SAR_CHAN_WORK13 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK14 CYREG_SAR_CHAN_WORK14 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK15 CYREG_SAR_CHAN_WORK15 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_CTRL CYREG_SAR_CTRL +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_DFT_CTRL CYREG_SAR_DFT_CTRL +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR CYREG_SAR_INTR +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_CAUSE CYREG_SAR_INTR_CAUSE +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_MASK CYREG_SAR_INTR_MASK +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_MASKED CYREG_SAR_INTR_MASKED +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_SET CYREG_SAR_INTR_SET +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR0 CYREG_SAR_MUX_SWITCH_CLEAR0 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_MUX_SWITCH_CLEAR1 CYREG_SAR_MUX_SWITCH_CLEAR1 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL CYREG_SAR_MUX_SWITCH_HW_CTRL +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_MUX_SWITCH_STATUS CYREG_SAR_MUX_SWITCH_STATUS +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_MUX_SWITCH0 CYREG_SAR_MUX_SWITCH0 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_MUX_SWITCH1 CYREG_SAR_MUX_SWITCH1 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_NUMBER 0u +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_PUMP_CTRL CYREG_SAR_PUMP_CTRL +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_COND CYREG_SAR_RANGE_COND +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR CYREG_SAR_RANGE_INTR +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR_MASK CYREG_SAR_RANGE_INTR_MASK +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR_MASKED CYREG_SAR_RANGE_INTR_MASKED +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR_SET CYREG_SAR_RANGE_INTR_SET +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_THRES CYREG_SAR_RANGE_THRES +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_SAMPLE_CTRL CYREG_SAR_SAMPLE_CTRL +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_SAMPLE_TIME01 CYREG_SAR_SAMPLE_TIME01 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_SAMPLE_TIME23 CYREG_SAR_SAMPLE_TIME23 +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR CYREG_SAR_SATURATE_INTR +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR_MASK CYREG_SAR_SATURATE_INTR_MASK +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED CYREG_SAR_SATURATE_INTR_MASKED +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR_SET CYREG_SAR_SATURATE_INTR_SET +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_START_CTRL CYREG_SAR_START_CTRL +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_STATUS CYREG_SAR_STATUS +#define ADC_SAR_Seq_cy_psoc4_sar__SAR_WOUNDING CYREG_SAR_WOUNDING + +/*************************************** +* Data Struct Definition +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 enableState; + uint32 dftRegVal; +} ADC_SAR_Seq_BACKUP_STRUCT; + + +/************************************** +* Enumerated Types and Parameters +**************************************/ + +/* Clock Source setting constants */ +#define ADC_SAR_Seq__EXTERNAL 0 +#define ADC_SAR_Seq__INTERNAL 1 + +/* Sample Mode setting constants */ +#define ADC_SAR_Seq__FREERUNNING 0 +#define ADC_SAR_Seq__HARDWARESOC 1 + +/* Reference type setting constants */ +#define ADC_SAR_Seq__VDDA_2 0 +#define ADC_SAR_Seq__VDDA 1 +#define ADC_SAR_Seq__INTERNAL1024 2 +#define ADC_SAR_Seq__INTERNAL1024BYPASSED 3 +#define ADC_SAR_Seq__INTERNALVREF 4 +#define ADC_SAR_Seq__INTERNALVREFBYPASSED 5 +#define ADC_SAR_Seq__VDDA_2BYPASSED 6 +#define ADC_SAR_Seq__EXTERNALVREF 7 + +/* Input buffer gain setting constants */ +#define ADC_SAR_Seq__DISABLED 0 +#define ADC_SAR_Seq__ONE 1 +#define ADC_SAR_Seq__TWO 2 +#define ADC_SAR_Seq__FOUR 3 +#define ADC_SAR_Seq__EIGHT 4 +#define ADC_SAR_Seq__SIXTEEN 5 + +/* Negative input setting sonstants in single ended mode */ +#define ADC_SAR_Seq__VSS 0 +#define ADC_SAR_Seq__VREF 1 +#define ADC_SAR_Seq__OTHER 2 + +/* Compare mode setting constants: +* Mode0 - Disable +* Mode1 - Result < Low_Limit +* Mode2 - Low_Limit <= Result < High_Limit +* Mode3 - High_Limit <= Result +* Mode4 - (Result < Low_Limit) or (High_Limit <= Result) +*/ +#define ADC_SAR_Seq__MODE0 0 +#define ADC_SAR_Seq__MODE1 1 +#define ADC_SAR_Seq__MODE2 2 +#define ADC_SAR_Seq__MODE3 3 + +#define ADC_SAR_Seq__RES8 0 +#define ADC_SAR_Seq__RES10 1 + +#define ADC_SAR_Seq__RIGHT 0 +#define ADC_SAR_Seq__LEFT 1 + +#define ADC_SAR_Seq__FSIGNED 1 +#define ADC_SAR_Seq__FUNSIGNED 0 + +#define ADC_SAR_Seq__ACCUMULATE 0 +#define ADC_SAR_Seq__FIXEDRESOLUTION 1 + + + +/*************************************** +* Conditional Compilation Parameters +****************************************/ + +#define ADC_SAR_Seq_CY_SAR_IP_VER0 (0u) +#define ADC_SAR_Seq_CY_SAR_IP_VER1 (1u) + +#if (CY_PSOC4_4100 || CY_PSOC4_4200) + #define ADC_SAR_Seq_CY_SAR_IP_VER (ADC_SAR_Seq_CY_SAR_IP_VER0) +#else /* Other devices */ + #define ADC_SAR_Seq_CY_SAR_IP_VER (ADC_SAR_Seq_CY_SAR_IP_VER1) +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + + +/*************************************** +* Initial Parameter Constants +***************************************/ +#define ADC_SAR_Seq_DEFAULT_SAMPLE_MODE_SEL (1u) +#define ADC_SAR_Seq_DEFAULT_VREF_SEL (1u) +#define ADC_SAR_Seq_DEFAULT_NEG_INPUT_SEL (0u) +#define ADC_SAR_Seq_DEFAULT_ALT_RESOLUTION_SEL (1u) +#define ADC_SAR_Seq_DEFAULT_JUSTIFICATION_SEL (0u) +#define ADC_SAR_Seq_DEFAULT_DIFF_RESULT_FORMAT_SEL (1u) +#define ADC_SAR_Seq_DEFAULT_SE_RESULT_FORMAT_SEL (1u) +#define ADC_SAR_Seq_DEFAULT_CLOCK_SOURCE (1u) +#define ADC_SAR_Seq_DEFAULT_VREF_MV_VALUE (3300) +#define ADC_SAR_Seq_DEFAULT_BUFFER_GAIN (0u) +#define ADC_SAR_Seq_DEFAULT_AVG_SAMPLES_NUM (7u) +#define ADC_SAR_Seq_DEFAULT_AVG_SAMPLES_DIV (7u < 4u) ? (int16)(0x100u >> (7u - 7u)) : (int16)(0x100u >> 4u) +#define ADC_SAR_Seq_DEFAULT_AVG_MODE (1u) +#define ADC_SAR_Seq_MAX_RESOLUTION (12u) +#define ADC_SAR_Seq_DEFAULT_LOW_LIMIT (0u) +#define ADC_SAR_Seq_DEFAULT_HIGH_LIMIT (2047u) +#define ADC_SAR_Seq_DEFAULT_COMPARE_MODE (0u) +#define ADC_SAR_Seq_DEFAULT_ACLKS_NUM (6u) +#define ADC_SAR_Seq_DEFAULT_BCLKS_NUM (2u) +#define ADC_SAR_Seq_DEFAULT_CCLKS_NUM (2u) +#define ADC_SAR_Seq_DEFAULT_DCLKS_NUM (2u) +#define ADC_SAR_Seq_TOTAL_CHANNELS_NUM (1u) +#define ADC_SAR_Seq_SEQUENCED_CHANNELS_NUM (1u) +#define ADC_SAR_Seq_DEFAULT_EN_CHANNELS (1u) +#define ADC_SAR_Seq_NOMINAL_CLOCK_FREQ (1000000) +#define ADC_SAR_Seq_INJ_CHANNEL_ENABLED (0u) +#define ADC_SAR_Seq_IRQ_REMOVE (0u) + +/* Determines whether the configuration contains external negative input. */ +#define ADC_SAR_Seq_SINGLE_PRESENT (0u) +#define ADC_SAR_Seq_CHANNELS_MODE (0u) +#define ADC_SAR_Seq_MAX_CHANNELS_EN_MASK (0xffffu >> (16u - ADC_SAR_Seq_SEQUENCED_CHANNELS_NUM)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void ADC_SAR_Seq_Start(void); +void ADC_SAR_Seq_Stop(void); +void ADC_SAR_Seq_Init(void); +void ADC_SAR_Seq_Enable(void); +void ADC_SAR_Seq_StartConvert(void); +void ADC_SAR_Seq_StopConvert(void); +uint32 ADC_SAR_Seq_IsEndConversion(uint32 retMode); +int16 ADC_SAR_Seq_GetResult16(uint32 chan); +void ADC_SAR_Seq_SetChanMask(uint32 mask); +void ADC_SAR_Seq_SetLowLimit(uint32 lowLimit); +void ADC_SAR_Seq_SetHighLimit(uint32 highLimit); +void ADC_SAR_Seq_SetLimitMask(uint32 mask); +void ADC_SAR_Seq_SetSatMask(uint32 mask); +void ADC_SAR_Seq_SetOffset(uint32 chan, int16 offset); +void ADC_SAR_Seq_SetGain(uint32 chan, int32 adcGain); +#if(ADC_SAR_Seq_INJ_CHANNEL_ENABLED) + void ADC_SAR_Seq_EnableInjection(void); +#endif /* ADC_SAR_Seq_INJ_CHANNEL_ENABLED */ +#if(ADC_SAR_Seq_DEFAULT_JUSTIFICATION_SEL == ADC_SAR_Seq__RIGHT) + int16 ADC_SAR_Seq_CountsTo_mVolts(uint32 chan, int16 adcCounts); + int32 ADC_SAR_Seq_CountsTo_uVolts(uint32 chan, int16 adcCounts); + float32 ADC_SAR_Seq_CountsTo_Volts(uint32 chan, int16 adcCounts); +#endif /* End ADC_SAR_Seq_DEFAULT_JUSTIFICATION_SEL == ADC_SAR_Seq__RIGHT */ +void ADC_SAR_Seq_Sleep(void); +void ADC_SAR_Seq_Wakeup(void); +void ADC_SAR_Seq_SaveConfig(void); +void ADC_SAR_Seq_RestoreConfig(void); + +CY_ISR_PROTO( ADC_SAR_Seq_ISR ); + + +/************************************** +* API Constants +**************************************/ +/* Constants for Sleep mode states */ +#define ADC_SAR_Seq_DISABLED (0x00u) +#define ADC_SAR_Seq_ENABLED (0x01u) +#define ADC_SAR_Seq_STARTED (0x02u) +#define ADC_SAR_Seq_BOOSTPUMP_ENABLED (0x04u) + +/* Constants for IsEndConversion() "retMode" parameter */ +#define ADC_SAR_Seq_RETURN_STATUS (0x01u) +#define ADC_SAR_Seq_WAIT_FOR_RESULT (0x02u) +#define ADC_SAR_Seq_RETURN_STATUS_INJ (0x04u) +#define ADC_SAR_Seq_WAIT_FOR_RESULT_INJ (0x08u) + +#define ADC_SAR_Seq_MAX_FREQUENCY (18000000) /*18Mhz*/ + +#define ADC_SAR_Seq_RESOLUTION_12 (12u) +#define ADC_SAR_Seq_RESOLUTION_10 (10u) +#define ADC_SAR_Seq_RESOLUTION_8 (8u) + +#define ADC_SAR_Seq_10US_DELAY (10u) + +#define ADC_SAR_Seq_10V_COUNTS (10.0F) +#define ADC_SAR_Seq_10MV_COUNTS (10000) +#define ADC_SAR_Seq_10UV_COUNTS (10000000L) + + +/*************************************** +* Global variables external identifier +***************************************/ + +extern uint8 ADC_SAR_Seq_initVar; +extern volatile int16 ADC_SAR_Seq_offset[ADC_SAR_Seq_TOTAL_CHANNELS_NUM]; +extern volatile int32 ADC_SAR_Seq_countsPer10Volt[ADC_SAR_Seq_TOTAL_CHANNELS_NUM]; + + +/*************************************** +* Registers +***************************************/ + +#define ADC_SAR_Seq_SAR_CTRL_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CTRL ) +#define ADC_SAR_Seq_SAR_CTRL_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CTRL ) + +#define ADC_SAR_Seq_SAR_SAMPLE_CTRL_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SAMPLE_CTRL ) +#define ADC_SAR_Seq_SAR_SAMPLE_CTRL_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SAMPLE_CTRL ) + +#define ADC_SAR_Seq_SAR_SAMPLE_TIME01_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SAMPLE_TIME01 ) +#define ADC_SAR_Seq_SAR_SAMPLE_TIME01_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SAMPLE_TIME01 ) + +#define ADC_SAR_Seq_SAR_SAMPLE_TIME23_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SAMPLE_TIME23 ) +#define ADC_SAR_Seq_SAR_SAMPLE_TIME23_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SAMPLE_TIME23 ) + +#define ADC_SAR_Seq_SAR_RANGE_THRES_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_THRES ) +#define ADC_SAR_Seq_SAR_RANGE_THRES_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_THRES ) + +#define ADC_SAR_Seq_SAR_RANGE_COND_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_COND ) +#define ADC_SAR_Seq_SAR_RANGE_COND_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_COND ) + +#define ADC_SAR_Seq_SAR_CHAN_EN_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_EN ) +#define ADC_SAR_Seq_SAR_CHAN_EN_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_EN ) + +#define ADC_SAR_Seq_SAR_START_CTRL_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_START_CTRL ) +#define ADC_SAR_Seq_SAR_START_CTRL_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_START_CTRL ) + +#define ADC_SAR_Seq_SAR_DFT_CTRL_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_DFT_CTRL ) +#define ADC_SAR_Seq_SAR_DFT_CTRL_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_DFT_CTRL ) + +#define ADC_SAR_Seq_SAR_CHAN_CONFIG_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG00 ) +#define ADC_SAR_Seq_SAR_CHAN_CONFIG_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG00 ) +#define ADC_SAR_Seq_SAR_CHAN_CONFIG_IND ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_CONFIG00 + +#define ADC_SAR_Seq_SAR_CHAN_WORK_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK00 ) +#define ADC_SAR_Seq_SAR_CHAN_WORK_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK00 ) + +#define ADC_SAR_Seq_SAR_CHAN_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT00 ) +#define ADC_SAR_Seq_SAR_CHAN_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT00 ) +#define ADC_SAR_Seq_SAR_CHAN_RESULT_IND ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT00 + +#define ADC_SAR_Seq_SAR_CHAN0_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT00 ) +#define ADC_SAR_Seq_SAR_CHAN0_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT00 ) + +#define ADC_SAR_Seq_SAR_CHAN1_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT01 ) +#define ADC_SAR_Seq_SAR_CHAN1_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT01 ) + +#define ADC_SAR_Seq_SAR_CHAN2_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT02 ) +#define ADC_SAR_Seq_SAR_CHAN2_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT02 ) + +#define ADC_SAR_Seq_SAR_CHAN3_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT03 ) +#define ADC_SAR_Seq_SAR_CHAN3_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT03 ) + +#define ADC_SAR_Seq_SAR_CHAN4_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT04 ) +#define ADC_SAR_Seq_SAR_CHAN4_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT04 ) + +#define ADC_SAR_Seq_SAR_CHAN5_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT05 ) +#define ADC_SAR_Seq_SAR_CHAN5_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT05 ) + +#define ADC_SAR_Seq_SAR_CHAN6_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT06 ) +#define ADC_SAR_Seq_SAR_CHAN6_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT06 ) + +#define ADC_SAR_Seq_SAR_CHAN7_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT07 ) +#define ADC_SAR_Seq_SAR_CHAN7_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT07 ) + +#if(ADC_SAR_Seq_CY_SAR_IP_VER != ADC_SAR_Seq_CY_SAR_IP_VER0) + #define ADC_SAR_Seq_SAR_CHAN8_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT08 ) + #define ADC_SAR_Seq_SAR_CHAN8_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT08 ) + + #define ADC_SAR_Seq_SAR_CHAN9_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT09 ) + #define ADC_SAR_Seq_SAR_CHAN9_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT09 ) + + #define ADC_SAR_Seq_SAR_CHAN10_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT10 ) + #define ADC_SAR_Seq_SAR_CHAN10_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT10 ) + + #define ADC_SAR_Seq_SAR_CHAN11_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT11 ) + #define ADC_SAR_Seq_SAR_CHAN11_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT11 ) + + #define ADC_SAR_Seq_SAR_CHAN12_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT12 ) + #define ADC_SAR_Seq_SAR_CHAN12_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT12 ) + + #define ADC_SAR_Seq_SAR_CHAN13_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT13 ) + #define ADC_SAR_Seq_SAR_CHAN13_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT13 ) + + #define ADC_SAR_Seq_SAR_CHAN14_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT14 ) + #define ADC_SAR_Seq_SAR_CHAN14_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT14 ) + + #define ADC_SAR_Seq_SAR_CHAN15_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT15 ) + #define ADC_SAR_Seq_SAR_CHAN15_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT15 ) +#endif /* (ADC_SAR_Seq_CY_SAR_IP_VER != ADC_SAR_Seq_CY_SAR_IP_VER0) */ + +#define ADC_SAR_Seq_SAR_CHAN_WORK_VALID_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK_VALID) +#define ADC_SAR_Seq_SAR_CHAN_WORK_VALID_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_WORK_VALID) + +#define ADC_SAR_Seq_SAR_CHAN_RESULT_VALID_REG ( *(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT_VALID ) +#define ADC_SAR_Seq_SAR_CHAN_RESULT_VALID_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_CHAN_RESULT_VALID ) + +#define ADC_SAR_Seq_SAR_STATUS_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_STATUS ) +#define ADC_SAR_Seq_SAR_STATUS_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_STATUS ) + +#define ADC_SAR_Seq_SAR_AVG_START_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_AVG_STAT ) +#define ADC_SAR_Seq_SAR_AVG_START_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_AVG_STAT ) + +#define ADC_SAR_Seq_SAR_INTR_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR ) +#define ADC_SAR_Seq_SAR_INTR_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR ) + +#define ADC_SAR_Seq_SAR_INTR_SET_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_SET ) +#define ADC_SAR_Seq_SAR_INTR_SET_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_SET ) + +#define ADC_SAR_Seq_SAR_INTR_MASK_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_MASK ) +#define ADC_SAR_Seq_SAR_INTR_MASK_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_MASK ) + +#define ADC_SAR_Seq_SAR_INTR_MASKED_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_MASKED ) +#define ADC_SAR_Seq_SAR_INTR_MASKED_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_MASKED ) + +#define ADC_SAR_Seq_SAR_SATURATE_INTR_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR ) +#define ADC_SAR_Seq_SAR_SATURATE_INTR_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR ) + +#define ADC_SAR_Seq_SAR_SATURATE_INTR_SET_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR_SET ) +#define ADC_SAR_Seq_SAR_SATURATE_INTR_SET_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR_SET ) + +#define ADC_SAR_Seq_SAR_SATURATE_INTR_MASK_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR_MASK ) +#define ADC_SAR_Seq_SAR_SATURATE_INTR_MASK_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR_MASK ) + +#define ADC_SAR_Seq_SAR_SATURATE_INTR_MASKED_REG \ + (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED ) +#define ADC_SAR_Seq_SAR_SATURATE_INTR_MASKED_PTR \ + ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED ) + +#define ADC_SAR_Seq_SAR_RANGE_INTR_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR ) +#define ADC_SAR_Seq_SAR_RANGE_INTR_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR ) + +#define ADC_SAR_Seq_SAR_RANGE_INTR_SET_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR_SET ) +#define ADC_SAR_Seq_SAR_RANGE_INTR_SET_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR_SET ) + +#define ADC_SAR_Seq_SAR_RANGE_INTR_MASK_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR_MASK ) +#define ADC_SAR_Seq_SAR_RANGE_INTR_MASK_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR_MASK ) + +#define ADC_SAR_Seq_SAR_RANGE_INTR_MASKED_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR_MASKED ) +#define ADC_SAR_Seq_SAR_RANGE_INTR_MASKED_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_RANGE_INTR_MASKED ) + +#define ADC_SAR_Seq_SAR_INTR_CAUSE_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_CAUSE ) +#define ADC_SAR_Seq_SAR_INTR_CAUSE_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_INTR_CAUSE ) + +#if(ADC_SAR_Seq_INJ_CHANNEL_ENABLED) + #define ADC_SAR_Seq_SAR_INJ_CHAN_CONFIG_REG \ + (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sarmux_8__SAR_INJ_CHAN_CONFIG ) + #define ADC_SAR_Seq_SAR_INJ_CHAN_CONFIG_PTR \ + ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sarmux_8__SAR_INJ_CHAN_CONFIG ) + + #define ADC_SAR_Seq_SAR_INJ_RESULT_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sarmux_8__SAR_INJ_RESULT ) + #define ADC_SAR_Seq_SAR_INJ_RESULT_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sarmux_8__SAR_INJ_RESULT ) +#endif /* ADC_SAR_Seq_INJ_CHANNEL_ENABLED */ + +#define ADC_SAR_Seq_MUX_SWITCH0_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_MUX_SWITCH0 ) +#define ADC_SAR_Seq_MUX_SWITCH0_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_MUX_SWITCH0 ) + +#define ADC_SAR_Seq_MUX_SWITCH_HW_CTRL_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL ) +#define ADC_SAR_Seq_MUX_SWITCH_HW_CTRL_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL ) + +#define ADC_SAR_Seq_PUMP_CTRL_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_PUMP_CTRL ) +#define ADC_SAR_Seq_PUMP_CTRL_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_PUMP_CTRL ) + +#define ADC_SAR_Seq_ANA_TRIM_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_ANA_TRIM ) +#define ADC_SAR_Seq_ANA_TRIM_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_ANA_TRIM ) + +#define ADC_SAR_Seq_WOUNDING_REG (*(reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_WOUNDING ) +#define ADC_SAR_Seq_WOUNDING_PTR ( (reg32 *) ADC_SAR_Seq_cy_psoc4_sar__SAR_WOUNDING ) + + +/************************************** +* Register Constants +**************************************/ +#define ADC_SAR_Seq_INTC_NUMBER (ADC_SAR_Seq_IRQ__INTC_NUMBER) +#define ADC_SAR_Seq_INTC_PRIOR_NUMBER (ADC_SAR_Seq_IRQ__INTC_PRIOR_NUM) + +/* defines for CTRL register */ +#define ADC_SAR_Seq_VREF_INTERNAL1024 (0x00000040Lu) +#define ADC_SAR_Seq_VREF_EXTERNAL (0x00000050Lu) +#define ADC_SAR_Seq_VREF_VDDA_2 (0x00000060Lu) +#define ADC_SAR_Seq_VREF_VDDA (0x00000070Lu) +#define ADC_SAR_Seq_VREF_INTERNAL1024BYPASSED (0x000000C0Lu) +#define ADC_SAR_Seq_VREF_VDDA_2BYPASSED (0x000000E0Lu) +#define ADC_SAR_Seq_VREF_INTERNALVREF (0x00000040Lu) +#define ADC_SAR_Seq_VREF_INTERNALVREFBYPASSED (0x000000C0Lu) + +#define ADC_SAR_Seq_NEG_VSSA_KELVIN (0x00000000Lu) +#define ADC_SAR_Seq_NEG_VSSA (0x00000200Lu) +#define ADC_SAR_Seq_NEG_VREF (0x00000E00Lu) +#if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 1u) + #define ADC_SAR_Seq_NEG_OTHER (uint16)((uint16)ADC_SAR_Seq_cy_psoc4_sarmux_8__VNEG0 << 9u) +#else + #define ADC_SAR_Seq_NEG_OTHER (0) +#endif /* ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 1u */ + +#define ADC_SAR_Seq_SAR_HW_CTRL_NEGVREF (0x00002000Lu) + +#define ADC_SAR_Seq_BOOSTPUMP_EN (0x00100000Lu) + +#define ADC_SAR_Seq_NORMAL_PWR (0x00000000Lu) +#define ADC_SAR_Seq_HALF_PWR (0x01000000Lu) +#define ADC_SAR_Seq_MORE_PWR (0x02000000Lu) +#define ADC_SAR_Seq_QUARTER_PWR (0x03000000Lu) +#define ADC_SAR_Seq_DEEPSLEEP_ON (0x08000000Lu) + +#define ADC_SAR_Seq_DSI_SYNC_CONFIG (0x10000000Lu) +#define ADC_SAR_Seq_DSI_MODE (0x20000000Lu) +#define ADC_SAR_Seq_SWITCH_DISABLE (0x40000000Lu) +#define ADC_SAR_Seq_ENABLE (0x80000000Lu) + +/* defines for STATUS register */ +#define ADC_SAR_Seq_STATUS_BUSY (0x80000000Lu) + +/* defines for SAMPLE_CTRL register */ +#define ADC_SAR_Seq_ALT_RESOLUTION_10BIT (0x00000001Lu) +#define ADC_SAR_Seq_ALT_RESOLUTION_8BIT (0x00000000Lu) + +#define ADC_SAR_Seq_DATA_ALIGN_LEFT (0x00000002Lu) +#define ADC_SAR_Seq_DATA_ALIGN_RIGHT (0x00000000Lu) + +#define ADC_SAR_Seq_SE_SIGNED_RESULT (0x00000004Lu) +#define ADC_SAR_Seq_SE_UNSIGNED_RESULT (0x00000000Lu) + +#define ADC_SAR_Seq_DIFF_SIGNED_RESULT (0x00000008Lu) +#define ADC_SAR_Seq_DIFF_UNSIGNED_RESULT (0x00000000Lu) + +#define ADC_SAR_Seq_AVG_CNT_OFFSET (4u) +#define ADC_SAR_Seq_AVG_CNT_MASK (0x00000070Lu) +#define ADC_SAR_Seq_AVG_SHIFT (0x00000080Lu) + +#define ADC_SAR_Seq_CONTINUOUS_EN (0x00010000Lu) +#define ADC_SAR_Seq_DSI_TRIGGER_EN (0x00020000Lu) +#define ADC_SAR_Seq_DSI_TRIGGER_LEVEL (0x00040000Lu) +#define ADC_SAR_Seq_DSI_SYNC_TRIGGER (0x00080000Lu) +#define ADC_SAR_Seq_EOS_DSI_OUT_EN (0x80000000Lu) + +/* defines for SAMPLE_TIME01 / SAMPLE_TIME23 registers */ +#define ADC_SAR_Seq_SAMPLE_TIME13_OFFSET (16u) +#define ADC_SAR_Seq_SAMPLE_TIME02_MASK (0x000003FFLu) +#define ADC_SAR_Seq_SAMPLE_TIME13_MASK (0x03FF0000Lu) + +/* defines for RANGE_THRES registers */ +#define ADC_SAR_Seq_RANGE_HIGH_OFFSET (16u) +#define ADC_SAR_Seq_RANGE_HIGH_MASK (0xFFFF0000Lu) +#define ADC_SAR_Seq_RANGE_LOW_MASK (0x0000FFFFLu) + +/* defines for RANGE_COND register */ +/* Compare mode setting constants: +* BELOW - Result < Low_Limit +* INSIDE - Low_Limit <= Result < High_Limit +* ABOVE - High_Limit <= Result +* OUTSIDE - (Result < Low_Limit) or (High_Limit <= Result) +*/ +#define ADC_SAR_Seq_CMP_MODE_BELOW (0x00000000Lu) +#define ADC_SAR_Seq_CMP_MODE_INSIDE (0x40000000Lu) +#define ADC_SAR_Seq_CMP_MODE_ABOVE (0x80000000Lu) +#define ADC_SAR_Seq_CMP_MODE_OUTSIDE (0xC0000000Lu) +#define ADC_SAR_Seq_CMP_OFFSET (30u) + +/* defines for _START_CTRL register */ +#define ADC_SAR_Seq_FW_TRIGGER (0x00000001Lu) + +/* defines for DFT_CTRL register */ +#define ADC_SAR_Seq_DLY_INC (0x00000001Lu) +#define ADC_SAR_Seq_HIZ (0x00000002Lu) +#define ADC_SAR_Seq_DFT_INC_MASK (0x000F0000Lu) +#define ADC_SAR_Seq_DFT_OUTC_MASK (0x00700000Lu) +#define ADC_SAR_Seq_SEL_CSEL_DFT_MASK (0x0F000000Lu) + +/* configuration for clock speed > 9 Mhz based on +* characterization results +*/ +#define ADC_SAR_Seq_SEL_CSEL_DFT_CHAR (0x03000000Lu) +#define ADC_SAR_Seq_EN_CSEL_DFT (0x10000000Lu) +#define ADC_SAR_Seq_DCEN (0x20000000Lu) +#define ADC_SAR_Seq_ADFT_OVERRIDE (0x80000000Lu) + +/* defines for CHAN_CONFIG / DIE_CHAN_CONFIG register +* and channelsConfig parameter +*/ +#define ADC_SAR_Seq_SARMUX_VIRT_SELECT (0x00000070Lu) +#define ADC_SAR_Seq_DIFFERENTIAL_EN (0x00000100Lu) +#define ADC_SAR_Seq_ALT_RESOLUTION_ON (0x00000200Lu) +#define ADC_SAR_Seq_AVERAGING_EN (0x00000400Lu) + +#define ADC_SAR_Seq_SAMPLE_TIME_SEL_SHIFT (12u) +#define ADC_SAR_Seq_SAMPLE_TIME_SEL_MASK (0x00003000Lu) + +#define ADC_SAR_Seq_CHANNEL_CONFIG_MASK (0x00003700Lu) + +/* for CHAN_CONFIG only */ +#define ADC_SAR_Seq_DSI_OUT_EN (0x80000000Lu) + +/* for INJ_CHAN_CONFIG only */ +#define ADC_SAR_Seq_INJ_TAILGATING (0x40000000Lu) +#define ADC_SAR_Seq_INJ_CHAN_EN (0x80000000Lu) + +/* defines for CHAN_WORK register */ +#define ADC_SAR_Seq_SAR_WRK_MAX_12BIT (0x00001000Lu) +#define ADC_SAR_Seq_SAR_WRK_MAX_10BIT (0x00000400Lu) +#define ADC_SAR_Seq_SAR_WRK_MAX_8BIT (0x00000100Lu) + +/* defines for CHAN_RESULT register */ +#define ADC_SAR_Seq_RESULT_MASK (0x0000FFFFLu) +#define ADC_SAR_Seq_SATURATE_INTR_MIR (0x20000000Lu) +#define ADC_SAR_Seq_RANGE_INTR_MIR (0x40000000Lu) +#define ADC_SAR_Seq_CHAN_RESULT_VALID_MIR (0x80000000Lu) + +/* defines for INTR_MASK register */ +#define ADC_SAR_Seq_EOS_MASK (0x00000001Lu) +#define ADC_SAR_Seq_OVERFLOW_MASK (0x00000002Lu) +#define ADC_SAR_Seq_FW_COLLISION_MASK (0x00000004Lu) +#define ADC_SAR_Seq_DSI_COLLISION_MASK (0x00000008Lu) +#define ADC_SAR_Seq_INJ_EOC_MASK (0x00000010Lu) +#define ADC_SAR_Seq_INJ_SATURATE_MASK (0x00000020Lu) +#define ADC_SAR_Seq_INJ_RANGE_MASK (0x00000040Lu) +#define ADC_SAR_Seq_INJ_COLLISION_MASK (0x00000080Lu) + +/* defines for INJ_RESULT register */ +#define ADC_SAR_Seq_INJ_COLLISION_INTR_MIR (0x10000000Lu) +#define ADC_SAR_Seq_INJ_SATURATE_INTR_MIR (0x20000000Lu) +#define ADC_SAR_Seq_INJ_RANGE_INTR_MIR (0x40000000Lu) +#define ADC_SAR_Seq_INJ_EOC_INTR_MIR (0x80000000Lu) + +/* defines for MUX_SWITCH0 register */ +#define ADC_SAR_Seq_MUX_FW_VSSA_VMINUS (0x00010000Lu) + +/* defines for PUMP_CTRL register */ +#define ADC_SAR_Seq_PUMP_CTRL_ENABLED (0x80000000Lu) + +/* additional defines for channelsConfig parameter */ +#define ADC_SAR_Seq_IS_SATURATE_EN_MASK (0x00000001Lu) +#define ADC_SAR_Seq_IS_RANGE_CTRL_EN_MASK (0x00000002Lu) + +/* defines for WOUNDING register */ +#define ADC_SAR_Seq_WOUNDING_12BIT (0x00000000Lu) +#define ADC_SAR_Seq_WOUNDING_10BIT (0x00000001Lu) +#define ADC_SAR_Seq_WOUNDING_8BIT (0x00000002Lu) + +/* Trim value based on characterization */ +#define ADC_SAR_Seq_TRIM_COEF (2u) + +#if(ADC_SAR_Seq_MAX_RESOLUTION == ADC_SAR_Seq_RESOLUTION_10) + #define ADC_SAR_Seq_ALT_WOUNDING ADC_SAR_Seq_WOUNDING_10BIT +#else + #define ADC_SAR_Seq_ALT_WOUNDING ADC_SAR_Seq_WOUNDING_8BIT +#endif /* ADC_SAR_Seq_MAX_RESOLUTION == ADC_SAR_Seq_RESOLUTION_10 */ + +#if(ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__VDDA_2) + #define ADC_SAR_Seq_DEFAULT_VREF_SOURCE ADC_SAR_Seq_VREF_VDDA_2 +#elif(ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__VDDA) + #define ADC_SAR_Seq_DEFAULT_VREF_SOURCE ADC_SAR_Seq_VREF_VDDA +#elif(ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__INTERNAL1024) + #define ADC_SAR_Seq_DEFAULT_VREF_SOURCE ADC_SAR_Seq_VREF_INTERNAL1024 +#elif(ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__INTERNAL1024BYPASSED) + #define ADC_SAR_Seq_DEFAULT_VREF_SOURCE ADC_SAR_Seq_VREF_INTERNAL1024BYPASSED +#elif(ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__INTERNALVREF) + #define ADC_SAR_Seq_DEFAULT_VREF_SOURCE ADC_SAR_Seq_VREF_INTERNALVREF +#elif(ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__INTERNALVREFBYPASSED) + #define ADC_SAR_Seq_DEFAULT_VREF_SOURCE ADC_SAR_Seq_VREF_INTERNALVREFBYPASSED +#elif(ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__VDDA_2BYPASSED) + #define ADC_SAR_Seq_DEFAULT_VREF_SOURCE ADC_SAR_Seq_VREF_VDDA_2BYPASSED +#else + #define ADC_SAR_Seq_DEFAULT_VREF_SOURCE ADC_SAR_Seq_VREF_EXTERNAL +#endif /* ADC_SAR_Seq_DEFAULT_VREF_SEL == ADC_SAR_Seq__VDDA_2 */ + +#if(ADC_SAR_Seq_DEFAULT_NEG_INPUT_SEL == ADC_SAR_Seq__VSS) + /* Connect NEG input of SARADC to VSSA close to the SARADC for single channel mode */ + #if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM == 1u) + #define ADC_SAR_Seq_DEFAULT_SE_NEG_INPUT ADC_SAR_Seq_NEG_VSSA + #else + #define ADC_SAR_Seq_DEFAULT_SE_NEG_INPUT ADC_SAR_Seq_NEG_VSSA_KELVIN + #endif /* (ADC_SAR_Seq_TOTAL_CHANNELS_NUM == 1u) */ + /* Do not connect VSSA to VMINUS when one channel in differential mode used */ + #if((ADC_SAR_Seq_TOTAL_CHANNELS_NUM == 1u) && (ADC_SAR_Seq_CHANNELS_MODE != 0u)) + #define ADC_SAR_Seq_DEFAULT_MUX_SWITCH0 0u + #else /* miltiple channels or one single channel */ + #define ADC_SAR_Seq_DEFAULT_MUX_SWITCH0 ADC_SAR_Seq_MUX_FW_VSSA_VMINUS + #endif /* (ADC_SAR_Seq_TOTAL_CHANNELS_NUM == 1u) */ +#elif(ADC_SAR_Seq_DEFAULT_NEG_INPUT_SEL == ADC_SAR_Seq__VREF) + /* Do not connect VNEG to VREF when one channel in differential mode used */ + #if((ADC_SAR_Seq_TOTAL_CHANNELS_NUM == 1u) && (ADC_SAR_Seq_CHANNELS_MODE != 0u)) + #define ADC_SAR_Seq_DEFAULT_SE_NEG_INPUT 0u + #else /* miltiple channels or one single channel */ + #define ADC_SAR_Seq_DEFAULT_SE_NEG_INPUT ADC_SAR_Seq_NEG_VREF + #endif /* (ADC_SAR_Seq_TOTAL_CHANNELS_NUM == 1u) */ + #define ADC_SAR_Seq_DEFAULT_MUX_SWITCH0 0u +#elif (ADC_SAR_Seq_SINGLE_PRESENT != 0u) + #define ADC_SAR_Seq_DEFAULT_SE_NEG_INPUT ADC_SAR_Seq_NEG_OTHER + #define ADC_SAR_Seq_DEFAULT_MUX_SWITCH0 0u +#else + #define ADC_SAR_Seq_DEFAULT_SE_NEG_INPUT 0u + #define ADC_SAR_Seq_DEFAULT_MUX_SWITCH0 0u +#endif /* ADC_SAR_Seq_DEFAULT_NEG_INPUT_SEL == ADC_SAR_Seq__VREF */ + +/* If the SAR is configured for multiple channels, always set SAR_HW_CTRL_NEGVREF to 1 */ +#if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM == 1u) + #define ADC_SAR_Seq_DEFAULT_HW_CTRL_NEGVREF 0u +#else + #define ADC_SAR_Seq_DEFAULT_HW_CTRL_NEGVREF ADC_SAR_Seq_SAR_HW_CTRL_NEGVREF +#endif /* (ADC_SAR_Seq_TOTAL_CHANNELS_NUM == 1u) */ + + +#if(ADC_SAR_Seq_DEFAULT_ALT_RESOLUTION_SEL == ADC_SAR_Seq__RES8) + #define ADC_SAR_Seq_DEFAULT_ALT_RESOLUTION (ADC_SAR_Seq_ALT_RESOLUTION_8BIT) + #define ADC_SAR_Seq_DEFAULT_MAX_WRK_ALT (ADC_SAR_Seq_SAR_WRK_MAX_8BIT) +#else + #define ADC_SAR_Seq_DEFAULT_ALT_RESOLUTION (ADC_SAR_Seq_ALT_RESOLUTION_10BIT) + #define ADC_SAR_Seq_DEFAULT_MAX_WRK_ALT (ADC_SAR_Seq_SAR_WRK_MAX_10BIT) +#endif /* End ADC_SAR_Seq_DEFAULT_ALT_RESOLUTION_SEL == ADC_SAR_Seq__RES8 */ + +#if(ADC_SAR_Seq_DEFAULT_JUSTIFICATION_SEL == ADC_SAR_Seq__RIGHT) + #define ADC_SAR_Seq_DEFAULT_JUSTIFICATION ADC_SAR_Seq_DATA_ALIGN_RIGHT +#else + #define ADC_SAR_Seq_DEFAULT_JUSTIFICATION ADC_SAR_Seq_DATA_ALIGN_LEFT +#endif /* ADC_SAR_Seq_DEFAULT_JUSTIFICATION_SEL == ADC_SAR_Seq__RIGHT */ + +#if(ADC_SAR_Seq_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC_SAR_Seq__FSIGNED) + #define ADC_SAR_Seq_DEFAULT_DIFF_RESULT_FORMAT ADC_SAR_Seq_DIFF_SIGNED_RESULT +#else + #define ADC_SAR_Seq_DEFAULT_DIFF_RESULT_FORMAT ADC_SAR_Seq_DIFF_UNSIGNED_RESULT +#endif /* ADC_SAR_Seq_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC_SAR_Seq__FSIGNED */ + +#if(ADC_SAR_Seq_DEFAULT_SE_RESULT_FORMAT_SEL == ADC_SAR_Seq__FSIGNED) + #define ADC_SAR_Seq_DEFAULT_SE_RESULT_FORMAT ADC_SAR_Seq_SE_SIGNED_RESULT +#else + #define ADC_SAR_Seq_DEFAULT_SE_RESULT_FORMAT ADC_SAR_Seq_SE_UNSIGNED_RESULT +#endif /* ADC_SAR_Seq_DEFAULT_SE_RESULT_FORMAT_SEL == ADC_SAR_Seq__FSIGNED */ + +#if(ADC_SAR_Seq_DEFAULT_SAMPLE_MODE_SEL == ADC_SAR_Seq__FREERUNNING) + #define ADC_SAR_Seq_DSI_TRIGGER 0u +#else /* Firmware trigger */ + #define ADC_SAR_Seq_DSI_TRIGGER (ADC_SAR_Seq_DSI_TRIGGER_EN | ADC_SAR_Seq_DSI_SYNC_TRIGGER) +#endif /* End ADC_SAR_Seq_DEFAULT_SAMPLE_MODE == ADC_SAR_Seq__FREERUNNING */ + +#if(ADC_SAR_Seq_INJ_CHANNEL_ENABLED) + #define ADC_SAR_Seq_SAR_INTR_MASK (ADC_SAR_Seq_EOS_MASK | ADC_SAR_Seq_INJ_EOC_MASK) +#else + #define ADC_SAR_Seq_SAR_INTR_MASK (ADC_SAR_Seq_EOS_MASK) +#endif /* ADC_SAR_Seq_INJ_CHANNEL_ENABLED*/ + +#if(ADC_SAR_Seq_DEFAULT_AVG_MODE == ADC_SAR_Seq__FIXEDRESOLUTION) + #define ADC_SAR_Seq_AVG_SHIFT_MODE ADC_SAR_Seq_AVG_SHIFT +#else + #define ADC_SAR_Seq_AVG_SHIFT_MODE 0u +#endif /* End ADC_SAR_Seq_DEFAULT_AVG_MODE */ + +#define ADC_SAR_Seq_COMPARE_MODE (uint32)((uint32)(ADC_SAR_Seq_DEFAULT_COMPARE_MODE) \ + << ADC_SAR_Seq_CMP_OFFSET) + +#if(ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 1u) + #define ADC_SAR_Seq_DEFAULT_SWITCH_CONF 0u +#else /* Disable SAR sequencer from enabling routing switches in single channel mode */ + #define ADC_SAR_Seq_DEFAULT_SWITCH_CONF ADC_SAR_Seq_SWITCH_DISABLE +#endif /* End ADC_SAR_Seq_TOTAL_CHANNELS_NUM > 1 */ + +#define ADC_SAR_Seq_DEFAULT_POWER \ + ((ADC_SAR_Seq_NOMINAL_CLOCK_FREQ > (ADC_SAR_Seq_MAX_FREQUENCY / 4)) ? ADC_SAR_Seq_NORMAL_PWR : \ + ((ADC_SAR_Seq_NOMINAL_CLOCK_FREQ > (ADC_SAR_Seq_MAX_FREQUENCY / 8)) ? ADC_SAR_Seq_HALF_PWR : \ + ADC_SAR_Seq_QUARTER_PWR)) + +#define ADC_SAR_Seq_DEFAULT_CTRL_REG_CFG (ADC_SAR_Seq_DEFAULT_VREF_SOURCE \ + | ADC_SAR_Seq_DEFAULT_SE_NEG_INPUT \ + | ADC_SAR_Seq_DEFAULT_HW_CTRL_NEGVREF \ + | ADC_SAR_Seq_DEFAULT_POWER \ + | ADC_SAR_Seq_DSI_SYNC_CONFIG \ + | ADC_SAR_Seq_DEFAULT_SWITCH_CONF) + +#define ADC_SAR_Seq_DEFAULT_SAMPLE_CTRL_REG_CFG (ADC_SAR_Seq_DEFAULT_DIFF_RESULT_FORMAT \ + | ADC_SAR_Seq_DEFAULT_SE_RESULT_FORMAT \ + | ADC_SAR_Seq_DEFAULT_JUSTIFICATION \ + | ADC_SAR_Seq_DEFAULT_ALT_RESOLUTION \ + | (uint8)(ADC_SAR_Seq_DEFAULT_AVG_SAMPLES_NUM \ + << ADC_SAR_Seq_AVG_CNT_OFFSET) \ + | ADC_SAR_Seq_AVG_SHIFT_MODE \ + | ADC_SAR_Seq_DSI_TRIGGER \ + | ADC_SAR_Seq_EOS_DSI_OUT_EN) + +#define ADC_SAR_Seq_DEFAULT_RANGE_THRES_REG_CFG (ADC_SAR_Seq_DEFAULT_LOW_LIMIT \ + | (uint32)((uint32)ADC_SAR_Seq_DEFAULT_HIGH_LIMIT << ADC_SAR_Seq_RANGE_HIGH_OFFSET)) + +#define ADC_SAR_Seq_DEFAULT_SAMPLE_TIME01_REG_CFG (ADC_SAR_Seq_DEFAULT_ACLKS_NUM \ + | (uint32)((uint32)ADC_SAR_Seq_DEFAULT_BCLKS_NUM << ADC_SAR_Seq_SAMPLE_TIME13_OFFSET)) + +#define ADC_SAR_Seq_DEFAULT_SAMPLE_TIME23_REG_CFG (ADC_SAR_Seq_DEFAULT_CCLKS_NUM \ + | (uint32)((uint32)ADC_SAR_Seq_DEFAULT_DCLKS_NUM << ADC_SAR_Seq_SAMPLE_TIME13_OFFSET)) + + +#endif /* End CY_ADC_SAR_SEQ_ADC_SAR_Seq_H */ + +#ifdef __cplusplus +} +#endif + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/ADC_SAR_Seq_INT.c b/cores/asr650x/cores/ADC_SAR_Seq_INT.c new file mode 100644 index 00000000..b1e43acf --- /dev/null +++ b/cores/asr650x/cores/ADC_SAR_Seq_INT.c @@ -0,0 +1,78 @@ +/******************************************************************************* +* File Name: ADC_SAR_Seq_INT.c +* Version 2.50 +* +* Description: +* This file contains the code that operates during the ADC_SAR interrupt +* service routine. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ADC_SAR_Seq.h" +#include "cyapicallbacks.h" + + +/****************************************************************************** +* Custom Declarations and Variables +* - add user inlcude files, prototypes and variables between the following +* #START and #END tags +******************************************************************************/ +/* `#START ADC_SYS_VAR` */ + +/* `#END` */ + +#if(ADC_SAR_Seq_IRQ_REMOVE == 0u) + + + /****************************************************************************** + * Function Name: ADC_SAR_Seq_ISR + ******************************************************************************* + * + * Summary: + * Handle Interrupt Service Routine. + * + * Parameters: + * None. + * + * Return: + * None. + * + * Reentrant: + * No. + * + ******************************************************************************/ + CY_ISR( ADC_SAR_Seq_ISR ) + { + uint32 intr_status; + + /* Read interrupt status register */ + intr_status = ADC_SAR_Seq_SAR_INTR_REG; + + #ifdef ADC_SAR_Seq_ISR_INTERRUPT_CALLBACK + ADC_SAR_Seq_ISR_InterruptCallback(); + #endif /* ADC_SAR_Seq_ISR_INTERRUPT_CALLBACK */ + + + /************************************************************************ + * Custom Code + * - add user ISR code between the following #START and #END tags + *************************************************************************/ + /* `#START MAIN_ADC_ISR` */ + + /* `#END` */ + + /* Clear handled interrupt */ + ADC_SAR_Seq_SAR_INTR_REG = intr_status; + } + +#endif /* End ADC_SAR_Seq_IRQ_REMOVE */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/ADC_SAR_Seq_IRQ.c b/cores/asr650x/cores/ADC_SAR_Seq_IRQ.c new file mode 100644 index 00000000..d64dbcb4 --- /dev/null +++ b/cores/asr650x/cores/ADC_SAR_Seq_IRQ.c @@ -0,0 +1,406 @@ +/******************************************************************************* +* File Name: ADC_SAR_Seq_IRQ.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include +#include "cyapicallbacks.h" + +#if !defined(ADC_SAR_Seq_IRQ__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START ADC_SAR_Seq_IRQ_intc` */ + +/* `#END` */ + +extern cyisraddress CyRamVectors[CYINT_IRQ_BASE + CY_NUM_INTERRUPTS]; + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_SAR_Seq_IRQ_Start(void) +{ + /* For all we know the interrupt is active. */ + ADC_SAR_Seq_IRQ_Disable(); + + /* Set the ISR to point to the ADC_SAR_Seq_IRQ Interrupt. */ + ADC_SAR_Seq_IRQ_SetVector(&ADC_SAR_Seq_IRQ_Interrupt); + + /* Set the priority. */ + ADC_SAR_Seq_IRQ_SetPriority((uint8)ADC_SAR_Seq_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + ADC_SAR_Seq_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void ADC_SAR_Seq_IRQ_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + ADC_SAR_Seq_IRQ_Disable(); + + /* Set the ISR to point to the ADC_SAR_Seq_IRQ Interrupt. */ + ADC_SAR_Seq_IRQ_SetVector(address); + + /* Set the priority. */ + ADC_SAR_Seq_IRQ_SetPriority((uint8)ADC_SAR_Seq_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + ADC_SAR_Seq_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_SAR_Seq_IRQ_Stop(void) +{ + /* Disable this interrupt. */ + ADC_SAR_Seq_IRQ_Disable(); + + /* Set the ISR to point to the passive one. */ + ADC_SAR_Seq_IRQ_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for ADC_SAR_Seq_IRQ. +* +* Add custom code between the START and END comments to keep the next version +* of this file from over-writing your code. +* +* Note You may use either the default ISR by using this API, or you may define +* your own separate ISR through ISR_StartEx(). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(ADC_SAR_Seq_IRQ_Interrupt) +{ + #ifdef ADC_SAR_Seq_IRQ_INTERRUPT_INTERRUPT_CALLBACK + ADC_SAR_Seq_IRQ_Interrupt_InterruptCallback(); + #endif /* ADC_SAR_Seq_IRQ_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START ADC_SAR_Seq_IRQ_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling ADC_SAR_Seq_IRQ_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use ADC_SAR_Seq_IRQ_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void ADC_SAR_Seq_IRQ_SetVector(cyisraddress address) +{ + CyRamVectors[CYINT_IRQ_BASE + ADC_SAR_Seq_IRQ__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress ADC_SAR_Seq_IRQ_GetVector(void) +{ + return CyRamVectors[CYINT_IRQ_BASE + ADC_SAR_Seq_IRQ__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling ADC_SAR_Seq_IRQ_Start or ADC_SAR_Seq_IRQ_StartEx will +* override any effect this API would have had. This API should only be called +* after ADC_SAR_Seq_IRQ_Start or ADC_SAR_Seq_IRQ_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void ADC_SAR_Seq_IRQ_SetPriority(uint8 priority) +{ + uint8 interruptState; + uint32 priorityOffset = ((ADC_SAR_Seq_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + interruptState = CyEnterCriticalSection(); + *ADC_SAR_Seq_IRQ_INTC_PRIOR = (*ADC_SAR_Seq_IRQ_INTC_PRIOR & (uint32)(~ADC_SAR_Seq_IRQ__INTC_PRIOR_MASK)) | + ((uint32)priority << priorityOffset); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 ADC_SAR_Seq_IRQ_GetPriority(void) +{ + uint32 priority; + uint32 priorityOffset = ((ADC_SAR_Seq_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + priority = (*ADC_SAR_Seq_IRQ_INTC_PRIOR & ADC_SAR_Seq_IRQ__INTC_PRIOR_MASK) >> priorityOffset; + + return (uint8)priority; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_SAR_Seq_IRQ_Enable(void) +{ + /* Enable the general interrupt. */ + *ADC_SAR_Seq_IRQ_INTC_SET_EN = ADC_SAR_Seq_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 ADC_SAR_Seq_IRQ_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*ADC_SAR_Seq_IRQ_INTC_SET_EN & (uint32)ADC_SAR_Seq_IRQ__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_SAR_Seq_IRQ_Disable(void) +{ + /* Disable the general interrupt. */ + *ADC_SAR_Seq_IRQ_INTC_CLR_EN = ADC_SAR_Seq_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void ADC_SAR_Seq_IRQ_SetPending(void) +{ + *ADC_SAR_Seq_IRQ_INTC_SET_PD = ADC_SAR_Seq_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_IRQ_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void ADC_SAR_Seq_IRQ_ClearPending(void) +{ + *ADC_SAR_Seq_IRQ_INTC_CLR_PD = ADC_SAR_Seq_IRQ__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/ADC_SAR_Seq_IRQ.h b/cores/asr650x/cores/ADC_SAR_Seq_IRQ.h new file mode 100644 index 00000000..5c1f5830 --- /dev/null +++ b/cores/asr650x/cores/ADC_SAR_Seq_IRQ.h @@ -0,0 +1,80 @@ +/******************************************************************************* +* File Name: ADC_SAR_Seq_IRQ.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_ADC_SAR_Seq_IRQ_H) +#define CY_ISR_ADC_SAR_Seq_IRQ_H + + +#include +#include + +#define ADC_SAR_Seq_IRQ__INTC_CLR_EN_REG CYREG_CM0P_ICER +#define ADC_SAR_Seq_IRQ__INTC_CLR_PD_REG CYREG_CM0P_ICPR +#define ADC_SAR_Seq_IRQ__INTC_MASK 0x2000000u +#define ADC_SAR_Seq_IRQ__INTC_NUMBER 25u +#define ADC_SAR_Seq_IRQ__INTC_PRIOR_MASK 0xC000u +#define ADC_SAR_Seq_IRQ__INTC_PRIOR_NUM 3u +#define ADC_SAR_Seq_IRQ__INTC_PRIOR_REG CYREG_CM0P_IPR6 +#define ADC_SAR_Seq_IRQ__INTC_SET_EN_REG CYREG_CM0P_ISER +#define ADC_SAR_Seq_IRQ__INTC_SET_PD_REG CYREG_CM0P_ISPR +/* Interrupt Controller API. */ +void ADC_SAR_Seq_IRQ_Start(void); +void ADC_SAR_Seq_IRQ_StartEx(cyisraddress address); +void ADC_SAR_Seq_IRQ_Stop(void); + +CY_ISR_PROTO(ADC_SAR_Seq_IRQ_Interrupt); + +void ADC_SAR_Seq_IRQ_SetVector(cyisraddress address); +cyisraddress ADC_SAR_Seq_IRQ_GetVector(void); + +void ADC_SAR_Seq_IRQ_SetPriority(uint8 priority); +uint8 ADC_SAR_Seq_IRQ_GetPriority(void); + +void ADC_SAR_Seq_IRQ_Enable(void); +uint8 ADC_SAR_Seq_IRQ_GetState(void); +void ADC_SAR_Seq_IRQ_Disable(void); + +void ADC_SAR_Seq_IRQ_SetPending(void); +void ADC_SAR_Seq_IRQ_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the ADC_SAR_Seq_IRQ ISR. */ +#define ADC_SAR_Seq_IRQ_INTC_VECTOR ((reg32 *) ADC_SAR_Seq_IRQ__INTC_VECT) + +/* Address of the ADC_SAR_Seq_IRQ ISR priority. */ +#define ADC_SAR_Seq_IRQ_INTC_PRIOR ((reg32 *) ADC_SAR_Seq_IRQ__INTC_PRIOR_REG) + +/* Priority of the ADC_SAR_Seq_IRQ interrupt. */ +#define ADC_SAR_Seq_IRQ_INTC_PRIOR_NUMBER ADC_SAR_Seq_IRQ__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable ADC_SAR_Seq_IRQ interrupt. */ +#define ADC_SAR_Seq_IRQ_INTC_SET_EN ((reg32 *) ADC_SAR_Seq_IRQ__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the ADC_SAR_Seq_IRQ interrupt. */ +#define ADC_SAR_Seq_IRQ_INTC_CLR_EN ((reg32 *) ADC_SAR_Seq_IRQ__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the ADC_SAR_Seq_IRQ interrupt state to pending. */ +#define ADC_SAR_Seq_IRQ_INTC_SET_PD ((reg32 *) ADC_SAR_Seq_IRQ__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the ADC_SAR_Seq_IRQ interrupt. */ +#define ADC_SAR_Seq_IRQ_INTC_CLR_PD ((reg32 *) ADC_SAR_Seq_IRQ__INTC_CLR_PD_REG) + + + +#endif /* CY_ISR_ADC_SAR_Seq_IRQ_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/ADC_SAR_Seq_PM.c b/cores/asr650x/cores/ADC_SAR_Seq_PM.c new file mode 100644 index 00000000..4f98e4b6 --- /dev/null +++ b/cores/asr650x/cores/ADC_SAR_Seq_PM.c @@ -0,0 +1,158 @@ +/******************************************************************************* +* File Name: ADC_SAR_Seq_PM.c +* Version 2.50 +* +* Description: +* This file provides Sleep/WakeUp APIs functionality. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ADC_SAR_Seq.h" + + +/*************************************** +* Local data allocation +***************************************/ + +static ADC_SAR_Seq_BACKUP_STRUCT ADC_SAR_Seq_backup = +{ + ADC_SAR_Seq_DISABLED, + 0u +}; + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SAR_Seq_SaveConfig(void) +{ + /* All configuration registers are marked as [reset_all_retention] */ +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void ADC_SAR_Seq_RestoreConfig(void) +{ + /* All configuration registers are marked as [reset_all_retention] */ +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_Sleep +******************************************************************************** +* +* Summary: +* Stops the ADC operation and saves the configuration registers and component +* enable state. Should be called just prior to entering sleep. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* ADC_SAR_Seq_backup - modified. +* +*******************************************************************************/ +void ADC_SAR_Seq_Sleep(void) +{ + /* During deepsleep/ hibernate mode keep SARMUX active, i.e. do not open + * all switches (disconnect), to be used for ADFT + */ + ADC_SAR_Seq_backup.dftRegVal = ADC_SAR_Seq_SAR_DFT_CTRL_REG & (uint32)~ADC_SAR_Seq_ADFT_OVERRIDE; + ADC_SAR_Seq_SAR_DFT_CTRL_REG |= ADC_SAR_Seq_ADFT_OVERRIDE; + if((ADC_SAR_Seq_SAR_CTRL_REG & ADC_SAR_Seq_ENABLE) != 0u) + { + if((ADC_SAR_Seq_SAR_SAMPLE_CTRL_REG & ADC_SAR_Seq_CONTINUOUS_EN) != 0u) + { + ADC_SAR_Seq_backup.enableState = ADC_SAR_Seq_ENABLED | ADC_SAR_Seq_STARTED; + } + else + { + ADC_SAR_Seq_backup.enableState = ADC_SAR_Seq_ENABLED; + } + ADC_SAR_Seq_StopConvert(); + ADC_SAR_Seq_Stop(); + + /* Disable the SAR internal pump before entering the chip low power mode */ + if((ADC_SAR_Seq_SAR_CTRL_REG & ADC_SAR_Seq_BOOSTPUMP_EN) != 0u) + { + ADC_SAR_Seq_SAR_CTRL_REG &= (uint32)~ADC_SAR_Seq_BOOSTPUMP_EN; + ADC_SAR_Seq_backup.enableState |= ADC_SAR_Seq_BOOSTPUMP_ENABLED; + } + } + else + { + ADC_SAR_Seq_backup.enableState = ADC_SAR_Seq_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component enable state and configuration registers. +* This should be called just after awaking from sleep mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* ADC_SAR_Seq_backup - used. +* +*******************************************************************************/ +void ADC_SAR_Seq_Wakeup(void) +{ + ADC_SAR_Seq_SAR_DFT_CTRL_REG = ADC_SAR_Seq_backup.dftRegVal; + if(ADC_SAR_Seq_backup.enableState != ADC_SAR_Seq_DISABLED) + { + /* Enable the SAR internal pump */ + if((ADC_SAR_Seq_backup.enableState & ADC_SAR_Seq_BOOSTPUMP_ENABLED) != 0u) + { + ADC_SAR_Seq_SAR_CTRL_REG |= ADC_SAR_Seq_BOOSTPUMP_EN; + } + ADC_SAR_Seq_Enable(); + if((ADC_SAR_Seq_backup.enableState & ADC_SAR_Seq_STARTED) != 0u) + { + ADC_SAR_Seq_StartConvert(); + } + } +} +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/ADC_SAR_Seq_intClock.c b/cores/asr650x/cores/ADC_SAR_Seq_intClock.c new file mode 100644 index 00000000..389cf8e9 --- /dev/null +++ b/cores/asr650x/cores/ADC_SAR_Seq_intClock.c @@ -0,0 +1,210 @@ +/******************************************************************************* +* File Name: ADC_SAR_Seq_intClock.c +* Version 2.20 +* +* Description: +* Provides system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "ADC_SAR_Seq_intClock.h" + +#if defined CYREG_PERI_DIV_CMD + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_intClock_StartEx +******************************************************************************** +* +* Summary: +* Starts the clock, aligned to the specified running clock. +* +* Parameters: +* alignClkDiv: The divider to which phase alignment is performed when the +* clock is started. +* +* Returns: +* None +* +*******************************************************************************/ +void ADC_SAR_Seq_intClock_StartEx(uint32 alignClkDiv) +{ + /* Make sure any previous start command has finished. */ + while((ADC_SAR_Seq_intClock_CMD_REG & ADC_SAR_Seq_intClock_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and enable. */ + ADC_SAR_Seq_intClock_CMD_REG = + ((uint32)ADC_SAR_Seq_intClock__DIV_ID << ADC_SAR_Seq_intClock_CMD_DIV_SHIFT)| + (alignClkDiv << ADC_SAR_Seq_intClock_CMD_PA_DIV_SHIFT) | + (uint32)ADC_SAR_Seq_intClock_CMD_ENABLE_MASK; +} + +#else + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_intClock_Start +******************************************************************************** +* +* Summary: +* Starts the clock. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ + +void ADC_SAR_Seq_intClock_Start(void) +{ + /* Set the bit to enable the clock. */ + ADC_SAR_Seq_intClock_ENABLE_REG |= ADC_SAR_Seq_intClock__ENABLE_MASK; +} + +#endif /* CYREG_PERI_DIV_CMD */ + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_intClock_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void ADC_SAR_Seq_intClock_Stop(void) +{ +#if defined CYREG_PERI_DIV_CMD + + /* Make sure any previous start command has finished. */ + while((ADC_SAR_Seq_intClock_CMD_REG & ADC_SAR_Seq_intClock_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and disable. */ + ADC_SAR_Seq_intClock_CMD_REG = + ((uint32)ADC_SAR_Seq_intClock__DIV_ID << ADC_SAR_Seq_intClock_CMD_DIV_SHIFT)| + ((uint32)ADC_SAR_Seq_intClock_CMD_DISABLE_MASK); + +#else + + /* Clear the bit to disable the clock. */ + ADC_SAR_Seq_intClock_ENABLE_REG &= (uint32)(~ADC_SAR_Seq_intClock__ENABLE_MASK); + +#endif /* CYREG_PERI_DIV_CMD */ +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_intClock_SetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and the fractional divider. +* +* Parameters: +* clkDivider: Divider register value (0-65535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* fracDivider: Fractional Divider register value (0-31). +* Returns: +* None +* +*******************************************************************************/ +void ADC_SAR_Seq_intClock_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional) +{ + uint32 maskVal; + uint32 regVal; + +#if defined (ADC_SAR_Seq_intClock__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD) + + /* get all but divider bits */ + maskVal = ADC_SAR_Seq_intClock_DIV_REG & + (uint32)(~(uint32)(ADC_SAR_Seq_intClock_DIV_INT_MASK | ADC_SAR_Seq_intClock_DIV_FRAC_MASK)); + /* combine mask and new divider vals into 32-bit value */ + regVal = maskVal | + ((uint32)((uint32)clkDivider << ADC_SAR_Seq_intClock_DIV_INT_SHIFT) & ADC_SAR_Seq_intClock_DIV_INT_MASK) | + ((uint32)((uint32)clkFractional << ADC_SAR_Seq_intClock_DIV_FRAC_SHIFT) & ADC_SAR_Seq_intClock_DIV_FRAC_MASK); + +#else + /* get all but integer divider bits */ + maskVal = ADC_SAR_Seq_intClock_DIV_REG & (uint32)(~(uint32)ADC_SAR_Seq_intClock__DIVIDER_MASK); + /* combine mask and new divider val into 32-bit value */ + regVal = clkDivider | maskVal; + +#endif /* ADC_SAR_Seq_intClock__FRAC_MASK || CYREG_PERI_DIV_CMD */ + + ADC_SAR_Seq_intClock_DIV_REG = regVal; +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_intClock_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 ADC_SAR_Seq_intClock_GetDividerRegister(void) +{ + return (uint16)((ADC_SAR_Seq_intClock_DIV_REG & ADC_SAR_Seq_intClock_DIV_INT_MASK) + >> ADC_SAR_Seq_intClock_DIV_INT_SHIFT); +} + + +/******************************************************************************* +* Function Name: ADC_SAR_Seq_intClock_GetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock fractional divider register value. +* +* Parameters: +* None +* +* Returns: +* Fractional Divide value of the clock +* 0 if the fractional divider is not in use. +* +*******************************************************************************/ +uint8 ADC_SAR_Seq_intClock_GetFractionalDividerRegister(void) +{ +#if defined (ADC_SAR_Seq_intClock__FRAC_MASK) + /* return fractional divider bits */ + return (uint8)((ADC_SAR_Seq_intClock_DIV_REG & ADC_SAR_Seq_intClock_DIV_FRAC_MASK) + >> ADC_SAR_Seq_intClock_DIV_FRAC_SHIFT); +#else + return 0u; +#endif /* ADC_SAR_Seq_intClock__FRAC_MASK */ +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/ADC_SAR_Seq_intClock.h b/cores/asr650x/cores/ADC_SAR_Seq_intClock.h new file mode 100644 index 00000000..7d278c1a --- /dev/null +++ b/cores/asr650x/cores/ADC_SAR_Seq_intClock.h @@ -0,0 +1,94 @@ +/******************************************************************************* +* File Name: ADC_SAR_Seq_intClock.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_ADC_SAR_Seq_intClock_H) +#define CY_CLOCK_ADC_SAR_Seq_intClock_H + +#include +#include + +#define ADC_SAR_Seq_intClock__CTRL_REGISTER CYREG_PERI_PCLK_CTL18 +#define ADC_SAR_Seq_intClock__DIV_ID 0x00000045u +#define ADC_SAR_Seq_intClock__DIV_REGISTER CYREG_PERI_DIV_16_CTL5 +#define ADC_SAR_Seq_intClock__PA_DIV_ID 0x000000FFu +/*************************************** +* Function Prototypes +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +void ADC_SAR_Seq_intClock_StartEx(uint32 alignClkDiv); +#define ADC_SAR_Seq_intClock_Start() \ + ADC_SAR_Seq_intClock_StartEx(ADC_SAR_Seq_intClock__PA_DIV_ID) + +#else + +void ADC_SAR_Seq_intClock_Start(void); + +#endif/* CYREG_PERI_DIV_CMD */ + +void ADC_SAR_Seq_intClock_Stop(void); + +void ADC_SAR_Seq_intClock_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional); + +uint16 ADC_SAR_Seq_intClock_GetDividerRegister(void); +uint8 ADC_SAR_Seq_intClock_GetFractionalDividerRegister(void); + +#define ADC_SAR_Seq_intClock_Enable() ADC_SAR_Seq_intClock_Start() +#define ADC_SAR_Seq_intClock_Disable() ADC_SAR_Seq_intClock_Stop() +#define ADC_SAR_Seq_intClock_SetDividerRegister(clkDivider, reset) \ + ADC_SAR_Seq_intClock_SetFractionalDividerRegister((clkDivider), 0u) +#define ADC_SAR_Seq_intClock_SetDivider(clkDivider) ADC_SAR_Seq_intClock_SetDividerRegister((clkDivider), 1u) +#define ADC_SAR_Seq_intClock_SetDividerValue(clkDivider) ADC_SAR_Seq_intClock_SetDividerRegister((clkDivider) - 1u, 1u) + + +/*************************************** +* Registers +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +#define ADC_SAR_Seq_intClock_DIV_ID ADC_SAR_Seq_intClock__DIV_ID + +#define ADC_SAR_Seq_intClock_CMD_REG (*(reg32 *)CYREG_PERI_DIV_CMD) +#define ADC_SAR_Seq_intClock_CTRL_REG (*(reg32 *)ADC_SAR_Seq_intClock__CTRL_REGISTER) +#define ADC_SAR_Seq_intClock_DIV_REG (*(reg32 *)ADC_SAR_Seq_intClock__DIV_REGISTER) + +#define ADC_SAR_Seq_intClock_CMD_DIV_SHIFT (0u) +#define ADC_SAR_Seq_intClock_CMD_PA_DIV_SHIFT (8u) +#define ADC_SAR_Seq_intClock_CMD_DISABLE_SHIFT (30u) +#define ADC_SAR_Seq_intClock_CMD_ENABLE_SHIFT (31u) + +#define ADC_SAR_Seq_intClock_CMD_DISABLE_MASK ((uint32)((uint32)1u << ADC_SAR_Seq_intClock_CMD_DISABLE_SHIFT)) +#define ADC_SAR_Seq_intClock_CMD_ENABLE_MASK ((uint32)((uint32)1u << ADC_SAR_Seq_intClock_CMD_ENABLE_SHIFT)) + +#define ADC_SAR_Seq_intClock_DIV_FRAC_MASK (0x000000F8u) +#define ADC_SAR_Seq_intClock_DIV_FRAC_SHIFT (3u) +#define ADC_SAR_Seq_intClock_DIV_INT_MASK (0xFFFFFF00u) +#define ADC_SAR_Seq_intClock_DIV_INT_SHIFT (8u) + +#else + +#define ADC_SAR_Seq_intClock_DIV_REG (*(reg32 *)ADC_SAR_Seq_intClock__REGISTER) +#define ADC_SAR_Seq_intClock_ENABLE_REG ADC_SAR_Seq_intClock_DIV_REG +#define ADC_SAR_Seq_intClock_DIV_FRAC_MASK ADC_SAR_Seq_intClock__FRAC_MASK +#define ADC_SAR_Seq_intClock_DIV_FRAC_SHIFT (16u) +#define ADC_SAR_Seq_intClock_DIV_INT_MASK ADC_SAR_Seq_intClock__DIVIDER_MASK +#define ADC_SAR_Seq_intClock_DIV_INT_SHIFT (0u) + +#endif/* CYREG_PERI_DIV_CMD */ + +#endif /* !defined(CY_CLOCK_ADC_SAR_Seq_intClock_H) */ + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/ASR_Arduino.h b/cores/asr650x/cores/ASR_Arduino.h new file mode 100644 index 00000000..db70aaba --- /dev/null +++ b/cores/asr650x/cores/ASR_Arduino.h @@ -0,0 +1,114 @@ +#if !defined(__ASR_Arduino__) +#define __ASR_Arduino__ + +#include "cytypes.h" + +#ifdef __cplusplus + extern "C" { +#endif + +#define COLOR_SEND 0x500000 //color red, light 0x10 +#define COLOR_JOINED 0x500050 //color Violet, light 0x10 +#define COLOR_RXWINDOW1 0x000050 //color blue, light 0x10 +#define COLOR_RXWINDOW2 0x505000 //color yellow, light 0x10 +#define COLOR_RECEIVED 0x005000 //color green, light 0x10 + + + +#define UART_RX_LEVEL 1 //the of external uartchip tx PIN when it is powered + +#define PORT_REG_SHFIT 0x100 +#define PIN_NUMBER_IN_PORT 8 +#define MCU_PINS \ + P0_0 = 0, P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, \ + P1_0 , P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, \ + P2_0 , P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, \ + P3_0 , P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, \ + P4_0 , P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, \ + P5_0 , P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, \ + P6_0 , P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, \ + P7_0 , P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7 + +typedef enum +{ + MCU_PINS, + NC = (int)0xFFFFFFFF +}PinNames; + +#define UART_RX P3_0 +#define UART_TX P3_1 +#define Vext P3_2 //gpio6 +#define ADC_CTL P3_3 //gpio7 +#define GPIO0 P0_2 +#define GPIO1 P6_1 +#define GPIO2 P6_2 //can be used in PWM mode +#define GPIO3 P6_4 //can be used in PWM mode +#define GPIO4 P0_7 +#define GPIO5 P0_6 +#define GPIO6 P3_2 +#define GPIO7 P3_3 +#define SDA P0_1 +#define SCL P0_0 +#define ADC P2_3 +#define PWM1 P6_2 //gpio2 +#define PWM2 P6_4 //gpio3 +#define RGB P0_7 //gpio4 + +typedef enum +{ + ANALOG = 0, /**< \brief High Impedance Analog */ + INPUT, /**< \brief High Impedance Digital */ + OUTPUT_PULLUP , /**< \brief Resistive Pull Up */ + OUTPUT_PULLDOWN , /**< \brief Resistive Pull Down */ + OD_LO , /**< \brief Open Drain, Drives Low */ + OD_HI , /**< \brief Open Drain, Drives High */ + OUTPUT , /**< \brief Strong Drive */ + OUTPUT_PULLUP_PULLDOWN , /**< \brief Resistive Pull Up/Down */ +}PINMODE; + + +typedef enum +{ + LOW = 0, + HIGH , +}PINLEVEL; + +typedef enum +{ + NONE, + RISING, + FALLING, + BOTH, +}IrqModes; + +#define DRIVE_MODE_BITS (3) +#define DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - DRIVE_MODE_BITS)) + + +typedef void( *GpioIrqHandler )( void ); +extern GpioIrqHandler GpioIrqHandlerCallback[P7_7]; + +void globalGpioIsrEntry (void); +void pinMode(uint8_t pin_name,PINMODE mode); +void digitalWrite(uint8_t pin_name,PINLEVEL level); +uint8 digitalRead(uint8_t pin_name); +uint8 digitalReadOutPut(uint8_t pin_name); +void pinToggle(uint8_t pin_name); +void ClearPinInterrupt(uint8_t pin_name); +void attachInterrupt(uint8_t pin_name, GpioIrqHandler GpioIrqHandlerCallback, IrqModes interrupt_mode); +void detachInterrupt(uint8_t pin_name); +int16 analogRead (uint8_t pin);//the value returned is in mV units, max value can be read is 3300 mV. +void analogWrite (uint8_t pin, uint8_t value) ; +void delay(uint32_t milliseconds); +void delayMicroseconds(uint16 microseconds); +uint32_t millis(void); + + +#ifdef __cplusplus +} +#endif + +#endif + +/* [] END OF FILE */ + diff --git a/cores/asr650x/cores/AT_Command.h b/cores/asr650x/cores/AT_Command.h new file mode 100644 index 00000000..4974ac89 --- /dev/null +++ b/cores/asr650x/cores/AT_Command.h @@ -0,0 +1,23 @@ +#ifndef __AT_COMMAND_H__ +#define __AT_COMMAND_H__ + +#include "hw.h" +#include "low_power.h" +#include "lorawan_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void Enable_AT(void); +void getDevParam(void); +void printDevParam(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + diff --git a/cores/asr650x/cores/I2C.h b/cores/asr650x/cores/I2C.h new file mode 100644 index 00000000..9a2cc040 --- /dev/null +++ b/cores/asr650x/cores/I2C.h @@ -0,0 +1,2233 @@ +/***************************************************************************//** +* \file I2C.h +* \version 4.0 +* +* \brief +* This file provides constants and parameter values for the SCB Component. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + + +#if !defined(CY_SCB_I2C_H) +#define CY_SCB_I2C_H + +#include +#include +#include +#include + +/* SCB IP block v0 is available in PSoC 4100/PSoC 4200 */ +#define I2C_CY_SCBIP_V0 (CYIPBLOCK_m0s8scb_VERSION == 0u) +/* SCB IP block v1 is available in PSoC 4000 */ +#define I2C_CY_SCBIP_V1 (CYIPBLOCK_m0s8scb_VERSION == 1u) +/* SCB IP block v2 is available in all other devices */ +#define I2C_CY_SCBIP_V2 (CYIPBLOCK_m0s8scb_VERSION >= 2u) + +/** Component version major.minor */ +#define I2C_COMP_VERSION_MAJOR (4) +#define I2C_COMP_VERSION_MINOR (0) + +#define I2C_SCB_MODE (1u) + +/* SCB modes enum */ +#define I2C_SCB_MODE_I2C (0x01u) +#define I2C_SCB_MODE_SPI (0x02u) +#define I2C_SCB_MODE_UART (0x04u) +#define I2C_SCB_MODE_EZI2C (0x08u) +#define I2C_SCB_MODE_UNCONFIG (0xFFu) + +/* Condition compilation depends on operation mode: Unconfigured implies apply to all modes */ +#define I2C_SCB_MODE_I2C_CONST_CFG (I2C_SCB_MODE_I2C == I2C_SCB_MODE) +#define I2C_SCB_MODE_SPI_CONST_CFG (I2C_SCB_MODE_SPI == I2C_SCB_MODE) +#define I2C_SCB_MODE_UART_CONST_CFG (I2C_SCB_MODE_UART == I2C_SCB_MODE) +#define I2C_SCB_MODE_EZI2C_CONST_CFG (I2C_SCB_MODE_EZI2C == I2C_SCB_MODE) +#define I2C_SCB_MODE_UNCONFIG_CONST_CFG (I2C_SCB_MODE_UNCONFIG == I2C_SCB_MODE) + +/* Condition compilation for includes */ +#define I2C_SCB_MODE_I2C_INC (0u !=(I2C_SCB_MODE_I2C & I2C_SCB_MODE)) +#define I2C_SCB_MODE_EZI2C_INC (0u !=(I2C_SCB_MODE_EZI2C & I2C_SCB_MODE)) +#if (!I2C_CY_SCBIP_V1) + #define I2C_SCB_MODE_SPI_INC (0u !=(I2C_SCB_MODE_SPI & I2C_SCB_MODE)) + #define I2C_SCB_MODE_UART_INC (0u !=(I2C_SCB_MODE_UART & I2C_SCB_MODE)) +#else + #define I2C_SCB_MODE_SPI_INC (0u) + #define I2C_SCB_MODE_UART_INC (0u) +#endif /* (!I2C_CY_SCBIP_V1) */ + +/* Interrupts remove options */ +#define I2C_REMOVE_SCB_IRQ (0u) +#define I2C_SCB_IRQ_INTERNAL (0u == I2C_REMOVE_SCB_IRQ) + +#define I2C_REMOVE_UART_RX_WAKEUP_IRQ (1u) +#define I2C_UART_RX_WAKEUP_IRQ (0u == I2C_REMOVE_UART_RX_WAKEUP_IRQ) + +/* SCB interrupt enum */ +#define I2C_SCB_INTR_MODE_NONE (0u) +#define I2C_SCB_INTR_MODE_INTERNAL (1u) +#define I2C_SCB_INTR_MODE_EXTERNAL (2u) + +/* Internal clock remove option */ +#define I2C_REMOVE_SCB_CLK (0u) +#define I2C_SCB_CLK_INTERNAL (0u == I2C_REMOVE_SCB_CLK) + + +/*************************************** +* Includes +****************************************/ + + +#if (I2C_SCB_CLK_INTERNAL) + #include "I2C_SCBCLK.h" +#endif /* (I2C_SCB_CLK_INTERNAL) */ + + +/*************************************** +* Type Definitions +***************************************/ + +typedef struct +{ + uint8 enableState; +} I2C_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ + +/* Start and Stop APIs */ +void I2C_Init(void); +void I2C_Enable(void); +void I2C_Start(void); +void I2C_Stop(void); + +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +/* Sleep and Wakeup APis */ +void I2C_Sleep(void); +void I2C_Wakeup(void); +/** @} power */ + +/** +* \addtogroup group_interrupt +* @{ +*/ +#if (I2C_SCB_IRQ_INTERNAL) + /* Custom interrupt handler */ + void I2C_SetCustomInterruptHandler(void (*func)(void)); +#endif /* (I2C_SCB_IRQ_INTERNAL) */ +/** @} interrupt */ + +/* Interface to internal interrupt component */ +#if (I2C_SCB_IRQ_INTERNAL) + /** + * \addtogroup group_interrupt + * @{ + */ + /******************************************************************************* + * Function Name: I2C_EnableInt + ****************************************************************************//** + * + * When using an Internal interrupt, this enables the interrupt in the NVIC. + * When using an external interrupt the API for the interrupt component must + * be used to enable the interrupt. + * + *******************************************************************************/ + #define I2C_EnableInt() CyIntEnable(I2C_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: I2C_DisableInt + ****************************************************************************//** + * + * When using an Internal interrupt, this disables the interrupt in the NVIC. + * When using an external interrupt the API for the interrupt component must + * be used to disable the interrupt. + * + *******************************************************************************/ + #define I2C_DisableInt() CyIntDisable(I2C_ISR_NUMBER) + /** @} interrupt */ + + /******************************************************************************* + * Function Name: I2C_ClearPendingInt + ****************************************************************************//** + * + * This function clears the interrupt pending status in the NVIC. + * + *******************************************************************************/ + #define I2C_ClearPendingInt() CyIntClearPending(I2C_ISR_NUMBER) +#endif /* (I2C_SCB_IRQ_INTERNAL) */ + +#if (I2C_UART_RX_WAKEUP_IRQ) + /******************************************************************************* + * Function Name: I2C_RxWakeEnableInt + ****************************************************************************//** + * + * This function enables the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define I2C_RxWakeEnableInt() CyIntEnable(I2C_RX_WAKE_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: I2C_RxWakeDisableInt + ****************************************************************************//** + * + * This function disables the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define I2C_RxWakeDisableInt() CyIntDisable(I2C_RX_WAKE_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: I2C_RxWakeClearPendingInt + ****************************************************************************//** + * + * This function clears the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define I2C_RxWakeClearPendingInt() CyIntClearPending(I2C_RX_WAKE_ISR_NUMBER) +#endif /* (I2C_UART_RX_WAKEUP_IRQ) */ + +/** +* \addtogroup group_interrupt +* @{ +*/ +/* Get interrupt cause */ +/******************************************************************************* +* Function Name: I2C_GetInterruptCause +****************************************************************************//** +* +* Returns a mask of bits showing the source of the current triggered interrupt. +* This is useful for modes of operation where an interrupt can be generated by +* conditions in multiple interrupt source registers. +* +* \return +* Mask with the OR of the following conditions that have been triggered. +* - I2C_INTR_CAUSE_MASTER - Interrupt from Master +* - I2C_INTR_CAUSE_SLAVE - Interrupt from Slave +* - I2C_INTR_CAUSE_TX - Interrupt from TX +* - I2C_INTR_CAUSE_RX - Interrupt from RX +* +*******************************************************************************/ +#define I2C_GetInterruptCause() (I2C_INTR_CAUSE_REG) + + +/* APIs to service INTR_RX register */ +/******************************************************************************* +* Function Name: I2C_GetRxInterruptSource +****************************************************************************//** +* +* Returns RX interrupt request register. This register contains current status +* of RX interrupt sources. +* +* \return +* Current status of RX interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - I2C_INTR_RX_FIFO_LEVEL - The number of data elements in the + RX FIFO is greater than the value of RX FIFO level. +* - I2C_INTR_RX_NOT_EMPTY - Receiver FIFO is not empty. +* - I2C_INTR_RX_FULL - Receiver FIFO is full. +* - I2C_INTR_RX_OVERFLOW - Attempt to write to a full +* receiver FIFO. +* - I2C_INTR_RX_UNDERFLOW - Attempt to read from an empty +* receiver FIFO. +* - I2C_INTR_RX_FRAME_ERROR - UART framing error detected. +* - I2C_INTR_RX_PARITY_ERROR - UART parity error detected. +* +*******************************************************************************/ +#define I2C_GetRxInterruptSource() (I2C_INTR_RX_REG) + + +/******************************************************************************* +* Function Name: I2C_SetRxInterruptMode +****************************************************************************//** +* +* Writes RX interrupt mask register. This register configures which bits from +* RX interrupt request register will trigger an interrupt event. +* +* \param interruptMask: RX interrupt sources to be enabled (refer to +* I2C_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define I2C_SetRxInterruptMode(interruptMask) I2C_WRITE_INTR_RX_MASK(interruptMask) + + +/******************************************************************************* +* Function Name: I2C_GetRxInterruptMode +****************************************************************************//** +* +* Returns RX interrupt mask register This register specifies which bits from +* RX interrupt request register will trigger an interrupt event. +* +* \return +* RX interrupt sources to be enabled (refer to +* I2C_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define I2C_GetRxInterruptMode() (I2C_INTR_RX_MASK_REG) + + +/******************************************************************************* +* Function Name: I2C_GetRxInterruptSourceMasked +****************************************************************************//** +* +* Returns RX interrupt masked request register. This register contains logical +* AND of corresponding bits from RX interrupt request and mask registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled RX interrupt sources cause interrupt event. +* +* \return +* Current status of enabled RX interrupt sources (refer to +* I2C_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define I2C_GetRxInterruptSourceMasked() (I2C_INTR_RX_MASKED_REG) + + +/******************************************************************************* +* Function Name: I2C_ClearRxInterruptSource +****************************************************************************//** +* +* Clears RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to be cleared (refer to +* I2C_GetRxInterruptSource() function for bit fields values). +* +* \sideeffects +* The side effects are listed in the table below for each +* affected interrupt source. Refer to section RX FIFO interrupt sources for +* detailed description. +* - I2C_INTR_RX_FIFO_LEVEL Interrupt source is not cleared when +* the receiver FIFO has more entries than level. +* - I2C_INTR_RX_NOT_EMPTY Interrupt source is not cleared when +* receiver FIFO is not empty. +* - I2C_INTR_RX_FULL Interrupt source is not cleared when +* receiver FIFO is full. +* +*******************************************************************************/ +#define I2C_ClearRxInterruptSource(interruptMask) I2C_CLEAR_INTR_RX(interruptMask) + + +/******************************************************************************* +* Function Name: I2C_SetRxInterrupt +****************************************************************************//** +* +* Sets RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to set in the RX interrupt request +* register (refer to I2C_GetRxInterruptSource() function for bit +* fields values). +* +*******************************************************************************/ +#define I2C_SetRxInterrupt(interruptMask) I2C_SET_INTR_RX(interruptMask) + +void I2C_SetRxFifoLevel(uint32 level); + + +/* APIs to service INTR_TX register */ +/******************************************************************************* +* Function Name: I2C_GetTxInterruptSource +****************************************************************************//** +* +* Returns TX interrupt request register. This register contains current status +* of TX interrupt sources. +* +* \return +* Current status of TX interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - I2C_INTR_TX_FIFO_LEVEL - The number of data elements in the +* TX FIFO is less than the value of TX FIFO level. +* - I2C_INTR_TX_NOT_FULL - Transmitter FIFO is not full. +* - I2C_INTR_TX_EMPTY - Transmitter FIFO is empty. +* - I2C_INTR_TX_OVERFLOW - Attempt to write to a full +* transmitter FIFO. +* - I2C_INTR_TX_UNDERFLOW - Attempt to read from an empty +* transmitter FIFO. +* - I2C_INTR_TX_UART_NACK - UART received a NACK in SmartCard +* mode. +* - I2C_INTR_TX_UART_DONE - UART transfer is complete. +* All data elements from the TX FIFO are sent. +* - I2C_INTR_TX_UART_ARB_LOST - Value on the TX line of the UART +* does not match the value on the RX line. +* +*******************************************************************************/ +#define I2C_GetTxInterruptSource() (I2C_INTR_TX_REG) + + +/******************************************************************************* +* Function Name: I2C_SetTxInterruptMode +****************************************************************************//** +* +* Writes TX interrupt mask register. This register configures which bits from +* TX interrupt request register will trigger an interrupt event. +* +* \param interruptMask: TX interrupt sources to be enabled (refer to +* I2C_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define I2C_SetTxInterruptMode(interruptMask) I2C_WRITE_INTR_TX_MASK(interruptMask) + + +/******************************************************************************* +* Function Name: I2C_GetTxInterruptMode +****************************************************************************//** +* +* Returns TX interrupt mask register This register specifies which bits from +* TX interrupt request register will trigger an interrupt event. +* +* \return +* Enabled TX interrupt sources (refer to +* I2C_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define I2C_GetTxInterruptMode() (I2C_INTR_TX_MASK_REG) + + +/******************************************************************************* +* Function Name: I2C_GetTxInterruptSourceMasked +****************************************************************************//** +* +* Returns TX interrupt masked request register. This register contains logical +* AND of corresponding bits from TX interrupt request and mask registers. +* This function is intended to be used in the interrupt service routine to identify +* which of enabled TX interrupt sources cause interrupt event. +* +* \return +* Current status of enabled TX interrupt sources (refer to +* I2C_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define I2C_GetTxInterruptSourceMasked() (I2C_INTR_TX_MASKED_REG) + + +/******************************************************************************* +* Function Name: I2C_ClearTxInterruptSource +****************************************************************************//** +* +* Clears TX interrupt sources in the interrupt request register. +* +* \param interruptMask: TX interrupt sources to be cleared (refer to +* I2C_GetTxInterruptSource() function for bit field values). +* +* \sideeffects +* The side effects are listed in the table below for each affected interrupt +* source. Refer to section TX FIFO interrupt sources for detailed description. +* - I2C_INTR_TX_FIFO_LEVEL - Interrupt source is not cleared when +* transmitter FIFO has less entries than level. +* - I2C_INTR_TX_NOT_FULL - Interrupt source is not cleared when +* transmitter FIFO has empty entries. +* - I2C_INTR_TX_EMPTY - Interrupt source is not cleared when +* transmitter FIFO is empty. +* - I2C_INTR_TX_UNDERFLOW - Interrupt source is not cleared when +* transmitter FIFO is empty and I2C mode with clock stretching is selected. +* Put data into the transmitter FIFO before clearing it. This behavior only +* applicable for PSoC 4100/PSoC 4200 devices. +* +*******************************************************************************/ +#define I2C_ClearTxInterruptSource(interruptMask) I2C_CLEAR_INTR_TX(interruptMask) + + +/******************************************************************************* +* Function Name: I2C_SetTxInterrupt +****************************************************************************//** +* +* Sets RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to set in the RX interrupt request +* register (refer to I2C_GetRxInterruptSource() function for bit +* fields values). +* +*******************************************************************************/ +#define I2C_SetTxInterrupt(interruptMask) I2C_SET_INTR_TX(interruptMask) + +void I2C_SetTxFifoLevel(uint32 level); + + +/* APIs to service INTR_MASTER register */ +/******************************************************************************* +* Function Name: I2C_GetMasterInterruptSource +****************************************************************************//** +* +* Returns Master interrupt request register. This register contains current +* status of Master interrupt sources. +* +* \return +* Current status of Master interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - I2C_INTR_MASTER_SPI_DONE - SPI master transfer is complete. +* Refer to Interrupt sources section for detailed description. +* - I2C_INTR_MASTER_I2C_ARB_LOST - I2C master lost arbitration. +* - I2C_INTR_MASTER_I2C_NACK - I2C master received negative +* acknowledgement (NAK). +* - I2C_INTR_MASTER_I2C_ACK - I2C master received acknowledgement. +* - I2C_INTR_MASTER_I2C_STOP - I2C master generated STOP. +* - I2C_INTR_MASTER_I2C_BUS_ERROR - I2C master bus error +* (detection of unexpected START or STOP condition). +* +*******************************************************************************/ +#define I2C_GetMasterInterruptSource() (I2C_INTR_MASTER_REG) + +/******************************************************************************* +* Function Name: I2C_SetMasterInterruptMode +****************************************************************************//** +* +* Writes Master interrupt mask register. This register configures which bits +* from Master interrupt request register will trigger an interrupt event. +* +* \param interruptMask: Master interrupt sources to be enabled (refer to +* I2C_GetMasterInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define I2C_SetMasterInterruptMode(interruptMask) I2C_WRITE_INTR_MASTER_MASK(interruptMask) + +/******************************************************************************* +* Function Name: I2C_GetMasterInterruptMode +****************************************************************************//** +* +* Returns Master interrupt mask register This register specifies which bits +* from Master interrupt request register will trigger an interrupt event. +* +* \return +* Enabled Master interrupt sources (refer to +* I2C_GetMasterInterruptSource() function for return values). +* +*******************************************************************************/ +#define I2C_GetMasterInterruptMode() (I2C_INTR_MASTER_MASK_REG) + +/******************************************************************************* +* Function Name: I2C_GetMasterInterruptSourceMasked +****************************************************************************//** +* +* Returns Master interrupt masked request register. This register contains +* logical AND of corresponding bits from Master interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled Master interrupt sources cause interrupt event. +* +* \return +* Current status of enabled Master interrupt sources (refer to +* I2C_GetMasterInterruptSource() function for return values). +* +*******************************************************************************/ +#define I2C_GetMasterInterruptSourceMasked() (I2C_INTR_MASTER_MASKED_REG) + +/******************************************************************************* +* Function Name: I2C_ClearMasterInterruptSource +****************************************************************************//** +* +* Clears Master interrupt sources in the interrupt request register. +* +* \param interruptMask: Master interrupt sources to be cleared (refer to +* I2C_GetMasterInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define I2C_ClearMasterInterruptSource(interruptMask) I2C_CLEAR_INTR_MASTER(interruptMask) + +/******************************************************************************* +* Function Name: I2C_SetMasterInterrupt +****************************************************************************//** +* +* Sets Master interrupt sources in the interrupt request register. +* +* \param interruptMask: Master interrupt sources to set in the Master interrupt +* request register (refer to I2C_GetMasterInterruptSource() +* function for bit field values). +* +*******************************************************************************/ +#define I2C_SetMasterInterrupt(interruptMask) I2C_SET_INTR_MASTER(interruptMask) + + +/* APIs to service INTR_SLAVE register */ +/******************************************************************************* +* Function Name: I2C_GetSlaveInterruptSource +****************************************************************************//** +* +* Returns Slave interrupt request register. This register contains current +* status of Slave interrupt sources. +* +* \return +* Current status of Slave interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - I2C_INTR_SLAVE_I2C_ARB_LOST - I2C slave lost arbitration: +* the value driven on the SDA line is not the same as the value observed +* on the SDA line. +* - I2C_INTR_SLAVE_I2C_NACK - I2C slave received negative +* acknowledgement (NAK). +* - I2C_INTR_SLAVE_I2C_ACK - I2C slave received +* acknowledgement (ACK). +* - I2C_INTR_SLAVE_I2C_WRITE_STOP - Stop or Repeated Start +* event for write transfer intended for this slave (address matching +* is performed). +* - I2C_INTR_SLAVE_I2C_STOP - Stop or Repeated Start event +* for (read or write) transfer intended for this slave (address matching +* is performed). +* - I2C_INTR_SLAVE_I2C_START - I2C slave received Start +* condition. +* - I2C_INTR_SLAVE_I2C_ADDR_MATCH - I2C slave received matching +* address. +* - I2C_INTR_SLAVE_I2C_GENERAL - I2C Slave received general +* call address. +* - I2C_INTR_SLAVE_I2C_BUS_ERROR - I2C slave bus error (detection +* of unexpected Start or Stop condition). +* - I2C_INTR_SLAVE_SPI_BUS_ERROR - SPI slave select line is +* deselected at an expected time while the SPI transfer. +* +*******************************************************************************/ +#define I2C_GetSlaveInterruptSource() (I2C_INTR_SLAVE_REG) + +/******************************************************************************* +* Function Name: I2C_SetSlaveInterruptMode +****************************************************************************//** +* +* Writes Slave interrupt mask register. +* This register configures which bits from Slave interrupt request register +* will trigger an interrupt event. +* +* \param interruptMask: Slave interrupt sources to be enabled (refer to +* I2C_GetSlaveInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define I2C_SetSlaveInterruptMode(interruptMask) I2C_WRITE_INTR_SLAVE_MASK(interruptMask) + +/******************************************************************************* +* Function Name: I2C_GetSlaveInterruptMode +****************************************************************************//** +* +* Returns Slave interrupt mask register. +* This register specifies which bits from Slave interrupt request register +* will trigger an interrupt event. +* +* \return +* Enabled Slave interrupt sources(refer to +* I2C_GetSlaveInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define I2C_GetSlaveInterruptMode() (I2C_INTR_SLAVE_MASK_REG) + +/******************************************************************************* +* Function Name: I2C_GetSlaveInterruptSourceMasked +****************************************************************************//** +* +* Returns Slave interrupt masked request register. This register contains +* logical AND of corresponding bits from Slave interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled Slave interrupt sources cause interrupt event. +* +* \return +* Current status of enabled Slave interrupt sources (refer to +* I2C_GetSlaveInterruptSource() function for return values). +* +*******************************************************************************/ +#define I2C_GetSlaveInterruptSourceMasked() (I2C_INTR_SLAVE_MASKED_REG) + +/******************************************************************************* +* Function Name: I2C_ClearSlaveInterruptSource +****************************************************************************//** +* +* Clears Slave interrupt sources in the interrupt request register. +* +* \param interruptMask: Slave interrupt sources to be cleared (refer to +* I2C_GetSlaveInterruptSource() function for return values). +* +*******************************************************************************/ +#define I2C_ClearSlaveInterruptSource(interruptMask) I2C_CLEAR_INTR_SLAVE(interruptMask) + +/******************************************************************************* +* Function Name: I2C_SetSlaveInterrupt +****************************************************************************//** +* +* Sets Slave interrupt sources in the interrupt request register. +* +* \param interruptMask: Slave interrupt sources to set in the Slave interrupt +* request register (refer to I2C_GetSlaveInterruptSource() +* function for return values). +* +*******************************************************************************/ +#define I2C_SetSlaveInterrupt(interruptMask) I2C_SET_INTR_SLAVE(interruptMask) + +/** @} interrupt */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +/** +* \addtogroup group_globals +* @{ +*/ + +/** I2C_initVar indicates whether the I2C +* component has been initialized. The variable is initialized to 0 +* and set to 1 the first time SCB_Start() is called. This allows +* the component to restart without reinitialization after the first +* call to the I2C_Start() routine. +* +* If re-initialization of the component is required, then the +* I2C_Init() function can be called before the +* I2C_Start() or I2C_Enable() function. +*/ +extern uint8 I2C_initVar; +/** @} globals */ + +/*************************************** +* Registers +***************************************/ + +#define I2C_SCB__CTRL CYREG_SCB2_CTRL +#define I2C_SCB__EZ_DATA0 CYREG_SCB2_EZ_DATA0 +#define I2C_SCB__EZ_DATA1 CYREG_SCB2_EZ_DATA1 +#define I2C_SCB__EZ_DATA10 CYREG_SCB2_EZ_DATA10 +#define I2C_SCB__EZ_DATA11 CYREG_SCB2_EZ_DATA11 +#define I2C_SCB__EZ_DATA12 CYREG_SCB2_EZ_DATA12 +#define I2C_SCB__EZ_DATA13 CYREG_SCB2_EZ_DATA13 +#define I2C_SCB__EZ_DATA14 CYREG_SCB2_EZ_DATA14 +#define I2C_SCB__EZ_DATA15 CYREG_SCB2_EZ_DATA15 +#define I2C_SCB__EZ_DATA16 CYREG_SCB2_EZ_DATA16 +#define I2C_SCB__EZ_DATA17 CYREG_SCB2_EZ_DATA17 +#define I2C_SCB__EZ_DATA18 CYREG_SCB2_EZ_DATA18 +#define I2C_SCB__EZ_DATA19 CYREG_SCB2_EZ_DATA19 +#define I2C_SCB__EZ_DATA2 CYREG_SCB2_EZ_DATA2 +#define I2C_SCB__EZ_DATA20 CYREG_SCB2_EZ_DATA20 +#define I2C_SCB__EZ_DATA21 CYREG_SCB2_EZ_DATA21 +#define I2C_SCB__EZ_DATA22 CYREG_SCB2_EZ_DATA22 +#define I2C_SCB__EZ_DATA23 CYREG_SCB2_EZ_DATA23 +#define I2C_SCB__EZ_DATA24 CYREG_SCB2_EZ_DATA24 +#define I2C_SCB__EZ_DATA25 CYREG_SCB2_EZ_DATA25 +#define I2C_SCB__EZ_DATA26 CYREG_SCB2_EZ_DATA26 +#define I2C_SCB__EZ_DATA27 CYREG_SCB2_EZ_DATA27 +#define I2C_SCB__EZ_DATA28 CYREG_SCB2_EZ_DATA28 +#define I2C_SCB__EZ_DATA29 CYREG_SCB2_EZ_DATA29 +#define I2C_SCB__EZ_DATA3 CYREG_SCB2_EZ_DATA3 +#define I2C_SCB__EZ_DATA30 CYREG_SCB2_EZ_DATA30 +#define I2C_SCB__EZ_DATA31 CYREG_SCB2_EZ_DATA31 +#define I2C_SCB__EZ_DATA4 CYREG_SCB2_EZ_DATA4 +#define I2C_SCB__EZ_DATA5 CYREG_SCB2_EZ_DATA5 +#define I2C_SCB__EZ_DATA6 CYREG_SCB2_EZ_DATA6 +#define I2C_SCB__EZ_DATA7 CYREG_SCB2_EZ_DATA7 +#define I2C_SCB__EZ_DATA8 CYREG_SCB2_EZ_DATA8 +#define I2C_SCB__EZ_DATA9 CYREG_SCB2_EZ_DATA9 +#define I2C_SCB__I2C_CFG CYREG_SCB2_I2C_CFG +#define I2C_SCB__I2C_CTRL CYREG_SCB2_I2C_CTRL +#define I2C_SCB__I2C_M_CMD CYREG_SCB2_I2C_M_CMD +#define I2C_SCB__I2C_S_CMD CYREG_SCB2_I2C_S_CMD +#define I2C_SCB__I2C_STATUS CYREG_SCB2_I2C_STATUS +#define I2C_SCB__INTR_CAUSE CYREG_SCB2_INTR_CAUSE +#define I2C_SCB__INTR_I2C_EC CYREG_SCB2_INTR_I2C_EC +#define I2C_SCB__INTR_I2C_EC_MASK CYREG_SCB2_INTR_I2C_EC_MASK +#define I2C_SCB__INTR_I2C_EC_MASKED CYREG_SCB2_INTR_I2C_EC_MASKED +#define I2C_SCB__INTR_M CYREG_SCB2_INTR_M +#define I2C_SCB__INTR_M_MASK CYREG_SCB2_INTR_M_MASK +#define I2C_SCB__INTR_M_MASKED CYREG_SCB2_INTR_M_MASKED +#define I2C_SCB__INTR_M_SET CYREG_SCB2_INTR_M_SET +#define I2C_SCB__INTR_RX CYREG_SCB2_INTR_RX +#define I2C_SCB__INTR_RX_MASK CYREG_SCB2_INTR_RX_MASK +#define I2C_SCB__INTR_RX_MASKED CYREG_SCB2_INTR_RX_MASKED +#define I2C_SCB__INTR_RX_SET CYREG_SCB2_INTR_RX_SET +#define I2C_SCB__INTR_S CYREG_SCB2_INTR_S +#define I2C_SCB__INTR_S_MASK CYREG_SCB2_INTR_S_MASK +#define I2C_SCB__INTR_S_MASKED CYREG_SCB2_INTR_S_MASKED +#define I2C_SCB__INTR_S_SET CYREG_SCB2_INTR_S_SET +#define I2C_SCB__INTR_SPI_EC CYREG_SCB2_INTR_SPI_EC +#define I2C_SCB__INTR_SPI_EC_MASK CYREG_SCB2_INTR_SPI_EC_MASK +#define I2C_SCB__INTR_SPI_EC_MASKED CYREG_SCB2_INTR_SPI_EC_MASKED +#define I2C_SCB__INTR_TX CYREG_SCB2_INTR_TX +#define I2C_SCB__INTR_TX_MASK CYREG_SCB2_INTR_TX_MASK +#define I2C_SCB__INTR_TX_MASKED CYREG_SCB2_INTR_TX_MASKED +#define I2C_SCB__INTR_TX_SET CYREG_SCB2_INTR_TX_SET +#define I2C_SCB__RX_CTRL CYREG_SCB2_RX_CTRL +#define I2C_SCB__RX_FIFO_CTRL CYREG_SCB2_RX_FIFO_CTRL +#define I2C_SCB__RX_FIFO_RD CYREG_SCB2_RX_FIFO_RD +#define I2C_SCB__RX_FIFO_RD_SILENT CYREG_SCB2_RX_FIFO_RD_SILENT +#define I2C_SCB__RX_FIFO_STATUS CYREG_SCB2_RX_FIFO_STATUS +#define I2C_SCB__RX_MATCH CYREG_SCB2_RX_MATCH +#define I2C_SCB__SPI_CTRL CYREG_SCB2_SPI_CTRL +#define I2C_SCB__SPI_STATUS CYREG_SCB2_SPI_STATUS +#define I2C_SCB__SS0_POSISTION 0u +#define I2C_SCB__SS1_POSISTION 1u +#define I2C_SCB__SS2_POSISTION 2u +#define I2C_SCB__SS3_POSISTION 3u +#define I2C_SCB__STATUS CYREG_SCB2_STATUS +#define I2C_SCB__TX_CTRL CYREG_SCB2_TX_CTRL +#define I2C_SCB__TX_FIFO_CTRL CYREG_SCB2_TX_FIFO_CTRL +#define I2C_SCB__TX_FIFO_STATUS CYREG_SCB2_TX_FIFO_STATUS +#define I2C_SCB__TX_FIFO_WR CYREG_SCB2_TX_FIFO_WR +#define I2C_SCB__UART_CTRL CYREG_SCB2_UART_CTRL +#define I2C_SCB__UART_FLOW_CTRL CYREG_SCB2_UART_FLOW_CTRL +#define I2C_SCB__UART_RX_CTRL CYREG_SCB2_UART_RX_CTRL +#define I2C_SCB__UART_RX_STATUS CYREG_SCB2_UART_RX_STATUS +#define I2C_SCB__UART_TX_CTRL CYREG_SCB2_UART_TX_CTRL +#define I2C_SCB_IRQ__INTC_CLR_EN_REG CYREG_CM0P_ICER +#define I2C_SCB_IRQ__INTC_CLR_PD_REG CYREG_CM0P_ICPR +#define I2C_SCB_IRQ__INTC_MASK 0x200u +#define I2C_SCB_IRQ__INTC_NUMBER 9u +#define I2C_SCB_IRQ__INTC_PRIOR_MASK 0xC000u +#define I2C_SCB_IRQ__INTC_PRIOR_NUM 3u +#define I2C_SCB_IRQ__INTC_PRIOR_REG CYREG_CM0P_IPR2 +#define I2C_SCB_IRQ__INTC_SET_EN_REG CYREG_CM0P_ISER +#define I2C_SCB_IRQ__INTC_SET_PD_REG CYREG_CM0P_ISPR + +/* I2C_SCBCLK */ +#define I2C_SCBCLK__CTRL_REGISTER CYREG_PERI_PCLK_CTL2 +#define I2C_SCBCLK__DIV_ID 0x00000043u +#define I2C_SCBCLK__DIV_REGISTER CYREG_PERI_DIV_16_CTL3 +#define I2C_SCBCLK__PA_DIV_ID 0x000000FFu + + +#define I2C_CTRL_REG (*(reg32 *) I2C_SCB__CTRL) +#define I2C_CTRL_PTR ( (reg32 *) I2C_SCB__CTRL) + +#define I2C_STATUS_REG (*(reg32 *) I2C_SCB__STATUS) +#define I2C_STATUS_PTR ( (reg32 *) I2C_SCB__STATUS) + +#if (!I2C_CY_SCBIP_V1) + #define I2C_SPI_CTRL_REG (*(reg32 *) I2C_SCB__SPI_CTRL) + #define I2C_SPI_CTRL_PTR ( (reg32 *) I2C_SCB__SPI_CTRL) + + #define I2C_SPI_STATUS_REG (*(reg32 *) I2C_SCB__SPI_STATUS) + #define I2C_SPI_STATUS_PTR ( (reg32 *) I2C_SCB__SPI_STATUS) + + #define I2C_UART_CTRL_REG (*(reg32 *) I2C_SCB__UART_CTRL) + #define I2C_UART_CTRL_PTR ( (reg32 *) I2C_SCB__UART_CTRL) + + #define I2C_UART_TX_CTRL_REG (*(reg32 *) I2C_SCB__UART_TX_CTRL) + #define I2C_UART_TX_CTRL_PTR ( (reg32 *) I2C_SCB__UART_TX_CTRL) + + #define I2C_UART_RX_CTRL_REG (*(reg32 *) I2C_SCB__UART_RX_CTRL) + #define I2C_UART_RX_CTRL_PTR ( (reg32 *) I2C_SCB__UART_RX_CTRL) + + #define I2C_UART_RX_STATUS_REG (*(reg32 *) I2C_SCB__UART_RX_STATUS) + #define I2C_UART_RX_STATUS_PTR ( (reg32 *) I2C_SCB__UART_RX_STATUS) +#endif /* (!I2C_CY_SCBIP_V1) */ + +#if !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) + #define I2C_UART_FLOW_CTRL_REG (*(reg32 *) I2C_SCB__UART_FLOW_CTRL) + #define I2C_UART_FLOW_CTRL_PTR ( (reg32 *) I2C_SCB__UART_FLOW_CTRL) +#endif /* !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) */ + +#define I2C_I2C_CTRL_REG (*(reg32 *) I2C_SCB__I2C_CTRL) +#define I2C_I2C_CTRL_PTR ( (reg32 *) I2C_SCB__I2C_CTRL) + +#define I2C_I2C_STATUS_REG (*(reg32 *) I2C_SCB__I2C_STATUS) +#define I2C_I2C_STATUS_PTR ( (reg32 *) I2C_SCB__I2C_STATUS) + +#define I2C_I2C_MASTER_CMD_REG (*(reg32 *) I2C_SCB__I2C_M_CMD) +#define I2C_I2C_MASTER_CMD_PTR ( (reg32 *) I2C_SCB__I2C_M_CMD) + +#define I2C_I2C_SLAVE_CMD_REG (*(reg32 *) I2C_SCB__I2C_S_CMD) +#define I2C_I2C_SLAVE_CMD_PTR ( (reg32 *) I2C_SCB__I2C_S_CMD) + +#define I2C_I2C_CFG_REG (*(reg32 *) I2C_SCB__I2C_CFG) +#define I2C_I2C_CFG_PTR ( (reg32 *) I2C_SCB__I2C_CFG) + +#define I2C_TX_CTRL_REG (*(reg32 *) I2C_SCB__TX_CTRL) +#define I2C_TX_CTRL_PTR ( (reg32 *) I2C_SCB__TX_CTRL) + +#define I2C_TX_FIFO_CTRL_REG (*(reg32 *) I2C_SCB__TX_FIFO_CTRL) +#define I2C_TX_FIFO_CTRL_PTR ( (reg32 *) I2C_SCB__TX_FIFO_CTRL) + +#define I2C_TX_FIFO_STATUS_REG (*(reg32 *) I2C_SCB__TX_FIFO_STATUS) +#define I2C_TX_FIFO_STATUS_PTR ( (reg32 *) I2C_SCB__TX_FIFO_STATUS) + +#define I2C_TX_FIFO_WR_REG (*(reg32 *) I2C_SCB__TX_FIFO_WR) +#define I2C_TX_FIFO_WR_PTR ( (reg32 *) I2C_SCB__TX_FIFO_WR) + +#define I2C_RX_CTRL_REG (*(reg32 *) I2C_SCB__RX_CTRL) +#define I2C_RX_CTRL_PTR ( (reg32 *) I2C_SCB__RX_CTRL) + +#define I2C_RX_FIFO_CTRL_REG (*(reg32 *) I2C_SCB__RX_FIFO_CTRL) +#define I2C_RX_FIFO_CTRL_PTR ( (reg32 *) I2C_SCB__RX_FIFO_CTRL) + +#define I2C_RX_FIFO_STATUS_REG (*(reg32 *) I2C_SCB__RX_FIFO_STATUS) +#define I2C_RX_FIFO_STATUS_PTR ( (reg32 *) I2C_SCB__RX_FIFO_STATUS) + +#define I2C_RX_MATCH_REG (*(reg32 *) I2C_SCB__RX_MATCH) +#define I2C_RX_MATCH_PTR ( (reg32 *) I2C_SCB__RX_MATCH) + +#define I2C_RX_FIFO_RD_REG (*(reg32 *) I2C_SCB__RX_FIFO_RD) +#define I2C_RX_FIFO_RD_PTR ( (reg32 *) I2C_SCB__RX_FIFO_RD) + +#define I2C_RX_FIFO_RD_SILENT_REG (*(reg32 *) I2C_SCB__RX_FIFO_RD_SILENT) +#define I2C_RX_FIFO_RD_SILENT_PTR ( (reg32 *) I2C_SCB__RX_FIFO_RD_SILENT) + +#ifdef I2C_SCB__EZ_DATA0 + #define I2C_EZBUF_DATA0_REG (*(reg32 *) I2C_SCB__EZ_DATA0) + #define I2C_EZBUF_DATA0_PTR ( (reg32 *) I2C_SCB__EZ_DATA0) +#else + #define I2C_EZBUF_DATA0_REG (*(reg32 *) I2C_SCB__EZ_DATA00) + #define I2C_EZBUF_DATA0_PTR ( (reg32 *) I2C_SCB__EZ_DATA00) +#endif /* I2C_SCB__EZ_DATA00 */ + +#define I2C_INTR_CAUSE_REG (*(reg32 *) I2C_SCB__INTR_CAUSE) +#define I2C_INTR_CAUSE_PTR ( (reg32 *) I2C_SCB__INTR_CAUSE) + +#define I2C_INTR_I2C_EC_REG (*(reg32 *) I2C_SCB__INTR_I2C_EC) +#define I2C_INTR_I2C_EC_PTR ( (reg32 *) I2C_SCB__INTR_I2C_EC) + +#define I2C_INTR_I2C_EC_MASK_REG (*(reg32 *) I2C_SCB__INTR_I2C_EC_MASK) +#define I2C_INTR_I2C_EC_MASK_PTR ( (reg32 *) I2C_SCB__INTR_I2C_EC_MASK) + +#define I2C_INTR_I2C_EC_MASKED_REG (*(reg32 *) I2C_SCB__INTR_I2C_EC_MASKED) +#define I2C_INTR_I2C_EC_MASKED_PTR ( (reg32 *) I2C_SCB__INTR_I2C_EC_MASKED) + +#if (!I2C_CY_SCBIP_V1) + #define I2C_INTR_SPI_EC_REG (*(reg32 *) I2C_SCB__INTR_SPI_EC) + #define I2C_INTR_SPI_EC_PTR ( (reg32 *) I2C_SCB__INTR_SPI_EC) + + #define I2C_INTR_SPI_EC_MASK_REG (*(reg32 *) I2C_SCB__INTR_SPI_EC_MASK) + #define I2C_INTR_SPI_EC_MASK_PTR ( (reg32 *) I2C_SCB__INTR_SPI_EC_MASK) + + #define I2C_INTR_SPI_EC_MASKED_REG (*(reg32 *) I2C_SCB__INTR_SPI_EC_MASKED) + #define I2C_INTR_SPI_EC_MASKED_PTR ( (reg32 *) I2C_SCB__INTR_SPI_EC_MASKED) +#endif /* (!I2C_CY_SCBIP_V1) */ + +#define I2C_INTR_MASTER_REG (*(reg32 *) I2C_SCB__INTR_M) +#define I2C_INTR_MASTER_PTR ( (reg32 *) I2C_SCB__INTR_M) + +#define I2C_INTR_MASTER_SET_REG (*(reg32 *) I2C_SCB__INTR_M_SET) +#define I2C_INTR_MASTER_SET_PTR ( (reg32 *) I2C_SCB__INTR_M_SET) + +#define I2C_INTR_MASTER_MASK_REG (*(reg32 *) I2C_SCB__INTR_M_MASK) +#define I2C_INTR_MASTER_MASK_PTR ( (reg32 *) I2C_SCB__INTR_M_MASK) + +#define I2C_INTR_MASTER_MASKED_REG (*(reg32 *) I2C_SCB__INTR_M_MASKED) +#define I2C_INTR_MASTER_MASKED_PTR ( (reg32 *) I2C_SCB__INTR_M_MASKED) + +#define I2C_INTR_SLAVE_REG (*(reg32 *) I2C_SCB__INTR_S) +#define I2C_INTR_SLAVE_PTR ( (reg32 *) I2C_SCB__INTR_S) + +#define I2C_INTR_SLAVE_SET_REG (*(reg32 *) I2C_SCB__INTR_S_SET) +#define I2C_INTR_SLAVE_SET_PTR ( (reg32 *) I2C_SCB__INTR_S_SET) + +#define I2C_INTR_SLAVE_MASK_REG (*(reg32 *) I2C_SCB__INTR_S_MASK) +#define I2C_INTR_SLAVE_MASK_PTR ( (reg32 *) I2C_SCB__INTR_S_MASK) + +#define I2C_INTR_SLAVE_MASKED_REG (*(reg32 *) I2C_SCB__INTR_S_MASKED) +#define I2C_INTR_SLAVE_MASKED_PTR ( (reg32 *) I2C_SCB__INTR_S_MASKED) + +#define I2C_INTR_TX_REG (*(reg32 *) I2C_SCB__INTR_TX) +#define I2C_INTR_TX_PTR ( (reg32 *) I2C_SCB__INTR_TX) + +#define I2C_INTR_TX_SET_REG (*(reg32 *) I2C_SCB__INTR_TX_SET) +#define I2C_INTR_TX_SET_PTR ( (reg32 *) I2C_SCB__INTR_TX_SET) + +#define I2C_INTR_TX_MASK_REG (*(reg32 *) I2C_SCB__INTR_TX_MASK) +#define I2C_INTR_TX_MASK_PTR ( (reg32 *) I2C_SCB__INTR_TX_MASK) + +#define I2C_INTR_TX_MASKED_REG (*(reg32 *) I2C_SCB__INTR_TX_MASKED) +#define I2C_INTR_TX_MASKED_PTR ( (reg32 *) I2C_SCB__INTR_TX_MASKED) + +#define I2C_INTR_RX_REG (*(reg32 *) I2C_SCB__INTR_RX) +#define I2C_INTR_RX_PTR ( (reg32 *) I2C_SCB__INTR_RX) + +#define I2C_INTR_RX_SET_REG (*(reg32 *) I2C_SCB__INTR_RX_SET) +#define I2C_INTR_RX_SET_PTR ( (reg32 *) I2C_SCB__INTR_RX_SET) + +#define I2C_INTR_RX_MASK_REG (*(reg32 *) I2C_SCB__INTR_RX_MASK) +#define I2C_INTR_RX_MASK_PTR ( (reg32 *) I2C_SCB__INTR_RX_MASK) + +#define I2C_INTR_RX_MASKED_REG (*(reg32 *) I2C_SCB__INTR_RX_MASKED) +#define I2C_INTR_RX_MASKED_PTR ( (reg32 *) I2C_SCB__INTR_RX_MASKED) + +/* Defines get from SCB IP parameters. */ +#define I2C_FIFO_SIZE (8u) /* TX or RX FIFO size. */ +#define I2C_EZ_DATA_NR (32u) /* Number of words in EZ memory. */ +#define I2C_ONE_BYTE_WIDTH (8u) /* Number of bits in one byte. */ +#define I2C_FF_DATA_NR_LOG2_MASK (0x0Fu) /* Number of bits to represent a FIFO address. */ +#define I2C_FF_DATA_NR_LOG2_PLUS1_MASK (0x1Fu) /* Number of bits to represent #bytes in FIFO. */ + + +/*************************************** +* Registers Constants +***************************************/ + +#if (I2C_SCB_IRQ_INTERNAL) + #define I2C_ISR_NUMBER ((uint8) I2C_SCB_IRQ__INTC_NUMBER) + #define I2C_ISR_PRIORITY ((uint8) I2C_SCB_IRQ__INTC_PRIOR_NUM) +#endif /* (I2C_SCB_IRQ_INTERNAL) */ + +#if (I2C_UART_RX_WAKEUP_IRQ) + #define I2C_RX_WAKE_ISR_NUMBER ((uint8) I2C_RX_WAKEUP_IRQ__INTC_NUMBER) + #define I2C_RX_WAKE_ISR_PRIORITY ((uint8) I2C_RX_WAKEUP_IRQ__INTC_PRIOR_NUM) +#endif /* (I2C_UART_RX_WAKEUP_IRQ) */ + +/* I2C_CTRL_REG */ +#define I2C_CTRL_OVS_POS (0u) /* [3:0] Oversampling factor */ +#define I2C_CTRL_EC_AM_MODE_POS (8u) /* [8] Externally clocked address match */ +#define I2C_CTRL_EC_OP_MODE_POS (9u) /* [9] Externally clocked operation mode */ +#define I2C_CTRL_EZBUF_MODE_POS (10u) /* [10] EZ buffer is enabled */ +#if !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) + #define I2C_CTRL_BYTE_MODE_POS (11u) /* [11] Determines the number of bits per FIFO data element */ +#endif /* !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) */ +#define I2C_CTRL_ADDR_ACCEPT_POS (16u) /* [16] Put matched address in RX FIFO */ +#define I2C_CTRL_BLOCK_POS (17u) /* [17] Ext and Int logic to resolve collide */ +#define I2C_CTRL_MODE_POS (24u) /* [25:24] Operation mode */ +#define I2C_CTRL_ENABLED_POS (31u) /* [31] Enable SCB block */ +#define I2C_CTRL_OVS_MASK ((uint32) 0x0Fu) +#define I2C_CTRL_EC_AM_MODE ((uint32) 0x01u << I2C_CTRL_EC_AM_MODE_POS) +#define I2C_CTRL_EC_OP_MODE ((uint32) 0x01u << I2C_CTRL_EC_OP_MODE_POS) +#define I2C_CTRL_EZBUF_MODE ((uint32) 0x01u << I2C_CTRL_EZBUF_MODE_POS) +#if !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) + #define I2C_CTRL_BYTE_MODE ((uint32) 0x01u << I2C_CTRL_BYTE_MODE_POS) +#endif /* !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) */ +#define I2C_CTRL_ADDR_ACCEPT ((uint32) 0x01u << I2C_CTRL_ADDR_ACCEPT_POS) +#define I2C_CTRL_BLOCK ((uint32) 0x01u << I2C_CTRL_BLOCK_POS) +#define I2C_CTRL_MODE_MASK ((uint32) 0x03u << I2C_CTRL_MODE_POS) +#define I2C_CTRL_MODE_I2C ((uint32) 0x00u) +#define I2C_CTRL_MODE_SPI ((uint32) 0x01u << I2C_CTRL_MODE_POS) +#define I2C_CTRL_MODE_UART ((uint32) 0x02u << I2C_CTRL_MODE_POS) +#define I2C_CTRL_ENABLED ((uint32) 0x01u << I2C_CTRL_ENABLED_POS) + +/* I2C_STATUS_REG */ +#define I2C_STATUS_EC_BUSY_POS (0u) /* [0] Bus busy. Externally clocked logic access to EZ memory */ +#define I2C_STATUS_EC_BUSY ((uint32) 0x0Fu) + +/* I2C_SPI_CTRL_REG */ +#define I2C_SPI_CTRL_CONTINUOUS_POS (0u) /* [0] Continuous or Separated SPI data transfers */ +#define I2C_SPI_CTRL_SELECT_PRECEDE_POS (1u) /* [1] Precedes or coincides start of data frame */ +#define I2C_SPI_CTRL_CPHA_POS (2u) /* [2] SCLK phase */ +#define I2C_SPI_CTRL_CPOL_POS (3u) /* [3] SCLK polarity */ +#define I2C_SPI_CTRL_LATE_MISO_SAMPLE_POS (4u) /* [4] Late MISO sample enabled */ +#if !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) + #define I2C_SPI_CTRL_SCLK_CONTINUOUS_POS (5u) /* [5] Enable continuous SCLK generation */ + #define I2C_SPI_CTRL_SSEL0_POLARITY_POS (8u) /* [8] SS0 polarity */ + #define I2C_SPI_CTRL_SSEL1_POLARITY_POS (9u) /* [9] SS1 polarity */ + #define I2C_SPI_CTRL_SSEL2_POLARITY_POS (10u) /* [10] SS2 polarity */ + #define I2C_SPI_CTRL_SSEL3_POLARITY_POS (11u) /* [11] SS3 polarity */ +#endif /* !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) */ +#define I2C_SPI_CTRL_LOOPBACK_POS (16u) /* [16] Local loop-back control enabled */ +#define I2C_SPI_CTRL_MODE_POS (24u) /* [25:24] Submode of SPI operation */ +#define I2C_SPI_CTRL_SLAVE_SELECT_POS (26u) /* [27:26] Selects SPI SS signal */ +#define I2C_SPI_CTRL_MASTER_MODE_POS (31u) /* [31] Master mode enabled */ +#define I2C_SPI_CTRL_CONTINUOUS ((uint32) 0x01u) +#define I2C_SPI_CTRL_SELECT_PRECEDE ((uint32) 0x01u << I2C_SPI_CTRL_SELECT_PRECEDE_POS) +#define I2C_SPI_CTRL_SCLK_MODE_MASK ((uint32) 0x03u << I2C_SPI_CTRL_CPHA_POS) +#define I2C_SPI_CTRL_CPHA ((uint32) 0x01u << I2C_SPI_CTRL_CPHA_POS) +#define I2C_SPI_CTRL_CPOL ((uint32) 0x01u << I2C_SPI_CTRL_CPOL_POS) +#define I2C_SPI_CTRL_LATE_MISO_SAMPLE ((uint32) 0x01u << \ + I2C_SPI_CTRL_LATE_MISO_SAMPLE_POS) +#if !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) + #define I2C_SPI_CTRL_SCLK_CONTINUOUS ((uint32) 0x01u << I2C_SPI_CTRL_SCLK_CONTINUOUS_POS) + #define I2C_SPI_CTRL_SSEL0_POLARITY ((uint32) 0x01u << I2C_SPI_CTRL_SSEL0_POLARITY_POS) + #define I2C_SPI_CTRL_SSEL1_POLARITY ((uint32) 0x01u << I2C_SPI_CTRL_SSEL1_POLARITY_POS) + #define I2C_SPI_CTRL_SSEL2_POLARITY ((uint32) 0x01u << I2C_SPI_CTRL_SSEL2_POLARITY_POS) + #define I2C_SPI_CTRL_SSEL3_POLARITY ((uint32) 0x01u << I2C_SPI_CTRL_SSEL3_POLARITY_POS) + #define I2C_SPI_CTRL_SSEL_POLARITY_MASK ((uint32)0x0Fu << I2C_SPI_CTRL_SSEL0_POLARITY_POS) +#endif /* !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) */ + +#define I2C_SPI_CTRL_LOOPBACK ((uint32) 0x01u << I2C_SPI_CTRL_LOOPBACK_POS) +#define I2C_SPI_CTRL_MODE_MASK ((uint32) 0x03u << I2C_SPI_CTRL_MODE_POS) +#define I2C_SPI_CTRL_MODE_MOTOROLA ((uint32) 0x00u) +#define I2C_SPI_CTRL_MODE_TI ((uint32) 0x01u << I2C_CTRL_MODE_POS) +#define I2C_SPI_CTRL_MODE_NS ((uint32) 0x02u << I2C_CTRL_MODE_POS) +#define I2C_SPI_CTRL_SLAVE_SELECT_MASK ((uint32) 0x03u << I2C_SPI_CTRL_SLAVE_SELECT_POS) +#define I2C_SPI_CTRL_SLAVE_SELECT0 ((uint32) 0x00u) +#define I2C_SPI_CTRL_SLAVE_SELECT1 ((uint32) 0x01u << I2C_SPI_CTRL_SLAVE_SELECT_POS) +#define I2C_SPI_CTRL_SLAVE_SELECT2 ((uint32) 0x02u << I2C_SPI_CTRL_SLAVE_SELECT_POS) +#define I2C_SPI_CTRL_SLAVE_SELECT3 ((uint32) 0x03u << I2C_SPI_CTRL_SLAVE_SELECT_POS) +#define I2C_SPI_CTRL_MASTER ((uint32) 0x01u << I2C_SPI_CTRL_MASTER_MODE_POS) +#define I2C_SPI_CTRL_SLAVE ((uint32) 0x00u) + +/* I2C_SPI_STATUS_REG */ +#define I2C_SPI_STATUS_BUS_BUSY_POS (0u) /* [0] Bus busy - slave selected */ +#define I2C_SPI_STATUS_EZBUF_ADDR_POS (8u) /* [15:8] EzAddress */ +#define I2C_SPI_STATUS_BUS_BUSY ((uint32) 0x01u) +#define I2C_SPI_STATUS_EZBUF_ADDR_MASK ((uint32) 0xFFu << I2C_I2C_STATUS_EZBUF_ADDR_POS) + +/* I2C_UART_CTRL */ +#define I2C_UART_CTRL_LOOPBACK_POS (16u) /* [16] Loop-back */ +#define I2C_UART_CTRL_MODE_POS (24u) /* [24] UART subMode */ +#define I2C_UART_CTRL_LOOPBACK ((uint32) 0x01u << I2C_UART_CTRL_LOOPBACK_POS) +#define I2C_UART_CTRL_MODE_UART_STD ((uint32) 0x00u) +#define I2C_UART_CTRL_MODE_UART_SMARTCARD ((uint32) 0x01u << I2C_UART_CTRL_MODE_POS) +#define I2C_UART_CTRL_MODE_UART_IRDA ((uint32) 0x02u << I2C_UART_CTRL_MODE_POS) +#define I2C_UART_CTRL_MODE_MASK ((uint32) 0x03u << I2C_UART_CTRL_MODE_POS) + +/* I2C_UART_TX_CTRL */ +#define I2C_UART_TX_CTRL_STOP_BITS_POS (0u) /* [2:0] Stop bits: (Stop bits + 1) * 0.5 period */ +#define I2C_UART_TX_CTRL_PARITY_POS (4u) /* [4] Parity bit */ +#define I2C_UART_TX_CTRL_PARITY_ENABLED_POS (5u) /* [5] Parity enable */ +#define I2C_UART_TX_CTRL_RETRY_ON_NACK_POS (8u) /* [8] Smart Card: re-send frame on NACK */ +#define I2C_UART_TX_CTRL_ONE_STOP_BIT ((uint32) 0x01u) +#define I2C_UART_TX_CTRL_ONE_HALF_STOP_BITS ((uint32) 0x02u) +#define I2C_UART_TX_CTRL_TWO_STOP_BITS ((uint32) 0x03u) +#define I2C_UART_TX_CTRL_STOP_BITS_MASK ((uint32) 0x07u) +#define I2C_UART_TX_CTRL_PARITY ((uint32) 0x01u << \ + I2C_UART_TX_CTRL_PARITY_POS) +#define I2C_UART_TX_CTRL_PARITY_ENABLED ((uint32) 0x01u << \ + I2C_UART_TX_CTRL_PARITY_ENABLED_POS) +#define I2C_UART_TX_CTRL_RETRY_ON_NACK ((uint32) 0x01u << \ + I2C_UART_TX_CTRL_RETRY_ON_NACK_POS) + +/* I2C_UART_RX_CTRL */ +#define I2C_UART_RX_CTRL_STOP_BITS_POS (0u) /* [2:0] Stop bits: (Stop bits + 1) * 0.5 period*/ +#define I2C_UART_RX_CTRL_PARITY_POS (4u) /* [4] Parity bit */ +#define I2C_UART_RX_CTRL_PARITY_ENABLED_POS (5u) /* [5] Parity enable */ +#define I2C_UART_RX_CTRL_POLARITY_POS (6u) /* [6] IrDA: inverts polarity of RX signal */ +#define I2C_UART_RX_CTRL_DROP_ON_PARITY_ERR_POS (8u) /* [8] Drop and lost RX FIFO on parity error */ +#define I2C_UART_RX_CTRL_DROP_ON_FRAME_ERR_POS (9u) /* [9] Drop and lost RX FIFO on frame error */ +#define I2C_UART_RX_CTRL_MP_MODE_POS (10u) /* [10] Multi-processor mode */ +#define I2C_UART_RX_CTRL_LIN_MODE_POS (12u) /* [12] Lin mode: applicable for UART Standard */ +#define I2C_UART_RX_CTRL_SKIP_START_POS (13u) /* [13] Skip start not: only for UART Standard */ +#define I2C_UART_RX_CTRL_BREAK_WIDTH_POS (16u) /* [19:16] Break width: (Break width + 1) */ +#define I2C_UART_TX_CTRL_ONE_STOP_BIT ((uint32) 0x01u) +#define I2C_UART_TX_CTRL_ONE_HALF_STOP_BITS ((uint32) 0x02u) +#define I2C_UART_TX_CTRL_TWO_STOP_BITS ((uint32) 0x03u) +#define I2C_UART_RX_CTRL_STOP_BITS_MASK ((uint32) 0x07u) +#define I2C_UART_RX_CTRL_PARITY ((uint32) 0x01u << \ + I2C_UART_RX_CTRL_PARITY_POS) +#define I2C_UART_RX_CTRL_PARITY_ENABLED ((uint32) 0x01u << \ + I2C_UART_RX_CTRL_PARITY_ENABLED_POS) +#define I2C_UART_RX_CTRL_POLARITY ((uint32) 0x01u << \ + I2C_UART_RX_CTRL_POLARITY_POS) +#define I2C_UART_RX_CTRL_DROP_ON_PARITY_ERR ((uint32) 0x01u << \ + I2C_UART_RX_CTRL_DROP_ON_PARITY_ERR_POS) +#define I2C_UART_RX_CTRL_DROP_ON_FRAME_ERR ((uint32) 0x01u << \ + I2C_UART_RX_CTRL_DROP_ON_FRAME_ERR_POS) +#define I2C_UART_RX_CTRL_MP_MODE ((uint32) 0x01u << \ + I2C_UART_RX_CTRL_MP_MODE_POS) +#define I2C_UART_RX_CTRL_LIN_MODE ((uint32) 0x01u << \ + I2C_UART_RX_CTRL_LIN_MODE_POS) +#define I2C_UART_RX_CTRL_SKIP_START ((uint32) 0x01u << \ + I2C_UART_RX_CTRL_SKIP_START_POS) +#define I2C_UART_RX_CTRL_BREAK_WIDTH_MASK ((uint32) 0x0Fu << \ + I2C_UART_RX_CTRL_BREAK_WIDTH_POS) +/* I2C_UART_RX_STATUS_REG */ +#define I2C_UART_RX_STATUS_BR_COUNTER_POS (0u) /* [11:0] Baud Rate counter */ +#define I2C_UART_RX_STATUS_BR_COUNTER_MASK ((uint32) 0xFFFu) + +#if !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) + /* I2C_UART_FLOW_CTRL_REG */ + #define I2C_UART_FLOW_CTRL_TRIGGER_LEVEL_POS (0u) /* [7:0] RTS RX FIFO trigger level */ + #define I2C_UART_FLOW_CTRL_RTS_POLARITY_POS (16u) /* [16] Polarity of the RTS output signal */ + #define I2C_UART_FLOW_CTRL_CTS_POLARITY_POS (24u) /* [24] Polarity of the CTS input signal */ + #define I2C_UART_FLOW_CTRL_CTS_ENABLED_POS (25u) /* [25] Enable CTS signal */ + #define I2C_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK ((uint32) I2C_FF_DATA_NR_LOG2_MASK) + #define I2C_UART_FLOW_CTRL_RTS_POLARITY ((uint32) 0x01u << \ + I2C_UART_FLOW_CTRL_RTS_POLARITY_POS) + #define I2C_UART_FLOW_CTRL_CTS_POLARITY ((uint32) 0x01u << \ + I2C_UART_FLOW_CTRL_CTS_POLARITY_POS) + #define I2C_UART_FLOW_CTRL_CTS_ENABLE ((uint32) 0x01u << \ + I2C_UART_FLOW_CTRL_CTS_ENABLED_POS) +#endif /* !(I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) */ + +/* I2C_I2C_CTRL */ +#define I2C_I2C_CTRL_HIGH_PHASE_OVS_POS (0u) /* [3:0] Oversampling factor high: master only */ +#define I2C_I2C_CTRL_LOW_PHASE_OVS_POS (4u) /* [7:4] Oversampling factor low: master only */ +#define I2C_I2C_CTRL_M_READY_DATA_ACK_POS (8u) /* [8] Master ACKs data while RX FIFO != FULL*/ +#define I2C_I2C_CTRL_M_NOT_READY_DATA_NACK_POS (9u) /* [9] Master NACKs data if RX FIFO == FULL */ +#define I2C_I2C_CTRL_S_GENERAL_IGNORE_POS (11u) /* [11] Slave ignores General call */ +#define I2C_I2C_CTRL_S_READY_ADDR_ACK_POS (12u) /* [12] Slave ACKs Address if RX FIFO != FULL */ +#define I2C_I2C_CTRL_S_READY_DATA_ACK_POS (13u) /* [13] Slave ACKs data while RX FIFO == FULL */ +#define I2C_I2C_CTRL_S_NOT_READY_ADDR_NACK_POS (14u) /* [14] Slave NACKs address if RX FIFO == FULL*/ +#define I2C_I2C_CTRL_S_NOT_READY_DATA_NACK_POS (15u) /* [15] Slave NACKs data if RX FIFO is FULL */ +#define I2C_I2C_CTRL_LOOPBACK_POS (16u) /* [16] Loop-back */ +#define I2C_I2C_CTRL_SLAVE_MODE_POS (30u) /* [30] Slave mode enabled */ +#define I2C_I2C_CTRL_MASTER_MODE_POS (31u) /* [31] Master mode enabled */ +#define I2C_I2C_CTRL_HIGH_PHASE_OVS_MASK ((uint32) 0x0Fu) +#define I2C_I2C_CTRL_LOW_PHASE_OVS_MASK ((uint32) 0x0Fu << \ + I2C_I2C_CTRL_LOW_PHASE_OVS_POS) +#define I2C_I2C_CTRL_M_READY_DATA_ACK ((uint32) 0x01u << \ + I2C_I2C_CTRL_M_READY_DATA_ACK_POS) +#define I2C_I2C_CTRL_M_NOT_READY_DATA_NACK ((uint32) 0x01u << \ + I2C_I2C_CTRL_M_NOT_READY_DATA_NACK_POS) +#define I2C_I2C_CTRL_S_GENERAL_IGNORE ((uint32) 0x01u << \ + I2C_I2C_CTRL_S_GENERAL_IGNORE_POS) +#define I2C_I2C_CTRL_S_READY_ADDR_ACK ((uint32) 0x01u << \ + I2C_I2C_CTRL_S_READY_ADDR_ACK_POS) +#define I2C_I2C_CTRL_S_READY_DATA_ACK ((uint32) 0x01u << \ + I2C_I2C_CTRL_S_READY_DATA_ACK_POS) +#define I2C_I2C_CTRL_S_NOT_READY_ADDR_NACK ((uint32) 0x01u << \ + I2C_I2C_CTRL_S_NOT_READY_ADDR_NACK_POS) +#define I2C_I2C_CTRL_S_NOT_READY_DATA_NACK ((uint32) 0x01u << \ + I2C_I2C_CTRL_S_NOT_READY_DATA_NACK_POS) +#define I2C_I2C_CTRL_LOOPBACK ((uint32) 0x01u << \ + I2C_I2C_CTRL_LOOPBACK_POS) +#define I2C_I2C_CTRL_SLAVE_MODE ((uint32) 0x01u << \ + I2C_I2C_CTRL_SLAVE_MODE_POS) +#define I2C_I2C_CTRL_MASTER_MODE ((uint32) 0x01u << \ + I2C_I2C_CTRL_MASTER_MODE_POS) +#define I2C_I2C_CTRL_SLAVE_MASTER_MODE_MASK ((uint32) 0x03u << \ + I2C_I2C_CTRL_SLAVE_MODE_POS) + +/* I2C_I2C_STATUS_REG */ +#define I2C_I2C_STATUS_BUS_BUSY_POS (0u) /* [0] Bus busy: internally clocked */ +#define I2C_I2C_STATUS_S_READ_POS (4u) /* [4] Slave is read by master */ +#define I2C_I2C_STATUS_M_READ_POS (5u) /* [5] Master reads Slave */ +#define I2C_I2C_STATUS_EZBUF_ADDR_POS (8u) /* [15:8] EZAddress */ +#define I2C_I2C_STATUS_BUS_BUSY ((uint32) 0x01u) +#define I2C_I2C_STATUS_S_READ ((uint32) 0x01u << I2C_I2C_STATUS_S_READ_POS) +#define I2C_I2C_STATUS_M_READ ((uint32) 0x01u << I2C_I2C_STATUS_M_READ_POS) +#define I2C_I2C_STATUS_EZBUF_ADDR_MASK ((uint32) 0xFFu << I2C_I2C_STATUS_EZBUF_ADDR_POS) + +/* I2C_I2C_MASTER_CMD_REG */ +#define I2C_I2C_MASTER_CMD_M_START_POS (0u) /* [0] Master generate Start */ +#define I2C_I2C_MASTER_CMD_M_START_ON_IDLE_POS (1u) /* [1] Master generate Start if bus is free */ +#define I2C_I2C_MASTER_CMD_M_ACK_POS (2u) /* [2] Master generate ACK */ +#define I2C_I2C_MASTER_CMD_M_NACK_POS (3u) /* [3] Master generate NACK */ +#define I2C_I2C_MASTER_CMD_M_STOP_POS (4u) /* [4] Master generate Stop */ +#define I2C_I2C_MASTER_CMD_M_START ((uint32) 0x01u) +#define I2C_I2C_MASTER_CMD_M_START_ON_IDLE ((uint32) 0x01u << \ + I2C_I2C_MASTER_CMD_M_START_ON_IDLE_POS) +#define I2C_I2C_MASTER_CMD_M_ACK ((uint32) 0x01u << \ + I2C_I2C_MASTER_CMD_M_ACK_POS) +#define I2C_I2C_MASTER_CMD_M_NACK ((uint32) 0x01u << \ + I2C_I2C_MASTER_CMD_M_NACK_POS) +#define I2C_I2C_MASTER_CMD_M_STOP ((uint32) 0x01u << \ + I2C_I2C_MASTER_CMD_M_STOP_POS) + +/* I2C_I2C_SLAVE_CMD_REG */ +#define I2C_I2C_SLAVE_CMD_S_ACK_POS (0u) /* [0] Slave generate ACK */ +#define I2C_I2C_SLAVE_CMD_S_NACK_POS (1u) /* [1] Slave generate NACK */ +#define I2C_I2C_SLAVE_CMD_S_ACK ((uint32) 0x01u) +#define I2C_I2C_SLAVE_CMD_S_NACK ((uint32) 0x01u << I2C_I2C_SLAVE_CMD_S_NACK_POS) + +#define I2C_I2C_SLAVE_CMD_S_ACK_POS (0u) /* [0] Slave generate ACK */ +#define I2C_I2C_SLAVE_CMD_S_NACK_POS (1u) /* [1] Slave generate NACK */ +#define I2C_I2C_SLAVE_CMD_S_ACK ((uint32) 0x01u) +#define I2C_I2C_SLAVE_CMD_S_NACK ((uint32) 0x01u << I2C_I2C_SLAVE_CMD_S_NACK_POS) + +/* I2C_I2C_CFG_REG */ +#if (I2C_CY_SCBIP_V0) +#define I2C_I2C_CFG_SDA_FILT_HYS_POS (0u) /* [1:0] Trim bits for the I2C SDA filter */ +#define I2C_I2C_CFG_SDA_FILT_TRIM_POS (2u) /* [3:2] Trim bits for the I2C SDA filter */ +#define I2C_I2C_CFG_SCL_FILT_HYS_POS (4u) /* [5:4] Trim bits for the I2C SCL filter */ +#define I2C_I2C_CFG_SCL_FILT_TRIM_POS (6u) /* [7:6] Trim bits for the I2C SCL filter */ +#define I2C_I2C_CFG_SDA_FILT_OUT_HYS_POS (8u) /* [9:8] Trim bits for I2C SDA filter output path */ +#define I2C_I2C_CFG_SDA_FILT_OUT_TRIM_POS (10u) /* [11:10] Trim bits for I2C SDA filter output path */ +#define I2C_I2C_CFG_SDA_FILT_HS_POS (16u) /* [16] '0': 50 ns filter, '1': 10 ns filter */ +#define I2C_I2C_CFG_SDA_FILT_ENABLED_POS (17u) /* [17] I2C SDA filter enabled */ +#define I2C_I2C_CFG_SCL_FILT_HS_POS (24u) /* [24] '0': 50 ns filter, '1': 10 ns filter */ +#define I2C_I2C_CFG_SCL_FILT_ENABLED_POS (25u) /* [25] I2C SCL filter enabled */ +#define I2C_I2C_CFG_SDA_FILT_OUT_HS_POS (26u) /* [26] '0': 50 ns filter, '1': 10 ns filter */ +#define I2C_I2C_CFG_SDA_FILT_OUT_ENABLED_POS (27u) /* [27] I2C SDA output delay filter enabled */ +#define I2C_I2C_CFG_SDA_FILT_HYS_MASK ((uint32) 0x03u) +#define I2C_I2C_CFG_SDA_FILT_TRIM_MASK ((uint32) 0x03u << \ + I2C_I2C_CFG_SDA_FILT_TRIM_POS) +#define I2C_I2C_CFG_SCL_FILT_HYS_MASK ((uint32) 0x03u << \ + I2C_I2C_CFG_SCL_FILT_HYS_POS) +#define I2C_I2C_CFG_SCL_FILT_TRIM_MASK ((uint32) 0x03u << \ + I2C_I2C_CFG_SCL_FILT_TRIM_POS) +#define I2C_I2C_CFG_SDA_FILT_OUT_HYS_MASK ((uint32) 0x03u << \ + I2C_I2C_CFG_SDA_FILT_OUT_HYS_POS) +#define I2C_I2C_CFG_SDA_FILT_OUT_TRIM_MASK ((uint32) 0x03u << \ + I2C_I2C_CFG_SDA_FILT_OUT_TRIM_POS) +#define I2C_I2C_CFG_SDA_FILT_HS ((uint32) 0x01u << \ + I2C_I2C_CFG_SDA_FILT_HS_POS) +#define I2C_I2C_CFG_SDA_FILT_ENABLED ((uint32) 0x01u << \ + I2C_I2C_CFG_SDA_FILT_ENABLED_POS) +#define I2C_I2C_CFG_SCL_FILT_HS ((uint32) 0x01u << \ + I2C_I2C_CFG_SCL_FILT_HS_POS) +#define I2C_I2C_CFG_SCL_FILT_ENABLED ((uint32) 0x01u << \ + I2C_I2C_CFG_SCL_FILT_ENABLED_POS) +#define I2C_I2C_CFG_SDA_FILT_OUT_HS ((uint32) 0x01u << \ + I2C_I2C_CFG_SDA_FILT_OUT_HS_POS) +#define I2C_I2C_CFG_SDA_FILT_OUT_ENABLED ((uint32) 0x01u << \ + I2C_I2C_CFG_SDA_FILT_OUT_ENABLED_POS) +#else +#define I2C_I2C_CFG_SDA_IN_FILT_TRIM_POS (0u) /* [1:0] Trim bits for "i2c_sda_in" 50 ns filter */ +#define I2C_I2C_CFG_SDA_IN_FILT_SEL_POS (4u) /* [4] "i2c_sda_in" filter delay: 0 ns and 50 ns */ +#define I2C_I2C_CFG_SCL_IN_FILT_TRIM_POS (8u) /* [9:8] Trim bits for "i2c_scl_in" 50 ns filter */ +#define I2C_I2C_CFG_SCL_IN_FILT_SEL_POS (12u) /* [12] "i2c_scl_in" filter delay: 0 ns and 50 ns */ +#define I2C_I2C_CFG_SDA_OUT_FILT0_TRIM_POS (16u) /* [17:16] Trim bits for "i2c_sda_out" 50 ns filter 0 */ +#define I2C_I2C_CFG_SDA_OUT_FILT1_TRIM_POS (18u) /* [19:18] Trim bits for "i2c_sda_out" 50 ns filter 1 */ +#define I2C_I2C_CFG_SDA_OUT_FILT2_TRIM_POS (20u) /* [21:20] Trim bits for "i2c_sda_out" 50 ns filter 2 */ +#define I2C_I2C_CFG_SDA_OUT_FILT_SEL_POS (28u) /* [29:28] Cumulative "i2c_sda_out" filter delay: */ + +#define I2C_I2C_CFG_SDA_IN_FILT_TRIM_MASK ((uint32) 0x03u) +#define I2C_I2C_CFG_SDA_IN_FILT_SEL ((uint32) 0x01u << I2C_I2C_CFG_SDA_IN_FILT_SEL_POS) +#define I2C_I2C_CFG_SCL_IN_FILT_TRIM_MASK ((uint32) 0x03u << \ + I2C_I2C_CFG_SCL_IN_FILT_TRIM_POS) +#define I2C_I2C_CFG_SCL_IN_FILT_SEL ((uint32) 0x01u << I2C_I2C_CFG_SCL_IN_FILT_SEL_POS) +#define I2C_I2C_CFG_SDA_OUT_FILT0_TRIM_MASK ((uint32) 0x03u << \ + I2C_I2C_CFG_SDA_OUT_FILT0_TRIM_POS) +#define I2C_I2C_CFG_SDA_OUT_FILT1_TRIM_MASK ((uint32) 0x03u << \ + I2C_I2C_CFG_SDA_OUT_FILT1_TRIM_POS) +#define I2C_I2C_CFG_SDA_OUT_FILT2_TRIM_MASK ((uint32) 0x03u << \ + I2C_I2C_CFG_SDA_OUT_FILT2_TRIM_POS) +#define I2C_I2C_CFG_SDA_OUT_FILT_SEL_MASK ((uint32) 0x03u << \ + I2C_I2C_CFG_SDA_OUT_FILT_SEL_POS) +#endif /* (I2C_CY_SCBIP_V0) */ + + +/* I2C_TX_CTRL_REG */ +#define I2C_TX_CTRL_DATA_WIDTH_POS (0u) /* [3:0] Data frame width: (Data width - 1) */ +#define I2C_TX_CTRL_MSB_FIRST_POS (8u) /* [8] MSB first shifter-out */ +#define I2C_TX_CTRL_ENABLED_POS (31u) /* [31] Transmitter enabled */ +#define I2C_TX_CTRL_DATA_WIDTH_MASK ((uint32) 0x0Fu) +#define I2C_TX_CTRL_MSB_FIRST ((uint32) 0x01u << I2C_TX_CTRL_MSB_FIRST_POS) +#define I2C_TX_CTRL_LSB_FIRST ((uint32) 0x00u) +#define I2C_TX_CTRL_ENABLED ((uint32) 0x01u << I2C_TX_CTRL_ENABLED_POS) + +/* I2C_TX_CTRL_FIFO_REG */ +#define I2C_TX_FIFO_CTRL_TRIGGER_LEVEL_POS (0u) /* [2:0] Trigger level */ +#define I2C_TX_FIFO_CTRL_CLEAR_POS (16u) /* [16] Clear TX FIFO: cleared after set */ +#define I2C_TX_FIFO_CTRL_FREEZE_POS (17u) /* [17] Freeze TX FIFO: HW do not inc read pointer */ +#define I2C_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK ((uint32) I2C_FF_DATA_NR_LOG2_MASK) +#define I2C_TX_FIFO_CTRL_CLEAR ((uint32) 0x01u << I2C_TX_FIFO_CTRL_CLEAR_POS) +#define I2C_TX_FIFO_CTRL_FREEZE ((uint32) 0x01u << I2C_TX_FIFO_CTRL_FREEZE_POS) + +/* I2C_TX_FIFO_STATUS_REG */ +#define I2C_TX_FIFO_STATUS_USED_POS (0u) /* [3:0] Amount of entries in TX FIFO */ +#define I2C_TX_FIFO_SR_VALID_POS (15u) /* [15] Shifter status of TX FIFO */ +#define I2C_TX_FIFO_STATUS_RD_PTR_POS (16u) /* [18:16] TX FIFO read pointer */ +#define I2C_TX_FIFO_STATUS_WR_PTR_POS (24u) /* [26:24] TX FIFO write pointer */ +#define I2C_TX_FIFO_STATUS_USED_MASK ((uint32) I2C_FF_DATA_NR_LOG2_PLUS1_MASK) +#define I2C_TX_FIFO_SR_VALID ((uint32) 0x01u << I2C_TX_FIFO_SR_VALID_POS) +#define I2C_TX_FIFO_STATUS_RD_PTR_MASK ((uint32) I2C_FF_DATA_NR_LOG2_MASK << \ + I2C_TX_FIFO_STATUS_RD_PTR_POS) +#define I2C_TX_FIFO_STATUS_WR_PTR_MASK ((uint32) I2C_FF_DATA_NR_LOG2_MASK << \ + I2C_TX_FIFO_STATUS_WR_PTR_POS) + +/* I2C_TX_FIFO_WR_REG */ +#define I2C_TX_FIFO_WR_POS (0u) /* [15:0] Data written into TX FIFO */ +#define I2C_TX_FIFO_WR_MASK ((uint32) 0xFFu) + +/* I2C_RX_CTRL_REG */ +#define I2C_RX_CTRL_DATA_WIDTH_POS (0u) /* [3:0] Data frame width: (Data width - 1) */ +#define I2C_RX_CTRL_MSB_FIRST_POS (8u) /* [8] MSB first shifter-out */ +#define I2C_RX_CTRL_MEDIAN_POS (9u) /* [9] Median filter */ +#define I2C_RX_CTRL_ENABLED_POS (31u) /* [31] Receiver enabled */ +#define I2C_RX_CTRL_DATA_WIDTH_MASK ((uint32) 0x0Fu) +#define I2C_RX_CTRL_MSB_FIRST ((uint32) 0x01u << I2C_RX_CTRL_MSB_FIRST_POS) +#define I2C_RX_CTRL_LSB_FIRST ((uint32) 0x00u) +#define I2C_RX_CTRL_MEDIAN ((uint32) 0x01u << I2C_RX_CTRL_MEDIAN_POS) +#define I2C_RX_CTRL_ENABLED ((uint32) 0x01u << I2C_RX_CTRL_ENABLED_POS) + + +/* I2C_RX_FIFO_CTRL_REG */ +#define I2C_RX_FIFO_CTRL_TRIGGER_LEVEL_POS (0u) /* [2:0] Trigger level */ +#define I2C_RX_FIFO_CTRL_CLEAR_POS (16u) /* [16] Clear RX FIFO: clear after set */ +#define I2C_RX_FIFO_CTRL_FREEZE_POS (17u) /* [17] Freeze RX FIFO: HW writes has not effect */ +#define I2C_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK ((uint32) I2C_FF_DATA_NR_LOG2_MASK) +#define I2C_RX_FIFO_CTRL_CLEAR ((uint32) 0x01u << I2C_RX_FIFO_CTRL_CLEAR_POS) +#define I2C_RX_FIFO_CTRL_FREEZE ((uint32) 0x01u << I2C_RX_FIFO_CTRL_FREEZE_POS) + +/* I2C_RX_FIFO_STATUS_REG */ +#define I2C_RX_FIFO_STATUS_USED_POS (0u) /* [3:0] Amount of entries in RX FIFO */ +#define I2C_RX_FIFO_SR_VALID_POS (15u) /* [15] Shifter status of RX FIFO */ +#define I2C_RX_FIFO_STATUS_RD_PTR_POS (16u) /* [18:16] RX FIFO read pointer */ +#define I2C_RX_FIFO_STATUS_WR_PTR_POS (24u) /* [26:24] RX FIFO write pointer */ +#define I2C_RX_FIFO_STATUS_USED_MASK ((uint32) I2C_FF_DATA_NR_LOG2_PLUS1_MASK) +#define I2C_RX_FIFO_SR_VALID ((uint32) 0x01u << I2C_RX_FIFO_SR_VALID_POS) +#define I2C_RX_FIFO_STATUS_RD_PTR_MASK ((uint32) I2C_FF_DATA_NR_LOG2_MASK << \ + I2C_RX_FIFO_STATUS_RD_PTR_POS) +#define I2C_RX_FIFO_STATUS_WR_PTR_MASK ((uint32) I2C_FF_DATA_NR_LOG2_MASK << \ + I2C_RX_FIFO_STATUS_WR_PTR_POS) + +/* I2C_RX_MATCH_REG */ +#define I2C_RX_MATCH_ADDR_POS (0u) /* [7:0] Slave address */ +#define I2C_RX_MATCH_MASK_POS (16u) /* [23:16] Slave address mask: 0 - doesn't care */ +#define I2C_RX_MATCH_ADDR_MASK ((uint32) 0xFFu) +#define I2C_RX_MATCH_MASK_MASK ((uint32) 0xFFu << I2C_RX_MATCH_MASK_POS) + +/* I2C_RX_FIFO_WR_REG */ +#define I2C_RX_FIFO_RD_POS (0u) /* [15:0] Data read from RX FIFO */ +#define I2C_RX_FIFO_RD_MASK ((uint32) 0xFFu) + +/* I2C_RX_FIFO_RD_SILENT_REG */ +#define I2C_RX_FIFO_RD_SILENT_POS (0u) /* [15:0] Data read from RX FIFO: not remove data from FIFO */ +#define I2C_RX_FIFO_RD_SILENT_MASK ((uint32) 0xFFu) + +/* I2C_RX_FIFO_RD_SILENT_REG */ +#define I2C_RX_FIFO_RD_SILENT_POS (0u) /* [15:0] Data read from RX FIFO: not remove data from FIFO */ +#define I2C_RX_FIFO_RD_SILENT_MASK ((uint32) 0xFFu) + +/* I2C_EZBUF_DATA_REG */ +#define I2C_EZBUF_DATA_POS (0u) /* [7:0] Data from EZ Memory */ +#define I2C_EZBUF_DATA_MASK ((uint32) 0xFFu) + +/* I2C_INTR_CAUSE_REG */ +#define I2C_INTR_CAUSE_MASTER_POS (0u) /* [0] Master interrupt active */ +#define I2C_INTR_CAUSE_SLAVE_POS (1u) /* [1] Slave interrupt active */ +#define I2C_INTR_CAUSE_TX_POS (2u) /* [2] Transmitter interrupt active */ +#define I2C_INTR_CAUSE_RX_POS (3u) /* [3] Receiver interrupt active */ +#define I2C_INTR_CAUSE_I2C_EC_POS (4u) /* [4] Externally clock I2C interrupt active */ +#define I2C_INTR_CAUSE_SPI_EC_POS (5u) /* [5] Externally clocked SPI interrupt active */ +#define I2C_INTR_CAUSE_MASTER ((uint32) 0x01u) +#define I2C_INTR_CAUSE_SLAVE ((uint32) 0x01u << I2C_INTR_CAUSE_SLAVE_POS) +#define I2C_INTR_CAUSE_TX ((uint32) 0x01u << I2C_INTR_CAUSE_TX_POS) +#define I2C_INTR_CAUSE_RX ((uint32) 0x01u << I2C_INTR_CAUSE_RX_POS) +#define I2C_INTR_CAUSE_I2C_EC ((uint32) 0x01u << I2C_INTR_CAUSE_I2C_EC_POS) +#define I2C_INTR_CAUSE_SPI_EC ((uint32) 0x01u << I2C_INTR_CAUSE_SPI_EC_POS) + +/* I2C_INTR_SPI_EC_REG, I2C_INTR_SPI_EC_MASK_REG, I2C_INTR_SPI_EC_MASKED_REG */ +#define I2C_INTR_SPI_EC_WAKE_UP_POS (0u) /* [0] Address match: triggers wakeup of chip */ +#define I2C_INTR_SPI_EC_EZBUF_STOP_POS (1u) /* [1] Externally clocked Stop detected */ +#define I2C_INTR_SPI_EC_EZBUF_WRITE_STOP_POS (2u) /* [2] Externally clocked Write Stop detected */ +#define I2C_INTR_SPI_EC_WAKE_UP ((uint32) 0x01u) +#define I2C_INTR_SPI_EC_EZBUF_STOP ((uint32) 0x01u << \ + I2C_INTR_SPI_EC_EZBUF_STOP_POS) +#define I2C_INTR_SPI_EC_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + I2C_INTR_SPI_EC_EZBUF_WRITE_STOP_POS) + +/* I2C_INTR_I2C_EC, I2C_INTR_I2C_EC_MASK, I2C_INTR_I2C_EC_MASKED */ +#define I2C_INTR_I2C_EC_WAKE_UP_POS (0u) /* [0] Address match: triggers wakeup of chip */ +#define I2C_INTR_I2C_EC_EZBUF_STOP_POS (1u) /* [1] Externally clocked Stop detected */ +#define I2C_INTR_I2C_EC_EZBUF_WRITE_STOP_POS (2u) /* [2] Externally clocked Write Stop detected */ +#define I2C_INTR_I2C_EC_WAKE_UP ((uint32) 0x01u) +#define I2C_INTR_I2C_EC_EZBUF_STOP ((uint32) 0x01u << \ + I2C_INTR_I2C_EC_EZBUF_STOP_POS) +#define I2C_INTR_I2C_EC_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + I2C_INTR_I2C_EC_EZBUF_WRITE_STOP_POS) + +/* I2C_INTR_MASTER, I2C_INTR_MASTER_SET, + I2C_INTR_MASTER_MASK, I2C_INTR_MASTER_MASKED */ +#define I2C_INTR_MASTER_I2C_ARB_LOST_POS (0u) /* [0] Master lost arbitration */ +#define I2C_INTR_MASTER_I2C_NACK_POS (1u) /* [1] Master receives NACK: address or write to slave */ +#define I2C_INTR_MASTER_I2C_ACK_POS (2u) /* [2] Master receives NACK: address or write to slave */ +#define I2C_INTR_MASTER_I2C_STOP_POS (4u) /* [4] Master detects the Stop: only self generated Stop*/ +#define I2C_INTR_MASTER_I2C_BUS_ERROR_POS (8u) /* [8] Master detects bus error: misplaced Start or Stop*/ +#define I2C_INTR_MASTER_SPI_DONE_POS (9u) /* [9] Master complete transfer: Only for SPI */ +#define I2C_INTR_MASTER_I2C_ARB_LOST ((uint32) 0x01u) +#define I2C_INTR_MASTER_I2C_NACK ((uint32) 0x01u << I2C_INTR_MASTER_I2C_NACK_POS) +#define I2C_INTR_MASTER_I2C_ACK ((uint32) 0x01u << I2C_INTR_MASTER_I2C_ACK_POS) +#define I2C_INTR_MASTER_I2C_STOP ((uint32) 0x01u << I2C_INTR_MASTER_I2C_STOP_POS) +#define I2C_INTR_MASTER_I2C_BUS_ERROR ((uint32) 0x01u << \ + I2C_INTR_MASTER_I2C_BUS_ERROR_POS) +#define I2C_INTR_MASTER_SPI_DONE ((uint32) 0x01u << I2C_INTR_MASTER_SPI_DONE_POS) + +/* +* I2C_INTR_SLAVE, I2C_INTR_SLAVE_SET, +* I2C_INTR_SLAVE_MASK, I2C_INTR_SLAVE_MASKED +*/ +#define I2C_INTR_SLAVE_I2C_ARB_LOST_POS (0u) /* [0] Slave lost arbitration */ +#define I2C_INTR_SLAVE_I2C_NACK_POS (1u) /* [1] Slave receives NACK: master reads data */ +#define I2C_INTR_SLAVE_I2C_ACK_POS (2u) /* [2] Slave receives ACK: master reads data */ +#define I2C_INTR_SLAVE_I2C_WRITE_STOP_POS (3u) /* [3] Slave detects end of write transaction */ +#define I2C_INTR_SLAVE_I2C_STOP_POS (4u) /* [4] Slave detects end of transaction intended */ +#define I2C_INTR_SLAVE_I2C_START_POS (5u) /* [5] Slave detects Start */ +#define I2C_INTR_SLAVE_I2C_ADDR_MATCH_POS (6u) /* [6] Slave address matches */ +#define I2C_INTR_SLAVE_I2C_GENERAL_POS (7u) /* [7] General call received */ +#define I2C_INTR_SLAVE_I2C_BUS_ERROR_POS (8u) /* [8] Slave detects bus error */ +#define I2C_INTR_SLAVE_SPI_EZBUF_WRITE_STOP_POS (9u) /* [9] Slave write complete: Only for SPI */ +#define I2C_INTR_SLAVE_SPI_EZBUF_STOP_POS (10u) /* [10] Slave end of transaction: Only for SPI */ +#define I2C_INTR_SLAVE_SPI_BUS_ERROR_POS (11u) /* [11] Slave detects bus error: Only for SPI */ +#define I2C_INTR_SLAVE_I2C_ARB_LOST ((uint32) 0x01u) +#define I2C_INTR_SLAVE_I2C_NACK ((uint32) 0x01u << \ + I2C_INTR_SLAVE_I2C_NACK_POS) +#define I2C_INTR_SLAVE_I2C_ACK ((uint32) 0x01u << \ + I2C_INTR_SLAVE_I2C_ACK_POS) +#define I2C_INTR_SLAVE_I2C_WRITE_STOP ((uint32) 0x01u << \ + I2C_INTR_SLAVE_I2C_WRITE_STOP_POS) +#define I2C_INTR_SLAVE_I2C_STOP ((uint32) 0x01u << \ + I2C_INTR_SLAVE_I2C_STOP_POS) +#define I2C_INTR_SLAVE_I2C_START ((uint32) 0x01u << \ + I2C_INTR_SLAVE_I2C_START_POS) +#define I2C_INTR_SLAVE_I2C_ADDR_MATCH ((uint32) 0x01u << \ + I2C_INTR_SLAVE_I2C_ADDR_MATCH_POS) +#define I2C_INTR_SLAVE_I2C_GENERAL ((uint32) 0x01u << \ + I2C_INTR_SLAVE_I2C_GENERAL_POS) +#define I2C_INTR_SLAVE_I2C_BUS_ERROR ((uint32) 0x01u << \ + I2C_INTR_SLAVE_I2C_BUS_ERROR_POS) +#define I2C_INTR_SLAVE_SPI_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + I2C_INTR_SLAVE_SPI_EZBUF_WRITE_STOP_POS) +#define I2C_INTR_SLAVE_SPI_EZBUF_STOP ((uint32) 0x01u << \ + I2C_INTR_SLAVE_SPI_EZBUF_STOP_POS) +#define I2C_INTR_SLAVE_SPI_BUS_ERROR ((uint32) 0x01u << \ + I2C_INTR_SLAVE_SPI_BUS_ERROR_POS) + +/* +* I2C_INTR_TX, I2C_INTR_TX_SET, +* I2C_INTR_TX_MASK, I2C_INTR_TX_MASKED +*/ +#define I2C_INTR_TX_TRIGGER_POS (0u) /* [0] Trigger on TX FIFO entires */ +#define I2C_INTR_TX_NOT_FULL_POS (1u) /* [1] TX FIFO is not full */ +#define I2C_INTR_TX_EMPTY_POS (4u) /* [4] TX FIFO is empty */ +#define I2C_INTR_TX_OVERFLOW_POS (5u) /* [5] Attempt to write to a full TX FIFO */ +#define I2C_INTR_TX_UNDERFLOW_POS (6u) /* [6] Attempt to read from an empty TX FIFO */ +#define I2C_INTR_TX_BLOCKED_POS (7u) /* [7] No access to the EZ memory */ +#define I2C_INTR_TX_UART_NACK_POS (8u) /* [8] UART transmitter received a NACK: SmartCard mode */ +#define I2C_INTR_TX_UART_DONE_POS (9u) /* [9] UART transmitter done even */ +#define I2C_INTR_TX_UART_ARB_LOST_POS (10u) /* [10] UART lost arbitration: LIN or SmartCard */ +#define I2C_INTR_TX_TRIGGER ((uint32) 0x01u) +#define I2C_INTR_TX_FIFO_LEVEL (I2C_INTR_TX_TRIGGER) +#define I2C_INTR_TX_NOT_FULL ((uint32) 0x01u << I2C_INTR_TX_NOT_FULL_POS) +#define I2C_INTR_TX_EMPTY ((uint32) 0x01u << I2C_INTR_TX_EMPTY_POS) +#define I2C_INTR_TX_OVERFLOW ((uint32) 0x01u << I2C_INTR_TX_OVERFLOW_POS) +#define I2C_INTR_TX_UNDERFLOW ((uint32) 0x01u << I2C_INTR_TX_UNDERFLOW_POS) +#define I2C_INTR_TX_BLOCKED ((uint32) 0x01u << I2C_INTR_TX_BLOCKED_POS) +#define I2C_INTR_TX_UART_NACK ((uint32) 0x01u << I2C_INTR_TX_UART_NACK_POS) +#define I2C_INTR_TX_UART_DONE ((uint32) 0x01u << I2C_INTR_TX_UART_DONE_POS) +#define I2C_INTR_TX_UART_ARB_LOST ((uint32) 0x01u << I2C_INTR_TX_UART_ARB_LOST_POS) + +/* +* I2C_INTR_RX, I2C_INTR_RX_SET, +* I2C_INTR_RX_MASK, I2C_INTR_RX_MASKED +*/ +#define I2C_INTR_RX_TRIGGER_POS (0u) /* [0] Trigger on RX FIFO entires */ +#define I2C_INTR_RX_NOT_EMPTY_POS (2u) /* [2] RX FIFO is not empty */ +#define I2C_INTR_RX_FULL_POS (3u) /* [3] RX FIFO is full */ +#define I2C_INTR_RX_OVERFLOW_POS (5u) /* [5] Attempt to write to a full RX FIFO */ +#define I2C_INTR_RX_UNDERFLOW_POS (6u) /* [6] Attempt to read from an empty RX FIFO */ +#define I2C_INTR_RX_BLOCKED_POS (7u) /* [7] No access to the EZ memory */ +#define I2C_INTR_RX_FRAME_ERROR_POS (8u) /* [8] Frame error in received data frame */ +#define I2C_INTR_RX_PARITY_ERROR_POS (9u) /* [9] Parity error in received data frame */ +#define I2C_INTR_RX_BAUD_DETECT_POS (10u) /* [10] LIN baud rate detection is completed */ +#define I2C_INTR_RX_BREAK_DETECT_POS (11u) /* [11] Break detection is successful */ +#define I2C_INTR_RX_TRIGGER ((uint32) 0x01u) +#define I2C_INTR_RX_FIFO_LEVEL (I2C_INTR_RX_TRIGGER) +#define I2C_INTR_RX_NOT_EMPTY ((uint32) 0x01u << I2C_INTR_RX_NOT_EMPTY_POS) +#define I2C_INTR_RX_FULL ((uint32) 0x01u << I2C_INTR_RX_FULL_POS) +#define I2C_INTR_RX_OVERFLOW ((uint32) 0x01u << I2C_INTR_RX_OVERFLOW_POS) +#define I2C_INTR_RX_UNDERFLOW ((uint32) 0x01u << I2C_INTR_RX_UNDERFLOW_POS) +#define I2C_INTR_RX_BLOCKED ((uint32) 0x01u << I2C_INTR_RX_BLOCKED_POS) +#define I2C_INTR_RX_FRAME_ERROR ((uint32) 0x01u << I2C_INTR_RX_FRAME_ERROR_POS) +#define I2C_INTR_RX_PARITY_ERROR ((uint32) 0x01u << I2C_INTR_RX_PARITY_ERROR_POS) +#define I2C_INTR_RX_BAUD_DETECT ((uint32) 0x01u << I2C_INTR_RX_BAUD_DETECT_POS) +#define I2C_INTR_RX_BREAK_DETECT ((uint32) 0x01u << I2C_INTR_RX_BREAK_DETECT_POS) + +/* Define all interrupt sources */ +#define I2C_INTR_I2C_EC_ALL (I2C_INTR_I2C_EC_WAKE_UP | \ + I2C_INTR_I2C_EC_EZBUF_STOP | \ + I2C_INTR_I2C_EC_EZBUF_WRITE_STOP) + +#define I2C_INTR_SPI_EC_ALL (I2C_INTR_SPI_EC_WAKE_UP | \ + I2C_INTR_SPI_EC_EZBUF_STOP | \ + I2C_INTR_SPI_EC_EZBUF_WRITE_STOP) + +#define I2C_INTR_MASTER_ALL (I2C_INTR_MASTER_I2C_ARB_LOST | \ + I2C_INTR_MASTER_I2C_NACK | \ + I2C_INTR_MASTER_I2C_ACK | \ + I2C_INTR_MASTER_I2C_STOP | \ + I2C_INTR_MASTER_I2C_BUS_ERROR | \ + I2C_INTR_MASTER_SPI_DONE) + +#define I2C_INTR_SLAVE_ALL (I2C_INTR_SLAVE_I2C_ARB_LOST | \ + I2C_INTR_SLAVE_I2C_NACK | \ + I2C_INTR_SLAVE_I2C_ACK | \ + I2C_INTR_SLAVE_I2C_WRITE_STOP | \ + I2C_INTR_SLAVE_I2C_STOP | \ + I2C_INTR_SLAVE_I2C_START | \ + I2C_INTR_SLAVE_I2C_ADDR_MATCH | \ + I2C_INTR_SLAVE_I2C_GENERAL | \ + I2C_INTR_SLAVE_I2C_BUS_ERROR | \ + I2C_INTR_SLAVE_SPI_EZBUF_WRITE_STOP | \ + I2C_INTR_SLAVE_SPI_EZBUF_STOP | \ + I2C_INTR_SLAVE_SPI_BUS_ERROR) + +#define I2C_INTR_TX_ALL (I2C_INTR_TX_TRIGGER | \ + I2C_INTR_TX_NOT_FULL | \ + I2C_INTR_TX_EMPTY | \ + I2C_INTR_TX_OVERFLOW | \ + I2C_INTR_TX_UNDERFLOW | \ + I2C_INTR_TX_BLOCKED | \ + I2C_INTR_TX_UART_NACK | \ + I2C_INTR_TX_UART_DONE | \ + I2C_INTR_TX_UART_ARB_LOST) + +#define I2C_INTR_RX_ALL (I2C_INTR_RX_TRIGGER | \ + I2C_INTR_RX_NOT_EMPTY | \ + I2C_INTR_RX_FULL | \ + I2C_INTR_RX_OVERFLOW | \ + I2C_INTR_RX_UNDERFLOW | \ + I2C_INTR_RX_BLOCKED | \ + I2C_INTR_RX_FRAME_ERROR | \ + I2C_INTR_RX_PARITY_ERROR | \ + I2C_INTR_RX_BAUD_DETECT | \ + I2C_INTR_RX_BREAK_DETECT) + +/* I2C and EZI2C slave address defines */ +#define I2C_I2C_SLAVE_ADDR_POS (0x01u) /* 7-bit address shift */ +#define I2C_I2C_SLAVE_ADDR_MASK (0xFEu) /* 8-bit address mask */ + +/* OVS constants for IrDA Low Power operation */ +#define I2C_CTRL_OVS_IRDA_LP_OVS16 (0x00u) +#define I2C_CTRL_OVS_IRDA_LP_OVS32 (0x01u) +#define I2C_CTRL_OVS_IRDA_LP_OVS48 (0x02u) +#define I2C_CTRL_OVS_IRDA_LP_OVS96 (0x03u) +#define I2C_CTRL_OVS_IRDA_LP_OVS192 (0x04u) +#define I2C_CTRL_OVS_IRDA_LP_OVS768 (0x05u) +#define I2C_CTRL_OVS_IRDA_LP_OVS1536 (0x06u) + +/* OVS constant for IrDA */ +#define I2C_CTRL_OVS_IRDA_OVS16 (I2C_UART_IRDA_LP_OVS16) + + +/*************************************** +* Common Macro Definitions +***************************************/ + +/* Re-enables the SCB IP. A clear enable bit has a different effect +* on the scb IP depending on the version: +* CY_SCBIP_V0: resets state, status, TX and RX FIFOs. +* CY_SCBIP_V1 or later: resets state, status, TX and RX FIFOs and interrupt sources. +* Clear I2C command registers are because they are not impacted by re-enable. +*/ +#define I2C_SCB_SW_RESET I2C_I2CFwBlockReset() + +/* TX FIFO macro */ +#define I2C_CLEAR_TX_FIFO \ + do{ \ + I2C_TX_FIFO_CTRL_REG |= ((uint32) I2C_TX_FIFO_CTRL_CLEAR); \ + I2C_TX_FIFO_CTRL_REG &= ((uint32) ~I2C_TX_FIFO_CTRL_CLEAR); \ + }while(0) + +#define I2C_GET_TX_FIFO_ENTRIES (I2C_TX_FIFO_STATUS_REG & \ + I2C_TX_FIFO_STATUS_USED_MASK) + +#define I2C_GET_TX_FIFO_SR_VALID ((0u != (I2C_TX_FIFO_STATUS_REG & \ + I2C_TX_FIFO_SR_VALID)) ? (1u) : (0u)) + +/* RX FIFO macro */ +#define I2C_CLEAR_RX_FIFO \ + do{ \ + I2C_RX_FIFO_CTRL_REG |= ((uint32) I2C_RX_FIFO_CTRL_CLEAR); \ + I2C_RX_FIFO_CTRL_REG &= ((uint32) ~I2C_RX_FIFO_CTRL_CLEAR); \ + }while(0) + +#define I2C_GET_RX_FIFO_ENTRIES (I2C_RX_FIFO_STATUS_REG & \ + I2C_RX_FIFO_STATUS_USED_MASK) + +#define I2C_GET_RX_FIFO_SR_VALID ((0u != (I2C_RX_FIFO_STATUS_REG & \ + I2C_RX_FIFO_SR_VALID)) ? (1u) : (0u)) + +/* Write interrupt source: set sourceMask bits in I2C_INTR_X_MASK_REG */ +#define I2C_WRITE_INTR_I2C_EC_MASK(sourceMask) \ + do{ \ + I2C_INTR_I2C_EC_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#if (!I2C_CY_SCBIP_V1) + #define I2C_WRITE_INTR_SPI_EC_MASK(sourceMask) \ + do{ \ + I2C_INTR_SPI_EC_MASK_REG = (uint32) (sourceMask); \ + }while(0) +#endif /* (!I2C_CY_SCBIP_V1) */ + +#define I2C_WRITE_INTR_MASTER_MASK(sourceMask) \ + do{ \ + I2C_INTR_MASTER_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define I2C_WRITE_INTR_SLAVE_MASK(sourceMask) \ + do{ \ + I2C_INTR_SLAVE_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define I2C_WRITE_INTR_TX_MASK(sourceMask) \ + do{ \ + I2C_INTR_TX_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define I2C_WRITE_INTR_RX_MASK(sourceMask) \ + do{ \ + I2C_INTR_RX_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +/* Enable interrupt source: set sourceMask bits in I2C_INTR_X_MASK_REG */ +#define I2C_ENABLE_INTR_I2C_EC(sourceMask) \ + do{ \ + I2C_INTR_I2C_EC_MASK_REG |= (uint32) (sourceMask); \ + }while(0) +#if (!I2C_CY_SCBIP_V1) + #define I2C_ENABLE_INTR_SPI_EC(sourceMask) \ + do{ \ + I2C_INTR_SPI_EC_MASK_REG |= (uint32) (sourceMask); \ + }while(0) +#endif /* (!I2C_CY_SCBIP_V1) */ + +#define I2C_ENABLE_INTR_MASTER(sourceMask) \ + do{ \ + I2C_INTR_MASTER_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define I2C_ENABLE_INTR_SLAVE(sourceMask) \ + do{ \ + I2C_INTR_SLAVE_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define I2C_ENABLE_INTR_TX(sourceMask) \ + do{ \ + I2C_INTR_TX_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define I2C_ENABLE_INTR_RX(sourceMask) \ + do{ \ + I2C_INTR_RX_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +/* Disable interrupt source: clear sourceMask bits in I2C_INTR_X_MASK_REG */ +#define I2C_DISABLE_INTR_I2C_EC(sourceMask) \ + do{ \ + I2C_INTR_I2C_EC_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#if (!I2C_CY_SCBIP_V1) + #define I2C_DISABLE_INTR_SPI_EC(sourceMask) \ + do{ \ + I2C_INTR_SPI_EC_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) +#endif /* (!I2C_CY_SCBIP_V1) */ + +#define I2C_DISABLE_INTR_MASTER(sourceMask) \ + do{ \ + I2C_INTR_MASTER_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define I2C_DISABLE_INTR_SLAVE(sourceMask) \ + do{ \ + I2C_INTR_SLAVE_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define I2C_DISABLE_INTR_TX(sourceMask) \ + do{ \ + I2C_INTR_TX_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define I2C_DISABLE_INTR_RX(sourceMask) \ + do{ \ + I2C_INTR_RX_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +/* Set interrupt sources: write sourceMask bits in I2C_INTR_X_SET_REG */ +#define I2C_SET_INTR_MASTER(sourceMask) \ + do{ \ + I2C_INTR_MASTER_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define I2C_SET_INTR_SLAVE(sourceMask) \ + do{ \ + I2C_INTR_SLAVE_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define I2C_SET_INTR_TX(sourceMask) \ + do{ \ + I2C_INTR_TX_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define I2C_SET_INTR_RX(sourceMask) \ + do{ \ + I2C_INTR_RX_SET_REG = (uint32) (sourceMask); \ + }while(0) + +/* Clear interrupt sources: write sourceMask bits in I2C_INTR_X_REG */ +#define I2C_CLEAR_INTR_I2C_EC(sourceMask) \ + do{ \ + I2C_INTR_I2C_EC_REG = (uint32) (sourceMask); \ + }while(0) + +#if (!I2C_CY_SCBIP_V1) + #define I2C_CLEAR_INTR_SPI_EC(sourceMask) \ + do{ \ + I2C_INTR_SPI_EC_REG = (uint32) (sourceMask); \ + }while(0) +#endif /* (!I2C_CY_SCBIP_V1) */ + +#define I2C_CLEAR_INTR_MASTER(sourceMask) \ + do{ \ + I2C_INTR_MASTER_REG = (uint32) (sourceMask); \ + }while(0) + +#define I2C_CLEAR_INTR_SLAVE(sourceMask) \ + do{ \ + I2C_INTR_SLAVE_REG = (uint32) (sourceMask); \ + }while(0) + +#define I2C_CLEAR_INTR_TX(sourceMask) \ + do{ \ + I2C_INTR_TX_REG = (uint32) (sourceMask); \ + }while(0) + +#define I2C_CLEAR_INTR_RX(sourceMask) \ + do{ \ + I2C_INTR_RX_REG = (uint32) (sourceMask); \ + }while(0) + +/* Return true if sourceMask is set in I2C_INTR_CAUSE_REG */ +#define I2C_CHECK_CAUSE_INTR(sourceMask) (0u != (I2C_INTR_CAUSE_REG & (sourceMask))) + +/* Return true if sourceMask is set in INTR_X_MASKED_REG */ +#define I2C_CHECK_INTR_I2C_EC(sourceMask) (0u != (I2C_INTR_I2C_EC_REG & (sourceMask))) +#if (!I2C_CY_SCBIP_V1) + #define I2C_CHECK_INTR_SPI_EC(sourceMask) (0u != (I2C_INTR_SPI_EC_REG & (sourceMask))) +#endif /* (!I2C_CY_SCBIP_V1) */ +#define I2C_CHECK_INTR_MASTER(sourceMask) (0u != (I2C_INTR_MASTER_REG & (sourceMask))) +#define I2C_CHECK_INTR_SLAVE(sourceMask) (0u != (I2C_INTR_SLAVE_REG & (sourceMask))) +#define I2C_CHECK_INTR_TX(sourceMask) (0u != (I2C_INTR_TX_REG & (sourceMask))) +#define I2C_CHECK_INTR_RX(sourceMask) (0u != (I2C_INTR_RX_REG & (sourceMask))) + +/* Return true if sourceMask is set in I2C_INTR_X_MASKED_REG */ +#define I2C_CHECK_INTR_I2C_EC_MASKED(sourceMask) (0u != (I2C_INTR_I2C_EC_MASKED_REG & \ + (sourceMask))) +#if (!I2C_CY_SCBIP_V1) + #define I2C_CHECK_INTR_SPI_EC_MASKED(sourceMask) (0u != (I2C_INTR_SPI_EC_MASKED_REG & \ + (sourceMask))) +#endif /* (!I2C_CY_SCBIP_V1) */ +#define I2C_CHECK_INTR_MASTER_MASKED(sourceMask) (0u != (I2C_INTR_MASTER_MASKED_REG & \ + (sourceMask))) +#define I2C_CHECK_INTR_SLAVE_MASKED(sourceMask) (0u != (I2C_INTR_SLAVE_MASKED_REG & \ + (sourceMask))) +#define I2C_CHECK_INTR_TX_MASKED(sourceMask) (0u != (I2C_INTR_TX_MASKED_REG & \ + (sourceMask))) +#define I2C_CHECK_INTR_RX_MASKED(sourceMask) (0u != (I2C_INTR_RX_MASKED_REG & \ + (sourceMask))) + +/* Return true if sourceMask is set in I2C_CTRL_REG: generally is used to check enable bit */ +#define I2C_GET_CTRL_ENABLED (0u != (I2C_CTRL_REG & I2C_CTRL_ENABLED)) + +#define I2C_CHECK_SLAVE_AUTO_ADDR_NACK (0u != (I2C_I2C_CTRL_REG & \ + I2C_I2C_CTRL_S_NOT_READY_DATA_NACK)) + + +/*************************************** +* I2C Macro Definitions +***************************************/ + +/* Enable auto ACK/NACK */ +#define I2C_ENABLE_SLAVE_AUTO_ADDR_NACK \ + do{ \ + I2C_I2C_CTRL_REG |= I2C_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define I2C_ENABLE_SLAVE_AUTO_DATA_ACK \ + do{ \ + I2C_I2C_CTRL_REG |= I2C_I2C_CTRL_S_READY_DATA_ACK; \ + }while(0) + +#define I2C_ENABLE_SLAVE_AUTO_DATA_NACK \ + do{ \ + I2C_I2C_CTRL_REG |= I2C_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define I2C_ENABLE_MASTER_AUTO_DATA_ACK \ + do{ \ + I2C_I2C_CTRL_REG |= I2C_I2C_CTRL_M_READY_DATA_ACK; \ + }while(0) + +#define I2C_ENABLE_MASTER_AUTO_DATA_NACK \ + do{ \ + I2C_I2C_CTRL_REG |= I2C_I2C_CTRL_M_NOT_READY_DATA_NACK; \ + }while(0) + +/* Disable auto ACK/NACK */ +#define I2C_DISABLE_SLAVE_AUTO_ADDR_NACK \ + do{ \ + I2C_I2C_CTRL_REG &= ~I2C_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define I2C_DISABLE_SLAVE_AUTO_DATA_ACK \ + do{ \ + I2C_I2C_CTRL_REG &= ~I2C_I2C_CTRL_S_READY_DATA_ACK; \ + }while(0) + +#define I2C_DISABLE_SLAVE_AUTO_DATA_NACK \ + do{ \ + I2C_I2C_CTRL_REG &= ~I2C_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define I2C_DISABLE_MASTER_AUTO_DATA_ACK \ + do{ \ + I2C_I2C_CTRL_REG &= ~I2C_I2C_CTRL_M_READY_DATA_ACK; \ + }while(0) + +#define I2C_DISABLE_MASTER_AUTO_DATA_NACK \ + do{ \ + I2C_I2C_CTRL_REG &= ~I2C_I2C_CTRL_M_NOT_READY_DATA_NACK; \ + }while(0) + +/* Enable Slave autoACK/NACK Data */ +#define I2C_ENABLE_SLAVE_AUTO_DATA \ + do{ \ + I2C_I2C_CTRL_REG |= (I2C_I2C_CTRL_S_READY_DATA_ACK | \ + I2C_I2C_CTRL_S_NOT_READY_DATA_NACK); \ + }while(0) + +/* Disable Slave autoACK/NACK Data */ +#define I2C_DISABLE_SLAVE_AUTO_DATA \ + do{ \ + I2C_I2C_CTRL_REG &= ((uint32) \ + ~(I2C_I2C_CTRL_S_READY_DATA_ACK | \ + I2C_I2C_CTRL_S_NOT_READY_DATA_NACK)); \ + }while(0) + +/* Disable Master autoACK/NACK Data */ +#define I2C_DISABLE_MASTER_AUTO_DATA \ + do{ \ + I2C_I2C_CTRL_REG &= ((uint32) \ + ~(I2C_I2C_CTRL_M_READY_DATA_ACK | \ + I2C_I2C_CTRL_M_NOT_READY_DATA_NACK)); \ + }while(0) +/* Disables auto data ACK/NACK bits */ +#define I2C_DISABLE_AUTO_DATA \ + do{ \ + I2C_I2C_CTRL_REG &= ((uint32) ~(I2C_I2C_CTRL_M_READY_DATA_ACK | \ + I2C_I2C_CTRL_M_NOT_READY_DATA_NACK | \ + I2C_I2C_CTRL_S_READY_DATA_ACK | \ + I2C_I2C_CTRL_S_NOT_READY_DATA_NACK)); \ + }while(0) + +/* Master commands */ +#define I2C_I2C_MASTER_GENERATE_START \ + do{ \ + I2C_I2C_MASTER_CMD_REG = I2C_I2C_MASTER_CMD_M_START_ON_IDLE; \ + }while(0) + +#define I2C_I2C_MASTER_CLEAR_START \ + do{ \ + I2C_I2C_MASTER_CMD_REG = ((uint32) 0u); \ + }while(0) + +#define I2C_I2C_MASTER_GENERATE_RESTART I2C_I2CReStartGeneration() + +#define I2C_I2C_MASTER_GENERATE_STOP \ + do{ \ + I2C_I2C_MASTER_CMD_REG = \ + (I2C_I2C_MASTER_CMD_M_STOP | \ + (I2C_CHECK_I2C_STATUS(I2C_I2C_STATUS_M_READ) ? \ + (I2C_I2C_MASTER_CMD_M_NACK) : (0u))); \ + }while(0) + +#define I2C_I2C_MASTER_GENERATE_ACK \ + do{ \ + I2C_I2C_MASTER_CMD_REG = I2C_I2C_MASTER_CMD_M_ACK; \ + }while(0) + +#define I2C_I2C_MASTER_GENERATE_NACK \ + do{ \ + I2C_I2C_MASTER_CMD_REG = I2C_I2C_MASTER_CMD_M_NACK; \ + }while(0) + +/* Slave commands */ +#define I2C_I2C_SLAVE_GENERATE_ACK \ + do{ \ + I2C_I2C_SLAVE_CMD_REG = I2C_I2C_SLAVE_CMD_S_ACK; \ + }while(0) + +#if (I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) + /* Slave NACK generation for EC_AM logic on address phase. Ticket ID #183902 */ + void I2C_I2CSlaveNackGeneration(void); + #define I2C_I2C_SLAVE_GENERATE_NACK I2C_I2CSlaveNackGeneration() + +#else + #define I2C_I2C_SLAVE_GENERATE_NACK \ + do{ \ + I2C_I2C_SLAVE_CMD_REG = I2C_I2C_SLAVE_CMD_S_NACK; \ + }while(0) +#endif /* (I2C_CY_SCBIP_V0 || I2C_CY_SCBIP_V1) */ + +#define I2C_I2C_SLAVE_CLEAR_NACK \ + do{ \ + I2C_I2C_SLAVE_CMD_REG = 0u; \ + }while(0) + +/* Return 8-bit address. The input address should be 7-bits */ +#define I2C_GET_I2C_8BIT_ADDRESS(addr) (((uint32) ((uint32) (addr) << \ + I2C_I2C_SLAVE_ADDR_POS)) & \ + I2C_I2C_SLAVE_ADDR_MASK) + +#define I2C_GET_I2C_7BIT_ADDRESS(addr) ((uint32) (addr) >> I2C_I2C_SLAVE_ADDR_POS) + +/* Adjust SDA filter Trim settings */ +#define I2C_DEFAULT_I2C_CFG_SDA_FILT_TRIM (0x02u) +#define I2C_EC_AM_I2C_CFG_SDA_FILT_TRIM (0x03u) + +#if (I2C_CY_SCBIP_V0) + #define I2C_SET_I2C_CFG_SDA_FILT_TRIM(sdaTrim) \ + do{ \ + I2C_I2C_CFG_REG = \ + ((I2C_I2C_CFG_REG & (uint32) ~I2C_I2C_CFG_SDA_FILT_TRIM_MASK) | \ + ((uint32) ((uint32) (sdaTrim) < I2C_I2C_FIFO_SIZE) + { + diffCount = I2C_I2C_FIFO_SIZE; + } + else + { + if(0u == diffCount) + { + I2C_DISABLE_MASTER_AUTO_DATA_ACK; + + diffCount = I2C_I2C_FIFO_SIZE; + endTransfer = I2C_I2C_CMPLT_ANY_TRANSFER; + } + } + + for(; (0u != diffCount); diffCount--) + { + I2C_mstrRdBufPtr[I2C_mstrRdBufIndex] = (uint8) + I2C_RX_FIFO_RD_REG; + I2C_mstrRdBufIndex++; + } + } + /* INTR_RX_NOT_EMPTY: + * RX direction: the master received one data byte, ACK or NACK it. + * The last byte is stored and NACKed by the master. The NACK and Stop is + * generated by one command generate Stop. + */ + else if(I2C_CHECK_INTR_RX_MASKED(I2C_INTR_RX_NOT_EMPTY)) + { + /* Put data in component buffer */ + I2C_mstrRdBufPtr[I2C_mstrRdBufIndex] = (uint8) I2C_RX_FIFO_RD_REG; + I2C_mstrRdBufIndex++; + + if(I2C_mstrRdBufIndex < I2C_mstrRdBufSize) + { + I2C_I2C_MASTER_GENERATE_ACK; + } + else + { + endTransfer = I2C_I2C_CMPLT_ANY_TRANSFER; + } + } + else + { + /* Do nothing */ + } + + I2C_ClearRxInterruptSource(I2C_INTR_RX_ALL); + } + else /* Writing */ + { + /* INTR_MASTER_I2C_NACK : + * The master writes data to the slave and NACK was received: not all the bytes were + * written to the slave from the TX FIFO. Revert the index if there is data in + * the TX FIFO and pass control to a complete transfer. + */ + if(I2C_CHECK_INTR_MASTER_MASKED(I2C_INTR_MASTER_I2C_NACK)) + { + I2C_ClearMasterInterruptSource(I2C_INTR_MASTER_I2C_NACK); + + /* Rollback write buffer index: NACKed byte remains in shifter */ + I2C_mstrWrBufIndexTmp -= (I2C_GET_TX_FIFO_ENTRIES + + I2C_GET_TX_FIFO_SR_VALID); + + /* Update number of transferred bytes */ + I2C_mstrWrBufIndex = I2C_mstrWrBufIndexTmp; + + I2C_mstrStatus |= (uint16) (I2C_I2C_MSTAT_ERR_XFER | + I2C_I2C_MSTAT_ERR_SHORT_XFER); + + I2C_CLEAR_TX_FIFO; + + endTransfer = I2C_I2C_CMPLT_ANY_TRANSFER; + } + /* INTR_TX_EMPTY : + * TX direction: the TX FIFO is EMPTY, the data from the buffer needs to be put there. + * When there is no data in the component buffer, the underflow interrupt is + * enabled to catch when all the data has been transferred. + */ + else if(I2C_CHECK_INTR_TX_MASKED(I2C_INTR_TX_EMPTY)) + { + while(I2C_I2C_FIFO_SIZE != I2C_GET_TX_FIFO_ENTRIES) + { + /* The temporary mstrWrBufIndexTmp is used because slave could NACK the byte and index + * roll-back required in this case. The mstrWrBufIndex is updated at the end of transfer. + */ + if(I2C_mstrWrBufIndexTmp < I2C_mstrWrBufSize) + { + #if(!I2C_CY_SCBIP_V0) + /* Clear INTR_TX.UNDERFLOW before putting the last byte into TX FIFO. This ensures + * a proper trigger at the end of transaction when INTR_TX.UNDERFLOW single trigger + * event. Ticket ID# 156735. + */ + if(I2C_mstrWrBufIndexTmp == (I2C_mstrWrBufSize - 1u)) + { + I2C_ClearTxInterruptSource(I2C_INTR_TX_UNDERFLOW); + I2C_SetTxInterruptMode(I2C_INTR_TX_UNDERFLOW); + } + #endif /* (!I2C_CY_SCBIP_V0) */ + + /* Put data into TX FIFO */ + I2C_TX_FIFO_WR_REG = (uint32) I2C_mstrWrBufPtr[I2C_mstrWrBufIndexTmp]; + I2C_mstrWrBufIndexTmp++; + } + else + { + break; /* No more data to put */ + } + } + + #if(I2C_CY_SCBIP_V0) + if(I2C_mstrWrBufIndexTmp == I2C_mstrWrBufSize) + { + I2C_SetTxInterruptMode(I2C_INTR_TX_UNDERFLOW); + } + + I2C_ClearTxInterruptSource(I2C_INTR_TX_ALL); + #else + I2C_ClearTxInterruptSource(I2C_INTR_TX_EMPTY); + #endif /* (I2C_CY_SCBIP_V0) */ + } + /* INTR_TX_UNDERFLOW: + * TX direction: all data from the TX FIFO was transferred to the slave. + * The transaction needs to be completed. + */ + else if(I2C_CHECK_INTR_TX_MASKED(I2C_INTR_TX_UNDERFLOW)) + { + /* Update number of transferred bytes */ + I2C_mstrWrBufIndex = I2C_mstrWrBufIndexTmp; + + endTransfer = I2C_I2C_CMPLT_ANY_TRANSFER; + } + else + { + /* Do nothing */ + } + } + } + + if(0u != endTransfer) /* Complete transfer */ + { + /* Clean-up master after reading: only in case of NACK */ + I2C_DISABLE_MASTER_AUTO_DATA_ACK; + + /* Disable data processing interrupts: they have to be cleared before */ + I2C_SetRxInterruptMode(I2C_NO_INTR_SOURCES); + I2C_SetTxInterruptMode(I2C_NO_INTR_SOURCES); + + if(I2C_CHECK_I2C_MODE_NO_STOP(I2C_mstrControl)) + { + /* On-going transaction is suspended: the ReStart is generated by the API request */ + I2C_mstrStatus |= (uint16) (I2C_I2C_MSTAT_XFER_HALT | + I2C_GET_I2C_MSTAT_CMPLT); + + I2C_state = I2C_I2C_FSM_MSTR_HALT; + } + else + { + /* Complete transaction: exclude the data processing state and generate Stop. + * The completion status will be set after Stop generation. + * A special case is read: because NACK and Stop are generated by the command below. + * Lost arbitration can occur during NACK generation when + * the other master is still reading from the slave. + */ + I2C_I2C_MASTER_GENERATE_STOP; + } + } + } + + } /* (I2C_I2C_MASTER) */ + #endif + + } /* (I2C_CHECK_I2C_FSM_MASTER) */ + + /* FSM EXIT: + * Slave: INTR_SLAVE_I2C_BUS_ERROR, INTR_SLAVE_I2C_ARB_LOST + * Master: INTR_MASTER_I2C_BUS_ERROR, INTR_MASTER_I2C_ARB_LOST. + */ + else + { + I2C_I2CFwBlockReset(); + + } + +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/I2C_I2C_MASTER.c b/cores/asr650x/cores/I2C_I2C_MASTER.c new file mode 100644 index 00000000..3100eda8 --- /dev/null +++ b/cores/asr650x/cores/I2C_I2C_MASTER.c @@ -0,0 +1,1072 @@ +/***************************************************************************//** +* \file I2C_I2C_MASTER.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component in +* I2C Master mode. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "I2C_PVT.h" +#include "I2C_I2C_PVT.h" + +#if(I2C_I2C_MASTER_CONST) + +/*************************************** +* I2C Master Private Vars +***************************************/ + +/* Master variables */ +volatile uint16 I2C_mstrStatus; /* Master Status byte */ +volatile uint8 I2C_mstrControl; /* Master Control byte */ + +/* Receive buffer variables */ +volatile uint8 * I2C_mstrRdBufPtr; /* Pointer to Master Read buffer */ +volatile uint32 I2C_mstrRdBufSize; /* Master Read buffer size */ +volatile uint32 I2C_mstrRdBufIndex; /* Master Read buffer Index */ + +/* Transmit buffer variables */ +volatile uint8 * I2C_mstrWrBufPtr; /* Pointer to Master Write buffer */ +volatile uint32 I2C_mstrWrBufSize; /* Master Write buffer size */ +volatile uint32 I2C_mstrWrBufIndex; /* Master Write buffer Index */ +volatile uint32 I2C_mstrWrBufIndexTmp; /* Master Write buffer Index Tmp */ + +#if (!I2C_CY_SCBIP_V0 && \ + I2C_I2C_MULTI_MASTER_SLAVE_CONST && I2C_I2C_WAKE_ENABLE_CONST) + static void I2C_I2CMasterDisableEcAm(void); +#else + #define I2C_I2CMasterDisableEcAm() do{ /* Empty */ }while(0) +#endif /* (!I2C_CY_SCBIP_V0) */ + +static uint32 I2C_I2CMasterHandleStatus(uint32 status); +static uint32 I2C_I2CMasterWaitOneUnit(uint32 *timeout); + + +/******************************************************************************* +* Function Name: I2C_I2CMasterWriteBuf +****************************************************************************//** +* +* Automatically writes an entire buffer of data to a slave device. +* Once the data transfer is initiated by this function, further data transfer +* is handled by the included ISR. +* Enables the I2C interrupt and clears I2C_I2C_MSTAT_WR_CMPLT +* status. +* +* \param slaveAddr: 7-bit slave address. +* \param xferData: Pointer to buffer of data to be sent. +* \param cnt: Size of buffer to send. +* \param mode: Transfer mode defines: +* (1) Whether a start or restart condition is generated at the beginning +* of the transfer, and +* (2) Whether the transfer is completed or halted before the stop +* condition is generated on the bus.Transfer mode, mode constants +* may be ORed together. +* - I2C_I2C_MODE_COMPLETE_XFER - Perform complete transfer +* from Start to Stop. +* - I2C_I2C_MODE_REPEAT_START - Send Repeat Start instead +* of Start. A Stop is generated after transfer is completed unless +* NO_STOP is specified. +* - I2C_I2C_MODE_NO_STOP Execute transfer without a Stop. +* The following transfer expected to perform ReStart. +* +* \return +* Error status. +* - I2C_I2C_MSTR_NO_ERROR - Function complete without error. +* The master started the transfer. +* - I2C_I2C_MSTR_BUS_BUSY - Bus is busy. Nothing was sent on +* the bus. The attempt has to be retried. +* - I2C_I2C_MSTR_NOT_READY - Master is not ready for to start +* transfer. A master still has not completed previous transaction or a +* slave operation is in progress (in multi-master-slave configuration). +* Nothing was sent on the bus. The attempt has to be retried. +* +* \globalvars +* I2C_mstrStatus - used to store current status of I2C Master. +* I2C_state - used to store current state of software FSM. +* I2C_mstrControl - used to control master end of transaction with +* or without the Stop generation. +* I2C_mstrWrBufPtr - used to store pointer to master write buffer. +* I2C_mstrWrBufIndex - used to current index within master write +* buffer. +* I2C_mstrWrBufSize - used to store master write buffer size. +* +*******************************************************************************/ +uint32 I2C_I2CMasterWriteBuf(uint32 slaveAddress, uint8 * wrData, uint32 cnt, uint32 mode) +{ + uint32 errStatus; + + errStatus = I2C_I2C_MSTR_NOT_READY; + + if(NULL != wrData) /* Check buffer pointer */ + { + /* Check FSM state and bus before generating Start/ReStart condition */ + if(I2C_CHECK_I2C_FSM_IDLE) + { + I2C_DisableInt(); /* Lock from interruption */ + + /* Check bus state */ + errStatus = I2C_CHECK_I2C_STATUS(I2C_I2C_STATUS_BUS_BUSY) ? + I2C_I2C_MSTR_BUS_BUSY : I2C_I2C_MSTR_NO_ERROR; + } + else if(I2C_CHECK_I2C_FSM_HALT) + { + I2C_mstrStatus &= (uint16) ~I2C_I2C_MSTAT_XFER_HALT; + errStatus = I2C_I2C_MSTR_NO_ERROR; + } + else + { + /* Unexpected FSM state: exit */ + } + } + + /* Check if master is ready to start */ + if(I2C_I2C_MSTR_NO_ERROR == errStatus) /* No error proceed */ + { + /* Non-empty for master-slave mode when wakeup enabled */ + I2C_I2CMasterDisableEcAm(); + + /* Set up write transaction */ + I2C_state = I2C_I2C_FSM_MSTR_WR_ADDR; + I2C_mstrWrBufIndexTmp = 0u; + I2C_mstrWrBufIndex = 0u; + I2C_mstrWrBufSize = cnt; + I2C_mstrWrBufPtr = (volatile uint8 *) wrData; + I2C_mstrControl = (uint8) mode; + + slaveAddress = I2C_GET_I2C_8BIT_ADDRESS(slaveAddress); + + I2C_mstrStatus &= (uint16) ~I2C_I2C_MSTAT_WR_CMPLT; + + I2C_ClearTxInterruptSource (I2C_INTR_TX_UNDERFLOW); + I2C_ClearMasterInterruptSource(I2C_INTR_MASTER_ALL); + I2C_SetMasterInterruptMode (I2C_I2C_INTR_MASTER_MASK); + + /* The TX and RX FIFO have to be EMPTY */ + + /* Enable interrupt source to catch when address is sent */ + I2C_SetTxInterruptMode(I2C_INTR_TX_UNDERFLOW); + + /* Generate Start or ReStart */ + if(I2C_CHECK_I2C_MODE_RESTART(mode)) + { + I2C_I2C_MASTER_GENERATE_RESTART; + I2C_TX_FIFO_WR_REG = slaveAddress; + } + else + { + I2C_TX_FIFO_WR_REG = slaveAddress; + I2C_I2C_MASTER_GENERATE_START; + } + } + + I2C_EnableInt(); /* Release lock */ + + return(errStatus); +} + + +/******************************************************************************* +* Function Name: I2C_I2CMasterReadBuf +****************************************************************************//** +* +* Automatically reads an entire buffer of data from a slave device. +* Once the data transfer is initiated by this function, further data transfer +* is handled by the included ISR. +* Enables the I2C interrupt and clears I2C_I2C_MSTAT_RD_CMPLT +* status. +* +* \param slaveAddr: 7-bit slave address. +* \param xferData: Pointer to buffer of data to be sent. +* \param cnt: Size of buffer to send. +* \param mode: Transfer mode defines: +* (1) Whether a start or restart condition is generated at the beginning +* of the transfer, and +* (2) Whether the transfer is completed or halted before the stop +* condition is generated on the bus.Transfer mode, mode constants may +* be ORed together. See I2C_I2CMasterWriteBuf() +* function for constants. +* +* \return +* Error status.See I2C_I2CMasterWriteBuf() +* function for constants. +* +* \globalvars +* I2C_mstrStatus - used to store current status of I2C Master. +* I2C_state - used to store current state of software FSM. +* I2C_mstrControl - used to control master end of transaction with +* or without the Stop generation. +* I2C_mstrRdBufPtr - used to store pointer to master read buffer. +* I2C_mstrRdBufIndex - used to current index within master read +* buffer. +* I2C_mstrRdBufSize - used to store master read buffer size. +* +*******************************************************************************/ +uint32 I2C_I2CMasterReadBuf(uint32 slaveAddress, uint8 * rdData, uint32 cnt, uint32 mode) +{ + uint32 errStatus; + + errStatus = I2C_I2C_MSTR_NOT_READY; + + if(NULL != rdData) + { + /* Check FSM state and bus before generating Start/ReStart condition */ + if(I2C_CHECK_I2C_FSM_IDLE) + { + I2C_DisableInt(); /* Lock from interruption */ + + /* Check bus state */ + errStatus = I2C_CHECK_I2C_STATUS(I2C_I2C_STATUS_BUS_BUSY) ? + I2C_I2C_MSTR_BUS_BUSY : I2C_I2C_MSTR_NO_ERROR; + } + else if(I2C_CHECK_I2C_FSM_HALT) + { + I2C_mstrStatus &= (uint16) ~I2C_I2C_MSTAT_XFER_HALT; + errStatus = I2C_I2C_MSTR_NO_ERROR; + } + else + { + /* Unexpected FSM state: exit */ + } + } + + /* Check master ready to proceed */ + if(I2C_I2C_MSTR_NO_ERROR == errStatus) /* No error proceed */ + { + /* Non-empty for master-slave mode when wakeup enabled */ + I2C_I2CMasterDisableEcAm(); + + /* Set up read transaction */ + I2C_state = I2C_I2C_FSM_MSTR_RD_ADDR; + I2C_mstrRdBufIndex = 0u; + I2C_mstrRdBufSize = cnt; + I2C_mstrRdBufPtr = (volatile uint8 *) rdData; + I2C_mstrControl = (uint8) mode; + + slaveAddress = (I2C_GET_I2C_8BIT_ADDRESS(slaveAddress) | I2C_I2C_READ_FLAG); + + I2C_mstrStatus &= (uint16) ~I2C_I2C_MSTAT_RD_CMPLT; + + I2C_ClearMasterInterruptSource(I2C_INTR_MASTER_ALL); + I2C_SetMasterInterruptMode (I2C_I2C_INTR_MASTER_MASK); + + /* TX and RX FIFO have to be EMPTY */ + + /* Prepare reading */ + if(I2C_mstrRdBufSize < I2C_I2C_FIFO_SIZE) + { + /* Reading byte-by-byte */ + I2C_SetRxInterruptMode(I2C_INTR_RX_NOT_EMPTY); + } + else + { + /* Receive RX FIFO chunks */ + I2C_ENABLE_MASTER_AUTO_DATA_ACK; + I2C_SetRxInterruptMode(I2C_INTR_RX_FULL); + } + + /* Generate Start or ReStart */ + if(I2C_CHECK_I2C_MODE_RESTART(mode)) + { + I2C_I2C_MASTER_GENERATE_RESTART; + I2C_TX_FIFO_WR_REG = slaveAddress; + } + else + { + I2C_TX_FIFO_WR_REG = slaveAddress; + I2C_I2C_MASTER_GENERATE_START; + } + } + + I2C_EnableInt(); /* Release lock */ + + return(errStatus); +} + + +/******************************************************************************* +* Function Name: I2C_I2CMasterSendStart +****************************************************************************//** +* +* Generates Start condition and sends slave address with read/write bit. +* Disables the I2C interrupt. +* This function is blocking and does not return until start condition and +* address byte are sent and ACK/NACK response is received or errors occurred. +* +* \param slaveAddress +* Right justified 7-bit Slave address (valid range 8 to 120). +* +* \param bitRnW +* Direction of the following transfer. It is defined by read/write bit within +* address byte. +* - I2C_I2C_WRITE_XFER_MODE - Set write direction for the +* following transfer. +* - I2C_I2C_READ_XFER_MODE - Set read direction for the +* following transfer. +* +* \param timeoutMs +* Defines in milliseconds the time that this function can block for. +* If that time expires, the function returns. If a zero is passed, +* the function waits forever for the action to complete. If a timeout occurs, +* the SCB block is reset. Note The maximum value is (maximum uint32)/1000. +* +* \return +* Error status. +* - I2C_I2C_MSTR_NO_ERROR - Function complete without error. +* - I2C_I2C_MSTR_BUS_BUSY - Bus is busy. +* Nothing was sent on the bus. The attempt has to be retried. +* - I2C_I2C_MSTR_NOT_READY - Master is not ready for to +* start transfer. +* A master still has not completed previous transaction or a slave +* operation is in progress (in multi-master-slave configuration). +* Nothing was sent on the bus. The attempt has to be retried. +* - I2C_I2C_MSTR_ERR_LB_NAK - Error condition: Last byte was +* NAKed. +* - I2C_I2C_MSTR_ERR_ARB_LOST - Error condition: Master lost +* arbitration. +* - I2C_I2C_MSTR_ERR_BUS_ERR - Error condition: Master +* encountered a bus error. Bus error is misplaced start or stop detection. +* - I2C_I2C_MSTR_ERR_ABORT_START - Error condition: The start +* condition generation was aborted due to beginning of Slave operation. +* This error condition is only applicable for Multi-Master-Slave mode. +* +* \globalvars +* I2C_state - used to store current state of software FSM. +* +*******************************************************************************/ +uint32 I2C_I2CMasterSendStart(uint32 slaveAddress, uint32 bitRnW, uint32 timeoutMs) +{ + uint32 errStatus = I2C_I2C_MSTR_NOT_READY; + + if(I2C_CHECK_I2C_FSM_IDLE) + { + I2C_DisableInt(); /* Lock from interruption */ + + if(I2C_CHECK_I2C_STATUS(I2C_I2C_STATUS_BUS_BUSY)) + { + errStatus = I2C_I2C_MSTR_BUS_BUSY; + } + else + { + uint32 locStatus; + uint32 timeout = I2C_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs); + + /* Non-empty for master-slave mode when wakeup enabled */ + I2C_I2CMasterDisableEcAm(); + + /* Clean up the hardware before a transaction. */ + I2C_SetMasterInterruptMode (I2C_NO_INTR_SOURCES); + I2C_ClearMasterInterruptSource(I2C_INTR_MASTER_ALL); + I2C_ClearRxInterruptSource (I2C_INTR_RX_ALL); + + slaveAddress = I2C_GET_I2C_8BIT_ADDRESS(slaveAddress); + + if(0u == bitRnW) /* Write direction */ + { + I2C_state = I2C_I2C_FSM_MSTR_WR_DATA; + } + else /* Read direction */ + { + I2C_state = I2C_I2C_FSM_MSTR_RD_DATA; + slaveAddress |= I2C_I2C_READ_FLAG; + } + + /* TX and RX FIFO have to be empty at here */ + + /* Generate Start and send address */ + I2C_TX_FIFO_WR_REG = slaveAddress; + I2C_I2C_MASTER_GENERATE_START; + + /* Wait until address has been transferred. Note that for master reads at least one byte. */ + do + { + locStatus = I2C_GetMasterInterruptSource() & I2C_INTR_MASTER_SEND_BYTE; + locStatus |= I2C_GetSlaveInterruptSource() & I2C_SLAVE_INTR_I2C_ADDR; + locStatus |= I2C_I2CMasterWaitOneUnit(&timeout); + } + while (0u == locStatus); + + /* Handle completion event and convert to status */ + errStatus = I2C_I2CMasterHandleStatus(locStatus); + } + + I2C_EnableInt(); /* Release lock */ + } + + return(errStatus); +} + + +/******************************************************************************* +* Function Name: I2C_I2CMasterSendRestart +****************************************************************************//** +* +* Generates Restart condition and sends slave address with read/write bit. +* This function is blocking and does not return until start condition and +* address are sent and ACK/NACK response is received or errors occurred. +* +* \param slaveAddress +* Right justified 7-bit Slave address (valid range 8 to 120). +* +* \param bitRnW +* Direction of the following transfer. It is defined by read/write bit within +* address byte.See I2C_I2CMasterSendStart() function for constants. +* +* \param timeoutMs +* Defines in milliseconds the time that this function can block for. +* If that time expires, the function returns. If a zero is passed, +* the function waits forever for the action to complete. If a timeout occurs, +* the SCB block is reset. Note The maximum value is (maximum uint32)/1000. +* +* \return +* Error status. +* See I2C_I2CMasterSendStart() function for constants. +* +* \sideeffect +* A valid Start or ReStart condition must be generated before calling +* this function. This function does nothing if Start or ReStart conditions +* failed before this function was called. +* For read transaction, at least one byte has to be read before ReStart +* generation. +* +* \globalvars +* I2C_state - used to store current state of software FSM. +* +*******************************************************************************/ +uint32 I2C_I2CMasterSendRestart(uint32 slaveAddress, uint32 bitRnW, uint32 timeoutMs) +{ + uint32 errStatus = I2C_I2C_MSTR_NOT_READY; + + /* Check FSM state before generating ReStart condition */ + if(I2C_CHECK_I2C_MASTER_ACTIVE) + { + uint32 locStatus; + uint32 timeout = I2C_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs); + + slaveAddress = I2C_GET_I2C_8BIT_ADDRESS(slaveAddress); + + if(0u == bitRnW) /* Write direction */ + { + I2C_state = I2C_I2C_FSM_MSTR_WR_DATA; + } + else /* Read direction */ + { + I2C_state = I2C_I2C_FSM_MSTR_RD_DATA; + slaveAddress |= I2C_I2C_READ_FLAG; + } + + /* TX and RX FIFO have to be empty at here */ + + /* A proper ReStart sequence is: set command to generate ReStart, then put an address byte in the TX FIFO. + * Put address into the TX FIFO the 1st makes scb IP think that this data byte for current write transaction. + */ + I2C_I2C_MASTER_GENERATE_RESTART; + I2C_TX_FIFO_WR_REG = slaveAddress; + + /* Wait until address has been transferred. Note that for master reads at least one byte. */ + do + { + locStatus = I2C_GetMasterInterruptSource() & I2C_INTR_MASTER_SEND_BYTE; + locStatus |= I2C_I2CMasterWaitOneUnit(&timeout); + } + while (0u == locStatus); + + + /* Handle completion event and convert to status */ + errStatus = I2C_I2CMasterHandleStatus(locStatus); + } + + return(errStatus); +} + + +/******************************************************************************* +* Function Name: I2C_I2CMasterSendStop +****************************************************************************//** +* +* Generates Stop condition on the bus. +* The NAK is generated before Stop in case of a read transaction. +* At least one byte has to be read if a Start or ReStart condition with read +* direction was generated before. +* This function is blocking and does not return until a Stop condition is +* generated or error occurred. +* +* \param timeoutMs +* Defines in milliseconds the time that this function can block for. +* If that time expires, the function returns. If a zero is passed, +* the function waits forever for the action to complete. If a timeout occurs, +* the SCB block is reset. Note The maximum value is (maximum uint32)/1000. +* +* \return +* Error status. +* See I2C_I2CMasterSendStart() function for constants. +* +* \sideeffect +* A valid Start or ReStart condition must be generated before calling +* this function. This function does nothing if Start or ReStart conditions +* failed before this function was called. +* For read transaction, at least one byte has to be read before ReStart +* generation. +* +* \globalvars +* I2C_state - used to store current state of software FSM. +* +*******************************************************************************/ +uint32 I2C_I2CMasterSendStop(uint32 timeoutMs) +{ + uint32 errStatus = I2C_I2C_MSTR_NOT_READY; + + /* Check FSM state before generating Stop condition */ + if(I2C_CHECK_I2C_MASTER_ACTIVE) + { + uint32 locStatus; + uint32 timeout = I2C_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs); + + /* Write direction: generates Stop; Read direction: generates NACK and Stop; */ + I2C_I2C_MASTER_GENERATE_STOP; + + /* Wait for a completion event from the master */ + do + { + locStatus = I2C_GetMasterInterruptSource() & I2C_INTR_MASTER_SEND_STOP; + locStatus |= I2C_I2CMasterWaitOneUnit(&timeout); + } + while (0u == locStatus); + + /* Handle completion event and convert to status */ + errStatus = I2C_I2CMasterHandleStatus(locStatus); + } + + return(errStatus); +} + + +/******************************************************************************* +* Function Name: I2C_I2CMasterWriteByte +****************************************************************************//** +* +* Sends one byte to a slave. +* This function is blocking and does not return until byte is transmitted +* or error occurred. +* +* \param wrByte +* The data byte to send to the slave. +* +* \param timeoutMs +* Defines in milliseconds the time that this function can block for. +* If that time expires, the function returns. If a zero is passed, +* the function waits forever for the action to complete. If a timeout occurs, +* the SCB block is reset. Note The maximum value is (maximum uint32)/1000. +* +* \return +* Error status. +* See I2C_I2CMasterSendStart() function for constants. +* +* \sideeffect +* A valid Start or ReStart condition must be generated before calling +* this function. This function does nothing if Start or ReStart condition +* failed before this function was called. +* +* \globalvars +* I2C_state - used to store current state of software FSM. +* +*******************************************************************************/ +uint32 I2C_I2CMasterWriteByte(uint32 wrByte, uint32 timeoutMs) +{ + uint32 errStatus = I2C_I2C_MSTR_NOT_READY; + + /* Check FSM state before write byte */ + if(I2C_CHECK_I2C_MASTER_ACTIVE) + { + uint32 locStatus; + uint32 timeout = I2C_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs); + + I2C_TX_FIFO_WR_REG = wrByte; + + /* Wait for a completion event from the master */ + do + { + locStatus = I2C_GetMasterInterruptSource() & I2C_INTR_MASTER_SEND_BYTE; + locStatus |= I2C_I2CMasterWaitOneUnit(&timeout); + } + while (0u == locStatus); + + /* Handle completion event and convert to status */ + errStatus = I2C_I2CMasterHandleStatus(locStatus); + } + + return(errStatus); +} + + + +/******************************************************************************* +* Function Name: I2C_I2CMasterReadByte +****************************************************************************//** +* +* Reads one byte from a slave and generates ACK or prepares to generate NAK. +* The NAK will be generated before Stop or ReStart condition by +* I2C_I2CMasterSendStop() or +* I2C_I2CMasterSendRestart() function appropriately. +* This function is blocking. It does not return until a byte is received or +* an error occurs. +* +* \param ackNack +* Response to received byte. +* - I2C_I2C_ACK_DATA - Generates ACK. +* The master notifies slave that transfer continues. +* - I2C_I2C_NAK_DATA - Prepares to generate NAK. +* The master will notify slave that transfer is completed. +* +* \param rdByte +* The pointer to the location to store the data byte that was read from +* the slave. +* Note that the byte should be ignored if error status is returned. +* +* \param timeoutMs +* Defines in milliseconds the time that this function can block for. +* If that time expires, the function returns. If a zero is passed, +* the function waits forever for the action to complete. If a timeout occurs, +* the SCB block is reset. Note The maximum value is (maximum uint32)/1000. +* +* \return +* Error status. +* See I2C_I2CMasterSendStart() function for constants. +* +* \sideeffect +* A valid Start or ReStart condition must be generated before calling +* this function. This function does nothing if Start or ReStart condition +* failed before this function was called. +* +* \globalvars +* I2C_state - used to store current state of software FSM. +* +*******************************************************************************/ +uint32 I2C_I2CMasterReadByte(uint32 ackNack, uint8 *rdByte, uint32 timeoutMs) +{ + uint32 errStatus = I2C_I2C_MSTR_NOT_READY; + + /* Check FSM state before read byte */ + if(I2C_CHECK_I2C_MASTER_ACTIVE) + { + uint32 locStatus; + uint32 rxNotEmpty; + uint32 timeout = I2C_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs); + + /* Wait for a completion event from the master */ + do + { + locStatus = I2C_GetMasterInterruptSource() & I2C_INTR_MASTER_RECEIVE_BYTE; + rxNotEmpty = I2C_GetRxInterruptSource() & I2C_INTR_RX_NOT_EMPTY; + locStatus |= I2C_I2CMasterWaitOneUnit(&timeout); + } + while ((0u == locStatus) && (0u == rxNotEmpty)); + + /* Get byte from RX FIFO */ + if (0u != rxNotEmpty) + { + *rdByte = (uint8)I2C_RX_FIFO_RD_REG; + I2C_ClearRxInterruptSource(I2C_INTR_RX_ALL); + } + + /* Handle completion event and convert to status */ + errStatus = I2C_I2CMasterHandleStatus(locStatus); + + if (I2C_I2C_MSTR_NO_ERROR == errStatus) + { + if(I2C_I2C_ACK_DATA == ackNack) + { + I2C_I2C_MASTER_GENERATE_ACK; + } + else + { + /* NACK is generated by Stop or ReStart command */ + } + } + } + + return(errStatus); +} + + +/******************************************************************************* +* Function Name: I2C_I2CMasterGetReadBufSize +****************************************************************************//** +* +* Returns the number of bytes that has been transferred with an +* I2C_I2CMasterReadBuf() function. +* +* \return +* Byte count of transfer. If the transfer is not yet complete, it returns +* the byte count transferred so far. +* +* \sideeffect +* This function returns not valid value if +* I2C_I2C_MSTAT_ERR_ARB_LOST or +* I2C_I2C_MSTAT_ERR_BUS_ERROR occurred while read transfer. +* +* \globalvars +* I2C_mstrRdBufIndex - used to current index within master read +* buffer. +* +*******************************************************************************/ +uint32 I2C_I2CMasterGetReadBufSize(void) +{ + return(I2C_mstrRdBufIndex); +} + + +/******************************************************************************* +* Function Name: I2C_I2CMasterGetWriteBufSize +****************************************************************************//** +* +* Returns the number of bytes that have been transferred with an +* SCB_I2CMasterWriteBuf() function. +* +* \return +* Byte count of transfer. If the transfer is not yet complete, it returns +* zero unit transfer completion. +* +* \sideeffect +* This function returns not valid value if +* I2C_I2C_MSTAT_ERR_ARB_LOST or +* I2C_I2C_MSTAT_ERR_BUS_ERROR occurred while read transfer. +* +* \globalvars +* I2C_mstrWrBufIndex - used to current index within master write +* buffer. +* +*******************************************************************************/ +uint32 I2C_I2CMasterGetWriteBufSize(void) +{ + return(I2C_mstrWrBufIndex); +} + + +/******************************************************************************* +* Function Name: I2C_I2CMasterClearReadBuf +****************************************************************************//** +* +* Resets the read buffer pointer back to the first byte in the buffer. +* +* \globalvars +* I2C_mstrRdBufIndex - used to current index within master read +* buffer. +* I2C_mstrStatus - used to store current status of I2C Master. +* +*******************************************************************************/ +void I2C_I2CMasterClearReadBuf(void) +{ + I2C_DisableInt(); /* Lock from interruption */ + + I2C_mstrRdBufIndex = 0u; + I2C_mstrStatus &= (uint16) ~I2C_I2C_MSTAT_RD_CMPLT; + + I2C_EnableInt(); /* Release lock */ +} + + +/******************************************************************************* +* Function Name: I2C_I2CMasterClearWriteBuf +****************************************************************************//** +* +* Resets the write buffer pointer back to the first byte in the buffer. +* +* \globalvars +* I2C_mstrRdBufIndex - used to current index within master read +* buffer. +* I2C_mstrStatus - used to store current status of I2C Master. +* +*******************************************************************************/ +void I2C_I2CMasterClearWriteBuf(void) +{ + I2C_DisableInt(); /* Lock from interruption */ + + I2C_mstrWrBufIndex = 0u; + I2C_mstrStatus &= (uint16) ~I2C_I2C_MSTAT_WR_CMPLT; + + I2C_EnableInt(); /* Release lock */ +} + + +/******************************************************************************* +* Function Name: I2C_I2CMasterStatus +****************************************************************************//** +* +* Returns the master's communication status. +* +* \return +* Current status of I2C master. This status incorporates status constants. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the status of the read or write transfer. +* - I2C_I2C_MSTAT_RD_CMPLT - Read transfer complete. +* The error condition status bits must be checked to ensure that +* read transfer was completed successfully. +* - I2C_I2C_MSTAT_WR_CMPLT - Write transfer complete. +* The error condition status bits must be checked to ensure that write +* transfer was completed successfully. +* - I2C_I2C_MSTAT_XFER_INP - Transfer in progress. +* - I2C_I2C_MSTAT_XFER_HALT - Transfer has been halted. +* The I2C bus is waiting for ReStart or Stop condition generation. +* - I2C_I2C_MSTAT_ERR_SHORT_XFER - Error condition: Write +* transfer completed before all bytes were transferred. The slave NAKed +* the byte which was expected to be ACKed. +* - I2C_I2C_MSTAT_ERR_ADDR_NAK - Error condition: Slave did +* not acknowledge address. +* - I2C_I2C_MSTAT_ERR_ARB_LOST - Error condition: Master lost +* arbitration during communications with slave. +* - I2C_I2C_MSTAT_ERR_BUS_ERROR - Error condition: bus error +* occurred during master transfer due to misplaced Start or Stop +* condition on the bus. +* - I2C_I2C_MSTAT_ERR_ABORT_XFER - Error condition: Slave was +* addressed by another master while master performed the start condition +* generation. As a result, master has automatically switched to slave +* mode and is responding. The master transaction has not taken place +* This error condition only applicable for Multi-Master-Slave mode. +* - I2C_I2C_MSTAT_ERR_XFER - Error condition: This is the +* ORed value of all error conditions provided above. +* +* \globalvars +* I2C_mstrStatus - used to store current status of I2C Master. +* +*******************************************************************************/ +uint32 I2C_I2CMasterStatus(void) +{ + uint32 status; + + I2C_DisableInt(); /* Lock from interruption */ + + status = (uint32) I2C_mstrStatus; + + if (I2C_CHECK_I2C_MASTER_ACTIVE) + { + /* Add status of master pending transaction: MSTAT_XFER_INP */ + status |= (uint32) I2C_I2C_MSTAT_XFER_INP; + } + + I2C_EnableInt(); /* Release lock */ + + return(status); +} + + +/******************************************************************************* +* Function Name: I2C_I2CMasterClearStatus +****************************************************************************//** +* +* Clears all status flags and returns the master status. +* +* \return +* Current status of master. See the I2C_I2CMasterStatus() +* function for constants. +* +* \globalvars +* I2C_mstrStatus - used to store current status of I2C Master. +* +*******************************************************************************/ +uint32 I2C_I2CMasterClearStatus(void) +{ + uint32 status; + + I2C_DisableInt(); /* Lock from interruption */ + + /* Read and clear master status */ + status = (uint32) I2C_mstrStatus; + I2C_mstrStatus = I2C_I2C_MSTAT_CLEAR; + + I2C_EnableInt(); /* Release lock */ + + return(status); +} + + +/******************************************************************************* +* Function Name: I2C_I2CReStartGeneration +****************************************************************************//** +* +* Generates a ReStart condition: +* - SCB IP V1 and later: Generates ReStart using the scb IP functionality +* Sets the I2C_MASTER_CMD_M_START and I2C_MASTER_CMD_M_NACK (if the previous +* transaction was read) bits in the SCB.I2C_MASTER_CMD register. +* This combination forces the master to generate ReStart. +* +* - SCB IP V0: Generates Restart using the GPIO and scb IP functionality. +* After the master completes write or read, the SCL is stretched. +* The master waits until SDA line is released by the slave. Then the GPIO +* function is enabled and the scb IP disabled as it already does not drive +* the bus. In case of the previous transfer was read, the NACK is generated +* by the GPIO. The delay of tLOW is added to manage the hold time. +* Set I2C_M_CMD.START and enable the scb IP. The ReStart generation +* is started after the I2C function is enabled for the SCL. +* Note1: the scb IP due re-enable generates Start but on the I2C bus it +* appears as ReStart. +* Note2: the I2C_M_CMD.START is queued if scb IP is disabled. +* Note3: the I2C_STATUS_M_READ is cleared is address was NACKed before. +* +* \sideeffect +* SCB IP V0: The NACK generation by the GPIO may cause a greater SCL period +* than expected for the selected master data rate. +* +*******************************************************************************/ +void I2C_I2CReStartGeneration(void) +{ + + uint32 cmd; + + /* Generates ReStart use scb IP functionality */ + cmd = I2C_I2C_MASTER_CMD_M_START; + cmd |= I2C_CHECK_I2C_STATUS(I2C_I2C_STATUS_M_READ) ? + (I2C_I2C_MASTER_CMD_M_NACK) : (0u); + + I2C_I2C_MASTER_CMD_REG = cmd; + +} + +#endif /* (I2C_I2C_MASTER_CONST) */ + + + + +/******************************************************************************* +* Function Name: I2C_I2CMasterHandleStatus +****************************************************************************//** +* +* Converts hardware status to firmware status and executes required processing. +* +* \param status +* Hardware I2C master status to handle. It also includes +* I2C_I2C_MASTER_TIMEOUT and I2C_SLAVE_INTR_I2C_ADDR. +* +* \return +* Error status. +* See I2C_I2CMasterSendStart() function for constants. +* +*******************************************************************************/ +static uint32 I2C_I2CMasterHandleStatus(uint32 status) +{ + uint32 retStatus; + uint32 resetBlock = 0u; + + if (0u != (status & I2C_I2C_MASTER_TIMEOUT)) + { + retStatus = I2C_I2C_MASTER_TIMEOUT; + resetBlock = I2C_I2C_RESET_ERROR; + } + else if (0u != (I2C_SLAVE_INTR_I2C_ADDR & status)) + { + /* Abort the master operation, the slave was addressed first */ + retStatus = I2C_I2C_MSTR_ERR_ABORT_START; + + I2C_I2C_MASTER_CMD_REG = 0u; + + I2C_state = I2C_I2C_FSM_IDLE; + } + else if (0u != (status & I2C_INTR_MASTER_I2C_ARB_LOST)) + { + retStatus = I2C_I2C_MSTR_ERR_ARB_LOST; + + if (I2C_CHECK_I2C_FSM_ADDR) + { + /* If slave is not enabled reset IP, otherwise give it a chance to match address */ + if (0u == (I2C_I2C_CTRL_REG & I2C_I2C_CTRL_SLAVE_MODE)) + { + resetBlock = I2C_I2C_RESET_ERROR; + } + + I2C_state = I2C_I2C_FSM_IDLE; + } + else + { + /* Reset IP block when on address stage */ + resetBlock = I2C_I2C_RESET_ERROR; + } + } + else if (0u != (status & I2C_INTR_MASTER_I2C_BUS_ERROR)) + { + retStatus = I2C_I2C_MSTR_ERR_BUS_ERR; + resetBlock = I2C_I2C_RESET_ERROR; + } + else if (0u != (status & I2C_INTR_MASTER_I2C_NACK)) + { + retStatus = I2C_I2C_MSTR_ERR_LB_NAK; + } + else /* Includes: INTR_MASTER_I2C_STOP and INTR_MASTER_I2C_ACK */ + { + retStatus = I2C_I2C_MSTR_NO_ERROR; + + if (0u != (status & I2C_INTR_MASTER_I2C_STOP)) + { + /* Stop: end of transaction, go to idle state */ + I2C_state = I2C_I2C_FSM_IDLE; + } + else + { + /* ACK: continue transaction */ + if (I2C_CHECK_I2C_FSM_ADDR) + { + /* Move from address state to data */ + I2C_state = (I2C_CHECK_I2C_FSM_RD) ? + I2C_I2C_FSM_MSTR_RD_DATA : I2C_I2C_FSM_MSTR_WR_DATA; + } + } + } + + if (I2C_I2C_RESET_ERROR == resetBlock) + { + I2C_I2CFwBlockReset(); + } + else + { + I2C_ClearMasterInterruptSource(I2C_INTR_MASTER_ALL); + } + + return (retStatus); +} + + +/****************************************************************************** +* Function Name: I2CMasterWaitOneUnit +****************************************************************************//** +* +* Waits for one unit before unblock code execution. +* Note If a timeout value is 0, this function does nothing and returns 0. +* +* \param timeout +* The pointer to a timeout value. +* +* \return +* Returns 0 if a timeout does not expire or the timeout mask. +* +*******************************************************************************/ +static uint32 I2C_I2CMasterWaitOneUnit(uint32 *timeout) +{ + const uint16 oneUnit = 1u; + uint32 status = 0u; + + /* If the timeout equal to 0. Ignore the timeout */ + if (*timeout > 0u) + { + CyDelayUs(oneUnit); + --(*timeout); + + if (0u == *timeout) + { + status = I2C_I2C_MASTER_TIMEOUT; + } + } + + return (status); +} + + + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/I2C_I2C_PVT.h b/cores/asr650x/cores/I2C_I2C_PVT.h new file mode 100644 index 00000000..18872c53 --- /dev/null +++ b/cores/asr650x/cores/I2C_I2C_PVT.h @@ -0,0 +1,70 @@ +/***************************************************************************//** +* \file .h +* \version 4.0 +* +* \brief +* This private file provides constants and parameter values for the +* SCB Component in I2C mode. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_I2C_PVT_I2C_H) +#define CY_SCB_I2C_PVT_I2C_H + +#include "I2C_I2C.h" + + +/*************************************** +* Private Global Vars +***************************************/ + +extern volatile uint8 I2C_state; /* Current state of I2C FSM */ + + +#if(I2C_I2C_MASTER_CONST) + extern volatile uint16 I2C_mstrStatus; /* Master Status byte */ + extern volatile uint8 I2C_mstrControl; /* Master Control byte */ + + /* Receive buffer variables */ + extern volatile uint8 * I2C_mstrRdBufPtr; /* Pointer to Master Read buffer */ + extern volatile uint32 I2C_mstrRdBufSize; /* Master Read buffer size */ + extern volatile uint32 I2C_mstrRdBufIndex; /* Master Read buffer Index */ + + /* Transmit buffer variables */ + extern volatile uint8 * I2C_mstrWrBufPtr; /* Pointer to Master Write buffer */ + extern volatile uint32 I2C_mstrWrBufSize; /* Master Write buffer size */ + extern volatile uint32 I2C_mstrWrBufIndex; /* Master Write buffer Index */ + extern volatile uint32 I2C_mstrWrBufIndexTmp; /* Master Write buffer Index Tmp */ +#endif /* (I2C_I2C_MASTER_CONST) */ + +/*************************************** +* Private Function Prototypes +***************************************/ + +#if(I2C_SCB_MODE_I2C_CONST_CFG) + void I2C_I2CInit(void); +#endif /* (I2C_SCB_MODE_I2C_CONST_CFG) */ + +void I2C_I2CStop(void); +void I2C_I2CFwBlockReset(void); + +void I2C_I2CSaveConfig(void); +void I2C_I2CRestoreConfig(void); + +#if(I2C_I2C_MASTER_CONST) + void I2C_I2CReStartGeneration(void); +#endif /* (I2C_I2C_MASTER_CONST) */ + +#endif /* (CY_SCB_I2C_PVT_I2C_H) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/I2C_PVT.h b/cores/asr650x/cores/I2C_PVT.h new file mode 100644 index 00000000..459d405a --- /dev/null +++ b/cores/asr650x/cores/I2C_PVT.h @@ -0,0 +1,70 @@ +/***************************************************************************//** +* \file .h +* \version 4.0 +* +* \brief +* This private file provides constants and parameter values for the +* SCB Component. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_PVT_I2C_H) +#define CY_SCB_PVT_I2C_H + +#include "I2C.h" + + +/*************************************** +* Private Function Prototypes +***************************************/ + +/* APIs to service INTR_I2C_EC register */ +#define I2C_SetI2CExtClkInterruptMode(interruptMask) I2C_WRITE_INTR_I2C_EC_MASK(interruptMask) +#define I2C_ClearI2CExtClkInterruptSource(interruptMask) I2C_CLEAR_INTR_I2C_EC(interruptMask) +#define I2C_GetI2CExtClkInterruptSource() (I2C_INTR_I2C_EC_REG) +#define I2C_GetI2CExtClkInterruptMode() (I2C_INTR_I2C_EC_MASK_REG) +#define I2C_GetI2CExtClkInterruptSourceMasked() (I2C_INTR_I2C_EC_MASKED_REG) + + + /* APIs to service INTR_SPI_EC register */ + #define I2C_SetSpiExtClkInterruptMode(interruptMask) \ + I2C_WRITE_INTR_SPI_EC_MASK(interruptMask) + #define I2C_ClearSpiExtClkInterruptSource(interruptMask) \ + I2C_CLEAR_INTR_SPI_EC(interruptMask) + #define I2C_GetExtSpiClkInterruptSource() (I2C_INTR_SPI_EC_REG) + #define I2C_GetExtSpiClkInterruptMode() (I2C_INTR_SPI_EC_MASK_REG) + #define I2C_GetExtSpiClkInterruptSourceMasked() (I2C_INTR_SPI_EC_MASKED_REG) + + + +/*************************************** +* Vars with External Linkage +***************************************/ + +extern cyisraddress I2C_customIntrHandler; + +extern I2C_BACKUP_STRUCT I2C_backup; + +#if (! (I2C_SCB_MODE_I2C_CONST_CFG || \ + I2C_SCB_MODE_EZI2C_CONST_CFG)) + extern uint16 I2C_IntrTxMask; +#endif /* (! (I2C_SCB_MODE_I2C_CONST_CFG || \ + I2C_SCB_MODE_EZI2C_CONST_CFG)) */ + + +/* Defines maximum number of SCB pins */ +#define I2C_SCB_PINS_NUMBER (7u) + +#endif /* (CY_SCB_PVT_I2C_H) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/I2C_SCBCLK.c b/cores/asr650x/cores/I2C_SCBCLK.c new file mode 100644 index 00000000..e6fbc63f --- /dev/null +++ b/cores/asr650x/cores/I2C_SCBCLK.c @@ -0,0 +1,210 @@ +/******************************************************************************* +* File Name: I2C_SCBCLK.c +* Version 2.20 +* +* Description: +* Provides system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "I2C_SCBCLK.h" + +#if defined CYREG_PERI_DIV_CMD + +/******************************************************************************* +* Function Name: I2C_SCBCLK_StartEx +******************************************************************************** +* +* Summary: +* Starts the clock, aligned to the specified running clock. +* +* Parameters: +* alignClkDiv: The divider to which phase alignment is performed when the +* clock is started. +* +* Returns: +* None +* +*******************************************************************************/ +void I2C_SCBCLK_StartEx(uint32 alignClkDiv) +{ + /* Make sure any previous start command has finished. */ + while((I2C_SCBCLK_CMD_REG & I2C_SCBCLK_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and enable. */ + I2C_SCBCLK_CMD_REG = + ((uint32)I2C_SCBCLK__DIV_ID << I2C_SCBCLK_CMD_DIV_SHIFT)| + (alignClkDiv << I2C_SCBCLK_CMD_PA_DIV_SHIFT) | + (uint32)I2C_SCBCLK_CMD_ENABLE_MASK; +} + +#else + +/******************************************************************************* +* Function Name: I2C_SCBCLK_Start +******************************************************************************** +* +* Summary: +* Starts the clock. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ + +void I2C_SCBCLK_Start(void) +{ + /* Set the bit to enable the clock. */ + I2C_SCBCLK_ENABLE_REG |= I2C_SCBCLK__ENABLE_MASK; +} + +#endif /* CYREG_PERI_DIV_CMD */ + + +/******************************************************************************* +* Function Name: I2C_SCBCLK_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void I2C_SCBCLK_Stop(void) +{ +#if defined CYREG_PERI_DIV_CMD + + /* Make sure any previous start command has finished. */ + while((I2C_SCBCLK_CMD_REG & I2C_SCBCLK_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and disable. */ + I2C_SCBCLK_CMD_REG = + ((uint32)I2C_SCBCLK__DIV_ID << I2C_SCBCLK_CMD_DIV_SHIFT)| + ((uint32)I2C_SCBCLK_CMD_DISABLE_MASK); + +#else + + /* Clear the bit to disable the clock. */ + I2C_SCBCLK_ENABLE_REG &= (uint32)(~I2C_SCBCLK__ENABLE_MASK); + +#endif /* CYREG_PERI_DIV_CMD */ +} + + +/******************************************************************************* +* Function Name: I2C_SCBCLK_SetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and the fractional divider. +* +* Parameters: +* clkDivider: Divider register value (0-65535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* fracDivider: Fractional Divider register value (0-31). +* Returns: +* None +* +*******************************************************************************/ +void I2C_SCBCLK_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional) +{ + uint32 maskVal; + uint32 regVal; + +#if defined (I2C_SCBCLK__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD) + + /* get all but divider bits */ + maskVal = I2C_SCBCLK_DIV_REG & + (uint32)(~(uint32)(I2C_SCBCLK_DIV_INT_MASK | I2C_SCBCLK_DIV_FRAC_MASK)); + /* combine mask and new divider vals into 32-bit value */ + regVal = maskVal | + ((uint32)((uint32)clkDivider << I2C_SCBCLK_DIV_INT_SHIFT) & I2C_SCBCLK_DIV_INT_MASK) | + ((uint32)((uint32)clkFractional << I2C_SCBCLK_DIV_FRAC_SHIFT) & I2C_SCBCLK_DIV_FRAC_MASK); + +#else + /* get all but integer divider bits */ + maskVal = I2C_SCBCLK_DIV_REG & (uint32)(~(uint32)I2C_SCBCLK__DIVIDER_MASK); + /* combine mask and new divider val into 32-bit value */ + regVal = clkDivider | maskVal; + +#endif /* I2C_SCBCLK__FRAC_MASK || CYREG_PERI_DIV_CMD */ + + I2C_SCBCLK_DIV_REG = regVal; +} + + +/******************************************************************************* +* Function Name: I2C_SCBCLK_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 I2C_SCBCLK_GetDividerRegister(void) +{ + return (uint16)((I2C_SCBCLK_DIV_REG & I2C_SCBCLK_DIV_INT_MASK) + >> I2C_SCBCLK_DIV_INT_SHIFT); +} + + +/******************************************************************************* +* Function Name: I2C_SCBCLK_GetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock fractional divider register value. +* +* Parameters: +* None +* +* Returns: +* Fractional Divide value of the clock +* 0 if the fractional divider is not in use. +* +*******************************************************************************/ +uint8 I2C_SCBCLK_GetFractionalDividerRegister(void) +{ +#if defined (I2C_SCBCLK__FRAC_MASK) + /* return fractional divider bits */ + return (uint8)((I2C_SCBCLK_DIV_REG & I2C_SCBCLK_DIV_FRAC_MASK) + >> I2C_SCBCLK_DIV_FRAC_SHIFT); +#else + return 0u; +#endif /* I2C_SCBCLK__FRAC_MASK */ +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/I2C_SCBCLK.h b/cores/asr650x/cores/I2C_SCBCLK.h new file mode 100644 index 00000000..4c494dab --- /dev/null +++ b/cores/asr650x/cores/I2C_SCBCLK.h @@ -0,0 +1,94 @@ +/******************************************************************************* +* File Name: I2C_SCBCLK.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_I2C_SCBCLK_H) +#define CY_CLOCK_I2C_SCBCLK_H + +#include +#include + +#define I2C_SCBCLK__CTRL_REGISTER CYREG_PERI_PCLK_CTL2 +#define I2C_SCBCLK__DIV_ID 0x00000040u +#define I2C_SCBCLK__DIV_REGISTER CYREG_PERI_DIV_16_CTL0 +#define I2C_SCBCLK__PA_DIV_ID 0x000000FFu +/*************************************** +* Function Prototypes +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +void I2C_SCBCLK_StartEx(uint32 alignClkDiv); +#define I2C_SCBCLK_Start() \ + I2C_SCBCLK_StartEx(I2C_SCBCLK__PA_DIV_ID) + +#else + +void I2C_SCBCLK_Start(void); + +#endif/* CYREG_PERI_DIV_CMD */ + +void I2C_SCBCLK_Stop(void); + +void I2C_SCBCLK_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional); + +uint16 I2C_SCBCLK_GetDividerRegister(void); +uint8 I2C_SCBCLK_GetFractionalDividerRegister(void); + +#define I2C_SCBCLK_Enable() I2C_SCBCLK_Start() +#define I2C_SCBCLK_Disable() I2C_SCBCLK_Stop() +#define I2C_SCBCLK_SetDividerRegister(clkDivider, reset) \ + I2C_SCBCLK_SetFractionalDividerRegister((clkDivider), 0u) +#define I2C_SCBCLK_SetDivider(clkDivider) I2C_SCBCLK_SetDividerRegister((clkDivider), 1u) +#define I2C_SCBCLK_SetDividerValue(clkDivider) I2C_SCBCLK_SetDividerRegister((clkDivider) - 1u, 1u) + + +/*************************************** +* Registers +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +#define I2C_SCBCLK_DIV_ID I2C_SCBCLK__DIV_ID + +#define I2C_SCBCLK_CMD_REG (*(reg32 *)CYREG_PERI_DIV_CMD) +#define I2C_SCBCLK_CTRL_REG (*(reg32 *)I2C_SCBCLK__CTRL_REGISTER) +#define I2C_SCBCLK_DIV_REG (*(reg32 *)I2C_SCBCLK__DIV_REGISTER) + +#define I2C_SCBCLK_CMD_DIV_SHIFT (0u) +#define I2C_SCBCLK_CMD_PA_DIV_SHIFT (8u) +#define I2C_SCBCLK_CMD_DISABLE_SHIFT (30u) +#define I2C_SCBCLK_CMD_ENABLE_SHIFT (31u) + +#define I2C_SCBCLK_CMD_DISABLE_MASK ((uint32)((uint32)1u << I2C_SCBCLK_CMD_DISABLE_SHIFT)) +#define I2C_SCBCLK_CMD_ENABLE_MASK ((uint32)((uint32)1u << I2C_SCBCLK_CMD_ENABLE_SHIFT)) + +#define I2C_SCBCLK_DIV_FRAC_MASK (0x000000F8u) +#define I2C_SCBCLK_DIV_FRAC_SHIFT (3u) +#define I2C_SCBCLK_DIV_INT_MASK (0xFFFFFF00u) +#define I2C_SCBCLK_DIV_INT_SHIFT (8u) + +#else + +#define I2C_SCBCLK_DIV_REG (*(reg32 *)I2C_SCBCLK__REGISTER) +#define I2C_SCBCLK_ENABLE_REG I2C_SCBCLK_DIV_REG +#define I2C_SCBCLK_DIV_FRAC_MASK I2C_SCBCLK__FRAC_MASK +#define I2C_SCBCLK_DIV_FRAC_SHIFT (16u) +#define I2C_SCBCLK_DIV_INT_MASK I2C_SCBCLK__DIVIDER_MASK +#define I2C_SCBCLK_DIV_INT_SHIFT (0u) + +#endif/* CYREG_PERI_DIV_CMD */ + +#endif /* !defined(CY_CLOCK_I2C_SCBCLK_H) */ + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/I2C_SCB_IRQ.c b/cores/asr650x/cores/I2C_SCB_IRQ.c new file mode 100644 index 00000000..2cd019ab --- /dev/null +++ b/cores/asr650x/cores/I2C_SCB_IRQ.c @@ -0,0 +1,406 @@ +/******************************************************************************* +* File Name: I2C_SCB_IRQ.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include +#include "cyapicallbacks.h" + +#if !defined(I2C_SCB_IRQ__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START I2C_SCB_IRQ_intc` */ + +/* `#END` */ + +extern cyisraddress CyRamVectors[CYINT_IRQ_BASE + CY_NUM_INTERRUPTS]; + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void I2C_SCB_IRQ_Start(void) +{ + /* For all we know the interrupt is active. */ + I2C_SCB_IRQ_Disable(); + + /* Set the ISR to point to the I2C_SCB_IRQ Interrupt. */ + I2C_SCB_IRQ_SetVector(&I2C_SCB_IRQ_Interrupt); + + /* Set the priority. */ + I2C_SCB_IRQ_SetPriority((uint8)I2C_SCB_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + I2C_SCB_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void I2C_SCB_IRQ_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + I2C_SCB_IRQ_Disable(); + + /* Set the ISR to point to the I2C_SCB_IRQ Interrupt. */ + I2C_SCB_IRQ_SetVector(address); + + /* Set the priority. */ + I2C_SCB_IRQ_SetPriority((uint8)I2C_SCB_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + I2C_SCB_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void I2C_SCB_IRQ_Stop(void) +{ + /* Disable this interrupt. */ + I2C_SCB_IRQ_Disable(); + + /* Set the ISR to point to the passive one. */ + I2C_SCB_IRQ_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for I2C_SCB_IRQ. +* +* Add custom code between the START and END comments to keep the next version +* of this file from over-writing your code. +* +* Note You may use either the default ISR by using this API, or you may define +* your own separate ISR through ISR_StartEx(). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(I2C_SCB_IRQ_Interrupt) +{ + #ifdef I2C_SCB_IRQ_INTERRUPT_INTERRUPT_CALLBACK + I2C_SCB_IRQ_Interrupt_InterruptCallback(); + #endif /* I2C_SCB_IRQ_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START I2C_SCB_IRQ_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling I2C_SCB_IRQ_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use I2C_SCB_IRQ_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void I2C_SCB_IRQ_SetVector(cyisraddress address) +{ + CyRamVectors[CYINT_IRQ_BASE + I2C_SCB_IRQ__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress I2C_SCB_IRQ_GetVector(void) +{ + return CyRamVectors[CYINT_IRQ_BASE + I2C_SCB_IRQ__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling I2C_SCB_IRQ_Start or I2C_SCB_IRQ_StartEx will +* override any effect this API would have had. This API should only be called +* after I2C_SCB_IRQ_Start or I2C_SCB_IRQ_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void I2C_SCB_IRQ_SetPriority(uint8 priority) +{ + uint8 interruptState; + uint32 priorityOffset = ((I2C_SCB_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + interruptState = CyEnterCriticalSection(); + *I2C_SCB_IRQ_INTC_PRIOR = (*I2C_SCB_IRQ_INTC_PRIOR & (uint32)(~I2C_SCB_IRQ__INTC_PRIOR_MASK)) | + ((uint32)priority << priorityOffset); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 I2C_SCB_IRQ_GetPriority(void) +{ + uint32 priority; + uint32 priorityOffset = ((I2C_SCB_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + priority = (*I2C_SCB_IRQ_INTC_PRIOR & I2C_SCB_IRQ__INTC_PRIOR_MASK) >> priorityOffset; + + return (uint8)priority; +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void I2C_SCB_IRQ_Enable(void) +{ + /* Enable the general interrupt. */ + *I2C_SCB_IRQ_INTC_SET_EN = I2C_SCB_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 I2C_SCB_IRQ_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*I2C_SCB_IRQ_INTC_SET_EN & (uint32)I2C_SCB_IRQ__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void I2C_SCB_IRQ_Disable(void) +{ + /* Disable the general interrupt. */ + *I2C_SCB_IRQ_INTC_CLR_EN = I2C_SCB_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void I2C_SCB_IRQ_SetPending(void) +{ + *I2C_SCB_IRQ_INTC_SET_PD = I2C_SCB_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: I2C_SCB_IRQ_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void I2C_SCB_IRQ_ClearPending(void) +{ + *I2C_SCB_IRQ_INTC_CLR_PD = I2C_SCB_IRQ__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/I2C_SCB_IRQ.h b/cores/asr650x/cores/I2C_SCB_IRQ.h new file mode 100644 index 00000000..c6c19986 --- /dev/null +++ b/cores/asr650x/cores/I2C_SCB_IRQ.h @@ -0,0 +1,81 @@ +/******************************************************************************* +* File Name: I2C_SCB_IRQ.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_I2C_SCB_IRQ_H) +#define CY_ISR_I2C_SCB_IRQ_H + + +#include +#include + +#define I2C_SCB_IRQ__INTC_CLR_EN_REG CYREG_CM0P_ICER +#define I2C_SCB_IRQ__INTC_CLR_PD_REG CYREG_CM0P_ICPR +#define I2C_SCB_IRQ__INTC_MASK 0x200u +#define I2C_SCB_IRQ__INTC_NUMBER 9u +#define I2C_SCB_IRQ__INTC_PRIOR_MASK 0xC000u +#define I2C_SCB_IRQ__INTC_PRIOR_NUM 3u +#define I2C_SCB_IRQ__INTC_PRIOR_REG CYREG_CM0P_IPR2 +#define I2C_SCB_IRQ__INTC_SET_EN_REG CYREG_CM0P_ISER +#define I2C_SCB_IRQ__INTC_SET_PD_REG CYREG_CM0P_ISPR + +/* Interrupt Controller API. */ +void I2C_SCB_IRQ_Start(void); +void I2C_SCB_IRQ_StartEx(cyisraddress address); +void I2C_SCB_IRQ_Stop(void); + +CY_ISR_PROTO(I2C_SCB_IRQ_Interrupt); + +void I2C_SCB_IRQ_SetVector(cyisraddress address); +cyisraddress I2C_SCB_IRQ_GetVector(void); + +void I2C_SCB_IRQ_SetPriority(uint8 priority); +uint8 I2C_SCB_IRQ_GetPriority(void); + +void I2C_SCB_IRQ_Enable(void); +uint8 I2C_SCB_IRQ_GetState(void); +void I2C_SCB_IRQ_Disable(void); + +void I2C_SCB_IRQ_SetPending(void); +void I2C_SCB_IRQ_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the I2C_SCB_IRQ ISR. */ +#define I2C_SCB_IRQ_INTC_VECTOR ((reg32 *) I2C_SCB_IRQ__INTC_VECT) + +/* Address of the I2C_SCB_IRQ ISR priority. */ +#define I2C_SCB_IRQ_INTC_PRIOR ((reg32 *) I2C_SCB_IRQ__INTC_PRIOR_REG) + +/* Priority of the I2C_SCB_IRQ interrupt. */ +#define I2C_SCB_IRQ_INTC_PRIOR_NUMBER I2C_SCB_IRQ__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable I2C_SCB_IRQ interrupt. */ +#define I2C_SCB_IRQ_INTC_SET_EN ((reg32 *) I2C_SCB_IRQ__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the I2C_SCB_IRQ interrupt. */ +#define I2C_SCB_IRQ_INTC_CLR_EN ((reg32 *) I2C_SCB_IRQ__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the I2C_SCB_IRQ interrupt state to pending. */ +#define I2C_SCB_IRQ_INTC_SET_PD ((reg32 *) I2C_SCB_IRQ__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the I2C_SCB_IRQ interrupt. */ +#define I2C_SCB_IRQ_INTC_CLR_PD ((reg32 *) I2C_SCB_IRQ__INTC_CLR_PD_REG) + + + +#endif /* CY_ISR_I2C_SCB_IRQ_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/PWM1.c b/cores/asr650x/cores/PWM1.c new file mode 100644 index 00000000..364730dd --- /dev/null +++ b/cores/asr650x/cores/PWM1.c @@ -0,0 +1,1420 @@ +/******************************************************************************* +* File Name: PWM1.c +* Version 2.10 +* +* Description: +* This file provides the source code to the API for the PWM1 +* component +* +* Note: +* None +* +******************************************************************************** +* Copyright 2013-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "PWM1.h" +#include "ASR_Arduino.h" +uint8 PWM1_initVar = 0u; + + +/******************************************************************************* +* Function Name: PWM1_Init +******************************************************************************** +* +* Summary: +* Initialize/Restore default PWM1 configuration. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_Init(void) +{ + + /* Set values from customizer to CTRL */ + #if (PWM1__QUAD == PWM1_CONFIG) + PWM1_CONTROL_REG = PWM1_CTRL_QUAD_BASE_CONFIG; + + /* Set values from customizer to CTRL1 */ + PWM1_TRIG_CONTROL1_REG = PWM1_QUAD_SIGNALS_MODES; + + /* Set values from customizer to INTR */ + PWM1_SetInterruptMode(PWM1_QUAD_INTERRUPT_MASK); + + /* Set other values */ + PWM1_SetCounterMode(PWM1_COUNT_DOWN); + PWM1_WritePeriod(PWM1_QUAD_PERIOD_INIT_VALUE); + PWM1_WriteCounter(PWM1_QUAD_PERIOD_INIT_VALUE); + #endif /* (PWM1__QUAD == PWM1_CONFIG) */ + + #if (PWM1__TIMER == PWM1_CONFIG) + PWM1_CONTROL_REG = PWM1_CTRL_TIMER_BASE_CONFIG; + + /* Set values from customizer to CTRL1 */ + PWM1_TRIG_CONTROL1_REG = PWM1_TIMER_SIGNALS_MODES; + + /* Set values from customizer to INTR */ + PWM1_SetInterruptMode(PWM1_TC_INTERRUPT_MASK); + + /* Set other values from customizer */ + PWM1_WritePeriod(PWM1_TC_PERIOD_VALUE ); + + #if (PWM1__COMPARE == PWM1_TC_COMP_CAP_MODE) + PWM1_WriteCompare(PWM1_TC_COMPARE_VALUE); + + #if (1u == PWM1_TC_COMPARE_SWAP) + PWM1_SetCompareSwap(1u); + PWM1_WriteCompareBuf(PWM1_TC_COMPARE_BUF_VALUE); + #endif /* (1u == PWM1_TC_COMPARE_SWAP) */ + #endif /* (PWM1__COMPARE == PWM1_TC_COMP_CAP_MODE) */ + + /* Initialize counter value */ + #if (PWM1_CY_TCPWM_V2 && PWM1_TIMER_UPDOWN_CNT_USED && !PWM1_CY_TCPWM_4000) + PWM1_WriteCounter(1u); + #elif(PWM1__COUNT_DOWN == PWM1_TC_COUNTER_MODE) + PWM1_WriteCounter(PWM1_TC_PERIOD_VALUE); + #else + PWM1_WriteCounter(0u); + #endif /* (PWM1_CY_TCPWM_V2 && PWM1_TIMER_UPDOWN_CNT_USED && !PWM1_CY_TCPWM_4000) */ + #endif /* (PWM1__TIMER == PWM1_CONFIG) */ + + #if (PWM1__PWM_SEL == PWM1_CONFIG) + PWM1_CONTROL_REG = PWM1_CTRL_PWM_BASE_CONFIG; + + #if (PWM1__PWM_PR == PWM1_PWM_MODE) + PWM1_CONTROL_REG |= PWM1_CTRL_PWM_RUN_MODE; + PWM1_WriteCounter(PWM1_PWM_PR_INIT_VALUE); + #else + PWM1_CONTROL_REG |= PWM1_CTRL_PWM_ALIGN | PWM1_CTRL_PWM_KILL_EVENT; + + /* Initialize counter value */ + #if (PWM1_CY_TCPWM_V2 && PWM1_PWM_UPDOWN_CNT_USED && !PWM1_CY_TCPWM_4000) + PWM1_WriteCounter(1u); + #elif (PWM1__RIGHT == PWM1_PWM_ALIGN) + PWM1_WriteCounter(PWM1_PWM_PERIOD_VALUE); + #else + PWM1_WriteCounter(0u); + #endif /* (PWM1_CY_TCPWM_V2 && PWM1_PWM_UPDOWN_CNT_USED && !PWM1_CY_TCPWM_4000) */ + #endif /* (PWM1__PWM_PR == PWM1_PWM_MODE) */ + + #if (PWM1__PWM_DT == PWM1_PWM_MODE) + PWM1_CONTROL_REG |= PWM1_CTRL_PWM_DEAD_TIME_CYCLE; + #endif /* (PWM1__PWM_DT == PWM1_PWM_MODE) */ + + #if (PWM1__PWM == PWM1_PWM_MODE) + PWM1_CONTROL_REG |= PWM1_CTRL_PWM_PRESCALER; + #endif /* (PWM1__PWM == PWM1_PWM_MODE) */ + + /* Set values from customizer to CTRL1 */ + PWM1_TRIG_CONTROL1_REG = PWM1_PWM_SIGNALS_MODES; + + /* Set values from customizer to INTR */ + PWM1_SetInterruptMode(PWM1_PWM_INTERRUPT_MASK); + + /* Set values from customizer to CTRL2 */ + #if (PWM1__PWM_PR == PWM1_PWM_MODE) + PWM1_TRIG_CONTROL2_REG = + (PWM1_CC_MATCH_NO_CHANGE | + PWM1_OVERLOW_NO_CHANGE | + PWM1_UNDERFLOW_NO_CHANGE); + #else + #if (PWM1__LEFT == PWM1_PWM_ALIGN) + PWM1_TRIG_CONTROL2_REG = PWM1_PWM_MODE_LEFT; + #endif /* ( PWM1_PWM_LEFT == PWM1_PWM_ALIGN) */ + + #if (PWM1__RIGHT == PWM1_PWM_ALIGN) + PWM1_TRIG_CONTROL2_REG = PWM1_PWM_MODE_RIGHT; + #endif /* ( PWM1_PWM_RIGHT == PWM1_PWM_ALIGN) */ + + #if (PWM1__CENTER == PWM1_PWM_ALIGN) + PWM1_TRIG_CONTROL2_REG = PWM1_PWM_MODE_CENTER; + #endif /* ( PWM1_PWM_CENTER == PWM1_PWM_ALIGN) */ + + #if (PWM1__ASYMMETRIC == PWM1_PWM_ALIGN) + PWM1_TRIG_CONTROL2_REG = PWM1_PWM_MODE_ASYM; + #endif /* (PWM1__ASYMMETRIC == PWM1_PWM_ALIGN) */ + #endif /* (PWM1__PWM_PR == PWM1_PWM_MODE) */ + + /* Set other values from customizer */ + PWM1_WritePeriod(PWM1_PWM_PERIOD_VALUE ); + PWM1_WriteCompare(PWM1_PWM_COMPARE_VALUE); + + #if (1u == PWM1_PWM_COMPARE_SWAP) + PWM1_SetCompareSwap(1u); + PWM1_WriteCompareBuf(PWM1_PWM_COMPARE_BUF_VALUE); + #endif /* (1u == PWM1_PWM_COMPARE_SWAP) */ + + #if (1u == PWM1_PWM_PERIOD_SWAP) + PWM1_SetPeriodSwap(1u); + PWM1_WritePeriodBuf(PWM1_PWM_PERIOD_BUF_VALUE); + #endif /* (1u == PWM1_PWM_PERIOD_SWAP) */ + #endif /* (PWM1__PWM_SEL == PWM1_CONFIG) */ + +} + + +/******************************************************************************* +* Function Name: PWM1_Enable +******************************************************************************** +* +* Summary: +* Enables the PWM1. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_Enable(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + PWM1_BLOCK_CONTROL_REG |= PWM1_MASK; + CyExitCriticalSection(enableInterrupts); + + /* Start Timer or PWM if start input is absent */ + #if (PWM1__PWM_SEL == PWM1_CONFIG) + #if (0u == PWM1_PWM_START_SIGNAL_PRESENT) + PWM1_TriggerCommand(PWM1_MASK, PWM1_CMD_START); + #endif /* (0u == PWM1_PWM_START_SIGNAL_PRESENT) */ + #endif /* (PWM1__PWM_SEL == PWM1_CONFIG) */ + + #if (PWM1__TIMER == PWM1_CONFIG) + #if (0u == PWM1_TC_START_SIGNAL_PRESENT) + PWM1_TriggerCommand(PWM1_MASK, PWM1_CMD_START); + #endif /* (0u == PWM1_TC_START_SIGNAL_PRESENT) */ + #endif /* (PWM1__TIMER == PWM1_CONFIG) */ + + #if (PWM1__QUAD == PWM1_CONFIG) + #if (0u != PWM1_QUAD_AUTO_START) + PWM1_TriggerCommand(PWM1_MASK, PWM1_CMD_RELOAD); + #endif /* (0u != PWM1_QUAD_AUTO_START) */ + #endif /* (PWM1__QUAD == PWM1_CONFIG) */ +} + + +/******************************************************************************* +* Function Name: PWM1_Start +******************************************************************************** +* +* Summary: +* Initializes the PWM1 with default customizer +* values when called the first time and enables the PWM1. +* For subsequent calls the configuration is left unchanged and the component is +* just enabled. +* +* Parameters: +* None +* +* Return: +* None +* +* Global variables: +* PWM1_initVar: global variable is used to indicate initial +* configuration of this component. The variable is initialized to zero and set +* to 1 the first time PWM1_Start() is called. This allows +* enabling/disabling a component without re-initialization in all subsequent +* calls to the PWM1_Start() routine. +* +*******************************************************************************/ +void PWM1_Start(void) +{ + (* (reg32 *) CYREG_HSIOM_PORT_SEL6)=((* (reg32 *) CYREG_HSIOM_PORT_SEL6)&(~0x00000800u))|0x00000800u; + if (0u == PWM1_initVar) + { + PWM1_Init(); + PWM1_initVar = 1u; + } + + PWM1_Enable(); +} + + +/******************************************************************************* +* Function Name: PWM1_Stop +******************************************************************************** +* +* Summary: +* Disables the PWM1. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_Stop(void) +{ + pinMode(P6_2,ANALOG); + (* (reg32 *) CYREG_HSIOM_PORT_SEL6)=((* (reg32 *) CYREG_HSIOM_PORT_SEL6)&(~0x00000800u)); + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_BLOCK_CONTROL_REG &= (uint32)~PWM1_MASK; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetMode +******************************************************************************** +* +* Summary: +* Sets the operation mode of the PWM1. This function is used when +* configured as a generic PWM1 and the actual mode of operation is +* set at runtime. The mode must be set while the component is disabled. +* +* Parameters: +* mode: Mode for the PWM1 to operate in +* Values: +* - PWM1_MODE_TIMER_COMPARE - Timer / Counter with +* compare capability +* - PWM1_MODE_TIMER_CAPTURE - Timer / Counter with +* capture capability +* - PWM1_MODE_QUAD - Quadrature decoder +* - PWM1_MODE_PWM - PWM +* - PWM1_MODE_PWM_DT - PWM with dead time +* - PWM1_MODE_PWM_PR - PWM with pseudo random capability +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetMode(uint32 mode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_CONTROL_REG &= (uint32)~PWM1_MODE_MASK; + PWM1_CONTROL_REG |= mode; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetQDMode +******************************************************************************** +* +* Summary: +* Sets the the Quadrature Decoder to one of the 3 supported modes. +* Its functionality is only applicable to Quadrature Decoder operation. +* +* Parameters: +* qdMode: Quadrature Decoder mode +* Values: +* - PWM1_MODE_X1 - Counts on phi 1 rising +* - PWM1_MODE_X2 - Counts on both edges of phi1 (2x faster) +* - PWM1_MODE_X4 - Counts on both edges of phi1 and phi2 +* (4x faster) +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetQDMode(uint32 qdMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_CONTROL_REG &= (uint32)~PWM1_QUAD_MODE_MASK; + PWM1_CONTROL_REG |= qdMode; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetPrescaler +******************************************************************************** +* +* Summary: +* Sets the prescaler value that is applied to the clock input. Not applicable +* to a PWM with the dead time mode or Quadrature Decoder mode. +* +* Parameters: +* prescaler: Prescaler divider value +* Values: +* - PWM1_PRESCALE_DIVBY1 - Divide by 1 (no prescaling) +* - PWM1_PRESCALE_DIVBY2 - Divide by 2 +* - PWM1_PRESCALE_DIVBY4 - Divide by 4 +* - PWM1_PRESCALE_DIVBY8 - Divide by 8 +* - PWM1_PRESCALE_DIVBY16 - Divide by 16 +* - PWM1_PRESCALE_DIVBY32 - Divide by 32 +* - PWM1_PRESCALE_DIVBY64 - Divide by 64 +* - PWM1_PRESCALE_DIVBY128 - Divide by 128 +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetPrescaler(uint32 prescaler) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_CONTROL_REG &= (uint32)~PWM1_PRESCALER_MASK; + PWM1_CONTROL_REG |= prescaler; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetOneShot +******************************************************************************** +* +* Summary: +* Writes the register that controls whether the PWM1 runs +* continuously or stops when terminal count is reached. By default the +* PWM1 operates in the continuous mode. +* +* Parameters: +* oneShotEnable +* Values: +* - 0 - Continuous +* - 1 - Enable One Shot +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetOneShot(uint32 oneShotEnable) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_CONTROL_REG &= (uint32)~PWM1_ONESHOT_MASK; + PWM1_CONTROL_REG |= ((uint32)((oneShotEnable & PWM1_1BIT_MASK) << + PWM1_ONESHOT_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetPWMMode +******************************************************************************** +* +* Summary: +* Writes the control register that determines what mode of operation the PWM +* output lines are driven in. There is a setting for what to do on a +* comparison match (CC_MATCH), on an overflow (OVERFLOW) and on an underflow +* (UNDERFLOW). The value for each of the three must be ORed together to form +* the mode. +* +* Parameters: +* modeMask: A combination of three mode settings. Mask must include a value +* for each of the three or use one of the preconfigured PWM settings. +* Values: +* - CC_MATCH_SET - Set on comparison match +* - CC_MATCH_CLEAR - Clear on comparison match +* - CC_MATCH_INVERT - Invert on comparison match +* - CC_MATCH_NO_CHANGE - No change on comparison match +* - OVERLOW_SET - Set on overflow +* - OVERLOW_CLEAR - Clear on overflow +* - OVERLOW_INVERT - Invert on overflow +* - OVERLOW_NO_CHANGE - No change on overflow +* - UNDERFLOW_SET - Set on underflow +* - UNDERFLOW_CLEAR - Clear on underflow +* - UNDERFLOW_INVERT - Invert on underflow +* - UNDERFLOW_NO_CHANGE - No change on underflow +* - PWM_MODE_LEFT - Setting for left aligned PWM. Should be combined +* with up counting mode +* - PWM_MODE_RIGHT - Setting for right aligned PWM. Should be combined +* with down counting mode +* - PWM_MODE_CENTER - Setting for center aligned PWM. Should be +* combined with up/down 0 mode +* - PWM_MODE_ASYM - Setting for asymmetric PWM. Should be combined +* with up/down 1 mode +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetPWMMode(uint32 modeMask) +{ + PWM1_TRIG_CONTROL2_REG = (modeMask & PWM1_6BIT_MASK); +} + + + +/******************************************************************************* +* Function Name: PWM1_SetPWMSyncKill +******************************************************************************** +* +* Summary: +* Writes the register that controls whether the PWM kill signal (stop input) +* causes asynchronous or synchronous kill operation. By default the kill +* operation is asynchronous. This functionality is only applicable to the PWM +* and PWM with dead time modes. +* +* For Synchronous mode the kill signal disables both the line and line_n +* signals until the next terminal count. +* +* For Asynchronous mode the kill signal disables both the line and line_n +* signals when the kill signal is present. This mode should only be used +* when the kill signal (stop input) is configured in the pass through mode +* (Level sensitive signal). + +* +* Parameters: +* syncKillEnable +* Values: +* - 0 - Asynchronous +* - 1 - Synchronous +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetPWMSyncKill(uint32 syncKillEnable) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_CONTROL_REG &= (uint32)~PWM1_PWM_SYNC_KILL_MASK; + PWM1_CONTROL_REG |= ((uint32)((syncKillEnable & PWM1_1BIT_MASK) << + PWM1_PWM_SYNC_KILL_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetPWMStopOnKill +******************************************************************************** +* +* Summary: +* Writes the register that controls whether the PWM kill signal (stop input) +* causes the PWM counter to stop. By default the kill operation does not stop +* the counter. This functionality is only applicable to the three PWM modes. +* +* +* Parameters: +* stopOnKillEnable +* Values: +* - 0 - Don't stop +* - 1 - Stop +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetPWMStopOnKill(uint32 stopOnKillEnable) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_CONTROL_REG &= (uint32)~PWM1_PWM_STOP_KILL_MASK; + PWM1_CONTROL_REG |= ((uint32)((stopOnKillEnable & PWM1_1BIT_MASK) << + PWM1_PWM_STOP_KILL_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetPWMDeadTime +******************************************************************************** +* +* Summary: +* Writes the dead time control value. This value delays the rising edge of +* both the line and line_n signals the designated number of cycles resulting +* in both signals being inactive for that many cycles. This functionality is +* only applicable to the PWM in the dead time mode. + +* +* Parameters: +* Dead time to insert +* Values: 0 to 255 +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetPWMDeadTime(uint32 deadTime) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_CONTROL_REG &= (uint32)~PWM1_PRESCALER_MASK; + PWM1_CONTROL_REG |= ((uint32)((deadTime & PWM1_8BIT_MASK) << + PWM1_PRESCALER_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetPWMInvert +******************************************************************************** +* +* Summary: +* Writes the bits that control whether the line and line_n outputs are +* inverted from their normal output values. This functionality is only +* applicable to the three PWM modes. +* +* Parameters: +* mask: Mask of outputs to invert. +* Values: +* - PWM1_INVERT_LINE - Inverts the line output +* - PWM1_INVERT_LINE_N - Inverts the line_n output +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetPWMInvert(uint32 mask) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_CONTROL_REG &= (uint32)~PWM1_INV_OUT_MASK; + PWM1_CONTROL_REG |= mask; + + CyExitCriticalSection(enableInterrupts); +} + + + +/******************************************************************************* +* Function Name: PWM1_WriteCounter +******************************************************************************** +* +* Summary: +* Writes a new 16bit counter value directly into the counter register, thus +* setting the counter (not the period) to the value written. It is not +* advised to write to this field when the counter is running. +* +* Parameters: +* count: value to write +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_WriteCounter(uint32 count) +{ + PWM1_COUNTER_REG = (count & PWM1_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM1_ReadCounter +******************************************************************************** +* +* Summary: +* Reads the current counter value. +* +* Parameters: +* None +* +* Return: +* Current counter value +* +*******************************************************************************/ +uint32 PWM1_ReadCounter(void) +{ + return (PWM1_COUNTER_REG & PWM1_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM1_SetCounterMode +******************************************************************************** +* +* Summary: +* Sets the counter mode. Applicable to all modes except Quadrature Decoder +* and the PWM with a pseudo random output. +* +* Parameters: +* counterMode: Enumerated counter type values +* Values: +* - PWM1_COUNT_UP - Counts up +* - PWM1_COUNT_DOWN - Counts down +* - PWM1_COUNT_UPDOWN0 - Counts up and down. Terminal count +* generated when counter reaches 0 +* - PWM1_COUNT_UPDOWN1 - Counts up and down. Terminal count +* generated both when counter reaches 0 +* and period +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetCounterMode(uint32 counterMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_CONTROL_REG &= (uint32)~PWM1_UPDOWN_MASK; + PWM1_CONTROL_REG |= counterMode; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_WritePeriod +******************************************************************************** +* +* Summary: +* Writes the 16 bit period register with the new period value. +* To cause the counter to count for N cycles this register should be written +* with N-1 (counts from 0 to period inclusive). +* +* Parameters: +* period: Period value +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_WritePeriod(uint32 period) +{ + PWM1_PERIOD_REG = (period & PWM1_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM1_ReadPeriod +******************************************************************************** +* +* Summary: +* Reads the 16 bit period register. +* +* Parameters: +* None +* +* Return: +* Period value +* +*******************************************************************************/ +uint32 PWM1_ReadPeriod(void) +{ + return (PWM1_PERIOD_REG & PWM1_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM1_SetCompareSwap +******************************************************************************** +* +* Summary: +* Writes the register that controls whether the compare registers are +* swapped. When enabled in the Timer/Counter mode(without capture) the swap +* occurs at a TC event. In the PWM mode the swap occurs at the next TC event +* following a hardware switch event. +* +* Parameters: +* swapEnable +* Values: +* - 0 - Disable swap +* - 1 - Enable swap +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetCompareSwap(uint32 swapEnable) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_CONTROL_REG &= (uint32)~PWM1_RELOAD_CC_MASK; + PWM1_CONTROL_REG |= (swapEnable & PWM1_1BIT_MASK); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_WritePeriodBuf +******************************************************************************** +* +* Summary: +* Writes the 16 bit period buf register with the new period value. +* +* Parameters: +* periodBuf: Period value +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_WritePeriodBuf(uint32 periodBuf) +{ + PWM1_PERIOD_BUF_REG = (periodBuf & PWM1_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM1_ReadPeriodBuf +******************************************************************************** +* +* Summary: +* Reads the 16 bit period buf register. +* +* Parameters: +* None +* +* Return: +* Period value +* +*******************************************************************************/ +uint32 PWM1_ReadPeriodBuf(void) +{ + return (PWM1_PERIOD_BUF_REG & PWM1_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM1_SetPeriodSwap +******************************************************************************** +* +* Summary: +* Writes the register that controls whether the period registers are +* swapped. When enabled in Timer/Counter mode the swap occurs at a TC event. +* In the PWM mode the swap occurs at the next TC event following a hardware +* switch event. +* +* Parameters: +* swapEnable +* Values: +* - 0 - Disable swap +* - 1 - Enable swap +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetPeriodSwap(uint32 swapEnable) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_CONTROL_REG &= (uint32)~PWM1_RELOAD_PERIOD_MASK; + PWM1_CONTROL_REG |= ((uint32)((swapEnable & PWM1_1BIT_MASK) << + PWM1_RELOAD_PERIOD_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_WriteCompare +******************************************************************************** +* +* Summary: +* Writes the 16 bit compare register with the new compare value. Not +* applicable for Timer/Counter with Capture or in Quadrature Decoder modes. +* +* Parameters: +* compare: Compare value +* +* Return: +* None +* +* Note: +* It is not recommended to use the value equal to "0" or equal to +* "period value" in Center or Asymmetric align PWM modes on the +* PSoC 4100/PSoC 4200 devices. +* PSoC 4000 devices write the 16 bit compare register with the decremented +* compare value in the Up counting mode (except 0x0u), and the incremented +* compare value in the Down counting mode (except 0xFFFFu). +* +*******************************************************************************/ +void PWM1_WriteCompare(uint32 compare) +{ + #if (PWM1_CY_TCPWM_4000) + uint32 currentMode; + #endif /* (PWM1_CY_TCPWM_4000) */ + + #if (PWM1_CY_TCPWM_4000) + currentMode = ((PWM1_CONTROL_REG & PWM1_UPDOWN_MASK) >> PWM1_UPDOWN_SHIFT); + + if (((uint32)PWM1__COUNT_DOWN == currentMode) && (0xFFFFu != compare)) + { + compare++; + } + else if (((uint32)PWM1__COUNT_UP == currentMode) && (0u != compare)) + { + compare--; + } + else + { + } + + + #endif /* (PWM1_CY_TCPWM_4000) */ + + PWM1_COMP_CAP_REG = (compare & PWM1_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM1_ReadCompare +******************************************************************************** +* +* Summary: +* Reads the compare register. Not applicable for Timer/Counter with Capture +* or in Quadrature Decoder modes. +* PSoC 4000 devices read the incremented compare register value in the +* Up counting mode (except 0xFFFFu), and the decremented value in the +* Down counting mode (except 0x0u). +* +* Parameters: +* None +* +* Return: +* Compare value +* +* Note: +* PSoC 4000 devices read the incremented compare register value in the +* Up counting mode (except 0xFFFFu), and the decremented value in the +* Down counting mode (except 0x0u). +* +*******************************************************************************/ +uint32 PWM1_ReadCompare(void) +{ + #if (PWM1_CY_TCPWM_4000) + uint32 currentMode; + uint32 regVal; + #endif /* (PWM1_CY_TCPWM_4000) */ + + #if (PWM1_CY_TCPWM_4000) + currentMode = ((PWM1_CONTROL_REG & PWM1_UPDOWN_MASK) >> PWM1_UPDOWN_SHIFT); + + regVal = PWM1_COMP_CAP_REG; + + if (((uint32)PWM1__COUNT_DOWN == currentMode) && (0u != regVal)) + { + regVal--; + } + else if (((uint32)PWM1__COUNT_UP == currentMode) && (0xFFFFu != regVal)) + { + regVal++; + } + else + { + } + + return (regVal & PWM1_16BIT_MASK); + #else + return (PWM1_COMP_CAP_REG & PWM1_16BIT_MASK); + #endif /* (PWM1_CY_TCPWM_4000) */ +} + + +/******************************************************************************* +* Function Name: PWM1_WriteCompareBuf +******************************************************************************** +* +* Summary: +* Writes the 16 bit compare buffer register with the new compare value. Not +* applicable for Timer/Counter with Capture or in Quadrature Decoder modes. +* +* Parameters: +* compareBuf: Compare value +* +* Return: +* None +* +* Note: +* It is not recommended to use the value equal to "0" or equal to +* "period value" in Center or Asymmetric align PWM modes on the +* PSoC 4100/PSoC 4200 devices. +* PSoC 4000 devices write the 16 bit compare register with the decremented +* compare value in the Up counting mode (except 0x0u), and the incremented +* compare value in the Down counting mode (except 0xFFFFu). +* +*******************************************************************************/ +void PWM1_WriteCompareBuf(uint32 compareBuf) +{ + #if (PWM1_CY_TCPWM_4000) + uint32 currentMode; + #endif /* (PWM1_CY_TCPWM_4000) */ + + #if (PWM1_CY_TCPWM_4000) + currentMode = ((PWM1_CONTROL_REG & PWM1_UPDOWN_MASK) >> PWM1_UPDOWN_SHIFT); + + if (((uint32)PWM1__COUNT_DOWN == currentMode) && (0xFFFFu != compareBuf)) + { + compareBuf++; + } + else if (((uint32)PWM1__COUNT_UP == currentMode) && (0u != compareBuf)) + { + compareBuf --; + } + else + { + } + #endif /* (PWM1_CY_TCPWM_4000) */ + + PWM1_COMP_CAP_BUF_REG = (compareBuf & PWM1_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM1_ReadCompareBuf +******************************************************************************** +* +* Summary: +* Reads the compare buffer register. Not applicable for Timer/Counter with +* Capture or in Quadrature Decoder modes. +* +* Parameters: +* None +* +* Return: +* Compare buffer value +* +* Note: +* PSoC 4000 devices read the incremented compare register value in the +* Up counting mode (except 0xFFFFu), and the decremented value in the +* Down counting mode (except 0x0u). +* +*******************************************************************************/ +uint32 PWM1_ReadCompareBuf(void) +{ + #if (PWM1_CY_TCPWM_4000) + uint32 currentMode; + uint32 regVal; + #endif /* (PWM1_CY_TCPWM_4000) */ + + #if (PWM1_CY_TCPWM_4000) + currentMode = ((PWM1_CONTROL_REG & PWM1_UPDOWN_MASK) >> PWM1_UPDOWN_SHIFT); + + regVal = PWM1_COMP_CAP_BUF_REG; + + if (((uint32)PWM1__COUNT_DOWN == currentMode) && (0u != regVal)) + { + regVal--; + } + else if (((uint32)PWM1__COUNT_UP == currentMode) && (0xFFFFu != regVal)) + { + regVal++; + } + else + { + } + + return (regVal & PWM1_16BIT_MASK); + #else + return (PWM1_COMP_CAP_BUF_REG & PWM1_16BIT_MASK); + #endif /* (PWM1_CY_TCPWM_4000) */ +} + + +/******************************************************************************* +* Function Name: PWM1_ReadCapture +******************************************************************************** +* +* Summary: +* Reads the captured counter value. This API is applicable only for +* Timer/Counter with the capture mode and Quadrature Decoder modes. +* +* Parameters: +* None +* +* Return: +* Capture value +* +*******************************************************************************/ +uint32 PWM1_ReadCapture(void) +{ + return (PWM1_COMP_CAP_REG & PWM1_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM1_ReadCaptureBuf +******************************************************************************** +* +* Summary: +* Reads the capture buffer register. This API is applicable only for +* Timer/Counter with the capture mode and Quadrature Decoder modes. +* +* Parameters: +* None +* +* Return: +* Capture buffer value +* +*******************************************************************************/ +uint32 PWM1_ReadCaptureBuf(void) +{ + return (PWM1_COMP_CAP_BUF_REG & PWM1_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM1_SetCaptureMode +******************************************************************************** +* +* Summary: +* Sets the capture trigger mode. For PWM mode this is the switch input. +* This input is not applicable to the Timer/Counter without Capture and +* Quadrature Decoder modes. +* +* Parameters: +* triggerMode: Enumerated trigger mode value +* Values: +* - PWM1_TRIG_LEVEL - Level +* - PWM1_TRIG_RISING - Rising edge +* - PWM1_TRIG_FALLING - Falling edge +* - PWM1_TRIG_BOTH - Both rising and falling edge +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetCaptureMode(uint32 triggerMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_TRIG_CONTROL1_REG &= (uint32)~PWM1_CAPTURE_MASK; + PWM1_TRIG_CONTROL1_REG |= triggerMode; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetReloadMode +******************************************************************************** +* +* Summary: +* Sets the reload trigger mode. For Quadrature Decoder mode this is the index +* input. +* +* Parameters: +* triggerMode: Enumerated trigger mode value +* Values: +* - PWM1_TRIG_LEVEL - Level +* - PWM1_TRIG_RISING - Rising edge +* - PWM1_TRIG_FALLING - Falling edge +* - PWM1_TRIG_BOTH - Both rising and falling edge +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetReloadMode(uint32 triggerMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_TRIG_CONTROL1_REG &= (uint32)~PWM1_RELOAD_MASK; + PWM1_TRIG_CONTROL1_REG |= ((uint32)(triggerMode << PWM1_RELOAD_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetStartMode +******************************************************************************** +* +* Summary: +* Sets the start trigger mode. For Quadrature Decoder mode this is the +* phiB input. +* +* Parameters: +* triggerMode: Enumerated trigger mode value +* Values: +* - PWM1_TRIG_LEVEL - Level +* - PWM1_TRIG_RISING - Rising edge +* - PWM1_TRIG_FALLING - Falling edge +* - PWM1_TRIG_BOTH - Both rising and falling edge +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetStartMode(uint32 triggerMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_TRIG_CONTROL1_REG &= (uint32)~PWM1_START_MASK; + PWM1_TRIG_CONTROL1_REG |= ((uint32)(triggerMode << PWM1_START_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetStopMode +******************************************************************************** +* +* Summary: +* Sets the stop trigger mode. For PWM mode this is the kill input. +* +* Parameters: +* triggerMode: Enumerated trigger mode value +* Values: +* - PWM1_TRIG_LEVEL - Level +* - PWM1_TRIG_RISING - Rising edge +* - PWM1_TRIG_FALLING - Falling edge +* - PWM1_TRIG_BOTH - Both rising and falling edge +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetStopMode(uint32 triggerMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_TRIG_CONTROL1_REG &= (uint32)~PWM1_STOP_MASK; + PWM1_TRIG_CONTROL1_REG |= ((uint32)(triggerMode << PWM1_STOP_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_SetCountMode +******************************************************************************** +* +* Summary: +* Sets the count trigger mode. For Quadrature Decoder mode this is the phiA +* input. +* +* Parameters: +* triggerMode: Enumerated trigger mode value +* Values: +* - PWM1_TRIG_LEVEL - Level +* - PWM1_TRIG_RISING - Rising edge +* - PWM1_TRIG_FALLING - Falling edge +* - PWM1_TRIG_BOTH - Both rising and falling edge +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetCountMode(uint32 triggerMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_TRIG_CONTROL1_REG &= (uint32)~PWM1_COUNT_MASK; + PWM1_TRIG_CONTROL1_REG |= ((uint32)(triggerMode << PWM1_COUNT_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_TriggerCommand +******************************************************************************** +* +* Summary: +* Triggers the designated command to occur on the designated TCPWM instances. +* The mask can be used to apply this command simultaneously to more than one +* instance. This allows multiple TCPWM instances to be synchronized. +* +* Parameters: +* mask: A combination of mask bits for each instance of the TCPWM that the +* command should apply to. This function from one instance can be used +* to apply the command to any of the instances in the design. +* The mask value for a specific instance is available with the MASK +* define. +* command: Enumerated command values. Capture command only applicable for +* Timer/Counter with Capture and PWM modes. +* Values: +* - PWM1_CMD_CAPTURE - Trigger Capture/Switch command +* - PWM1_CMD_RELOAD - Trigger Reload/Index command +* - PWM1_CMD_STOP - Trigger Stop/Kill command +* - PWM1_CMD_START - Trigger Start/phiB command +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_TriggerCommand(uint32 mask, uint32 command) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM1_COMMAND_REG = ((uint32)(mask << command)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM1_ReadStatus +******************************************************************************** +* +* Summary: +* Reads the status of the PWM1. +* +* Parameters: +* None +* +* Return: +* Status +* Values: +* - PWM1_STATUS_DOWN - Set if counting down +* - PWM1_STATUS_RUNNING - Set if counter is running +* +*******************************************************************************/ +uint32 PWM1_ReadStatus(void) +{ + return ((PWM1_STATUS_REG >> PWM1_RUNNING_STATUS_SHIFT) | + (PWM1_STATUS_REG & PWM1_STATUS_DOWN)); +} + + +/******************************************************************************* +* Function Name: PWM1_SetInterruptMode +******************************************************************************** +* +* Summary: +* Sets the interrupt mask to control which interrupt +* requests generate the interrupt signal. +* +* Parameters: +* interruptMask: Mask of bits to be enabled +* Values: +* - PWM1_INTR_MASK_TC - Terminal count mask +* - PWM1_INTR_MASK_CC_MATCH - Compare count / capture mask +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetInterruptMode(uint32 interruptMask) +{ + PWM1_INTERRUPT_MASK_REG = interruptMask; +} + + +/******************************************************************************* +* Function Name: PWM1_GetInterruptSourceMasked +******************************************************************************** +* +* Summary: +* Gets the interrupt requests masked by the interrupt mask. +* +* Parameters: +* None +* +* Return: +* Masked interrupt source +* Values: +* - PWM1_INTR_MASK_TC - Terminal count mask +* - PWM1_INTR_MASK_CC_MATCH - Compare count / capture mask +* +*******************************************************************************/ +uint32 PWM1_GetInterruptSourceMasked(void) +{ + return (PWM1_INTERRUPT_MASKED_REG); +} + + +/******************************************************************************* +* Function Name: PWM1_GetInterruptSource +******************************************************************************** +* +* Summary: +* Gets the interrupt requests (without masking). +* +* Parameters: +* None +* +* Return: +* Interrupt request value +* Values: +* - PWM1_INTR_MASK_TC - Terminal count mask +* - PWM1_INTR_MASK_CC_MATCH - Compare count / capture mask +* +*******************************************************************************/ +uint32 PWM1_GetInterruptSource(void) +{ + return (PWM1_INTERRUPT_REQ_REG); +} + + +/******************************************************************************* +* Function Name: PWM1_ClearInterrupt +******************************************************************************** +* +* Summary: +* Clears the interrupt request. +* +* Parameters: +* interruptMask: Mask of interrupts to clear +* Values: +* - PWM1_INTR_MASK_TC - Terminal count mask +* - PWM1_INTR_MASK_CC_MATCH - Compare count / capture mask +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_ClearInterrupt(uint32 interruptMask) +{ + PWM1_INTERRUPT_REQ_REG = interruptMask; +} + + +/******************************************************************************* +* Function Name: PWM1_SetInterrupt +******************************************************************************** +* +* Summary: +* Sets a software interrupt request. +* +* Parameters: +* interruptMask: Mask of interrupts to set +* Values: +* - PWM1_INTR_MASK_TC - Terminal count mask +* - PWM1_INTR_MASK_CC_MATCH - Compare count / capture mask +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SetInterrupt(uint32 interruptMask) +{ + PWM1_INTERRUPT_SET_REG = interruptMask; +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/PWM1.h b/cores/asr650x/cores/PWM1.h new file mode 100644 index 00000000..fc4ba704 --- /dev/null +++ b/cores/asr650x/cores/PWM1.h @@ -0,0 +1,583 @@ +/******************************************************************************* +* File Name: PWM1.h +* Version 2.10 +* +* Description: +* This file provides constants and parameter values for the PWM1 +* component. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2013-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_TCPWM_PWM1_H) +#define CY_TCPWM_PWM1_H + + +#include "CyLib.h" +#include "cytypes.h" +#include "cyfitter.h" + + +/* PWM1 */ +#define PWM1_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT5_CC +#define PWM1_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT5_CC_BUFF +#define PWM1_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT5_COUNTER +#define PWM1_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT5_CTRL +#define PWM1_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT5_INTR +#define PWM1_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT5_INTR_MASK +#define PWM1_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT5_INTR_MASKED +#define PWM1_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT5_INTR_SET +#define PWM1_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT5_PERIOD +#define PWM1_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT5_PERIOD_BUFF +#define PWM1_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT5_STATUS +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x20u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 5u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x2000u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 13u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x20000000u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 29u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x200000u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 21u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x20u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 5u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x20u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 5u +#define PWM1_cy_m0s8_tcpwm_1__TCPWM_NUMBER 5u +#define PWM1_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT5_TR_CTRL0 +#define PWM1_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT5_TR_CTRL1 +#define PWM1_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT5_TR_CTRL2 + +/* ClockPWM1 */ +#define ClockPWM1__CTRL_REGISTER CYREG_PERI_PCLK_CTL11 +#define ClockPWM1__DIV_ID 0x00000041u +#define ClockPWM1__DIV_REGISTER CYREG_PERI_DIV_16_CTL1 +#define ClockPWM1__PA_DIV_ID 0x000000FFu + + +/******************************************************************************* +* Internal Type defines +*******************************************************************************/ + +/* Structure to save state before go to sleep */ +typedef struct +{ + uint8 enableState; +} PWM1_BACKUP_STRUCT; + + +/******************************************************************************* +* Variables +*******************************************************************************/ +extern uint8 PWM1_initVar; + + +/*************************************** +* Conditional Compilation Parameters +****************************************/ + +#define PWM1_CY_TCPWM_V2 (CYIPBLOCK_m0s8tcpwm_VERSION == 2u) +#define PWM1_CY_TCPWM_4000 (CY_PSOC4_4000) + +/* TCPWM Configuration */ +#define PWM1_CONFIG (7lu) + +/* Quad Mode */ +/* Parameters */ +#define PWM1_QUAD_ENCODING_MODES (0lu) +#define PWM1_QUAD_AUTO_START (0lu) + +/* Signal modes */ +#define PWM1_QUAD_INDEX_SIGNAL_MODE (0lu) +#define PWM1_QUAD_PHIA_SIGNAL_MODE (3lu) +#define PWM1_QUAD_PHIB_SIGNAL_MODE (3lu) +#define PWM1_QUAD_STOP_SIGNAL_MODE (0lu) + +/* Signal present */ +#define PWM1_QUAD_INDEX_SIGNAL_PRESENT (0lu) +#define PWM1_QUAD_STOP_SIGNAL_PRESENT (0lu) + +/* Interrupt Mask */ +#define PWM1_QUAD_INTERRUPT_MASK (1lu) + +/* Timer/Counter Mode */ +/* Parameters */ +#define PWM1_TC_RUN_MODE (0lu) +#define PWM1_TC_COUNTER_MODE (0lu) +#define PWM1_TC_COMP_CAP_MODE (2lu) +#define PWM1_TC_PRESCALER (0lu) + +/* Signal modes */ +#define PWM1_TC_RELOAD_SIGNAL_MODE (0lu) +#define PWM1_TC_COUNT_SIGNAL_MODE (3lu) +#define PWM1_TC_START_SIGNAL_MODE (0lu) +#define PWM1_TC_STOP_SIGNAL_MODE (0lu) +#define PWM1_TC_CAPTURE_SIGNAL_MODE (0lu) + +/* Signal present */ +#define PWM1_TC_RELOAD_SIGNAL_PRESENT (0lu) +#define PWM1_TC_COUNT_SIGNAL_PRESENT (0lu) +#define PWM1_TC_START_SIGNAL_PRESENT (0lu) +#define PWM1_TC_STOP_SIGNAL_PRESENT (0lu) +#define PWM1_TC_CAPTURE_SIGNAL_PRESENT (0lu) + +/* Interrupt Mask */ +#define PWM1_TC_INTERRUPT_MASK (1lu) + +/* PWM Mode */ +/* Parameters */ +#define PWM1_PWM_KILL_EVENT (0lu) +#define PWM1_PWM_STOP_EVENT (0lu) +#define PWM1_PWM_MODE (4lu) +#define PWM1_PWM_OUT_N_INVERT (0lu) +#define PWM1_PWM_OUT_INVERT (0lu) +#define PWM1_PWM_ALIGN (0lu) +#define PWM1_PWM_RUN_MODE (0lu) +#define PWM1_PWM_DEAD_TIME_CYCLE (0lu) +#define PWM1_PWM_PRESCALER (0lu) + +/* Signal modes */ +#define PWM1_PWM_RELOAD_SIGNAL_MODE (0lu) +#define PWM1_PWM_COUNT_SIGNAL_MODE (3lu) +#define PWM1_PWM_START_SIGNAL_MODE (0lu) +#define PWM1_PWM_STOP_SIGNAL_MODE (0lu) +#define PWM1_PWM_SWITCH_SIGNAL_MODE (0lu) + +/* Signal present */ +#define PWM1_PWM_RELOAD_SIGNAL_PRESENT (0lu) +#define PWM1_PWM_COUNT_SIGNAL_PRESENT (0lu) +#define PWM1_PWM_START_SIGNAL_PRESENT (0lu) +#define PWM1_PWM_STOP_SIGNAL_PRESENT (0lu) +#define PWM1_PWM_SWITCH_SIGNAL_PRESENT (0lu) + +/* Interrupt Mask */ +#define PWM1_PWM_INTERRUPT_MASK (1lu) + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +/* Timer/Counter Mode */ +#define PWM1_TC_PERIOD_VALUE (65535lu) +#define PWM1_TC_COMPARE_VALUE (65535lu) +#define PWM1_TC_COMPARE_BUF_VALUE (65535lu) +#define PWM1_TC_COMPARE_SWAP (0lu) + +/* PWM Mode */ +#define PWM1_PWM_PERIOD_VALUE (63000lu) +#define PWM1_PWM_PERIOD_BUF_VALUE (65535lu) +#define PWM1_PWM_PERIOD_SWAP (0lu) +#define PWM1_PWM_COMPARE_VALUE (0lu) +#define PWM1_PWM_COMPARE_BUF_VALUE (65535lu) +#define PWM1_PWM_COMPARE_SWAP (0lu) + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +#define PWM1__LEFT 0 +#define PWM1__RIGHT 1 +#define PWM1__CENTER 2 +#define PWM1__ASYMMETRIC 3 + +#define PWM1__X1 0 +#define PWM1__X2 1 +#define PWM1__X4 2 + +#define PWM1__PWM 4 +#define PWM1__PWM_DT 5 +#define PWM1__PWM_PR 6 + +#define PWM1__INVERSE 1 +#define PWM1__DIRECT 0 + +#define PWM1__CAPTURE 2 +#define PWM1__COMPARE 0 + +#define PWM1__TRIG_LEVEL 3 +#define PWM1__TRIG_RISING 0 +#define PWM1__TRIG_FALLING 1 +#define PWM1__TRIG_BOTH 2 + +#define PWM1__INTR_MASK_TC 1 +#define PWM1__INTR_MASK_CC_MATCH 2 +#define PWM1__INTR_MASK_NONE 0 +#define PWM1__INTR_MASK_TC_CC 3 + +#define PWM1__UNCONFIG 8 +#define PWM1__TIMER 1 +#define PWM1__QUAD 3 +#define PWM1__PWM_SEL 7 + +#define PWM1__COUNT_UP 0 +#define PWM1__COUNT_DOWN 1 +#define PWM1__COUNT_UPDOWN0 2 +#define PWM1__COUNT_UPDOWN1 3 + + +/* Prescaler */ +#define PWM1_PRESCALE_DIVBY1 ((uint32)(0u << PWM1_PRESCALER_SHIFT)) +#define PWM1_PRESCALE_DIVBY2 ((uint32)(1u << PWM1_PRESCALER_SHIFT)) +#define PWM1_PRESCALE_DIVBY4 ((uint32)(2u << PWM1_PRESCALER_SHIFT)) +#define PWM1_PRESCALE_DIVBY8 ((uint32)(3u << PWM1_PRESCALER_SHIFT)) +#define PWM1_PRESCALE_DIVBY16 ((uint32)(4u << PWM1_PRESCALER_SHIFT)) +#define PWM1_PRESCALE_DIVBY32 ((uint32)(5u << PWM1_PRESCALER_SHIFT)) +#define PWM1_PRESCALE_DIVBY64 ((uint32)(6u << PWM1_PRESCALER_SHIFT)) +#define PWM1_PRESCALE_DIVBY128 ((uint32)(7u << PWM1_PRESCALER_SHIFT)) + +/* TCPWM set modes */ +#define PWM1_MODE_TIMER_COMPARE ((uint32)(PWM1__COMPARE << \ + PWM1_MODE_SHIFT)) +#define PWM1_MODE_TIMER_CAPTURE ((uint32)(PWM1__CAPTURE << \ + PWM1_MODE_SHIFT)) +#define PWM1_MODE_QUAD ((uint32)(PWM1__QUAD << \ + PWM1_MODE_SHIFT)) +#define PWM1_MODE_PWM ((uint32)(PWM1__PWM << \ + PWM1_MODE_SHIFT)) +#define PWM1_MODE_PWM_DT ((uint32)(PWM1__PWM_DT << \ + PWM1_MODE_SHIFT)) +#define PWM1_MODE_PWM_PR ((uint32)(PWM1__PWM_PR << \ + PWM1_MODE_SHIFT)) + +/* Quad Modes */ +#define PWM1_MODE_X1 ((uint32)(PWM1__X1 << \ + PWM1_QUAD_MODE_SHIFT)) +#define PWM1_MODE_X2 ((uint32)(PWM1__X2 << \ + PWM1_QUAD_MODE_SHIFT)) +#define PWM1_MODE_X4 ((uint32)(PWM1__X4 << \ + PWM1_QUAD_MODE_SHIFT)) + +/* Counter modes */ +#define PWM1_COUNT_UP ((uint32)(PWM1__COUNT_UP << \ + PWM1_UPDOWN_SHIFT)) +#define PWM1_COUNT_DOWN ((uint32)(PWM1__COUNT_DOWN << \ + PWM1_UPDOWN_SHIFT)) +#define PWM1_COUNT_UPDOWN0 ((uint32)(PWM1__COUNT_UPDOWN0 << \ + PWM1_UPDOWN_SHIFT)) +#define PWM1_COUNT_UPDOWN1 ((uint32)(PWM1__COUNT_UPDOWN1 << \ + PWM1_UPDOWN_SHIFT)) + +/* PWM output invert */ +#define PWM1_INVERT_LINE ((uint32)(PWM1__INVERSE << \ + PWM1_INV_OUT_SHIFT)) +#define PWM1_INVERT_LINE_N ((uint32)(PWM1__INVERSE << \ + PWM1_INV_COMPL_OUT_SHIFT)) + +/* Trigger modes */ +#define PWM1_TRIG_RISING ((uint32)PWM1__TRIG_RISING) +#define PWM1_TRIG_FALLING ((uint32)PWM1__TRIG_FALLING) +#define PWM1_TRIG_BOTH ((uint32)PWM1__TRIG_BOTH) +#define PWM1_TRIG_LEVEL ((uint32)PWM1__TRIG_LEVEL) + +/* Interrupt mask */ +#define PWM1_INTR_MASK_TC ((uint32)PWM1__INTR_MASK_TC) +#define PWM1_INTR_MASK_CC_MATCH ((uint32)PWM1__INTR_MASK_CC_MATCH) + +/* PWM Output Controls */ +#define PWM1_CC_MATCH_SET (0x00u) +#define PWM1_CC_MATCH_CLEAR (0x01u) +#define PWM1_CC_MATCH_INVERT (0x02u) +#define PWM1_CC_MATCH_NO_CHANGE (0x03u) +#define PWM1_OVERLOW_SET (0x00u) +#define PWM1_OVERLOW_CLEAR (0x04u) +#define PWM1_OVERLOW_INVERT (0x08u) +#define PWM1_OVERLOW_NO_CHANGE (0x0Cu) +#define PWM1_UNDERFLOW_SET (0x00u) +#define PWM1_UNDERFLOW_CLEAR (0x10u) +#define PWM1_UNDERFLOW_INVERT (0x20u) +#define PWM1_UNDERFLOW_NO_CHANGE (0x30u) + +/* PWM Align */ +#define PWM1_PWM_MODE_LEFT (PWM1_CC_MATCH_CLEAR | \ + PWM1_OVERLOW_SET | \ + PWM1_UNDERFLOW_NO_CHANGE) +#define PWM1_PWM_MODE_RIGHT (PWM1_CC_MATCH_SET | \ + PWM1_OVERLOW_NO_CHANGE | \ + PWM1_UNDERFLOW_CLEAR) +#define PWM1_PWM_MODE_ASYM (PWM1_CC_MATCH_INVERT | \ + PWM1_OVERLOW_SET | \ + PWM1_UNDERFLOW_CLEAR) + +#if (PWM1_CY_TCPWM_V2) + #if(PWM1_CY_TCPWM_4000) + #define PWM1_PWM_MODE_CENTER (PWM1_CC_MATCH_INVERT | \ + PWM1_OVERLOW_NO_CHANGE | \ + PWM1_UNDERFLOW_CLEAR) + #else + #define PWM1_PWM_MODE_CENTER (PWM1_CC_MATCH_INVERT | \ + PWM1_OVERLOW_SET | \ + PWM1_UNDERFLOW_CLEAR) + #endif /* (PWM1_CY_TCPWM_4000) */ +#else + #define PWM1_PWM_MODE_CENTER (PWM1_CC_MATCH_INVERT | \ + PWM1_OVERLOW_NO_CHANGE | \ + PWM1_UNDERFLOW_CLEAR) +#endif /* (PWM1_CY_TCPWM_NEW) */ + +/* Command operations without condition */ +#define PWM1_CMD_CAPTURE (0u) +#define PWM1_CMD_RELOAD (8u) +#define PWM1_CMD_STOP (16u) +#define PWM1_CMD_START (24u) + +/* Status */ +#define PWM1_STATUS_DOWN (1u) +#define PWM1_STATUS_RUNNING (2u) + + +/*************************************** +* Function Prototypes +****************************************/ + +void PWM1_Init(void); +void PWM1_Enable(void); +void PWM1_Start(void); +void PWM1_Stop(void); + +void PWM1_SetMode(uint32 mode); +void PWM1_SetCounterMode(uint32 counterMode); +void PWM1_SetPWMMode(uint32 modeMask); +void PWM1_SetQDMode(uint32 qdMode); + +void PWM1_SetPrescaler(uint32 prescaler); +void PWM1_TriggerCommand(uint32 mask, uint32 command); +void PWM1_SetOneShot(uint32 oneShotEnable); +uint32 PWM1_ReadStatus(void); + +void PWM1_SetPWMSyncKill(uint32 syncKillEnable); +void PWM1_SetPWMStopOnKill(uint32 stopOnKillEnable); +void PWM1_SetPWMDeadTime(uint32 deadTime); +void PWM1_SetPWMInvert(uint32 mask); + +void PWM1_SetInterruptMode(uint32 interruptMask); +uint32 PWM1_GetInterruptSourceMasked(void); +uint32 PWM1_GetInterruptSource(void); +void PWM1_ClearInterrupt(uint32 interruptMask); +void PWM1_SetInterrupt(uint32 interruptMask); + +void PWM1_WriteCounter(uint32 count); +uint32 PWM1_ReadCounter(void); + +uint32 PWM1_ReadCapture(void); +uint32 PWM1_ReadCaptureBuf(void); + +void PWM1_WritePeriod(uint32 period); +uint32 PWM1_ReadPeriod(void); +void PWM1_WritePeriodBuf(uint32 periodBuf); +uint32 PWM1_ReadPeriodBuf(void); + +void PWM1_WriteCompare(uint32 compare); +uint32 PWM1_ReadCompare(void); +void PWM1_WriteCompareBuf(uint32 compareBuf); +uint32 PWM1_ReadCompareBuf(void); + +void PWM1_SetPeriodSwap(uint32 swapEnable); +void PWM1_SetCompareSwap(uint32 swapEnable); + +void PWM1_SetCaptureMode(uint32 triggerMode); +void PWM1_SetReloadMode(uint32 triggerMode); +void PWM1_SetStartMode(uint32 triggerMode); +void PWM1_SetStopMode(uint32 triggerMode); +void PWM1_SetCountMode(uint32 triggerMode); + +void PWM1_SaveConfig(void); +void PWM1_RestoreConfig(void); +void PWM1_Sleep(void); +void PWM1_Wakeup(void); + + +/*************************************** +* Registers +***************************************/ + +#define PWM1_BLOCK_CONTROL_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__TCPWM_CTRL ) +#define PWM1_BLOCK_CONTROL_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__TCPWM_CTRL ) +#define PWM1_COMMAND_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__TCPWM_CMD ) +#define PWM1_COMMAND_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__TCPWM_CMD ) +#define PWM1_INTRRUPT_CAUSE_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE ) +#define PWM1_INTRRUPT_CAUSE_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE ) +#define PWM1_CONTROL_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__CTRL ) +#define PWM1_CONTROL_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__CTRL ) +#define PWM1_STATUS_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__STATUS ) +#define PWM1_STATUS_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__STATUS ) +#define PWM1_COUNTER_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__COUNTER ) +#define PWM1_COUNTER_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__COUNTER ) +#define PWM1_COMP_CAP_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__CC ) +#define PWM1_COMP_CAP_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__CC ) +#define PWM1_COMP_CAP_BUF_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__CC_BUFF ) +#define PWM1_COMP_CAP_BUF_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__CC_BUFF ) +#define PWM1_PERIOD_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__PERIOD ) +#define PWM1_PERIOD_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__PERIOD ) +#define PWM1_PERIOD_BUF_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__PERIOD_BUFF ) +#define PWM1_PERIOD_BUF_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__PERIOD_BUFF ) +#define PWM1_TRIG_CONTROL0_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__TR_CTRL0 ) +#define PWM1_TRIG_CONTROL0_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__TR_CTRL0 ) +#define PWM1_TRIG_CONTROL1_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__TR_CTRL1 ) +#define PWM1_TRIG_CONTROL1_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__TR_CTRL1 ) +#define PWM1_TRIG_CONTROL2_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__TR_CTRL2 ) +#define PWM1_TRIG_CONTROL2_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__TR_CTRL2 ) +#define PWM1_INTERRUPT_REQ_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__INTR ) +#define PWM1_INTERRUPT_REQ_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__INTR ) +#define PWM1_INTERRUPT_SET_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__INTR_SET ) +#define PWM1_INTERRUPT_SET_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__INTR_SET ) +#define PWM1_INTERRUPT_MASK_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__INTR_MASK ) +#define PWM1_INTERRUPT_MASK_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__INTR_MASK ) +#define PWM1_INTERRUPT_MASKED_REG (*(reg32 *) PWM1_cy_m0s8_tcpwm_1__INTR_MASKED ) +#define PWM1_INTERRUPT_MASKED_PTR ( (reg32 *) PWM1_cy_m0s8_tcpwm_1__INTR_MASKED ) + + +/*************************************** +* Registers Constants +***************************************/ + +/* Mask */ +#define PWM1_MASK ((uint32)PWM1_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK) + +/* Shift constants for control register */ +#define PWM1_RELOAD_CC_SHIFT (0u) +#define PWM1_RELOAD_PERIOD_SHIFT (1u) +#define PWM1_PWM_SYNC_KILL_SHIFT (2u) +#define PWM1_PWM_STOP_KILL_SHIFT (3u) +#define PWM1_PRESCALER_SHIFT (8u) +#define PWM1_UPDOWN_SHIFT (16u) +#define PWM1_ONESHOT_SHIFT (18u) +#define PWM1_QUAD_MODE_SHIFT (20u) +#define PWM1_INV_OUT_SHIFT (20u) +#define PWM1_INV_COMPL_OUT_SHIFT (21u) +#define PWM1_MODE_SHIFT (24u) + +/* Mask constants for control register */ +#define PWM1_RELOAD_CC_MASK ((uint32)(PWM1_1BIT_MASK << \ + PWM1_RELOAD_CC_SHIFT)) +#define PWM1_RELOAD_PERIOD_MASK ((uint32)(PWM1_1BIT_MASK << \ + PWM1_RELOAD_PERIOD_SHIFT)) +#define PWM1_PWM_SYNC_KILL_MASK ((uint32)(PWM1_1BIT_MASK << \ + PWM1_PWM_SYNC_KILL_SHIFT)) +#define PWM1_PWM_STOP_KILL_MASK ((uint32)(PWM1_1BIT_MASK << \ + PWM1_PWM_STOP_KILL_SHIFT)) +#define PWM1_PRESCALER_MASK ((uint32)(PWM1_8BIT_MASK << \ + PWM1_PRESCALER_SHIFT)) +#define PWM1_UPDOWN_MASK ((uint32)(PWM1_2BIT_MASK << \ + PWM1_UPDOWN_SHIFT)) +#define PWM1_ONESHOT_MASK ((uint32)(PWM1_1BIT_MASK << \ + PWM1_ONESHOT_SHIFT)) +#define PWM1_QUAD_MODE_MASK ((uint32)(PWM1_3BIT_MASK << \ + PWM1_QUAD_MODE_SHIFT)) +#define PWM1_INV_OUT_MASK ((uint32)(PWM1_2BIT_MASK << \ + PWM1_INV_OUT_SHIFT)) +#define PWM1_MODE_MASK ((uint32)(PWM1_3BIT_MASK << \ + PWM1_MODE_SHIFT)) + +/* Shift constants for trigger control register 1 */ +#define PWM1_CAPTURE_SHIFT (0u) +#define PWM1_COUNT_SHIFT (2u) +#define PWM1_RELOAD_SHIFT (4u) +#define PWM1_STOP_SHIFT (6u) +#define PWM1_START_SHIFT (8u) + +/* Mask constants for trigger control register 1 */ +#define PWM1_CAPTURE_MASK ((uint32)(PWM1_2BIT_MASK << \ + PWM1_CAPTURE_SHIFT)) +#define PWM1_COUNT_MASK ((uint32)(PWM1_2BIT_MASK << \ + PWM1_COUNT_SHIFT)) +#define PWM1_RELOAD_MASK ((uint32)(PWM1_2BIT_MASK << \ + PWM1_RELOAD_SHIFT)) +#define PWM1_STOP_MASK ((uint32)(PWM1_2BIT_MASK << \ + PWM1_STOP_SHIFT)) +#define PWM1_START_MASK ((uint32)(PWM1_2BIT_MASK << \ + PWM1_START_SHIFT)) + +/* MASK */ +#define PWM1_1BIT_MASK ((uint32)0x01u) +#define PWM1_2BIT_MASK ((uint32)0x03u) +#define PWM1_3BIT_MASK ((uint32)0x07u) +#define PWM1_6BIT_MASK ((uint32)0x3Fu) +#define PWM1_8BIT_MASK ((uint32)0xFFu) +#define PWM1_16BIT_MASK ((uint32)0xFFFFu) + +/* Shift constant for status register */ +#define PWM1_RUNNING_STATUS_SHIFT (30u) + + +/*************************************** +* Initial Constants +***************************************/ + +#define PWM1_CTRL_QUAD_BASE_CONFIG \ + (((uint32)(PWM1_QUAD_ENCODING_MODES << PWM1_QUAD_MODE_SHIFT)) |\ + ((uint32)(PWM1_CONFIG << PWM1_MODE_SHIFT))) + +#define PWM1_CTRL_PWM_BASE_CONFIG \ + (((uint32)(PWM1_PWM_STOP_EVENT << PWM1_PWM_STOP_KILL_SHIFT)) |\ + ((uint32)(PWM1_PWM_OUT_INVERT << PWM1_INV_OUT_SHIFT)) |\ + ((uint32)(PWM1_PWM_OUT_N_INVERT << PWM1_INV_COMPL_OUT_SHIFT)) |\ + ((uint32)(PWM1_PWM_MODE << PWM1_MODE_SHIFT))) + +#define PWM1_CTRL_PWM_RUN_MODE \ + ((uint32)(PWM1_PWM_RUN_MODE << PWM1_ONESHOT_SHIFT)) + +#define PWM1_CTRL_PWM_ALIGN \ + ((uint32)(PWM1_PWM_ALIGN << PWM1_UPDOWN_SHIFT)) + +#define PWM1_CTRL_PWM_KILL_EVENT \ + ((uint32)(PWM1_PWM_KILL_EVENT << PWM1_PWM_SYNC_KILL_SHIFT)) + +#define PWM1_CTRL_PWM_DEAD_TIME_CYCLE \ + ((uint32)(PWM1_PWM_DEAD_TIME_CYCLE << PWM1_PRESCALER_SHIFT)) + +#define PWM1_CTRL_PWM_PRESCALER \ + ((uint32)(PWM1_PWM_PRESCALER << PWM1_PRESCALER_SHIFT)) + +#define PWM1_CTRL_TIMER_BASE_CONFIG \ + (((uint32)(PWM1_TC_PRESCALER << PWM1_PRESCALER_SHIFT)) |\ + ((uint32)(PWM1_TC_COUNTER_MODE << PWM1_UPDOWN_SHIFT)) |\ + ((uint32)(PWM1_TC_RUN_MODE << PWM1_ONESHOT_SHIFT)) |\ + ((uint32)(PWM1_TC_COMP_CAP_MODE << PWM1_MODE_SHIFT))) + +#define PWM1_QUAD_SIGNALS_MODES \ + (((uint32)(PWM1_QUAD_PHIA_SIGNAL_MODE << PWM1_COUNT_SHIFT)) |\ + ((uint32)(PWM1_QUAD_INDEX_SIGNAL_MODE << PWM1_RELOAD_SHIFT)) |\ + ((uint32)(PWM1_QUAD_STOP_SIGNAL_MODE << PWM1_STOP_SHIFT)) |\ + ((uint32)(PWM1_QUAD_PHIB_SIGNAL_MODE << PWM1_START_SHIFT))) + +#define PWM1_PWM_SIGNALS_MODES \ + (((uint32)(PWM1_PWM_SWITCH_SIGNAL_MODE << PWM1_CAPTURE_SHIFT)) |\ + ((uint32)(PWM1_PWM_COUNT_SIGNAL_MODE << PWM1_COUNT_SHIFT)) |\ + ((uint32)(PWM1_PWM_RELOAD_SIGNAL_MODE << PWM1_RELOAD_SHIFT)) |\ + ((uint32)(PWM1_PWM_STOP_SIGNAL_MODE << PWM1_STOP_SHIFT)) |\ + ((uint32)(PWM1_PWM_START_SIGNAL_MODE << PWM1_START_SHIFT))) + +#define PWM1_TIMER_SIGNALS_MODES \ + (((uint32)(PWM1_TC_CAPTURE_SIGNAL_MODE << PWM1_CAPTURE_SHIFT)) |\ + ((uint32)(PWM1_TC_COUNT_SIGNAL_MODE << PWM1_COUNT_SHIFT)) |\ + ((uint32)(PWM1_TC_RELOAD_SIGNAL_MODE << PWM1_RELOAD_SHIFT)) |\ + ((uint32)(PWM1_TC_STOP_SIGNAL_MODE << PWM1_STOP_SHIFT)) |\ + ((uint32)(PWM1_TC_START_SIGNAL_MODE << PWM1_START_SHIFT))) + +#define PWM1_TIMER_UPDOWN_CNT_USED \ + ((PWM1__COUNT_UPDOWN0 == PWM1_TC_COUNTER_MODE) ||\ + (PWM1__COUNT_UPDOWN1 == PWM1_TC_COUNTER_MODE)) + +#define PWM1_PWM_UPDOWN_CNT_USED \ + ((PWM1__CENTER == PWM1_PWM_ALIGN) ||\ + (PWM1__ASYMMETRIC == PWM1_PWM_ALIGN)) + +#define PWM1_PWM_PR_INIT_VALUE (1u) +#define PWM1_QUAD_PERIOD_INIT_VALUE (0x8000u) + + + +#endif /* End CY_TCPWM_PWM1_H */ + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/PWM1_ISR.c b/cores/asr650x/cores/PWM1_ISR.c new file mode 100644 index 00000000..be1942c2 --- /dev/null +++ b/cores/asr650x/cores/PWM1_ISR.c @@ -0,0 +1,406 @@ +/******************************************************************************* +* File Name: PWM1_ISR.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include +#include "cyapicallbacks.h" + +#if !defined(PWM1_ISR__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START PWM1_ISR_intc` */ + +/* `#END` */ + +extern cyisraddress CyRamVectors[CYINT_IRQ_BASE + CY_NUM_INTERRUPTS]; + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: PWM1_ISR_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_ISR_Start(void) +{ + /* For all we know the interrupt is active. */ + PWM1_ISR_Disable(); + + /* Set the ISR to point to the PWM1_ISR Interrupt. */ + PWM1_ISR_SetVector(&PWM1_ISR_Interrupt); + + /* Set the priority. */ + PWM1_ISR_SetPriority((uint8)PWM1_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + PWM1_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_ISR_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + PWM1_ISR_Disable(); + + /* Set the ISR to point to the PWM1_ISR Interrupt. */ + PWM1_ISR_SetVector(address); + + /* Set the priority. */ + PWM1_ISR_SetPriority((uint8)PWM1_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + PWM1_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_ISR_Stop(void) +{ + /* Disable this interrupt. */ + PWM1_ISR_Disable(); + + /* Set the ISR to point to the passive one. */ + PWM1_ISR_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for PWM1_ISR. +* +* Add custom code between the START and END comments to keep the next version +* of this file from over-writing your code. +* +* Note You may use either the default ISR by using this API, or you may define +* your own separate ISR through ISR_StartEx(). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(PWM1_ISR_Interrupt) +{ + #ifdef PWM1_ISR_INTERRUPT_INTERRUPT_CALLBACK + PWM1_ISR_Interrupt_InterruptCallback(); + #endif /* PWM1_ISR_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START PWM1_ISR_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling PWM1_ISR_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use PWM1_ISR_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_ISR_SetVector(cyisraddress address) +{ + CyRamVectors[CYINT_IRQ_BASE + PWM1_ISR__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress PWM1_ISR_GetVector(void) +{ + return CyRamVectors[CYINT_IRQ_BASE + PWM1_ISR__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling PWM1_ISR_Start or PWM1_ISR_StartEx will +* override any effect this API would have had. This API should only be called +* after PWM1_ISR_Start or PWM1_ISR_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_ISR_SetPriority(uint8 priority) +{ + uint8 interruptState; + uint32 priorityOffset = ((PWM1_ISR__INTC_NUMBER % 4u) * 8u) + 6u; + + interruptState = CyEnterCriticalSection(); + *PWM1_ISR_INTC_PRIOR = (*PWM1_ISR_INTC_PRIOR & (uint32)(~PWM1_ISR__INTC_PRIOR_MASK)) | + ((uint32)priority << priorityOffset); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 PWM1_ISR_GetPriority(void) +{ + uint32 priority; + uint32 priorityOffset = ((PWM1_ISR__INTC_NUMBER % 4u) * 8u) + 6u; + + priority = (*PWM1_ISR_INTC_PRIOR & PWM1_ISR__INTC_PRIOR_MASK) >> priorityOffset; + + return (uint8)priority; +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_ISR_Enable(void) +{ + /* Enable the general interrupt. */ + *PWM1_ISR_INTC_SET_EN = PWM1_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 PWM1_ISR_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*PWM1_ISR_INTC_SET_EN & (uint32)PWM1_ISR__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_ISR_Disable(void) +{ + /* Disable the general interrupt. */ + *PWM1_ISR_INTC_CLR_EN = PWM1_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void PWM1_ISR_SetPending(void) +{ + *PWM1_ISR_INTC_SET_PD = PWM1_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: PWM1_ISR_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_ISR_ClearPending(void) +{ + *PWM1_ISR_INTC_CLR_PD = PWM1_ISR__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/PWM1_ISR.h b/cores/asr650x/cores/PWM1_ISR.h new file mode 100644 index 00000000..092e2103 --- /dev/null +++ b/cores/asr650x/cores/PWM1_ISR.h @@ -0,0 +1,82 @@ +/******************************************************************************* +* File Name: PWM1_ISR.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_PWM1_ISR_H) +#define CY_ISR_PWM1_ISR_H + + + +#include +#include + +#define PWM1_ISR__INTC_CLR_EN_REG CYREG_CM0P_ICER +#define PWM1_ISR__INTC_CLR_PD_REG CYREG_CM0P_ICPR +#define PWM1_ISR__INTC_MASK 0x400000u +#define PWM1_ISR__INTC_NUMBER 22u +#define PWM1_ISR__INTC_PRIOR_MASK 0xC00000u +#define PWM1_ISR__INTC_PRIOR_NUM 3u +#define PWM1_ISR__INTC_PRIOR_REG CYREG_CM0P_IPR5 +#define PWM1_ISR__INTC_SET_EN_REG CYREG_CM0P_ISER +#define PWM1_ISR__INTC_SET_PD_REG CYREG_CM0P_ISPR + +/* Interrupt Controller API. */ +void PWM1_ISR_Start(void); +void PWM1_ISR_StartEx(cyisraddress address); +void PWM1_ISR_Stop(void); + +CY_ISR_PROTO(PWM1_ISR_Interrupt); + +void PWM1_ISR_SetVector(cyisraddress address); +cyisraddress PWM1_ISR_GetVector(void); + +void PWM1_ISR_SetPriority(uint8 priority); +uint8 PWM1_ISR_GetPriority(void); + +void PWM1_ISR_Enable(void); +uint8 PWM1_ISR_GetState(void); +void PWM1_ISR_Disable(void); + +void PWM1_ISR_SetPending(void); +void PWM1_ISR_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the PWM1_ISR ISR. */ +#define PWM1_ISR_INTC_VECTOR ((reg32 *) PWM1_ISR__INTC_VECT) + +/* Address of the PWM1_ISR ISR priority. */ +#define PWM1_ISR_INTC_PRIOR ((reg32 *) PWM1_ISR__INTC_PRIOR_REG) + +/* Priority of the PWM1_ISR interrupt. */ +#define PWM1_ISR_INTC_PRIOR_NUMBER PWM1_ISR__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable PWM1_ISR interrupt. */ +#define PWM1_ISR_INTC_SET_EN ((reg32 *) PWM1_ISR__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the PWM1_ISR interrupt. */ +#define PWM1_ISR_INTC_CLR_EN ((reg32 *) PWM1_ISR__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the PWM1_ISR interrupt state to pending. */ +#define PWM1_ISR_INTC_SET_PD ((reg32 *) PWM1_ISR__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the PWM1_ISR interrupt. */ +#define PWM1_ISR_INTC_CLR_PD ((reg32 *) PWM1_ISR__INTC_CLR_PD_REG) + + + +#endif /* CY_ISR_PWM1_ISR_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/PWM1_PM.c b/cores/asr650x/cores/PWM1_PM.c new file mode 100644 index 00000000..dd57b449 --- /dev/null +++ b/cores/asr650x/cores/PWM1_PM.c @@ -0,0 +1,119 @@ +/******************************************************************************* +* File Name: PWM1_PM.c +* Version 2.10 +* +* Description: +* This file contains the setup, control, and status commands to support +* the component operations in the low power mode. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2013-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "PWM1.h" + +static PWM1_BACKUP_STRUCT PWM1_backup; + + +/******************************************************************************* +* Function Name: PWM1_SaveConfig +******************************************************************************** +* +* Summary: +* All configuration registers are retention. Nothing to save here. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_SaveConfig(void) +{ + +} + + +/******************************************************************************* +* Function Name: PWM1_Sleep +******************************************************************************** +* +* Summary: +* Stops the component operation and saves the user configuration. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_Sleep(void) +{ + if(0u != (PWM1_BLOCK_CONTROL_REG & PWM1_MASK)) + { + PWM1_backup.enableState = 1u; + } + else + { + PWM1_backup.enableState = 0u; + } + + PWM1_Stop(); + PWM1_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: PWM1_RestoreConfig +******************************************************************************** +* +* Summary: +* All configuration registers are retention. Nothing to restore here. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_RestoreConfig(void) +{ + +} + + +/******************************************************************************* +* Function Name: PWM1_Wakeup +******************************************************************************** +* +* Summary: +* Restores the user configuration and restores the enable state. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM1_Wakeup(void) +{ + PWM1_RestoreConfig(); + + if(0u != PWM1_backup.enableState) + { + PWM1_Enable(); + } +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/PWM2.c b/cores/asr650x/cores/PWM2.c new file mode 100644 index 00000000..fb25e956 --- /dev/null +++ b/cores/asr650x/cores/PWM2.c @@ -0,0 +1,1420 @@ +/******************************************************************************* +* File Name: PWM2.c +* Version 2.10 +* +* Description: +* This file provides the source code to the API for the PWM2 +* component +* +* Note: +* None +* +******************************************************************************** +* Copyright 2013-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "PWM2.h" +#include "ASR_Arduino.h" +uint8 PWM2_initVar = 0u; + + +/******************************************************************************* +* Function Name: PWM2_Init +******************************************************************************** +* +* Summary: +* Initialize/Restore default PWM2 configuration. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_Init(void) +{ + + /* Set values from customizer to CTRL */ + #if (PWM2__QUAD == PWM2_CONFIG) + PWM2_CONTROL_REG = PWM2_CTRL_QUAD_BASE_CONFIG; + + /* Set values from customizer to CTRL1 */ + PWM2_TRIG_CONTROL1_REG = PWM2_QUAD_SIGNALS_MODES; + + /* Set values from customizer to INTR */ + PWM2_SetInterruptMode(PWM2_QUAD_INTERRUPT_MASK); + + /* Set other values */ + PWM2_SetCounterMode(PWM2_COUNT_DOWN); + PWM2_WritePeriod(PWM2_QUAD_PERIOD_INIT_VALUE); + PWM2_WriteCounter(PWM2_QUAD_PERIOD_INIT_VALUE); + #endif /* (PWM2__QUAD == PWM2_CONFIG) */ + + #if (PWM2__TIMER == PWM2_CONFIG) + PWM2_CONTROL_REG = PWM2_CTRL_TIMER_BASE_CONFIG; + + /* Set values from customizer to CTRL1 */ + PWM2_TRIG_CONTROL1_REG = PWM2_TIMER_SIGNALS_MODES; + + /* Set values from customizer to INTR */ + PWM2_SetInterruptMode(PWM2_TC_INTERRUPT_MASK); + + /* Set other values from customizer */ + PWM2_WritePeriod(PWM2_TC_PERIOD_VALUE ); + + #if (PWM2__COMPARE == PWM2_TC_COMP_CAP_MODE) + PWM2_WriteCompare(PWM2_TC_COMPARE_VALUE); + + #if (1u == PWM2_TC_COMPARE_SWAP) + PWM2_SetCompareSwap(1u); + PWM2_WriteCompareBuf(PWM2_TC_COMPARE_BUF_VALUE); + #endif /* (1u == PWM2_TC_COMPARE_SWAP) */ + #endif /* (PWM2__COMPARE == PWM2_TC_COMP_CAP_MODE) */ + + /* Initialize counter value */ + #if (PWM2_CY_TCPWM_V2 && PWM2_TIMER_UPDOWN_CNT_USED && !PWM2_CY_TCPWM_4000) + PWM2_WriteCounter(1u); + #elif(PWM2__COUNT_DOWN == PWM2_TC_COUNTER_MODE) + PWM2_WriteCounter(PWM2_TC_PERIOD_VALUE); + #else + PWM2_WriteCounter(0u); + #endif /* (PWM2_CY_TCPWM_V2 && PWM2_TIMER_UPDOWN_CNT_USED && !PWM2_CY_TCPWM_4000) */ + #endif /* (PWM2__TIMER == PWM2_CONFIG) */ + + #if (PWM2__PWM_SEL == PWM2_CONFIG) + PWM2_CONTROL_REG = PWM2_CTRL_PWM_BASE_CONFIG; + + #if (PWM2__PWM_PR == PWM2_PWM_MODE) + PWM2_CONTROL_REG |= PWM2_CTRL_PWM_RUN_MODE; + PWM2_WriteCounter(PWM2_PWM_PR_INIT_VALUE); + #else + PWM2_CONTROL_REG |= PWM2_CTRL_PWM_ALIGN | PWM2_CTRL_PWM_KILL_EVENT; + + /* Initialize counter value */ + #if (PWM2_CY_TCPWM_V2 && PWM2_PWM_UPDOWN_CNT_USED && !PWM2_CY_TCPWM_4000) + PWM2_WriteCounter(1u); + #elif (PWM2__RIGHT == PWM2_PWM_ALIGN) + PWM2_WriteCounter(PWM2_PWM_PERIOD_VALUE); + #else + PWM2_WriteCounter(0u); + #endif /* (PWM2_CY_TCPWM_V2 && PWM2_PWM_UPDOWN_CNT_USED && !PWM2_CY_TCPWM_4000) */ + #endif /* (PWM2__PWM_PR == PWM2_PWM_MODE) */ + + #if (PWM2__PWM_DT == PWM2_PWM_MODE) + PWM2_CONTROL_REG |= PWM2_CTRL_PWM_DEAD_TIME_CYCLE; + #endif /* (PWM2__PWM_DT == PWM2_PWM_MODE) */ + + #if (PWM2__PWM == PWM2_PWM_MODE) + PWM2_CONTROL_REG |= PWM2_CTRL_PWM_PRESCALER; + #endif /* (PWM2__PWM == PWM2_PWM_MODE) */ + + /* Set values from customizer to CTRL1 */ + PWM2_TRIG_CONTROL1_REG = PWM2_PWM_SIGNALS_MODES; + + /* Set values from customizer to INTR */ + PWM2_SetInterruptMode(PWM2_PWM_INTERRUPT_MASK); + + /* Set values from customizer to CTRL2 */ + #if (PWM2__PWM_PR == PWM2_PWM_MODE) + PWM2_TRIG_CONTROL2_REG = + (PWM2_CC_MATCH_NO_CHANGE | + PWM2_OVERLOW_NO_CHANGE | + PWM2_UNDERFLOW_NO_CHANGE); + #else + #if (PWM2__LEFT == PWM2_PWM_ALIGN) + PWM2_TRIG_CONTROL2_REG = PWM2_PWM_MODE_LEFT; + #endif /* ( PWM2_PWM_LEFT == PWM2_PWM_ALIGN) */ + + #if (PWM2__RIGHT == PWM2_PWM_ALIGN) + PWM2_TRIG_CONTROL2_REG = PWM2_PWM_MODE_RIGHT; + #endif /* ( PWM2_PWM_RIGHT == PWM2_PWM_ALIGN) */ + + #if (PWM2__CENTER == PWM2_PWM_ALIGN) + PWM2_TRIG_CONTROL2_REG = PWM2_PWM_MODE_CENTER; + #endif /* ( PWM2_PWM_CENTER == PWM2_PWM_ALIGN) */ + + #if (PWM2__ASYMMETRIC == PWM2_PWM_ALIGN) + PWM2_TRIG_CONTROL2_REG = PWM2_PWM_MODE_ASYM; + #endif /* (PWM2__ASYMMETRIC == PWM2_PWM_ALIGN) */ + #endif /* (PWM2__PWM_PR == PWM2_PWM_MODE) */ + + /* Set other values from customizer */ + PWM2_WritePeriod(PWM2_PWM_PERIOD_VALUE ); + PWM2_WriteCompare(PWM2_PWM_COMPARE_VALUE); + + #if (1u == PWM2_PWM_COMPARE_SWAP) + PWM2_SetCompareSwap(1u); + PWM2_WriteCompareBuf(PWM2_PWM_COMPARE_BUF_VALUE); + #endif /* (1u == PWM2_PWM_COMPARE_SWAP) */ + + #if (1u == PWM2_PWM_PERIOD_SWAP) + PWM2_SetPeriodSwap(1u); + PWM2_WritePeriodBuf(PWM2_PWM_PERIOD_BUF_VALUE); + #endif /* (1u == PWM2_PWM_PERIOD_SWAP) */ + #endif /* (PWM2__PWM_SEL == PWM2_CONFIG) */ + +} + + +/******************************************************************************* +* Function Name: PWM2_Enable +******************************************************************************** +* +* Summary: +* Enables the PWM2. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_Enable(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + PWM2_BLOCK_CONTROL_REG |= PWM2_MASK; + CyExitCriticalSection(enableInterrupts); + + /* Start Timer or PWM if start input is absent */ + #if (PWM2__PWM_SEL == PWM2_CONFIG) + #if (0u == PWM2_PWM_START_SIGNAL_PRESENT) + PWM2_TriggerCommand(PWM2_MASK, PWM2_CMD_START); + #endif /* (0u == PWM2_PWM_START_SIGNAL_PRESENT) */ + #endif /* (PWM2__PWM_SEL == PWM2_CONFIG) */ + + #if (PWM2__TIMER == PWM2_CONFIG) + #if (0u == PWM2_TC_START_SIGNAL_PRESENT) + PWM2_TriggerCommand(PWM2_MASK, PWM2_CMD_START); + #endif /* (0u == PWM2_TC_START_SIGNAL_PRESENT) */ + #endif /* (PWM2__TIMER == PWM2_CONFIG) */ + + #if (PWM2__QUAD == PWM2_CONFIG) + #if (0u != PWM2_QUAD_AUTO_START) + PWM2_TriggerCommand(PWM2_MASK, PWM2_CMD_RELOAD); + #endif /* (0u != PWM2_QUAD_AUTO_START) */ + #endif /* (PWM2__QUAD == PWM2_CONFIG) */ +} + + +/******************************************************************************* +* Function Name: PWM2_Start +******************************************************************************** +* +* Summary: +* Initializes the PWM2 with default customizer +* values when called the first time and enables the PWM2. +* For subsequent calls the configuration is left unchanged and the component is +* just enabled. +* +* Parameters: +* None +* +* Return: +* None +* +* Global variables: +* PWM2_initVar: global variable is used to indicate initial +* configuration of this component. The variable is initialized to zero and set +* to 1 the first time PWM2_Start() is called. This allows +* enabling/disabling a component without re-initialization in all subsequent +* calls to the PWM2_Start() routine. +* +*******************************************************************************/ +void PWM2_Start(void) +{ + (* (reg32 *) CYREG_HSIOM_PORT_SEL6)=((* (reg32 *) CYREG_HSIOM_PORT_SEL6)&(~0x00080000u))|0x00080000u; + if (0u == PWM2_initVar) + { + PWM2_Init(); + PWM2_initVar = 1u; + } + + PWM2_Enable(); +} + + +/******************************************************************************* +* Function Name: PWM2_Stop +******************************************************************************** +* +* Summary: +* Disables the PWM2. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_Stop(void) +{ + pinMode(P6_4,ANALOG); + (* (reg32 *) CYREG_HSIOM_PORT_SEL6)=((* (reg32 *) CYREG_HSIOM_PORT_SEL6)&(~0x00080000u)); + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_BLOCK_CONTROL_REG &= (uint32)~PWM2_MASK; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetMode +******************************************************************************** +* +* Summary: +* Sets the operation mode of the PWM2. This function is used when +* configured as a generic PWM2 and the actual mode of operation is +* set at runtime. The mode must be set while the component is disabled. +* +* Parameters: +* mode: Mode for the PWM2 to operate in +* Values: +* - PWM2_MODE_TIMER_COMPARE - Timer / Counter with +* compare capability +* - PWM2_MODE_TIMER_CAPTURE - Timer / Counter with +* capture capability +* - PWM2_MODE_QUAD - Quadrature decoder +* - PWM2_MODE_PWM - PWM +* - PWM2_MODE_PWM_DT - PWM with dead time +* - PWM2_MODE_PWM_PR - PWM with pseudo random capability +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetMode(uint32 mode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_CONTROL_REG &= (uint32)~PWM2_MODE_MASK; + PWM2_CONTROL_REG |= mode; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetQDMode +******************************************************************************** +* +* Summary: +* Sets the the Quadrature Decoder to one of the 3 supported modes. +* Its functionality is only applicable to Quadrature Decoder operation. +* +* Parameters: +* qdMode: Quadrature Decoder mode +* Values: +* - PWM2_MODE_X1 - Counts on phi 1 rising +* - PWM2_MODE_X2 - Counts on both edges of phi1 (2x faster) +* - PWM2_MODE_X4 - Counts on both edges of phi1 and phi2 +* (4x faster) +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetQDMode(uint32 qdMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_CONTROL_REG &= (uint32)~PWM2_QUAD_MODE_MASK; + PWM2_CONTROL_REG |= qdMode; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetPrescaler +******************************************************************************** +* +* Summary: +* Sets the prescaler value that is applied to the clock input. Not applicable +* to a PWM with the dead time mode or Quadrature Decoder mode. +* +* Parameters: +* prescaler: Prescaler divider value +* Values: +* - PWM2_PRESCALE_DIVBY1 - Divide by 1 (no prescaling) +* - PWM2_PRESCALE_DIVBY2 - Divide by 2 +* - PWM2_PRESCALE_DIVBY4 - Divide by 4 +* - PWM2_PRESCALE_DIVBY8 - Divide by 8 +* - PWM2_PRESCALE_DIVBY16 - Divide by 16 +* - PWM2_PRESCALE_DIVBY32 - Divide by 32 +* - PWM2_PRESCALE_DIVBY64 - Divide by 64 +* - PWM2_PRESCALE_DIVBY128 - Divide by 128 +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetPrescaler(uint32 prescaler) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_CONTROL_REG &= (uint32)~PWM2_PRESCALER_MASK; + PWM2_CONTROL_REG |= prescaler; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetOneShot +******************************************************************************** +* +* Summary: +* Writes the register that controls whether the PWM2 runs +* continuously or stops when terminal count is reached. By default the +* PWM2 operates in the continuous mode. +* +* Parameters: +* oneShotEnable +* Values: +* - 0 - Continuous +* - 1 - Enable One Shot +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetOneShot(uint32 oneShotEnable) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_CONTROL_REG &= (uint32)~PWM2_ONESHOT_MASK; + PWM2_CONTROL_REG |= ((uint32)((oneShotEnable & PWM2_1BIT_MASK) << + PWM2_ONESHOT_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetPWMMode +******************************************************************************** +* +* Summary: +* Writes the control register that determines what mode of operation the PWM +* output lines are driven in. There is a setting for what to do on a +* comparison match (CC_MATCH), on an overflow (OVERFLOW) and on an underflow +* (UNDERFLOW). The value for each of the three must be ORed together to form +* the mode. +* +* Parameters: +* modeMask: A combination of three mode settings. Mask must include a value +* for each of the three or use one of the preconfigured PWM settings. +* Values: +* - CC_MATCH_SET - Set on comparison match +* - CC_MATCH_CLEAR - Clear on comparison match +* - CC_MATCH_INVERT - Invert on comparison match +* - CC_MATCH_NO_CHANGE - No change on comparison match +* - OVERLOW_SET - Set on overflow +* - OVERLOW_CLEAR - Clear on overflow +* - OVERLOW_INVERT - Invert on overflow +* - OVERLOW_NO_CHANGE - No change on overflow +* - UNDERFLOW_SET - Set on underflow +* - UNDERFLOW_CLEAR - Clear on underflow +* - UNDERFLOW_INVERT - Invert on underflow +* - UNDERFLOW_NO_CHANGE - No change on underflow +* - PWM_MODE_LEFT - Setting for left aligned PWM. Should be combined +* with up counting mode +* - PWM_MODE_RIGHT - Setting for right aligned PWM. Should be combined +* with down counting mode +* - PWM_MODE_CENTER - Setting for center aligned PWM. Should be +* combined with up/down 0 mode +* - PWM_MODE_ASYM - Setting for asymmetric PWM. Should be combined +* with up/down 1 mode +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetPWMMode(uint32 modeMask) +{ + PWM2_TRIG_CONTROL2_REG = (modeMask & PWM2_6BIT_MASK); +} + + + +/******************************************************************************* +* Function Name: PWM2_SetPWMSyncKill +******************************************************************************** +* +* Summary: +* Writes the register that controls whether the PWM kill signal (stop input) +* causes asynchronous or synchronous kill operation. By default the kill +* operation is asynchronous. This functionality is only applicable to the PWM +* and PWM with dead time modes. +* +* For Synchronous mode the kill signal disables both the line and line_n +* signals until the next terminal count. +* +* For Asynchronous mode the kill signal disables both the line and line_n +* signals when the kill signal is present. This mode should only be used +* when the kill signal (stop input) is configured in the pass through mode +* (Level sensitive signal). + +* +* Parameters: +* syncKillEnable +* Values: +* - 0 - Asynchronous +* - 1 - Synchronous +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetPWMSyncKill(uint32 syncKillEnable) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_CONTROL_REG &= (uint32)~PWM2_PWM_SYNC_KILL_MASK; + PWM2_CONTROL_REG |= ((uint32)((syncKillEnable & PWM2_1BIT_MASK) << + PWM2_PWM_SYNC_KILL_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetPWMStopOnKill +******************************************************************************** +* +* Summary: +* Writes the register that controls whether the PWM kill signal (stop input) +* causes the PWM counter to stop. By default the kill operation does not stop +* the counter. This functionality is only applicable to the three PWM modes. +* +* +* Parameters: +* stopOnKillEnable +* Values: +* - 0 - Don't stop +* - 1 - Stop +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetPWMStopOnKill(uint32 stopOnKillEnable) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_CONTROL_REG &= (uint32)~PWM2_PWM_STOP_KILL_MASK; + PWM2_CONTROL_REG |= ((uint32)((stopOnKillEnable & PWM2_1BIT_MASK) << + PWM2_PWM_STOP_KILL_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetPWMDeadTime +******************************************************************************** +* +* Summary: +* Writes the dead time control value. This value delays the rising edge of +* both the line and line_n signals the designated number of cycles resulting +* in both signals being inactive for that many cycles. This functionality is +* only applicable to the PWM in the dead time mode. + +* +* Parameters: +* Dead time to insert +* Values: 0 to 255 +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetPWMDeadTime(uint32 deadTime) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_CONTROL_REG &= (uint32)~PWM2_PRESCALER_MASK; + PWM2_CONTROL_REG |= ((uint32)((deadTime & PWM2_8BIT_MASK) << + PWM2_PRESCALER_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetPWMInvert +******************************************************************************** +* +* Summary: +* Writes the bits that control whether the line and line_n outputs are +* inverted from their normal output values. This functionality is only +* applicable to the three PWM modes. +* +* Parameters: +* mask: Mask of outputs to invert. +* Values: +* - PWM2_INVERT_LINE - Inverts the line output +* - PWM2_INVERT_LINE_N - Inverts the line_n output +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetPWMInvert(uint32 mask) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_CONTROL_REG &= (uint32)~PWM2_INV_OUT_MASK; + PWM2_CONTROL_REG |= mask; + + CyExitCriticalSection(enableInterrupts); +} + + + +/******************************************************************************* +* Function Name: PWM2_WriteCounter +******************************************************************************** +* +* Summary: +* Writes a new 16bit counter value directly into the counter register, thus +* setting the counter (not the period) to the value written. It is not +* advised to write to this field when the counter is running. +* +* Parameters: +* count: value to write +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_WriteCounter(uint32 count) +{ + PWM2_COUNTER_REG = (count & PWM2_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM2_ReadCounter +******************************************************************************** +* +* Summary: +* Reads the current counter value. +* +* Parameters: +* None +* +* Return: +* Current counter value +* +*******************************************************************************/ +uint32 PWM2_ReadCounter(void) +{ + return (PWM2_COUNTER_REG & PWM2_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM2_SetCounterMode +******************************************************************************** +* +* Summary: +* Sets the counter mode. Applicable to all modes except Quadrature Decoder +* and the PWM with a pseudo random output. +* +* Parameters: +* counterMode: Enumerated counter type values +* Values: +* - PWM2_COUNT_UP - Counts up +* - PWM2_COUNT_DOWN - Counts down +* - PWM2_COUNT_UPDOWN0 - Counts up and down. Terminal count +* generated when counter reaches 0 +* - PWM2_COUNT_UPDOWN1 - Counts up and down. Terminal count +* generated both when counter reaches 0 +* and period +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetCounterMode(uint32 counterMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_CONTROL_REG &= (uint32)~PWM2_UPDOWN_MASK; + PWM2_CONTROL_REG |= counterMode; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_WritePeriod +******************************************************************************** +* +* Summary: +* Writes the 16 bit period register with the new period value. +* To cause the counter to count for N cycles this register should be written +* with N-1 (counts from 0 to period inclusive). +* +* Parameters: +* period: Period value +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_WritePeriod(uint32 period) +{ + PWM2_PERIOD_REG = (period & PWM2_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM2_ReadPeriod +******************************************************************************** +* +* Summary: +* Reads the 16 bit period register. +* +* Parameters: +* None +* +* Return: +* Period value +* +*******************************************************************************/ +uint32 PWM2_ReadPeriod(void) +{ + return (PWM2_PERIOD_REG & PWM2_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM2_SetCompareSwap +******************************************************************************** +* +* Summary: +* Writes the register that controls whether the compare registers are +* swapped. When enabled in the Timer/Counter mode(without capture) the swap +* occurs at a TC event. In the PWM mode the swap occurs at the next TC event +* following a hardware switch event. +* +* Parameters: +* swapEnable +* Values: +* - 0 - Disable swap +* - 1 - Enable swap +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetCompareSwap(uint32 swapEnable) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_CONTROL_REG &= (uint32)~PWM2_RELOAD_CC_MASK; + PWM2_CONTROL_REG |= (swapEnable & PWM2_1BIT_MASK); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_WritePeriodBuf +******************************************************************************** +* +* Summary: +* Writes the 16 bit period buf register with the new period value. +* +* Parameters: +* periodBuf: Period value +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_WritePeriodBuf(uint32 periodBuf) +{ + PWM2_PERIOD_BUF_REG = (periodBuf & PWM2_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM2_ReadPeriodBuf +******************************************************************************** +* +* Summary: +* Reads the 16 bit period buf register. +* +* Parameters: +* None +* +* Return: +* Period value +* +*******************************************************************************/ +uint32 PWM2_ReadPeriodBuf(void) +{ + return (PWM2_PERIOD_BUF_REG & PWM2_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM2_SetPeriodSwap +******************************************************************************** +* +* Summary: +* Writes the register that controls whether the period registers are +* swapped. When enabled in Timer/Counter mode the swap occurs at a TC event. +* In the PWM mode the swap occurs at the next TC event following a hardware +* switch event. +* +* Parameters: +* swapEnable +* Values: +* - 0 - Disable swap +* - 1 - Enable swap +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetPeriodSwap(uint32 swapEnable) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_CONTROL_REG &= (uint32)~PWM2_RELOAD_PERIOD_MASK; + PWM2_CONTROL_REG |= ((uint32)((swapEnable & PWM2_1BIT_MASK) << + PWM2_RELOAD_PERIOD_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_WriteCompare +******************************************************************************** +* +* Summary: +* Writes the 16 bit compare register with the new compare value. Not +* applicable for Timer/Counter with Capture or in Quadrature Decoder modes. +* +* Parameters: +* compare: Compare value +* +* Return: +* None +* +* Note: +* It is not recommended to use the value equal to "0" or equal to +* "period value" in Center or Asymmetric align PWM modes on the +* PSoC 4100/PSoC 4200 devices. +* PSoC 4000 devices write the 16 bit compare register with the decremented +* compare value in the Up counting mode (except 0x0u), and the incremented +* compare value in the Down counting mode (except 0xFFFFu). +* +*******************************************************************************/ +void PWM2_WriteCompare(uint32 compare) +{ + #if (PWM2_CY_TCPWM_4000) + uint32 currentMode; + #endif /* (PWM2_CY_TCPWM_4000) */ + + #if (PWM2_CY_TCPWM_4000) + currentMode = ((PWM2_CONTROL_REG & PWM2_UPDOWN_MASK) >> PWM2_UPDOWN_SHIFT); + + if (((uint32)PWM2__COUNT_DOWN == currentMode) && (0xFFFFu != compare)) + { + compare++; + } + else if (((uint32)PWM2__COUNT_UP == currentMode) && (0u != compare)) + { + compare--; + } + else + { + } + + + #endif /* (PWM2_CY_TCPWM_4000) */ + + PWM2_COMP_CAP_REG = (compare & PWM2_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM2_ReadCompare +******************************************************************************** +* +* Summary: +* Reads the compare register. Not applicable for Timer/Counter with Capture +* or in Quadrature Decoder modes. +* PSoC 4000 devices read the incremented compare register value in the +* Up counting mode (except 0xFFFFu), and the decremented value in the +* Down counting mode (except 0x0u). +* +* Parameters: +* None +* +* Return: +* Compare value +* +* Note: +* PSoC 4000 devices read the incremented compare register value in the +* Up counting mode (except 0xFFFFu), and the decremented value in the +* Down counting mode (except 0x0u). +* +*******************************************************************************/ +uint32 PWM2_ReadCompare(void) +{ + #if (PWM2_CY_TCPWM_4000) + uint32 currentMode; + uint32 regVal; + #endif /* (PWM2_CY_TCPWM_4000) */ + + #if (PWM2_CY_TCPWM_4000) + currentMode = ((PWM2_CONTROL_REG & PWM2_UPDOWN_MASK) >> PWM2_UPDOWN_SHIFT); + + regVal = PWM2_COMP_CAP_REG; + + if (((uint32)PWM2__COUNT_DOWN == currentMode) && (0u != regVal)) + { + regVal--; + } + else if (((uint32)PWM2__COUNT_UP == currentMode) && (0xFFFFu != regVal)) + { + regVal++; + } + else + { + } + + return (regVal & PWM2_16BIT_MASK); + #else + return (PWM2_COMP_CAP_REG & PWM2_16BIT_MASK); + #endif /* (PWM2_CY_TCPWM_4000) */ +} + + +/******************************************************************************* +* Function Name: PWM2_WriteCompareBuf +******************************************************************************** +* +* Summary: +* Writes the 16 bit compare buffer register with the new compare value. Not +* applicable for Timer/Counter with Capture or in Quadrature Decoder modes. +* +* Parameters: +* compareBuf: Compare value +* +* Return: +* None +* +* Note: +* It is not recommended to use the value equal to "0" or equal to +* "period value" in Center or Asymmetric align PWM modes on the +* PSoC 4100/PSoC 4200 devices. +* PSoC 4000 devices write the 16 bit compare register with the decremented +* compare value in the Up counting mode (except 0x0u), and the incremented +* compare value in the Down counting mode (except 0xFFFFu). +* +*******************************************************************************/ +void PWM2_WriteCompareBuf(uint32 compareBuf) +{ + #if (PWM2_CY_TCPWM_4000) + uint32 currentMode; + #endif /* (PWM2_CY_TCPWM_4000) */ + + #if (PWM2_CY_TCPWM_4000) + currentMode = ((PWM2_CONTROL_REG & PWM2_UPDOWN_MASK) >> PWM2_UPDOWN_SHIFT); + + if (((uint32)PWM2__COUNT_DOWN == currentMode) && (0xFFFFu != compareBuf)) + { + compareBuf++; + } + else if (((uint32)PWM2__COUNT_UP == currentMode) && (0u != compareBuf)) + { + compareBuf --; + } + else + { + } + #endif /* (PWM2_CY_TCPWM_4000) */ + + PWM2_COMP_CAP_BUF_REG = (compareBuf & PWM2_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM2_ReadCompareBuf +******************************************************************************** +* +* Summary: +* Reads the compare buffer register. Not applicable for Timer/Counter with +* Capture or in Quadrature Decoder modes. +* +* Parameters: +* None +* +* Return: +* Compare buffer value +* +* Note: +* PSoC 4000 devices read the incremented compare register value in the +* Up counting mode (except 0xFFFFu), and the decremented value in the +* Down counting mode (except 0x0u). +* +*******************************************************************************/ +uint32 PWM2_ReadCompareBuf(void) +{ + #if (PWM2_CY_TCPWM_4000) + uint32 currentMode; + uint32 regVal; + #endif /* (PWM2_CY_TCPWM_4000) */ + + #if (PWM2_CY_TCPWM_4000) + currentMode = ((PWM2_CONTROL_REG & PWM2_UPDOWN_MASK) >> PWM2_UPDOWN_SHIFT); + + regVal = PWM2_COMP_CAP_BUF_REG; + + if (((uint32)PWM2__COUNT_DOWN == currentMode) && (0u != regVal)) + { + regVal--; + } + else if (((uint32)PWM2__COUNT_UP == currentMode) && (0xFFFFu != regVal)) + { + regVal++; + } + else + { + } + + return (regVal & PWM2_16BIT_MASK); + #else + return (PWM2_COMP_CAP_BUF_REG & PWM2_16BIT_MASK); + #endif /* (PWM2_CY_TCPWM_4000) */ +} + + +/******************************************************************************* +* Function Name: PWM2_ReadCapture +******************************************************************************** +* +* Summary: +* Reads the captured counter value. This API is applicable only for +* Timer/Counter with the capture mode and Quadrature Decoder modes. +* +* Parameters: +* None +* +* Return: +* Capture value +* +*******************************************************************************/ +uint32 PWM2_ReadCapture(void) +{ + return (PWM2_COMP_CAP_REG & PWM2_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM2_ReadCaptureBuf +******************************************************************************** +* +* Summary: +* Reads the capture buffer register. This API is applicable only for +* Timer/Counter with the capture mode and Quadrature Decoder modes. +* +* Parameters: +* None +* +* Return: +* Capture buffer value +* +*******************************************************************************/ +uint32 PWM2_ReadCaptureBuf(void) +{ + return (PWM2_COMP_CAP_BUF_REG & PWM2_16BIT_MASK); +} + + +/******************************************************************************* +* Function Name: PWM2_SetCaptureMode +******************************************************************************** +* +* Summary: +* Sets the capture trigger mode. For PWM mode this is the switch input. +* This input is not applicable to the Timer/Counter without Capture and +* Quadrature Decoder modes. +* +* Parameters: +* triggerMode: Enumerated trigger mode value +* Values: +* - PWM2_TRIG_LEVEL - Level +* - PWM2_TRIG_RISING - Rising edge +* - PWM2_TRIG_FALLING - Falling edge +* - PWM2_TRIG_BOTH - Both rising and falling edge +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetCaptureMode(uint32 triggerMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_TRIG_CONTROL1_REG &= (uint32)~PWM2_CAPTURE_MASK; + PWM2_TRIG_CONTROL1_REG |= triggerMode; + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetReloadMode +******************************************************************************** +* +* Summary: +* Sets the reload trigger mode. For Quadrature Decoder mode this is the index +* input. +* +* Parameters: +* triggerMode: Enumerated trigger mode value +* Values: +* - PWM2_TRIG_LEVEL - Level +* - PWM2_TRIG_RISING - Rising edge +* - PWM2_TRIG_FALLING - Falling edge +* - PWM2_TRIG_BOTH - Both rising and falling edge +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetReloadMode(uint32 triggerMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_TRIG_CONTROL1_REG &= (uint32)~PWM2_RELOAD_MASK; + PWM2_TRIG_CONTROL1_REG |= ((uint32)(triggerMode << PWM2_RELOAD_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetStartMode +******************************************************************************** +* +* Summary: +* Sets the start trigger mode. For Quadrature Decoder mode this is the +* phiB input. +* +* Parameters: +* triggerMode: Enumerated trigger mode value +* Values: +* - PWM2_TRIG_LEVEL - Level +* - PWM2_TRIG_RISING - Rising edge +* - PWM2_TRIG_FALLING - Falling edge +* - PWM2_TRIG_BOTH - Both rising and falling edge +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetStartMode(uint32 triggerMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_TRIG_CONTROL1_REG &= (uint32)~PWM2_START_MASK; + PWM2_TRIG_CONTROL1_REG |= ((uint32)(triggerMode << PWM2_START_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetStopMode +******************************************************************************** +* +* Summary: +* Sets the stop trigger mode. For PWM mode this is the kill input. +* +* Parameters: +* triggerMode: Enumerated trigger mode value +* Values: +* - PWM2_TRIG_LEVEL - Level +* - PWM2_TRIG_RISING - Rising edge +* - PWM2_TRIG_FALLING - Falling edge +* - PWM2_TRIG_BOTH - Both rising and falling edge +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetStopMode(uint32 triggerMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_TRIG_CONTROL1_REG &= (uint32)~PWM2_STOP_MASK; + PWM2_TRIG_CONTROL1_REG |= ((uint32)(triggerMode << PWM2_STOP_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_SetCountMode +******************************************************************************** +* +* Summary: +* Sets the count trigger mode. For Quadrature Decoder mode this is the phiA +* input. +* +* Parameters: +* triggerMode: Enumerated trigger mode value +* Values: +* - PWM2_TRIG_LEVEL - Level +* - PWM2_TRIG_RISING - Rising edge +* - PWM2_TRIG_FALLING - Falling edge +* - PWM2_TRIG_BOTH - Both rising and falling edge +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetCountMode(uint32 triggerMode) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_TRIG_CONTROL1_REG &= (uint32)~PWM2_COUNT_MASK; + PWM2_TRIG_CONTROL1_REG |= ((uint32)(triggerMode << PWM2_COUNT_SHIFT)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_TriggerCommand +******************************************************************************** +* +* Summary: +* Triggers the designated command to occur on the designated TCPWM instances. +* The mask can be used to apply this command simultaneously to more than one +* instance. This allows multiple TCPWM instances to be synchronized. +* +* Parameters: +* mask: A combination of mask bits for each instance of the TCPWM that the +* command should apply to. This function from one instance can be used +* to apply the command to any of the instances in the design. +* The mask value for a specific instance is available with the MASK +* define. +* command: Enumerated command values. Capture command only applicable for +* Timer/Counter with Capture and PWM modes. +* Values: +* - PWM2_CMD_CAPTURE - Trigger Capture/Switch command +* - PWM2_CMD_RELOAD - Trigger Reload/Index command +* - PWM2_CMD_STOP - Trigger Stop/Kill command +* - PWM2_CMD_START - Trigger Start/phiB command +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_TriggerCommand(uint32 mask, uint32 command) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + PWM2_COMMAND_REG = ((uint32)(mask << command)); + + CyExitCriticalSection(enableInterrupts); +} + + +/******************************************************************************* +* Function Name: PWM2_ReadStatus +******************************************************************************** +* +* Summary: +* Reads the status of the PWM2. +* +* Parameters: +* None +* +* Return: +* Status +* Values: +* - PWM2_STATUS_DOWN - Set if counting down +* - PWM2_STATUS_RUNNING - Set if counter is running +* +*******************************************************************************/ +uint32 PWM2_ReadStatus(void) +{ + return ((PWM2_STATUS_REG >> PWM2_RUNNING_STATUS_SHIFT) | + (PWM2_STATUS_REG & PWM2_STATUS_DOWN)); +} + + +/******************************************************************************* +* Function Name: PWM2_SetInterruptMode +******************************************************************************** +* +* Summary: +* Sets the interrupt mask to control which interrupt +* requests generate the interrupt signal. +* +* Parameters: +* interruptMask: Mask of bits to be enabled +* Values: +* - PWM2_INTR_MASK_TC - Terminal count mask +* - PWM2_INTR_MASK_CC_MATCH - Compare count / capture mask +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetInterruptMode(uint32 interruptMask) +{ + PWM2_INTERRUPT_MASK_REG = interruptMask; +} + + +/******************************************************************************* +* Function Name: PWM2_GetInterruptSourceMasked +******************************************************************************** +* +* Summary: +* Gets the interrupt requests masked by the interrupt mask. +* +* Parameters: +* None +* +* Return: +* Masked interrupt source +* Values: +* - PWM2_INTR_MASK_TC - Terminal count mask +* - PWM2_INTR_MASK_CC_MATCH - Compare count / capture mask +* +*******************************************************************************/ +uint32 PWM2_GetInterruptSourceMasked(void) +{ + return (PWM2_INTERRUPT_MASKED_REG); +} + + +/******************************************************************************* +* Function Name: PWM2_GetInterruptSource +******************************************************************************** +* +* Summary: +* Gets the interrupt requests (without masking). +* +* Parameters: +* None +* +* Return: +* Interrupt request value +* Values: +* - PWM2_INTR_MASK_TC - Terminal count mask +* - PWM2_INTR_MASK_CC_MATCH - Compare count / capture mask +* +*******************************************************************************/ +uint32 PWM2_GetInterruptSource(void) +{ + return (PWM2_INTERRUPT_REQ_REG); +} + + +/******************************************************************************* +* Function Name: PWM2_ClearInterrupt +******************************************************************************** +* +* Summary: +* Clears the interrupt request. +* +* Parameters: +* interruptMask: Mask of interrupts to clear +* Values: +* - PWM2_INTR_MASK_TC - Terminal count mask +* - PWM2_INTR_MASK_CC_MATCH - Compare count / capture mask +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_ClearInterrupt(uint32 interruptMask) +{ + PWM2_INTERRUPT_REQ_REG = interruptMask; +} + + +/******************************************************************************* +* Function Name: PWM2_SetInterrupt +******************************************************************************** +* +* Summary: +* Sets a software interrupt request. +* +* Parameters: +* interruptMask: Mask of interrupts to set +* Values: +* - PWM2_INTR_MASK_TC - Terminal count mask +* - PWM2_INTR_MASK_CC_MATCH - Compare count / capture mask +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SetInterrupt(uint32 interruptMask) +{ + PWM2_INTERRUPT_SET_REG = interruptMask; +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/PWM2.h b/cores/asr650x/cores/PWM2.h new file mode 100644 index 00000000..8f82befc --- /dev/null +++ b/cores/asr650x/cores/PWM2.h @@ -0,0 +1,583 @@ +/******************************************************************************* +* File Name: PWM2.h +* Version 2.10 +* +* Description: +* This file provides constants and parameter values for the PWM2 +* component. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2013-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_TCPWM_PWM2_H) +#define CY_TCPWM_PWM2_H + + +#include "CyLib.h" +#include "cytypes.h" +#include "cyfitter.h" + + +/******************************************************************************* +* Internal Type defines +*******************************************************************************/ + +/* PWM2 */ +#define PWM2_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT6_CC +#define PWM2_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT6_CC_BUFF +#define PWM2_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT6_COUNTER +#define PWM2_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT6_CTRL +#define PWM2_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT6_INTR +#define PWM2_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT6_INTR_MASK +#define PWM2_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT6_INTR_MASKED +#define PWM2_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT6_INTR_SET +#define PWM2_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT6_PERIOD +#define PWM2_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT6_PERIOD_BUFF +#define PWM2_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT6_STATUS +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x40u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 6u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x4000u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 14u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x40000000u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 30u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x400000u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 22u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x40u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 6u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x40u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 6u +#define PWM2_cy_m0s8_tcpwm_1__TCPWM_NUMBER 6u +#define PWM2_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT6_TR_CTRL0 +#define PWM2_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT6_TR_CTRL1 +#define PWM2_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT6_TR_CTRL2 + +/* ClockPWM2 */ +#define ClockPWM2__CTRL_REGISTER CYREG_PERI_PCLK_CTL12 +#define ClockPWM2__DIV_ID 0x00000042u +#define ClockPWM2__DIV_REGISTER CYREG_PERI_DIV_16_CTL2 +#define ClockPWM2__PA_DIV_ID 0x000000FFu + + +/* Structure to save state before go to sleep */ +typedef struct +{ + uint8 enableState; +} PWM2_BACKUP_STRUCT; + + +/******************************************************************************* +* Variables +*******************************************************************************/ +extern uint8 PWM2_initVar; + + +/*************************************** +* Conditional Compilation Parameters +****************************************/ + +#define PWM2_CY_TCPWM_V2 (CYIPBLOCK_m0s8tcpwm_VERSION == 2u) +#define PWM2_CY_TCPWM_4000 (CY_PSOC4_4000) + +/* TCPWM Configuration */ +#define PWM2_CONFIG (7lu) + +/* Quad Mode */ +/* Parameters */ +#define PWM2_QUAD_ENCODING_MODES (0lu) +#define PWM2_QUAD_AUTO_START (0lu) + +/* Signal modes */ +#define PWM2_QUAD_INDEX_SIGNAL_MODE (0lu) +#define PWM2_QUAD_PHIA_SIGNAL_MODE (3lu) +#define PWM2_QUAD_PHIB_SIGNAL_MODE (3lu) +#define PWM2_QUAD_STOP_SIGNAL_MODE (0lu) + +/* Signal present */ +#define PWM2_QUAD_INDEX_SIGNAL_PRESENT (0lu) +#define PWM2_QUAD_STOP_SIGNAL_PRESENT (0lu) + +/* Interrupt Mask */ +#define PWM2_QUAD_INTERRUPT_MASK (1lu) + +/* Timer/Counter Mode */ +/* Parameters */ +#define PWM2_TC_RUN_MODE (0lu) +#define PWM2_TC_COUNTER_MODE (0lu) +#define PWM2_TC_COMP_CAP_MODE (2lu) +#define PWM2_TC_PRESCALER (0lu) + +/* Signal modes */ +#define PWM2_TC_RELOAD_SIGNAL_MODE (0lu) +#define PWM2_TC_COUNT_SIGNAL_MODE (3lu) +#define PWM2_TC_START_SIGNAL_MODE (0lu) +#define PWM2_TC_STOP_SIGNAL_MODE (0lu) +#define PWM2_TC_CAPTURE_SIGNAL_MODE (0lu) + +/* Signal present */ +#define PWM2_TC_RELOAD_SIGNAL_PRESENT (0lu) +#define PWM2_TC_COUNT_SIGNAL_PRESENT (0lu) +#define PWM2_TC_START_SIGNAL_PRESENT (0lu) +#define PWM2_TC_STOP_SIGNAL_PRESENT (0lu) +#define PWM2_TC_CAPTURE_SIGNAL_PRESENT (0lu) + +/* Interrupt Mask */ +#define PWM2_TC_INTERRUPT_MASK (1lu) + +/* PWM Mode */ +/* Parameters */ +#define PWM2_PWM_KILL_EVENT (0lu) +#define PWM2_PWM_STOP_EVENT (0lu) +#define PWM2_PWM_MODE (4lu) +#define PWM2_PWM_OUT_N_INVERT (0lu) +#define PWM2_PWM_OUT_INVERT (0lu) +#define PWM2_PWM_ALIGN (0lu) +#define PWM2_PWM_RUN_MODE (0lu) +#define PWM2_PWM_DEAD_TIME_CYCLE (0lu) +#define PWM2_PWM_PRESCALER (0lu) + +/* Signal modes */ +#define PWM2_PWM_RELOAD_SIGNAL_MODE (0lu) +#define PWM2_PWM_COUNT_SIGNAL_MODE (3lu) +#define PWM2_PWM_START_SIGNAL_MODE (0lu) +#define PWM2_PWM_STOP_SIGNAL_MODE (0lu) +#define PWM2_PWM_SWITCH_SIGNAL_MODE (0lu) + +/* Signal present */ +#define PWM2_PWM_RELOAD_SIGNAL_PRESENT (0lu) +#define PWM2_PWM_COUNT_SIGNAL_PRESENT (0lu) +#define PWM2_PWM_START_SIGNAL_PRESENT (0lu) +#define PWM2_PWM_STOP_SIGNAL_PRESENT (0lu) +#define PWM2_PWM_SWITCH_SIGNAL_PRESENT (0lu) + +/* Interrupt Mask */ +#define PWM2_PWM_INTERRUPT_MASK (1lu) + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +/* Timer/Counter Mode */ +#define PWM2_TC_PERIOD_VALUE (65535lu) +#define PWM2_TC_COMPARE_VALUE (65535lu) +#define PWM2_TC_COMPARE_BUF_VALUE (65535lu) +#define PWM2_TC_COMPARE_SWAP (0lu) + +/* PWM Mode */ +#define PWM2_PWM_PERIOD_VALUE (63000lu) +#define PWM2_PWM_PERIOD_BUF_VALUE (65535lu) +#define PWM2_PWM_PERIOD_SWAP (0lu) +#define PWM2_PWM_COMPARE_VALUE (0lu) +#define PWM2_PWM_COMPARE_BUF_VALUE (65535lu) +#define PWM2_PWM_COMPARE_SWAP (0lu) + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +#define PWM2__LEFT 0 +#define PWM2__RIGHT 1 +#define PWM2__CENTER 2 +#define PWM2__ASYMMETRIC 3 + +#define PWM2__X1 0 +#define PWM2__X2 1 +#define PWM2__X4 2 + +#define PWM2__PWM 4 +#define PWM2__PWM_DT 5 +#define PWM2__PWM_PR 6 + +#define PWM2__INVERSE 1 +#define PWM2__DIRECT 0 + +#define PWM2__CAPTURE 2 +#define PWM2__COMPARE 0 + +#define PWM2__TRIG_LEVEL 3 +#define PWM2__TRIG_RISING 0 +#define PWM2__TRIG_FALLING 1 +#define PWM2__TRIG_BOTH 2 + +#define PWM2__INTR_MASK_TC 1 +#define PWM2__INTR_MASK_CC_MATCH 2 +#define PWM2__INTR_MASK_NONE 0 +#define PWM2__INTR_MASK_TC_CC 3 + +#define PWM2__UNCONFIG 8 +#define PWM2__TIMER 1 +#define PWM2__QUAD 3 +#define PWM2__PWM_SEL 7 + +#define PWM2__COUNT_UP 0 +#define PWM2__COUNT_DOWN 1 +#define PWM2__COUNT_UPDOWN0 2 +#define PWM2__COUNT_UPDOWN1 3 + + +/* Prescaler */ +#define PWM2_PRESCALE_DIVBY1 ((uint32)(0u << PWM2_PRESCALER_SHIFT)) +#define PWM2_PRESCALE_DIVBY2 ((uint32)(1u << PWM2_PRESCALER_SHIFT)) +#define PWM2_PRESCALE_DIVBY4 ((uint32)(2u << PWM2_PRESCALER_SHIFT)) +#define PWM2_PRESCALE_DIVBY8 ((uint32)(3u << PWM2_PRESCALER_SHIFT)) +#define PWM2_PRESCALE_DIVBY16 ((uint32)(4u << PWM2_PRESCALER_SHIFT)) +#define PWM2_PRESCALE_DIVBY32 ((uint32)(5u << PWM2_PRESCALER_SHIFT)) +#define PWM2_PRESCALE_DIVBY64 ((uint32)(6u << PWM2_PRESCALER_SHIFT)) +#define PWM2_PRESCALE_DIVBY128 ((uint32)(7u << PWM2_PRESCALER_SHIFT)) + +/* TCPWM set modes */ +#define PWM2_MODE_TIMER_COMPARE ((uint32)(PWM2__COMPARE << \ + PWM2_MODE_SHIFT)) +#define PWM2_MODE_TIMER_CAPTURE ((uint32)(PWM2__CAPTURE << \ + PWM2_MODE_SHIFT)) +#define PWM2_MODE_QUAD ((uint32)(PWM2__QUAD << \ + PWM2_MODE_SHIFT)) +#define PWM2_MODE_PWM ((uint32)(PWM2__PWM << \ + PWM2_MODE_SHIFT)) +#define PWM2_MODE_PWM_DT ((uint32)(PWM2__PWM_DT << \ + PWM2_MODE_SHIFT)) +#define PWM2_MODE_PWM_PR ((uint32)(PWM2__PWM_PR << \ + PWM2_MODE_SHIFT)) + +/* Quad Modes */ +#define PWM2_MODE_X1 ((uint32)(PWM2__X1 << \ + PWM2_QUAD_MODE_SHIFT)) +#define PWM2_MODE_X2 ((uint32)(PWM2__X2 << \ + PWM2_QUAD_MODE_SHIFT)) +#define PWM2_MODE_X4 ((uint32)(PWM2__X4 << \ + PWM2_QUAD_MODE_SHIFT)) + +/* Counter modes */ +#define PWM2_COUNT_UP ((uint32)(PWM2__COUNT_UP << \ + PWM2_UPDOWN_SHIFT)) +#define PWM2_COUNT_DOWN ((uint32)(PWM2__COUNT_DOWN << \ + PWM2_UPDOWN_SHIFT)) +#define PWM2_COUNT_UPDOWN0 ((uint32)(PWM2__COUNT_UPDOWN0 << \ + PWM2_UPDOWN_SHIFT)) +#define PWM2_COUNT_UPDOWN1 ((uint32)(PWM2__COUNT_UPDOWN1 << \ + PWM2_UPDOWN_SHIFT)) + +/* PWM output invert */ +#define PWM2_INVERT_LINE ((uint32)(PWM2__INVERSE << \ + PWM2_INV_OUT_SHIFT)) +#define PWM2_INVERT_LINE_N ((uint32)(PWM2__INVERSE << \ + PWM2_INV_COMPL_OUT_SHIFT)) + +/* Trigger modes */ +#define PWM2_TRIG_RISING ((uint32)PWM2__TRIG_RISING) +#define PWM2_TRIG_FALLING ((uint32)PWM2__TRIG_FALLING) +#define PWM2_TRIG_BOTH ((uint32)PWM2__TRIG_BOTH) +#define PWM2_TRIG_LEVEL ((uint32)PWM2__TRIG_LEVEL) + +/* Interrupt mask */ +#define PWM2_INTR_MASK_TC ((uint32)PWM2__INTR_MASK_TC) +#define PWM2_INTR_MASK_CC_MATCH ((uint32)PWM2__INTR_MASK_CC_MATCH) + +/* PWM Output Controls */ +#define PWM2_CC_MATCH_SET (0x00u) +#define PWM2_CC_MATCH_CLEAR (0x01u) +#define PWM2_CC_MATCH_INVERT (0x02u) +#define PWM2_CC_MATCH_NO_CHANGE (0x03u) +#define PWM2_OVERLOW_SET (0x00u) +#define PWM2_OVERLOW_CLEAR (0x04u) +#define PWM2_OVERLOW_INVERT (0x08u) +#define PWM2_OVERLOW_NO_CHANGE (0x0Cu) +#define PWM2_UNDERFLOW_SET (0x00u) +#define PWM2_UNDERFLOW_CLEAR (0x10u) +#define PWM2_UNDERFLOW_INVERT (0x20u) +#define PWM2_UNDERFLOW_NO_CHANGE (0x30u) + +/* PWM Align */ +#define PWM2_PWM_MODE_LEFT (PWM2_CC_MATCH_CLEAR | \ + PWM2_OVERLOW_SET | \ + PWM2_UNDERFLOW_NO_CHANGE) +#define PWM2_PWM_MODE_RIGHT (PWM2_CC_MATCH_SET | \ + PWM2_OVERLOW_NO_CHANGE | \ + PWM2_UNDERFLOW_CLEAR) +#define PWM2_PWM_MODE_ASYM (PWM2_CC_MATCH_INVERT | \ + PWM2_OVERLOW_SET | \ + PWM2_UNDERFLOW_CLEAR) + +#if (PWM2_CY_TCPWM_V2) + #if(PWM2_CY_TCPWM_4000) + #define PWM2_PWM_MODE_CENTER (PWM2_CC_MATCH_INVERT | \ + PWM2_OVERLOW_NO_CHANGE | \ + PWM2_UNDERFLOW_CLEAR) + #else + #define PWM2_PWM_MODE_CENTER (PWM2_CC_MATCH_INVERT | \ + PWM2_OVERLOW_SET | \ + PWM2_UNDERFLOW_CLEAR) + #endif /* (PWM2_CY_TCPWM_4000) */ +#else + #define PWM2_PWM_MODE_CENTER (PWM2_CC_MATCH_INVERT | \ + PWM2_OVERLOW_NO_CHANGE | \ + PWM2_UNDERFLOW_CLEAR) +#endif /* (PWM2_CY_TCPWM_NEW) */ + +/* Command operations without condition */ +#define PWM2_CMD_CAPTURE (0u) +#define PWM2_CMD_RELOAD (8u) +#define PWM2_CMD_STOP (16u) +#define PWM2_CMD_START (24u) + +/* Status */ +#define PWM2_STATUS_DOWN (1u) +#define PWM2_STATUS_RUNNING (2u) + + +/*************************************** +* Function Prototypes +****************************************/ + +void PWM2_Init(void); +void PWM2_Enable(void); +void PWM2_Start(void); +void PWM2_Stop(void); + +void PWM2_SetMode(uint32 mode); +void PWM2_SetCounterMode(uint32 counterMode); +void PWM2_SetPWMMode(uint32 modeMask); +void PWM2_SetQDMode(uint32 qdMode); + +void PWM2_SetPrescaler(uint32 prescaler); +void PWM2_TriggerCommand(uint32 mask, uint32 command); +void PWM2_SetOneShot(uint32 oneShotEnable); +uint32 PWM2_ReadStatus(void); + +void PWM2_SetPWMSyncKill(uint32 syncKillEnable); +void PWM2_SetPWMStopOnKill(uint32 stopOnKillEnable); +void PWM2_SetPWMDeadTime(uint32 deadTime); +void PWM2_SetPWMInvert(uint32 mask); + +void PWM2_SetInterruptMode(uint32 interruptMask); +uint32 PWM2_GetInterruptSourceMasked(void); +uint32 PWM2_GetInterruptSource(void); +void PWM2_ClearInterrupt(uint32 interruptMask); +void PWM2_SetInterrupt(uint32 interruptMask); + +void PWM2_WriteCounter(uint32 count); +uint32 PWM2_ReadCounter(void); + +uint32 PWM2_ReadCapture(void); +uint32 PWM2_ReadCaptureBuf(void); + +void PWM2_WritePeriod(uint32 period); +uint32 PWM2_ReadPeriod(void); +void PWM2_WritePeriodBuf(uint32 periodBuf); +uint32 PWM2_ReadPeriodBuf(void); + +void PWM2_WriteCompare(uint32 compare); +uint32 PWM2_ReadCompare(void); +void PWM2_WriteCompareBuf(uint32 compareBuf); +uint32 PWM2_ReadCompareBuf(void); + +void PWM2_SetPeriodSwap(uint32 swapEnable); +void PWM2_SetCompareSwap(uint32 swapEnable); + +void PWM2_SetCaptureMode(uint32 triggerMode); +void PWM2_SetReloadMode(uint32 triggerMode); +void PWM2_SetStartMode(uint32 triggerMode); +void PWM2_SetStopMode(uint32 triggerMode); +void PWM2_SetCountMode(uint32 triggerMode); + +void PWM2_SaveConfig(void); +void PWM2_RestoreConfig(void); +void PWM2_Sleep(void); +void PWM2_Wakeup(void); + + +/*************************************** +* Registers +***************************************/ + +#define PWM2_BLOCK_CONTROL_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__TCPWM_CTRL ) +#define PWM2_BLOCK_CONTROL_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__TCPWM_CTRL ) +#define PWM2_COMMAND_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__TCPWM_CMD ) +#define PWM2_COMMAND_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__TCPWM_CMD ) +#define PWM2_INTRRUPT_CAUSE_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE ) +#define PWM2_INTRRUPT_CAUSE_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE ) +#define PWM2_CONTROL_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__CTRL ) +#define PWM2_CONTROL_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__CTRL ) +#define PWM2_STATUS_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__STATUS ) +#define PWM2_STATUS_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__STATUS ) +#define PWM2_COUNTER_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__COUNTER ) +#define PWM2_COUNTER_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__COUNTER ) +#define PWM2_COMP_CAP_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__CC ) +#define PWM2_COMP_CAP_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__CC ) +#define PWM2_COMP_CAP_BUF_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__CC_BUFF ) +#define PWM2_COMP_CAP_BUF_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__CC_BUFF ) +#define PWM2_PERIOD_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__PERIOD ) +#define PWM2_PERIOD_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__PERIOD ) +#define PWM2_PERIOD_BUF_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__PERIOD_BUFF ) +#define PWM2_PERIOD_BUF_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__PERIOD_BUFF ) +#define PWM2_TRIG_CONTROL0_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__TR_CTRL0 ) +#define PWM2_TRIG_CONTROL0_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__TR_CTRL0 ) +#define PWM2_TRIG_CONTROL1_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__TR_CTRL1 ) +#define PWM2_TRIG_CONTROL1_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__TR_CTRL1 ) +#define PWM2_TRIG_CONTROL2_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__TR_CTRL2 ) +#define PWM2_TRIG_CONTROL2_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__TR_CTRL2 ) +#define PWM2_INTERRUPT_REQ_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__INTR ) +#define PWM2_INTERRUPT_REQ_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__INTR ) +#define PWM2_INTERRUPT_SET_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__INTR_SET ) +#define PWM2_INTERRUPT_SET_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__INTR_SET ) +#define PWM2_INTERRUPT_MASK_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__INTR_MASK ) +#define PWM2_INTERRUPT_MASK_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__INTR_MASK ) +#define PWM2_INTERRUPT_MASKED_REG (*(reg32 *) PWM2_cy_m0s8_tcpwm_1__INTR_MASKED ) +#define PWM2_INTERRUPT_MASKED_PTR ( (reg32 *) PWM2_cy_m0s8_tcpwm_1__INTR_MASKED ) + + +/*************************************** +* Registers Constants +***************************************/ + +/* Mask */ +#define PWM2_MASK ((uint32)PWM2_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK) + +/* Shift constants for control register */ +#define PWM2_RELOAD_CC_SHIFT (0u) +#define PWM2_RELOAD_PERIOD_SHIFT (1u) +#define PWM2_PWM_SYNC_KILL_SHIFT (2u) +#define PWM2_PWM_STOP_KILL_SHIFT (3u) +#define PWM2_PRESCALER_SHIFT (8u) +#define PWM2_UPDOWN_SHIFT (16u) +#define PWM2_ONESHOT_SHIFT (18u) +#define PWM2_QUAD_MODE_SHIFT (20u) +#define PWM2_INV_OUT_SHIFT (20u) +#define PWM2_INV_COMPL_OUT_SHIFT (21u) +#define PWM2_MODE_SHIFT (24u) + +/* Mask constants for control register */ +#define PWM2_RELOAD_CC_MASK ((uint32)(PWM2_1BIT_MASK << \ + PWM2_RELOAD_CC_SHIFT)) +#define PWM2_RELOAD_PERIOD_MASK ((uint32)(PWM2_1BIT_MASK << \ + PWM2_RELOAD_PERIOD_SHIFT)) +#define PWM2_PWM_SYNC_KILL_MASK ((uint32)(PWM2_1BIT_MASK << \ + PWM2_PWM_SYNC_KILL_SHIFT)) +#define PWM2_PWM_STOP_KILL_MASK ((uint32)(PWM2_1BIT_MASK << \ + PWM2_PWM_STOP_KILL_SHIFT)) +#define PWM2_PRESCALER_MASK ((uint32)(PWM2_8BIT_MASK << \ + PWM2_PRESCALER_SHIFT)) +#define PWM2_UPDOWN_MASK ((uint32)(PWM2_2BIT_MASK << \ + PWM2_UPDOWN_SHIFT)) +#define PWM2_ONESHOT_MASK ((uint32)(PWM2_1BIT_MASK << \ + PWM2_ONESHOT_SHIFT)) +#define PWM2_QUAD_MODE_MASK ((uint32)(PWM2_3BIT_MASK << \ + PWM2_QUAD_MODE_SHIFT)) +#define PWM2_INV_OUT_MASK ((uint32)(PWM2_2BIT_MASK << \ + PWM2_INV_OUT_SHIFT)) +#define PWM2_MODE_MASK ((uint32)(PWM2_3BIT_MASK << \ + PWM2_MODE_SHIFT)) + +/* Shift constants for trigger control register 1 */ +#define PWM2_CAPTURE_SHIFT (0u) +#define PWM2_COUNT_SHIFT (2u) +#define PWM2_RELOAD_SHIFT (4u) +#define PWM2_STOP_SHIFT (6u) +#define PWM2_START_SHIFT (8u) + +/* Mask constants for trigger control register 1 */ +#define PWM2_CAPTURE_MASK ((uint32)(PWM2_2BIT_MASK << \ + PWM2_CAPTURE_SHIFT)) +#define PWM2_COUNT_MASK ((uint32)(PWM2_2BIT_MASK << \ + PWM2_COUNT_SHIFT)) +#define PWM2_RELOAD_MASK ((uint32)(PWM2_2BIT_MASK << \ + PWM2_RELOAD_SHIFT)) +#define PWM2_STOP_MASK ((uint32)(PWM2_2BIT_MASK << \ + PWM2_STOP_SHIFT)) +#define PWM2_START_MASK ((uint32)(PWM2_2BIT_MASK << \ + PWM2_START_SHIFT)) + +/* MASK */ +#define PWM2_1BIT_MASK ((uint32)0x01u) +#define PWM2_2BIT_MASK ((uint32)0x03u) +#define PWM2_3BIT_MASK ((uint32)0x07u) +#define PWM2_6BIT_MASK ((uint32)0x3Fu) +#define PWM2_8BIT_MASK ((uint32)0xFFu) +#define PWM2_16BIT_MASK ((uint32)0xFFFFu) + +/* Shift constant for status register */ +#define PWM2_RUNNING_STATUS_SHIFT (30u) + + +/*************************************** +* Initial Constants +***************************************/ + +#define PWM2_CTRL_QUAD_BASE_CONFIG \ + (((uint32)(PWM2_QUAD_ENCODING_MODES << PWM2_QUAD_MODE_SHIFT)) |\ + ((uint32)(PWM2_CONFIG << PWM2_MODE_SHIFT))) + +#define PWM2_CTRL_PWM_BASE_CONFIG \ + (((uint32)(PWM2_PWM_STOP_EVENT << PWM2_PWM_STOP_KILL_SHIFT)) |\ + ((uint32)(PWM2_PWM_OUT_INVERT << PWM2_INV_OUT_SHIFT)) |\ + ((uint32)(PWM2_PWM_OUT_N_INVERT << PWM2_INV_COMPL_OUT_SHIFT)) |\ + ((uint32)(PWM2_PWM_MODE << PWM2_MODE_SHIFT))) + +#define PWM2_CTRL_PWM_RUN_MODE \ + ((uint32)(PWM2_PWM_RUN_MODE << PWM2_ONESHOT_SHIFT)) + +#define PWM2_CTRL_PWM_ALIGN \ + ((uint32)(PWM2_PWM_ALIGN << PWM2_UPDOWN_SHIFT)) + +#define PWM2_CTRL_PWM_KILL_EVENT \ + ((uint32)(PWM2_PWM_KILL_EVENT << PWM2_PWM_SYNC_KILL_SHIFT)) + +#define PWM2_CTRL_PWM_DEAD_TIME_CYCLE \ + ((uint32)(PWM2_PWM_DEAD_TIME_CYCLE << PWM2_PRESCALER_SHIFT)) + +#define PWM2_CTRL_PWM_PRESCALER \ + ((uint32)(PWM2_PWM_PRESCALER << PWM2_PRESCALER_SHIFT)) + +#define PWM2_CTRL_TIMER_BASE_CONFIG \ + (((uint32)(PWM2_TC_PRESCALER << PWM2_PRESCALER_SHIFT)) |\ + ((uint32)(PWM2_TC_COUNTER_MODE << PWM2_UPDOWN_SHIFT)) |\ + ((uint32)(PWM2_TC_RUN_MODE << PWM2_ONESHOT_SHIFT)) |\ + ((uint32)(PWM2_TC_COMP_CAP_MODE << PWM2_MODE_SHIFT))) + +#define PWM2_QUAD_SIGNALS_MODES \ + (((uint32)(PWM2_QUAD_PHIA_SIGNAL_MODE << PWM2_COUNT_SHIFT)) |\ + ((uint32)(PWM2_QUAD_INDEX_SIGNAL_MODE << PWM2_RELOAD_SHIFT)) |\ + ((uint32)(PWM2_QUAD_STOP_SIGNAL_MODE << PWM2_STOP_SHIFT)) |\ + ((uint32)(PWM2_QUAD_PHIB_SIGNAL_MODE << PWM2_START_SHIFT))) + +#define PWM2_PWM_SIGNALS_MODES \ + (((uint32)(PWM2_PWM_SWITCH_SIGNAL_MODE << PWM2_CAPTURE_SHIFT)) |\ + ((uint32)(PWM2_PWM_COUNT_SIGNAL_MODE << PWM2_COUNT_SHIFT)) |\ + ((uint32)(PWM2_PWM_RELOAD_SIGNAL_MODE << PWM2_RELOAD_SHIFT)) |\ + ((uint32)(PWM2_PWM_STOP_SIGNAL_MODE << PWM2_STOP_SHIFT)) |\ + ((uint32)(PWM2_PWM_START_SIGNAL_MODE << PWM2_START_SHIFT))) + +#define PWM2_TIMER_SIGNALS_MODES \ + (((uint32)(PWM2_TC_CAPTURE_SIGNAL_MODE << PWM2_CAPTURE_SHIFT)) |\ + ((uint32)(PWM2_TC_COUNT_SIGNAL_MODE << PWM2_COUNT_SHIFT)) |\ + ((uint32)(PWM2_TC_RELOAD_SIGNAL_MODE << PWM2_RELOAD_SHIFT)) |\ + ((uint32)(PWM2_TC_STOP_SIGNAL_MODE << PWM2_STOP_SHIFT)) |\ + ((uint32)(PWM2_TC_START_SIGNAL_MODE << PWM2_START_SHIFT))) + +#define PWM2_TIMER_UPDOWN_CNT_USED \ + ((PWM2__COUNT_UPDOWN0 == PWM2_TC_COUNTER_MODE) ||\ + (PWM2__COUNT_UPDOWN1 == PWM2_TC_COUNTER_MODE)) + +#define PWM2_PWM_UPDOWN_CNT_USED \ + ((PWM2__CENTER == PWM2_PWM_ALIGN) ||\ + (PWM2__ASYMMETRIC == PWM2_PWM_ALIGN)) + +#define PWM2_PWM_PR_INIT_VALUE (1u) +#define PWM2_QUAD_PERIOD_INIT_VALUE (0x8000u) + + + +#endif /* End CY_TCPWM_PWM2_H */ + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/PWM2_ISR.c b/cores/asr650x/cores/PWM2_ISR.c new file mode 100644 index 00000000..a73afada --- /dev/null +++ b/cores/asr650x/cores/PWM2_ISR.c @@ -0,0 +1,406 @@ +/******************************************************************************* +* File Name: PWM2_ISR.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include +#include "cyapicallbacks.h" + +#if !defined(PWM2_ISR__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START PWM2_ISR_intc` */ + +/* `#END` */ + +extern cyisraddress CyRamVectors[CYINT_IRQ_BASE + CY_NUM_INTERRUPTS]; + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: PWM2_ISR_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_ISR_Start(void) +{ + /* For all we know the interrupt is active. */ + PWM2_ISR_Disable(); + + /* Set the ISR to point to the PWM2_ISR Interrupt. */ + PWM2_ISR_SetVector(&PWM2_ISR_Interrupt); + + /* Set the priority. */ + PWM2_ISR_SetPriority((uint8)PWM2_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + PWM2_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_ISR_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + PWM2_ISR_Disable(); + + /* Set the ISR to point to the PWM2_ISR Interrupt. */ + PWM2_ISR_SetVector(address); + + /* Set the priority. */ + PWM2_ISR_SetPriority((uint8)PWM2_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + PWM2_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_ISR_Stop(void) +{ + /* Disable this interrupt. */ + PWM2_ISR_Disable(); + + /* Set the ISR to point to the passive one. */ + PWM2_ISR_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for PWM2_ISR. +* +* Add custom code between the START and END comments to keep the next version +* of this file from over-writing your code. +* +* Note You may use either the default ISR by using this API, or you may define +* your own separate ISR through ISR_StartEx(). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(PWM2_ISR_Interrupt) +{ + #ifdef PWM2_ISR_INTERRUPT_INTERRUPT_CALLBACK + PWM2_ISR_Interrupt_InterruptCallback(); + #endif /* PWM2_ISR_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START PWM2_ISR_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling PWM2_ISR_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use PWM2_ISR_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_ISR_SetVector(cyisraddress address) +{ + CyRamVectors[CYINT_IRQ_BASE + PWM2_ISR__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress PWM2_ISR_GetVector(void) +{ + return CyRamVectors[CYINT_IRQ_BASE + PWM2_ISR__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling PWM2_ISR_Start or PWM2_ISR_StartEx will +* override any effect this API would have had. This API should only be called +* after PWM2_ISR_Start or PWM2_ISR_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_ISR_SetPriority(uint8 priority) +{ + uint8 interruptState; + uint32 priorityOffset = ((PWM2_ISR__INTC_NUMBER % 4u) * 8u) + 6u; + + interruptState = CyEnterCriticalSection(); + *PWM2_ISR_INTC_PRIOR = (*PWM2_ISR_INTC_PRIOR & (uint32)(~PWM2_ISR__INTC_PRIOR_MASK)) | + ((uint32)priority << priorityOffset); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 PWM2_ISR_GetPriority(void) +{ + uint32 priority; + uint32 priorityOffset = ((PWM2_ISR__INTC_NUMBER % 4u) * 8u) + 6u; + + priority = (*PWM2_ISR_INTC_PRIOR & PWM2_ISR__INTC_PRIOR_MASK) >> priorityOffset; + + return (uint8)priority; +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_ISR_Enable(void) +{ + /* Enable the general interrupt. */ + *PWM2_ISR_INTC_SET_EN = PWM2_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 PWM2_ISR_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*PWM2_ISR_INTC_SET_EN & (uint32)PWM2_ISR__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_ISR_Disable(void) +{ + /* Disable the general interrupt. */ + *PWM2_ISR_INTC_CLR_EN = PWM2_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void PWM2_ISR_SetPending(void) +{ + *PWM2_ISR_INTC_SET_PD = PWM2_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: PWM2_ISR_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_ISR_ClearPending(void) +{ + *PWM2_ISR_INTC_CLR_PD = PWM2_ISR__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/PWM2_ISR.h b/cores/asr650x/cores/PWM2_ISR.h new file mode 100644 index 00000000..69196a65 --- /dev/null +++ b/cores/asr650x/cores/PWM2_ISR.h @@ -0,0 +1,82 @@ +/******************************************************************************* +* File Name: PWM2_ISR.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_PWM2_ISR_H) +#define CY_ISR_PWM2_ISR_H + + +#include +#include + + +#define PWM2_ISR__INTC_CLR_EN_REG CYREG_CM0P_ICER +#define PWM2_ISR__INTC_CLR_PD_REG CYREG_CM0P_ICPR +#define PWM2_ISR__INTC_MASK 0x800000u +#define PWM2_ISR__INTC_NUMBER 23u +#define PWM2_ISR__INTC_PRIOR_MASK 0xC0000000u +#define PWM2_ISR__INTC_PRIOR_NUM 3u +#define PWM2_ISR__INTC_PRIOR_REG CYREG_CM0P_IPR5 +#define PWM2_ISR__INTC_SET_EN_REG CYREG_CM0P_ISER +#define PWM2_ISR__INTC_SET_PD_REG CYREG_CM0P_ISPR + +/* Interrupt Controller API. */ +void PWM2_ISR_Start(void); +void PWM2_ISR_StartEx(cyisraddress address); +void PWM2_ISR_Stop(void); + +CY_ISR_PROTO(PWM2_ISR_Interrupt); + +void PWM2_ISR_SetVector(cyisraddress address); +cyisraddress PWM2_ISR_GetVector(void); + +void PWM2_ISR_SetPriority(uint8 priority); +uint8 PWM2_ISR_GetPriority(void); + +void PWM2_ISR_Enable(void); +uint8 PWM2_ISR_GetState(void); +void PWM2_ISR_Disable(void); + +void PWM2_ISR_SetPending(void); +void PWM2_ISR_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the PWM2_ISR ISR. */ +#define PWM2_ISR_INTC_VECTOR ((reg32 *) PWM2_ISR__INTC_VECT) + +/* Address of the PWM2_ISR ISR priority. */ +#define PWM2_ISR_INTC_PRIOR ((reg32 *) PWM2_ISR__INTC_PRIOR_REG) + +/* Priority of the PWM2_ISR interrupt. */ +#define PWM2_ISR_INTC_PRIOR_NUMBER PWM2_ISR__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable PWM2_ISR interrupt. */ +#define PWM2_ISR_INTC_SET_EN ((reg32 *) PWM2_ISR__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the PWM2_ISR interrupt. */ +#define PWM2_ISR_INTC_CLR_EN ((reg32 *) PWM2_ISR__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the PWM2_ISR interrupt state to pending. */ +#define PWM2_ISR_INTC_SET_PD ((reg32 *) PWM2_ISR__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the PWM2_ISR interrupt. */ +#define PWM2_ISR_INTC_CLR_PD ((reg32 *) PWM2_ISR__INTC_CLR_PD_REG) + + + +#endif /* CY_ISR_PWM2_ISR_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/PWM2_PM.c b/cores/asr650x/cores/PWM2_PM.c new file mode 100644 index 00000000..641c7355 --- /dev/null +++ b/cores/asr650x/cores/PWM2_PM.c @@ -0,0 +1,119 @@ +/******************************************************************************* +* File Name: PWM2_PM.c +* Version 2.10 +* +* Description: +* This file contains the setup, control, and status commands to support +* the component operations in the low power mode. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2013-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "PWM2.h" + +static PWM2_BACKUP_STRUCT PWM2_backup; + + +/******************************************************************************* +* Function Name: PWM2_SaveConfig +******************************************************************************** +* +* Summary: +* All configuration registers are retention. Nothing to save here. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_SaveConfig(void) +{ + +} + + +/******************************************************************************* +* Function Name: PWM2_Sleep +******************************************************************************** +* +* Summary: +* Stops the component operation and saves the user configuration. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_Sleep(void) +{ + if(0u != (PWM2_BLOCK_CONTROL_REG & PWM2_MASK)) + { + PWM2_backup.enableState = 1u; + } + else + { + PWM2_backup.enableState = 0u; + } + + PWM2_Stop(); + PWM2_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: PWM2_RestoreConfig +******************************************************************************** +* +* Summary: +* All configuration registers are retention. Nothing to restore here. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_RestoreConfig(void) +{ + +} + + +/******************************************************************************* +* Function Name: PWM2_Wakeup +******************************************************************************** +* +* Summary: +* Restores the user configuration and restores the enable state. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void PWM2_Wakeup(void) +{ + PWM2_RestoreConfig(); + + if(0u != PWM2_backup.enableState) + { + PWM2_Enable(); + } +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/Print.cpp b/cores/asr650x/cores/Print.cpp new file mode 100644 index 00000000..8c295347 --- /dev/null +++ b/cores/asr650x/cores/Print.cpp @@ -0,0 +1,317 @@ +/* + Print.cpp - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 23 November 2006 by David A. Mellis + Modified December 2014 by Ivan Grokhotkov + Modified May 2015 by Michael C. Miller - ESP31B progmem support + */ + +#include +#include +#include +#include +#include "Arduino.h" + +#include "Print.h" +extern "C" { + #include "time.h" +} + +// Public Methods ////////////////////////////////////////////////////////////// + +/* default implementation: may be overridden */ +size_t Print::write(const uint8_t *buffer, size_t size) +{ + size_t n = 0; + while(size--) { + n += write(*buffer++); + } + return n; +} + +size_t Print::printf(const char *format, ...) +{ + char loc_buf[64]; + char * temp = loc_buf; + va_list arg; + va_list copy; + va_start(arg, format); + va_copy(copy, arg); + size_t len = vsnprintf(NULL, 0, format, arg); + va_end(copy); + if(len >= sizeof(loc_buf)){ + temp = new char[len+1]; + if(temp == NULL) { + return 0; + } + } + len = vsnprintf(temp, len+1, format, arg); + write((uint8_t*)temp, len); + va_end(arg); + if(len >= sizeof(loc_buf)){ + delete[] temp; + } + return len; +} + +size_t Print::print(const __FlashStringHelper *ifsh) +{ + return print(reinterpret_cast(ifsh)); +} + +size_t Print::print(const String &s) +{ + return write(s.c_str(), s.length()); +} + +size_t Print::print(const char str[]) +{ + return write(str); +} + +size_t Print::print(char c) +{ + return write(c); +} + +size_t Print::print(unsigned char b, int base) +{ + return print((unsigned long) b, base); +} + +size_t Print::print(int n, int base) +{ + return print((long) n, base); +} + +size_t Print::print(unsigned int n, int base) +{ + return print((unsigned long) n, base); +} + +size_t Print::print(long n, int base) +{ + if(base == 0) { + return write(n); + } else if(base == 10) { + if(n < 0) { + int t = print('-'); + n = -n; + return printNumber(n, 10) + t; + } + return printNumber(n, 10); + } else { + return printNumber(n, base); + } +} + +size_t Print::print(unsigned long n, int base) +{ + if(base == 0) { + return write(n); + } else { + return printNumber(n, base); + } +} + +size_t Print::print(double n, int digits) +{ + return printFloat(n, digits); +} + +size_t Print::println(const __FlashStringHelper *ifsh) +{ + size_t n = print(ifsh); + n += println(); + return n; +} + +size_t Print::print(const Printable& x) +{ + return x.printTo(*this); +} + +size_t Print::print(struct tm * timeinfo, const char * format) +{ + const char * f = format; + if(!f){ + f = "%c"; + } + char buf[64]; + size_t written = strftime(buf, 64, f, timeinfo); + print(buf); + return written; +} + +size_t Print::println(void) +{ + return print("\r\n"); +} + +size_t Print::println(const String &s) +{ + size_t n = print(s); + n += println(); + return n; +} + +size_t Print::println(const char c[]) +{ + size_t n = print(c); + n += println(); + return n; +} + +size_t Print::println(char c) +{ + size_t n = print(c); + n += println(); + return n; +} + +size_t Print::println(unsigned char b, int base) +{ + size_t n = print(b, base); + n += println(); + return n; +} + +size_t Print::println(int num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(unsigned int num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(long num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(unsigned long num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(double num, int digits) +{ + size_t n = print(num, digits); + n += println(); + return n; +} + +size_t Print::println(const Printable& x) +{ + size_t n = print(x); + n += println(); + return n; +} + +size_t Print::println(struct tm * timeinfo, const char * format) +{ + size_t n = print(timeinfo, format); + n += println(); + return n; +} + +// Private Methods ///////////////////////////////////////////////////////////// + +size_t Print::printNumber(unsigned long n, uint8_t base) +{ + char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. + char *str = &buf[sizeof(buf) - 1]; + + *str = '\0'; + + // prevent crash if called with base == 1 + if(base < 2) { + base = 10; + } + + do { + unsigned long m = n; + n /= base; + char c = m - base * n; + *--str = c < 10 ? c + '0' : c + 'A' - 10; + } while(n); + + return write(str); +} + +size_t Print::printFloat(double number, uint8_t digits) +{ + size_t n = 0; + + if(isnan(number)) { + return print("nan"); + } + if(isinf(number)) { + return print("inf"); + } + if(number > 4294967040.0) { + return print("ovf"); // constant determined empirically + } + if(number < -4294967040.0) { + return print("ovf"); // constant determined empirically + } + + // Handle negative numbers + if(number < 0.0) { + n += print('-'); + number = -number; + } + + // Round correctly so that print(1.999, 2) prints as "2.00" + double rounding = 0.5; + for(uint8_t i = 0; i < digits; ++i) { + rounding /= 10.0; + } + + number += rounding; + + // Extract the integer part of the number and print it + unsigned long int_part = (unsigned long) number; + double remainder = number - (double) int_part; + n += print(int_part); + + // Print the decimal point, but only if there are digits beyond + if(digits > 0) { + n += print("."); + } + + // Extract digits from the remainder one at a time + while(digits-- > 0) { + remainder *= 10.0; + int toPrint = int(remainder); + n += print(toPrint); + remainder -= toPrint; + } + + return n; +} diff --git a/cores/asr650x/cores/Print.h b/cores/asr650x/cores/Print.h new file mode 100644 index 00000000..6c3ecb53 --- /dev/null +++ b/cores/asr650x/cores/Print.h @@ -0,0 +1,108 @@ +/* + Print.h - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Print_h +#define Print_h + +#include +#include +#include +#include +#include +#include + + +#include "WString.h" +#include "Printable.h" + +#define DEC 10 +#define HEX 16 +#define OCT 8 +#define BIN 2 + +class Print +{ +private: + int write_error; + size_t printNumber(unsigned long, uint8_t); + size_t printFloat(double, uint8_t); +protected: + void setWriteError(int err = 1) + { + write_error = err; + } +public: + Print() : + write_error(0) + { + } + virtual ~Print() {} + int getWriteError() + { + return write_error; + } + void clearWriteError() + { + setWriteError(0); + } + + virtual size_t write(uint8_t) = 0; + size_t write(const char *str) + { + if(str == NULL) { + return 0; + } + return write((const uint8_t *) str, strlen(str)); + } + virtual size_t write(const uint8_t *buffer, size_t size); + size_t write(const char *buffer, size_t size) + { + return write((const uint8_t *) buffer, size); + } + + size_t printf(const char * format, ...) __attribute__ ((format (printf, 2, 3))); + size_t print(const __FlashStringHelper *); + size_t print(const String &); + size_t print(const char[]); + size_t print(char); + size_t print(unsigned char, int = DEC); + size_t print(int, int = DEC); + size_t print(unsigned int, int = DEC); + size_t print(long, int = DEC); + size_t print(unsigned long, int = DEC); + size_t print(double, int = 2); + size_t print(const Printable&); + size_t print(struct tm * timeinfo, const char * format = NULL); + + size_t println(const __FlashStringHelper *); + size_t println(const String &s); + size_t println(const char[]); + size_t println(char); + size_t println(unsigned char, int = DEC); + size_t println(int, int = DEC); + size_t println(unsigned int, int = DEC); + size_t println(long, int = DEC); + size_t println(unsigned long, int = DEC); + size_t println(double, int = 2); + size_t println(const Printable&); + size_t println(struct tm * timeinfo, const char * format = NULL); + size_t println(void); +}; + +#endif diff --git a/cores/asr650x/cores/Printable.h b/cores/asr650x/cores/Printable.h new file mode 100644 index 00000000..aa4e62f8 --- /dev/null +++ b/cores/asr650x/cores/Printable.h @@ -0,0 +1,41 @@ +/* + Printable.h - Interface class that allows printing of complex types + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Printable_h +#define Printable_h + +#include + +class Print; + +/** The Printable class provides a way for new classes to allow themselves to be printed. + By deriving from Printable and implementing the printTo method, it will then be possible + for users to print out instances of this class by passing them into the usual + Print::print and Print::println methods. + */ + +class Printable +{ +public: + virtual ~Printable() {} + virtual size_t printTo(Print& p) const = 0; +}; + +#endif + diff --git a/cores/asr650x/cores/Stream.cpp b/cores/asr650x/cores/Stream.cpp new file mode 100644 index 00000000..131bf346 --- /dev/null +++ b/cores/asr650x/cores/Stream.cpp @@ -0,0 +1,275 @@ +/* + Stream.cpp - adds parsing methods to Stream class + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Created July 2011 + parsing functions based on TextFinder library by Michael Margolis + */ + +#include "Arduino.h" +#include "Stream.h" + + +#define PARSE_TIMEOUT 1000 // default number of milli-seconds to wait +#define NO_SKIP_CHAR 1 // a magic char not found in a valid ASCII numeric field + +// private method to read stream with timeout +int Stream::timedRead() +{ + return -1; // -1 indicates timeout +} + +// private method to peek stream with timeout +int Stream::timedPeek() +{ + return -1; // -1 indicates timeout +} + +// returns peek of the next digit in the stream or -1 if timeout +// discards non-numeric characters +int Stream::peekNextDigit() +{ + int c; + while(1) { + c = timedPeek(); + if(c < 0) { + return c; // timeout + } + if(c == '-') { + return c; + } + if(c >= '0' && c <= '9') { + return c; + } + read(); // discard non-numeric + } +} + +// Public Methods +////////////////////////////////////////////////////////////// + +void Stream::setTimeout(unsigned long timeout) // sets the maximum number of milliseconds to wait +{ + _timeout = timeout; +} + +// find returns true if the target string is found +bool Stream::find(const char *target) +{ + return findUntil(target, (char*) ""); +} + +// reads data from the stream until the target string of given length is found +// returns true if target string is found, false if timed out +bool Stream::find(const char *target, size_t length) +{ + return findUntil(target, length, NULL, 0); +} + +// as find but search ends if the terminator string is found +bool Stream::findUntil(const char *target, const char *terminator) +{ + return findUntil(target, strlen(target), terminator, strlen(terminator)); +} + +// reads data from the stream until the target string of the given length is found +// search terminated if the terminator string is found +// returns true if target string is found, false if terminated or timed out +bool Stream::findUntil(const char *target, size_t targetLen, const char *terminator, size_t termLen) +{ + size_t index = 0; // maximum target string length is 64k bytes! + size_t termIndex = 0; + int c; + + if(*target == 0) { + return true; // return true if target is a null string + } + while((c = timedRead()) > 0) { + + if(c != target[index]) { + index = 0; // reset index if any char does not match + } + + if(c == target[index]) { + //////Serial.print("found "); Serial.write(c); Serial.print("index now"); Serial.println(index+1); + if(++index >= targetLen) { // return true if all chars in the target match + return true; + } + } + + if(termLen > 0 && c == terminator[termIndex]) { + if(++termIndex >= termLen) { + return false; // return false if terminate string found before target string + } + } else { + termIndex = 0; + } + } + return false; +} + +// returns the first valid (long) integer value from the current position. +// initial characters that are not digits (or the minus sign) are skipped +// function is terminated by the first character that is not a digit. +long Stream::parseInt() +{ + return parseInt(NO_SKIP_CHAR); // terminate on first non-digit character (or timeout) +} + +// as above but a given skipChar is ignored +// this allows format characters (typically commas) in values to be ignored +long Stream::parseInt(char skipChar) +{ + boolean isNegative = false; + long value = 0; + int c; + + c = peekNextDigit(); + // ignore non numeric leading characters + if(c < 0) { + return 0; // zero returned if timeout + } + + do { + if(c == skipChar) { + } // ignore this charactor + else if(c == '-') { + isNegative = true; + } else if(c >= '0' && c <= '9') { // is c a digit? + value = value * 10 + c - '0'; + } + read(); // consume the character we got with peek + c = timedPeek(); + } while((c >= '0' && c <= '9') || c == skipChar); + + if(isNegative) { + value = -value; + } + return value; +} + +// as parseInt but returns a floating point value +float Stream::parseFloat() +{ + return parseFloat(NO_SKIP_CHAR); +} + +// as above but the given skipChar is ignored +// this allows format characters (typically commas) in values to be ignored +float Stream::parseFloat(char skipChar) +{ + boolean isNegative = false; + boolean isFraction = false; + long value = 0; + int c; + float fraction = 1.0; + + c = peekNextDigit(); + // ignore non numeric leading characters + if(c < 0) { + return 0; // zero returned if timeout + } + + do { + if(c == skipChar) { + } // ignore + else if(c == '-') { + isNegative = true; + } else if(c == '.') { + isFraction = true; + } else if(c >= '0' && c <= '9') { // is c a digit? + value = value * 10 + c - '0'; + if(isFraction) { + fraction *= 0.1; + } + } + read(); // consume the character we got with peek + c = timedPeek(); + } while((c >= '0' && c <= '9') || c == '.' || c == skipChar); + + if(isNegative) { + value = -value; + } + if(isFraction) { + return value * fraction; + } else { + return value; + } +} + +// read characters from stream into buffer +// terminates if length characters have been read, or timeout (see setTimeout) +// returns the number of characters placed in the buffer +// the buffer is NOT null terminated. +// +size_t Stream::readBytes(char *buffer, size_t length) +{ + size_t count = 0; + while(count < length) { + int c = timedRead(); + if(c < 0) { + break; + } + *buffer++ = (char) c; + count++; + } + return count; +} + +// as readBytes with terminator character +// terminates if length characters have been read, timeout, or if the terminator character detected +// returns the number of characters placed in the buffer (0 means no valid data found) + +size_t Stream::readBytesUntil(char terminator, char *buffer, size_t length) +{ + if(length < 1) { + return 0; + } + size_t index = 0; + while(index < length) { + int c = timedRead(); + if(c < 0 || c == terminator) { + break; + } + *buffer++ = (char) c; + index++; + } + return index; // return number of characters, not including null terminator +} + +String Stream::readString() +{ + String ret; + int c = timedRead(); + while(c >= 0) { + ret += (char) c; + c = timedRead(); + } + return ret; +} + +String Stream::readStringUntil(char terminator) +{ + String ret; + int c = timedRead(); + while(c >= 0 && c != terminator) { + ret += (char) c; + c = timedRead(); + } + return ret; +} + diff --git a/cores/asr650x/cores/Stream.h b/cores/asr650x/cores/Stream.h new file mode 100644 index 00000000..dd67c7aa --- /dev/null +++ b/cores/asr650x/cores/Stream.h @@ -0,0 +1,128 @@ +/* + Stream.h - base class for character-based streams. + Copyright (c) 2010 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + parsing functions based on TextFinder library by Michael Margolis + */ + +#ifndef Stream_h +#define Stream_h + +#include +#include "Print.h" + +// compatability macros for testing +/* + #define getInt() parseInt() + #define getInt(skipChar) parseInt(skipchar) + #define getFloat() parseFloat() + #define getFloat(skipChar) parseFloat(skipChar) + #define getString( pre_string, post_string, buffer, length) + readBytesBetween( pre_string, terminator, buffer, length) + */ + +class Stream: public Print +{ +protected: + unsigned long _timeout; // number of milliseconds to wait for the next char before aborting timed read + unsigned long _startMillis; // used for timeout measurement + int timedRead(); // private method to read stream with timeout + int timedPeek(); // private method to peek stream with timeout + int peekNextDigit(); // returns the next numeric digit in the stream or -1 if timeout + +public: + virtual int available() = 0; + virtual uint32 read() = 0; + virtual int peek() = 0; + virtual void flush() = 0; + + Stream():_startMillis(0) + { + _timeout = 1000; + } + virtual ~Stream() {} + +// parsing methods + + void setTimeout(unsigned long timeout); // sets maximum milliseconds to wait for stream data, default is 1 second + + bool find(const char *target); // reads data from the stream until the target string is found + bool find(uint8_t *target) + { + return find((char *) target); + } + // returns true if target string is found, false if timed out (see setTimeout) + + bool find(const char *target, size_t length); // reads data from the stream until the target string of given length is found + bool find(const uint8_t *target, size_t length) + { + return find((char *) target, length); + } + // returns true if target string is found, false if timed out + + bool find(char target) + { + return find (&target, 1); + } + + bool findUntil(const char *target, const char *terminator); // as find but search ends if the terminator string is found + bool findUntil(const uint8_t *target, const char *terminator) + { + return findUntil((char *) target, terminator); + } + + bool findUntil(const char *target, size_t targetLen, const char *terminate, size_t termLen); // as above but search ends if the terminate string is found + bool findUntil(const uint8_t *target, size_t targetLen, const char *terminate, size_t termLen) + { + return findUntil((char *) target, targetLen, terminate, termLen); + } + + long parseInt(); // returns the first valid (long) integer value from the current position. + // initial characters that are not digits (or the minus sign) are skipped + // integer is terminated by the first character that is not a digit. + + float parseFloat(); // float version of parseInt + + size_t readBytes(char *buffer, size_t length); // read chars from stream into buffer + size_t readBytes(uint8_t *buffer, size_t length) + { + return readBytes((char *) buffer, length); + } + // terminates if length characters have been read or timeout (see setTimeout) + // returns the number of characters placed in the buffer (0 means no valid data found) + + size_t readBytesUntil(char terminator, char *buffer, size_t length); // as readBytes with terminator character + size_t readBytesUntil(char terminator, uint8_t *buffer, size_t length) + { + return readBytesUntil(terminator, (char *) buffer, length); + } + // terminates if length characters have been read, timeout, or if the terminator character detected + // returns the number of characters placed in the buffer (0 means no valid data found) + + // Arduino String functions to be added here + String readString(); + String readStringUntil(char terminator); + +protected: + long parseInt(char skipChar); // as above but the given skipChar is ignored + // as above but the given skipChar is ignored + // this allows format characters (typically commas) in values to be ignored + + float parseFloat(char skipChar); // as above but the given skipChar is ignored +}; + +#endif diff --git a/cores/asr650x/cores/WString.cpp b/cores/asr650x/cores/WString.cpp new file mode 100644 index 00000000..c16f7b39 --- /dev/null +++ b/cores/asr650x/cores/WString.cpp @@ -0,0 +1,914 @@ +/* + WString.cpp - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All rights reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + Modified by Ivan Grokhotkov, 2014 - ESP31B support + Modified by Michael C. Miller, 2015 - ESP31B progmem support + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "WString.h" +#include "stdlib_noniso.h" + + +/*********************************************/ +/* Constructors */ +/*********************************************/ + +String::String(const char *cstr) +{ + init(); + if(cstr) { + copy(cstr, strlen(cstr)); + } +} + +String::String(const String &value) +{ + init(); + *this = value; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String::String(String &&rval) +{ + init(); + move(rval); +} + +String::String(StringSumHelper &&rval) +{ + init(); + move(rval); +} +#endif + +String::String(char c) +{ + init(); + char buf[2]; + buf[0] = c; + buf[1] = 0; + *this = buf; +} + +String::String(unsigned char value, unsigned char base) +{ + init(); + char buf[1 + 8 * sizeof(unsigned char)]; + utoa(value, buf, base); + *this = buf; +} + +String::String(int value, unsigned char base) +{ + init(); + char buf[2 + 8 * sizeof(int)]; + itoa(value, buf, base); + *this = buf; +} + +String::String(unsigned int value, unsigned char base) +{ + init(); + char buf[1 + 8 * sizeof(unsigned int)]; + utoa(value, buf, base); + *this = buf; +} + +String::String(long value, unsigned char base) +{ + init(); + char buf[2 + 8 * sizeof(long)]; + ltoa(value, buf, base); + *this = buf; +} + +String::String(unsigned long value, unsigned char base) +{ + init(); + char buf[1 + 8 * sizeof(unsigned long)]; + ultoa(value, buf, base); + *this = buf; +} + +String::String(float value, unsigned char decimalPlaces) +{ + init(); + char buf[33]; + *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); +} + +String::String(double value, unsigned char decimalPlaces) +{ + init(); + char buf[33]; + *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); +} + +String::~String() +{ + if(buffer) { + free(buffer); + } + init(); +} + +// /*********************************************/ +// /* Memory Management */ +// /*********************************************/ + +inline void String::init(void) +{ + buffer = NULL; + capacity = 0; + len = 0; +} + +void String::invalidate(void) +{ + if(buffer) { + free(buffer); + } + init(); +} + +unsigned char String::reserve(unsigned int size) +{ + if(buffer && capacity >= size) { + return 1; + } + if(changeBuffer(size)) { + if(len == 0) { + buffer[0] = 0; + } + return 1; + } + return 0; +} + +unsigned char String::changeBuffer(unsigned int maxStrLen) +{ + size_t newSize = ((maxStrLen + 16) & (~0xf)) - 1; + char *newbuffer = (char *) realloc(buffer, newSize+1); + if(newbuffer) { + if(newSize > len){ + if(newSize > capacity){ + memset(newbuffer+capacity, 0, newSize-capacity); + } + } else { + //new buffer can not fit the old len + newbuffer[newSize] = 0; + len = newSize; + } + capacity = newSize; + buffer = newbuffer; + return 1; + } + //log_e("realloc failed! Buffer unchanged"); + return 0; +} + +// /*********************************************/ +// /* Copy and Move */ +// /*********************************************/ + +String & String::copy(const char *cstr, unsigned int length) +{ + if(!reserve(length)) { + invalidate(); + return *this; + } + len = length; + strcpy(buffer, cstr); + return *this; +} + +String & String::copy(const __FlashStringHelper *pstr, unsigned int length) +{ + return copy(reinterpret_cast(pstr), length); +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +void String::move(String &rhs) +{ + if(buffer) { + if(capacity >= rhs.len) { + strcpy(buffer, rhs.buffer); + len = rhs.len; + rhs.len = 0; + return; + } else { + free(buffer); + } + } + buffer = rhs.buffer; + capacity = rhs.capacity; + len = rhs.len; + rhs.buffer = NULL; + rhs.capacity = 0; + rhs.len = 0; +} +#endif + +String & String::operator =(const String &rhs) +{ + if(this == &rhs) { + return *this; + } + + if(rhs.buffer) { + copy(rhs.buffer, rhs.len); + } else { + invalidate(); + } + + return *this; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String & String::operator =(String &&rval) +{ + if(this != &rval) { + move(rval); + } + return *this; +} + +String & String::operator =(StringSumHelper &&rval) +{ + if(this != &rval) { + move(rval); + } + return *this; +} +#endif + +String & String::operator =(const char *cstr) +{ + if(cstr) { + copy(cstr, strlen(cstr)); + } else { + invalidate(); + } + + return *this; +} + +String & String::operator = (const __FlashStringHelper *pstr) +{ + if (pstr) copy(pstr, strlen_P((PGM_P)pstr)); + else invalidate(); + + return *this; +} + +// /*********************************************/ +// /* concat */ +// /*********************************************/ + +unsigned char String::concat(const String &s) +{ + return concat(s.buffer, s.len); +} + +unsigned char String::concat(const char *cstr, unsigned int length) +{ + unsigned int newlen = len + length; + if(!cstr) { + return 0; + } + if(length == 0) { + return 1; + } + if(!reserve(newlen)) { + return 0; + } + strcpy(buffer + len, cstr); + len = newlen; + return 1; +} + +unsigned char String::concat(const char *cstr) +{ + if(!cstr) { + return 0; + } + return concat(cstr, strlen(cstr)); +} + +unsigned char String::concat(char c) +{ + char buf[2]; + buf[0] = c; + buf[1] = 0; + return concat(buf, 1); +} + +unsigned char String::concat(unsigned char num) +{ + char buf[1 + 3 * sizeof(unsigned char)]; + itoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(int num) +{ + char buf[2 + 3 * sizeof(int)]; + itoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(unsigned int num) +{ + char buf[1 + 3 * sizeof(unsigned int)]; + utoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(long num) +{ + char buf[2 + 3 * sizeof(long)]; + ltoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(unsigned long num) +{ + char buf[1 + 3 * sizeof(unsigned long)]; + ultoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(float num) +{ + char buf[20]; + char* string = dtostrf(num, 4, 2, buf); + return concat(string, strlen(string)); +} + +unsigned char String::concat(double num) +{ + char buf[20]; + char* string = dtostrf(num, 4, 2, buf); + return concat(string, strlen(string)); +} + +unsigned char String::concat(const __FlashStringHelper * str) +{ + return concat(reinterpret_cast(str)); +} + +/*********************************************/ +/* Concatenate */ +/*********************************************/ + +StringSumHelper & operator +(const StringSumHelper &lhs, const String &rhs) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(rhs.buffer, rhs.len)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, const char *cstr) +{ + StringSumHelper &a = const_cast(lhs); + if(!cstr || !a.concat(cstr, strlen(cstr))) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, char c) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(c)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, unsigned char num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, int num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, unsigned int num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, long num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, unsigned long num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, float num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator +(const StringSumHelper &lhs, double num) +{ + StringSumHelper &a = const_cast(lhs); + if(!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(rhs)) a.invalidate(); + return a; +} + +// /*********************************************/ +// /* Comparison */ +// /*********************************************/ + +int String::compareTo(const String &s) const +{ + if(!buffer || !s.buffer) { + if(s.buffer && s.len > 0) { + return 0 - *(unsigned char *) s.buffer; + } + if(buffer && len > 0) { + return *(unsigned char *) buffer; + } + return 0; + } + return strcmp(buffer, s.buffer); +} + +unsigned char String::equals(const String &s2) const +{ + return (len == s2.len && compareTo(s2) == 0); +} + +unsigned char String::equals(const char *cstr) const +{ + if(len == 0) { + return (cstr == NULL || *cstr == 0); + } + if(cstr == NULL) { + return buffer[0] == 0; + } + return strcmp(buffer, cstr) == 0; +} + +unsigned char String::operator<(const String &rhs) const +{ + return compareTo(rhs) < 0; +} + +unsigned char String::operator>(const String &rhs) const +{ + return compareTo(rhs) > 0; +} + +unsigned char String::operator<=(const String &rhs) const +{ + return compareTo(rhs) <= 0; +} + +unsigned char String::operator>=(const String &rhs) const +{ + return compareTo(rhs) >= 0; +} + +unsigned char String::equalsIgnoreCase(const String &s2) const +{ + if(this == &s2) { + return 1; + } + if(len != s2.len) { + return 0; + } + if(len == 0) { + return 1; + } + const char *p1 = buffer; + const char *p2 = s2.buffer; + while(*p1) { + if(tolower(*p1++) != tolower(*p2++)) { + return 0; + } + } + return 1; +} + +unsigned char String::startsWith(const String &s2) const +{ + if(len < s2.len) { + return 0; + } + return startsWith(s2, 0); +} + +unsigned char String::startsWith(const String &s2, unsigned int offset) const +{ + if(offset > len - s2.len || !buffer || !s2.buffer) { + return 0; + } + return strncmp(&buffer[offset], s2.buffer, s2.len) == 0; +} + +unsigned char String::endsWith(const String &s2) const +{ + if(len < s2.len || !buffer || !s2.buffer) { + return 0; + } + return strcmp(&buffer[len - s2.len], s2.buffer) == 0; +} + +// /*********************************************/ +// /* Character Access */ +// /*********************************************/ + +char String::charAt(unsigned int loc) const +{ + return operator[](loc); +} + +void String::setCharAt(unsigned int loc, char c) +{ + if(loc < len) { + buffer[loc] = c; + } +} + +char & String::operator[](unsigned int index) +{ + static char dummy_writable_char; + if(index >= len || !buffer) { + dummy_writable_char = 0; + return dummy_writable_char; + } + return buffer[index]; +} + +char String::operator[](unsigned int index) const +{ + if(index >= len || !buffer) { + return 0; + } + return buffer[index]; +} + +void String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const +{ + if(!bufsize || !buf) { + return; + } + if(index >= len) { + buf[0] = 0; + return; + } + unsigned int n = bufsize - 1; + if(n > len - index) { + n = len - index; + } + strncpy((char *) buf, buffer + index, n); + buf[n] = 0; +} + +// /*********************************************/ +// /* Search */ +// /*********************************************/ + +int String::indexOf(char c) const +{ + return indexOf(c, 0); +} + +int String::indexOf(char ch, unsigned int fromIndex) const +{ + if(fromIndex >= len) { + return -1; + } + const char* temp = strchr(buffer + fromIndex, ch); + if(temp == NULL) { + return -1; + } + return temp - buffer; +} + +int String::indexOf(const String &s2) const +{ + return indexOf(s2, 0); +} + +int String::indexOf(const String &s2, unsigned int fromIndex) const +{ + if(fromIndex >= len) { + return -1; + } + const char *found = strstr(buffer + fromIndex, s2.buffer); + if(found == NULL) { + return -1; + } + return found - buffer; +} + +int String::lastIndexOf(char theChar) const +{ + return lastIndexOf(theChar, len - 1); +} + +int String::lastIndexOf(char ch, unsigned int fromIndex) const +{ + if(fromIndex >= len) { + return -1; + } + char tempchar = buffer[fromIndex + 1]; + buffer[fromIndex + 1] = '\0'; + char* temp = strrchr(buffer, ch); + buffer[fromIndex + 1] = tempchar; + if(temp == NULL) { + return -1; + } + return temp - buffer; +} + +int String::lastIndexOf(const String &s2) const +{ + return lastIndexOf(s2, len - s2.len); +} + +int String::lastIndexOf(const String &s2, unsigned int fromIndex) const +{ + if(s2.len == 0 || len == 0 || s2.len > len) { + return -1; + } + if(fromIndex >= len) { + fromIndex = len - 1; + } + int found = -1; + for(char *p = buffer; p <= buffer + fromIndex; p++) { + p = strstr(p, s2.buffer); + if(!p) { + break; + } + if((unsigned int) (p - buffer) <= fromIndex) { + found = p - buffer; + } + } + return found; +} + +String String::substring(unsigned int left, unsigned int right) const +{ + if(left > right) { + unsigned int temp = right; + right = left; + left = temp; + } + String out; + if(left >= len) { + return out; + } + if(right > len) { + right = len; + } + char temp = buffer[right]; // save the replaced character + buffer[right] = '\0'; + out = buffer + left; // pointer arithmetic + buffer[right] = temp; //restore character + return out; +} + +// /*********************************************/ +// /* Modification */ +// /*********************************************/ + +void String::replace(char find, char replace) +{ + if(!buffer) { + return; + } + for(char *p = buffer; *p; p++) { + if(*p == find) { + *p = replace; + } + } +} + +void String::replace(const String& find, const String& replace) +{ + if(len == 0 || find.len == 0) { + return; + } + int diff = replace.len - find.len; + char *readFrom = buffer; + char *foundAt; + if(diff == 0) { + while((foundAt = strstr(readFrom, find.buffer)) != NULL) { + memcpy(foundAt, replace.buffer, replace.len); + readFrom = foundAt + replace.len; + } + } else if(diff < 0) { + char *writeTo = buffer; + while((foundAt = strstr(readFrom, find.buffer)) != NULL) { + unsigned int n = foundAt - readFrom; + memcpy(writeTo, readFrom, n); + writeTo += n; + memcpy(writeTo, replace.buffer, replace.len); + writeTo += replace.len; + readFrom = foundAt + find.len; + len += diff; + } + strcpy(writeTo, readFrom); + } else { + unsigned int size = len; // compute size needed for result + while((foundAt = strstr(readFrom, find.buffer)) != NULL) { + readFrom = foundAt + find.len; + size += diff; + } + if(size == len) { + return; + } + if(size > capacity && !changeBuffer(size)) { + return; // XXX: tell user! + } + int index = len - 1; + while(index >= 0 && (index = lastIndexOf(find, index)) >= 0) { + readFrom = buffer + index + find.len; + memmove(readFrom + diff, readFrom, len - (readFrom - buffer)); + len += diff; + buffer[len] = 0; + memcpy(buffer + index, replace.buffer, replace.len); + index--; + } + } +} + +void String::remove(unsigned int index) +{ + // Pass the biggest integer as the count. The remove method + // below will take care of truncating it at the end of the + // string. + remove(index, (unsigned int) -1); +} + +void String::remove(unsigned int index, unsigned int count) +{ + if(index >= len) { + return; + } + if(count <= 0) { + return; + } + if(count > len - index) { + count = len - index; + } + char *writeTo = buffer + index; + len = len - count; + strncpy(writeTo, buffer + index + count, len - index); + buffer[len] = 0; +} + +void String::toLowerCase(void) +{ + if(!buffer) { + return; + } + for(char *p = buffer; *p; p++) { + *p = tolower(*p); + } +} + +void String::toUpperCase(void) +{ + if(!buffer) { + return; + } + for(char *p = buffer; *p; p++) { + *p = toupper(*p); + } +} + +void String::trim(void) +{ + if(!buffer || len == 0) { + return; + } + char *begin = buffer; + while(isspace(*begin)) { + begin++; + } + char *end = buffer + len - 1; + while(isspace(*end) && end >= begin) { + end--; + } + len = end + 1 - begin; + if(begin > buffer) { + memcpy(buffer, begin, len); + } + buffer[len] = 0; +} + +// /*********************************************/ +// /* Parsing / Conversion */ +// /*********************************************/ + +long String::toInt(void) const +{ + if(buffer) { + return atol(buffer); + } + return 0; +} + +float String::toFloat(void) const +{ + if(buffer) { + return atof(buffer); + } + return 0; +} + +double String::toDouble(void) const { + if (buffer) { + return atof(buffer); + } + return 0; +} + +unsigned char String::equalsConstantTime(const String &s2) const { + // To avoid possible time-based attacks present function + // compares given strings in a constant time. + if(len != s2.len) + return 0; + //at this point lengths are the same + if(len == 0) + return 1; + //at this point lenghts are the same and non-zero + const char *p1 = buffer; + const char *p2 = s2.buffer; + unsigned int equalchars = 0; + unsigned int diffchars = 0; + while(*p1) { + if(*p1 == *p2) + ++equalchars; + else + ++diffchars; + ++p1; + ++p2; + } + //the following should force a constant time eval of the condition without a compiler "logical shortcut" + unsigned char equalcond = (equalchars == len); + unsigned char diffcond = (diffchars == 0); + return (equalcond & diffcond); //bitwise AND +} diff --git a/cores/asr650x/cores/WString.h b/cores/asr650x/cores/WString.h new file mode 100644 index 00000000..c83184f5 --- /dev/null +++ b/cores/asr650x/cores/WString.h @@ -0,0 +1,329 @@ +/* + WString.h - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All right reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef String_class_h +#define String_class_h +#ifdef __cplusplus + +#include +#include +#include +#include + +// An inherited class for holding the result of a concatenation. These +// result objects are assumed to be writable by subsequent concatenations. +class StringSumHelper; + +// an abstract class used as a means to proide a unique pointer type +// but really has no body +class __FlashStringHelper; +#define F(string_literal) (reinterpret_cast(PSTR(string_literal))) + +// The string class +class String +{ + // use a function pointer to allow for "if (s)" without the + // complications of an operator bool(). for more information, see: + // http://www.artima.com/cppsource/safebool.html + typedef void (String::*StringIfHelperType)() const; + void StringIfHelper() const + { + } + +public: + // constructors + // creates a copy of the initial value. + // if the initial value is null or invalid, or if memory allocation + // fails, the string will be marked as invalid (i.e. "if (s)" will + // be false). + String(const char *cstr = ""); + String(const String &str); + String(const __FlashStringHelper *str) : String(reinterpret_cast(str)) {}; +#ifdef __GXX_EXPERIMENTAL_CXX0X__ + String(String &&rval); + String(StringSumHelper &&rval); +#endif + explicit String(char c); + explicit String(unsigned char, unsigned char base = 10); + explicit String(int, unsigned char base = 10); + explicit String(unsigned int, unsigned char base = 10); + explicit String(long, unsigned char base = 10); + explicit String(unsigned long, unsigned char base = 10); + explicit String(float, unsigned char decimalPlaces = 2); + explicit String(double, unsigned char decimalPlaces = 2); + ~String(void); + + // memory management + // return true on success, false on failure (in which case, the string + // is left unchanged). reserve(0), if successful, will validate an + // invalid string (i.e., "if (s)" will be true afterwards) + unsigned char reserve(unsigned int size); + inline unsigned int length(void) const + { + if(buffer) { + return len; + } else { + return 0; + } + } + + // creates a copy of the assigned value. if the value is null or + // invalid, or if the memory allocation fails, the string will be + // marked as invalid ("if (s)" will be false). + String & operator =(const String &rhs); + String & operator =(const char *cstr); + String & operator = (const __FlashStringHelper *str); +#ifdef __GXX_EXPERIMENTAL_CXX0X__ + String & operator =(String &&rval); + String & operator =(StringSumHelper &&rval); +#endif + + // concatenate (works w/ built-in types) + + // returns true on success, false on failure (in which case, the string + // is left unchanged). if the argument is null or invalid, the + // concatenation is considered unsucessful. + unsigned char concat(const String &str); + unsigned char concat(const char *cstr); + unsigned char concat(char c); + unsigned char concat(unsigned char c); + unsigned char concat(int num); + unsigned char concat(unsigned int num); + unsigned char concat(long num); + unsigned char concat(unsigned long num); + unsigned char concat(float num); + unsigned char concat(double num); + unsigned char concat(const __FlashStringHelper * str); + + // if there's not enough memory for the concatenated value, the string + // will be left unchanged (but this isn't signalled in any way) + String & operator +=(const String &rhs) + { + concat(rhs); + return (*this); + } + String & operator +=(const char *cstr) + { + concat(cstr); + return (*this); + } + String & operator +=(char c) + { + concat(c); + return (*this); + } + String & operator +=(unsigned char num) + { + concat(num); + return (*this); + } + String & operator +=(int num) + { + concat(num); + return (*this); + } + String & operator +=(unsigned int num) + { + concat(num); + return (*this); + } + String & operator +=(long num) + { + concat(num); + return (*this); + } + String & operator +=(unsigned long num) + { + concat(num); + return (*this); + } + String & operator +=(float num) + { + concat(num); + return (*this); + } + String & operator +=(double num) + { + concat(num); + return (*this); + } + String & operator += (const __FlashStringHelper *str) + { + concat(str); + return (*this); + } + + friend StringSumHelper & operator +(const StringSumHelper &lhs, const String &rhs); + friend StringSumHelper & operator +(const StringSumHelper &lhs, const char *cstr); + friend StringSumHelper & operator +(const StringSumHelper &lhs, char c); + friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned char num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, int num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned int num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, long num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned long num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, float num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, double num); + friend StringSumHelper & operator +(const StringSumHelper &lhs, const __FlashStringHelper *rhs); + + // comparison (only works w/ Strings and "strings") + operator StringIfHelperType() const + { + return buffer ? &String::StringIfHelper : 0; + } + int compareTo(const String &s) const; + unsigned char equals(const String &s) const; + unsigned char equals(const char *cstr) const; + unsigned char operator ==(const String &rhs) const + { + return equals(rhs); + } + unsigned char operator ==(const char *cstr) const + { + return equals(cstr); + } + unsigned char operator !=(const String &rhs) const + { + return !equals(rhs); + } + unsigned char operator !=(const char *cstr) const + { + return !equals(cstr); + } + unsigned char operator <(const String &rhs) const; + unsigned char operator >(const String &rhs) const; + unsigned char operator <=(const String &rhs) const; + unsigned char operator >=(const String &rhs) const; + unsigned char equalsIgnoreCase(const String &s) const; + unsigned char equalsConstantTime(const String &s) const; + unsigned char startsWith(const String &prefix) const; + unsigned char startsWith(const String &prefix, unsigned int offset) const; + unsigned char endsWith(const String &suffix) const; + + // character acccess + char charAt(unsigned int index) const; + void setCharAt(unsigned int index, char c); + char operator [](unsigned int index) const; + char& operator [](unsigned int index); + void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index = 0) const; + void toCharArray(char *buf, unsigned int bufsize, unsigned int index = 0) const + { + getBytes((unsigned char *) buf, bufsize, index); + } + const char * c_str() const + { + return buffer; + } + + // search + int indexOf(char ch) const; + int indexOf(char ch, unsigned int fromIndex) const; + int indexOf(const String &str) const; + int indexOf(const String &str, unsigned int fromIndex) const; + int lastIndexOf(char ch) const; + int lastIndexOf(char ch, unsigned int fromIndex) const; + int lastIndexOf(const String &str) const; + int lastIndexOf(const String &str, unsigned int fromIndex) const; + String substring(unsigned int beginIndex) const + { + return substring(beginIndex, len); + } + ; + String substring(unsigned int beginIndex, unsigned int endIndex) const; + + // modification + void replace(char find, char replace); + void replace(const String& find, const String& replace); + void remove(unsigned int index); + void remove(unsigned int index, unsigned int count); + void toLowerCase(void); + void toUpperCase(void); + void trim(void); + + // parsing/conversion + long toInt(void) const; + float toFloat(void) const; + double toDouble(void) const; + +protected: + char *buffer; // the actual char array + unsigned int capacity; // the array length minus one (for the '\0') + unsigned int len; // the String length (not counting the '\0') +protected: + void init(void); + void invalidate(void); + unsigned char changeBuffer(unsigned int maxStrLen); + unsigned char concat(const char *cstr, unsigned int length); + + // copy and move + String & copy(const char *cstr, unsigned int length); + String & copy(const __FlashStringHelper *pstr, unsigned int length); +#ifdef __GXX_EXPERIMENTAL_CXX0X__ + void move(String &rhs); +#endif +}; + +class StringSumHelper: public String +{ +public: + StringSumHelper(const String &s) : + String(s) + { + } + StringSumHelper(const char *p) : + String(p) + { + } + StringSumHelper(char c) : + String(c) + { + } + StringSumHelper(unsigned char num) : + String(num) + { + } + StringSumHelper(int num) : + String(num) + { + } + StringSumHelper(unsigned int num) : + String(num) + { + } + StringSumHelper(long num) : + String(num) + { + } + StringSumHelper(unsigned long num) : + String(num) + { + } + StringSumHelper(float num) : + String(num) + { + } + StringSumHelper(double num) : + String(num) + { + } +}; + +#endif // __cplusplus +#endif // String_class_h diff --git a/cores/asr650x/cores/irq.c b/cores/asr650x/cores/irq.c new file mode 100644 index 00000000..7a025de6 --- /dev/null +++ b/cores/asr650x/cores/irq.c @@ -0,0 +1,406 @@ +/******************************************************************************* +* File Name: global_irq.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include +#include "cyapicallbacks.h" + +#if !defined(global_irq__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START global_irq_intc` */ + +/* `#END` */ + +extern cyisraddress CyRamVectors[CYINT_IRQ_BASE + CY_NUM_INTERRUPTS]; + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: global_irq_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void global_irq_Start(void) +{ + /* For all we know the interrupt is active. */ + global_irq_Disable(); + + /* Set the ISR to point to the global_irq Interrupt. */ + global_irq_SetVector(&global_irq_Interrupt); + + /* Set the priority. */ + global_irq_SetPriority((uint8)global_irq_INTC_PRIOR_NUMBER); + + /* Enable it. */ + global_irq_Enable(); +} + + +/******************************************************************************* +* Function Name: global_irq_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void global_irq_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + global_irq_Disable(); + + /* Set the ISR to point to the global_irq Interrupt. */ + global_irq_SetVector(address); + + /* Set the priority. */ + global_irq_SetPriority((uint8)global_irq_INTC_PRIOR_NUMBER); + + /* Enable it. */ + global_irq_Enable(); +} + + +/******************************************************************************* +* Function Name: global_irq_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void global_irq_Stop(void) +{ + /* Disable this interrupt. */ + global_irq_Disable(); + + /* Set the ISR to point to the passive one. */ + global_irq_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: global_irq_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for global_irq. +* +* Add custom code between the START and END comments to keep the next version +* of this file from over-writing your code. +* +* Note You may use either the default ISR by using this API, or you may define +* your own separate ISR through ISR_StartEx(). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(global_irq_Interrupt) +{ + #ifdef global_irq_INTERRUPT_INTERRUPT_CALLBACK + global_irq_Interrupt_InterruptCallback(); + #endif /* global_irq_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START global_irq_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: global_irq_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling global_irq_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use global_irq_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void global_irq_SetVector(cyisraddress address) +{ + CyRamVectors[CYINT_IRQ_BASE + global_irq__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: global_irq_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress global_irq_GetVector(void) +{ + return CyRamVectors[CYINT_IRQ_BASE + global_irq__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: global_irq_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling global_irq_Start or global_irq_StartEx will +* override any effect this API would have had. This API should only be called +* after global_irq_Start or global_irq_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void global_irq_SetPriority(uint8 priority) +{ + uint8 interruptState; + uint32 priorityOffset = ((global_irq__INTC_NUMBER % 4u) * 8u) + 6u; + + interruptState = CyEnterCriticalSection(); + *global_irq_INTC_PRIOR = (*global_irq_INTC_PRIOR & (uint32)(~global_irq__INTC_PRIOR_MASK)) | + ((uint32)priority << priorityOffset); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: global_irq_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 global_irq_GetPriority(void) +{ + uint32 priority; + uint32 priorityOffset = ((global_irq__INTC_NUMBER % 4u) * 8u) + 6u; + + priority = (*global_irq_INTC_PRIOR & global_irq__INTC_PRIOR_MASK) >> priorityOffset; + + return (uint8)priority; +} + + +/******************************************************************************* +* Function Name: global_irq_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void global_irq_Enable(void) +{ + /* Enable the general interrupt. */ + *global_irq_INTC_SET_EN = global_irq__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: global_irq_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 global_irq_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*global_irq_INTC_SET_EN & (uint32)global_irq__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: global_irq_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void global_irq_Disable(void) +{ + /* Disable the general interrupt. */ + *global_irq_INTC_CLR_EN = global_irq__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: global_irq_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void global_irq_SetPending(void) +{ + *global_irq_INTC_SET_PD = global_irq__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: global_irq_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void global_irq_ClearPending(void) +{ + *global_irq_INTC_CLR_PD = global_irq__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/irq.h b/cores/asr650x/cores/irq.h new file mode 100644 index 00000000..eb5a8d12 --- /dev/null +++ b/cores/asr650x/cores/irq.h @@ -0,0 +1,95 @@ +/******************************************************************************* +* File Name: global_irq.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + + +#if !defined(global_irq_H) +#define global_irq_H + + +#include +#include + +/* Interrupt Controller API. */ +void global_irq_Start(void); +void global_irq_StartEx(cyisraddress address); +void global_irq_Stop(void); + +CY_ISR_PROTO(global_irq_Interrupt); + +void global_irq_SetVector(cyisraddress address); +cyisraddress global_irq_GetVector(void); + +void global_irq_SetPriority(uint8 priority); +uint8 global_irq_GetPriority(void); + +void global_irq_Enable(void); +uint8 global_irq_GetState(void); +void global_irq_Disable(void); + +void global_irq_SetPending(void); +void global_irq_ClearPending(void); + +/* global_irq */ +#define global_irq__INTC_CLR_EN_REG CYREG_CM0P_ICER +#define global_irq__INTC_CLR_PD_REG CYREG_CM0P_ICPR +#define global_irq__INTC_MASK 0x10u +#define global_irq__INTC_NUMBER 4u +#define global_irq__INTC_PRIOR_MASK 0xC0u +#define global_irq__INTC_PRIOR_NUM 2u +#define global_irq__INTC_PRIOR_REG CYREG_CM0P_IPR1 +#define global_irq__INTC_SET_EN_REG CYREG_CM0P_ISER +#define global_irq__INTC_SET_PD_REG CYREG_CM0P_ISPR + + +/* Interrupt Controller Constants */ + + + + +/* Address of the INTC.VECT[x] register that contains the Address of the global_irq ISR. */ +#define global_irq_INTC_VECTOR ((reg32 *) global_irq__INTC_VECT) + +/* Address of the global_irq ISR priority. */ +#define global_irq_INTC_PRIOR ((reg32 *) global_irq__INTC_PRIOR_REG) + +/* Priority of the global_irq interrupt. */ +#define global_irq_INTC_PRIOR_NUMBER global_irq__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable global_irq interrupt. */ +#define global_irq_INTC_SET_EN ((reg32 *) global_irq__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the global_irq interrupt. */ +#define global_irq_INTC_CLR_EN ((reg32 *) global_irq__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the global_irq interrupt state to pending. */ +#define global_irq_INTC_SET_PD ((reg32 *) global_irq__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the global_irq interrupt. */ +#define global_irq_INTC_CLR_PD ((reg32 *) global_irq__INTC_CLR_PD_REG) + + + +#endif /* CY_ISR_global_irq_H */ + + +#ifdef __cplusplus +} +#endif + + +/* [] END OF FILE */ diff --git a/cores/asr650x/cores/pgmspace.h b/cores/asr650x/cores/pgmspace.h new file mode 100644 index 00000000..c2bee48c --- /dev/null +++ b/cores/asr650x/cores/pgmspace.h @@ -0,0 +1,88 @@ +/* + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the RaspberryPi core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +#ifndef PGMSPACE_INCLUDE +#define PGMSPACE_INCLUDE + +typedef void prog_void; +typedef char prog_char; +typedef unsigned char prog_uchar; +typedef char prog_int8_t; +typedef unsigned char prog_uint8_t; +typedef short prog_int16_t; +typedef unsigned short prog_uint16_t; +typedef long prog_int32_t; +typedef unsigned long prog_uint32_t; + +#define PROGMEM +#define PGM_P const char * +#define PGM_VOID_P const void * +#define FPSTR(p) ((const char *)(p)) +#define PSTR(s) (s) +#define _SFR_BYTE(n) (n) + +#define pgm_read_byte(addr) (*(const unsigned char *)(addr)) +#define pgm_read_word(addr) ({ \ + typeof(addr) _addr = (addr); \ + *(const unsigned short *)(_addr); \ +}) +#define pgm_read_dword(addr) ({ \ + typeof(addr) _addr = (addr); \ + *(const unsigned long *)(_addr); \ +}) +#define pgm_read_float(addr) ({ \ + typeof(addr) _addr = (addr); \ + *(const float *)(_addr); \ +}) +#define pgm_read_ptr(addr) ({ \ + typeof(addr) _addr = (addr); \ + *(void * const *)(_addr); \ +}) + +#define pgm_read_byte_near(addr) pgm_read_byte(addr) +#define pgm_read_word_near(addr) pgm_read_word(addr) +#define pgm_read_dword_near(addr) pgm_read_dword(addr) +#define pgm_read_float_near(addr) pgm_read_float(addr) +#define pgm_read_ptr_near(addr) pgm_read_ptr(addr) +#define pgm_read_byte_far(addr) pgm_read_byte(addr) +#define pgm_read_word_far(addr) pgm_read_word(addr) +#define pgm_read_dword_far(addr) pgm_read_dword(addr) +#define pgm_read_float_far(addr) pgm_read_float(addr) +#define pgm_read_ptr_far(addr) pgm_read_ptr(addr) + +#define memcmp_P memcmp +#define memccpy_P memccpy +#define memmem_P memmem +#define memcpy_P memcpy +#define strcpy_P strcpy +#define strncpy_P strncpy +#define strcat_P strcat +#define strncat_P strncat +#define strcmp_P strcmp +#define strncmp_P strncmp +#define strcasecmp_P strcasecmp +#define strncasecmp_P strncasecmp +#define strlen_P strlen +#define strnlen_P strnlen +#define strstr_P strstr +#define printf_P printf +#define sprintf_P sprintf +#define snprintf_P snprintf +#define vsnprintf_P vsnprintf + +#endif diff --git a/cores/asr650x/cores/stdlib_noniso.c b/cores/asr650x/cores/stdlib_noniso.c new file mode 100644 index 00000000..e7920489 --- /dev/null +++ b/cores/asr650x/cores/stdlib_noniso.c @@ -0,0 +1,161 @@ +/* + core_esp8266_noniso.c - nonstandard (but usefull) conversion functions + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 03 April 2015 by Markus Sattler + + */ + +#include +#include +#include +#include +#include +#include "stdlib_noniso.h" + +void reverse(char* begin, char* end) { + char *is = begin; + char *ie = end - 1; + while(is < ie) { + char tmp = *ie; + *ie = *is; + *is = tmp; + ++is; + --ie; + } +} + +char* ltoa(long value, char* result, int base) { + if(base < 2 || base > 16) { + *result = 0; + return result; + } + + char* out = result; + long quotient = abs(value); + + do { + const long tmp = quotient / base; + *out = "0123456789abcdef"[quotient - (tmp * base)]; + ++out; + quotient = tmp; + } while(quotient); + + // Apply negative sign + if(value < 0) + *out++ = '-'; + + reverse(result, out); + *out = 0; + return result; +} + +char* ultoa(unsigned long value, char* result, int base) { + if(base < 2 || base > 16) { + *result = 0; + return result; + } + + char* out = result; + unsigned long quotient = value; + + do { + const unsigned long tmp = quotient / base; + *out = "0123456789abcdef"[quotient - (tmp * base)]; + ++out; + quotient = tmp; + } while(quotient); + + reverse(result, out); + *out = 0; + return result; +} + +char * dtostrf(double number, signed char width, unsigned char prec, char *s) { + bool negative = false; + + if (isnan(number)) { + strcpy(s, "nan"); + return s; + } + if (isinf(number)) { + strcpy(s, "inf"); + return s; + } + + char* out = s; + + int fillme = width; // how many cells to fill for the integer part + if (prec > 0) { + fillme -= (prec+1); + } + + // Handle negative numbers + if (number < 0.0) { + negative = true; + fillme--; + number = -number; + } + + // Round correctly so that print(1.999, 2) prints as "2.00" + // I optimized out most of the divisions + double rounding = 2.0; + for (uint8_t i = 0; i < prec; ++i) + rounding *= 10.0; + rounding = 1.0 / rounding; + + number += rounding; + + // Figure out how big our number really is + double tenpow = 1.0; + int digitcount = 1; + while (number >= 10.0 * tenpow) { + tenpow *= 10.0; + digitcount++; + } + + number /= tenpow; + fillme -= digitcount; + + // Pad unused cells with spaces + while (fillme-- > 0) { + *out++ = ' '; + } + + // Handle negative sign + if (negative) *out++ = '-'; + + // Print the digits, and if necessary, the decimal point + digitcount += prec; + int8_t digit = 0; + while (digitcount-- > 0) { + digit = (int8_t)number; + if (digit > 9) digit = 9; // insurance + *out++ = (char)('0' | digit); + if ((digitcount == prec) && (prec > 0)) { + *out++ = '.'; + } + number -= digit; + number *= 10.0; + } + + // make sure the string is terminated + *out = 0; + return s; +} diff --git a/cores/asr650x/cores/stdlib_noniso.h b/cores/asr650x/cores/stdlib_noniso.h new file mode 100644 index 00000000..3df2cc2a --- /dev/null +++ b/cores/asr650x/cores/stdlib_noniso.h @@ -0,0 +1,49 @@ +/* + stdlib_noniso.h - nonstandard (but usefull) conversion functions + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef STDLIB_NONISO_H +#define STDLIB_NONISO_H + +#ifdef __cplusplus +extern "C" { +#endif + +int atoi(const char *s); + +long atol(const char* s); + +double atof(const char* s); + +char* itoa (int val, char *s, int radix); + +char* ltoa (long val, char *s, int radix); + +char* utoa (unsigned int val, char *s, int radix); + +char* ultoa (unsigned long val, char *s, int radix); + +char* dtostrf (double val, signed char width, unsigned char prec, char *s); + +#ifdef __cplusplus +} // extern "C" +#endif + + +#endif diff --git a/cores/asr650x/device/asr6501_lrwan/radio.c b/cores/asr650x/device/asr6501_lrwan/radio.c new file mode 100644 index 00000000..d136dde0 --- /dev/null +++ b/cores/asr650x/device/asr6501_lrwan/radio.c @@ -0,0 +1,1231 @@ +#include +#include +#include "timer.h" +#include "delay.h" +#include "radio.h" +#include "sx126x.h" +#include "sx126x-board.h" +#include "board.h" +#include "utilities.h" + +/*! + * \brief Initializes the radio + * + * \param [IN] events Structure containing the driver callback functions + */ +int RadioInit( RadioEvents_t *events ); + +/*! + * Return current radio status + * + * \param status Radio status.[RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING] + */ +RadioState_t RadioGetStatus( void ); + +/*! + * \brief Configures the radio with the given modem + * + * \param [IN] modem Modem to be used [0: FSK, 1: LoRa] + */ +void RadioSetModem( RadioModems_t modem ); + +/*! + * \brief Sets the channel frequency + * + * \param [IN] freq Channel RF frequency + */ +void RadioSetChannel( uint32_t freq ); + +/*! + * \brief Checks if the channel is free for the given time + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] freq Channel RF frequency + * \param [IN] rssiThresh RSSI threshold + * \param [IN] maxCarrierSenseTime Max time while the RSSI is measured + * + * \retval isFree [true: Channel is free, false: Channel is not free] + */ +bool RadioIsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime ); + +/*! + * \brief Generates a 32 bits random value based on the RSSI readings + * + * \remark This function sets the radio in LoRa modem mode and disables + * all interrupts. + * After calling this function either Radio.SetRxConfig or + * Radio.SetTxConfig functions must be called. + * + * \retval randomValue 32 bits random value + */ +uint32_t RadioRandom( void ); + +/*! + * \brief Sets the reception parameters + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] bandwidth Sets the bandwidth + * FSK : >= 2600 and <= 250000 Hz + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [IN] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [IN] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [IN] bandwidthAfc Sets the AFC Bandwidth (FSK only) + * FSK : >= 2600 and <= 250000 Hz + * LoRa: N/A ( set to 0 ) + * \param [IN] preambleLen Sets the Preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [IN] symbTimeout Sets the RxSingle timeout value + * FSK : timeout in number of bytes + * LoRa: timeout in symbols + * \param [IN] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [IN] payloadLen Sets payload length when fixed length is used + * \param [IN] crcOn Enables/Disables the CRC [0: OFF, 1: ON] + * \param [IN] FreqHopOn Enables disables the intra-packet frequency hopping + * FSK : N/A ( set to 0 ) + * LoRa: [0: OFF, 1: ON] + * \param [IN] HopPeriod Number of symbols between each hop + * FSK : N/A ( set to 0 ) + * LoRa: Number of symbols + * \param [IN] iqInverted Inverts IQ signals (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [0: not inverted, 1: inverted] + * \param [IN] rxContinuous Sets the reception in continuous mode + * [false: single mode, true: continuous mode] + */ +void RadioSetRxConfig( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint32_t bandwidthAfc, uint16_t preambleLen, + uint16_t symbTimeout, bool fixLen, + uint8_t payloadLen, + bool crcOn, bool FreqHopOn, uint8_t HopPeriod, + bool iqInverted, bool rxContinuous ); + +/*! + * \brief Sets the transmission parameters + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] power Sets the output power [dBm] + * \param [IN] fdev Sets the frequency deviation (FSK only) + * FSK : [Hz] + * LoRa: 0 + * \param [IN] bandwidth Sets the bandwidth (LoRa only) + * FSK : 0 + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [IN] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [IN] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [IN] preambleLen Sets the preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [IN] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [IN] crcOn Enables disables the CRC [0: OFF, 1: ON] + * \param [IN] FreqHopOn Enables disables the intra-packet frequency hopping + * FSK : N/A ( set to 0 ) + * LoRa: [0: OFF, 1: ON] + * \param [IN] HopPeriod Number of symbols between each hop + * FSK : N/A ( set to 0 ) + * LoRa: Number of symbols + * \param [IN] iqInverted Inverts IQ signals (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [0: not inverted, 1: inverted] + * \param [IN] timeout Transmission timeout [ms] + */ +void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, + uint32_t bandwidth, uint32_t datarate, + uint8_t coderate, uint16_t preambleLen, + bool fixLen, bool crcOn, bool FreqHopOn, + uint8_t HopPeriod, bool iqInverted, uint32_t timeout ); + +/*! + * \brief Checks if the given RF frequency is supported by the hardware + * + * \param [IN] frequency RF frequency to be checked + * \retval isSupported [true: supported, false: unsupported] + */ +bool RadioCheckRfFrequency( uint32_t frequency ); + +/*! + * \brief Computes the packet time on air in ms for the given payload + * + * \Remark Can only be called once SetRxConfig or SetTxConfig have been called + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] pktLen Packet payload length + * + * \retval airTime Computed airTime (ms) for the given packet payload length + */ +uint32_t RadioTimeOnAir( RadioModems_t modem, uint8_t pktLen ); + +double RadioSymbTime(uint8_t bw, uint8_t sf); + +/*! + * \brief Sends the buffer of size. Prepares the packet to be sent and sets + * the radio in transmission + * + * \param [IN]: buffer Buffer pointer + * \param [IN]: size Buffer size + */ +void RadioSend( uint8_t *buffer, uint8_t size ); + +/*! + * \brief Sets the radio in sleep mode + */ +void RadioSleep( void ); + +/*! + * \brief Sets the radio in standby mode + */ +void RadioStandby( void ); + +/*! + * \brief Sets the radio in reception mode for the given time + * \param [IN] timeout Reception timeout [ms] + * [0: continuous, others timeout] + */ +void RadioRx( uint32_t timeout ); + +/*! + * \brief Start a Channel Activity Detection + */ +void RadioStartCad( uint8_t symbols ); + +/*! + * \brief Sets the radio in continuous wave transmission mode + * + * \param [IN]: freq Channel RF frequency + * \param [IN]: power Sets the output power [dBm] + * \param [IN]: time Transmission mode timeout [s] + */ +void RadioSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ); + +/*! + * \brief Reads the current RSSI value + * + * \retval rssiValue Current RSSI value in [dBm] + */ +int16_t RadioRssi( RadioModems_t modem ); + +/*! + * \brief Writes the radio register at the specified address + * + * \param [IN]: addr Register address + * \param [IN]: data New register value + */ +void RadioWrite( uint16_t addr, uint8_t data ); + +/*! + * \brief Reads the radio register at the specified address + * + * \param [IN]: addr Register address + * \retval data Register value + */ +uint8_t RadioRead( uint16_t addr ); + +/*! + * \brief Writes multiple radio registers starting at address + * + * \param [IN] addr First Radio register address + * \param [IN] buffer Buffer containing the new register's values + * \param [IN] size Number of registers to be written + */ +void RadioWriteBuffer( uint16_t addr, uint8_t *buffer, uint8_t size ); + +/*! + * \brief Reads multiple radio registers starting at address + * + * \param [IN] addr First Radio register address + * \param [OUT] buffer Buffer where to copy the registers data + * \param [IN] size Number of registers to be read + */ +void RadioReadBuffer( uint16_t addr, uint8_t *buffer, uint8_t size ); + +/*! + * \brief Sets the maximum payload length. + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] max Maximum payload length in bytes + */ +void RadioSetMaxPayloadLength( RadioModems_t modem, uint8_t max ); + +/*! + * \brief Sets the network to public or private. Updates the sync byte. + * + * \remark Applies to LoRa modem only + * + * \param [IN] enable if true, it enables a public network + */ +void RadioSetPublicNetwork( bool enable ); + +/*! + * \brief Gets the time required for the board plus radio to get out of sleep.[ms] + * + * \retval time Radio plus board wakeup time in ms. + */ +uint32_t RadioGetWakeupTime( void ); + +/*! + * \brief Process radio irq + */ +void RadioIrqProcess( void ); + +/*! + * \brief Sets the radio in reception mode with Max LNA gain for the given time + * \param [IN] timeout Reception timeout [ms] + * [0: continuous, others timeout] + */ +void RadioRxBoosted( uint32_t timeout ); + +/*! + * \brief Sets the Rx duty cycle management parameters + * + * \param [in] rxTime Structure describing reception timeout value + * \param [in] sleepTime Structure describing sleep timeout value + */ +void RadioSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ); +/*! + * \brief Set synchro word in radio + * + * \param [IN] data THe syncword + */ +void RadioSyncWord( uint8_t data ); +/*! + * Radio driver structure initialization + */ +const struct Radio_s Radio = +{ + RadioInit, + RadioGetStatus, + RadioSetModem, + RadioSetChannel, + RadioIsChannelFree, + RadioRandom, + RadioSetRxConfig, + RadioSetTxConfig, + RadioCheckRfFrequency, + RadioTimeOnAir, + RadioSend, + RadioSleep, + RadioStandby, + RadioRx, + RadioStartCad, + RadioSetTxContinuousWave, + RadioRssi, + RadioWrite, + RadioRead, + RadioWriteBuffer, + RadioReadBuffer, + RadioSyncWord, + RadioSetMaxPayloadLength, + RadioSetPublicNetwork, + RadioGetWakeupTime, + RadioIrqProcess, + // Available on SX126x only + RadioRxBoosted, + RadioSetRxDutyCycle +}; + +/* + * Local types definition + */ + + + /*! + * FSK bandwidth definition + */ +typedef struct +{ + uint32_t bandwidth; + uint8_t RegValue; +}FskBandwidth_t; + +/*! + * Precomputed FSK bandwidth registers values + */ +const FskBandwidth_t FskBandwidths[] = +{ + { 4800 , 0x1F }, + { 5800 , 0x17 }, + { 7300 , 0x0F }, + { 9700 , 0x1E }, + { 11700 , 0x16 }, + { 14600 , 0x0E }, + { 19500 , 0x1D }, + { 23400 , 0x15 }, + { 29300 , 0x0D }, + { 39000 , 0x1C }, + { 46900 , 0x14 }, + { 58600 , 0x0C }, + { 78200 , 0x1B }, + { 93800 , 0x13 }, + { 117300, 0x0B }, + { 156200, 0x1A }, + { 187200, 0x12 }, + { 234300, 0x0A }, + { 312000, 0x19 }, + { 373600, 0x11 }, + { 467000, 0x09 }, + { 500000, 0x00 }, // Invalid Bandwidth +}; + +const RadioLoRaBandwidths_t Bandwidths[] = { LORA_BW_125, LORA_BW_250, LORA_BW_500, LORA_BW_062,LORA_BW_041, LORA_BW_031, LORA_BW_020, LORA_BW_015, LORA_BW_010, LORA_BW_007 }; + +#if 0 +// SF12 SF11 SF10 SF9 SF8 SF7 +static double RadioLoRaSymbTime[3][6] = {{ 32.768, 16.384, 8.192, 4.096, 2.048, 1.024 }, // 125 KHz + { 16.384, 8.192, 4.096, 2.048, 1.024, 0.512 }, // 250 KHz + { 8.192, 4.096, 2.048, 1.024, 0.512, 0.256 }}; // 500 KHz +#endif + +uint8_t MaxPayloadLength = 0xFF; + +uint32_t TxTimeout = 0; +uint32_t RxTimeout = 0; + +bool RxContinuous = false; + + +PacketStatus_t RadioPktStatus; +uint8_t RadioRxPayload[255]; + +bool IrqFired = false; + +/* + * SX126x DIO IRQ callback functions prototype + */ + +/*! + * \brief DIO 0 IRQ callback + */ +void RadioOnDioIrq( void ); + +/*! + * \brief Tx timeout timer callback + */ +void RadioOnTxTimeoutIrq( void ); + +/*! + * \brief Rx timeout timer callback + */ +void RadioOnRxTimeoutIrq( void ); + +/*! + * \brief Cad timeout timer callback + */ +void RadioOnCadTimeoutIrq( void ); +/* + * Private global variables + */ + + +/*! + * Holds the current network type for the radio + */ +typedef struct +{ + bool Previous; + bool Current; +}RadioPublicNetwork_t; + +static RadioPublicNetwork_t RadioPublicNetwork = { false }; + +/*! + * Radio callbacks variable + */ +static RadioEvents_t* RadioEvents; + +/* + * Public global variables + */ + +/*! + * Radio hardware and global parameters + */ +SX126x_t SX126x; + +/*! + * Tx and Rx timers + */ +TimerEvent_t TxTimeoutTimer; +TimerEvent_t RxTimeoutTimer; +TimerEvent_t CadTimeoutTimer; + +/*! + * Returns the known FSK bandwidth registers value + * + * \param [IN] bandwidth Bandwidth value in Hz + * \retval regValue Bandwidth register value. + */ +static uint8_t RadioGetFskBandwidthRegValue( uint32_t bandwidth ) +{ + uint8_t i; + + if( bandwidth == 0 ) + { + return( 0x1F ); + } + + for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ ) + { + if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) ) + { + return FskBandwidths[i+1].RegValue; + } + } + // ERROR: Value not found + while( 1 ); +} + +int RadioInit( RadioEvents_t *events ) +{ + + RadioEvents = events; + + SX126xInit( RadioOnDioIrq ); + SX126xSetStandby( STDBY_RC ); + SX126xSetRegulatorMode( USE_DCDC ); + + SX126xSetBufferBaseAddress( 0x00, 0x00 ); + SX126xSetTxParams( 0, RADIO_RAMP_200_US ); + SX126xSetDioIrqParams( IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + + // Initialize driver timeout timers + TimerInit( &TxTimeoutTimer, RadioOnTxTimeoutIrq ); + TimerInit( &RxTimeoutTimer, RadioOnRxTimeoutIrq ); + TimerInit( &CadTimeoutTimer, RadioOnCadTimeoutIrq ); + + IrqFired = false; + return 0; +} + +RadioState_t RadioGetStatus( void ) +{ + switch( SX126xGetOperatingMode( ) ) + { + case MODE_TX: + return RF_TX_RUNNING; + case MODE_RX: + return RF_RX_RUNNING; + case RF_CAD: + return RF_CAD; + default: + return RF_IDLE; + } +} + +void RadioSetModem( RadioModems_t modem ) +{ + switch( modem ) + { + default: + case MODEM_FSK: + SX126xSetPacketType( PACKET_TYPE_GFSK ); + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + RadioPublicNetwork.Current = false; + break; + case MODEM_LORA: + SX126xSetPacketType( PACKET_TYPE_LORA ); + // Public/Private network register is reset when switching modems + if( RadioPublicNetwork.Current != RadioPublicNetwork.Previous ) + { + RadioPublicNetwork.Current = RadioPublicNetwork.Previous; + RadioSetPublicNetwork( RadioPublicNetwork.Current ); + } + break; + } +} + +void RadioSetChannel( uint32_t freq ) +{ + SX126xSetRfFrequency( freq ); +} + +bool RadioIsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime ) +{ + bool status = true; + int16_t rssi = 0; + uint32_t carrierSenseTime = 0; + + RadioSetModem( modem ); + + RadioSetChannel( freq ); + + RadioRx( 0 ); + + DelayMs( 1 ); + + carrierSenseTime = TimerGetCurrentTime( ); + + // Perform carrier sense for maxCarrierSenseTime + while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime ) + { + rssi = RadioRssi( modem ); + + if( rssi > rssiThresh ) + { + status = false; + break; + } + } + RadioSleep( ); + return status; +} + +uint32_t RadioRandom( void ) +{ + uint8_t i; + uint32_t rnd = 0; + + /* + * Radio setup for random number generation + */ + // Set LoRa modem ON + RadioSetModem( MODEM_LORA ); + + // Set radio in continuous reception + SX126xSetRx( 0 ); + + for( i = 0; i < 32; i++ ) + { + DelayMs( 1 ); + // Unfiltered RSSI value reading. Only takes the LSB value + rnd |= ( ( uint32_t )SX126xGetRssiInst( ) & 0x01 ) << i; + } + rnd += rand1(); + RadioSleep( ); + + return rnd; +} + +void RadioSetRxConfig( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint32_t bandwidthAfc, uint16_t preambleLen, + uint16_t symbTimeout, bool fixLen, + uint8_t payloadLen, + bool crcOn, bool freqHopOn, uint8_t hopPeriod, + bool iqInverted, bool rxContinuous ) +{ + + RxContinuous = rxContinuous; + + if( fixLen == true ) + { + MaxPayloadLength = payloadLen; + } + else + { + MaxPayloadLength = 0xFF; + } + + switch( modem ) + { + case MODEM_FSK: + SX126xSetStopRxTimerOnPreambleDetect( false ); + SX126x.ModulationParams.PacketType = PACKET_TYPE_GFSK; + + SX126x.ModulationParams.Params.Gfsk.BitRate = datarate; + SX126x.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; + SX126x.ModulationParams.Params.Gfsk.Bandwidth = RadioGetFskBandwidthRegValue( bandwidth ); + + SX126x.PacketParams.PacketType = PACKET_TYPE_GFSK; + SX126x.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + SX126x.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; + SX126x.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3; // convert byte into bit + SX126x.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + SX126x.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; + SX126x.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength; + if( crcOn == true ) + { + SX126x.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; + } + else + { + SX126x.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + } + SX126x.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; + + RadioStandby( ); + RadioSetModem( ( SX126x.ModulationParams.PacketType == PACKET_TYPE_GFSK ) ? MODEM_FSK : MODEM_LORA ); + SX126xSetModulationParams( &SX126x.ModulationParams ); + SX126xSetPacketParams( &SX126x.PacketParams ); + SX126xSetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + SX126xSetWhiteningSeed( 0x01FF ); + + RxTimeout = ( uint32_t )( symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1000 ); + break; + + case MODEM_LORA: + SX126xSetStopRxTimerOnPreambleDetect( false ); + SX126xSetLoRaSymbNumTimeout( symbTimeout ); + SX126x.ModulationParams.PacketType = PACKET_TYPE_LORA; + SX126x.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t )datarate; + SX126x.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; + SX126x.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t )coderate; + + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) || (RadioSymbTime(Bandwidths[bandwidth], coderate) >= 16.38) ) + { + SX126x.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; + } + else + { + SX126x.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; + } + + SX126x.PacketParams.PacketType = PACKET_TYPE_LORA; + + if( ( SX126x.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + ( SX126x.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) + { + if( preambleLen < 12 ) + { + SX126x.PacketParams.Params.LoRa.PreambleLength = 12; + } + else + { + SX126x.PacketParams.Params.LoRa.PreambleLength = preambleLen; + } + } + else + { + SX126x.PacketParams.Params.LoRa.PreambleLength = preambleLen; + } + + SX126x.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; + + SX126x.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + SX126x.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; + SX126x.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; + + RadioSetModem( ( SX126x.ModulationParams.PacketType == PACKET_TYPE_GFSK ) ? MODEM_FSK : MODEM_LORA ); + SX126xSetModulationParams( &SX126x.ModulationParams ); + SX126xSetPacketParams( &SX126x.PacketParams ); + + // Timeout Max, Timeout handled directly in SetRx function + RxTimeout = 0xFFFF; + + break; + } +} + +void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, + uint32_t bandwidth, uint32_t datarate, + uint8_t coderate, uint16_t preambleLen, + bool fixLen, bool crcOn, bool freqHopOn, + uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) +{ + + switch( modem ) + { + case MODEM_FSK: + SX126x.ModulationParams.PacketType = PACKET_TYPE_GFSK; + SX126x.ModulationParams.Params.Gfsk.BitRate = datarate; + + SX126x.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; + SX126x.ModulationParams.Params.Gfsk.Bandwidth = RadioGetFskBandwidthRegValue( bandwidth ); + SX126x.ModulationParams.Params.Gfsk.Fdev = fdev; + + SX126x.PacketParams.PacketType = PACKET_TYPE_GFSK; + SX126x.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + SX126x.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; + SX126x.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3 ; // convert byte into bit + SX126x.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + SX126x.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; + + if( crcOn == true ) + { + SX126x.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; + } + else + { + SX126x.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + } + SX126x.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; + + RadioStandby( ); + RadioSetModem( ( SX126x.ModulationParams.PacketType == PACKET_TYPE_GFSK ) ? MODEM_FSK : MODEM_LORA ); + SX126xSetModulationParams( &SX126x.ModulationParams ); + SX126xSetPacketParams( &SX126x.PacketParams ); + SX126xSetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + SX126xSetWhiteningSeed( 0x01FF ); + break; + + case MODEM_LORA: + SX126x.ModulationParams.PacketType = PACKET_TYPE_LORA; + SX126x.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) datarate; + SX126x.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; + SX126x.ModulationParams.Params.LoRa.CodingRate= ( RadioLoRaCodingRates_t )coderate; + + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) || (RadioSymbTime(Bandwidths[bandwidth], coderate) >= 16.38) ) + { + SX126x.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; + } + else + { + SX126x.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; + } + + SX126x.PacketParams.PacketType = PACKET_TYPE_LORA; + + if( ( SX126x.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + ( SX126x.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) + { + if( preambleLen < 12 ) + { + SX126x.PacketParams.Params.LoRa.PreambleLength = 12; + } + else + { + SX126x.PacketParams.Params.LoRa.PreambleLength = preambleLen; + } + } + else + { + SX126x.PacketParams.Params.LoRa.PreambleLength = preambleLen; + } + + SX126x.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; + SX126x.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + SX126x.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; + SX126x.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; + + RadioStandby( ); + RadioSetModem( ( SX126x.ModulationParams.PacketType == PACKET_TYPE_GFSK ) ? MODEM_FSK : MODEM_LORA ); + SX126xSetModulationParams( &SX126x.ModulationParams ); + SX126xSetPacketParams( &SX126x.PacketParams ); + break; + } + SX126xSetRfTxPower( power ); + TxTimeout = timeout; +} + +bool RadioCheckRfFrequency( uint32_t frequency ) +{ + return true; +} + +double RadioSymbTime(uint8_t bw, uint8_t sf) +{ + double bw_khz = 0; + switch(bw) { + case LORA_BW_007: bw_khz = 7.81; break; + case LORA_BW_010: bw_khz = 10.42; break; + case LORA_BW_015: bw_khz = 15.63; break; + case LORA_BW_020: bw_khz = 20.83; break; + case LORA_BW_031: bw_khz = 31.25; break; + case LORA_BW_041: bw_khz = 41.67; break; + case LORA_BW_062: bw_khz = 62.5; break; + case LORA_BW_125: bw_khz = 125; break; + case LORA_BW_250: bw_khz = 250; break; + case LORA_BW_500: bw_khz = 500; break; + default: break; + } + + return (1<> 3 ) + + ( ( SX126x.PacketParams.Params.Gfsk.HeaderType == RADIO_PACKET_FIXED_LENGTH ) ? 0.0 : 1.0 ) + + pktLen + + ( ( SX126x.PacketParams.Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES ) ? 2.0 : 0 ) ) / + SX126x.ModulationParams.Params.Gfsk.BitRate ) * 1e3 ); + } + break; + case MODEM_LORA: + { + //double ts = RadioLoRaSymbTime[SX126x.ModulationParams.Params.LoRa.Bandwidth - 4][12 - SX126x.ModulationParams.Params.LoRa.SpreadingFactor]; + double ts = RadioSymbTime(SX126x.ModulationParams.Params.LoRa.Bandwidth, SX126x.ModulationParams.Params.LoRa.SpreadingFactor); + // time of preamble + double tPreamble = ( SX126x.PacketParams.Params.LoRa.PreambleLength + 4.25 ) * ts; + // Symbol length of payload and time + double tmp = ceil( ( 8 * pktLen - 4 * SX126x.ModulationParams.Params.LoRa.SpreadingFactor + + 28 + 16 * SX126x.PacketParams.Params.LoRa.CrcMode - + ( ( SX126x.PacketParams.Params.LoRa.HeaderType == LORA_PACKET_FIXED_LENGTH ) ? 20 : 0 ) ) / + ( double )( 4 * ( SX126x.ModulationParams.Params.LoRa.SpreadingFactor - + ( ( SX126x.ModulationParams.Params.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) * + ( ( SX126x.ModulationParams.Params.LoRa.CodingRate % 4 ) + 4 ); + double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 ); + double tPayload = nPayload * ts; + // Time on air + double tOnAir = tPreamble + tPayload; + // return milli seconds + airTime = floor( tOnAir + 0.999 ); + } + break; + } + return airTime; +} + +void RadioSend( uint8_t *buffer, uint8_t size ) +{ + SX126xSetDioIrqParams( IRQ_TX_DONE , + IRQ_TX_DONE , + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + if( SX126xGetPacketType( ) == PACKET_TYPE_LORA ) + { + SX126x.PacketParams.Params.LoRa.PayloadLength = size; + } + else + { + SX126x.PacketParams.Params.Gfsk.PayloadLength = size; + } + SX126xSetPacketParams( &SX126x.PacketParams ); + + SX126xSendPayload( buffer, size, 0 ); + TimerSetValue( &TxTimeoutTimer, TxTimeout ); + TimerStart( &TxTimeoutTimer ); +} + +void RadioSleep( void ) +{ + + SleepParams_t params = { 0 }; + + params.Fields.WarmStart = 1; + SX126xSetSleep( params ); + + DelayMs( 2 ); + +} + +void RadioStandby( void ) +{ + + SX126xSetStandby( STDBY_RC ); +} + +void RadioRx( uint32_t timeout ) +{ + SX126xSetDioIrqParams( IRQ_RX_DONE | IRQ_CRC_ERROR| IRQ_RX_TX_TIMEOUT, + IRQ_RX_DONE | IRQ_CRC_ERROR| IRQ_RX_TX_TIMEOUT, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + if( timeout != 0 ) + { + TimerSetValue( &RxTimeoutTimer, timeout ); + TimerStart( &RxTimeoutTimer ); + } + + if( RxContinuous == true ) + { + SX126xSetLoRaSymbNumTimeout( 0 ); + SX126xSetRx( 0xFFFFFF ); // Rx Continuous + } + else + { + SX126xSetRx( RxTimeout << 6 ); + } +} + +void RadioRxBoosted( uint32_t timeout ) +{ + SX126xSetDioIrqParams( IRQ_RX_DONE, + IRQ_RX_DONE, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + + if( timeout != 0 ) + { + TimerSetValue( &RxTimeoutTimer, timeout ); + TimerStart( &RxTimeoutTimer ); + } + + if( RxContinuous == true ) + { + SX126xSetRxBoosted( 0xFFFFFF ); // Rx Continuous + } + else + { + SX126xSetRxBoosted( RxTimeout << 6 ); + } +} + +void RadioSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) +{ + SX126xSetRxDutyCycle( rxTime, sleepTime ); +} + +void RadioStartCad( uint8_t symbols ) +{ + uint8_t cadDetPeak = SX126x.ModulationParams.Params.LoRa.SpreadingFactor + 13; + uint8_t cadDetMin = 10; + RadioLoRaCadSymbols_t cadSymbolNum = LORA_CAD_16_SYMBOL; + + if(symbols>=16) + cadSymbolNum = LORA_CAD_16_SYMBOL; + else if(symbols>=8) + cadSymbolNum = LORA_CAD_08_SYMBOL; + else if(symbols>=4) + cadSymbolNum = LORA_CAD_04_SYMBOL; + else if(symbols>=2) + cadSymbolNum = LORA_CAD_02_SYMBOL; + else + cadSymbolNum = LORA_CAD_01_SYMBOL; + + SX126xSetDioIrqParams( IRQ_CAD_DONE | IRQ_CAD_ACTIVITY_DETECTED, + IRQ_CAD_DONE | IRQ_CAD_ACTIVITY_DETECTED, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + SX126xSetCadParams( cadSymbolNum, cadDetPeak, cadDetMin, LORA_CAD_ONLY, 0 ); + + SX126xSetCad( ); + + TimerSetValue( &CadTimeoutTimer, 2000 ); + TimerStart( &CadTimeoutTimer ); +} + +void RadioTx( uint32_t timeout ) +{ + SX126xSetTx( timeout << 6 ); +} + +void RadioSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ) +{ + SX126xSetRfFrequency( freq ); + SX126xSetRfTxPower( power ); + SX126xSetTxContinuousWave( ); + + TimerSetValue( &RxTimeoutTimer, time * 1e3 ); + TimerStart( &RxTimeoutTimer ); +} + +int16_t RadioRssi( RadioModems_t modem ) +{ + return SX126xGetRssiInst( ); +} + +void RadioWrite( uint16_t addr, uint8_t data ) +{ + SX126xWriteRegister( addr, data ); +} + +uint8_t RadioRead( uint16_t addr ) +{ + return SX126xReadRegister( addr ); +} + +void RadioWriteBuffer( uint16_t addr, uint8_t *buffer, uint8_t size ) +{ + SX126xWriteRegisters( addr, buffer, size ); +} + +void RadioReadBuffer( uint16_t addr, uint8_t *buffer, uint8_t size ) +{ + SX126xReadRegisters( addr, buffer, size ); +} +void RadioSyncWord( uint8_t data ) +{ + SX126xSetSyncWord(&data); +} + +void RadioWriteFifo( uint8_t *buffer, uint8_t size ) +{ + SX126xWriteBuffer( 0, buffer, size ); +} + +void RadioReadFifo( uint8_t *buffer, uint8_t size ) +{ + SX126xReadBuffer( 0, buffer, size ); +} + +void RadioSetMaxPayloadLength( RadioModems_t modem, uint8_t max ) +{ + if( modem == MODEM_LORA ) + { + SX126x.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength = max; + SX126xSetPacketParams( &SX126x.PacketParams ); + } + else + { + if( SX126x.PacketParams.Params.Gfsk.HeaderType == RADIO_PACKET_VARIABLE_LENGTH ) + { + SX126x.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max; + SX126xSetPacketParams( &SX126x.PacketParams ); + } + } +} + +void RadioSetPublicNetwork( bool enable ) +{ + RadioPublicNetwork.Current = RadioPublicNetwork.Previous = enable; + + RadioSetModem( MODEM_LORA ); + if( enable == true ) + { + // Change LoRa modem SyncWord + SX126xWriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PUBLIC_SYNCWORD >> 8 ) & 0xFF ); + SX126xWriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PUBLIC_SYNCWORD & 0xFF ); + } + else + { + // Change LoRa modem SyncWord + SX126xWriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF ); + SX126xWriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF ); + } +} + +uint32_t RadioGetWakeupTime( void ) +{ + return SX126xGetBoardTcxoWakeupTime( ) + RADIO_WAKEUP_TIME; +} + +void RadioOnTxTimeoutIrq( void ) +{ + SX126xSetOperatingMode(MODE_SLEEP); + if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) + { + RadioEvents->TxTimeout( ); + } +} + +void RadioOnRxTimeoutIrq( void ) +{ + SX126xSetOperatingMode(MODE_SLEEP); + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + { + RadioEvents->RxTimeout( ); + } +} + +void RadioOnCadTimeoutIrq( void ) +{ + SX126xSetOperatingMode(MODE_SLEEP); + if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) + { + RadioEvents->CadDone( 0 ); + } +} + +extern void enableUart(void); +extern uint8_t dio1_ClearInterrupt(void); +void RadioOnDioIrq( void ) +{ + IrqFired = true; + //dio1_ClearInterrupt(); + //RadioIrqProcess(); +} + +void RadioIrqProcess( void ) +{ + if( IrqFired == true ) + { + BoardDisableIrq( ); + IrqFired = false; + BoardEnableIrq( ); + + uint16_t irqRegs = SX126xGetIrqStatus( ); + SX126xClearIrqStatus( IRQ_RADIO_ALL ); + + if( ( irqRegs & IRQ_TX_DONE ) == IRQ_TX_DONE ) + { + //printf("tx done\r\n"); + TimerStop( &TxTimeoutTimer ); + SX126xSetOperatingMode(MODE_SLEEP); + if( ( RadioEvents != NULL ) && ( RadioEvents->TxDone != NULL ) ) + { + RadioEvents->TxDone( ); + } + } + + if( ( irqRegs & IRQ_RX_DONE ) == IRQ_RX_DONE ) + { + //printf("rx done\r\n"); + uint8_t size; + TimerStop( &RxTimeoutTimer ); + SX126xGetPayload( RadioRxPayload, &size , 255 ); + SX126xGetPacketStatus( &RadioPktStatus ); + if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) && ( irqRegs & IRQ_CRC_ERROR ) != IRQ_CRC_ERROR) + { + RadioEvents->RxDone( RadioRxPayload, size, RadioPktStatus.Params.LoRa.RssiPkt, RadioPktStatus.Params.LoRa.SnrPkt ); + } + } + + if( ( irqRegs & IRQ_CRC_ERROR ) == IRQ_CRC_ERROR ) + { + if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) ) + { + RadioEvents->RxError( ); + } + } + + if( ( irqRegs & IRQ_CAD_DONE ) == IRQ_CAD_DONE ) + { + TimerStop( &CadTimeoutTimer ); + if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) + { + RadioEvents->CadDone( ( ( irqRegs & IRQ_CAD_ACTIVITY_DETECTED ) == IRQ_CAD_ACTIVITY_DETECTED ) ); + } + } + + if( ( irqRegs & IRQ_RX_TX_TIMEOUT ) == IRQ_RX_TX_TIMEOUT ) + { + if( SX126xGetOperatingMode( ) == MODE_TX ) + { + TimerStop( &TxTimeoutTimer ); + SX126xSetOperatingMode(MODE_SLEEP); + if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) + { + RadioEvents->TxTimeout( ); + } + } + else if( SX126xGetOperatingMode( ) == MODE_RX ) + { + TimerStop( &RxTimeoutTimer ); + SX126xSetOperatingMode(MODE_SLEEP); + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + { + RadioEvents->RxTimeout( ); + } + } + } + + if( ( irqRegs & IRQ_PREAMBLE_DETECTED ) == IRQ_PREAMBLE_DETECTED ) + { + //__NOP( ); + } + + if( ( irqRegs & IRQ_SYNCWORD_VALID ) == IRQ_SYNCWORD_VALID ) + { + //__NOP( ); + } + + if( ( irqRegs & IRQ_HEADER_VALID ) == IRQ_HEADER_VALID ) + { + //__NOP( ); + } + + if( ( irqRegs & IRQ_HEADER_ERROR ) == IRQ_HEADER_ERROR ) + { + TimerStop( &RxTimeoutTimer ); + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + { + RadioEvents->RxTimeout( ); + } + } + } +} diff --git a/cores/asr650x/device/asr6501_lrwan/radio.h b/cores/asr650x/device/asr6501_lrwan/radio.h new file mode 100644 index 00000000..74de80c9 --- /dev/null +++ b/cores/asr650x/device/asr6501_lrwan/radio.h @@ -0,0 +1,384 @@ +/*! + * \file radio.h + * + * \brief Radio driver API definition + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +#ifndef __RADIO_H__ +#define __RADIO_H__ + +#include +#include + +/*! + * Radio driver supported modems + */ +typedef enum +{ + MODEM_FSK = 0, + MODEM_LORA, +}RadioModems_t; + +/*! + * Radio driver internal state machine states definition + */ +typedef enum +{ + RF_IDLE = 0, //!< The radio is idle + RF_RX_RUNNING, //!< The radio is in reception state + RF_TX_RUNNING, //!< The radio is in transmission state + RF_CAD, //!< The radio is doing channel activity detection +}RadioState_t; + +/*! + * \brief Radio driver callback functions + */ +typedef struct +{ + /*! + * \brief Tx Done callback prototype. + */ + void ( *TxDone )( void ); + /*! + * \brief Tx Timeout callback prototype. + */ + void ( *TxTimeout )( void ); + /*! + * \brief Rx Done callback prototype. + * + * \param [IN] payload Received buffer pointer + * \param [IN] size Received buffer size + * \param [IN] rssi RSSI value computed while receiving the frame [dBm] + * \param [IN] snr Raw SNR value given by the radio hardware + * FSK : N/A ( set to 0 ) + * LoRa: SNR value in dB + */ + void ( *RxDone )( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ); + /*! + * \brief Rx Timeout callback prototype. + */ + void ( *RxTimeout )( void ); + /*! + * \brief Rx Error callback prototype. + */ + void ( *RxError )( void ); + /*! + * \brief FHSS Change Channel callback prototype. + * + * \param [IN] currentChannel Index number of the current channel + */ + void ( *FhssChangeChannel )( uint8_t currentChannel ); + + /*! + * \brief CAD Done callback prototype. + * + * \param [IN] channelDetected Channel Activity detected during the CAD + */ + void ( *CadDone ) ( bool channelActivityDetected ); +}RadioEvents_t; + +/*! + * \brief Radio driver definition + */ +struct Radio_s +{ + /*! + * \brief Initializes the radio + * + * \param [IN] events Structure containing the driver callback functions + */ + int ( *Init )( RadioEvents_t *events ); + /*! + * Return current radio status + * + * \param status Radio status.[RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING] + */ + RadioState_t ( *GetStatus )( void ); + /*! + * \brief Configures the radio with the given modem + * + * \param [IN] modem Modem to be used [0: FSK, 1: LoRa] + */ + void ( *SetModem )( RadioModems_t modem ); + /*! + * \brief Sets the channel frequency + * + * \param [IN] freq Channel RF frequency + */ + void ( *SetChannel )( uint32_t freq ); + /*! + * \brief Checks if the channel is free for the given time + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] freq Channel RF frequency + * \param [IN] rssiThresh RSSI threshold + * \param [IN] maxCarrierSenseTime Max time while the RSSI is measured + * + * \retval isFree [true: Channel is free, false: Channel is not free] + */ + bool ( *IsChannelFree )( RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime ); + /*! + * \brief Generates a 32 bits random value based on the RSSI readings + * + * \remark This function sets the radio in LoRa modem mode and disables + * all interrupts. + * After calling this function either Radio.SetRxConfig or + * Radio.SetTxConfig functions must be called. + * + * \retval randomValue 32 bits random value + */ + uint32_t ( *Random )( void ); + /*! + * \brief Sets the reception parameters + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] bandwidth Sets the bandwidth + * FSK : >= 2600 and <= 250000 Hz + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [IN] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [IN] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [IN] bandwidthAfc Sets the AFC Bandwidth (FSK only) + * FSK : >= 2600 and <= 250000 Hz + * LoRa: N/A ( set to 0 ) + * \param [IN] preambleLen Sets the Preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [IN] symbTimeout Sets the RxSingle timeout value + * FSK : timeout in number of bytes + * LoRa: timeout in symbols + * \param [IN] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [IN] payloadLen Sets payload length when fixed length is used + * \param [IN] crcOn Enables/Disables the CRC [0: OFF, 1: ON] + * \param [IN] freqHopOn Enables disables the intra-packet frequency hopping + * FSK : N/A ( set to 0 ) + * LoRa: [0: OFF, 1: ON] + * \param [IN] hopPeriod Number of symbols between each hop + * FSK : N/A ( set to 0 ) + * LoRa: Number of symbols + * \param [IN] iqInverted Inverts IQ signals (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [0: not inverted, 1: inverted] + * \param [IN] rxContinuous Sets the reception in continuous mode + * [false: single mode, true: continuous mode] + */ + void ( *SetRxConfig )( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint32_t bandwidthAfc, uint16_t preambleLen, + uint16_t symbTimeout, bool fixLen, + uint8_t payloadLen, + bool crcOn, bool freqHopOn, uint8_t hopPeriod, + bool iqInverted, bool rxContinuous ); + /*! + * \brief Sets the transmission parameters + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] power Sets the output power [dBm] + * \param [IN] fdev Sets the frequency deviation (FSK only) + * FSK : [Hz] + * LoRa: 0 + * \param [IN] bandwidth Sets the bandwidth (LoRa only) + * FSK : 0 + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [IN] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [IN] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [IN] preambleLen Sets the preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [IN] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [IN] crcOn Enables disables the CRC [0: OFF, 1: ON] + * \param [IN] freqHopOn Enables disables the intra-packet frequency hopping + * FSK : N/A ( set to 0 ) + * LoRa: [0: OFF, 1: ON] + * \param [IN] hopPeriod Number of symbols between each hop + * FSK : N/A ( set to 0 ) + * LoRa: Number of symbols + * \param [IN] iqInverted Inverts IQ signals (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [0: not inverted, 1: inverted] + * \param [IN] timeout Transmission timeout [ms] + */ + void ( *SetTxConfig )( RadioModems_t modem, int8_t power, uint32_t fdev, + uint32_t bandwidth, uint32_t datarate, + uint8_t coderate, uint16_t preambleLen, + bool fixLen, bool crcOn, bool freqHopOn, + uint8_t hopPeriod, bool iqInverted, uint32_t timeout ); + /*! + * \brief Checks if the given RF frequency is supported by the hardware + * + * \param [IN] frequency RF frequency to be checked + * \retval isSupported [true: supported, false: unsupported] + */ + bool ( *CheckRfFrequency )( uint32_t frequency ); + /*! + * \brief Computes the packet time on air in ms for the given payload + * + * \Remark Can only be called once SetRxConfig or SetTxConfig have been called + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] pktLen Packet payload length + * + * \retval airTime Computed airTime (ms) for the given packet payload length + */ + uint32_t ( *TimeOnAir )( RadioModems_t modem, uint8_t pktLen ); + /*! + * \brief Sends the buffer of size. Prepares the packet to be sent and sets + * the radio in transmission + * + * \param [IN]: buffer Buffer pointer + * \param [IN]: size Buffer size + */ + void ( *Send )( uint8_t *buffer, uint8_t size ); + /*! + * \brief Sets the radio in sleep mode + */ + void ( *Sleep )( void ); + /*! + * \brief Sets the radio in standby mode + */ + void ( *Standby )( void ); + /*! + * \brief Sets the radio in reception mode for the given time + * \param [IN] timeout Reception timeout [ms] + * [0: continuous, others timeout] + */ + void ( *Rx )( uint32_t timeout ); + /*! + * \brief Start a Channel Activity Detection + */ + void ( *StartCad )( uint8_t symbols ); + /*! + * \brief Sets the radio in continuous wave transmission mode + * + * \param [IN]: freq Channel RF frequency + * \param [IN]: power Sets the output power [dBm] + * \param [IN]: time Transmission mode timeout [s] + */ + void ( *SetTxContinuousWave )( uint32_t freq, int8_t power, uint16_t time ); + /*! + * \brief Reads the current RSSI value + * + * \retval rssiValue Current RSSI value in [dBm] + */ + int16_t ( *Rssi )( RadioModems_t modem ); + /*! + * \brief Writes the radio register at the specified address + * + * \param [IN]: addr Register address + * \param [IN]: data New register value + */ + void ( *Write )( uint16_t addr, uint8_t data ); + /*! + * \brief Reads the radio register at the specified address + * + * \param [IN]: addr Register address + * \retval data Register value + */ + uint8_t ( *Read )( uint16_t addr ); + /*! + * \brief Writes multiple radio registers starting at address + * + * \param [IN] addr First Radio register address + * \param [IN] buffer Buffer containing the new register's values + * \param [IN] size Number of registers to be written + */ + void ( *WriteBuffer )( uint16_t addr, uint8_t *buffer, uint8_t size ); + /*! + * \brief Reads multiple radio registers starting at address + * + * \param [IN] addr First Radio register address + * \param [OUT] buffer Buffer where to copy the registers data + * \param [IN] size Number of registers to be read + */ + void ( *ReadBuffer )( uint16_t addr, uint8_t *buffer, uint8_t size ); + /*! + * \brief Set synchro word in radio + * + * \param [IN] data THe syncword + */ + void ( *SetSyncWord )( uint8_t data ); + + /*! + * \brief Sets the maximum payload length. + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] max Maximum payload length in bytes + */ + void ( *SetMaxPayloadLength )( RadioModems_t modem, uint8_t max ); + /*! + * \brief Sets the network to public or private. Updates the sync byte. + * + * \remark Applies to LoRa modem only + * + * \param [IN] enable if true, it enables a public network + */ + void ( *SetPublicNetwork )( bool enable ); + /*! + * \brief Gets the time required for the board plus radio to get out of sleep.[ms] + * + * \retval time Radio plus board wakeup time in ms. + */ + uint32_t ( *GetWakeupTime )( void ); + /*! + * \brief Process radio irq + */ + void ( *IrqProcess )( void ); + /* + * The next functions are available only on SX126x radios. + */ + /*! + * \brief Sets the radio in reception mode with Max LNA gain for the given time + * + * \remark Available on SX126x radios only. + * + * \param [IN] timeout Reception timeout [ms] + * [0: continuous, others timeout] + */ + void ( *RxBoosted )( uint32_t timeout ); + /*! + * \brief Sets the Rx duty cycle management parameters + * + * \remark Available on SX126x radios only. + * + * \param [in] rxTime Structure describing reception timeout value + * \param [in] sleepTime Structure describing sleep timeout value + */ + void ( *SetRxDutyCycle ) ( uint32_t rxTime, uint32_t sleepTime ); +}; + +/*! + * \brief Radio driver + * + * \remark This variable is defined and initialized in the specific radio + * board implementation + */ +extern const struct Radio_s Radio; + +#endif // __RADIO_H__ diff --git a/cores/asr650x/device/sx126x/sx126x.c b/cores/asr650x/device/sx126x/sx126x.c new file mode 100644 index 00000000..21d09e6f --- /dev/null +++ b/cores/asr650x/device/sx126x/sx126x.c @@ -0,0 +1,722 @@ +#include +#include "utilities.h" +#include "timer.h" +#include "radio.h" +#include "delay.h" +#include "sx126x.h" +#include "sx126x-board.h" + +/*! + * \brief Radio registers definition + */ +typedef struct +{ + uint16_t Addr; //!< The address of the register + uint8_t Value; //!< The value of the register +}RadioRegisters_t; + +/*! + * \brief Holds the internal operating mode of the radio + */ +static volatile RadioOperatingModes_t OperatingMode; + +/*! + * \brief Stores the current packet type set in the radio + */ +static RadioPacketTypes_t PacketType; + +/*! + * \brief Stores the last frequency error measured on LoRa received packet + */ +volatile uint32_t FrequencyError = 0; + +/*! + * \brief Hold the status of the Image calibration + */ +static bool ImageCalibrated = false; + +/* + * SX126x DIO IRQ callback functions prototype + */ + +/*! + * \brief DIO 0 IRQ callback + */ +void SX126xOnDioIrq( void ); + +/*! + * \brief DIO 0 IRQ callback + */ +void SX126xSetPollingMode( void ); + +/*! + * \brief DIO 0 IRQ callback + */ +void SX126xSetInterruptMode( void ); + +/* + * \brief Process the IRQ if handled by the driver + */ +void SX126xProcessIrqs( void ); + +extern bool UseTCXO; +extern uint8_t gPaOptSetting; +int SX126xInit( DioIrqHandler dioIrq ) +{ + SX126xReset( ); + + SX126xIoIrqInit( dioIrq ); + SX126xWakeup( ); + SX126xSetStandby( STDBY_RC ); + + if(UseTCXO) { + CalibrationParams_t calibParam; + + SX126xSetDio3AsTcxoCtrl( TCXO_CTRL_1_8V, SX126xGetBoardTcxoWakeupTime( ) << 6 ); // convert from ms to SX126x time base + calibParam.Value = 0x7F; + SX126xCalibrate( calibParam ); + } + + + SX126xSetDio2AsRfSwitchCtrl( true ); + OperatingMode = MODE_STDBY_RC; + return 0; +} + +RadioOperatingModes_t SX126xGetOperatingMode( void ) +{ + return OperatingMode; +} +void SX126xSetOperatingMode(RadioOperatingModes_t mode) +{ + OperatingMode=mode; +} + +void SX126xCheckDeviceReady( void ) +{ + if( ( SX126xGetOperatingMode( ) == MODE_SLEEP ) || ( SX126xGetOperatingMode( ) == MODE_RX_DC ) ) + { + SX126xWakeup( ); + // Switch is turned off when device is in sleep mode and turned on is all other modes + SX126xAntSwOn( ); + } + SX126xWaitOnBusy( ); +} + +void SX126xSetPayload( uint8_t *payload, uint8_t size ) +{ + SX126xWriteBuffer( 0x00, payload, size ); +} + +uint8_t SX126xGetPayload( uint8_t *buffer, uint8_t *size, uint8_t maxSize ) +{ + uint8_t offset = 0; + + SX126xGetRxBufferStatus( size, &offset ); + if( *size > maxSize ) + { + return 1; + } + SX126xReadBuffer( offset, buffer, *size ); + return 0; +} + +void SX126xSendPayload( uint8_t *payload, uint8_t size, uint32_t timeout ) +{ + SX126xSetPayload( payload, size ); + SX126xSetTx( timeout ); +} + +uint8_t SX126xSetSyncWord( uint8_t *syncWord ) +{ + SX126xWriteRegister(REG_LR_SYNCWORD, *syncWord); + return 0; +} + +void SX126xSetCrcSeed( uint16_t seed ) +{ + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( seed >> 8 ) & 0xFF ); + buf[1] = ( uint8_t )( seed & 0xFF ); + + switch( SX126xGetPacketType( ) ) + { + case PACKET_TYPE_GFSK: + SX126xWriteRegisters( REG_LR_CRCSEEDBASEADDR, buf, 2 ); + break; + + default: + break; + } +} + +void SX126xSetCrcPolynomial( uint16_t polynomial ) +{ + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( polynomial >> 8 ) & 0xFF ); + buf[1] = ( uint8_t )( polynomial & 0xFF ); + + switch( SX126xGetPacketType( ) ) + { + case PACKET_TYPE_GFSK: + SX126xWriteRegisters( REG_LR_CRCPOLYBASEADDR, buf, 2 ); + break; + + default: + break; + } +} + +void SX126xSetWhiteningSeed( uint16_t seed ) +{ + uint8_t regValue = 0; + + switch( SX126xGetPacketType( ) ) + { + case PACKET_TYPE_GFSK: + regValue = SX126xReadRegister( REG_LR_WHITSEEDBASEADDR_MSB ) & 0xFE; + regValue = ( ( seed >> 8 ) & 0x01 ) | regValue; + SX126xWriteRegister( REG_LR_WHITSEEDBASEADDR_MSB, regValue ); // only 1 bit. + SX126xWriteRegister( REG_LR_WHITSEEDBASEADDR_LSB, ( uint8_t )seed ); + break; + + default: + break; + } +} + +uint32_t SX126xGetRandom( void ) +{ + uint8_t buf[] = { 0, 0, 0, 0 }; + + // Set radio in continuous reception + SX126xSetRx( 0 ); + + DelayMs( 1 ); + + SX126xReadRegisters( RANDOM_NUMBER_GENERATORBASEADDR, buf, 4 ); + + SX126xSetStandby( STDBY_RC ); + + return ( buf[0] << 24 ) | ( buf[1] << 16 ) | ( buf[2] << 8 ) | buf[3]; +} + +void SX126xSetSleep( SleepParams_t sleepConfig ) +{ + SX126xAntSwOff( ); + + SX126xWriteCommand( RADIO_SET_SLEEP, &sleepConfig.Value, 1 ); + OperatingMode = MODE_SLEEP; +} + +void SX126xSetStandby( RadioStandbyModes_t standbyConfig ) +{ + SX126xWriteCommand( RADIO_SET_STANDBY, ( uint8_t* )&standbyConfig, 1 ); + if( standbyConfig == STDBY_RC ) + { + OperatingMode = MODE_STDBY_RC; + } + else + { + OperatingMode = MODE_STDBY_XOSC; + } +} + +void SX126xSetFs( void ) +{ + SX126xWriteCommand( RADIO_SET_FS, 0, 0 ); + OperatingMode = MODE_FS; +} + +void SX126xSetTx( uint32_t timeout ) +{ + uint8_t buf[3]; + + OperatingMode = MODE_TX; + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + buf[2] = ( uint8_t )( timeout & 0xFF ); + SX126xWriteCommand( RADIO_SET_TX, buf, 3 ); +} + +void SX126xSetRx( uint32_t timeout ) +{ + uint8_t buf[3]; + + OperatingMode = MODE_RX; + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + buf[2] = ( uint8_t )( timeout & 0xFF ); + SX126xWriteCommand( RADIO_SET_RX, buf, 3 ); +} + +void SX126xSetRxBoosted( uint32_t timeout ) +{ + uint8_t buf[3]; + + OperatingMode = MODE_RX; + + SX126xWriteRegister( REG_RX_GAIN, 0x96 ); // max LNA gain, increase current by ~2mA for around ~3dB in sensivity + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + buf[2] = ( uint8_t )( timeout & 0xFF ); + SX126xWriteCommand( RADIO_SET_RX, buf, 3 ); +} + +void SX126xSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) +{ + uint8_t buf[6]; + + buf[0] = ( uint8_t )( ( rxTime >> 16 ) & 0xFF ); + buf[1] = ( uint8_t )( ( rxTime >> 8 ) & 0xFF ); + buf[2] = ( uint8_t )( rxTime & 0xFF ); + buf[3] = ( uint8_t )( ( sleepTime >> 16 ) & 0xFF ); + buf[4] = ( uint8_t )( ( sleepTime >> 8 ) & 0xFF ); + buf[5] = ( uint8_t )( sleepTime & 0xFF ); + SX126xWriteCommand( RADIO_SET_RXDUTYCYCLE, buf, 6 ); + OperatingMode = MODE_RX_DC; +} + +void SX126xSetCad( void ) +{ + SX126xWriteCommand( RADIO_SET_CAD, 0, 0 ); + OperatingMode = MODE_CAD; +} + +void SX126xSetTxContinuousWave( void ) +{ + SX126xWriteCommand( RADIO_SET_TXCONTINUOUSWAVE, 0, 0 ); +} + +void SX126xSetTxInfinitePreamble( void ) +{ + SX126xWriteCommand( RADIO_SET_TXCONTINUOUSPREAMBLE, 0, 0 ); +} + +void SX126xSetStopRxTimerOnPreambleDetect( bool enable ) +{ + SX126xWriteCommand( RADIO_SET_STOPRXTIMERONPREAMBLE, ( uint8_t* )&enable, 1 ); +} + +void SX126xSetLoRaSymbNumTimeout( uint8_t SymbNum ) +{ + SX126xWriteCommand( RADIO_SET_LORASYMBTIMEOUT, &SymbNum, 1 ); +} + +void SX126xSetRegulatorMode( RadioRegulatorMode_t mode ) +{ + SX126xWriteCommand( RADIO_SET_REGULATORMODE, ( uint8_t* )&mode, 1 ); +} + +void SX126xCalibrate( CalibrationParams_t calibParam ) +{ + SX126xWriteCommand( RADIO_CALIBRATE, ( uint8_t* )&calibParam, 1 ); +} + +void SX126xCalibrateImage( uint32_t freq ) +{ + uint8_t calFreq[2]; + + if( freq > 900000000 ) + { + calFreq[0] = 0xE1; + calFreq[1] = 0xE9; + } + else if( freq > 850000000 ) + { + calFreq[0] = 0xD7; + calFreq[1] = 0xD8; + } + else if( freq > 770000000 ) + { + calFreq[0] = 0xC1; + calFreq[1] = 0xC5; + } + else if( freq > 460000000 ) + { + calFreq[0] = 0x75; + calFreq[1] = 0x81; + } + else if( freq > 425000000 ) + { + calFreq[0] = 0x6B; + calFreq[1] = 0x6F; + } + SX126xWriteCommand( RADIO_CALIBRATEIMAGE, calFreq, 2 ); +} + +void SX126xSetPaConfig( uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut ) +{ + uint8_t buf[4]; + + buf[0] = paDutyCycle; + buf[1] = hpMax; + buf[2] = deviceSel; + buf[3] = paLut; + SX126xWriteCommand( RADIO_SET_PACONFIG, buf, 4 ); +} + +void SX126xSetRxTxFallbackMode( uint8_t fallbackMode ) +{ + SX126xWriteCommand( RADIO_SET_TXFALLBACKMODE, &fallbackMode, 1 ); +} + +void SX126xSetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask ) +{ + uint8_t buf[8]; + + buf[0] = ( uint8_t )( ( irqMask >> 8 ) & 0x00FF ); + buf[1] = ( uint8_t )( irqMask & 0x00FF ); + buf[2] = ( uint8_t )( ( dio1Mask >> 8 ) & 0x00FF ); + buf[3] = ( uint8_t )( dio1Mask & 0x00FF ); + buf[4] = ( uint8_t )( ( dio2Mask >> 8 ) & 0x00FF ); + buf[5] = ( uint8_t )( dio2Mask & 0x00FF ); + buf[6] = ( uint8_t )( ( dio3Mask >> 8 ) & 0x00FF ); + buf[7] = ( uint8_t )( dio3Mask & 0x00FF ); + SX126xWriteCommand( RADIO_CFG_DIOIRQ, buf, 8 ); +} + +uint16_t SX126xGetIrqStatus( void ) +{ + uint8_t irqStatus[2]; + + SX126xReadCommand( RADIO_GET_IRQSTATUS, irqStatus, 2 ); + return ( irqStatus[0] << 8 ) | irqStatus[1]; +} + +void SX126xSetDio2AsRfSwitchCtrl( uint8_t enable ) +{ + SX126xWriteCommand( RADIO_SET_RFSWITCHMODE, &enable, 1 ); +} + +void SX126xSetDio3AsTcxoCtrl( RadioTcxoCtrlVoltage_t tcxoVoltage, uint32_t timeout ) +{ + uint8_t buf[4]; + + buf[0] = tcxoVoltage & 0x07; + buf[1] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + buf[2] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + buf[3] = ( uint8_t )( timeout & 0xFF ); + + SX126xWriteCommand( RADIO_SET_TCXOMODE, buf, 4 ); +} + +void SX126xSetRfFrequency( uint32_t frequency ) +{ + uint8_t buf[4]; + uint32_t freq = 0; + + if( ImageCalibrated == false ) + { + SX126xCalibrateImage( frequency ); + ImageCalibrated = true; + } + + freq = ( uint32_t )( ( double )frequency / ( double )FREQ_STEP ); + buf[0] = ( uint8_t )( ( freq >> 24 ) & 0xFF ); + buf[1] = ( uint8_t )( ( freq >> 16 ) & 0xFF ); + buf[2] = ( uint8_t )( ( freq >> 8 ) & 0xFF ); + buf[3] = ( uint8_t )( freq & 0xFF ); + SX126xWriteCommand( RADIO_SET_RFFREQUENCY, buf, 4 ); +} + +void SX126xSetPacketType( RadioPacketTypes_t packetType ) +{ + // Save packet type internally to avoid questioning the radio + PacketType = packetType; + SX126xWriteCommand( RADIO_SET_PACKETTYPE, ( uint8_t* )&packetType, 1 ); +} + +RadioPacketTypes_t SX126xGetPacketType( void ) +{ + return PacketType; +} + +void SX126xSetTxParams( int8_t power, RadioRampTimes_t rampTime ) +{ + uint8_t buf[2]; + + if( SX126xGetPaSelect( 0 ) == SX1261 ) + { + if( power == 15 ) + { + SX126xSetPaConfig( 0x06, 0x00, 0x01, 0x01 ); + } + else + { + SX126xSetPaConfig( 0x04, 0x00, 0x01, 0x01 ); + } + if( power >= 14 ) + { + power = 14; + } + else if( power < -3 ) + { + power = -3; + } + SX126xWriteRegister( REG_OCP, 0x18 ); // current max is 80 mA for the whole device + } + else // sx1262 + { + switch(gPaOptSetting) { + case 3: { + SX126xSetPaConfig( 0x02, 0x02, 0x00, 0x01 ); + break; + } + case 2: { + SX126xSetPaConfig( 0x02, 0x03, 0x00, 0x01 ); + break; + } + case 1: { + SX126xSetPaConfig( 0x03, 0x05, 0x00, 0x01 ); + break; + } + case 0: + default: { + SX126xSetPaConfig( 0x04, 0x07, 0x00, 0x01 ); + break; + } + } + + if( power > 22 ) + { + power = 22; + } + else if( power < -3 ) + { + power = -3; + } + SX126xWriteRegister( REG_OCP, 0x38 ); // current max 160mA for the whole device + } + buf[0] = power; + buf[1] = ( uint8_t )rampTime; + SX126xWriteCommand( RADIO_SET_TXPARAMS, buf, 2 ); +} + +void SX126xSetModulationParams( ModulationParams_t *modulationParams ) +{ + uint8_t n; + uint32_t tempVal = 0; + uint8_t buf[8] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + // Check if required configuration corresponds to the stored packet type + // If not, silently update radio packet type + if( PacketType != modulationParams->PacketType ) + { + SX126xSetPacketType( modulationParams->PacketType ); + } + + switch( modulationParams->PacketType ) + { + case PACKET_TYPE_GFSK: + n = 8; + tempVal = ( uint32_t )( 32 * ( ( double )XTAL_FREQ / ( double )modulationParams->Params.Gfsk.BitRate ) ); + buf[0] = ( tempVal >> 16 ) & 0xFF; + buf[1] = ( tempVal >> 8 ) & 0xFF; + buf[2] = tempVal & 0xFF; + buf[3] = modulationParams->Params.Gfsk.ModulationShaping; + buf[4] = modulationParams->Params.Gfsk.Bandwidth; + tempVal = ( uint32_t )( ( double )modulationParams->Params.Gfsk.Fdev / ( double )FREQ_STEP ); + buf[5] = ( tempVal >> 16 ) & 0xFF; + buf[6] = ( tempVal >> 8 ) & 0xFF; + buf[7] = ( tempVal& 0xFF ); + SX126xWriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + break; + case PACKET_TYPE_LORA: + n = 4; + buf[0] = modulationParams->Params.LoRa.SpreadingFactor; + buf[1] = modulationParams->Params.LoRa.Bandwidth; + buf[2] = modulationParams->Params.LoRa.CodingRate; + buf[3] = modulationParams->Params.LoRa.LowDatarateOptimize; + + SX126xWriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + + break; + default: + case PACKET_TYPE_NONE: + return; + } +} + +void SX126xSetPacketParams( PacketParams_t *packetParams ) +{ + uint8_t n; + uint8_t crcVal = 0; + uint8_t buf[9] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + // Check if required configuration corresponds to the stored packet type + // If not, silently update radio packet type + if( PacketType != packetParams->PacketType ) + { + SX126xSetPacketType( packetParams->PacketType ); + } + + switch( packetParams->PacketType ) + { + case PACKET_TYPE_GFSK: + if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_IBM ) + { + SX126xSetCrcSeed( CRC_IBM_SEED ); + SX126xSetCrcPolynomial( CRC_POLYNOMIAL_IBM ); + crcVal = RADIO_CRC_2_BYTES; + } + else if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_CCIT ) + { + SX126xSetCrcSeed( CRC_CCITT_SEED ); + SX126xSetCrcPolynomial( CRC_POLYNOMIAL_CCITT ); + crcVal = RADIO_CRC_2_BYTES_INV; + } + else + { + crcVal = packetParams->Params.Gfsk.CrcLength; + } + n = 9; + buf[0] = ( packetParams->Params.Gfsk.PreambleLength >> 8 ) & 0xFF; + buf[1] = packetParams->Params.Gfsk.PreambleLength; + buf[2] = packetParams->Params.Gfsk.PreambleMinDetect; + buf[3] = ( packetParams->Params.Gfsk.SyncWordLength /*<< 3*/ ); // convert from byte to bit + buf[4] = packetParams->Params.Gfsk.AddrComp; + buf[5] = packetParams->Params.Gfsk.HeaderType; + buf[6] = packetParams->Params.Gfsk.PayloadLength; + buf[7] = crcVal; + buf[8] = packetParams->Params.Gfsk.DcFree; + break; + case PACKET_TYPE_LORA: + n = 6; + buf[0] = ( packetParams->Params.LoRa.PreambleLength >> 8 ) & 0xFF; + buf[1] = packetParams->Params.LoRa.PreambleLength; + buf[2] = packetParams->Params.LoRa.HeaderType; + buf[3] = packetParams->Params.LoRa.PayloadLength; + buf[4] = packetParams->Params.LoRa.CrcMode; + buf[5] = packetParams->Params.LoRa.InvertIQ; + break; + default: + case PACKET_TYPE_NONE: + return; + } + SX126xWriteCommand( RADIO_SET_PACKETPARAMS, buf, n ); +} + +void SX126xSetCadParams( RadioLoRaCadSymbols_t cadSymbolNum, uint8_t cadDetPeak, uint8_t cadDetMin, RadioCadExitModes_t cadExitMode, uint32_t cadTimeout ) +{ + uint8_t buf[7]; + + buf[0] = ( uint8_t )cadSymbolNum; + buf[1] = cadDetPeak; + buf[2] = cadDetMin; + buf[3] = ( uint8_t )cadExitMode; + buf[4] = ( uint8_t )( ( cadTimeout >> 16 ) & 0xFF ); + buf[5] = ( uint8_t )( ( cadTimeout >> 8 ) & 0xFF ); + buf[6] = ( uint8_t )( cadTimeout & 0xFF ); + SX126xWriteCommand( RADIO_SET_CADPARAMS, buf, 5 ); + OperatingMode = MODE_CAD; +} + +void SX126xSetBufferBaseAddress( uint8_t txBaseAddress, uint8_t rxBaseAddress ) +{ + uint8_t buf[2]; + + buf[0] = txBaseAddress; + buf[1] = rxBaseAddress; + SX126xWriteCommand( RADIO_SET_BUFFERBASEADDRESS, buf, 2 ); +} + +RadioStatus_t SX126xGetStatus( void ) +{ + uint8_t stat = 0; + RadioStatus_t status; + + SX126xReadCommand( RADIO_GET_STATUS, ( uint8_t * )&stat, 1 ); + status.Value = stat; + return status; +} + +int8_t SX126xGetRssiInst( void ) +{ + uint8_t buf[1]; + int8_t rssi = 0; + + SX126xReadCommand( RADIO_GET_RSSIINST, buf, 1 ); + rssi = -buf[0] >> 1; + return rssi; +} + +void SX126xGetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBufferPointer ) +{ + uint8_t status[2]; + + SX126xReadCommand( RADIO_GET_RXBUFFERSTATUS, status, 2 ); + + // In case of LORA fixed header, the payloadLength is obtained by reading + // the register REG_LR_PAYLOADLENGTH + if( ( SX126xGetPacketType( ) == PACKET_TYPE_LORA ) && ( SX126xReadRegister( REG_LR_PACKETPARAMS ) >> 7 == 1 ) ) + { + *payloadLength = SX126xReadRegister( REG_LR_PAYLOADLENGTH ); + } + else + { + *payloadLength = status[0]; + } + *rxStartBufferPointer = status[1]; +} + +void SX126xGetPacketStatus( PacketStatus_t *pktStatus ) +{ + uint8_t status[3]; + + SX126xReadCommand( RADIO_GET_PACKETSTATUS, status, 3 ); + + pktStatus->packetType = SX126xGetPacketType( ); + switch( pktStatus->packetType ) + { + case PACKET_TYPE_GFSK: + pktStatus->Params.Gfsk.RxStatus = status[0]; + pktStatus->Params.Gfsk.RssiSync = -status[1] >> 1; + pktStatus->Params.Gfsk.RssiAvg = -status[2] >> 1; + pktStatus->Params.Gfsk.FreqError = 0; + break; + + case PACKET_TYPE_LORA: + pktStatus->Params.LoRa.RssiPkt = -status[0] >> 1; + ( status[1] < 128 ) ? ( pktStatus->Params.LoRa.SnrPkt = status[1] >> 2 ) : ( pktStatus->Params.LoRa.SnrPkt = ( ( status[1] - 256 ) >> 2 ) ); + pktStatus->Params.LoRa.SignalRssiPkt = -status[2] >> 1; + pktStatus->Params.LoRa.FreqError = FrequencyError; + break; + + default: + case PACKET_TYPE_NONE: + // In that specific case, we set everything in the pktStatus to zeros + // and reset the packet type accordingly + memset( pktStatus, 0, sizeof( PacketStatus_t ) ); + pktStatus->packetType = PACKET_TYPE_NONE; + break; + } +} + +RadioError_t SX126xGetDeviceErrors( void ) +{ + RadioError_t error; + + SX126xReadCommand( RADIO_GET_ERROR, ( uint8_t * )&error, 2 ); + return error; +} + +void SX126xClearDeviceErrors( void ) +{ + uint8_t buf[2] = { 0x00, 0x00 }; + SX126xWriteCommand( RADIO_CLR_ERROR, buf, 2 ); +} + +void SX126xClearIrqStatus( uint16_t irq ) +{ + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( ( uint16_t )irq >> 8 ) & 0x00FF ); + buf[1] = ( uint8_t )( ( uint16_t )irq & 0x00FF ); + SX126xWriteCommand( RADIO_CLR_IRQSTATUS, buf, 2 ); +} diff --git a/cores/asr650x/device/sx126x/sx126x.h b/cores/asr650x/device/sx126x/sx126x.h new file mode 100644 index 00000000..0bfbacf8 --- /dev/null +++ b/cores/asr650x/device/sx126x/sx126x.h @@ -0,0 +1,1123 @@ +/*! + * \file sx126x.h + * + * \brief SX126x driver implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ + + +#ifndef __SX126x_H__ +#define __SX126x_H__ + +#include +#include +#include +#include "gpio.h" +#include "spi-board.h" +#include "radio.h" + +#define SX1261 1 +#define SX1262 2 + + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Radio complete Wake-up Time with margin for temperature compensation + */ +#define RADIO_WAKEUP_TIME 3 // [ms] + +/*! + * \brief Compensation delay for SetAutoTx/Rx functions in 15.625 microseconds + */ +#define AUTO_RX_TX_OFFSET 2 + +/*! + * \brief LFSR initial value to compute IBM type CRC + */ +#define CRC_IBM_SEED 0xFFFF + +/*! + * \brief LFSR initial value to compute CCIT type CRC + */ +#define CRC_CCITT_SEED 0x1D0F + +/*! + * \brief Polynomial used to compute IBM CRC + */ +#define CRC_POLYNOMIAL_IBM 0x8005 + +/*! + * \brief Polynomial used to compute CCIT CRC + */ +#define CRC_POLYNOMIAL_CCITT 0x1021 + +/*! + * \brief The address of the register holding the first byte defining the CRC seed + * + */ +#define REG_LR_CRCSEEDBASEADDR 0x06BC + +/*! + * \brief The address of the register holding the first byte defining the CRC polynomial + */ +#define REG_LR_CRCPOLYBASEADDR 0x06BE + +/*! + * \brief The address of the register holding the first byte defining the whitening seed + */ +#define REG_LR_WHITSEEDBASEADDR_MSB 0x06B8 +#define REG_LR_WHITSEEDBASEADDR_LSB 0x06B9 + +/*! + * \brief The address of the register holding the packet configuration + */ +#define REG_LR_PACKETPARAMS 0x0704 + +/*! + * \brief The address of the register holding the payload size + */ +#define REG_LR_PAYLOADLENGTH 0x0702 + +/*! + * \brief The addresses of the registers holding SyncWords values + */ +#define REG_LR_SYNCWORDBASEADDRESS 0x06C0 + +/*! + * \brief The addresses of the register holding LoRa Modem SyncWord value + */ +#define REG_LR_SYNCWORD 0x0740 + +/*! + * Syncword for Private LoRa networks + */ +#define LORA_MAC_PRIVATE_SYNCWORD 0x1424 + +/*! + * Syncword for Public LoRa networks + */ +#define LORA_MAC_PUBLIC_SYNCWORD 0x3444 + +/*! + * The address of the register giving a 4 bytes random number + */ +#define RANDOM_NUMBER_GENERATORBASEADDR 0x0819 + +/*! + * The address of the register holding RX Gain value (0x94: power saving, 0x96: rx boosted) + */ +#define REG_RX_GAIN 0x08AC + +/*! + * Change the value on the device internal trimming capacitor + */ +#define REG_XTA_TRIM 0x0911 + +/*! + * Set the current max value in the over current protection + */ +#define REG_OCP 0x08E7 + +/*! + * \brief Structure describing the radio status + */ +typedef union RadioStatus_u +{ + uint8_t Value; + struct + { //bit order is lsb -> msb + uint8_t Reserved : 1; //!< Reserved + uint8_t CmdStatus : 3; //!< Command status + uint8_t ChipMode : 3; //!< Chip mode + uint8_t CpuBusy : 1; //!< Flag for CPU radio busy + }Fields; +}RadioStatus_t; + +/*! + * \brief Structure describing the error codes for callback functions + */ +typedef enum +{ + IRQ_HEADER_ERROR_CODE = 0x01, + IRQ_SYNCWORD_ERROR_CODE = 0x02, + IRQ_CRC_ERROR_CODE = 0x04, +}IrqErrorCode_t; + +enum IrqPblSyncHeaderCode_t +{ + IRQ_PBL_DETECT_CODE = 0x01, + IRQ_SYNCWORD_VALID_CODE = 0x02, + IRQ_HEADER_VALID_CODE = 0x04, +}; + +/*! + * \brief Represents the operating mode the radio is actually running + */ +typedef enum +{ + MODE_SLEEP = 0x00, //! The radio is in sleep mode + MODE_STDBY_RC, //! The radio is in standby mode with RC oscillator + MODE_STDBY_XOSC, //! The radio is in standby mode with XOSC oscillator + MODE_FS, //! The radio is in frequency synthesis mode + MODE_TX, //! The radio is in transmit mode + MODE_RX, //! The radio is in receive mode + MODE_RX_DC, //! The radio is in receive duty cycle mode + MODE_CAD //! The radio is in channel activity detection mode +}RadioOperatingModes_t; + +/*! + * \brief Declares the oscillator in use while in standby mode + * + * Using the STDBY_RC standby mode allow to reduce the energy consumption + * STDBY_XOSC should be used for time critical applications + */ +typedef enum +{ + STDBY_RC = 0x00, + STDBY_XOSC = 0x01, +}RadioStandbyModes_t; + +/*! + * \brief Declares the power regulation used to power the device + * + * This command allows the user to specify if DC-DC or LDO is used for power regulation. + * Using only LDO implies that the Rx or Tx current is doubled + */ +typedef enum +{ + USE_LDO = 0x00, // default + USE_DCDC = 0x01, +}RadioRegulatorMode_t; + +/*! + * \brief Represents the possible packet type (i.e. modem) used + */ +typedef enum +{ + PACKET_TYPE_GFSK = 0x00, + PACKET_TYPE_LORA = 0x01, + PACKET_TYPE_NONE = 0x0F, +}RadioPacketTypes_t; + +/*! + * \brief Represents the ramping time for power amplifier + */ +typedef enum +{ + RADIO_RAMP_10_US = 0x00, + RADIO_RAMP_20_US = 0x01, + RADIO_RAMP_40_US = 0x02, + RADIO_RAMP_80_US = 0x03, + RADIO_RAMP_200_US = 0x04, + RADIO_RAMP_800_US = 0x05, + RADIO_RAMP_1700_US = 0x06, + RADIO_RAMP_3400_US = 0x07, +}RadioRampTimes_t; + +/*! + * \brief Represents the number of symbols to be used for channel activity detection operation + */ +typedef enum +{ + LORA_CAD_01_SYMBOL = 0x00, + LORA_CAD_02_SYMBOL = 0x01, + LORA_CAD_04_SYMBOL = 0x02, + LORA_CAD_08_SYMBOL = 0x03, + LORA_CAD_16_SYMBOL = 0x04, +}RadioLoRaCadSymbols_t; + +/*! + * \brief Represents the Channel Activity Detection actions after the CAD operation is finished + */ +typedef enum +{ + LORA_CAD_ONLY = 0x00, + LORA_CAD_RX = 0x01, + LORA_CAD_LBT = 0x10, +}RadioCadExitModes_t; + +/*! + * \brief Represents the modulation shaping parameter + */ +typedef enum +{ + MOD_SHAPING_OFF = 0x00, + MOD_SHAPING_G_BT_03 = 0x08, + MOD_SHAPING_G_BT_05 = 0x09, + MOD_SHAPING_G_BT_07 = 0x0A, + MOD_SHAPING_G_BT_1 = 0x0B, +}RadioModShapings_t; + +/*! + * \brief Represents the modulation shaping parameter + */ +typedef enum +{ + RX_BW_4800 = 0x1F, + RX_BW_5800 = 0x17, + RX_BW_7300 = 0x0F, + RX_BW_9700 = 0x1E, + RX_BW_11700 = 0x16, + RX_BW_14600 = 0x0E, + RX_BW_19500 = 0x1D, + RX_BW_23400 = 0x15, + RX_BW_29300 = 0x0D, + RX_BW_39000 = 0x1C, + RX_BW_46900 = 0x14, + RX_BW_58600 = 0x0C, + RX_BW_78200 = 0x1B, + RX_BW_93800 = 0x13, + RX_BW_117300 = 0x0B, + RX_BW_156200 = 0x1A, + RX_BW_187200 = 0x12, + RX_BW_234300 = 0x0A, + RX_BW_312000 = 0x19, + RX_BW_373600 = 0x11, + RX_BW_467000 = 0x09, +}RadioRxBandwidth_t; + +/*! + * \brief Represents the possible spreading factor values in LoRa packet types + */ +typedef enum +{ + LORA_SF5 = 0x05, + LORA_SF6 = 0x06, + LORA_SF7 = 0x07, + LORA_SF8 = 0x08, + LORA_SF9 = 0x09, + LORA_SF10 = 0x0A, + LORA_SF11 = 0x0B, + LORA_SF12 = 0x0C, +}RadioLoRaSpreadingFactors_t; + +/*! + * \brief Represents the bandwidth values for LoRa packet type + */ +typedef enum +{ + LORA_BW_500 = 6, + LORA_BW_250 = 5, + LORA_BW_125 = 4, + LORA_BW_062 = 3, + LORA_BW_041 = 10, + LORA_BW_031 = 2, + LORA_BW_020 = 9, + LORA_BW_015 = 1, + LORA_BW_010 = 8, + LORA_BW_007 = 0, +}RadioLoRaBandwidths_t; + +/*! + * \brief Represents the coding rate values for LoRa packet type + */ +typedef enum +{ + LORA_CR_4_5 = 0x01, + LORA_CR_4_6 = 0x02, + LORA_CR_4_7 = 0x03, + LORA_CR_4_8 = 0x04, +}RadioLoRaCodingRates_t; + +/*! + * \brief Represents the preamble length used to detect the packet on Rx side + */ +typedef enum +{ + RADIO_PREAMBLE_DETECTOR_OFF = 0x00, //!< Preamble detection length off + RADIO_PREAMBLE_DETECTOR_08_BITS = 0x04, //!< Preamble detection length 8 bits + RADIO_PREAMBLE_DETECTOR_16_BITS = 0x05, //!< Preamble detection length 16 bits + RADIO_PREAMBLE_DETECTOR_24_BITS = 0x06, //!< Preamble detection length 24 bits + RADIO_PREAMBLE_DETECTOR_32_BITS = 0x07, //!< Preamble detection length 32 bit +}RadioPreambleDetection_t; + +/*! + * \brief Represents the possible combinations of SyncWord correlators activated + */ +typedef enum +{ + RADIO_ADDRESSCOMP_FILT_OFF = 0x00, //!< No correlator turned on, i.e. do not search for SyncWord + RADIO_ADDRESSCOMP_FILT_NODE = 0x01, + RADIO_ADDRESSCOMP_FILT_NODE_BROAD = 0x02, +}RadioAddressComp_t; + +/*! + * \brief Radio GFSK packet length mode + */ +typedef enum +{ + RADIO_PACKET_FIXED_LENGTH = 0x00, //!< The packet is known on both sides, no header included in the packet + RADIO_PACKET_VARIABLE_LENGTH = 0x01, //!< The packet is on variable size, header included +}RadioPacketLengthModes_t; + +/*! + * \brief Represents the CRC length + */ +typedef enum +{ + RADIO_CRC_OFF = 0x01, //!< No CRC in use + RADIO_CRC_1_BYTES = 0x00, + RADIO_CRC_2_BYTES = 0x02, + RADIO_CRC_1_BYTES_INV = 0x04, + RADIO_CRC_2_BYTES_INV = 0x06, + RADIO_CRC_2_BYTES_IBM = 0xF1, + RADIO_CRC_2_BYTES_CCIT = 0xF2, +}RadioCrcTypes_t; + +/*! + * \brief Radio whitening mode activated or deactivated + */ +typedef enum +{ + RADIO_DC_FREE_OFF = 0x00, + RADIO_DC_FREEWHITENING = 0x01, +}RadioDcFree_t; + +/*! + * \brief Holds the Radio lengths mode for the LoRa packet type + */ +typedef enum +{ + LORA_PACKET_VARIABLE_LENGTH = 0x00, //!< The packet is on variable size, header included + LORA_PACKET_FIXED_LENGTH = 0x01, //!< The packet is known on both sides, no header included in the packet + LORA_PACKET_EXPLICIT = LORA_PACKET_VARIABLE_LENGTH, + LORA_PACKET_IMPLICIT = LORA_PACKET_FIXED_LENGTH, +}RadioLoRaPacketLengthsMode_t; + +/*! + * \brief Represents the CRC mode for LoRa packet type + */ +typedef enum +{ + LORA_CRC_ON = 0x01, //!< CRC activated + LORA_CRC_OFF = 0x00, //!< CRC not used +}RadioLoRaCrcModes_t; + +/*! + * \brief Represents the IQ mode for LoRa packet type + */ +typedef enum +{ + LORA_IQ_NORMAL = 0x00, + LORA_IQ_INVERTED = 0x01, +}RadioLoRaIQModes_t; + +/*! + * \brief Represents the voltage used to control the TCXO on/off from DIO3 + */ +typedef enum +{ + TCXO_CTRL_1_6V = 0x00, + TCXO_CTRL_1_7V = 0x01, + TCXO_CTRL_1_8V = 0x02, + TCXO_CTRL_2_2V = 0x03, + TCXO_CTRL_2_4V = 0x04, + TCXO_CTRL_2_7V = 0x05, + TCXO_CTRL_3_0V = 0x06, + TCXO_CTRL_3_3V = 0x07, +}RadioTcxoCtrlVoltage_t; + +/*! + * \brief Represents the interruption masks available for the radio + * + * \remark Note that not all these interruptions are available for all packet types + */ +typedef enum +{ + IRQ_RADIO_NONE = 0x0000, + IRQ_TX_DONE = 0x0001, + IRQ_RX_DONE = 0x0002, + IRQ_PREAMBLE_DETECTED = 0x0004, + IRQ_SYNCWORD_VALID = 0x0008, + IRQ_HEADER_VALID = 0x0010, + IRQ_HEADER_ERROR = 0x0020, + IRQ_CRC_ERROR = 0x0040, + IRQ_CAD_DONE = 0x0080, + IRQ_CAD_ACTIVITY_DETECTED = 0x0100, + IRQ_RX_TX_TIMEOUT = 0x0200, + IRQ_RADIO_ALL = 0xFFFF, +}RadioIrqMasks_t; + +/*! + * \brief Represents all possible opcode understood by the radio + */ +typedef enum RadioCommands_e +{ + RADIO_GET_STATUS = 0xC0, + RADIO_WRITE_REGISTER = 0x0D, + RADIO_READ_REGISTER = 0x1D, + RADIO_WRITE_BUFFER = 0x0E, + RADIO_READ_BUFFER = 0x1E, + RADIO_SET_SLEEP = 0x84, + RADIO_SET_STANDBY = 0x80, + RADIO_SET_FS = 0xC1, + RADIO_SET_TX = 0x83, + RADIO_SET_RX = 0x82, + RADIO_SET_RXDUTYCYCLE = 0x94, + RADIO_SET_CAD = 0xC5, + RADIO_SET_TXCONTINUOUSWAVE = 0xD1, + RADIO_SET_TXCONTINUOUSPREAMBLE = 0xD2, + RADIO_SET_PACKETTYPE = 0x8A, + RADIO_GET_PACKETTYPE = 0x11, + RADIO_SET_RFFREQUENCY = 0x86, + RADIO_SET_TXPARAMS = 0x8E, + RADIO_SET_PACONFIG = 0x95, + RADIO_SET_CADPARAMS = 0x88, + RADIO_SET_BUFFERBASEADDRESS = 0x8F, + RADIO_SET_MODULATIONPARAMS = 0x8B, + RADIO_SET_PACKETPARAMS = 0x8C, + RADIO_GET_RXBUFFERSTATUS = 0x13, + RADIO_GET_PACKETSTATUS = 0x14, + RADIO_GET_RSSIINST = 0x15, + RADIO_GET_STATS = 0x10, + RADIO_RESET_STATS = 0x00, + RADIO_CFG_DIOIRQ = 0x08, + RADIO_GET_IRQSTATUS = 0x12, + RADIO_CLR_IRQSTATUS = 0x02, + RADIO_CALIBRATE = 0x89, + RADIO_CALIBRATEIMAGE = 0x98, + RADIO_SET_REGULATORMODE = 0x96, + RADIO_GET_ERROR = 0x17, + RADIO_CLR_ERROR = 0x07, + RADIO_SET_TCXOMODE = 0x97, + RADIO_SET_TXFALLBACKMODE = 0x93, + RADIO_SET_RFSWITCHMODE = 0x9D, + RADIO_SET_STOPRXTIMERONPREAMBLE = 0x9F, + RADIO_SET_LORASYMBTIMEOUT = 0xA0, +}RadioCommands_t; + +/*! + * \brief The type describing the modulation parameters for every packet types + */ +typedef struct +{ + RadioPacketTypes_t PacketType; //!< Packet to which the modulation parameters are referring to. + struct + { + struct + { + uint32_t BitRate; + uint32_t Fdev; + RadioModShapings_t ModulationShaping; + uint8_t Bandwidth; + }Gfsk; + struct + { + RadioLoRaSpreadingFactors_t SpreadingFactor; //!< Spreading Factor for the LoRa modulation + RadioLoRaBandwidths_t Bandwidth; //!< Bandwidth for the LoRa modulation + RadioLoRaCodingRates_t CodingRate; //!< Coding rate for the LoRa modulation + uint8_t LowDatarateOptimize; //!< Indicates if the modem uses the low datarate optimization + }LoRa; + }Params; //!< Holds the modulation parameters structure +}ModulationParams_t; + +/*! + * \brief The type describing the packet parameters for every packet types + */ +typedef struct +{ + RadioPacketTypes_t PacketType; //!< Packet to which the packet parameters are referring to. + struct + { + /*! + * \brief Holds the GFSK packet parameters + */ + struct + { + uint16_t PreambleLength; //!< The preamble Tx length for GFSK packet type in bit + RadioPreambleDetection_t PreambleMinDetect; //!< The preamble Rx length minimal for GFSK packet type + uint8_t SyncWordLength; //!< The synchronization word length for GFSK packet type + RadioAddressComp_t AddrComp; //!< Activated SyncWord correlators + RadioPacketLengthModes_t HeaderType; //!< If the header is explicit, it will be transmitted in the GFSK packet. If the header is implicit, it will not be transmitted + uint8_t PayloadLength; //!< Size of the payload in the GFSK packet + RadioCrcTypes_t CrcLength; //!< Size of the CRC block in the GFSK packet + RadioDcFree_t DcFree; + }Gfsk; + /*! + * \brief Holds the LoRa packet parameters + */ + struct + { + uint16_t PreambleLength; //!< The preamble length is the number of LoRa symbols in the preamble + RadioLoRaPacketLengthsMode_t HeaderType; //!< If the header is explicit, it will be transmitted in the LoRa packet. If the header is implicit, it will not be transmitted + uint8_t PayloadLength; //!< Size of the payload in the LoRa packet + RadioLoRaCrcModes_t CrcMode; //!< Size of CRC block in LoRa packet + RadioLoRaIQModes_t InvertIQ; //!< Allows to swap IQ for LoRa packet + }LoRa; + }Params; //!< Holds the packet parameters structure +}PacketParams_t; + +/*! + * \brief Represents the packet status for every packet type + */ +typedef struct +{ + RadioPacketTypes_t packetType; //!< Packet to which the packet status are referring to. + struct + { + struct + { + uint8_t RxStatus; + int8_t RssiAvg; //!< The averaged RSSI + int8_t RssiSync; //!< The RSSI measured on last packet + uint32_t FreqError; + }Gfsk; + struct + { + int8_t RssiPkt; //!< The RSSI of the last packet + int8_t SnrPkt; //!< The SNR of the last packet + int8_t SignalRssiPkt; + uint32_t FreqError; + }LoRa; + }Params; +}PacketStatus_t; + +/*! + * \brief Represents the Rx internal counters values when GFSK or LoRa packet type is used + */ +typedef struct +{ + RadioPacketTypes_t packetType; //!< Packet to which the packet status are referring to. + uint16_t PacketReceived; + uint16_t CrcOk; + uint16_t LengthError; +}RxCounter_t; + +/*! + * \brief Represents a calibration configuration + */ +typedef union +{ + struct + { + uint8_t RC64KEnable : 1; //!< Calibrate RC64K clock + uint8_t RC13MEnable : 1; //!< Calibrate RC13M clock + uint8_t PLLEnable : 1; //!< Calibrate PLL + uint8_t ADCPulseEnable : 1; //!< Calibrate ADC Pulse + uint8_t ADCBulkNEnable : 1; //!< Calibrate ADC bulkN + uint8_t ADCBulkPEnable : 1; //!< Calibrate ADC bulkP + uint8_t ImgEnable : 1; + uint8_t : 1; + }Fields; + uint8_t Value; +}CalibrationParams_t; + +/*! + * \brief Represents a sleep mode configuration + */ +typedef union +{ + struct + { + uint8_t WakeUpRTC : 1; //!< Get out of sleep mode if wakeup signal received from RTC + uint8_t Reset : 1; + uint8_t WarmStart : 1; + uint8_t Reserved : 5; + }Fields; + uint8_t Value; +}SleepParams_t; + +/*! + * \brief Represents the possible radio system error states + */ +typedef union +{ + struct + { + uint8_t Rc64kCalib : 1; //!< RC 64kHz oscillator calibration failed + uint8_t Rc13mCalib : 1; //!< RC 13MHz oscillator calibration failed + uint8_t PllCalib : 1; //!< PLL calibration failed + uint8_t AdcCalib : 1; //!< ADC calibration failed + uint8_t ImgCalib : 1; //!< Image calibration failed + uint8_t XoscStart : 1; //!< XOSC oscillator failed to start + uint8_t PllLock : 1; //!< PLL lock failed + uint8_t BuckStart : 1; //!< Buck converter failed to start + uint8_t PaRamp : 1; //!< PA ramp failed + uint8_t : 7; //!< Reserved + }Fields; + uint16_t Value; +}RadioError_t; + +/*! + * Radio hardware and global parameters + */ +typedef struct SX126x_s +{ + Gpio_t Reset; + Gpio_t BUSY; + Gpio_t DIO1; + Gpio_t DIO2; + Gpio_t DIO3; + Spi_t Spi; + PacketParams_t PacketParams; + PacketStatus_t PacketStatus; + ModulationParams_t ModulationParams; +}SX126x_t; + +/*! + * Hardware IO IRQ callback function definition + */ +typedef void ( DioIrqHandler )( void ); + +/*! + * SX126x definitions + */ + +/*! + * \brief Provides the frequency of the chip running on the radio and the frequency step + * + * \remark These defines are used for computing the frequency divider to set the RF frequency + */ +#define XTAL_FREQ ( double )32000000 +#define FREQ_DIV ( double )pow( 2.0, 25.0 ) +#define FREQ_STEP ( double )( XTAL_FREQ / FREQ_DIV ) + +#define RX_BUFFER_SIZE 256 + +/*! + * \brief The radio callbacks structure + * Holds function pointers to be called on radio interrupts + */ +typedef struct +{ + void ( *txDone )( void ); //!< Pointer to a function run on successful transmission + void ( *rxDone )( void ); //!< Pointer to a function run on successful reception + void ( *rxPreambleDetect )( void ); //!< Pointer to a function run on successful Preamble detection + void ( *rxSyncWordDone )( void ); //!< Pointer to a function run on successful SyncWord reception + void ( *rxHeaderDone )( bool isOk ); //!< Pointer to a function run on successful Header reception + void ( *txTimeout )( void ); //!< Pointer to a function run on transmission timeout + void ( *rxTimeout )( void ); //!< Pointer to a function run on reception timeout + void ( *rxError )( IrqErrorCode_t errCode ); //!< Pointer to a function run on reception error + void ( *cadDone )( bool cadFlag ); //!< Pointer to a function run on channel activity detected +}SX126xCallbacks_t; + +/*! + * ============================================================================ + * Public functions prototypes + * ============================================================================ + */ + +/*! + * \brief Initializes the radio driver + */ +int SX126xInit( DioIrqHandler dioIrq ); + +/*! + * \brief Gets the current Operation Mode of the Radio + * + * \retval RadioOperatingModes_t last operating mode + */ +RadioOperatingModes_t SX126xGetOperatingMode( void ); +/*! + * \brief Sets the current Operation Mode of the Radio + * + */ +void SX126xSetOperatingMode(RadioOperatingModes_t mode); +/*! + * \brief Wakeup the radio if it is in Sleep mode and check that Busy is low + */ +void SX126xCheckDeviceReady( void ); + +/*! + * \brief Saves the payload to be send in the radio buffer + * + * \param [in] payload A pointer to the payload + * \param [in] size The size of the payload + */ +void SX126xSetPayload( uint8_t *payload, uint8_t size ); + +/*! + * \brief Reads the payload received. If the received payload is longer + * than maxSize, then the method returns 1 and do not set size and payload. + * + * \param [out] payload A pointer to a buffer into which the payload will be copied + * \param [out] size A pointer to the size of the payload received + * \param [in] maxSize The maximal size allowed to copy into the buffer + */ +uint8_t SX126xGetPayload( uint8_t *payload, uint8_t *size, uint8_t maxSize ); + +/*! + * \brief Sends a payload + * + * \param [in] payload A pointer to the payload to send + * \param [in] size The size of the payload to send + * \param [in] timeout The timeout for Tx operation + */ +void SX126xSendPayload( uint8_t *payload, uint8_t size, uint32_t timeout ); + +/*! + * \brief Sets the Sync Word given by index used in GFSK + * + * \param [in] syncWord SyncWord bytes ( 8 bytes ) + * + * \retval status [0: OK, 1: NOK] + */ +uint8_t SX126xSetSyncWord( uint8_t *syncWord ); + +/*! + * \brief Sets the Initial value for the LFSR used for the CRC calculation + * + * \param [in] seed Initial LFSR value ( 2 bytes ) + * + */ +void SX126xSetCrcSeed( uint16_t seed ); + +/*! + * \brief Sets the seed used for the CRC calculation + * + * \param [in] seed The seed value + * + */ +void SX126xSetCrcPolynomial( uint16_t polynomial ); + +/*! + * \brief Sets the Initial value of the LFSR used for the whitening in GFSK protocols + * + * \param [in] seed Initial LFSR value + */ +void SX126xSetWhiteningSeed( uint16_t seed ); + +/*! + * \brief Gets a 32 bits random value generated by the radio + * + * \remark The radio must be in reception mode before executing this function + * + * \retval randomValue 32 bits random value + */ +uint32_t SX126xGetRandom( void ); + +/*! + * \brief Sets the radio in sleep mode + * + * \param [in] sleepConfig The sleep configuration describing data + * retention and RTC wake-up + */ +void SX126xSetSleep( SleepParams_t sleepConfig ); + +/*! + * \brief Sets the radio in configuration mode + * + * \param [in] mode The standby mode to put the radio into + */ +void SX126xSetStandby( RadioStandbyModes_t mode ); + +/*! + * \brief Sets the radio in FS mode + */ +void SX126xSetFs( void ); + +/*! + * \brief Sets the radio in transmission mode + * + * \param [in] timeout Structure describing the transmission timeout value + */ +void SX126xSetTx( uint32_t timeout ); + +/*! + * \brief Sets the radio in reception mode + * + * \param [in] timeout Structure describing the reception timeout value + */ +void SX126xSetRx( uint32_t timeout ); + +/*! + * \brief Sets the radio in reception mode with Boosted LNA gain + * + * \param [in] timeout Structure describing the reception timeout value + */ +void SX126xSetRxBoosted( uint32_t timeout ); + +/*! + * \brief Sets the Rx duty cycle management parameters + * + * \param [in] rxTime Structure describing reception timeout value + * \param [in] sleepTime Structure describing sleep timeout value + */ +void SX126xSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ); + +/*! + * \brief Sets the radio in CAD mode + */ +void SX126xSetCad( void ); + +/*! + * \brief Sets the radio in continuous wave transmission mode + */ +void SX126xSetTxContinuousWave( void ); + +/*! + * \brief Sets the radio in continuous preamble transmission mode + */ +void SX126xSetTxInfinitePreamble( void ); + +/*! + * \brief Decide which interrupt will stop the internal radio rx timer. + * + * \param [in] enable [0: Timer stop after header/syncword detection + * 1: Timer stop after preamble detection] + */ +void SX126xSetStopRxTimerOnPreambleDetect( bool enable ); + +/*! + * \brief Set the number of symbol the radio will wait to validate a reception + * + * \param [in] SymbNum number of LoRa symbols + */ +void SX126xSetLoRaSymbNumTimeout( uint8_t SymbNum ); + +/*! + * \brief Sets the power regulators operating mode + * + * \param [in] mode [0: LDO, 1:DC_DC] + */ +void SX126xSetRegulatorMode( RadioRegulatorMode_t mode ); + +/*! + * \brief Calibrates the given radio block + * + * \param [in] calibParam The description of blocks to be calibrated + */ +void SX126xCalibrate( CalibrationParams_t calibParam ); + +/*! + * \brief Calibrates the Image rejection depending of the frequency + * + * \param [in] freq The operating frequency + */ +void SX126xCalibrateImage( uint32_t freq ); + +/*! + * \brief Activate the extention of the timeout when long preamble is used + * + * \param [in] enable The radio will extend the timeout to cope with long preamble + */ +void SX126xSetLongPreamble( uint8_t enable ); + +/*! + * \brief Sets the transmission parameters + * + * \param [in] paDutyCycle Duty Cycle for the PA + * \param [in] hpMax 0 for sx1261, 7 for sx1262 + * \param [in] deviceSel 1 for sx1261, 0 for sx1262 + * \param [in] paLut 0 for 14dBm LUT, 1 for 22dBm LUT + */ +void SX126xSetPaConfig( uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut ); + +/*! + * \brief Defines into which mode the chip goes after a TX / RX done + * + * \param [in] fallbackMode The mode in which the radio goes + */ +void SX126xSetRxTxFallbackMode( uint8_t fallbackMode ); + +/*! + * \brief Write data to the radio memory + * + * \param [in] address The address of the first byte to write in the radio + * \param [in] buffer The data to be written in radio's memory + * \param [in] size The number of bytes to write in radio's memory + */ +void SX126xWriteRegisters( uint16_t address, uint8_t *buffer, uint16_t size ); + +/*! + * \brief Read data from the radio memory + * + * \param [in] address The address of the first byte to read from the radio + * \param [out] buffer The buffer that holds data read from radio + * \param [in] size The number of bytes to read from radio's memory + */ +void SX126xReadRegisters( uint16_t address, uint8_t *buffer, uint16_t size ); + +/*! + * \brief Write data to the buffer holding the payload in the radio + * + * \param [in] offset The offset to start writing the payload + * \param [in] buffer The data to be written (the payload) + * \param [in] size The number of byte to be written + */ +void SX126xWriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ); + +/*! + * \brief Read data from the buffer holding the payload in the radio + * + * \param [in] offset The offset to start reading the payload + * \param [out] buffer A pointer to a buffer holding the data from the radio + * \param [in] size The number of byte to be read + */ +void SX126xReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ); + +/*! + * \brief Sets the IRQ mask and DIO masks + * + * \param [in] irqMask General IRQ mask + * \param [in] dio1Mask DIO1 mask + * \param [in] dio2Mask DIO2 mask + * \param [in] dio3Mask DIO3 mask + */ +void SX126xSetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask ); + +/*! + * \brief Returns the current IRQ status + * + * \retval irqStatus IRQ status + */ +uint16_t SX126xGetIrqStatus( void ); + +/*! + * \brief Indicates if DIO2 is used to control an RF Switch + * + * \param [in] enable true of false + */ +void SX126xSetDio2AsRfSwitchCtrl( uint8_t enable ); + +/*! + * \brief Indicates if the Radio main clock is supplied from a tcxo + * + * \param [in] tcxoVoltage voltage used to control the TCXO + * \param [in] timeout time given to the TCXO to go to 32MHz + */ +void SX126xSetDio3AsTcxoCtrl( RadioTcxoCtrlVoltage_t tcxoVoltage, uint32_t timeout ); + +/*! + * \brief Sets the RF frequency + * + * \param [in] frequency RF frequency [Hz] + */ +void SX126xSetRfFrequency( uint32_t frequency ); + +/*! + * \brief Sets the radio for the given protocol + * + * \param [in] packetType [PACKET_TYPE_GFSK, PACKET_TYPE_LORA] + * + * \remark This method has to be called before SetRfFrequency, + * SetModulationParams and SetPacketParams + */ +void SX126xSetPacketType( RadioPacketTypes_t packetType ); + +/*! + * \brief Gets the current radio protocol + * + * \retval packetType [PACKET_TYPE_GFSK, PACKET_TYPE_LORA] + */ +RadioPacketTypes_t SX126xGetPacketType( void ); + +/*! + * \brief Sets the transmission parameters + * + * \param [in] power RF output power [-18..13] dBm + * \param [in] rampTime Transmission ramp up time + */ +void SX126xSetTxParams( int8_t power, RadioRampTimes_t rampTime ); + +/*! + * \brief Set the modulation parameters + * + * \param [in] modParams A structure describing the modulation parameters + */ +void SX126xSetModulationParams( ModulationParams_t *modParams ); + +/*! + * \brief Sets the packet parameters + * + * \param [in] packetParams A structure describing the packet parameters + */ +void SX126xSetPacketParams( PacketParams_t *packetParams ); + +/*! + * \brief Sets the Channel Activity Detection (CAD) parameters + * + * \param [in] cadSymbolNum The number of symbol to use for CAD operations + * [LORA_CAD_01_SYMBOL, LORA_CAD_02_SYMBOL, + * LORA_CAD_04_SYMBOL, LORA_CAD_08_SYMBOL, + * LORA_CAD_16_SYMBOL] + * \param [in] cadDetPeak Limit for detection of SNR peak used in the CAD + * \param [in] cadDetMin Set the minimum symbol recognition for CAD + * \param [in] cadExitMode Operation to be done at the end of CAD action + * [LORA_CAD_ONLY, LORA_CAD_RX, LORA_CAD_LBT] + * \param [in] cadTimeout Defines the timeout value to abort the CAD activity + */ +void SX126xSetCadParams( RadioLoRaCadSymbols_t cadSymbolNum, uint8_t cadDetPeak, uint8_t cadDetMin, RadioCadExitModes_t cadExitMode, uint32_t cadTimeout ); + +/*! + * \brief Sets the data buffer base address for transmission and reception + * + * \param [in] txBaseAddress Transmission base address + * \param [in] rxBaseAddress Reception base address + */ +void SX126xSetBufferBaseAddress( uint8_t txBaseAddress, uint8_t rxBaseAddress ); + +/*! + * \brief Gets the current radio status + * + * \retval status Radio status + */ +RadioStatus_t SX126xGetStatus( void ); + +/*! + * \brief Returns the instantaneous RSSI value for the last packet received + * + * \retval rssiInst Instantaneous RSSI + */ +int8_t SX126xGetRssiInst( void ); + +/*! + * \brief Gets the last received packet buffer status + * + * \param [out] payloadLength Last received packet payload length + * \param [out] rxStartBuffer Last received packet buffer address pointer + */ +void SX126xGetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBuffer ); + +/*! + * \brief Gets the last received packet payload length + * + * \param [out] pktStatus A structure of packet status + */ +void SX126xGetPacketStatus( PacketStatus_t *pktStatus ); + +/*! + * \brief Returns the possible system errors + * + * \retval sysErrors Value representing the possible sys failures + */ +RadioError_t SX126xGetDeviceErrors( void ); + +/*! + * \brief Clear all the errors in the device + */ +void SX126xClearDeviceErrors( void ); + +/*! + * \brief Clears the IRQs + * + * \param [in] irq IRQ(s) to be cleared + */ +void SX126xClearIrqStatus( uint16_t irq ); + +#ifdef __cplusplus +} +#endif + +#endif // __SX126x_H__ + + diff --git a/cores/asr650x/kernel/protocols/lorawan/README.md b/cores/asr650x/kernel/protocols/lorawan/README.md new file mode 100644 index 00000000..4180ca8a --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/README.md @@ -0,0 +1,2 @@ +#lib_lorawan +This is lib_lorawan component. \ No newline at end of file diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/LICENSE.txt b/cores/asr650x/kernel/protocols/lorawan/lora/LICENSE.txt new file mode 100644 index 00000000..d6dfb1b8 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/LICENSE.txt @@ -0,0 +1,25 @@ +--- Revised BSD License --- +Copyright (c) 2013, SEMTECH S.A. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Semtech corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL SEMTECH S.A. BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMac.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMac.c new file mode 100644 index 00000000..70395389 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMac.c @@ -0,0 +1,3987 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC layer implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include +#include "radio.h" +#include "timeServer.h" +#include "LoRaMac.h" +#include "region/Region.h" +#include "LoRaMacClassB.h" +#include "LoRaMacCrypto.h" +#ifdef CONFIG_LWAN +#include "lwan_config.h" +#endif +#include "debug.h" +#include "LoRaMacTest.h" +#include "LoRaMacConfirmQueue.h" + +#ifdef CONFIG_LORA_VERIFY +extern bool g_lora_debug; +TimerTime_t mcps_start_time; +#endif +/*! + * Maximum PHY layer payload size + */ +#define LORAMAC_PHY_MAXPAYLOAD 255 + +/*! + * Maximum MAC commands buffer size + */ +#define LORA_MAC_COMMAND_MAX_LENGTH 128 + +/*! + * Maximum length of the fOpts field + */ +#define LORA_MAC_COMMAND_MAX_FOPTS_LENGTH 15 + +/*! + * LoRaMac region. + */ +static LoRaMacRegion_t LoRaMacRegion; + +/*! + * LoRaMac duty cycle for the back-off procedure during the first hour. + */ +#define BACKOFF_DC_1_HOUR 100 + +/*! + * LoRaMac duty cycle for the back-off procedure during the next 10 hours. + */ +#define BACKOFF_DC_10_HOURS 1000 + +/*! + * LoRaMac duty cycle for the back-off procedure during the next 24 hours. + */ +#define BACKOFF_DC_24_HOURS 10000 + +#ifdef CONFIG_LORA_CAD +#define LORA_CAD_CNT_MAX 8 //send frame after LORA_CAD_CNT_MAX times CAD +#define LORA_CAD_SYMBOLS 8 //CAD symbols +#define LORA_CAD_DELAY 1 //delay 1ms after CAD +#endif + +/*! + * Device IEEE EUI + */ +static uint8_t *LoRaMacDevEui; + +/*! + * Application IEEE EUI + */ +static uint8_t *LoRaMacAppEui; + +/*! + * AES encryption/decryption cipher application key + */ +static uint8_t *LoRaMacAppKey; + +/*! + * AES encryption/decryption cipher network session key + */ +static uint8_t LoRaMacNwkSKey[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +/*! + * AES encryption/decryption cipher application session key + */ +static uint8_t LoRaMacAppSKey[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +/*! + * Device nonce is a random value extracted by issuing a sequence of RSSI + * measurements + */ +static uint16_t LoRaMacDevNonce; + +/*! + * Network ID ( 3 bytes ) + */ +static uint32_t LoRaMacNetID; + +/*! + * Mote Address + */ +static uint32_t LoRaMacDevAddr; + +/*! + * Multicast channels linked list + */ +static MulticastParams_t *MulticastChannels = NULL; + +/*! + * Actual device class + */ +static DeviceClass_t LoRaMacDeviceClass; + +/*! + * Indicates if the node is connected to a private or public network + */ +static bool PublicNetwork; + +/*! + * Buffer containing the data to be sent or received. + */ +static uint8_t LoRaMacBuffer[LORAMAC_PHY_MAXPAYLOAD]; + +/*! + * Length of packet in LoRaMacBuffer + */ +static uint16_t LoRaMacBufferPktLen = 0; + +/*! + * Length of the payload in LoRaMacBuffer + */ +static uint8_t LoRaMacTxPayloadLen = 0; + +/*! + * Buffer containing the upper layer data. + */ +static uint8_t LoRaMacRxPayload[LORAMAC_PHY_MAXPAYLOAD]; + +/*! + * LoRaMAC frame counter. Each time a packet is sent the counter is incremented. + * Only the 16 LSB bits are sent + */ +static uint32_t UpLinkCounter = 0; + +/*! + * LoRaMAC frame counter. Each time a packet is received the counter is incremented. + * Only the 16 LSB bits are received + */ +static uint32_t DownLinkCounter = 0; + +/*! + * IsPacketCounterFixed enables the MIC field tests by fixing the + * UpLinkCounter value + */ +static bool IsUpLinkCounterFixed = false; + +/*! + * Used for test purposes. Disables the opening of the reception windows. + */ +static bool IsRxWindowsEnabled = true; + +/*! + * Indicates if the MAC layer has already joined a network. + */ +bool IsLoRaMacNetworkJoined = false; + +/*! + * LoRaMac ADR control status + */ +static bool AdrCtrlOn = false; + +/*! + * Counts the number of missed ADR acknowledgements + */ +static uint32_t AdrAckCounter = 0; + +/*! + * If the node has sent a FRAME_TYPE_DATA_CONFIRMED_UP this variable indicates + * if the nodes needs to manage the server acknowledgement. + */ +static bool NodeAckRequested = false; + +/*! + * If the server has sent a FRAME_TYPE_DATA_CONFIRMED_DOWN this variable indicates + * if the ACK bit must be set for the next transmission + */ +static bool SrvAckRequested = false; + +/*! + * Indicates if the MAC layer wants to send MAC commands + */ +static bool MacCommandsInNextTx = false; + +/*! + * Contains the current MacCommandsBuffer index + */ +static uint8_t MacCommandsBufferIndex = 0; + +/*! + * Contains the current MacCommandsBuffer index for MAC commands to repeat + */ +static uint8_t MacCommandsBufferToRepeatIndex = 0; + +/*! + * Buffer containing the MAC layer commands + */ +static uint8_t MacCommandsBuffer[LORA_MAC_COMMAND_MAX_LENGTH]; + +/*! + * Buffer containing the MAC layer commands which must be repeated + */ +static uint8_t MacCommandsBufferToRepeat[LORA_MAC_COMMAND_MAX_LENGTH]; + +/*! + * LoRaMac parameters + */ +LoRaMacParams_t LoRaMacParams; + +/*! + * LoRaMac default parameters + */ +LoRaMacParams_t LoRaMacParamsDefaults; + +/*! + * Uplink messages repetitions counter + */ +static uint8_t ChannelsNbRepCounter = 0; + +/*! + * Maximum duty cycle + * \remark Possibility to shutdown the device. + */ +static uint8_t MaxDCycle = 0; + +/*! + * Aggregated duty cycle management + */ +static uint16_t AggregatedDCycle; +static TimerTime_t AggregatedLastTxDoneTime; +static TimerTime_t AggregatedTimeOff; + +/*! + * Enables/Disables duty cycle management (Test only) + */ +static bool DutyCycleOn; + +/*! + * Current channel index + */ +static uint8_t Channel; + +/*! + * Current channel index + */ +static uint8_t LastTxChannel; + +/*! + * Set to true, if the last uplink was a join request + */ +static bool LastTxIsJoinRequest; + +/*! + * Stores the time at LoRaMac initialization. + * + * \remark Used for the BACKOFF_DC computation. + */ +static TimerTime_t LoRaMacInitializationTime = 0; + +static TimerSysTime_t LastTxSysTime = { 0 }; + +/*! + * LoRaMac internal states + */ +enum eLoRaMacState { + LORAMAC_IDLE = 0x00000000, + LORAMAC_TX_RUNNING = 0x00000001, + LORAMAC_RX = 0x00000002, + LORAMAC_ACK_REQ = 0x00000004, + LORAMAC_ACK_RETRY = 0x00000008, + LORAMAC_TX_DELAYED = 0x00000010, + LORAMAC_TX_CONFIG = 0x00000020, + LORAMAC_RX_ABORT = 0x00000040, +}; + +/*! + * LoRaMac internal state + */ +uint32_t LoRaMacState = LORAMAC_IDLE; + +/*! + * LoRaMac timer used to check the LoRaMacState (runs every second) + */ +static TimerEvent_t MacStateCheckTimer; + +/*! + * LoRaMac upper layer event functions + */ +static LoRaMacPrimitives_t *LoRaMacPrimitives; + +/*! + * LoRaMac upper layer callback functions + */ +static LoRaMacCallback_t *LoRaMacCallbacks; + +/*! + * Radio events function pointer + */ +static RadioEvents_t RadioEvents; + +/*! + * LoRaMac duty cycle delayed Tx timer + */ +static TimerEvent_t TxDelayedTimer; + +#ifdef CONFIG_LORA_CAD +static TimerEvent_t TxImmediateTimer; +static uint8_t g_lora_cad_cnt = 1; +#endif +/*! + * LoRaMac reception windows timers + */ +static TimerEvent_t RxWindowTimer1; +static TimerEvent_t RxWindowTimer2; + +/*! + * LoRaMac reception windows delay + * \remark normal frame: RxWindowXDelay = ReceiveDelayX - RADIO_WAKEUP_TIME + * join frame : RxWindowXDelay = JoinAcceptDelayX - RADIO_WAKEUP_TIME + */ +static uint32_t RxWindow1Delay; +static uint32_t RxWindow2Delay; + +/*! + * LoRaMac Rx windows configuration + */ +static RxConfigParams_t RxWindow1Config; +static RxConfigParams_t RxWindow2Config; + +/*! + * Acknowledge timeout timer. Used for packet retransmissions. + */ +static TimerEvent_t AckTimeoutTimer; + +/*! + * Number of trials to get a frame acknowledged + */ +static uint8_t AckTimeoutRetries = 1; + +/*! + * Number of trials to get a frame acknowledged + */ +static uint8_t AckTimeoutRetriesCounter = 1; + +/*! + * Indicates if the AckTimeout timer has expired or not + */ +static bool AckTimeoutRetry = false; + +/*! + * Last transmission time on air + */ +TimerTime_t TxTimeOnAir = 0; + +/*! + * Number of trials for the Join Request + */ +static uint8_t JoinRequestTrials; + +/*! + * Maximum number of trials for the Join Request + */ +static uint8_t MaxJoinRequestTrials; + +/*! + * Structure to hold an MCPS indication data. + */ +static McpsIndication_t McpsIndication; + +/*! + * Structure to hold MCPS confirm data. + */ +static McpsConfirm_t McpsConfirm; + +/*! + * Structure to hold MLME indication data. + */ +static MlmeIndication_t MlmeIndication; + +/*! + * Structure to hold MLME confirm data. + */ +static MlmeConfirm_t MlmeConfirm; + +/*! + * Holds the current rx window slot + */ +static LoRaMacRxSlot_t RxSlot; + +/*! + * LoRaMac tx/rx operation state + */ +LoRaMacFlags_t LoRaMacFlags; + +#ifdef CONFIG_LWAN +static bool DownLinkFramePending = false; +#endif + +/*! + * \brief Function to be executed on Radio Tx Done event + */ +static void OnRadioTxDone( void ); + +/*! + * \brief This function prepares the MAC to abort the execution of function + * OnRadioRxDone in case of a reception error. + */ +static void PrepareRxDoneAbort( void ); + +/*! + * \brief Function to be executed on Radio Rx Done event + */ +static void OnRadioRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ); + +/*! + * \brief Function executed on Radio Tx Timeout event + */ +static void OnRadioTxTimeout( void ); + +/*! + * \brief Function executed on Radio Rx error event + */ +static void OnRadioRxError( void ); + +/*! + * \brief Function executed on Radio Rx Timeout event + */ +static void OnRadioRxTimeout( void ); + +#ifdef CONFIG_LORA_CAD +static void OnRadioCadDone( bool channelActivityDetected ); +static void OnTxImmediateTimerEvent( void ); +#endif + +/*! + * \brief Function executed on Resend Frame timer event. + */ +static void OnMacStateCheckTimerEvent( void ); + +/*! + * \brief Function executed on duty cycle delayed Tx timer event + */ +static void OnTxDelayedTimerEvent( void ); + +/*! + * \brief Function executed on first Rx window timer event + */ +static void OnRxWindow1TimerEvent( void ); + +/*! + * \brief Function executed on second Rx window timer event + */ +static void OnRxWindow2TimerEvent( void ); + +/*! + * \brief Check if the OnAckTimeoutTimer has do be disabled. If so, the + * function disables it. + * + * \param [IN] nodeAckRequested Set to true, if the node has requested an ACK + * \param [IN] class The device class + * \param [IN] ackReceived Set to true, if the node has received an ACK + * \param [IN] ackTimeoutRetriesCounter Retries counter for confirmed uplinks + * \param [IN] ackTimeoutRetries Maximum retries for confirmed uplinks + */ +static void CheckToDisableAckTimeout( bool nodeAckRequested, DeviceClass_t devClass, bool ackReceived, + uint8_t ackTimeoutRetriesCounter, uint8_t ackTimeoutRetries ); + +/*! + * \brief Function executed on AckTimeout timer event + */ +static void OnAckTimeoutTimerEvent( void ); + +/*! + * \brief Initializes and opens the reception window + * + * \param [IN] rxContinuous Set to true, if the RX is in continuous mode + * \param [IN] maxRxWindow Maximum RX window timeout + */ +static void RxWindowSetup( bool rxContinuous, uint32_t maxRxWindow ); + +/*! + * \brief Verifies if sticky MAC commands are pending. + * + * \retval [true: sticky MAC commands pending, false: No MAC commands pending] + */ +static bool IsStickyMacCommandPending( void ); + +/*! + * \brief Configures the events to trigger an MLME-Indication with + * a MLME type of MLME_SCHEDULE_UPLINK. + */ +static void SetMlmeScheduleUplinkIndication( void ); + +/*! + * \brief Switches the device class + * + * \param [IN] deviceClass Device class to switch to + */ +static LoRaMacStatus_t SwitchClass( DeviceClass_t deviceClass ); + +/*! + * \brief Adds a new MAC command to be sent. + * + * \Remark MAC layer internal function + * + * \param [in] cmd MAC command to be added + * [MOTE_MAC_LINK_CHECK_REQ, + * MOTE_MAC_LINK_ADR_ANS, + * MOTE_MAC_DUTY_CYCLE_ANS, + * MOTE_MAC_RX2_PARAM_SET_ANS, + * MOTE_MAC_DEV_STATUS_ANS + * MOTE_MAC_NEW_CHANNEL_ANS] + * \param [in] p1 1st parameter ( optional depends on the command ) + * \param [in] p2 2nd parameter ( optional depends on the command ) + * + * \retval status Function status [0: OK, 1: Unknown command, 2: Buffer full] + */ +static LoRaMacStatus_t AddMacCommand( uint8_t cmd, uint8_t p1, uint8_t p2 ); + +/*! + * \brief Parses the MAC commands which must be repeated. + * + * \Remark MAC layer internal function + * + * \param [IN] cmdBufIn Buffer which stores the MAC commands to send + * \param [IN] length Length of the input buffer to parse + * \param [OUT] cmdBufOut Buffer which stores the MAC commands which must be + * repeated. + * + * \retval Size of the MAC commands to repeat. + */ +static uint8_t ParseMacCommandsToRepeat( uint8_t *cmdBufIn, uint8_t length, uint8_t *cmdBufOut ); + +/*! + * \brief Validates if the payload fits into the frame, taking the datarate + * into account. + * + * \details Refer to chapter 4.3.2 of the LoRaWAN specification, v1.0 + * + * \param lenN Length of the application payload. The length depends on the + * datarate and is region specific + * + * \param datarate Current datarate + * + * \param fOptsLen Length of the fOpts field + * + * \retval [false: payload does not fit into the frame, true: payload fits into + * the frame] + */ +static bool ValidatePayloadLength( uint8_t lenN, int8_t datarate, uint8_t fOptsLen ); + +/*! + * \brief Decodes MAC commands in the fOpts field and in the payload + * + * \param [IN] payload A pointer to the payload + * \param [IN] macIndex The index of the payload where the MAC commands start + * \param [IN] commandsSize The size of the MAC commands + * \param [IN] snr The SNR value of the frame + * \param [IN] rxSlot The RX slot where the frame was received + */ +static void ProcessMacCommands( uint8_t *payload, uint8_t macIndex, uint8_t commandsSize, uint8_t snr, LoRaMacRxSlot_t rxSlot ); + +/*! + * \brief LoRaMAC layer generic send frame + * + * \param [IN] macHdr MAC header field + * \param [IN] fPort MAC payload port + * \param [IN] fBuffer MAC data buffer to be sent + * \param [IN] fBufferSize MAC data buffer size + * \retval status Status of the operation. + */ +LoRaMacStatus_t Send( LoRaMacHeader_t *macHdr, uint8_t fPort, void *fBuffer, uint16_t fBufferSize ); + +/*! + * \brief LoRaMAC layer frame buffer initialization + * + * \param [IN] macHdr MAC header field + * \param [IN] fCtrl MAC frame control field + * \param [IN] fOpts MAC commands buffer + * \param [IN] fPort MAC payload port + * \param [IN] fBuffer MAC data buffer to be sent + * \param [IN] fBufferSize MAC data buffer size + * \retval status Status of the operation. + */ +LoRaMacStatus_t PrepareFrame( LoRaMacHeader_t *macHdr, LoRaMacFrameCtrl_t *fCtrl, uint8_t fPort, void *fBuffer, + uint16_t fBufferSize ); + +/* + * \brief Schedules the frame according to the duty cycle + * + * \retval Status of the operation + */ +static LoRaMacStatus_t ScheduleTx( void ); + +/* + * \brief Calculates the back-off time for the band of a channel. + * + * \param [IN] channel The last Tx channel index + */ +static void CalculateBackOff( uint8_t channel ); + +/*! + * \brief LoRaMAC layer prepared frame buffer transmission with channel specification + * + * \remark PrepareFrame must be called at least once before calling this + * function. + * + * \param [IN] channel Channel to transmit on + * \retval status Status of the operation. + */ +LoRaMacStatus_t SendFrameOnChannel( uint8_t channel ); + +/*! + * \brief Sets the radio in continuous transmission mode + * + * \remark Uses the radio parameters set on the previous transmission. + * + * \param [IN] timeout Time in seconds while the radio is kept in continuous wave mode + * \retval status Status of the operation. + */ +LoRaMacStatus_t SetTxContinuousWave( uint16_t timeout ); + +/*! + * \brief Sets the radio in continuous transmission mode + * + * \remark Uses the radio parameters set on the previous transmission. + * + * \param [IN] timeout Time in seconds while the radio is kept in continuous wave mode + * \param [IN] frequency RF frequency to be set. + * \param [IN] power RF output power to be set. + * \retval status Status of the operation. + */ +LoRaMacStatus_t SetTxContinuousWave1( uint16_t timeout, uint32_t frequency, uint8_t power ); + +/*! + * \brief Sets the network to public or private. Updates the sync byte. + * + * \param [IN] enable if true, it enables a public network + */ +//static void SetPublicNetwork( bool enable ); + +/*! + * \brief Resets MAC specific parameters to default + */ +static void ResetMacParameters( void ); + +/*! + * \brief Resets MAC specific parameters to default + * + * \param [IN] fPort The fPort + * + * \retval [false: fPort not allowed, true: fPort allowed] + */ +static bool IsFPortAllowed( uint8_t fPort ); + +/*! + * \brief Opens up a continuous RX 2 window. This is used for + * class c devices. + */ +static void OpenContinuousRx2Window( void ); + +static void OnRadioTxDone( void ) +{ + GetPhyParams_t getPhy; + PhyParam_t phyParam; + SetBandTxDoneParams_t txDone; + TimerTime_t curTime = TimerGetCurrentTime( ); + LastTxSysTime = TimerGetSysTime( ); + + if( LoRaMacDeviceClass != CLASS_C ) + { + Radio.Sleep( ); + } + else + { + OpenContinuousRx2Window( ); + } + + // Setup timers + if ( IsRxWindowsEnabled == true ) { + TimerSetValue( &RxWindowTimer1, RxWindow1Delay ); + TimerStart( &RxWindowTimer1 ); + if ( LoRaMacDeviceClass != CLASS_C ) { + TimerSetValue( &RxWindowTimer2, RxWindow2Delay ); + TimerStart( &RxWindowTimer2 ); + } + if ( ( LoRaMacDeviceClass == CLASS_C ) || ( NodeAckRequested == true ) ) { + getPhy.Attribute = PHY_ACK_TIMEOUT; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + TimerSetValue( &AckTimeoutTimer, RxWindow2Delay + phyParam.Value ); + TimerStart( &AckTimeoutTimer ); + } + } else { + McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_OK; + LoRaMacConfirmQueueSetStatusCmn( LORAMAC_EVENT_INFO_STATUS_RX2_TIMEOUT ); + + if ( LoRaMacFlags.Value == 0 ) { + LoRaMacFlags.Bits.McpsReq = 1; + } + LoRaMacFlags.Bits.MacDone = 1; + } + + // Verify if the last uplink was a join request + if ( ( LoRaMacFlags.Bits.MlmeReq == 1 ) && ( MlmeConfirm.MlmeRequest == MLME_JOIN ) ) { + LastTxIsJoinRequest = true; + } else { + LastTxIsJoinRequest = false; + } + + // Store last Tx channel + LastTxChannel = Channel; + // Update last tx done time for the current channel + txDone.Channel = Channel; + txDone.Joined = IsLoRaMacNetworkJoined; + txDone.LastTxDoneTime = curTime; + RegionSetBandTxDone( LoRaMacRegion, &txDone ); + // Update Aggregated last tx done time + AggregatedLastTxDoneTime = curTime; + + if ( NodeAckRequested == false ) { + McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_OK; +#ifdef CONFIG_LWAN + McpsConfirm.NbRetries++; +#endif + ChannelsNbRepCounter++; + } +#ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) { + PRINTF_RAW("The trasaction consume %llu time(ms)\r\n", curTime - mcps_start_time); + } +#endif +#ifdef CONFIG_LWAN + lwan_dev_status_set(DEVICE_STATUS_SEND_PASS); +#endif + +#if (LoraWan_RGB==1) + RGB_OFF(); +#endif + +} + +static void PrepareRxDoneAbort( void ) +{ + LoRaMacState |= LORAMAC_RX_ABORT; + + if ( NodeAckRequested ) { + OnAckTimeoutTimerEvent( ); + } + + LoRaMacFlags.Bits.McpsInd = 1; + LoRaMacFlags.Bits.MacDone = 1; + + // Trig OnMacCheckTimerEvent call as soon as possible + TimerSetValue( &MacStateCheckTimer, 1 ); + TimerStart( &MacStateCheckTimer ); +} + +static void OnRadioRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ) +{ + LoRaMacHeader_t macHdr; + LoRaMacFrameCtrl_t fCtrl; + ApplyCFListParams_t applyCFList; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + uint8_t pktHeaderLen = 0; + uint32_t address = 0; + uint8_t appPayloadStartIndex = 0; + uint8_t port = 0xFF; + uint8_t frameLen = 0; + uint32_t mic = 0; + uint32_t micRx = 0; + + uint16_t sequenceCounter = 0; + uint16_t sequenceCounterPrev = 0; + uint16_t sequenceCounterDiff = 0; + uint32_t downLinkCounter = 0; + + MulticastParams_t *curMulticastParams = NULL; + uint8_t *nwkSKey = LoRaMacNwkSKey; + uint8_t *appSKey = LoRaMacAppSKey; + + uint8_t multicast = 0; + + bool isMicOk = false; + + McpsConfirm.AckReceived = false; +#ifdef CONFIG_LWAN + MlmeConfirm.Rssi = rssi; + MlmeConfirm.Snr = snr; + McpsIndication.DevTimeAnsReceived = false; + McpsIndication.LinkCheckAnsReceived = false; + McpsIndication.UplinkNeeded = false; +#endif + McpsIndication.Rssi = rssi; + McpsIndication.Snr = snr; + McpsIndication.RxSlot = RxSlot; + McpsIndication.Port = 0; + McpsIndication.Multicast = 0; + McpsIndication.FramePending = 0; + McpsIndication.Buffer = NULL; + McpsIndication.BufferSize = 0; + McpsIndication.RxData = false; + McpsIndication.AckReceived = false; + McpsIndication.DownLinkCounter = 0; + McpsIndication.McpsIndication = MCPS_UNCONFIRMED; + + Radio.Sleep( ); + TimerStop( &RxWindowTimer2 ); + + // This function must be called even if we are not in class b mode yet. + if( LoRaMacClassBRxBeacon( payload, size ) == true ) + { + MlmeIndication.BeaconInfo.Rssi = rssi; + MlmeIndication.BeaconInfo.Snr = snr; +#ifdef LORAMAC_CLASSB_TESTCASE + DBG_PRINTF("receive beacon\r\n"); +#endif + return; + } + // Check if we expect a ping or a multicast slot. + if( LoRaMacDeviceClass == CLASS_B ) + { + if( LoRaMacClassBIsPingExpected( ) == true ) + { + LoRaMacClassBSetPingSlotState( PINGSLOT_STATE_SET_TIMER ); + LoRaMacClassBPingSlotTimerEvent( ); + McpsIndication.RxSlot = RX_SLOT_WIN_PING_SLOT; + } + else if( LoRaMacClassBIsMulticastExpected( ) == true ) + { + LoRaMacClassBSetMulticastSlotState( PINGSLOT_STATE_SET_TIMER ); + LoRaMacClassBMulticastSlotTimerEvent( ); + McpsIndication.RxSlot = RX_SLOT_WIN_MULTICAST_SLOT; + } + } + + macHdr.Value = payload[pktHeaderLen++]; + + switch ( macHdr.Bits.MType ) { + case FRAME_TYPE_JOIN_ACCEPT: + if ( IsLoRaMacNetworkJoined == true ) { + McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + PrepareRxDoneAbort( ); + return; + } + LoRaMacJoinDecrypt( payload + 1, size - 1, LoRaMacAppKey, LoRaMacRxPayload + 1 ); + + LoRaMacRxPayload[0] = macHdr.Value; + + LoRaMacJoinComputeMic( LoRaMacRxPayload, size - LORAMAC_MFR_LEN, LoRaMacAppKey, &mic ); + + micRx |= ( uint32_t )LoRaMacRxPayload[size - LORAMAC_MFR_LEN]; + micRx |= ( ( uint32_t )LoRaMacRxPayload[size - LORAMAC_MFR_LEN + 1] << 8 ); + micRx |= ( ( uint32_t )LoRaMacRxPayload[size - LORAMAC_MFR_LEN + 2] << 16 ); + micRx |= ( ( uint32_t )LoRaMacRxPayload[size - LORAMAC_MFR_LEN + 3] << 24 ); + + if( LoRaMacConfirmQueueIsCmdActive( MLME_JOIN ) == true ) + { + if( micRx == mic ) { + LoRaMacJoinComputeSKeys( LoRaMacAppKey, LoRaMacRxPayload + 1, LoRaMacDevNonce, LoRaMacNwkSKey, LoRaMacAppSKey ); + + LoRaMacNetID = ( uint32_t )LoRaMacRxPayload[4]; + LoRaMacNetID |= ( ( uint32_t )LoRaMacRxPayload[5] << 8 ); + LoRaMacNetID |= ( ( uint32_t )LoRaMacRxPayload[6] << 16 ); + + LoRaMacDevAddr = ( uint32_t )LoRaMacRxPayload[7]; + LoRaMacDevAddr |= ( ( uint32_t )LoRaMacRxPayload[8] << 8 ); + LoRaMacDevAddr |= ( ( uint32_t )LoRaMacRxPayload[9] << 16 ); + LoRaMacDevAddr |= ( ( uint32_t )LoRaMacRxPayload[10] << 24 ); + + // DLSettings + LoRaMacParams.Rx1DrOffset = ( LoRaMacRxPayload[11] >> 4 ) & 0x07; + LoRaMacParams.Rx2Channel.Datarate = LoRaMacRxPayload[11] & 0x0F; + + // RxDelay + LoRaMacParams.ReceiveDelay1 = ( LoRaMacRxPayload[12] & 0x0F ); + if( LoRaMacParams.ReceiveDelay1 == 0 ) { + LoRaMacParams.ReceiveDelay1 = 1; + } + LoRaMacParams.ReceiveDelay1 *= 1000; + LoRaMacParams.ReceiveDelay2 = LoRaMacParams.ReceiveDelay1 + 1000; +#ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) { + PRINTF_RAW("Rx1DrOffset:%u Rx2Channel.Datarate:%u ReceiveDelay1:%u\r\n", + LoRaMacParams.Rx1DrOffset, LoRaMacParams.Rx2Channel.Datarate, (unsigned int)LoRaMacParams.ReceiveDelay1); + } +#endif + // Apply CF list + applyCFList.Payload = &LoRaMacRxPayload[13]; + // Size of the regular payload is 12. Plus 1 byte MHDR and 4 bytes MIC + applyCFList.Size = size - 17; + + RegionApplyCFList( LoRaMacRegion, &applyCFList ); + + LoRaMacConfirmQueueSetStatus( LORAMAC_EVENT_INFO_STATUS_OK, MLME_JOIN ); + IsLoRaMacNetworkJoined = true; + //Joined save its DR using LoRaMacParams.ChannelsDatarate, if set it will be default +// LoRaMacParams.ChannelsDatarate = LoRaMacParamsDefaults.ChannelsDatarate; + } else { + LoRaMacConfirmQueueSetStatus( LORAMAC_EVENT_INFO_STATUS_JOIN_FAIL, MLME_JOIN ); + } + } + break; + case FRAME_TYPE_DATA_CONFIRMED_DOWN: + case FRAME_TYPE_DATA_UNCONFIRMED_DOWN: { + // Check if the received payload size is valid + getPhy.UplinkDwellTime = LoRaMacParams.DownlinkDwellTime; + getPhy.Datarate = McpsIndication.RxDatarate; + getPhy.Attribute = PHY_MAX_PAYLOAD; + + // Get the maximum payload length + if( LoRaMacParams.RepeaterSupport == true ) { + getPhy.Attribute = PHY_MAX_PAYLOAD_REPEATER; + } + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + if ( MAX( 0, ( int16_t )( ( int16_t )size - ( int16_t )LORA_MAC_FRMPAYLOAD_OVERHEAD ) ) > phyParam.Value ) { + McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + PrepareRxDoneAbort( ); + return; + } + + address = payload[pktHeaderLen++]; + address |= ( (uint32_t)payload[pktHeaderLen++] << 8 ); + address |= ( (uint32_t)payload[pktHeaderLen++] << 16 ); + address |= ( (uint32_t)payload[pktHeaderLen++] << 24 ); + + fCtrl.Value = payload[pktHeaderLen++]; + + if ( address != LoRaMacDevAddr ) { + curMulticastParams = MulticastChannels; + while ( curMulticastParams != NULL ) { + if ( address == curMulticastParams->Address ) { + multicast = 1; + nwkSKey = curMulticastParams->NwkSKey; + appSKey = curMulticastParams->AppSKey; + downLinkCounter = curMulticastParams->DownLinkCounter; + break; + } + curMulticastParams = curMulticastParams->Next; + } + if ( multicast == 0 ) { + // We are not the destination of this frame. + McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_ADDRESS_FAIL; + PrepareRxDoneAbort( ); + return; + } + if( ( macHdr.Bits.MType != FRAME_TYPE_DATA_UNCONFIRMED_DOWN ) || + ( fCtrl.Bits.Ack == 1 ) || + ( fCtrl.Bits.AdrAckReq == 1 ) ) { + // Wrong multicast message format. Refer to chapter 11.2.2 of the specification + McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_MULTICAST_FAIL; + PrepareRxDoneAbort( ); + return; + } + } else { + multicast = 0; + nwkSKey = LoRaMacNwkSKey; + appSKey = LoRaMacAppSKey; + downLinkCounter = DownLinkCounter; + } + + sequenceCounter = ( uint16_t )payload[pktHeaderLen++]; + sequenceCounter |= ( uint16_t )payload[pktHeaderLen++] << 8; + + appPayloadStartIndex = 8 + fCtrl.Bits.FOptsLen; + micRx |= ( uint32_t )payload[size - LORAMAC_MFR_LEN]; + micRx |= ( ( uint32_t )payload[size - LORAMAC_MFR_LEN + 1] << 8 ); + micRx |= ( ( uint32_t )payload[size - LORAMAC_MFR_LEN + 2] << 16 ); + micRx |= ( ( uint32_t )payload[size - LORAMAC_MFR_LEN + 3] << 24 ); + + sequenceCounterPrev = ( uint16_t )downLinkCounter; + sequenceCounterDiff = ( sequenceCounter - sequenceCounterPrev ); + + if ( sequenceCounterDiff < ( 1 << 15 ) ) { + downLinkCounter += sequenceCounterDiff; + LoRaMacComputeMic( payload, size - LORAMAC_MFR_LEN, nwkSKey, address, DOWN_LINK, downLinkCounter, &mic ); + if ( micRx == mic ) { + isMicOk = true; + } + } else { + // check for sequence roll-over + uint32_t downLinkCounterTmp = downLinkCounter + 0x10000 + ( int16_t )sequenceCounterDiff; + LoRaMacComputeMic( payload, size - LORAMAC_MFR_LEN, nwkSKey, address, DOWN_LINK, downLinkCounterTmp, &mic ); + if ( micRx == mic ) { + isMicOk = true; + downLinkCounter = downLinkCounterTmp; + } + } + + // Check for a the maximum allowed counter difference + getPhy.Attribute = PHY_MAX_FCNT_GAP; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + if ( sequenceCounterDiff >= phyParam.Value ) { + McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_DOWNLINK_TOO_MANY_FRAMES_LOSS; + McpsIndication.DownLinkCounter = downLinkCounter; + PrepareRxDoneAbort( ); + return; + } + + if ( isMicOk == true ) { + McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_OK; + McpsIndication.Multicast = multicast; + McpsIndication.FramePending = fCtrl.Bits.FPending; + McpsIndication.Buffer = NULL; + McpsIndication.BufferSize = 0; + McpsIndication.DownLinkCounter = downLinkCounter; + McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_OK; + + AdrAckCounter = 0; + MacCommandsBufferToRepeatIndex = 0; + + // Update 32 bits downlink counter + if ( multicast == 1 ) { + McpsIndication.McpsIndication = MCPS_MULTICAST; + + if ( ( curMulticastParams->DownLinkCounter == downLinkCounter ) && + ( curMulticastParams->DownLinkCounter != 0 ) ) { + McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_DOWNLINK_REPEATED; + McpsIndication.DownLinkCounter = downLinkCounter; + PrepareRxDoneAbort( ); + return; + } + curMulticastParams->DownLinkCounter = downLinkCounter; + } else { + if ( macHdr.Bits.MType == FRAME_TYPE_DATA_CONFIRMED_DOWN ) { + SrvAckRequested = true; + McpsIndication.McpsIndication = MCPS_CONFIRMED; + + if ( ( DownLinkCounter == downLinkCounter ) && + ( DownLinkCounter != 0 ) ) { + // Duplicated confirmed downlink. Skip indication. + // In this case, the MAC layer shall accept the MAC commands + // which are included in the downlink retransmission. + // It should not provide the same frame to the application + // layer again. + LoRaMacFlags.Bits.McpsIndSkip = 1; + } + } else { + SrvAckRequested = false; + McpsIndication.McpsIndication = MCPS_UNCONFIRMED; + + if ( ( DownLinkCounter == downLinkCounter ) && + ( DownLinkCounter != 0 ) ) { + McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_DOWNLINK_REPEATED; + McpsIndication.DownLinkCounter = downLinkCounter; + PrepareRxDoneAbort( ); + return; + } + } + DownLinkCounter = downLinkCounter; + } + + // This must be done before parsing the payload and the MAC commands. + // We need to reset the MacCommandsBufferIndex here, since we need + // to take retransmissions and repetitions into account. Error cases + // will be handled in function OnMacStateCheckTimerEvent. + if ( McpsConfirm.McpsRequest == MCPS_CONFIRMED ) { + if ( fCtrl.Bits.Ack == 1 ) { + // Reset MacCommandsBufferIndex when we have received an ACK. + MacCommandsBufferIndex = 0; + // Update acknowledgement information + McpsConfirm.AckReceived = fCtrl.Bits.Ack; + McpsIndication.AckReceived = fCtrl.Bits.Ack; + } + } else { + // Reset the variable if we have received any valid frame. + MacCommandsBufferIndex = 0; + } + port = payload[appPayloadStartIndex]; + // Process payload and MAC commands + if ( ( ( size - 4 ) - appPayloadStartIndex ) > 0 ) { + port = payload[appPayloadStartIndex++]; + frameLen = ( size - 4 ) - appPayloadStartIndex; + + McpsIndication.Port = port; + if ( port == 0 ) { + // Only allow frames which do not have fOpts + if( ( fCtrl.Bits.FOptsLen == 0 ) && ( multicast == 0 ) ) { + LoRaMacPayloadDecrypt( payload + appPayloadStartIndex, + frameLen, + nwkSKey, + address, + DOWN_LINK, + downLinkCounter, + LoRaMacRxPayload ); + // Decode frame payload MAC commands + ProcessMacCommands( LoRaMacRxPayload, 0, frameLen, snr, McpsIndication.RxSlot ); + } else { + LoRaMacFlags.Bits.McpsIndSkip = 1; + // This is not a valid frame. Drop it and reset the ACK bits + McpsConfirm.AckReceived = false; + McpsIndication.AckReceived = false; + #ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) + PRINTF_RAW("CMD exist at FRMpayload and Fopts, ignore it\r\n"); + #endif + } + } else { + if( ( fCtrl.Bits.FOptsLen > 0 ) && ( multicast == 0 ) ){ + // Decode Options field MAC commands. Omit the fPort. + ProcessMacCommands( payload, 8, appPayloadStartIndex - 1, snr, McpsIndication.RxSlot ); + } + + LoRaMacPayloadDecrypt( payload + appPayloadStartIndex, + frameLen, + appSKey, + address, + DOWN_LINK, + downLinkCounter, + LoRaMacRxPayload ); + + McpsIndication.Buffer = LoRaMacRxPayload; + McpsIndication.BufferSize = frameLen; + McpsIndication.RxData = true; + } + } else { + if ( fCtrl.Bits.FOptsLen > 0 ) { + // Decode Options field MAC commands + ProcessMacCommands( payload, 8, appPayloadStartIndex, snr , McpsIndication.RxSlot); + } + } + + // Provide always an indication, skip the callback to the user application, + // in case of a confirmed downlink retransmission. + LoRaMacFlags.Bits.McpsInd = 1; + } else { +#ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) { + PRINTF_RAW("MIC verify failed ignore the frame\r\n"); + } +#endif + McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_MIC_FAIL; + + PrepareRxDoneAbort( ); + return; + } + } + break; + case FRAME_TYPE_PROPRIETARY: { + memcpy1( LoRaMacRxPayload, &payload[pktHeaderLen], size ); + + McpsIndication.McpsIndication = MCPS_PROPRIETARY; + McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_OK; + McpsIndication.Buffer = LoRaMacRxPayload; + McpsIndication.BufferSize = size - pktHeaderLen; + + LoRaMacFlags.Bits.McpsInd = 1; + break; + } + default: +#ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) + PRINTF_RAW("Download frame %d being received but not process it\r\n", macHdr.Bits.MType); +#endif + McpsIndication.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + PrepareRxDoneAbort( ); + break; + } + // Verify if we need to disable the AckTimeoutTimer + CheckToDisableAckTimeout( NodeAckRequested, LoRaMacDeviceClass, McpsConfirm.AckReceived, + AckTimeoutRetriesCounter, AckTimeoutRetries ); + if( AckTimeoutTimer.IsRunning == false ) + {// Procedure is completed when the AckTimeoutTimer is not running anymore + LoRaMacFlags.Bits.MacDone = 1; + + // Trig OnMacCheckTimerEvent call as soon as possible + TimerSetValue( &MacStateCheckTimer, 1 ); + TimerStart( &MacStateCheckTimer ); + } +} + +static void OnRadioTxTimeout( void ) +{ +#if (LoraWan_RGB==1) + RGB_OFF(); +#endif + + if( LoRaMacDeviceClass != CLASS_C ) + { + Radio.Sleep( ); + } + else + { + OpenContinuousRx2Window( ); + } + + McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_TX_TIMEOUT; + LoRaMacConfirmQueueSetStatusCmn( LORAMAC_EVENT_INFO_STATUS_TX_TIMEOUT ); + LoRaMacFlags.Bits.MacDone = 1; +#ifdef CONFIG_LWAN + lwan_dev_status_set(DEVICE_STATUS_SEND_FAIL); +#endif +} + +static void OnRadioRxError( void ) +{ + bool classBRx = false; + + if( LoRaMacDeviceClass != CLASS_C ) + { + Radio.Sleep( ); + } + + if( LoRaMacClassBIsBeaconExpected( ) == true ) + { + LoRaMacClassBSetBeaconState( BEACON_STATE_TIMEOUT ); + LoRaMacClassBBeaconTimerEvent( ); + classBRx = true; + } + if( LoRaMacDeviceClass == CLASS_B ) + { + if( LoRaMacClassBIsPingExpected( ) == true ) + { + LoRaMacClassBSetPingSlotState( PINGSLOT_STATE_SET_TIMER ); + LoRaMacClassBPingSlotTimerEvent( ); + classBRx = true; + } + if( LoRaMacClassBIsMulticastExpected( ) == true ) + { + LoRaMacClassBSetMulticastSlotState( PINGSLOT_STATE_SET_TIMER ); + LoRaMacClassBMulticastSlotTimerEvent( ); + classBRx = true; + } + } + + if( classBRx == false ) + { + if( RxSlot == RX_SLOT_WIN_1 ) + { + if( NodeAckRequested == true ) + { + McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX1_ERROR; + } + LoRaMacConfirmQueueSetStatusCmn( LORAMAC_EVENT_INFO_STATUS_RX1_ERROR ); + + if( LoRaMacDeviceClass != CLASS_C ) + { + if( TimerGetElapsedTime( AggregatedLastTxDoneTime ) >= RxWindow2Delay ) + { + TimerStop( &RxWindowTimer2 ); + LoRaMacFlags.Bits.MacDone = 1; + } + } + } + else + { + if( NodeAckRequested == true ) + { + McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX2_ERROR; + } + LoRaMacConfirmQueueSetStatusCmn( LORAMAC_EVENT_INFO_STATUS_RX2_ERROR ); + + if( LoRaMacDeviceClass != CLASS_C ) + { + LoRaMacFlags.Bits.MacDone = 1; + } + } + } + + if( LoRaMacDeviceClass == CLASS_C ) + { + OpenContinuousRx2Window( ); + } +} + +static void OnRadioRxTimeout( void ) +{ +#if (LoraWan_RGB==1) + RGB_OFF(); +#endif + bool classBRx = false; + + if( LoRaMacDeviceClass != CLASS_C ) + { + Radio.Sleep( ); + } + + if( LoRaMacClassBIsBeaconExpected( ) == true ) + { + LoRaMacClassBSetBeaconState( BEACON_STATE_TIMEOUT ); + LoRaMacClassBBeaconTimerEvent( ); + classBRx = true; + } + if( LoRaMacDeviceClass == CLASS_B ) + { + if( LoRaMacClassBIsPingExpected( ) == true ) + { + LoRaMacClassBSetPingSlotState( PINGSLOT_STATE_SET_TIMER ); + LoRaMacClassBPingSlotTimerEvent( ); + classBRx = true; + } + if( LoRaMacClassBIsMulticastExpected( ) == true ) + { + LoRaMacClassBSetMulticastSlotState( PINGSLOT_STATE_SET_TIMER ); + LoRaMacClassBMulticastSlotTimerEvent( ); + classBRx = true; + } + } + + if( classBRx == false ) + { + if( RxSlot == RX_SLOT_WIN_1 ) + { + if( NodeAckRequested == true ) + { + McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX1_TIMEOUT; + } + LoRaMacConfirmQueueSetStatusCmn( LORAMAC_EVENT_INFO_STATUS_RX1_TIMEOUT ); + + if( LoRaMacDeviceClass != CLASS_C ) + { + if( TimerGetElapsedTime( AggregatedLastTxDoneTime ) >= RxWindow2Delay ) + { + TimerStop( &RxWindowTimer2 ); + LoRaMacFlags.Bits.MacDone = 1; + } + } + } + else + { + if( NodeAckRequested == true ) + { + McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_RX2_TIMEOUT; + } + LoRaMacConfirmQueueSetStatusCmn( LORAMAC_EVENT_INFO_STATUS_RX2_TIMEOUT ); + + if( LoRaMacDeviceClass != CLASS_C ) + { + LoRaMacFlags.Bits.MacDone = 1; + } + } + } + + if( LoRaMacDeviceClass == CLASS_C ) + { + OpenContinuousRx2Window( ); + } +} + +#ifdef CONFIG_LORA_CAD +static void OnRadioCadDone( bool channelActivityDetected ) +{ + Radio.Sleep( ); + + if(channelActivityDetected && g_lora_cad_cnt= MaxJoinRequestTrials ) { + LoRaMacState &= ~LORAMAC_TX_RUNNING; + } else { + LoRaMacFlags.Bits.MacDone = 0; + // Sends the same frame again + OnTxDelayedTimerEvent( ); + } + } + } else { + // Procedure for all other frames + if ( ( ChannelsNbRepCounter >= LoRaMacParams.ChannelsNbRep ) || ( LoRaMacFlags.Bits.McpsInd == 1 ) ) { + if ( LoRaMacFlags.Bits.McpsInd == 0 ) { + // Maximum repetitions without downlink. Reset MacCommandsBufferIndex. Increase ADR Ack counter. + // Only process the case when the MAC did not receive a downlink. + MacCommandsBufferIndex = 0; + AdrAckCounter++; + } + + ChannelsNbRepCounter = 0; + + if ( IsUpLinkCounterFixed == false ) { + UpLinkCounter++; + #ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) + PRINTF_RAW("Unconfirmed data, UpLinkCounter:%u\r\n", (unsigned int)UpLinkCounter); + #endif + } + + LoRaMacState &= ~LORAMAC_TX_RUNNING; + } else { + LoRaMacFlags.Bits.MacDone = 0; + // Sends the same frame again + OnTxDelayedTimerEvent( ); + } + } + } + } + + if ( LoRaMacFlags.Bits.McpsInd == 1 ) { + // Procedure if we received a frame + if ( ( McpsConfirm.AckReceived == true ) || ( AckTimeoutRetriesCounter > AckTimeoutRetries ) ) { + AckTimeoutRetry = false; + NodeAckRequested = false; + if ( IsUpLinkCounterFixed == false ) { + UpLinkCounter++; + #ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) + PRINTF_RAW("Confirmed data received ACK, UpLinkCounter:%u\r\n", (unsigned int)UpLinkCounter); + #endif + } + McpsConfirm.NbRetries = AckTimeoutRetriesCounter; + + LoRaMacState &= ~LORAMAC_TX_RUNNING; + } +#ifdef CONFIG_LWAN + } else { + if ( !(( LoRaMacFlags.Bits.MlmeReq == 1 ) && ( MlmeConfirm.MlmeRequest == MLME_JOIN )) ) + lwan_dev_status_set(DEVICE_STATUS_SEND_PASS_WITHOUT_DL); + } +#else + } +#endif + if ( ( AckTimeoutRetry == true ) && ( ( LoRaMacState & LORAMAC_TX_DELAYED ) == 0 ) ) { + //printf("Counter %d %d %d\r\n",AckTimeoutRetriesCounter,AckTimeoutRetries,AckTimeoutRetry); + // Retransmissions procedure for confirmed uplinks + AckTimeoutRetry = false; + if ( ( AckTimeoutRetriesCounter < AckTimeoutRetries ) && ( AckTimeoutRetriesCounter <= MAX_ACK_RETRIES ) ) { + AckTimeoutRetriesCounter++; + // printf("Counter3 %d %d %d\r\n",AckTimeoutRetriesCounter,AckTimeoutRetries,AckTimeoutRetry); + + if ( ( AckTimeoutRetriesCounter % 2 ) == 1 ) { + getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + getPhy.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + getPhy.Datarate = LoRaMacParams.ChannelsDatarate; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParams.ChannelsDatarate = phyParam.Value; + } + // Try to send the frame again + if ( ScheduleTx( ) == LORAMAC_STATUS_OK ) { + LoRaMacFlags.Bits.MacDone = 0; + } else { + // The DR is not applicable for the payload size + McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_TX_DR_PAYLOAD_SIZE_ERROR; + + MacCommandsBufferIndex = 0; + LoRaMacState &= ~LORAMAC_TX_RUNNING; + NodeAckRequested = false; + McpsConfirm.AckReceived = false; + McpsConfirm.NbRetries = AckTimeoutRetriesCounter; + McpsConfirm.Datarate = LoRaMacParams.ChannelsDatarate; + if ( IsUpLinkCounterFixed == false ) { + UpLinkCounter++; + #ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) + PRINTF_RAW("Confirmed data can't send after decrease DR, UpLinkCounter:%u\r\n", (unsigned int)UpLinkCounter); + #endif + } + } + } else { + RegionInitDefaults( LoRaMacRegion, INIT_TYPE_RESTORE ); + + LoRaMacState &= ~LORAMAC_TX_RUNNING; + + MacCommandsBufferIndex = 0; + NodeAckRequested = false; + McpsConfirm.AckReceived = false; + McpsConfirm.NbRetries = AckTimeoutRetriesCounter; + if ( IsUpLinkCounterFixed == false ) { + UpLinkCounter++; + #ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) + PRINTF_RAW("Confirmed data exceed retry times, UpLinkCounter:%u\r\n", (unsigned int)UpLinkCounter); + #endif + } + } + } + } + + // Handle events + if( LoRaMacState == LORAMAC_IDLE ) + { + if( LoRaMacFlags.Bits.McpsReq == 1 ) + { + LoRaMacFlags.Bits.McpsReq = 0; + LoRaMacPrimitives->MacMcpsConfirm( &McpsConfirm ); + } + + if( LoRaMacFlags.Bits.MlmeReq == 1 ) + { + LoRaMacFlags.Bits.MlmeReq = 0; + LoRaMacConfirmQueueHandleCb( &MlmeConfirm ); + if( LoRaMacConfirmQueueGetCnt( ) > 0 ) + { + LoRaMacFlags.Bits.MlmeReq = 1; + } + } + + // Handle MLME indication + if( LoRaMacFlags.Bits.MlmeInd == 1 ) + { + LoRaMacPrimitives->MacMlmeIndication( &MlmeIndication ); + LoRaMacFlags.Bits.MlmeInd = 0; + +#ifdef CONFIG_LWAN + if(MlmeIndication.MlmeIndication == MLME_SCHEDULE_UPLINK) { + McpsIndication.UplinkNeeded = false; + } +#endif + } + + // Verify if sticky MAC commands are pending or not + if( IsStickyMacCommandPending( ) == true ) + {// Setup MLME indication + SetMlmeScheduleUplinkIndication( ); + LoRaMacPrimitives->MacMlmeIndication( &MlmeIndication ); + LoRaMacFlags.Bits.MlmeInd = 0; +#ifdef CONFIG_LWAN + if(MlmeIndication.MlmeIndication == MLME_SCHEDULE_UPLINK) { + McpsIndication.UplinkNeeded = false; + } +#endif + } + + // Procedure done. Reset variables. + LoRaMacFlags.Bits.MacDone = 0; + + LoRaMacClassBResumeBeaconing( ); + } + else + { + // Operation not finished restart timer + TimerSetValue( &MacStateCheckTimer, MAC_STATE_CHECK_TIMEOUT ); + TimerStart( &MacStateCheckTimer ); + } + + // Handle MCPS indication + if( LoRaMacFlags.Bits.McpsInd == 1 ) + { + LoRaMacFlags.Bits.McpsInd = 0; + if( LoRaMacDeviceClass == CLASS_C ) + {// Activate RX2 window for Class C + OpenContinuousRx2Window( ); + } + if( LoRaMacFlags.Bits.McpsIndSkip == 0 ) + { + LoRaMacPrimitives->MacMcpsIndication( &McpsIndication ); + } + LoRaMacFlags.Bits.McpsIndSkip = 0; + } + +} + +static void OnTxDelayedTimerEvent( void ) +{ + LoRaMacHeader_t macHdr; + LoRaMacFrameCtrl_t fCtrl; + AlternateDrParams_t altDr; + + TimerStop( &TxDelayedTimer ); + LoRaMacState &= ~LORAMAC_TX_DELAYED; + + if ( ( LoRaMacFlags.Bits.MlmeReq == 1 ) && ( MlmeConfirm.MlmeRequest == MLME_JOIN ) ) { + ResetMacParameters( ); + + altDr.NbTrials = JoinRequestTrials + 1; +#ifdef CONFIG_LINKWAN + altDr.joinmethod = LoRaMacParams.method; + altDr.datarate = LoRaMacParams.ChannelsDatarate; +#endif + LoRaMacParams.ChannelsDatarate = RegionAlternateDr( LoRaMacRegion, &altDr ); + + macHdr.Value = 0; + macHdr.Bits.MType = FRAME_TYPE_JOIN_REQ; + + fCtrl.Value = 0; + fCtrl.Bits.Adr = AdrCtrlOn; + + /* In case of join request retransmissions, the stack must prepare + * the frame again, because the network server keeps track of the random + * LoRaMacDevNonce values to prevent reply attacks. */ + PrepareFrame( &macHdr, &fCtrl, 0, NULL, 0 ); + } + + ScheduleTx( ); +} + +#ifdef CONFIG_LORA_CAD +static void OnTxImmediateTimerEvent( void ) +{ + TimerStop( &TxImmediateTimer ); + SendFrameOnChannel( Channel ); +} +#endif + +static void OnRxWindow1TimerEvent( void ) +{ + TimerStop( &RxWindowTimer1 ); + RxSlot = RX_SLOT_WIN_1; + + RxWindow1Config.Channel = Channel; + RxWindow1Config.DrOffset = LoRaMacParams.Rx1DrOffset; + RxWindow1Config.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; + RxWindow1Config.RepeaterSupport = LoRaMacParams.RepeaterSupport; + RxWindow1Config.RxContinuous = false; + RxWindow1Config.RxSlot = RxSlot; + + if ( LoRaMacDeviceClass == CLASS_C ) { + Radio.Standby( ); + } + + RegionRxConfig( LoRaMacRegion, &RxWindow1Config, ( int8_t * )&McpsIndication.RxDatarate ); + //printf("w1 dr:%d\r\n",McpsIndication.RxDatarate); + RxWindowSetup( RxWindow1Config.RxContinuous, LoRaMacParams.MaxRxWindow ); +#if(LoraWan_RGB==1) + RGB_ON(COLOR_RXWINDOW1,0); +#endif +} + +static void OnRxWindow2TimerEvent( void ) +{ + TimerStop( &RxWindowTimer2 ); + + RxWindow2Config.Channel = Channel; + RxWindow2Config.Frequency = LoRaMacParams.Rx2Channel.Frequency; + RxWindow2Config.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; + RxWindow2Config.RepeaterSupport = LoRaMacParams.RepeaterSupport; + RxWindow2Config.RxSlot = RX_SLOT_WIN_2; + + if ( LoRaMacDeviceClass != CLASS_C ) { + RxWindow2Config.RxContinuous = false; + } else { + RxWindow2Config.RxContinuous = true; + } + + if ( RegionRxConfig( LoRaMacRegion, &RxWindow2Config, ( int8_t * )&McpsIndication.RxDatarate ) == true ) { + //printf("w2 dr:%d\r\n",McpsIndication.RxDatarate); + RxWindowSetup( RxWindow2Config.RxContinuous, LoRaMacParams.MaxRxWindow ); + RxSlot = RX_SLOT_WIN_2; + } +#if(LoraWan_RGB==1) + RGB_ON(COLOR_RXWINDOW2,0); +#endif + +} + +static void CheckToDisableAckTimeout( bool nodeAckRequested, DeviceClass_t devClass, bool ackReceived, + uint8_t ackTimeoutRetriesCounter, uint8_t ackTimeoutRetries ) +{ + // There are three cases where we need to stop the AckTimeoutTimer: + if( nodeAckRequested == false ) + { + if( devClass == CLASS_C ) + {// FIRST CASE + // We have performed an unconfirmed uplink in class c mode + // and have received a downlink in RX1 or RX2. + TimerStop( &AckTimeoutTimer ); + } + } + else + { + if( ackReceived == 1 ) + {// SECOND CASE + // We have performed a confirmed uplink and have received a + // downlink with a valid ACK. + TimerStop( &AckTimeoutTimer ); + } + else + {// THIRD CASE + if( ackTimeoutRetriesCounter > ackTimeoutRetries ) + { + // We have performed a confirmed uplink and have not + // received a downlink with a valid ACK. In this case + // we need to verify if the maximum retries have been + // elapsed. If so, stop the timer. + TimerStop( &AckTimeoutTimer ); + } + } + } +} + +static void OnAckTimeoutTimerEvent( void ) +{ + TimerStop( &AckTimeoutTimer ); + + if ( NodeAckRequested == true ) { + AckTimeoutRetry = true; + LoRaMacState &= ~LORAMAC_ACK_REQ; + } + if ( LoRaMacDeviceClass == CLASS_C ) { + LoRaMacFlags.Bits.MacDone = 1; + } +} + +static void RxWindowSetup( bool rxContinuous, uint32_t maxRxWindow ) +{ + if ( rxContinuous == false ) { + Radio.Rx( maxRxWindow ); + } else { + Radio.Rx( 0 ); // Continuous mode + } +} + +static LoRaMacStatus_t SwitchClass( DeviceClass_t deviceClass ) +{ + LoRaMacStatus_t status = LORAMAC_STATUS_PARAMETER_INVALID; + + switch( LoRaMacDeviceClass ) + { + case CLASS_A: + { + if( deviceClass == CLASS_B ) + { + status = LoRaMacClassBSwitchClass( deviceClass ); + if( status == LORAMAC_STATUS_OK ) + { + LoRaMacDeviceClass = deviceClass; + } + } + + if( deviceClass == CLASS_C ) + { + LoRaMacDeviceClass = deviceClass; + + // Set the NodeAckRequested indicator to default + NodeAckRequested = false; + // Set the radio into sleep mode in case we are still in RX mode + Radio.Sleep( ); + // Compute Rx2 windows parameters in case the RX2 datarate has changed + RegionComputeRxWindowParameters( LoRaMacRegion, + LoRaMacParams.Rx2Channel.Datarate, + LoRaMacParams.MinRxSymbols, + LoRaMacParams.SystemMaxRxError, + &RxWindow2Config ); + OpenContinuousRx2Window( ); + + + status = LORAMAC_STATUS_OK; + } + break; + } + case CLASS_B: + { + status = LoRaMacClassBSwitchClass( deviceClass ); + if( status == LORAMAC_STATUS_OK ) + { + LoRaMacDeviceClass = deviceClass; + } + break; + } + case CLASS_C: + { + if( deviceClass == CLASS_A ) + { + LoRaMacDeviceClass = deviceClass; + + // Set the radio into sleep to setup a defined state + Radio.Sleep( ); + + status = LORAMAC_STATUS_OK; + } + break; + } + } + + return status; +} + +static bool ValidatePayloadLength( uint8_t lenN, int8_t datarate, uint8_t fOptsLen ) +{ + GetPhyParams_t getPhy; + PhyParam_t phyParam; + uint16_t maxN = 0; + uint16_t payloadSize = 0; + + // Setup PHY request + getPhy.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + getPhy.Datarate = datarate; + getPhy.Attribute = PHY_MAX_PAYLOAD; + + // Get the maximum payload length + if( LoRaMacParams.RepeaterSupport == true ) + { + getPhy.Attribute = PHY_MAX_PAYLOAD_REPEATER; + } + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + maxN = phyParam.Value; + + // Calculate the resulting payload size + payloadSize = ( lenN + fOptsLen ); + + // Validation of the application payload size + if ( ((( payloadSize > maxN ) && (fOptsLen != 0) && (fOptsLen <= maxN)) || ( payloadSize <= maxN )) && ( payloadSize <= LORAMAC_PHY_MAXPAYLOAD ) ) { + return true; + } + return false; +} + +static bool IsStickyMacCommandPending( void ) +{ + if( MacCommandsBufferToRepeatIndex > 0 ) + { + // Sticky MAC commands pending + return true; + } + return false; +} + +static void SetMlmeScheduleUplinkIndication( void ) +{ + MlmeIndication.MlmeIndication = MLME_SCHEDULE_UPLINK; + LoRaMacFlags.Bits.MlmeInd = 1; +} + +static LoRaMacStatus_t AddMacCommand( uint8_t cmd, uint8_t p1, uint8_t p2 ) +{ + LoRaMacStatus_t status = LORAMAC_STATUS_BUSY; + // The maximum buffer length must take MAC commands to re-send into account. + uint8_t bufLen = LORA_MAC_COMMAND_MAX_LENGTH - MacCommandsBufferToRepeatIndex; + + switch ( cmd ) { + case MOTE_MAC_LINK_CHECK_REQ: + if ( MacCommandsBufferIndex < bufLen ) { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // No payload for this command + status = LORAMAC_STATUS_OK; + } + break; + case MOTE_MAC_LINK_ADR_ANS: + if ( MacCommandsBufferIndex < ( bufLen - 1 ) ) { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // Margin + MacCommandsBuffer[MacCommandsBufferIndex++] = p1; + status = LORAMAC_STATUS_OK; + } + break; + case MOTE_MAC_DUTY_CYCLE_ANS: + if ( MacCommandsBufferIndex < bufLen ) { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // No payload for this answer + status = LORAMAC_STATUS_OK; + } + break; + case MOTE_MAC_RX_PARAM_SETUP_ANS: + if ( MacCommandsBufferIndex < ( bufLen - 1 ) ) { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // Status: Datarate ACK, Channel ACK + MacCommandsBuffer[MacCommandsBufferIndex++] = p1; + // This is a sticky MAC command answer. Setup indication + SetMlmeScheduleUplinkIndication( ); + status = LORAMAC_STATUS_OK; + } + break; + case MOTE_MAC_DEV_STATUS_ANS: + if ( MacCommandsBufferIndex < ( bufLen - 2 ) ) { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // 1st byte Battery + // 2nd byte Margin + MacCommandsBuffer[MacCommandsBufferIndex++] = p1; + MacCommandsBuffer[MacCommandsBufferIndex++] = p2; + SetMlmeScheduleUplinkIndication( ); + status = LORAMAC_STATUS_OK; +#ifdef LORAMAC_CLASSB_TESTCASE + DBG_PRINTF("ready to send MOTE_MAC_DEV_STATUS_ANS p1=%d p2=%d\r\n",p1,p2); +#endif + } + break; + case MOTE_MAC_NEW_CHANNEL_ANS: + if ( MacCommandsBufferIndex < ( bufLen - 1 ) ) { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // Status: Datarate range OK, Channel frequency OK + MacCommandsBuffer[MacCommandsBufferIndex++] = p1; + status = LORAMAC_STATUS_OK; + } + break; + case MOTE_MAC_RX_TIMING_SETUP_ANS: + if ( MacCommandsBufferIndex < bufLen ) { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // No payload for this answer + // This is a sticky MAC command answer. Setup indication + SetMlmeScheduleUplinkIndication( ); + status = LORAMAC_STATUS_OK; + } + break; + case MOTE_MAC_TX_PARAM_SETUP_ANS: + if ( MacCommandsBufferIndex < bufLen ) { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // No payload for this answer + status = LORAMAC_STATUS_OK; + } + break; + case MOTE_MAC_DL_CHANNEL_ANS: + if ( MacCommandsBufferIndex < bufLen ) { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // Status: Uplink frequency exists, Channel frequency OK + MacCommandsBuffer[MacCommandsBufferIndex++] = p1; + // This is a sticky MAC command answer. Setup indication + SetMlmeScheduleUplinkIndication( ); + + status = LORAMAC_STATUS_OK; + } + break; + case MOTE_MAC_DEVICE_TIME_REQ: + if( MacCommandsBufferIndex < LORA_MAC_COMMAND_MAX_LENGTH ) + { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // No payload for this answer + status = LORAMAC_STATUS_OK; +#ifdef LORAMAC_CLASSB_TESTCASE + DBG_PRINTF("ready to send MOTE_MAC_DEVICE_TIME_REQ\r\n"); +#endif + } + break; + case MOTE_MAC_PING_SLOT_INFO_REQ: + if( MacCommandsBufferIndex < ( LORA_MAC_COMMAND_MAX_LENGTH - 1 ) ) + { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // Status: Periodicity and Datarate + MacCommandsBuffer[MacCommandsBufferIndex++] = p1; + status = LORAMAC_STATUS_OK; +#ifdef LORAMAC_CLASSB_TESTCASE + DBG_PRINTF("ready to send MOTE_MAC_PING_SLOT_INFO_REQ value=%d\r\n",p1); +#endif + } + break; + case MOTE_MAC_PING_SLOT_FREQ_ANS: + if( MacCommandsBufferIndex < LORA_MAC_COMMAND_MAX_LENGTH ) + { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // Status: Datarate range OK, Channel frequency OK + MacCommandsBuffer[MacCommandsBufferIndex++] = p1; + SetMlmeScheduleUplinkIndication( ); + status = LORAMAC_STATUS_OK; + } + break; + case MOTE_MAC_BEACON_TIMING_REQ: + if( MacCommandsBufferIndex < LORA_MAC_COMMAND_MAX_LENGTH ) + { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // No payload for this answer + status = LORAMAC_STATUS_OK; + } + break; + case MOTE_MAC_BEACON_FREQ_ANS: + if( MacCommandsBufferIndex < LORA_MAC_COMMAND_MAX_LENGTH ) + { + MacCommandsBuffer[MacCommandsBufferIndex++] = cmd; + // Status: Channel frequency OK + MacCommandsBuffer[MacCommandsBufferIndex++] = p1; + SetMlmeScheduleUplinkIndication( ); + status = LORAMAC_STATUS_OK; + } + break; + default: + return LORAMAC_STATUS_SERVICE_UNKNOWN; + } + if ( status == LORAMAC_STATUS_OK ) { + MacCommandsInNextTx = true; + if (SrvAckRequested) { + SetMlmeScheduleUplinkIndication(); + } + } + return status; +} + +static uint8_t ParseMacCommandsToRepeat( uint8_t *cmdBufIn, uint8_t length, uint8_t *cmdBufOut ) +{ + uint8_t i = 0; + uint8_t cmdCount = 0; + + if ( ( cmdBufIn == NULL ) || ( cmdBufOut == NULL ) ) { + return 0; + } + + for ( i = 0; i < length; i++ ) { + switch ( cmdBufIn[i] ) { + // STICKY + case MOTE_MAC_DL_CHANNEL_ANS: + case MOTE_MAC_RX_PARAM_SETUP_ANS: { + // 1 byte payload + cmdBufOut[cmdCount++] = cmdBufIn[i++]; + cmdBufOut[cmdCount++] = cmdBufIn[i]; + break; + } + case MOTE_MAC_RX_TIMING_SETUP_ANS: { + // 0 byte payload + cmdBufOut[cmdCount++] = cmdBufIn[i]; + break; + } + // NON-STICKY + case MOTE_MAC_DEV_STATUS_ANS: { + // 2 bytes payload + i += 2; + break; + } + case MOTE_MAC_LINK_ADR_ANS: + case MOTE_MAC_NEW_CHANNEL_ANS: { + // 1 byte payload + i++; + break; + } + case MOTE_MAC_TX_PARAM_SETUP_ANS: + case MOTE_MAC_DUTY_CYCLE_ANS: + case MOTE_MAC_LINK_CHECK_REQ: { + // 0 byte payload + break; + } + default: + break; + } + } + + return cmdCount; +} + +static void ProcessMacCommands( uint8_t *payload, uint8_t macIndex, uint8_t commandsSize, uint8_t snr, LoRaMacRxSlot_t rxSlot ) +{ + uint8_t status = 0; + while ( macIndex < commandsSize ) { + // Decode Frame MAC commands +#ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) { + PRINTF_RAW("MacCommands:%d being processed\r\n", payload[macIndex]); + } +#endif + switch ( payload[macIndex++] ) { + case SRV_MAC_LINK_CHECK_ANS: + if( LoRaMacConfirmQueueIsCmdActive( MLME_LINK_CHECK ) == true ) + { + LoRaMacConfirmQueueSetStatus( LORAMAC_EVENT_INFO_STATUS_OK, MLME_LINK_CHECK ); + MlmeConfirm.DemodMargin = payload[macIndex++]; + MlmeConfirm.NbGateways = payload[macIndex++]; +#ifdef CONFIG_LWAN + McpsIndication.LinkCheckAnsReceived = true; +#endif + DBG_PRINTF("margin %d, gateways %d\r\n", MlmeConfirm.DemodMargin, MlmeConfirm.NbGateways); + } + break; + case SRV_MAC_LINK_ADR_REQ: { + LinkAdrReqParams_t linkAdrReq; + int8_t linkAdrDatarate = DR_0; + int8_t linkAdrTxPower = TX_POWER_0; + uint8_t linkAdrNbRep = 0; + uint8_t linkAdrNbBytesParsed = 0; + + // Fill parameter structure + linkAdrReq.Payload = &payload[macIndex - 1]; + linkAdrReq.PayloadSize = commandsSize - ( macIndex - 1 ); + linkAdrReq.AdrEnabled = AdrCtrlOn; + linkAdrReq.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + linkAdrReq.CurrentDatarate = LoRaMacParams.ChannelsDatarate; + linkAdrReq.CurrentTxPower = LoRaMacParams.ChannelsTxPower; + linkAdrReq.CurrentNbRep = LoRaMacParams.ChannelsNbRep; + // Process the ADR requests + status = RegionLinkAdrReq( LoRaMacRegion, &linkAdrReq, &linkAdrDatarate, + &linkAdrTxPower, &linkAdrNbRep, &linkAdrNbBytesParsed ); + //printf("status:%d\r\n",status); + if ( ( status & 0x07 ) == 0x07 ) { + LoRaMacParams.ChannelsDatarate = linkAdrDatarate; + LoRaMacParams.ChannelsTxPower = linkAdrTxPower; + LoRaMacParams.ChannelsNbRep = linkAdrNbRep; + //printf("ChannelsDatarate:%d ChannelsTxPower:%d,ChannelsNbRep:%d\r\n",LoRaMacParams.ChannelsDatarate,LoRaMacParams.ChannelsTxPower,LoRaMacParams.ChannelsNbRep); + } + + // Add the answers to the buffer + for ( uint8_t i = 0; i < ( linkAdrNbBytesParsed / 5 ); i++ ) { + AddMacCommand( MOTE_MAC_LINK_ADR_ANS, status, 0 ); + } + // Update MAC index + macIndex += linkAdrNbBytesParsed - 1; + } + break; + case SRV_MAC_DUTY_CYCLE_REQ: + MaxDCycle = payload[macIndex++]; + AggregatedDCycle = 1 << MaxDCycle; + AddMacCommand( MOTE_MAC_DUTY_CYCLE_ANS, 0, 0 ); + break; + case SRV_MAC_RX_PARAM_SETUP_REQ: { + RxParamSetupReqParams_t rxParamSetupReq; + status = 0x07; + + rxParamSetupReq.DrOffset = ( payload[macIndex] >> 4 ) & 0x07; + rxParamSetupReq.Datarate = payload[macIndex] & 0x0F; + macIndex++; + + rxParamSetupReq.Frequency = ( uint32_t )payload[macIndex++]; + rxParamSetupReq.Frequency |= ( uint32_t )payload[macIndex++] << 8; + rxParamSetupReq.Frequency |= ( uint32_t )payload[macIndex++] << 16; + rxParamSetupReq.Frequency *= 100; + + // Perform request on region + status = RegionRxParamSetupReq( LoRaMacRegion, &rxParamSetupReq ); + + if ( ( status & 0x07 ) == 0x07 ) { + LoRaMacParams.Rx2Channel.Datarate = rxParamSetupReq.Datarate; + LoRaMacParams.Rx2Channel.Frequency = rxParamSetupReq.Frequency; + LoRaMacParams.Rx1DrOffset = rxParamSetupReq.DrOffset; + } + AddMacCommand( MOTE_MAC_RX_PARAM_SETUP_ANS, status, 0 ); + } + break; + case SRV_MAC_DEV_STATUS_REQ: { + uint8_t batteryLevel = BAT_LEVEL_NO_MEASURE; + if ( ( LoRaMacCallbacks != NULL ) && ( LoRaMacCallbacks->GetBatteryLevel != NULL ) ) { + batteryLevel = LoRaMacCallbacks->GetBatteryLevel( ); + } +#ifdef LORAMAC_CLASSB_TESTCASE + DBG_PRINTF("receive SRV_MAC_DEV_STATUS_REQ\r\n"); +#endif + AddMacCommand( MOTE_MAC_DEV_STATUS_ANS, batteryLevel, snr ); + break; + } + case SRV_MAC_NEW_CHANNEL_REQ: { + NewChannelReqParams_t newChannelReq; + ChannelParams_t chParam; + status = 0x03; + + newChannelReq.ChannelId = payload[macIndex++]; + newChannelReq.NewChannel = &chParam; + + chParam.Frequency = ( uint32_t )payload[macIndex++]; + chParam.Frequency |= ( uint32_t )payload[macIndex++] << 8; + chParam.Frequency |= ( uint32_t )payload[macIndex++] << 16; + chParam.Frequency *= 100; + chParam.Rx1Frequency = 0; + chParam.DrRange.Value = payload[macIndex++]; + + status = RegionNewChannelReq( LoRaMacRegion, &newChannelReq ); + + AddMacCommand( MOTE_MAC_NEW_CHANNEL_ANS, status, 0 ); + } + break; + case SRV_MAC_RX_TIMING_SETUP_REQ: { + uint8_t delay = payload[macIndex++] & 0x0F; + + if ( delay == 0 ) { + delay++; + } + LoRaMacParams.ReceiveDelay1 = delay * 1000; + LoRaMacParams.ReceiveDelay2 = LoRaMacParams.ReceiveDelay1 + 1000; + AddMacCommand( MOTE_MAC_RX_TIMING_SETUP_ANS, 0, 0 ); + } + break; + case SRV_MAC_TX_PARAM_SETUP_REQ: { + TxParamSetupReqParams_t txParamSetupReq; + uint8_t eirpDwellTime = payload[macIndex++]; + + txParamSetupReq.UplinkDwellTime = 0; + txParamSetupReq.DownlinkDwellTime = 0; + + if ( ( eirpDwellTime & 0x20 ) == 0x20 ) { + txParamSetupReq.DownlinkDwellTime = 1; + } + if ( ( eirpDwellTime & 0x10 ) == 0x10 ) { + txParamSetupReq.UplinkDwellTime = 1; + } + txParamSetupReq.MaxEirp = eirpDwellTime & 0x0F; + + // Check the status for correctness + if ( RegionTxParamSetupReq( LoRaMacRegion, &txParamSetupReq ) != -1 ) { + // Accept command + LoRaMacParams.UplinkDwellTime = txParamSetupReq.UplinkDwellTime; + LoRaMacParams.DownlinkDwellTime = txParamSetupReq.DownlinkDwellTime; + LoRaMacParams.MaxEirp = LoRaMacMaxEirpTable[txParamSetupReq.MaxEirp]; + // Add command response + AddMacCommand( MOTE_MAC_TX_PARAM_SETUP_ANS, 0, 0 ); + } + } + break; + case SRV_MAC_DL_CHANNEL_REQ: { + DlChannelReqParams_t dlChannelReq; + status = 0x03; + + dlChannelReq.ChannelId = payload[macIndex++]; + dlChannelReq.Rx1Frequency = ( uint32_t )payload[macIndex++]; + dlChannelReq.Rx1Frequency |= ( uint32_t )payload[macIndex++] << 8; + dlChannelReq.Rx1Frequency |= ( uint32_t )payload[macIndex++] << 16; + dlChannelReq.Rx1Frequency *= 100; + + status = RegionDlChannelReq( LoRaMacRegion, &dlChannelReq ); + + AddMacCommand( MOTE_MAC_DL_CHANNEL_ANS, status, 0 ); + } + break; + case SRV_MAC_DEVICE_TIME_ANS: + { + TimerTime_t currentTime = 0; + TimerSysTime_t sysTimeAns = { 0 }; + TimerSysTime_t sysTime = { 0 }; + TimerSysTime_t sysTimeCurrent = { 0 }; + + sysTimeAns.Seconds = ( uint32_t )payload[macIndex++]; + sysTimeAns.Seconds |= ( uint32_t )payload[macIndex++] << 8; + sysTimeAns.Seconds |= ( uint32_t )payload[macIndex++] << 16; + sysTimeAns.Seconds |= ( uint32_t )payload[macIndex++] << 24; + sysTimeAns.SubSeconds = payload[macIndex++]; + + // Convert the fractional second received in ms + // round( pow( 0.5, 8.0 ) * 1000 ) = 3.90625 + sysTimeAns.SubSeconds = sysTimeAns.SubSeconds * 3.90625; + + // Add Unix to Gps epcoh offset. The system time is based on Unix time. + sysTimeAns.Seconds += UNIX_GPS_EPOCH_OFFSET; + + // Compensate time difference between Tx Done time and now + sysTimeCurrent = TimerGetSysTime( ); + + sysTime = TimerAddSysTime( sysTimeCurrent, TimerSubSysTime( sysTimeAns, LastTxSysTime ) ); +#ifdef LORAMAC_CLASSB_TESTCASE + DBG_PRINTF("receive SRV_MAC_DEVICE_TIME_ANS, set time=%u.%d\r\n", (unsigned int)sysTime.Seconds, sysTime.SubSeconds); +#endif + // Apply the new system time. + TimerSetSysTime( sysTime ); + currentTime = TimerGetCurrentTime( ); + + LoRaMacClassBDeviceTimeAns( currentTime ); +#ifdef CONFIG_LWAN + McpsIndication.DevTimeAnsReceived = true; +#endif + } + break; + case SRV_MAC_PING_SLOT_INFO_ANS: + { + // According to the specification, it is not allowed to process this answer in + // a ping or multicast slot + if( ( rxSlot != RX_SLOT_WIN_PING_SLOT ) && ( rxSlot != RX_SLOT_WIN_MULTICAST_SLOT ) ) + { +#ifdef LORAMAC_CLASSB_TESTCASE + DBG_PRINTF("receive SRV_MAC_PING_SLOT_INFO_ANS in RX1\r\n"); +#endif + LoRaMacClassBPingSlotInfoAns( ); + } + } + break; + case SRV_MAC_PING_SLOT_CHANNEL_REQ: + { + uint8_t status = 0x03; + uint32_t frequency = 0; + uint8_t datarate; + + frequency = ( uint32_t )payload[macIndex++]; + frequency |= ( uint32_t )payload[macIndex++] << 8; + frequency |= ( uint32_t )payload[macIndex++] << 16; + frequency *= 100; + datarate = payload[macIndex++] & 0x0F; +#ifdef LORAMAC_CLASSB_TESTCASE + DBG_PRINTF("receive SRV_MAC_PING_SLOT_CHANNEL_REQ frequency=%u datarate=%u\r\n", (unsigned int)frequency, datarate); +#endif + status = LoRaMacClassBPingSlotChannelReq( datarate, frequency ); + AddMacCommand( MOTE_MAC_PING_SLOT_FREQ_ANS, status, 0 ); + } + break; + case SRV_MAC_BEACON_TIMING_ANS: + { + uint16_t beaconTimingDelay = 0; + uint8_t beaconTimingChannel = 0; + + beaconTimingDelay = ( uint16_t )payload[macIndex++]; + beaconTimingDelay |= ( uint16_t )payload[macIndex++] << 8; + beaconTimingChannel = payload[macIndex++]; + + LoRaMacClassBBeaconTimingAns( beaconTimingDelay, beaconTimingChannel ); + } + break; + case SRV_MAC_BEACON_FREQ_REQ: + { + uint32_t frequency = 0; + + frequency = ( uint32_t )payload[macIndex++]; + frequency |= ( uint32_t )payload[macIndex++] << 8; + frequency |= ( uint32_t )payload[macIndex++] << 16; + frequency *= 100; +#ifdef LORAMAC_CLASSB_TESTCASE + DBG_PRINTF("receive SRV_MAC_BEACON_FREQ_REQ frequency=%u\r\n", (unsigned int)frequency); +#endif + if( LoRaMacClassBBeaconFreqReq( frequency ) == true ) + { + AddMacCommand( MOTE_MAC_BEACON_FREQ_ANS, 1, 0 ); + } + else + { + AddMacCommand( MOTE_MAC_BEACON_FREQ_ANS, 0, 0 ); + } + } + break; + default: + // Unknown command. ABORT MAC commands processing + return; + } + } +} + +#ifdef CONFIG_LORA_CAD +static bool StartCAD( uint8_t channel ) +{ + TxConfigParams_t txConfig; + int8_t txPower = 0; + TimerTime_t txTime = 0; + + memset(&txConfig, 0, sizeof(TxConfigParams_t)); + txConfig.Channel = channel; + txConfig.Datarate = LoRaMacParams.ChannelsDatarate; + txConfig.TxPower = LoRaMacParams.ChannelsTxPower; + txConfig.MaxEirp = LoRaMacParams.MaxEirp; + txConfig.AntennaGain = LoRaMacParams.AntennaGain; + txConfig.PktLen = LoRaMacBufferPktLen; + + bool ret = RegionTxConfig( LoRaMacRegion, &txConfig, &txPower, &txTime ); + Radio.StartCad(LORA_CAD_SYMBOLS); + + return ret; +} +#endif + +LoRaMacStatus_t Send( LoRaMacHeader_t *macHdr, uint8_t fPort, void *fBuffer, uint16_t fBufferSize ) +{ + LoRaMacFrameCtrl_t fCtrl; + LoRaMacStatus_t status = LORAMAC_STATUS_PARAMETER_INVALID; +#ifdef CONFIG_LWAN + lwan_dev_status_set(DEVICE_STATUS_IDLE); +#endif + fCtrl.Value = 0; + fCtrl.Bits.FOptsLen = 0; + if( LoRaMacDeviceClass == CLASS_B ) + { +#ifdef LORAMAC_CLASSB_TESTCASE + DBG_PRINTF("Send class b frame\r\n"); +#endif + fCtrl.Bits.FPending = 1; + } + else + { + fCtrl.Bits.FPending = 0; + } + fCtrl.Bits.Ack = false; + fCtrl.Bits.AdrAckReq = false; + fCtrl.Bits.Adr = AdrCtrlOn; + + // Prepare the frame + status = PrepareFrame( macHdr, &fCtrl, fPort, fBuffer, fBufferSize ); + + // Validate status + if ( status != LORAMAC_STATUS_OK ) { + return status; + } + + // Reset confirm parameters + McpsConfirm.NbRetries = 0; + McpsConfirm.AckReceived = false; + McpsConfirm.UpLinkCounter = UpLinkCounter; + + status = ScheduleTx( ); +#ifdef CONFIG_LORA_VERIFY + if (g_lora_debug == true) { + PRINTF_RAW("MacHdr major:%d rfu:%d mtype:%d\r\n", macHdr->Bits.Major, macHdr->Bits.RFU, macHdr->Bits.MType); + PRINTF_RAW("fCtrl rfu:%d Adr:%d AdrAckReq:%d fCtrl.Bits.Ack:%d\r\n", fCtrl.Bits.FPending, fCtrl.Bits.Adr, fCtrl.Bits.AdrAckReq, fCtrl.Bits.Ack); + } +#endif + return status; +} + +static LoRaMacStatus_t ScheduleTx( void ) +{ + TimerTime_t dutyCycleTimeOff = 0; + NextChanParams_t nextChan; + + // Check if the device is off + if ( MaxDCycle == 255 ) { + return LORAMAC_STATUS_DEVICE_OFF; + } + if ( MaxDCycle == 0 ) { + AggregatedTimeOff = 0; + } + + // Update Backoff + CalculateBackOff( LastTxChannel ); + + nextChan.AggrTimeOff = AggregatedTimeOff; + nextChan.Datarate = LoRaMacParams.ChannelsDatarate; + nextChan.DutyCycleEnabled = DutyCycleOn; + nextChan.Joined = IsLoRaMacNetworkJoined; + nextChan.LastAggrTx = AggregatedLastTxDoneTime; + + // Select channel + while ( RegionNextChannel( LoRaMacRegion, &nextChan, &Channel, &dutyCycleTimeOff, &AggregatedTimeOff ) == false ) { + // Set the default datarate + LoRaMacParams.ChannelsDatarate = LoRaMacParamsDefaults.ChannelsDatarate; + // Update datarate in the function parameters + nextChan.Datarate = LoRaMacParams.ChannelsDatarate; + } + + // Compute Rx1 windows parameters + RegionComputeRxWindowParameters( LoRaMacRegion, + RegionApplyDrOffset( LoRaMacRegion, LoRaMacParams.DownlinkDwellTime, LoRaMacParams.ChannelsDatarate, + LoRaMacParams.Rx1DrOffset ), + LoRaMacParams.MinRxSymbols, + LoRaMacParams.SystemMaxRxError, + &RxWindow1Config ); + // Compute Rx2 windows parameters + RegionComputeRxWindowParameters( LoRaMacRegion, + LoRaMacParams.Rx2Channel.Datarate, + LoRaMacParams.MinRxSymbols, + LoRaMacParams.SystemMaxRxError, + &RxWindow2Config ); + + if ( IsLoRaMacNetworkJoined == false ) { + RxWindow1Delay = LoRaMacParams.JoinAcceptDelay1 + RxWindow1Config.WindowOffset; + RxWindow2Delay = LoRaMacParams.JoinAcceptDelay2 + RxWindow2Config.WindowOffset; + } else { + if ( ValidatePayloadLength( LoRaMacTxPayloadLen, LoRaMacParams.ChannelsDatarate, MacCommandsBufferIndex ) == false ) { + return LORAMAC_STATUS_LENGTH_ERROR; + } + RxWindow1Delay = LoRaMacParams.ReceiveDelay1 + RxWindow1Config.WindowOffset; + RxWindow2Delay = LoRaMacParams.ReceiveDelay2 + RxWindow2Config.WindowOffset; + } + + // Schedule transmission of frame + if ( dutyCycleTimeOff == 0 ) { +#ifdef CONFIG_LORA_CAD + StartCAD(Channel); + return LORAMAC_STATUS_OK; +#else + // Try to send now + return SendFrameOnChannel( Channel ); +#endif + } else { + // Send later - prepare timer + LoRaMacState |= LORAMAC_TX_DELAYED; + TimerSetValue( &TxDelayedTimer, dutyCycleTimeOff ); + TimerStart( &TxDelayedTimer ); + + return LORAMAC_STATUS_OK; + } +} + +static void CalculateBackOff( uint8_t channel ) +{ + CalcBackOffParams_t calcBackOff; + + calcBackOff.Joined = IsLoRaMacNetworkJoined; + calcBackOff.DutyCycleEnabled = DutyCycleOn; + calcBackOff.Channel = channel; + calcBackOff.ElapsedTime = TimerGetElapsedTime( LoRaMacInitializationTime ); + calcBackOff.TxTimeOnAir = TxTimeOnAir; + calcBackOff.LastTxIsJoinRequest = LastTxIsJoinRequest; + + // Update regional back-off + RegionCalcBackOff( LoRaMacRegion, &calcBackOff ); + + // Update aggregated time-off + AggregatedTimeOff = TxTimeOnAir * AggregatedDCycle - TxTimeOnAir; +} + +static void ResetMacParameters( void ) +{ + IsLoRaMacNetworkJoined = false; + + // Counters + UpLinkCounter = 0; + DownLinkCounter = 0; + AdrAckCounter = 0; + + ChannelsNbRepCounter = 0; + + AckTimeoutRetries = 1; + AckTimeoutRetriesCounter = 1; + AckTimeoutRetry = false; + + MaxDCycle = 0; + AggregatedDCycle = 1; + + MacCommandsBufferIndex = 0; + MacCommandsBufferToRepeatIndex = 0; + + IsRxWindowsEnabled = true; + + LoRaMacParams.ChannelsTxPower = LoRaMacParamsDefaults.ChannelsTxPower; + LoRaMacParams.ChannelsDatarate = LoRaMacParamsDefaults.ChannelsDatarate; + LoRaMacParams.Rx1DrOffset = LoRaMacParamsDefaults.Rx1DrOffset; + memcpy(&LoRaMacParams.Rx2Channel, &LoRaMacParamsDefaults.Rx2Channel, sizeof(LoRaMacParams.Rx2Channel)); + LoRaMacParams.UplinkDwellTime = LoRaMacParamsDefaults.UplinkDwellTime; + LoRaMacParams.DownlinkDwellTime = LoRaMacParamsDefaults.DownlinkDwellTime; + LoRaMacParams.MaxEirp = LoRaMacParamsDefaults.MaxEirp; + LoRaMacParams.AntennaGain = LoRaMacParamsDefaults.AntennaGain; + + NodeAckRequested = false; + SrvAckRequested = false; + MacCommandsInNextTx = false; + + // Reset Multicast downlink counters + MulticastParams_t *cur = MulticastChannels; + while ( cur != NULL ) { + cur->DownLinkCounter = 0; + cur = cur->Next; + } + + // Initialize channel index. + Channel = 0; + LastTxChannel = Channel; +} + +static bool IsFPortAllowed( uint8_t fPort ) +{ + if( fPort > 224 ) + { + return false; + } + return true; +} + +static void OpenContinuousRx2Window( void ) +{ + OnRxWindow2TimerEvent( ); + RxSlot = RX_SLOT_WIN_CLASS_C; +} + +LoRaMacStatus_t PrepareFrame( LoRaMacHeader_t *macHdr, LoRaMacFrameCtrl_t *fCtrl, uint8_t fPort, void *fBuffer, + uint16_t fBufferSize ) +{ + AdrNextParams_t adrNext; + uint16_t i; + uint8_t pktHeaderLen = 0; + uint32_t mic = 0; + const void *payload = fBuffer; + uint8_t framePort = fPort; + + LoRaMacBufferPktLen = 0; + + NodeAckRequested = false; + + if ( fBuffer == NULL ) { + fBufferSize = 0; + } + + LoRaMacTxPayloadLen = fBufferSize; + + LoRaMacBuffer[pktHeaderLen++] = macHdr->Value; + + switch ( macHdr->Bits.MType ) { +#ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) + PRINTF_RAW("UpLoad frame %d being processed\r\n", macHdr->Bits.MType); +#endif + case FRAME_TYPE_JOIN_REQ: + LoRaMacBufferPktLen = pktHeaderLen; + + memcpyr( LoRaMacBuffer + LoRaMacBufferPktLen, LoRaMacAppEui, 8 ); + LoRaMacBufferPktLen += 8; + memcpyr( LoRaMacBuffer + LoRaMacBufferPktLen, LoRaMacDevEui, 8 ); + LoRaMacBufferPktLen += 8; + + LoRaMacDevNonce = rand1( ); +#ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) { + PRINTF_RAW("DevNonce:%d\rn\n", LoRaMacDevNonce); + } +#endif + LoRaMacBuffer[LoRaMacBufferPktLen++] = LoRaMacDevNonce & 0xFF; + LoRaMacBuffer[LoRaMacBufferPktLen++] = ( LoRaMacDevNonce >> 8 ) & 0xFF; + + LoRaMacJoinComputeMic( LoRaMacBuffer, LoRaMacBufferPktLen & 0xFF, LoRaMacAppKey, &mic ); + + LoRaMacBuffer[LoRaMacBufferPktLen++] = mic & 0xFF; + LoRaMacBuffer[LoRaMacBufferPktLen++] = ( mic >> 8 ) & 0xFF; + LoRaMacBuffer[LoRaMacBufferPktLen++] = ( mic >> 16 ) & 0xFF; + LoRaMacBuffer[LoRaMacBufferPktLen++] = ( mic >> 24 ) & 0xFF; + + break; + case FRAME_TYPE_DATA_CONFIRMED_UP: + NodeAckRequested = true; + //Intentional fallthrough + case FRAME_TYPE_DATA_UNCONFIRMED_UP: + if ( IsLoRaMacNetworkJoined == false ) { + return LORAMAC_STATUS_NO_NETWORK_JOINED; // No network has been joined yet + } + + // Adr next request + adrNext.UpdateChanMask = true; + adrNext.AdrEnabled = fCtrl->Bits.Adr; + adrNext.AdrAckCounter = AdrAckCounter; + adrNext.Datarate = LoRaMacParams.ChannelsDatarate; + adrNext.TxPower = LoRaMacParams.ChannelsTxPower; + adrNext.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + + fCtrl->Bits.AdrAckReq = RegionAdrNext( LoRaMacRegion, &adrNext, + &LoRaMacParams.ChannelsDatarate, &LoRaMacParams.ChannelsTxPower, &AdrAckCounter ); + + if ( SrvAckRequested == true ) { + SrvAckRequested = false; + fCtrl->Bits.Ack = 1; + } + + LoRaMacBuffer[pktHeaderLen++] = ( LoRaMacDevAddr ) & 0xFF; + LoRaMacBuffer[pktHeaderLen++] = ( LoRaMacDevAddr >> 8 ) & 0xFF; + LoRaMacBuffer[pktHeaderLen++] = ( LoRaMacDevAddr >> 16 ) & 0xFF; + LoRaMacBuffer[pktHeaderLen++] = ( LoRaMacDevAddr >> 24 ) & 0xFF; + + LoRaMacBuffer[pktHeaderLen++] = fCtrl->Value; + + LoRaMacBuffer[pktHeaderLen++] = UpLinkCounter & 0xFF; + LoRaMacBuffer[pktHeaderLen++] = ( UpLinkCounter >> 8 ) & 0xFF; + + // Copy the MAC commands which must be re-send into the MAC command buffer + memcpy1( &MacCommandsBuffer[MacCommandsBufferIndex], MacCommandsBufferToRepeat, MacCommandsBufferToRepeatIndex ); + MacCommandsBufferIndex += MacCommandsBufferToRepeatIndex; + + if ( ( payload != NULL ) && ( LoRaMacTxPayloadLen > 0 ) ) { + if ( MacCommandsInNextTx == true ) { + if ( MacCommandsBufferIndex <= LORA_MAC_COMMAND_MAX_FOPTS_LENGTH ) { + fCtrl->Bits.FOptsLen += MacCommandsBufferIndex; + + // Update FCtrl field with new value of OptionsLength + LoRaMacBuffer[0x05] = fCtrl->Value; + for ( i = 0; i < MacCommandsBufferIndex; i++ ) { + LoRaMacBuffer[pktHeaderLen++] = MacCommandsBuffer[i]; + } + } else { + LoRaMacTxPayloadLen = MacCommandsBufferIndex; + payload = MacCommandsBuffer; + framePort = 0; + } + } + } else { + if ( ( MacCommandsBufferIndex > 0 ) && ( MacCommandsInNextTx == true ) ) { + LoRaMacTxPayloadLen = MacCommandsBufferIndex; + payload = MacCommandsBuffer; + framePort = 0; + } + } + MacCommandsInNextTx = false; + // Store MAC commands which must be re-send in case the device does not receive a downlink anymore + MacCommandsBufferToRepeatIndex = ParseMacCommandsToRepeat( MacCommandsBuffer, MacCommandsBufferIndex, + MacCommandsBufferToRepeat ); + if ( MacCommandsBufferToRepeatIndex > 0 ) { + MacCommandsInNextTx = true; + } + + if ( ( payload != NULL ) && ( LoRaMacTxPayloadLen > 0 ) ) { + LoRaMacBuffer[pktHeaderLen++] = framePort; + if ((pktHeaderLen + LoRaMacTxPayloadLen) > (LORAMAC_PHY_MAXPAYLOAD - 4)) { + LoRaMacTxPayloadLen = LORAMAC_PHY_MAXPAYLOAD - 4 - pktHeaderLen; + } + + if ( framePort == 0 ) { + // Reset buffer index as the mac commands are being sent on port 0 + MacCommandsBufferIndex = 0; + LoRaMacPayloadEncrypt( (uint8_t * ) payload, LoRaMacTxPayloadLen, LoRaMacNwkSKey, LoRaMacDevAddr, UP_LINK, + UpLinkCounter, &LoRaMacBuffer[pktHeaderLen] ); + } else { + LoRaMacPayloadEncrypt( (uint8_t * ) payload, LoRaMacTxPayloadLen, LoRaMacAppSKey, LoRaMacDevAddr, UP_LINK, + UpLinkCounter, &LoRaMacBuffer[pktHeaderLen] ); + } + } + LoRaMacBufferPktLen = pktHeaderLen + LoRaMacTxPayloadLen; + + LoRaMacComputeMic( LoRaMacBuffer, LoRaMacBufferPktLen, LoRaMacNwkSKey, LoRaMacDevAddr, UP_LINK, UpLinkCounter, &mic ); + + LoRaMacBuffer[LoRaMacBufferPktLen + 0] = mic & 0xFF; + LoRaMacBuffer[LoRaMacBufferPktLen + 1] = ( mic >> 8 ) & 0xFF; + LoRaMacBuffer[LoRaMacBufferPktLen + 2] = ( mic >> 16 ) & 0xFF; + LoRaMacBuffer[LoRaMacBufferPktLen + 3] = ( mic >> 24 ) & 0xFF; + + LoRaMacBufferPktLen += LORAMAC_MFR_LEN; + + break; + case FRAME_TYPE_PROPRIETARY: + if ( ( fBuffer != NULL ) && ( LoRaMacTxPayloadLen > 0 ) ) { + memcpy1( LoRaMacBuffer + pktHeaderLen, ( uint8_t * ) fBuffer, LoRaMacTxPayloadLen ); + LoRaMacBufferPktLen = pktHeaderLen + LoRaMacTxPayloadLen; + } + break; + default: + return LORAMAC_STATUS_SERVICE_UNKNOWN; + } + + return LORAMAC_STATUS_OK; +} + + + + +LoRaMacStatus_t SendFrameOnChannel( uint8_t channel ) +{ + + TxConfigParams_t txConfig; + int8_t txPower = 0; + + txConfig.Channel = channel; + txConfig.Datarate = LoRaMacParams.ChannelsDatarate; + txConfig.TxPower = LoRaMacParams.ChannelsTxPower; + txConfig.MaxEirp = LoRaMacParams.MaxEirp; + txConfig.AntennaGain = LoRaMacParams.AntennaGain; + txConfig.PktLen = LoRaMacBufferPktLen; + + + if( LoRaMacClassBIsBeaconExpected( ) == true ) + { + return LORAMAC_STATUS_BUSY_BEACON_RESERVED_TIME; + } + + if( LoRaMacDeviceClass == CLASS_B ) + { + if( LoRaMacClassBIsPingExpected( ) == true ) + { + return LORAMAC_STATUS_BUSY_PING_SLOT_WINDOW_TIME; + } + else if( LoRaMacClassBIsMulticastExpected( ) == true ) + { + return LORAMAC_STATUS_BUSY_PING_SLOT_WINDOW_TIME; + } + else + { + LoRaMacClassBStopRxSlots( ); + } + } + RegionTxConfig( LoRaMacRegion, &txConfig, &txPower, &TxTimeOnAir ); + + LoRaMacConfirmQueueSetStatusCmn( LORAMAC_EVENT_INFO_STATUS_ERROR ); + McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + McpsConfirm.Datarate = LoRaMacParams.ChannelsDatarate; + McpsConfirm.TxPower = txPower; + McpsConfirm.Channel = channel; + + // Store the time on air + McpsConfirm.TxTimeOnAir = TxTimeOnAir; + MlmeConfirm.TxTimeOnAir = TxTimeOnAir; + + if( LoRaMacClassBIsBeaconModeActive( ) == true ) + { + // Currently, the Time-On-Air can only be computed when the radion is configured with + // the TX configuration + TimerTime_t collisionTime = LoRaMacClassBIsUplinkCollision( TxTimeOnAir ); + + if( collisionTime > 0 ) + { + return LORAMAC_STATUS_BUSY_UPLINK_COLLISION; + } + } + + LoRaMacClassBHaltBeaconing( ); + + // Starts the MAC layer status check timer + TimerSetValue( &MacStateCheckTimer, MAC_STATE_CHECK_TIMEOUT ); + TimerStart( &MacStateCheckTimer ); + + if ( IsLoRaMacNetworkJoined == false ) { + JoinRequestTrials++; + } + // Send now +#if (LoraWan_RGB==1) + RGB_ON(COLOR_SEND,0); +#endif + Radio.Send( LoRaMacBuffer, LoRaMacBufferPktLen ); + + LoRaMacState |= LORAMAC_TX_RUNNING; + + return LORAMAC_STATUS_OK; +} + +LoRaMacStatus_t SetTxContinuousWave( uint16_t timeout ) +{ + ContinuousWaveParams_t continuousWave; + + continuousWave.Channel = Channel; + continuousWave.Datarate = LoRaMacParams.ChannelsDatarate; + continuousWave.TxPower = LoRaMacParams.ChannelsTxPower; + continuousWave.MaxEirp = LoRaMacParams.MaxEirp; + continuousWave.AntennaGain = LoRaMacParams.AntennaGain; + continuousWave.Timeout = timeout; + + RegionSetContinuousWave( LoRaMacRegion, &continuousWave ); + + // Starts the MAC layer status check timer + TimerSetValue( &MacStateCheckTimer, MAC_STATE_CHECK_TIMEOUT ); + TimerStart( &MacStateCheckTimer ); + + LoRaMacState |= LORAMAC_TX_RUNNING; + + return LORAMAC_STATUS_OK; +} + +LoRaMacStatus_t SetTxContinuousWave1( uint16_t timeout, uint32_t frequency, uint8_t power ) +{ + Radio.SetTxContinuousWave( frequency, power, timeout ); + + // Starts the MAC layer status check timer + TimerSetValue( &MacStateCheckTimer, MAC_STATE_CHECK_TIMEOUT ); + TimerStart( &MacStateCheckTimer ); + + LoRaMacState |= LORAMAC_TX_RUNNING; + + return LORAMAC_STATUS_OK; +} + +LoRaMacStatus_t LoRaMacInitialization( LoRaMacPrimitives_t *primitives, LoRaMacCallback_t *callbacks, + LoRaMacRegion_t region ) +{ + GetPhyParams_t getPhy; + PhyParam_t phyParam; + LoRaMacClassBCallback_t classBCallbacks; + LoRaMacClassBParams_t classBParams; + + if ( primitives == NULL ) { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + + if( ( primitives->MacMcpsConfirm == NULL ) || + ( primitives->MacMcpsIndication == NULL ) || + ( primitives->MacMlmeConfirm == NULL ) || + ( primitives->MacMlmeIndication == NULL ) ) { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + // Verify if the region is supported + if ( RegionIsActive( region ) == false ) { + return LORAMAC_STATUS_REGION_NOT_SUPPORTED; + } + + // Confirm queue reset + LoRaMacConfirmQueueInit( primitives ); + + LoRaMacPrimitives = primitives; + LoRaMacCallbacks = callbacks; + LoRaMacRegion = region; + + LoRaMacFlags.Value = 0; + + LoRaMacDeviceClass = CLASS_A; + LoRaMacState = LORAMAC_IDLE; + + JoinRequestTrials = 0; + MaxJoinRequestTrials = 1; + + // Reset duty cycle times + AggregatedLastTxDoneTime = 0; + AggregatedTimeOff = 0; + + // Reset to defaults + getPhy.Attribute = PHY_DUTY_CYCLE; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + DutyCycleOn = ( bool ) phyParam.Value; + + getPhy.Attribute = PHY_DEF_TX_POWER; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.ChannelsTxPower = phyParam.Value; + + getPhy.Attribute = PHY_DEF_TX_DR; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.ChannelsDatarate = phyParam.Value; + + getPhy.Attribute = PHY_MAX_RX_WINDOW; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.MaxRxWindow = phyParam.Value; + + getPhy.Attribute = PHY_RECEIVE_DELAY1; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.ReceiveDelay1 = phyParam.Value; + + getPhy.Attribute = PHY_RECEIVE_DELAY2; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.ReceiveDelay2 = phyParam.Value; + + getPhy.Attribute = PHY_JOIN_ACCEPT_DELAY1; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.JoinAcceptDelay1 = phyParam.Value; + + getPhy.Attribute = PHY_JOIN_ACCEPT_DELAY2; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.JoinAcceptDelay2 = phyParam.Value; + + getPhy.Attribute = PHY_DEF_DR1_OFFSET; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.Rx1DrOffset = phyParam.Value; + + getPhy.Attribute = PHY_DEF_RX2_FREQUENCY; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.Rx2Channel.Frequency = phyParam.Value; + + getPhy.Attribute = PHY_DEF_RX2_DR; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.Rx2Channel.Datarate = phyParam.Value; + + getPhy.Attribute = PHY_DEF_UPLINK_DWELL_TIME; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.UplinkDwellTime = phyParam.Value; + + getPhy.Attribute = PHY_DEF_DOWNLINK_DWELL_TIME; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.DownlinkDwellTime = phyParam.Value; + + getPhy.Attribute = PHY_DEF_MAX_EIRP; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.MaxEirp = phyParam.fValue; + + getPhy.Attribute = PHY_DEF_ANTENNA_GAIN; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + LoRaMacParamsDefaults.AntennaGain = phyParam.fValue; + + RegionInitDefaults( LoRaMacRegion, INIT_TYPE_INIT ); + + // Init parameters which are not set in function ResetMacParameters + LoRaMacParams.RepeaterSupport = false; + LoRaMacParamsDefaults.ChannelsNbRep = 1; + LoRaMacParamsDefaults.SystemMaxRxError = 10; + LoRaMacParamsDefaults.MinRxSymbols = 6; + + LoRaMacParams.SystemMaxRxError = LoRaMacParamsDefaults.SystemMaxRxError; + LoRaMacParams.MinRxSymbols = LoRaMacParamsDefaults.MinRxSymbols; + LoRaMacParams.MaxRxWindow = LoRaMacParamsDefaults.MaxRxWindow; + LoRaMacParams.ReceiveDelay1 = LoRaMacParamsDefaults.ReceiveDelay1; + LoRaMacParams.ReceiveDelay2 = LoRaMacParamsDefaults.ReceiveDelay2; + LoRaMacParams.JoinAcceptDelay1 = LoRaMacParamsDefaults.JoinAcceptDelay1; + LoRaMacParams.JoinAcceptDelay2 = LoRaMacParamsDefaults.JoinAcceptDelay2; + LoRaMacParams.ChannelsNbRep = LoRaMacParamsDefaults.ChannelsNbRep; + + ResetMacParameters( ); + + // Initialize timers + TimerInit( &MacStateCheckTimer, OnMacStateCheckTimerEvent ); + TimerSetValue( &MacStateCheckTimer, MAC_STATE_CHECK_TIMEOUT ); + + TimerInit( &TxDelayedTimer, OnTxDelayedTimerEvent ); + TimerInit( &RxWindowTimer1, OnRxWindow1TimerEvent ); + TimerInit( &RxWindowTimer2, OnRxWindow2TimerEvent ); + TimerInit( &AckTimeoutTimer, OnAckTimeoutTimerEvent ); +#ifdef CONFIG_LORA_CAD + TimerInit( &TxImmediateTimer, OnTxImmediateTimerEvent ); +#endif + + // Store the current initialization time + LoRaMacInitializationTime = TimerGetCurrentTime( ); + + // Initialize Radio driver + RadioEvents.TxDone = OnRadioTxDone; + RadioEvents.RxDone = OnRadioRxDone; + RadioEvents.RxError = OnRadioRxError; + RadioEvents.TxTimeout = OnRadioTxTimeout; + RadioEvents.RxTimeout = OnRadioRxTimeout; +#ifdef CONFIG_LORA_CAD + RadioEvents.CadDone = OnRadioCadDone; +#endif + Radio.Init( &RadioEvents ); + + // Random seed initialization + srand1( Radio.Random( ) ); + + PublicNetwork = true; + Radio.SetPublicNetwork(true); + Radio.Sleep( ); + + // Initialize class b + // Apply callback + classBCallbacks.GetTemperatureLevel = NULL; + if( callbacks != NULL ) + { + classBCallbacks.GetTemperatureLevel = callbacks->GetTemperatureLevel; + } + + // Must all be static. Don't use local references. + classBParams.MlmeIndication = &MlmeIndication; + classBParams.McpsIndication = &McpsIndication; + classBParams.MlmeConfirm = &MlmeConfirm; + classBParams.LoRaMacFlags = &LoRaMacFlags; + classBParams.LoRaMacDevAddr = &LoRaMacDevAddr; + classBParams.LoRaMacRegion = &LoRaMacRegion; + classBParams.MacStateCheckTimer = &MacStateCheckTimer; + classBParams.LoRaMacParams = &LoRaMacParams; + classBParams.MulticastChannels = &MulticastChannels; + + LoRaMacClassBInit( &classBParams, &classBCallbacks ); + + return LORAMAC_STATUS_OK; +} + +LoRaMacStatus_t LoRaMacQueryTxPossible( uint8_t size, LoRaMacTxInfo_t *txInfo ) +{ + AdrNextParams_t adrNext; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + int8_t datarate = LoRaMacParamsDefaults.ChannelsDatarate; + int8_t txPower = LoRaMacParamsDefaults.ChannelsTxPower; + uint8_t fOptLen = MacCommandsBufferIndex + MacCommandsBufferToRepeatIndex; + + if ( txInfo == NULL ) { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + + // Setup ADR request + adrNext.UpdateChanMask = false; + adrNext.AdrEnabled = AdrCtrlOn; + adrNext.AdrAckCounter = AdrAckCounter; + adrNext.Datarate = LoRaMacParams.ChannelsDatarate; + adrNext.TxPower = LoRaMacParams.ChannelsTxPower; + adrNext.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + + // We call the function for information purposes only. We don't want to + // apply the datarate, the tx power and the ADR ack counter. + RegionAdrNext( LoRaMacRegion, &adrNext, &datarate, &txPower, &AdrAckCounter ); + + // Setup PHY request + getPhy.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + getPhy.Datarate = datarate; + getPhy.Attribute = PHY_MAX_PAYLOAD; + + // Change request in case repeater is supported + if( LoRaMacParams.RepeaterSupport == true ) { + getPhy.Attribute = PHY_MAX_PAYLOAD_REPEATER; + } + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + txInfo->CurrentPayloadSize = phyParam.Value; + + // Verify if the fOpts fit into the maximum payload + if ( txInfo->CurrentPayloadSize >= fOptLen ) { + txInfo->MaxPossiblePayload = txInfo->CurrentPayloadSize - fOptLen; + } else { + txInfo->MaxPossiblePayload = txInfo->CurrentPayloadSize; + // The fOpts don't fit into the maximum payload. Omit the MAC commands to + // ensure that another uplink is possible. + fOptLen = 0; + MacCommandsBufferIndex = 0; + MacCommandsBufferToRepeatIndex = 0; + } + + // Verify if the fOpts and the payload fit into the maximum payload + if ( ValidatePayloadLength( size, datarate, fOptLen ) == false ) { + return LORAMAC_STATUS_LENGTH_ERROR; + } + return LORAMAC_STATUS_OK; +} + +LoRaMacStatus_t LoRaMacMibGetRequestConfirm( MibRequestConfirm_t *mibGet ) +{ + LoRaMacStatus_t status = LORAMAC_STATUS_OK; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + if ( mibGet == NULL ) { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + + switch ( mibGet->Type ) { + case MIB_DEVICE_CLASS: { + mibGet->Param.Class = LoRaMacDeviceClass; + break; + } + case MIB_NETWORK_JOINED: { + mibGet->Param.IsNetworkJoined = IsLoRaMacNetworkJoined; + break; + } + case MIB_ADR: { + mibGet->Param.AdrEnable = AdrCtrlOn; + break; + } + case MIB_NET_ID: { + mibGet->Param.NetID = LoRaMacNetID; + break; + } + case MIB_DEV_ADDR: { + mibGet->Param.DevAddr = LoRaMacDevAddr; + break; + } + case MIB_NWK_SKEY: { + mibGet->Param.NwkSKey = LoRaMacNwkSKey; + break; + } + case MIB_APP_SKEY: { + mibGet->Param.AppSKey = LoRaMacAppSKey; + break; + } + case MIB_PUBLIC_NETWORK: { + mibGet->Param.EnablePublicNetwork = PublicNetwork; + break; + } + case MIB_REPEATER_SUPPORT: { + mibGet->Param.EnableRepeaterSupport = LoRaMacParams.RepeaterSupport; + break; + } + case MIB_CHANNELS: { + getPhy.Attribute = PHY_CHANNELS; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + + mibGet->Param.ChannelList = phyParam.Channels; + break; + } + case MIB_RX2_CHANNEL: { + mibGet->Param.Rx2Channel = LoRaMacParams.Rx2Channel; + break; + } + case MIB_RX2_DEFAULT_CHANNEL: { + mibGet->Param.Rx2Channel = LoRaMacParamsDefaults.Rx2Channel; + break; + } + case MIB_CHANNELS_DEFAULT_MASK: { + getPhy.Attribute = PHY_CHANNELS_DEFAULT_MASK; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + + mibGet->Param.ChannelsDefaultMask = phyParam.ChannelsMask; + break; + } + case MIB_CHANNELS_MASK: { + getPhy.Attribute = PHY_CHANNELS_MASK; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + + mibGet->Param.ChannelsMask = phyParam.ChannelsMask; + break; + } + case MIB_CHANNELS_NB_REP: { + mibGet->Param.ChannelNbRep = LoRaMacParams.ChannelsNbRep; + break; + } + case MIB_MAX_RX_WINDOW_DURATION: { + mibGet->Param.MaxRxWindow = LoRaMacParams.MaxRxWindow; + break; + } + case MIB_RECEIVE_DELAY_1: { + mibGet->Param.ReceiveDelay1 = LoRaMacParams.ReceiveDelay1; + break; + } + case MIB_RECEIVE_DELAY_2: { + mibGet->Param.ReceiveDelay2 = LoRaMacParams.ReceiveDelay2; + break; + } + case MIB_JOIN_ACCEPT_DELAY_1: { + mibGet->Param.JoinAcceptDelay1 = LoRaMacParams.JoinAcceptDelay1; + break; + } + case MIB_JOIN_ACCEPT_DELAY_2: { + mibGet->Param.JoinAcceptDelay2 = LoRaMacParams.JoinAcceptDelay2; + break; + } + case MIB_CHANNELS_DEFAULT_DATARATE: { + mibGet->Param.ChannelsDefaultDatarate = LoRaMacParamsDefaults.ChannelsDatarate; + break; + } + case MIB_CHANNELS_DATARATE: { + mibGet->Param.ChannelsDatarate = LoRaMacParams.ChannelsDatarate; + break; + } + case MIB_CHANNELS_DEFAULT_TX_POWER: { + mibGet->Param.ChannelsDefaultTxPower = LoRaMacParamsDefaults.ChannelsTxPower; + break; + } + case MIB_CHANNELS_TX_POWER: { + mibGet->Param.ChannelsTxPower = LoRaMacParams.ChannelsTxPower; + break; + } + case MIB_UPLINK_COUNTER: { + mibGet->Param.UpLinkCounter = UpLinkCounter; + break; + } + case MIB_DOWNLINK_COUNTER: { + mibGet->Param.DownLinkCounter = DownLinkCounter; + break; + } + case MIB_MULTICAST_CHANNEL: { + mibGet->Param.MulticastList = MulticastChannels; + break; + } + case MIB_SYSTEM_MAX_RX_ERROR: { + mibGet->Param.SystemMaxRxError = LoRaMacParams.SystemMaxRxError; + break; + } + case MIB_MIN_RX_SYMBOLS: { + mibGet->Param.MinRxSymbols = LoRaMacParams.MinRxSymbols; + break; + } + case MIB_ANTENNA_GAIN: { + mibGet->Param.AntennaGain = LoRaMacParams.AntennaGain; + break; + } +#ifdef CONFIG_LWAN + case MIB_RX1_DATARATE_OFFSET: { + mibGet->Param.Rx1DrOffset = LoRaMacParams.Rx1DrOffset; + break; + } + case MIB_MAC_STATE: { + mibGet->Param.LoRaMacState = LoRaMacState; + break; + } +#endif +#ifdef CONFIG_LINKWAN + case MIB_FREQ_BAND: { + mibGet->Param.freqband = LoRaMacParams.freqband; + break; + } +#endif + default: + if( LoRaMacDeviceClass == CLASS_B ) + { + status = LoRaMacClassBMibGetRequestConfirm( mibGet ); + } + else + { + status = LORAMAC_STATUS_SERVICE_UNKNOWN; + } + break; + } + + return status; +} + +LoRaMacStatus_t LoRaMacMibSetRequestConfirm( MibRequestConfirm_t *mibSet ) +{ + LoRaMacStatus_t status = LORAMAC_STATUS_OK; + ChanMaskSetParams_t chanMaskSet; + VerifyParams_t verify; + + if ( mibSet == NULL ) { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + if ( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) { + return LORAMAC_STATUS_BUSY; + } + + switch ( mibSet->Type ) { + case MIB_DEVICE_CLASS: + { + status = SwitchClass( mibSet->Param.Class ); + break; + } + case MIB_NETWORK_JOINED: + { + IsLoRaMacNetworkJoined = mibSet->Param.IsNetworkJoined; + break; + } + case MIB_ADR: { + AdrCtrlOn = mibSet->Param.AdrEnable; + break; + } + case MIB_NET_ID: { + LoRaMacNetID = mibSet->Param.NetID; + break; + } + case MIB_DEV_ADDR: { + LoRaMacDevAddr = mibSet->Param.DevAddr; + break; + } + case MIB_NWK_SKEY: { + if ( mibSet->Param.NwkSKey != NULL ) { + memcpy1( LoRaMacNwkSKey, mibSet->Param.NwkSKey, + sizeof( LoRaMacNwkSKey ) ); + } else { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + break; + } + case MIB_APP_SKEY: { + if ( mibSet->Param.AppSKey != NULL ) { + memcpy1( LoRaMacAppSKey, mibSet->Param.AppSKey, + sizeof( LoRaMacAppSKey ) ); + } else { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + break; + } + case MIB_PUBLIC_NETWORK: { + PublicNetwork = mibSet->Param.EnablePublicNetwork; + Radio.SetPublicNetwork(mibSet->Param.EnablePublicNetwork); + break; + } + case MIB_REPEATER_SUPPORT: { + LoRaMacParams.RepeaterSupport = mibSet->Param.EnableRepeaterSupport; + break; + } + case MIB_RX2_CHANNEL: { + verify.DatarateParams.Datarate = mibSet->Param.Rx2Channel.Datarate; + verify.DatarateParams.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; + + if ( RegionVerify( LoRaMacRegion, &verify, PHY_RX_DR ) == true ) { + memcpy(&LoRaMacParams.Rx2Channel, &mibSet->Param.Rx2Channel, sizeof(LoRaMacParams.Rx2Channel)); + if ( ( LoRaMacDeviceClass == CLASS_C ) && ( IsLoRaMacNetworkJoined == true ) ) { + // Compute Rx2 windows parameters + RegionComputeRxWindowParameters( LoRaMacRegion, + LoRaMacParams.Rx2Channel.Datarate, + LoRaMacParams.MinRxSymbols, + LoRaMacParams.SystemMaxRxError, + &RxWindow2Config ); + + RxWindow2Config.Channel = Channel; + RxWindow2Config.Frequency = LoRaMacParams.Rx2Channel.Frequency; + RxWindow2Config.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; + RxWindow2Config.RepeaterSupport = LoRaMacParams.RepeaterSupport; + RxWindow2Config.RxSlot = RX_SLOT_WIN_2; + RxWindow2Config.RxContinuous = true; + + Radio.Sleep(); + if ( RegionRxConfig( LoRaMacRegion, &RxWindow2Config, ( int8_t * )&McpsIndication.RxDatarate ) == true ) { + RxWindowSetup( RxWindow2Config.RxContinuous, LoRaMacParams.MaxRxWindow ); + RxSlot = RxWindow2Config.RxSlot; + } else { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + } + } else { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + break; + } + case MIB_RX2_DEFAULT_CHANNEL: { + verify.DatarateParams.Datarate = mibSet->Param.Rx2Channel.Datarate; + verify.DatarateParams.DownlinkDwellTime = LoRaMacParams.DownlinkDwellTime; + + if ( RegionVerify( LoRaMacRegion, &verify, PHY_RX_DR ) == true ) { + LoRaMacParamsDefaults.Rx2Channel = mibSet->Param.Rx2DefaultChannel; + } else { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + break; + } + case MIB_CHANNELS_DEFAULT_MASK: { + chanMaskSet.ChannelsMaskIn = mibSet->Param.ChannelsMask; + chanMaskSet.ChannelsMaskType = CHANNELS_DEFAULT_MASK; + + if ( RegionChanMaskSet( LoRaMacRegion, &chanMaskSet ) == false ) { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + break; + } + case MIB_CHANNELS_MASK: { + chanMaskSet.ChannelsMaskIn = mibSet->Param.ChannelsMask; + chanMaskSet.ChannelsMaskType = CHANNELS_MASK; + + if ( RegionChanMaskSet( LoRaMacRegion, &chanMaskSet ) == false ) { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + break; + } + case MIB_CHANNELS_NB_REP: { + if ( ( mibSet->Param.ChannelNbRep >= 1 ) && + ( mibSet->Param.ChannelNbRep <= 15 ) ) { + LoRaMacParams.ChannelsNbRep = mibSet->Param.ChannelNbRep; + } else { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + break; + } + case MIB_MAX_RX_WINDOW_DURATION: { + LoRaMacParams.MaxRxWindow = mibSet->Param.MaxRxWindow; + break; + } + case MIB_RECEIVE_DELAY_1: { + LoRaMacParams.ReceiveDelay1 = mibSet->Param.ReceiveDelay1; + break; + } + case MIB_RECEIVE_DELAY_2: { + LoRaMacParams.ReceiveDelay2 = mibSet->Param.ReceiveDelay2; + break; + } + case MIB_JOIN_ACCEPT_DELAY_1: { + LoRaMacParams.JoinAcceptDelay1 = mibSet->Param.JoinAcceptDelay1; + break; + } + case MIB_JOIN_ACCEPT_DELAY_2: { + LoRaMacParams.JoinAcceptDelay2 = mibSet->Param.JoinAcceptDelay2; + break; + } + case MIB_CHANNELS_DEFAULT_DATARATE: { + verify.DatarateParams.Datarate = mibSet->Param.ChannelsDefaultDatarate; + + if ( RegionVerify( LoRaMacRegion, &verify, PHY_DEF_TX_DR ) == true ) { + LoRaMacParamsDefaults.ChannelsDatarate = verify.DatarateParams.Datarate; + } else { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + break; + } + case MIB_CHANNELS_DATARATE: { + verify.DatarateParams.Datarate = mibSet->Param.ChannelsDatarate; + + if ( RegionVerify( LoRaMacRegion, &verify, PHY_TX_DR ) == true ) { + LoRaMacParams.ChannelsDatarate = verify.DatarateParams.Datarate; + } else { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + break; + } + case MIB_CHANNELS_DEFAULT_TX_POWER: { + verify.TxPower = mibSet->Param.ChannelsDefaultTxPower; + + if ( RegionVerify( LoRaMacRegion, &verify, PHY_DEF_TX_POWER ) == true ) { + LoRaMacParamsDefaults.ChannelsTxPower = verify.TxPower; + } else { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + break; + } + case MIB_CHANNELS_TX_POWER: { + verify.TxPower = mibSet->Param.ChannelsTxPower; + + if ( RegionVerify( LoRaMacRegion, &verify, PHY_TX_POWER ) == true ) { + LoRaMacParams.ChannelsTxPower = verify.TxPower; + } else { + status = LORAMAC_STATUS_PARAMETER_INVALID; + } + break; + } + case MIB_UPLINK_COUNTER: { + UpLinkCounter = mibSet->Param.UpLinkCounter; + break; + } + case MIB_DOWNLINK_COUNTER: { + DownLinkCounter = mibSet->Param.DownLinkCounter; + break; + } + case MIB_SYSTEM_MAX_RX_ERROR: { + LoRaMacParams.SystemMaxRxError = LoRaMacParamsDefaults.SystemMaxRxError = mibSet->Param.SystemMaxRxError; + break; + } + case MIB_MIN_RX_SYMBOLS: { + LoRaMacParams.MinRxSymbols = LoRaMacParamsDefaults.MinRxSymbols = mibSet->Param.MinRxSymbols; + break; + } + case MIB_ANTENNA_GAIN: { + LoRaMacParams.AntennaGain = mibSet->Param.AntennaGain; + break; + } + case MIB_MULTICAST_CHANNEL: { + status = LoRaMacMulticastChannelLink(mibSet->Param.MulticastList); + break; + } + case MIB_MULTICAST_CHANNEL_DEL: { + status = LoRaMacMulticastChannelUnlink(mibSet->Param.MulticastList); + break; + } +#ifdef CONFIG_LWAN + case MIB_RX1_DATARATE_OFFSET: { + LoRaMacParams.Rx1DrOffset = mibSet->Param.Rx1DrOffset; + break; + } +#endif + +#ifdef CONFIG_LINKWAN + case MIB_FREQ_BAND: { + LoRaMacParams.freqband = mibSet->Param.freqband; + break; + } +#endif + default: + { + if( LoRaMacDeviceClass == CLASS_B ) + { + status = LoRaMacMibClassBSetRequestConfirm( mibSet ); + } + else + { + status = LORAMAC_STATUS_SERVICE_UNKNOWN; + } + break; + } + } + + return status; +} + +LoRaMacStatus_t LoRaMacChannelAdd( uint8_t id, ChannelParams_t params ) +{ + ChannelAddParams_t channelAdd; + + // Validate if the MAC is in a correct state + if ( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) { + if ( ( LoRaMacState & LORAMAC_TX_CONFIG ) != LORAMAC_TX_CONFIG ) { + return LORAMAC_STATUS_BUSY; + } + } + + channelAdd.NewChannel = ¶ms; + channelAdd.ChannelId = id; + + return RegionChannelAdd( LoRaMacRegion, &channelAdd ); +} + +LoRaMacStatus_t LoRaMacChannelRemove( uint8_t id ) +{ + ChannelRemoveParams_t channelRemove; + + if ( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) { + if ( ( LoRaMacState & LORAMAC_TX_CONFIG ) != LORAMAC_TX_CONFIG ) { + return LORAMAC_STATUS_BUSY; + } + } + + channelRemove.ChannelId = id; + + if ( RegionChannelsRemove( LoRaMacRegion, &channelRemove ) == false ) { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + return LORAMAC_STATUS_OK; +} + +LoRaMacStatus_t LoRaMacMulticastChannelLink( MulticastParams_t *channelParam ) +{ + if ( channelParam == NULL ) { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + if ( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) { + return LORAMAC_STATUS_BUSY; + } + + // Calculate class b parameters + LoRaMacClassBSetMulticastPeriodicity( channelParam ); + + // Reset downlink counter + channelParam->DownLinkCounter = 0; + channelParam->Next = NULL; + + if ( MulticastChannels == NULL ) { + // New node is the fist element + MulticastChannels = channelParam; + } else { + MulticastParams_t *cur = MulticastChannels; + + // Search the last node in the list + while ( cur->Next != NULL ) { + cur = cur->Next; + } + // This function always finds the last node + cur->Next = channelParam; + } + + return LORAMAC_STATUS_OK; +} + +LoRaMacStatus_t LoRaMacMulticastChannelUnlink( MulticastParams_t *channelParam ) +{ + if ( channelParam == NULL ) { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + if ( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) { + return LORAMAC_STATUS_BUSY; + } + + if ( MulticastChannels != NULL ) { + if ( MulticastChannels == channelParam ) { + // First element + MulticastChannels = channelParam->Next; + } else { + MulticastParams_t *cur = MulticastChannels; + + // Search the node in the list + while ( cur->Next && cur->Next != channelParam ) { + cur = cur->Next; + } + // If we found the node, remove it + if ( cur->Next ) { + cur->Next = channelParam->Next; + } + } + channelParam->Next = NULL; + } + + return LORAMAC_STATUS_OK; +} + +LoRaMacStatus_t LoRaMacMlmeRequest( MlmeReq_t *mlmeRequest ) +{ + LoRaMacStatus_t status = LORAMAC_STATUS_SERVICE_UNKNOWN; + LoRaMacHeader_t macHdr; + MlmeConfirmQueue_t queueElement; + AlternateDrParams_t altDr; + VerifyParams_t verify; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + if ( mlmeRequest == NULL ) { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + if( LoRaMacState != LORAMAC_IDLE ) + { + return LORAMAC_STATUS_BUSY; + } + if( LoRaMacConfirmQueueIsFull( ) == true ) + { + return LORAMAC_STATUS_BUSY; + } + + + switch ( mlmeRequest->Type ) { + case MLME_JOIN: { + if ( ( mlmeRequest->Req.Join.DevEui == NULL ) || + ( mlmeRequest->Req.Join.AppEui == NULL ) || + ( mlmeRequest->Req.Join.AppKey == NULL ) || + ( mlmeRequest->Req.Join.NbTrials == 0 ) ) { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + + // Verify the parameter NbTrials for the join procedure + verify.NbJoinTrials = mlmeRequest->Req.Join.NbTrials; + + if ( RegionVerify( LoRaMacRegion, &verify, PHY_NB_JOIN_TRIALS ) == false ) { + // Value not supported, get default + getPhy.Attribute = PHY_DEF_NB_JOIN_TRIALS; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + mlmeRequest->Req.Join.NbTrials = ( uint8_t ) phyParam.Value; + } + + LoRaMacFlags.Bits.MlmeReq = 1; + queueElement.Request = mlmeRequest->Type; + + LoRaMacDevEui = mlmeRequest->Req.Join.DevEui; + LoRaMacAppEui = mlmeRequest->Req.Join.AppEui; + LoRaMacAppKey = mlmeRequest->Req.Join.AppKey; + queueElement.Status = LORAMAC_EVENT_INFO_STATUS_JOIN_FAIL; + queueElement.RestrictCommonReadyToHandle = false; + LoRaMacConfirmQueueAdd( &queueElement ); + MaxJoinRequestTrials = mlmeRequest->Req.Join.NbTrials; + + // Reset variable JoinRequestTrials + JoinRequestTrials = 0; + + // Setup header information + macHdr.Value = 0; + macHdr.Bits.MType = FRAME_TYPE_JOIN_REQ; + + ResetMacParameters( ); + + altDr.NbTrials = JoinRequestTrials + 1; +#ifdef CONFIG_LINKWAN + altDr.joinmethod = mlmeRequest->Req.Join.method; + altDr.datarate = mlmeRequest->Req.Join.datarate; + LoRaMacParams.method = altDr.joinmethod; + LoRaMacParams.freqband = mlmeRequest->Req.Join.freqband; + LoRaMacParams.update_freqband = true; +#endif + LoRaMacParams.ChannelsDatarate = RegionAlternateDr( LoRaMacRegion, &altDr ); +#ifdef CONFIG_LORA_VERIFY + if (g_lora_debug == true) + PRINTF_RAW("MacHdr major:%d rfu:%d mtype:%d\r\n", macHdr.Bits.Major, macHdr.Bits.RFU, macHdr.Bits.MType); +#endif + status = Send( &macHdr, 0, NULL, 0 ); + break; + } + case MLME_LINK_CHECK: { + // Apply the request + LoRaMacFlags.Bits.MlmeReq = 1; + queueElement.Request = mlmeRequest->Type; + queueElement.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + queueElement.RestrictCommonReadyToHandle = false; + LoRaMacConfirmQueueAdd( &queueElement ); + + // LoRaMac will send this command piggy-pack + status = AddMacCommand( MOTE_MAC_LINK_CHECK_REQ, 0, 0 ); + break; + } + case MLME_TXCW: { + // Apply the request + LoRaMacFlags.Bits.MlmeReq = 1; + queueElement.Request = mlmeRequest->Type; + queueElement.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + queueElement.RestrictCommonReadyToHandle = false; + LoRaMacConfirmQueueAdd( &queueElement ); + + status = SetTxContinuousWave( mlmeRequest->Req.TxCw.Timeout ); + break; + } + case MLME_TXCW_1: + { + // Apply the request + LoRaMacFlags.Bits.MlmeReq = 1; + queueElement.Request = mlmeRequest->Type; + queueElement.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + queueElement.RestrictCommonReadyToHandle = false; + LoRaMacConfirmQueueAdd( &queueElement ); + + status = SetTxContinuousWave1( mlmeRequest->Req.TxCw.Timeout, mlmeRequest->Req.TxCw.Frequency, mlmeRequest->Req.TxCw.Power ); + break; + } + case MLME_DEVICE_TIME: + { + // Apply the request + LoRaMacFlags.Bits.MlmeReq = 1; + queueElement.Request = mlmeRequest->Type; + queueElement.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + queueElement.RestrictCommonReadyToHandle = false; + LoRaMacConfirmQueueAdd( &queueElement ); + + // LoRaMac will send this command piggy-pack + status = AddMacCommand( MOTE_MAC_DEVICE_TIME_REQ, 0, 0 ); + break; + } + case MLME_PING_SLOT_INFO: + { + uint8_t value = mlmeRequest->Req.PingSlotInfo.PingSlot.Value; + + // Apply the request + LoRaMacFlags.Bits.MlmeReq = 1; + queueElement.Request = mlmeRequest->Type; + queueElement.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + queueElement.RestrictCommonReadyToHandle = false; + LoRaMacConfirmQueueAdd( &queueElement ); + + // LoRaMac will send this command piggy-pack + LoRaMacClassBSetPingSlotInfo( mlmeRequest->Req.PingSlotInfo.PingSlot.Fields.Periodicity ); + + status = AddMacCommand( MOTE_MAC_PING_SLOT_INFO_REQ, value, 0 ); + break; + } + case MLME_BEACON_TIMING: + { + // Apply the request + LoRaMacFlags.Bits.MlmeReq = 1; + queueElement.Request = mlmeRequest->Type; + queueElement.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + queueElement.RestrictCommonReadyToHandle = false; + LoRaMacConfirmQueueAdd( &queueElement ); + + // LoRaMac will send this command piggy-pack + status = AddMacCommand( MOTE_MAC_BEACON_TIMING_REQ, 0, 0 ); + break; + } + case MLME_BEACON_ACQUISITION: + { + // Apply the request + LoRaMacFlags.Bits.MlmeReq = 1; + queueElement.Request = mlmeRequest->Type; + queueElement.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + queueElement.RestrictCommonReadyToHandle = true; + LoRaMacConfirmQueueAdd( &queueElement ); + + if( LoRaMacClassBIsAcquisitionInProgress( ) == false ) + { + // Start class B algorithm + LoRaMacClassBSetBeaconState( BEACON_STATE_ACQUISITION ); + LoRaMacClassBBeaconTimerEvent( ); + + status = LORAMAC_STATUS_OK; + } + else + { + status = LORAMAC_STATUS_BUSY; + } + break; + } + default: + break; + } + + if ( status != LORAMAC_STATUS_OK ) { + NodeAckRequested = false; + LoRaMacConfirmQueueRemoveLast( ); + if( LoRaMacConfirmQueueGetCnt( ) == 0 ) + { + LoRaMacFlags.Bits.MlmeReq = 0; + } + } + + return status; +} + +LoRaMacStatus_t LoRaMacMcpsRequest( McpsReq_t *mcpsRequest ) +{ + GetPhyParams_t getPhy; + PhyParam_t phyParam; + LoRaMacStatus_t status = LORAMAC_STATUS_SERVICE_UNKNOWN; + LoRaMacHeader_t macHdr; + VerifyParams_t verify; + uint8_t fPort = 0; + void *fBuffer; + uint16_t fBufferSize; + int8_t datarate; + bool readyToSend = false; + +#ifdef CONFIG_LORA_VERIFY + if (g_lora_debug) { + mcps_start_time = TimerGetCurrentTime( ); + } +#endif + if ( mcpsRequest == NULL ) { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + if ( ( ( LoRaMacState & LORAMAC_TX_RUNNING ) == LORAMAC_TX_RUNNING ) || + ( ( LoRaMacState & LORAMAC_TX_DELAYED ) == LORAMAC_TX_DELAYED ) ) { + return LORAMAC_STATUS_BUSY; + } + + macHdr.Value = 0; + memset1 ( ( uint8_t * ) &McpsConfirm, 0, sizeof( McpsConfirm ) ); + McpsConfirm.Status = LORAMAC_EVENT_INFO_STATUS_ERROR; + + // AckTimeoutRetriesCounter must be reset every time a new request (unconfirmed or confirmed) is performed. + AckTimeoutRetriesCounter = 1; + + switch ( mcpsRequest->Type ) { + case MCPS_UNCONFIRMED: { + readyToSend = true; + AckTimeoutRetries = 1; + + macHdr.Bits.MType = FRAME_TYPE_DATA_UNCONFIRMED_UP; + fPort = mcpsRequest->Req.Unconfirmed.fPort; + fBuffer = mcpsRequest->Req.Unconfirmed.fBuffer; + fBufferSize = mcpsRequest->Req.Unconfirmed.fBufferSize; + datarate = mcpsRequest->Req.Unconfirmed.Datarate; + break; + } + case MCPS_CONFIRMED: { + readyToSend = true; + AckTimeoutRetries = mcpsRequest->Req.Confirmed.NbTrials; + + macHdr.Bits.MType = FRAME_TYPE_DATA_CONFIRMED_UP; + fPort = mcpsRequest->Req.Confirmed.fPort; + fBuffer = mcpsRequest->Req.Confirmed.fBuffer; + fBufferSize = mcpsRequest->Req.Confirmed.fBufferSize; + datarate = mcpsRequest->Req.Confirmed.Datarate; + break; + } + case MCPS_PROPRIETARY: { + readyToSend = true; + AckTimeoutRetries = 1; + + macHdr.Bits.MType = FRAME_TYPE_PROPRIETARY; + fBuffer = mcpsRequest->Req.Proprietary.fBuffer; + fBufferSize = mcpsRequest->Req.Proprietary.fBufferSize; + datarate = mcpsRequest->Req.Proprietary.Datarate; + break; + } + default: + break; + } + + // Filter fPorts + if( IsFPortAllowed( fPort ) == false ) + { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + + // Get the minimum possible datarate + getPhy.Attribute = PHY_MIN_TX_DR; + getPhy.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + phyParam = RegionGetPhyParam( LoRaMacRegion, &getPhy ); + // Apply the minimum possible datarate. + // Some regions have limitations for the minimum datarate. + datarate = MAX( datarate, phyParam.Value ); + + if ( readyToSend == true ) { + if ( AdrCtrlOn == false ) { + verify.DatarateParams.Datarate = datarate; + verify.DatarateParams.UplinkDwellTime = LoRaMacParams.UplinkDwellTime; + + if ( RegionVerify( LoRaMacRegion, &verify, PHY_TX_DR ) == true ) { + LoRaMacParams.ChannelsDatarate = verify.DatarateParams.Datarate; + } else { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + } + + status = Send( &macHdr, fPort, fBuffer, fBufferSize ); + if ( status == LORAMAC_STATUS_OK ) { + McpsConfirm.McpsRequest = mcpsRequest->Type; + LoRaMacFlags.Bits.McpsReq = 1; + } else { + NodeAckRequested = false; + } + } + + return status; +} + +void LoRaMacTestRxWindowsOn( bool enable ) +{ + IsRxWindowsEnabled = enable; +} + +void LoRaMacTestSetMic( uint16_t txPacketCounter ) +{ + UpLinkCounter = txPacketCounter; + IsUpLinkCounterFixed = true; +} + +void LoRaMacTestSetDutyCycleOn( bool enable ) +{ + VerifyParams_t verify; + + verify.DutyCycle = enable; + + if ( RegionVerify( LoRaMacRegion, &verify, PHY_DUTY_CYCLE ) == true ) { + DutyCycleOn = enable; + } +} + +void LoRaMacTestSetChannel( uint8_t channel ) +{ + Channel = channel; +} + +#if 0 +static void SetPublicNetwork( bool enable ) +{ + PublicNetwork = enable; + Radio.SetModem( MODEM_LORA ); + if ( PublicNetwork == true ) { + // Change LoRa modem SyncWord + Radio.SetSyncWord( LORA_MAC_PUBLIC_SYNCWORD ); + } else { + // Change LoRa modem SyncWord + Radio.SetSyncWord( LORA_MAC_PRIVATE_SYNCWORD ); + } +} +#endif diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMac.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMac.h new file mode 100644 index 00000000..e7754781 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMac.h @@ -0,0 +1,2466 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file LoRaMac.h + * + * \brief LoRa MAC layer implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup LORAMAC LoRa MAC layer implementation + * This module specifies the API implementation of the LoRaMAC layer. + * This is a placeholder for a detailed description of the LoRaMac + * layer and the supported features. + * \{ + * + * \example classA/LoRaMote/main.c + * LoRaWAN class A application example for the LoRaMote. + * + * \example classB/LoRaMote/main.c + * LoRaWAN class B application example for the LoRaMote. + * + * \example classC/LoRaMote/main.c + * LoRaWAN class C application example for the LoRaMote. + */ +#ifndef __LORAMAC_H__ +#define __LORAMAC_H__ + +#include +#include +#include "timer.h" +#include "radio.h" +#include "timeServer.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Check the Mac layer state every MAC_STATE_CHECK_TIMEOUT in ms + */ +#define MAC_STATE_CHECK_TIMEOUT 1000 + +/*! + * Maximum number of times the MAC layer tries to get an acknowledge. + */ +#define MAX_ACK_RETRIES 8 + +/*! + * RSSI free threshold [dBm] + */ +#define RSSI_FREE_TH ( int8_t )( -90 ) + +/*! + * Frame direction definition for up-link communications + */ +#define UP_LINK 0 + +/*! + * Frame direction definition for down-link communications + */ +#define DOWN_LINK 1 + +/*! + * Sets the length of the LoRaMAC footer field. + * Mainly indicates the MIC field length + */ +#define LORAMAC_MFR_LEN 4 + +/*! + * LoRaMac MLME-Confirm queue length + */ +#define LORA_MAC_MLME_CONFIRM_QUEUE_LEN 5 + +/*! + * FRMPayload overhead to be used when setting the Radio.SetMaxPayloadLength + * in RxWindowSetup function. + * Maximum PHYPayload = MaxPayloadOfDatarate/MaxPayloadOfDatarateRepeater + LORA_MAC_FRMPAYLOAD_OVERHEAD + */ +#define LORA_MAC_FRMPAYLOAD_OVERHEAD 13 // MHDR(1) + FHDR(7) + Port(1) + MIC(4) + +/*! + * Syncword for Private LoRa networks + */ +#define LORA_MAC_PRIVATE_SYNCWORD 0x12 + +/*! + * Syncword for Public LoRa networks + */ +#define LORA_MAC_PUBLIC_SYNCWORD 0x34 + +/*! + * LoRaWAN devices classes definition + * + * LoRaWAN Specification V1.0.2, chapter 2.1 + */ +typedef enum eDeviceClass { + /*! + * LoRaWAN device class A + * + * LoRaWAN Specification V1.0.2, chapter 3 + */ + CLASS_A, + /*! + * LoRaWAN device class B + * + * LoRaWAN Specification V1.0.2, chapter 8 + */ + CLASS_B, + /*! + * LoRaWAN device class C + * + * LoRaWAN Specification V1.0.2, chapter 17 + */ + CLASS_C, +} DeviceClass_t; + +/*! + * LoRaMAC channels parameters definition + */ +typedef union uDrRange { + /*! + * Byte-access to the bits + */ + int8_t Value; + /*! + * Structure to store the minimum and the maximum datarate + */ + struct sFields { + /*! + * Minimum data rate + * + * LoRaWAN Regional Parameters V1.0.2rB + * + * The allowed ranges are region specific. Please refer to \ref DR_0 to \ref DR_15 for details. + */ + int8_t Min : 4; + /*! + * Maximum data rate + * + * LoRaWAN Regional Parameters V1.0.2rB + * + * The allowed ranges are region specific. Please refer to \ref DR_0 to \ref DR_15 for details. + */ + int8_t Max : 4; + } Fields; +} DrRange_t; + +/*! + * LoRaMAC band parameters definition + */ +typedef struct sBand { + /*! + * Duty cycle + */ + uint16_t DCycle; + /*! + * Maximum Tx power + */ + int8_t TxMaxPower; + /*! + * Time stamp of the last JoinReq Tx frame. + */ + TimerTime_t LastJoinTxDoneTime; + /*! + * Time stamp of the last Tx frame + */ + TimerTime_t LastTxDoneTime; + /*! + * Holds the time where the device is off + */ + TimerTime_t TimeOff; +} Band_t; + +/*! + * LoRaMAC channel definition + */ +typedef struct sChannelParams { + /*! + * Frequency in Hz + */ + uint32_t Frequency; + /*! + * Alternative frequency for RX window 1 + */ + uint32_t Rx1Frequency; + /*! + * Data rate definition + */ + DrRange_t DrRange; + /*! + * Band index + */ + uint8_t Band; +} ChannelParams_t; + +/*! + * LoRaMAC receive window 2 channel parameters + */ +typedef struct sRx2ChannelParams { + /*! + * Frequency in Hz + */ + uint32_t Frequency; + /*! + * Data rate + * + * LoRaWAN Regional Parameters V1.0.2rB + * + * The allowed ranges are region specific. Please refer to \ref DR_0 to \ref DR_15 for details. + */ + uint8_t Datarate; +} Rx2ChannelParams_t; + +/*! + * LoRaMAC receive window enumeration + */ +typedef enum eLoRaMacRxSlot +{ + /*! + * LoRaMAC receive window 1 + */ + RX_SLOT_WIN_1, + /*! + * LoRaMAC receive window 2 + */ + RX_SLOT_WIN_2, + /*! + * LoRaMAC receive window 2 for class c - continuous listening + */ + RX_SLOT_WIN_CLASS_C, + /*! + * LoRaMAC class b ping slot window + */ + RX_SLOT_WIN_PING_SLOT, + /*! + * LoRaMAC class b multicast slot window + */ + RX_SLOT_WIN_MULTICAST_SLOT, +}LoRaMacRxSlot_t; + +/*! + * Global MAC layer parameters + */ +typedef struct sLoRaMacParams { + /*! + * Channels TX power + */ + int8_t ChannelsTxPower; + /*! + * Channels data rate + */ + int8_t ChannelsDatarate; + /*! + * System overall timing error in milliseconds. + * [-SystemMaxRxError : +SystemMaxRxError] + * Default: +/-10 ms + */ + uint32_t SystemMaxRxError; + /*! + * Minimum required number of symbols to detect an Rx frame + * Default: 6 symbols + */ + uint8_t MinRxSymbols; + /*! + * LoRaMac maximum time a reception window stays open + */ + uint32_t MaxRxWindow; + /*! + * Receive delay 1 + */ + uint32_t ReceiveDelay1; + /*! + * Receive delay 2 + */ + uint32_t ReceiveDelay2; + /*! + * Join accept delay 1 + */ + uint32_t JoinAcceptDelay1; + /*! + * Join accept delay 1 + */ + uint32_t JoinAcceptDelay2; + /*! + * Number of uplink messages repetitions [1:15] (unconfirmed messages only) + */ + uint8_t ChannelsNbRep; + /*! + * Datarate offset between uplink and downlink on first window + */ + uint8_t Rx1DrOffset; + /*! + * LoRaMAC 2nd reception window settings + */ + Rx2ChannelParams_t Rx2Channel; + /*! + * Uplink dwell time configuration. 0: No limit, 1: 400ms + */ + uint8_t UplinkDwellTime; + /*! + * Downlink dwell time configuration. 0: No limit, 1: 400ms + */ + uint8_t DownlinkDwellTime; + /*! + * Maximum possible EIRP + */ + float MaxEirp; + /*! + * Antenna gain of the node + */ + float AntennaGain; + /*! + * Indicates if the node supports repeaters + */ + bool RepeaterSupport; + +#ifdef CONFIG_LINKWAN + uint8_t method; + uint8_t freqband; + bool update_freqband; +#endif +} LoRaMacParams_t; + +/*! + * LoRaMAC multicast channel parameter + */ +typedef struct sMulticastParams { + /*! + * Address + */ + uint32_t Address; + /*! + * Network session key + */ + uint8_t NwkSKey[16]; + /*! + * Application session key + */ + uint8_t AppSKey[16]; + /*! + * Downlink counter + */ + uint32_t DownLinkCounter; + /*! + * Reception frequency of the ping slot windows + */ + uint32_t Frequency; + /*! + * Datarate of the ping slot + */ + int8_t Datarate; + /*! + * This parameter is necessary for class b operation. It defines the + * periodicity of the multicast downlink slots + */ + uint16_t Periodicity; + /*! + * Number of multicast slots. The variable can be + * calculated as follows: + * PingNb = 128 / ( 1 << periodicity ), where + * 0 <= periodicity <= 7 + * This parameter will be calculated automatically. + */ + uint8_t PingNb; + /*! + * Period of the multicast slots. The variable can be + * calculated as follows: + * PingPeriod = 4096 / PingNb + * This parameter will be calculated automatically. + */ + uint16_t PingPeriod; + /*! + * Ping offset of the multicast channel for Class B + * This parameter will be calculated automatically. + */ + uint16_t PingOffset; + /*! + * Reference pointer to the next multicast channel parameters in the list + * This parameter will be calculated automatically. + */ + struct sMulticastParams *Next; +} MulticastParams_t; + +/*! + * LoRaMAC frame types + * + * LoRaWAN Specification V1.0.2, chapter 4.2.1, table 1 + */ +typedef enum eLoRaMacFrameType { + /*! + * LoRaMAC join request frame + */ + FRAME_TYPE_JOIN_REQ = 0x00, + /*! + * LoRaMAC join accept frame + */ + FRAME_TYPE_JOIN_ACCEPT = 0x01, + /*! + * LoRaMAC unconfirmed up-link frame + */ + FRAME_TYPE_DATA_UNCONFIRMED_UP = 0x02, + /*! + * LoRaMAC unconfirmed down-link frame + */ + FRAME_TYPE_DATA_UNCONFIRMED_DOWN = 0x03, + /*! + * LoRaMAC confirmed up-link frame + */ + FRAME_TYPE_DATA_CONFIRMED_UP = 0x04, + /*! + * LoRaMAC confirmed down-link frame + */ + FRAME_TYPE_DATA_CONFIRMED_DOWN = 0x05, + /*! + * LoRaMAC RFU frame + */ + FRAME_TYPE_RFU = 0x06, + /*! + * LoRaMAC proprietary frame + */ + FRAME_TYPE_PROPRIETARY = 0x07, +} LoRaMacFrameType_t; + +/*! + * LoRaMAC mote MAC commands + * + * LoRaWAN Specification V1.0.2, chapter 5, table 4 + */ +typedef enum eLoRaMacMoteCmd { + /*! + * LinkCheckReq + */ + MOTE_MAC_LINK_CHECK_REQ = 0x02, + /*! + * LinkADRAns + */ + MOTE_MAC_LINK_ADR_ANS = 0x03, + /*! + * DutyCycleAns + */ + MOTE_MAC_DUTY_CYCLE_ANS = 0x04, + /*! + * RXParamSetupAns + */ + MOTE_MAC_RX_PARAM_SETUP_ANS = 0x05, + /*! + * DevStatusAns + */ + MOTE_MAC_DEV_STATUS_ANS = 0x06, + /*! + * NewChannelAns + */ + MOTE_MAC_NEW_CHANNEL_ANS = 0x07, + /*! + * RXTimingSetupAns + */ + MOTE_MAC_RX_TIMING_SETUP_ANS = 0x08, + /*! + * TXParamSetupAns + */ + MOTE_MAC_TX_PARAM_SETUP_ANS = 0x09, + /*! + * DlChannelAns + */ + MOTE_MAC_DL_CHANNEL_ANS = 0x0A, + /*! + * DeviceTimeReq + */ + MOTE_MAC_DEVICE_TIME_REQ = 0x0D, + /*! + * PingSlotInfoReq + */ + MOTE_MAC_PING_SLOT_INFO_REQ = 0x10, + /*! + * PingSlotFreqAns + */ + MOTE_MAC_PING_SLOT_FREQ_ANS = 0x11, + /*! + * BeaconTimingReq + */ + MOTE_MAC_BEACON_TIMING_REQ = 0x12, + /*! + * BeaconFreqAns + */ + MOTE_MAC_BEACON_FREQ_ANS = 0x13, +} LoRaMacMoteCmd_t; + +/*! + * LoRaMAC server MAC commands + * + * LoRaWAN Specification V1.0.2 chapter 5, table 4 + */ +typedef enum eLoRaMacSrvCmd { + /*! + * LinkCheckAns + */ + SRV_MAC_LINK_CHECK_ANS = 0x02, + /*! + * LinkADRReq + */ + SRV_MAC_LINK_ADR_REQ = 0x03, + /*! + * DutyCycleReq + */ + SRV_MAC_DUTY_CYCLE_REQ = 0x04, + /*! + * RXParamSetupReq + */ + SRV_MAC_RX_PARAM_SETUP_REQ = 0x05, + /*! + * DevStatusReq + */ + SRV_MAC_DEV_STATUS_REQ = 0x06, + /*! + * NewChannelReq + */ + SRV_MAC_NEW_CHANNEL_REQ = 0x07, + /*! + * RXTimingSetupReq + */ + SRV_MAC_RX_TIMING_SETUP_REQ = 0x08, + /*! + * NewChannelReq + */ + SRV_MAC_TX_PARAM_SETUP_REQ = 0x09, + /*! + * DlChannelReq + */ + SRV_MAC_DL_CHANNEL_REQ = 0x0A, + /*! + * DeviceTimeAns + */ + SRV_MAC_DEVICE_TIME_ANS = 0x0D, + /*! + * PingSlotInfoAns + */ + SRV_MAC_PING_SLOT_INFO_ANS = 0x10, + /*! + * PingSlotChannelReq + */ + SRV_MAC_PING_SLOT_CHANNEL_REQ = 0x11, + /*! + * BeaconTimingAns + */ + SRV_MAC_BEACON_TIMING_ANS = 0x12, + /*! + * BeaconFreqReq + */ + SRV_MAC_BEACON_FREQ_REQ = 0x13, +} LoRaMacSrvCmd_t; + +/*! + * LoRaMAC Battery level indicator + */ +typedef enum eLoRaMacBatteryLevel { + /*! + * External power source + */ + BAT_LEVEL_EXT_SRC = 0x00, + /*! + * Battery level empty + */ + BAT_LEVEL_EMPTY = 0x01, + /*! + * Battery level full + */ + BAT_LEVEL_FULL = 0xFE, + /*! + * Battery level - no measurement available + */ + BAT_LEVEL_NO_MEASURE = 0xFF, +} LoRaMacBatteryLevel_t; + +/*! + * LoRaMAC header field definition (MHDR field) + * + * LoRaWAN Specification V1.0.2, chapter 4.2 + */ +typedef union uLoRaMacHeader { + /*! + * Byte-access to the bits + */ + uint8_t Value; + /*! + * Structure containing single access to header bits + */ + struct sHdrBits { + /*! + * Major version + */ + uint8_t Major : 2; + /*! + * RFU + */ + uint8_t RFU : 3; + /*! + * Message type + */ + uint8_t MType : 3; + } Bits; +} LoRaMacHeader_t; + +/*! + * LoRaMAC frame control field definition (FCtrl) + * + * LoRaWAN Specification V1.0.2, chapter 4.3.1 + */ +typedef union uLoRaMacFrameCtrl { + /*! + * Byte-access to the bits + */ + uint8_t Value; + /*! + * Structure containing single access to bits + */ + struct sCtrlBits { + /*! + * Frame options length + */ + uint8_t FOptsLen : 4; + /*! + * Frame pending bit + */ + uint8_t FPending : 1; + /*! + * Message acknowledge bit + */ + uint8_t Ack : 1; + /*! + * ADR acknowledgment request bit + */ + uint8_t AdrAckReq : 1; + /*! + * ADR control in frame header + */ + uint8_t Adr : 1; + } Bits; +} LoRaMacFrameCtrl_t; + +/*! + * LoRaMAC data structure for a PingSlotInfoReq \ref MLME_PING_SLOT_INFO + * + * LoRaWAN Specification + */ +typedef union uPingSlotInfo +{ + /*! + * Parameter for byte access + */ + uint8_t Value; + /*! + * Structure containing the parameters for the PingSlotInfoReq + */ + struct sInfoFields + { + /*! + * Periodicity = 0: ping slot every second + * Periodicity = 7: ping slot every 128 seconds + */ + uint8_t Periodicity : 3; + /*! + * RFU + */ + uint8_t RFU : 5; + }Fields; +}PingSlotInfo_t; + +/*! + * LoRaMAC data structure for the \ref MLME_BEACON MLME-Indication + * + * LoRaWAN Specification + */ +typedef struct sBeaconInfo +{ + /*! + * Timestamp in seconds since 00:00:00, Sunday 6th of January 1980 + * (start of the GPS epoch) modulo 2^32 + */ + uint32_t Time; + /*! + * Frequency + */ + uint32_t Frequency; + /*! + * Datarate + */ + uint8_t Datarate; + /*! + * RSSI + */ + int16_t Rssi; + /*! + * SNR + */ + uint8_t Snr; + /*! + * Data structure for the gateway specific part. The + * content of the values may differ for each gateway + */ + struct sGwSpecific + { + /*! + * Info descriptor - can differ for each gateway + */ + uint8_t InfoDesc; + /*! + * Info - can differ for each gateway + */ + uint8_t Info[6]; + }GwSpecific; +}BeaconInfo_t; + +/*! + * Enumeration containing the status of the operation of a MAC service + */ +typedef enum eLoRaMacEventInfoStatus { + /*! + * Service performed successfully + */ + LORAMAC_EVENT_INFO_STATUS_OK = 0, + /*! + * An error occurred during the execution of the service + */ + LORAMAC_EVENT_INFO_STATUS_ERROR, + /*! + * A Tx timeout occurred + */ + LORAMAC_EVENT_INFO_STATUS_TX_TIMEOUT, + /*! + * An Rx timeout occurred on receive window 1 + */ + LORAMAC_EVENT_INFO_STATUS_RX1_TIMEOUT, + /*! + * An Rx timeout occurred on receive window 2 + */ + LORAMAC_EVENT_INFO_STATUS_RX2_TIMEOUT, + /*! + * An Rx error occurred on receive window 1 + */ + LORAMAC_EVENT_INFO_STATUS_RX1_ERROR, + /*! + * An Rx error occurred on receive window 2 + */ + LORAMAC_EVENT_INFO_STATUS_RX2_ERROR, + /*! + * An error occurred in the join procedure + */ + LORAMAC_EVENT_INFO_STATUS_JOIN_FAIL, + /*! + * A frame with an invalid downlink counter was received. The + * downlink counter of the frame was equal to the local copy + * of the downlink counter of the node. + */ + LORAMAC_EVENT_INFO_STATUS_DOWNLINK_REPEATED, + /*! + * The MAC could not retransmit a frame since the MAC decreased the datarate. The + * payload size is not applicable for the datarate. + */ + LORAMAC_EVENT_INFO_STATUS_TX_DR_PAYLOAD_SIZE_ERROR, + /*! + * The node has lost MAX_FCNT_GAP or more frames. + */ + LORAMAC_EVENT_INFO_STATUS_DOWNLINK_TOO_MANY_FRAMES_LOSS, + /*! + * An address error occurred + */ + LORAMAC_EVENT_INFO_STATUS_ADDRESS_FAIL, + /*! + * message integrity check failure + */ + LORAMAC_EVENT_INFO_STATUS_MIC_FAIL, + /*! + * ToDo + */ + LORAMAC_EVENT_INFO_STATUS_MULTICAST_FAIL, + /*! + * ToDo + */ + LORAMAC_EVENT_INFO_STATUS_BEACON_LOCKED, + /*! + * ToDo + */ + LORAMAC_EVENT_INFO_STATUS_BEACON_LOST, + /*! + * ToDo + */ + LORAMAC_EVENT_INFO_STATUS_BEACON_NOT_FOUND, +} LoRaMacEventInfoStatus_t; + +/*! + * LoRaMac tx/rx operation state + */ +typedef union eLoRaMacFlags_t { + /*! + * Byte-access to the bits + */ + uint8_t Value; + /*! + * Structure containing single access to bits + */ + struct sMacFlagBits { + /*! + * MCPS-Req pending + */ + uint8_t McpsReq : 1; + /*! + * MCPS-Ind pending + */ + uint8_t McpsInd : 1; + /*! + * MCPS-Ind pending. Skip indication to the application layer + */ + uint8_t McpsIndSkip : 1; + /*! + * MLME-Req pending + */ + uint8_t MlmeReq : 1; + /*! + * MLME-Ind pending + */ + uint8_t MlmeInd : 1; + /*! + * MAC cycle done + */ + uint8_t MacDone : 1; + } Bits; +} LoRaMacFlags_t; + +/*! + * + * \brief LoRaMAC data services + * + * \details The following table list the primitives which are supported by the + * specific MAC data service: + * + * Name | Request | Indication | Response | Confirm + * --------------------- | :-----: | :--------: | :------: | :-----: + * \ref MCPS_UNCONFIRMED | YES | YES | NO | YES + * \ref MCPS_CONFIRMED | YES | YES | NO | YES + * \ref MCPS_MULTICAST | NO | YES | NO | NO + * \ref MCPS_PROPRIETARY | YES | YES | NO | YES + * + * The following table provides links to the function implementations of the + * related MCPS primitives: + * + * Primitive | Function + * ---------------- | :---------------------: + * MCPS-Request | \ref LoRaMacMlmeRequest + * MCPS-Confirm | MacMcpsConfirm in \ref LoRaMacPrimitives_t + * MCPS-Indication | MacMcpsIndication in \ref LoRaMacPrimitives_t + */ +typedef enum eMcps { + /*! + * Unconfirmed LoRaMAC frame + */ + MCPS_UNCONFIRMED, + /*! + * Confirmed LoRaMAC frame + */ + MCPS_CONFIRMED, + /*! + * Multicast LoRaMAC frame + */ + MCPS_MULTICAST, + /*! + * Proprietary frame + */ + MCPS_PROPRIETARY, +} Mcps_t; + +/*! + * LoRaMAC MCPS-Request for an unconfirmed frame + */ +typedef struct sMcpsReqUnconfirmed { + /*! + * Frame port field. Must be set if the payload is not empty. Use the + * application specific frame port values: [1...223] + * + * LoRaWAN Specification V1.0.2, chapter 4.3.2 + */ + uint8_t fPort; + /*! + * Pointer to the buffer of the frame payload + */ + void *fBuffer; + /*! + * Size of the frame payload + */ + uint16_t fBufferSize; + /*! + * Uplink datarate, if ADR is off + */ + int8_t Datarate; +} McpsReqUnconfirmed_t; + +/*! + * LoRaMAC MCPS-Request for a confirmed frame + */ +typedef struct sMcpsReqConfirmed { + /*! + * Frame port field. Must be set if the payload is not empty. Use the + * application specific frame port values: [1...223] + * + * LoRaWAN Specification V1.0.2, chapter 4.3.2 + */ + uint8_t fPort; + /*! + * Pointer to the buffer of the frame payload + */ + void *fBuffer; + /*! + * Size of the frame payload + */ + uint16_t fBufferSize; + /*! + * Uplink datarate, if ADR is off + */ + int8_t Datarate; + /*! + * Number of trials to transmit the frame, if the LoRaMAC layer did not + * receive an acknowledgment. The MAC performs a datarate adaptation, + * according to the LoRaWAN Specification V1.0.2, chapter 18.4, according + * to the following table: + * + * Transmission nb | Data Rate + * ----------------|----------- + * 1 (first) | DR + * 2 | DR + * 3 | max(DR-1,0) + * 4 | max(DR-1,0) + * 5 | max(DR-2,0) + * 6 | max(DR-2,0) + * 7 | max(DR-3,0) + * 8 | max(DR-3,0) + * + * Note, that if NbTrials is set to 1 or 2, the MAC will not decrease + * the datarate, in case the LoRaMAC layer did not receive an acknowledgment + */ + uint8_t NbTrials; +} McpsReqConfirmed_t; + +/*! + * LoRaMAC MCPS-Request for a proprietary frame + */ +typedef struct sMcpsReqProprietary { + /*! + * Pointer to the buffer of the frame payload + */ + void *fBuffer; + /*! + * Size of the frame payload + */ + uint16_t fBufferSize; + /*! + * Uplink datarate, if ADR is off + */ + int8_t Datarate; +} McpsReqProprietary_t; + +/*! + * LoRaMAC MCPS-Request structure + */ +typedef struct sMcpsReq { + /*! + * MCPS-Request type + */ + Mcps_t Type; + + /*! + * MCPS-Request parameters + */ + union uMcpsParam { + /*! + * MCPS-Request parameters for an unconfirmed frame + */ + McpsReqUnconfirmed_t Unconfirmed; + /*! + * MCPS-Request parameters for a confirmed frame + */ + McpsReqConfirmed_t Confirmed; + /*! + * MCPS-Request parameters for a proprietary frame + */ + McpsReqProprietary_t Proprietary; + } Req; +} McpsReq_t; + +/*! + * LoRaMAC MCPS-Confirm + */ +typedef struct sMcpsConfirm { + /*! + * Holds the previously performed MCPS-Request + */ + Mcps_t McpsRequest; + /*! + * Status of the operation + */ + LoRaMacEventInfoStatus_t Status; + /*! + * Uplink datarate + */ + uint8_t Datarate; + /*! + * Transmission power + */ + int8_t TxPower; + /*! + * Set if an acknowledgement was received + */ + bool AckReceived; + /*! + * Provides the number of retransmissions + */ + uint8_t NbRetries; + /*! + * The transmission time on air of the frame + */ + TimerTime_t TxTimeOnAir; + /*! + * The uplink counter value related to the frame + */ + uint32_t UpLinkCounter; + /*! + * The uplink channel related to the frame + */ + uint32_t Channel; +} McpsConfirm_t; + +/*! + * LoRaMAC MCPS-Indication primitive + */ +typedef struct sMcpsIndication { + /*! + * MCPS-Indication type + */ + Mcps_t McpsIndication; + /*! + * Status of the operation + */ + LoRaMacEventInfoStatus_t Status; + /*! + * Multicast + */ + uint8_t Multicast; + /*! + * Application port + */ + uint8_t Port; + /*! + * Downlink datarate + */ + uint8_t RxDatarate; + /*! + * Frame pending status + */ + uint8_t FramePending; + /*! + * Pointer to the received data stream + */ + uint8_t *Buffer; + /*! + * Size of the received data stream + */ + uint8_t BufferSize; + /*! + * Indicates, if data is available + */ + bool RxData; + /*! + * Rssi of the received packet + */ + int16_t Rssi; + /*! + * Snr of the received packet + */ + int8_t Snr; + /*! + * Receive window + */ + LoRaMacRxSlot_t RxSlot; + /*! + * Set if an acknowledgement was received + */ + bool AckReceived; + /*! + * The downlink counter value for the received frame + */ + uint32_t DownLinkCounter; +#ifdef CONFIG_LWAN + bool DevTimeAnsReceived; + bool LinkCheckAnsReceived; + bool UplinkNeeded; +#endif +} McpsIndication_t; + +/*! + * \brief LoRaMAC management services + * + * \details The following table list the primitives which are supported by the + * specific MAC management service: + * + * Name | Request | Indication | Response | Confirm + * --------------------- | :-----: | :--------: | :------: | :-----: + * \ref MLME_JOIN | YES | NO | NO | YES + * \ref MLME_LINK_CHECK | YES | NO | NO | YES + * \ref MLME_TXCW | YES | NO | NO | YES + * \ref MLME_SCHEDULE_UPLINK | NO | YES | NO | NO + * + * The following table provides links to the function implementations of the + * related MLME primitives. + * + * Primitive | Function + * ---------------- | :---------------------: + * MLME-Request | \ref LoRaMacMlmeRequest + * MLME-Confirm | MacMlmeConfirm in \ref LoRaMacPrimitives_t + * MLME-Indication | MacMlmeIndication in \ref LoRaMacPrimitives_t + */ +typedef enum eMlme { + /*! + * Initiates the Over-the-Air activation + * + * LoRaWAN Specification V1.0.2, chapter 6.2 + */ + MLME_JOIN, + /*! + * LinkCheckReq - Connectivity validation + * + * LoRaWAN Specification V1.0.2, chapter 5, table 4 + */ + MLME_LINK_CHECK, + /*! + * Sets Tx continuous wave mode + * + * LoRaWAN end-device certification + */ + MLME_TXCW, + /*! + * Sets Tx continuous wave mode (new LoRa-Alliance CC definition) + * + * LoRaWAN end-device certification + */ + MLME_TXCW_1, + /*! + * Indicates that the application shall perform an uplink as + * soon as possible. + */ + MLME_SCHEDULE_UPLINK, + /*! + * Initiates a DeviceTimeReq + * + * LoRaWAN end-device certification + */ + MLME_DEVICE_TIME, + /*! + * The MAC uses this MLME primitive to indicate a beacon reception + * status. + * + * LoRaWAN end-device certification + */ + MLME_BEACON, + /*! + * Initiate a beacon acquisition. The MAC will search for a beacon. + * It will search for XX_BEACON_INTERVAL milliseconds. + * + * LoRaWAN end-device certification + */ + MLME_BEACON_ACQUISITION, + /*! + * Initiates a PingSlotInfoReq + * + * LoRaWAN end-device certification + */ + MLME_PING_SLOT_INFO, + /*! + * Initiates a BeaconTimingReq + * + * LoRaWAN end-device certification + */ + MLME_BEACON_TIMING, + /*! + * Primitive which indicates that the beacon has been lost + * + * \remark The upper layer is required to switch the device class to ClassA + * + * LoRaWAN end-device certification + */ + MLME_BEACON_LOST, +} Mlme_t; + +/*! + * LoRaMAC MLME-Request for the join service + */ +typedef struct sMlmeReqJoin { + /*! + * Globally unique end-device identifier + * + * LoRaWAN Specification V1.0.2, chapter 6.2.1 + */ + uint8_t *DevEui; + /*! + * Application identifier + * + * LoRaWAN Specification V1.0.2, chapter 6.1.2 + */ + uint8_t *AppEui; + /*! + * AES-128 application key + * + * LoRaWAN Specification V1.0.2, chapter 6.2.2 + */ + uint8_t *AppKey; + /*! + * Number of trials for the join request. + */ + uint8_t NbTrials; + +#ifdef CONFIG_LINKWAN + int8_t datarate; + uint8_t method; + uint8_t freqband; +#endif +} MlmeReqJoin_t; + +/*! + * LoRaMAC MLME-Request for the ping slot info service + */ +typedef struct sMlmeReqPingSlotInfo +{ + PingSlotInfo_t PingSlot; +}MlmeReqPingSlotInfo_t; + +/*! + * LoRaMAC MLME-Request for Tx continuous wave mode + */ +typedef struct sMlmeReqTxCw { + /*! + * Time in seconds while the radio is kept in continuous wave mode + */ + uint16_t Timeout; + /*! + * RF frequency to set (Only used with new way) + */ + uint32_t Frequency; + /*! + * RF output power to set (Only used with new way) + */ + uint8_t Power; +} MlmeReqTxCw_t; + +/*! + * LoRaMAC MLME-Request structure + */ +typedef struct sMlmeReq { + /*! + * MLME-Request type + */ + Mlme_t Type; + + /*! + * MLME-Request parameters + */ + union uMlmeParam { + /*! + * MLME-Request parameters for a join request + */ + MlmeReqJoin_t Join; + /*! + * MLME-Request parameters for a ping slot info request + */ + MlmeReqPingSlotInfo_t PingSlotInfo; + /*! + * MLME-Request parameters for Tx continuous mode request + */ + MlmeReqTxCw_t TxCw; + } Req; +} MlmeReq_t; + +/*! + * LoRaMAC MLME-Confirm primitive + */ +typedef struct sMlmeConfirm { + /*! + * Holds the previously performed MLME-Request + */ + Mlme_t MlmeRequest; + /*! + * Status of the operation + */ + LoRaMacEventInfoStatus_t Status; +#ifdef CONFIG_LWAN + /*! + * Rssi of the received packet + */ + int16_t Rssi; + /*! + * Snr of the received packet + */ + int8_t Snr; +#endif + /*! + * The transmission time on air of the frame + */ + TimerTime_t TxTimeOnAir; + /*! + * Demodulation margin. Contains the link margin [dB] of the last + * successfully received LinkCheckReq + */ + uint8_t DemodMargin; + /*! + * Number of gateways which received the last LinkCheckReq + */ + uint8_t NbGateways; + /*! + * Provides the number of retransmissions + */ + uint8_t NbRetries; + /*! + * The delay which we have received through the + * BeaconTimingAns + */ + TimerTime_t BeaconTimingDelay; + /*! + * The channel of the next beacon + */ + uint8_t BeaconTimingChannel; +} MlmeConfirm_t; + +/*! + * LoRaMAC MLME-Indication primitive + */ +typedef struct sMlmeIndication +{ + /*! + * Holds the previously performed MLME-Request + */ + Mlme_t MlmeIndication; + /*! + * Status of the operation + */ + LoRaMacEventInfoStatus_t Status; + /*! + * Beacon information. Only valid for \ref MLME_BEACON, + * status \ref LORAMAC_EVENT_INFO_STATUS_BEACON_LOCKED + */ + BeaconInfo_t BeaconInfo; +}MlmeIndication_t; +/*! + * LoRa Mac Information Base (MIB) + * + * The following table lists the MIB parameters and the related attributes: + * + * Attribute | Get | Set + * --------------------------------- | :-: | :-: + * \ref MIB_DEVICE_CLASS | YES | YES + * \ref MIB_NETWORK_JOINED | YES | YES + * \ref MIB_ADR | YES | YES + * \ref MIB_NET_ID | YES | YES + * \ref MIB_DEV_ADDR | YES | YES + * \ref MIB_NWK_SKEY | YES | YES + * \ref MIB_APP_SKEY | YES | YES + * \ref MIB_PUBLIC_NETWORK | YES | YES + * \ref MIB_REPEATER_SUPPORT | YES | YES + * \ref MIB_CHANNELS | YES | NO + * \ref MIB_RX2_CHANNEL | YES | YES + * \ref MIB_CHANNELS_MASK | YES | YES + * \ref MIB_CHANNELS_DEFAULT_MASK | YES | YES + * \ref MIB_CHANNELS_NB_REP | YES | YES + * \ref MIB_MAX_RX_WINDOW_DURATION | YES | YES + * \ref MIB_RECEIVE_DELAY_1 | YES | YES + * \ref MIB_RECEIVE_DELAY_2 | YES | YES + * \ref MIB_JOIN_ACCEPT_DELAY_1 | YES | YES + * \ref MIB_JOIN_ACCEPT_DELAY_2 | YES | YES + * \ref MIB_CHANNELS_DATARATE | YES | YES + * \ref MIB_CHANNELS_DEFAULT_DATARATE| YES | YES + * \ref MIB_CHANNELS_TX_POWER | YES | YES + * \ref MIB_CHANNELS_DEFAULT_TX_POWER| YES | YES + * \ref MIB_UPLINK_COUNTER | YES | YES + * \ref MIB_DOWNLINK_COUNTER | YES | YES + * \ref MIB_MULTICAST_CHANNEL | YES | NO + * \ref MIB_SYSTEM_MAX_RX_ERROR | YES | YES + * \ref MIB_MIN_RX_SYMBOLS | YES | YES + * \ref MIB_BEACON_INTERVAL | YES | YES + * \ref MIB_BEACON_RESERVED | YES | YES + * \ref MIB_BEACON_GUARD | YES | YES + * \ref MIB_BEACON_WINDOW | YES | YES + * \ref MIB_BEACON_WINDOW_SLOTS | YES | YES + * \ref MIB_PING_SLOT_WINDOW | YES | YES + * \ref MIB_BEACON_SYMBOL_TO_DEFAULT | YES | YES + * \ref MIB_BEACON_SYMBOL_TO_EXPANSION_MAX | YES | YES + * \ref MIB_PING_SLOT_SYMBOL_TO_EXPANSION_MAX | YES | YES + * \ref MIB_BEACON_SYMBOL_TO_EXPANSION_FACTOR | YES | YES + * \ref MIB_PING_SLOT_SYMBOL_TO_EXPANSION_FACTOR | YES | YES + * \ref MIB_MAX_BEACON_LESS_PERIOD | YES | YES + * \ref MIB_ANTENNA_GAIN | YES | YES + * \ref MIB_DEFAULT_ANTENNA_GAIN | YES | YES + * \ref MIB_FREQ_BAND | YES | NO + * + * The following table provides links to the function implementations of the + * related MIB primitives: + * + * Primitive | Function + * ---------------- | :---------------------: + * MIB-Set | \ref LoRaMacMibSetRequestConfirm + * MIB-Get | \ref LoRaMacMibGetRequestConfirm + */ +typedef enum eMib { + /*! + * LoRaWAN device class + * + * LoRaWAN Specification V1.0.2 + */ + MIB_DEVICE_CLASS, + /*! + * LoRaWAN Network joined attribute + * + * LoRaWAN Specification V1.0.2 + */ + MIB_NETWORK_JOINED, + /*! + * Adaptive data rate + * + * LoRaWAN Specification V1.0.2, chapter 4.3.1.1 + * + * [true: ADR enabled, false: ADR disabled] + */ + MIB_ADR, + /*! + * Network identifier + * + * LoRaWAN Specification V1.0.2, chapter 6.1.1 + */ + MIB_NET_ID, + /*! + * End-device address + * + * LoRaWAN Specification V1.0.2, chapter 6.1.1 + */ + MIB_DEV_ADDR, + /*! + * Network session key + * + * LoRaWAN Specification V1.0.2, chapter 6.1.3 + */ + MIB_NWK_SKEY, + /*! + * Application session key + * + * LoRaWAN Specification V1.0.2, chapter 6.1.4 + */ + MIB_APP_SKEY, + /*! + * Set the network type to public or private + * + * LoRaWAN Regional Parameters V1.0.2rB + * + * [true: public network, false: private network] + */ + MIB_PUBLIC_NETWORK, + /*! + * Support the operation with repeaters + * + * LoRaWAN Regional Parameters V1.0.2rB + * + * [true: repeater support enabled, false: repeater support disabled] + */ + MIB_REPEATER_SUPPORT, + /*! + * Communication channels. A get request will return a + * pointer which references the first entry of the channel list. The + * list is of size LORA_MAX_NB_CHANNELS + * + * LoRaWAN Regional Parameters V1.0.2rB + */ + MIB_CHANNELS, + /*! + * Set receive window 2 channel + * + * LoRaWAN Specification V1.0.2, chapter 3.3.1 + */ + MIB_RX2_CHANNEL, + /*! + * Set receive window 2 channel + * + * LoRaWAN Specification V1.0.2, chapter 3.3.2 + */ + MIB_RX2_DEFAULT_CHANNEL, + /*! + * LoRaWAN channels mask + * + * LoRaWAN Regional Parameters V1.0.2rB + */ + MIB_CHANNELS_MASK, + /*! + * LoRaWAN default channels mask + * + * LoRaWAN Regional Parameters V1.0.2rB + */ + MIB_CHANNELS_DEFAULT_MASK, + /*! + * Set the number of repetitions on a channel + * + * LoRaWAN Specification V1.0.2, chapter 5.2 + */ + MIB_CHANNELS_NB_REP, + /*! + * Maximum receive window duration in [ms] + * + * LoRaWAN Specification V1.0.2, chapter 3.3.3 + */ + MIB_MAX_RX_WINDOW_DURATION, + /*! + * Receive delay 1 in [ms] + * + * LoRaWAN Regional Parameters V1.0.2rB + */ + MIB_RECEIVE_DELAY_1, + /*! + * Receive delay 2 in [ms] + * + * LoRaWAN Regional Parameters V1.0.2rB + */ + MIB_RECEIVE_DELAY_2, + /*! + * Join accept delay 1 in [ms] + * + * LoRaWAN Regional Parameters V1.0.2rB + */ + MIB_JOIN_ACCEPT_DELAY_1, + /*! + * Join accept delay 2 in [ms] + * + * LoRaWAN Regional Parameters V1.0.2rB + */ + MIB_JOIN_ACCEPT_DELAY_2, + /*! + * Default Data rate of a channel + * + * LoRaWAN Regional Parameters V1.0.2rB + * + * The allowed ranges are region specific. Please refer to \ref DR_0 to \ref DR_15 for details. + */ + MIB_CHANNELS_DEFAULT_DATARATE, + /*! + * Data rate of a channel + * + * LoRaWAN Regional Parameters V1.0.2rB + * + * The allowed ranges are region specific. Please refer to \ref DR_0 to \ref DR_15 for details. + */ + MIB_CHANNELS_DATARATE, + /*! + * Transmission power of a channel + * + * LoRaWAN Regional Parameters V1.0.2rB + * + * The allowed ranges are region specific. Please refer to \ref TX_POWER_0 to \ref TX_POWER_15 for details. + */ + MIB_CHANNELS_TX_POWER, + /*! + * Transmission power of a channel + * + * LoRaWAN Regional Parameters V1.0.2rB + * + * The allowed ranges are region specific. Please refer to \ref TX_POWER_0 to \ref TX_POWER_15 for details. + */ + MIB_CHANNELS_DEFAULT_TX_POWER, + /*! + * LoRaWAN Up-link counter + * + * LoRaWAN Specification V1.0.2, chapter 4.3.1.5 + */ + MIB_UPLINK_COUNTER, + /*! + * LoRaWAN Down-link counter + * + * LoRaWAN Specification V1.0.2, chapter 4.3.1.5 + */ + MIB_DOWNLINK_COUNTER, + /*! + * Multicast channels. A get request will return a pointer to the first + * entry of the multicast channel linked list. If the pointer is equal to + * NULL, the list is empty. + */ + MIB_MULTICAST_CHANNEL, + MIB_MULTICAST_CHANNEL_DEL, + /*! + * System overall timing error in milliseconds. + * [-SystemMaxRxError : +SystemMaxRxError] + * Default: +/-10 ms + */ + MIB_SYSTEM_MAX_RX_ERROR, + /*! + * Minimum required number of symbols to detect an Rx frame + * Default: 6 symbols + */ + MIB_MIN_RX_SYMBOLS, + /*! + * Antenna gain of the node. Default value is region specific. + * The antenna gain is used to calculate the TX power of the node. + * The formula is: + * radioTxPower = ( int8_t )floor( maxEirp - antennaGain ) + */ + MIB_ANTENNA_GAIN, + /*! + * Default antenna gain of the node. Default value is region specific. + * The antenna gain is used to calculate the TX power of the node. + * The formula is: + * radioTxPower = ( int8_t )floor( maxEirp - antennaGain ) + */ + MIB_DEFAULT_ANTENNA_GAIN, + /*! + * Beacon interval in ms + */ + MIB_BEACON_INTERVAL, + /*! + * Beacon reserved time in ms + */ + MIB_BEACON_RESERVED, + /*! + * Beacon guard time in ms + */ + MIB_BEACON_GUARD, + /*! + * Beacon window time in ms + */ + MIB_BEACON_WINDOW, + /*! + * Beacon window time in number of slots + */ + MIB_BEACON_WINDOW_SLOTS, + /*! + * Ping slot length time in ms + */ + MIB_PING_SLOT_WINDOW, + /*! + * Default symbol timeout for beacons and ping slot windows + */ + MIB_BEACON_SYMBOL_TO_DEFAULT, + /*! + * Maximum symbol timeout for beacons + */ + MIB_BEACON_SYMBOL_TO_EXPANSION_MAX, + /*! + * Maximum symbol timeout for ping slots + */ + MIB_PING_SLOT_SYMBOL_TO_EXPANSION_MAX, + /*! + * Symbol expansion value for beacon windows in case of beacon + * loss in symbols + */ + MIB_BEACON_SYMBOL_TO_EXPANSION_FACTOR, + /*! + * Symbol expansion value for ping slot windows in case of beacon + * loss in symbols + */ + MIB_PING_SLOT_SYMBOL_TO_EXPANSION_FACTOR, + /*! + * Maximum allowed beacon less time in ms + */ + MIB_MAX_BEACON_LESS_PERIOD, + /*! + * Ping slot data rate + * + * LoRaWAN Regional Parameters V1.0.2rB + * + * The allowed ranges are region specific. Please refer to \ref DR_0 to \ref DR_15 for details. + */ + MIB_PING_SLOT_DATARATE, + +#ifdef CONFIG_LWAN + MIB_RX1_DATARATE_OFFSET, + MIB_MAC_STATE, +#endif + +#ifdef CONFIG_LINKWAN + MIB_FREQ_BAND +#endif +} Mib_t; + +/*! + * LoRaMAC MIB parameters + */ +typedef union uMibParam { + /*! + * LoRaWAN device class + * + * Related MIB type: \ref MIB_DEVICE_CLASS + */ + DeviceClass_t Class; + /*! + * LoRaWAN network joined attribute + * + * Related MIB type: \ref MIB_NETWORK_JOINED + */ + bool IsNetworkJoined; + /*! + * Activation state of ADR + * + * Related MIB type: \ref MIB_ADR + */ + bool AdrEnable; + /*! + * Network identifier + * + * Related MIB type: \ref MIB_NET_ID + */ + uint32_t NetID; + /*! + * End-device address + * + * Related MIB type: \ref MIB_DEV_ADDR + */ + uint32_t DevAddr; + /*! + * Network session key + * + * Related MIB type: \ref MIB_NWK_SKEY + */ + uint8_t *NwkSKey; + /*! + * Application session key + * + * Related MIB type: \ref MIB_APP_SKEY + */ + uint8_t *AppSKey; + /*! + * Enable or disable a public network + * + * Related MIB type: \ref MIB_PUBLIC_NETWORK + */ + bool EnablePublicNetwork; + /*! + * Enable or disable repeater support + * + * Related MIB type: \ref MIB_REPEATER_SUPPORT + */ + bool EnableRepeaterSupport; + /*! + * LoRaWAN Channel + * + * Related MIB type: \ref MIB_CHANNELS + */ + ChannelParams_t *ChannelList; + /*! + * Channel for the receive window 2 + * + * Related MIB type: \ref MIB_RX2_CHANNEL + */ + Rx2ChannelParams_t Rx2Channel; + /*! + * Channel for the receive window 2 + * + * Related MIB type: \ref MIB_RX2_DEFAULT_CHANNEL + */ + Rx2ChannelParams_t Rx2DefaultChannel; + /*! + * Channel mask + * + * Related MIB type: \ref MIB_CHANNELS_MASK + */ + uint16_t *ChannelsMask; + /*! + * Default channel mask + * + * Related MIB type: \ref MIB_CHANNELS_DEFAULT_MASK + */ + uint16_t *ChannelsDefaultMask; + /*! + * Number of frame repetitions + * + * Related MIB type: \ref MIB_CHANNELS_NB_REP + */ + uint8_t ChannelNbRep; + /*! + * Maximum receive window duration + * + * Related MIB type: \ref MIB_MAX_RX_WINDOW_DURATION + */ + uint32_t MaxRxWindow; + /*! + * Receive delay 1 + * + * Related MIB type: \ref MIB_RECEIVE_DELAY_1 + */ + uint32_t ReceiveDelay1; + /*! + * Receive delay 2 + * + * Related MIB type: \ref MIB_RECEIVE_DELAY_2 + */ + uint32_t ReceiveDelay2; + /*! + * Join accept delay 1 + * + * Related MIB type: \ref MIB_JOIN_ACCEPT_DELAY_1 + */ + uint32_t JoinAcceptDelay1; + /*! + * Join accept delay 2 + * + * Related MIB type: \ref MIB_JOIN_ACCEPT_DELAY_2 + */ + uint32_t JoinAcceptDelay2; + /*! + * Channels data rate + * + * Related MIB type: \ref MIB_CHANNELS_DEFAULT_DATARATE + */ + int8_t ChannelsDefaultDatarate; + /*! + * Channels data rate + * + * Related MIB type: \ref MIB_CHANNELS_DATARATE + */ + int8_t ChannelsDatarate; + /*! + * Channels TX power + * + * Related MIB type: \ref MIB_CHANNELS_DEFAULT_TX_POWER + */ + int8_t ChannelsDefaultTxPower; + /*! + * Channels TX power + * + * Related MIB type: \ref MIB_CHANNELS_TX_POWER + */ + int8_t ChannelsTxPower; + /*! + * LoRaWAN Up-link counter + * + * Related MIB type: \ref MIB_UPLINK_COUNTER + */ + uint32_t UpLinkCounter; + /*! + * LoRaWAN Down-link counter + * + * Related MIB type: \ref MIB_DOWNLINK_COUNTER + */ + uint32_t DownLinkCounter; + /*! + * Multicast channel + * + * Related MIB type: \ref MIB_MULTICAST_CHANNEL + */ + MulticastParams_t *MulticastList; + /*! + * System overall timing error in milliseconds. + * + * Related MIB type: \ref MIB_SYSTEM_MAX_RX_ERROR + */ + uint32_t SystemMaxRxError; + /*! + * Minimum required number of symbols to detect an Rx frame + * + * Related MIB type: \ref MIB_MIN_RX_SYMBOLS + */ + uint8_t MinRxSymbols; + /*! + * Antenna gain + * + * Related MIB type: \ref MIB_ANTENNA_GAIN + */ + float AntennaGain; + /*! + * Default antenna gain + * + * Related MIB type: \ref MIB_DEFAULT_ANTENNA_GAIN + */ + float DefaultAntennaGain; + /*! + * Beacon interval in ms + * + * Related MIB type: \ref MIB_BEACON_INTERVAL + */ + uint32_t BeaconInterval; + /*! + * Beacon reserved time in ms + * + * Related MIB type: \ref MIB_BEACON_RESERVED + */ + uint32_t BeaconReserved; + /*! + * Beacon guard time in ms + * + * Related MIB type: \ref MIB_BEACON_GUARD + */ + uint32_t BeaconGuard; + /*! + * Beacon window time in ms + * + * Related MIB type: \ref MIB_BEACON_WINDOW + */ + uint32_t BeaconWindow; + /*! + * Beacon window time in number of slots + * + * Related MIB type: \ref MIB_BEACON_WINDOW_SLOTS + */ + uint32_t BeaconWindowSlots; + /*! + * Ping slot length time in ms + * + * Related MIB type: \ref MIB_PING_SLOT_WINDOW + */ + uint32_t PingSlotWindow; + /*! + * Default symbol timeout for beacons and ping slot windows + * + * Related MIB type: \ref MIB_BEACON_SYMBOL_TO_DEFAULT + */ + uint32_t BeaconSymbolToDefault; + /*! + * Maximum symbol timeout for beacons + * + * Related MIB type: \ref MIB_BEACON_SYMBOL_TO_EXPANSION_MAX + */ + uint32_t BeaconSymbolToExpansionMax; + /*! + * Maximum symbol timeout for ping slots + * + * Related MIB type: \ref MIB_PING_SLOT_SYMBOL_TO_EXPANSION_MAX + */ + uint32_t PingSlotSymbolToExpansionMax; + /*! + * Symbol expansion value for beacon windows in case of beacon + * loss in symbols + * + * Related MIB type: \ref MIB_BEACON_SYMBOL_TO_EXPANSION_FACTOR + */ + uint32_t BeaconSymbolToExpansionFactor; + /*! + * Symbol expansion value for ping slot windows in case of beacon + * loss in symbols + * + * Related MIB type: \ref MIB_PING_SLOT_SYMBOL_TO_EXPANSION_FACTOR + */ + uint32_t PingSlotSymbolToExpansionFactor; + /*! + * Maximum allowed beacon less time in ms + * + * Related MIB type: \ref MIB_MAX_BEACON_LESS_PERIOD + */ + uint32_t MaxBeaconLessPeriod; + /*! + * Ping slots data rate + * + * Related MIB type: \ref MIB_PING_SLOT_DATARATE + */ + int8_t PingSlotDatarate; + +#ifdef CONFIG_LWAN + uint8_t Rx1DrOffset; + uint32_t LoRaMacState; +#endif + +#ifdef CONFIG_LINKWAN + uint32_t freqband; +#endif +} MibParam_t; + +/*! + * LoRaMAC MIB-RequestConfirm structure + */ +typedef struct eMibRequestConfirm { + /*! + * MIB-Request type + */ + Mib_t Type; + + /*! + * MLME-RequestConfirm parameters + */ + MibParam_t Param; +} MibRequestConfirm_t; + +/*! + * LoRaMAC tx information + */ +typedef struct sLoRaMacTxInfo { + /*! + * Defines the size of the applicative payload which can be processed + */ + uint8_t MaxPossiblePayload; + /*! + * The current payload size, dependent on the current datarate + */ + uint8_t CurrentPayloadSize; +} LoRaMacTxInfo_t; + +/*! + * LoRaMAC Status + */ +typedef enum eLoRaMacStatus { + /*! + * Service started successfully + */ + LORAMAC_STATUS_OK, + /*! + * Service not started - LoRaMAC is busy + */ + LORAMAC_STATUS_BUSY, + /*! + * Service unknown + */ + LORAMAC_STATUS_SERVICE_UNKNOWN, + /*! + * Service not started - invalid parameter + */ + LORAMAC_STATUS_PARAMETER_INVALID, + /*! + * Service not started - invalid frequency + */ + LORAMAC_STATUS_FREQUENCY_INVALID, + /*! + * Service not started - invalid datarate + */ + LORAMAC_STATUS_DATARATE_INVALID, + /*! + * Service not started - invalid frequency and datarate + */ + LORAMAC_STATUS_FREQ_AND_DR_INVALID, + /*! + * Service not started - the device is not in a LoRaWAN + */ + LORAMAC_STATUS_NO_NETWORK_JOINED, + /*! + * Service not started - payload length error + */ + LORAMAC_STATUS_LENGTH_ERROR, + /*! + * Service not started - the device is switched off + */ + LORAMAC_STATUS_DEVICE_OFF, + /*! + * Service not started - the specified region is not supported + * or not activated with preprocessor definitions. + */ + LORAMAC_STATUS_REGION_NOT_SUPPORTED, + /*! + * ToDo + */ + LORAMAC_STATUS_DUTYCYCLE_RESTRICTED, + /*! + * ToDo + */ + LORAMAC_STATUS_NO_CHANNEL_FOUND, + /*! + * ToDo + */ + LORAMAC_STATUS_NO_FREE_CHANNEL_FOUND, + /*! + * ToDo + */ + LORAMAC_STATUS_BUSY_BEACON_RESERVED_TIME, + /*! + * ToDo + */ + LORAMAC_STATUS_BUSY_PING_SLOT_WINDOW_TIME, + /*! + * ToDo + */ + LORAMAC_STATUS_BUSY_UPLINK_COLLISION +} LoRaMacStatus_t; + +/*! + * LoRaMAC region enumeration + */ +typedef enum eLoRaMacRegion_t { + /*! + * AS band on 923MHz + */ + LORAMAC_REGION_AS923, + /*! + * Australian band on 915MHz + */ + LORAMAC_REGION_AU915, + /*! + * Chinese band on 470MHz + */ + LORAMAC_REGION_CN470, + /*! + * Chinese band on 779MHz + */ + LORAMAC_REGION_CN779, + /*! + * European band on 433MHz + */ + LORAMAC_REGION_EU433, + /*! + * European band on 868MHz + */ + LORAMAC_REGION_EU868, + /*! + * South korean band on 920MHz + */ + LORAMAC_REGION_KR920, + /*! + * India band on 865MHz + */ + LORAMAC_REGION_IN865, + /*! + * North american band on 915MHz + */ + LORAMAC_REGION_US915, + /*! + * North american band on 915MHz with a maximum of 16 channels + */ + LORAMAC_REGION_US915_HYBRID, + + /*! + * Chinese band on 470MHz (Alibaba) + * Uplink = Downlink + */ + LORAMAC_REGION_CN470A, +} LoRaMacRegion_t; + +/*! + * LoRaMAC events structure + * Used to notify upper layers of MAC events + */ +typedef struct sLoRaMacPrimitives { + /*! + * \brief MCPS-Confirm primitive + * + * \param [OUT] MCPS-Confirm parameters + */ + void ( *MacMcpsConfirm )( McpsConfirm_t *McpsConfirm ); + /*! + * \brief MCPS-Indication primitive + * + * \param [OUT] MCPS-Indication parameters + */ + void ( *MacMcpsIndication )( McpsIndication_t *McpsIndication ); + /*! + * \brief MLME-Confirm primitive + * + * \param [OUT] MLME-Confirm parameters + */ + void ( *MacMlmeConfirm )( MlmeConfirm_t *MlmeConfirm ); + /*! + * \brief MLME-Indication primitive + * + * \param [OUT] MLME-Indication parameters + */ + void ( *MacMlmeIndication )( MlmeIndication_t *MlmeIndication ); +} LoRaMacPrimitives_t; + +/*! + * LoRaMAC callback structure + */ +typedef struct sLoRaMacCallback { + /*! + * \brief Measures the battery level + * + * \retval Battery level [0: node is connected to an external + * power source, 1..254: battery level, where 1 is the minimum + * and 254 is the maximum value, 255: the node was not able + * to measure the battery level] + */ + uint8_t ( *GetBatteryLevel )( void ); + /*! + * \brief Measures the temperature level + * + * \retval Temperature level + */ + float ( *GetTemperatureLevel )( void ); +} LoRaMacCallback_t; + +/*! + * LoRaMAC Max EIRP (dBm) table + */ +static const uint8_t LoRaMacMaxEirpTable[] = { 8, 10, 12, 13, 14, 16, 18, 20, 21, 24, 26, 27, 29, 30, 33, 36 }; + + + +/*! + * \brief LoRaMAC layer initialization + * + * \details In addition to the initialization of the LoRaMAC layer, this + * function initializes the callback primitives of the MCPS and + * MLME services. Every data field of \ref LoRaMacPrimitives_t must be + * set to a valid callback function. + * + * \param [IN] primitives - Pointer to a structure defining the LoRaMAC + * event functions. Refer to \ref LoRaMacPrimitives_t. + * + * \param [IN] events - Pointer to a structure defining the LoRaMAC + * callback functions. Refer to \ref LoRaMacCallback_t. + * + * \param [IN] region - The region to start. + * + * \retval LoRaMacStatus_t Status of the operation. Possible returns are: + * returns are: + * \ref LORAMAC_STATUS_OK, + * \ref LORAMAC_STATUS_PARAMETER_INVALID, + * \ref LORAMAC_STATUS_REGION_NOT_SUPPORTED. + */ +LoRaMacStatus_t LoRaMacInitialization( LoRaMacPrimitives_t *primitives, LoRaMacCallback_t *callbacks, + LoRaMacRegion_t region ); + +/*! + * \brief Queries the LoRaMAC if it is possible to send the next frame with + * a given payload size. The LoRaMAC takes scheduled MAC commands into + * account and reports, when the frame can be send or not. + * + * \param [IN] size - Size of applicative payload to be send next + * + * \param [OUT] txInfo - The structure \ref LoRaMacTxInfo_t contains + * information about the actual maximum payload possible + * ( according to the configured datarate or the next + * datarate according to ADR ), and the maximum frame + * size, taking the scheduled MAC commands into account. + * + * \retval LoRaMacStatus_t Status of the operation. When the parameters are + * not valid, the function returns \ref LORAMAC_STATUS_PARAMETER_INVALID. + * In case of a length error caused by the applicative payload in combination + * with the MAC commands, the function returns \ref LORAMAC_STATUS_LENGTH_ERROR. + * Please note that if the size of the MAC commands which are in the queue do + * not fit into the payload size on the related datarate, the LoRaMAC will + * omit the MAC commands. + * In case the query is valid, and the LoRaMAC is able to send the frame, + * the function returns \ref LORAMAC_STATUS_OK. + */ +LoRaMacStatus_t LoRaMacQueryTxPossible( uint8_t size, LoRaMacTxInfo_t *txInfo ); + +/*! + * \brief LoRaMAC channel add service + * + * \details Adds a new channel to the channel list and activates the id in + * the channel mask. Please note that this functionality is not available + * on all regions. Information about allowed ranges are available at the LoRaWAN Regional Parameters V1.0.2rB + * + * \param [IN] id - Id of the channel. + * + * \param [IN] params - Channel parameters to set. + * + * \retval LoRaMacStatus_t Status of the operation. Possible returns are: + * \ref LORAMAC_STATUS_OK, + * \ref LORAMAC_STATUS_BUSY, + * \ref LORAMAC_STATUS_PARAMETER_INVALID. + */ +LoRaMacStatus_t LoRaMacChannelAdd( uint8_t id, ChannelParams_t params ); + +/*! + * \brief LoRaMAC channel remove service + * + * \details Deactivates the id in the channel mask. + * + * \param [IN] id - Id of the channel. + * + * \retval LoRaMacStatus_t Status of the operation. Possible returns are: + * \ref LORAMAC_STATUS_OK, + * \ref LORAMAC_STATUS_BUSY, + * \ref LORAMAC_STATUS_PARAMETER_INVALID. + */ +LoRaMacStatus_t LoRaMacChannelRemove( uint8_t id ); + +/*! + * \brief LoRaMAC multicast channel link service + * + * \details Links a multicast channel into the linked list. + * + * \param [IN] channelParam - Multicast channel parameters to link. + * + * \retval LoRaMacStatus_t Status of the operation. Possible returns are: + * \ref LORAMAC_STATUS_OK, + * \ref LORAMAC_STATUS_BUSY, + * \ref LORAMAC_STATUS_PARAMETER_INVALID. + */ +LoRaMacStatus_t LoRaMacMulticastChannelLink( MulticastParams_t *channelParam ); + +/*! + * \brief LoRaMAC multicast channel unlink service + * + * \details Unlinks a multicast channel from the linked list. + * + * \param [IN] channelParam - Multicast channel parameters to unlink. + * + * \retval LoRaMacStatus_t Status of the operation. Possible returns are: + * \ref LORAMAC_STATUS_OK, + * \ref LORAMAC_STATUS_BUSY, + * \ref LORAMAC_STATUS_PARAMETER_INVALID. + */ +LoRaMacStatus_t LoRaMacMulticastChannelUnlink( MulticastParams_t *channelParam ); + +/*! + * \brief LoRaMAC MIB-Get + * + * \details The mac information base service to get attributes of the LoRaMac + * layer. + * + * The following code-snippet shows how to use the API to get the + * parameter AdrEnable, defined by the enumeration type + * \ref MIB_ADR. + * \code + * MibRequestConfirm_t mibReq; + * mibReq.Type = MIB_ADR; + * + * if( LoRaMacMibGetRequestConfirm( &mibReq ) == LORAMAC_STATUS_OK ) + * { + * // LoRaMAC updated the parameter mibParam.AdrEnable + * } + * \endcode + * + * \param [IN] mibRequest - MIB-GET-Request to perform. Refer to \ref MibRequestConfirm_t. + * + * \retval LoRaMacStatus_t Status of the operation. Possible returns are: + * \ref LORAMAC_STATUS_OK, + * \ref LORAMAC_STATUS_SERVICE_UNKNOWN, + * \ref LORAMAC_STATUS_PARAMETER_INVALID. + */ +LoRaMacStatus_t LoRaMacMibGetRequestConfirm( MibRequestConfirm_t *mibGet ); + +/*! + * \brief LoRaMAC MIB-Set + * + * \details The mac information base service to set attributes of the LoRaMac + * layer. + * + * The following code-snippet shows how to use the API to set the + * parameter AdrEnable, defined by the enumeration type + * \ref MIB_ADR. + * + * \code + * MibRequestConfirm_t mibReq; + * mibReq.Type = MIB_ADR; + * mibReq.Param.AdrEnable = true; + * + * if( LoRaMacMibGetRequestConfirm( &mibReq ) == LORAMAC_STATUS_OK ) + * { + * // LoRaMAC updated the parameter + * } + * \endcode + * + * \param [IN] mibRequest - MIB-SET-Request to perform. Refer to \ref MibRequestConfirm_t. + * + * \retval LoRaMacStatus_t Status of the operation. Possible returns are: + * \ref LORAMAC_STATUS_OK, + * \ref LORAMAC_STATUS_BUSY, + * \ref LORAMAC_STATUS_SERVICE_UNKNOWN, + * \ref LORAMAC_STATUS_PARAMETER_INVALID. + */ +LoRaMacStatus_t LoRaMacMibSetRequestConfirm( MibRequestConfirm_t *mibSet ); + +/*! + * \brief LoRaMAC MLME-Request + * + * \details The Mac layer management entity handles management services. The + * following code-snippet shows how to use the API to perform a + * network join request. + * + * \code + * static uint8_t DevEui[] = + * { + * 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + * }; + * static uint8_t AppEui[] = + * { + * 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + * }; + * static uint8_t AppKey[] = + * { + * 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + * 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C + * }; + * + * MlmeReq_t mlmeReq; + * mlmeReq.Type = MLME_JOIN; + * mlmeReq.Req.Join.DevEui = DevEui; + * mlmeReq.Req.Join.AppEui = AppEui; + * mlmeReq.Req.Join.AppKey = AppKey; + * + * if( LoRaMacMlmeRequest( &mlmeReq ) == LORAMAC_STATUS_OK ) + * { + * // Service started successfully. Waiting for the Mlme-Confirm event + * } + * \endcode + * + * \param [IN] mlmeRequest - MLME-Request to perform. Refer to \ref MlmeReq_t. + * + * \retval LoRaMacStatus_t Status of the operation. Possible returns are: + * \ref LORAMAC_STATUS_OK, + * \ref LORAMAC_STATUS_BUSY, + * \ref LORAMAC_STATUS_SERVICE_UNKNOWN, + * \ref LORAMAC_STATUS_PARAMETER_INVALID, + * \ref LORAMAC_STATUS_NO_NETWORK_JOINED, + * \ref LORAMAC_STATUS_LENGTH_ERROR, + * \ref LORAMAC_STATUS_DEVICE_OFF. + */ +LoRaMacStatus_t LoRaMacMlmeRequest( MlmeReq_t *mlmeRequest ); + +/*! + * \brief LoRaMAC MCPS-Request + * + * \details The Mac Common Part Sublayer handles data services. The following + * code-snippet shows how to use the API to send an unconfirmed + * LoRaMAC frame. + * + * \code + * uint8_t myBuffer[] = { 1, 2, 3 }; + * + * McpsReq_t mcpsReq; + * mcpsReq.Type = MCPS_UNCONFIRMED; + * mcpsReq.Req.Unconfirmed.fPort = 1; + * mcpsReq.Req.Unconfirmed.fBuffer = myBuffer; + * mcpsReq.Req.Unconfirmed.fBufferSize = sizeof( myBuffer ); + * + * if( LoRaMacMcpsRequest( &mcpsReq ) == LORAMAC_STATUS_OK ) + * { + * // Service started successfully. Waiting for the MCPS-Confirm event + * } + * \endcode + * + * \param [IN] mcpsRequest - MCPS-Request to perform. Refer to \ref McpsReq_t. + * + * \retval LoRaMacStatus_t Status of the operation. Possible returns are: + * \ref LORAMAC_STATUS_OK, + * \ref LORAMAC_STATUS_BUSY, + * \ref LORAMAC_STATUS_SERVICE_UNKNOWN, + * \ref LORAMAC_STATUS_PARAMETER_INVALID, + * \ref LORAMAC_STATUS_NO_NETWORK_JOINED, + * \ref LORAMAC_STATUS_LENGTH_ERROR, + * \ref LORAMAC_STATUS_DEVICE_OFF. + */ +LoRaMacStatus_t LoRaMacMcpsRequest( McpsReq_t *mcpsRequest ); + +extern void RGB_ON(uint32_t color,uint32_t time); +extern void RGB_OFF(void); + + +#ifdef __cplusplus +} +#endif + +#include "region/Region.h" + +/*! \} defgroup LORAMAC */ + +#endif // __LORAMAC_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacClassB.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacClassB.h new file mode 100644 index 00000000..4b4f02cc --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacClassB.h @@ -0,0 +1,533 @@ +/*! + * \file LoRaMacClassB.h + * + * \brief LoRa MAC Class B layer implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup LORAMACCLASSB LoRa MAC Class B layer implementation + * This module specifies the API implementation of the LoRaMAC Class B layer. + * This is a placeholder for a detailed description of the LoRaMac + * layer and the supported features. + * \{ + */ +#ifndef __LORAMACCLASSB_H__ +#define __LORAMACCLASSB_H__ + +#define LORAMAC_CLASSB_TESTCASE +/*! + * States of the class B beacon acquisition and tracking + */ +typedef enum eBeaconState +{ + /*! + * Initial state to acquire the beacon + */ + BEACON_STATE_ACQUISITION, + /*! + * Beacon acquisition state when a time reference is available + */ + BEACON_STATE_ACQUISITION_BY_TIME, + /*! + * Handles the state when the beacon reception fails + */ + BEACON_STATE_TIMEOUT, + /*! + * Handles the state when the beacon was missed due to an uplink + */ + BEACON_STATE_BEACON_MISSED, + /*! + * Reacquisition state which applies the algorithm to enlarge the reception + * windows + */ + BEACON_STATE_REACQUISITION, + /*! + * The node has locked a beacon successfully + */ + BEACON_STATE_LOCKED, + /*! + * The beacon state machine is stopped due to operations with higher priority + */ + BEACON_STATE_HALT, + /*! + * The node currently operates in the beacon window and is idle. In this + * state, the temperature measurement takes place + */ + BEACON_STATE_IDLE, + /*! + * The node operates in the guard time of class B + */ + BEACON_STATE_GUARD, + /*! + * The node is in receive mode to lock a beacon + */ + BEACON_STATE_RX, + /*! + * The nodes switches the device class + */ + BEACON_STATE_LOST, +}BeaconState_t; + +/*! + * States of the class B ping slot mechanism + */ +typedef enum ePingSlotState +{ + /*! + * Calculation of the ping slot offset + */ + PINGSLOT_STATE_CALC_PING_OFFSET, + /*! + * State to set the timer to open the next ping slot + */ + PINGSLOT_STATE_SET_TIMER, + /*! + * The node is in idle state + */ + PINGSLOT_STATE_IDLE, + /*! + * The node opens up a ping slot window + */ + PINGSLOT_STATE_RX, +}PingSlotState_t; + +/*! + * Class B ping slot context structure + */ +typedef struct sPingSlotContext +{ + struct sPingSlotCtrl + { + /*! + * Set when the server assigned a ping slot to the node + */ + uint8_t Assigned : 1; + /*! + * Set when a custom frequency is used + */ + uint8_t CustomFreq : 1; + }Ctrl; + + /*! + * Ping slot length time in ms + */ + uint32_t PingSlotWindow; + /*! + * Number of ping slots + */ + uint8_t PingNb; + /*! + * Period of the ping slots + */ + uint16_t PingPeriod; + /*! + * Ping offset + */ + uint16_t PingOffset; + /*! + * Reception frequency of the ping slot windows + */ + uint32_t Frequency; + /*! + * Datarate of the ping slot + */ + int8_t Datarate; + /*! + * Current symbol timeout. The node enlarges this variable in case of beacon + * loss. + */ + uint16_t SymbolTimeout; + /*! + * The multicast channel which will be enabled next. + */ + MulticastParams_t *NextMulticastChannel; +}PingSlotContext_t; + + +/*! + * Class B beacon context structure + */ +typedef struct sBeaconContext +{ + struct sBeaconCtrl + { + /*! + * Set if the node receives beacons + */ + uint8_t BeaconMode : 1; + /*! + * Set if the node has acquired the beacon + */ + uint8_t BeaconAcquired : 1; + /*! + * Set if the node has a custom frequency for beaconing and ping slots + */ + uint8_t CustomFreq : 1; + /*! + * Set if a beacon delay was set for the beacon acquisition + */ + uint8_t BeaconDelaySet : 1; + /*! + * Set if a beacon channel was set for the beacon acquisition + */ + uint8_t BeaconChannelSet : 1; + /*! + * Set if beacon acquisition is pending + */ + uint8_t AcquisitionPending : 1; + /*! + * Set if the beacon state machine will be resumed + */ + uint8_t ResumeBeaconing : 1; + }Ctrl; + /*! + * Beacon reception frequency + */ + uint32_t Frequency; + /*! + * Current temperature + */ + float Temperature; + /*! + * Beacon time received with the beacon frame + */ + TimerTime_t BeaconTime; + /*! + * Time when the last beacon was received + */ + TimerTime_t LastBeaconRx; + /*! + * Time when the next beacon will be received + */ + TimerTime_t NextBeaconRx; + /*! + * This is the time where the RX window will be opened. + * Its base is NextBeaconRx with temperature compensations + * and RX window movement. + */ + TimerTime_t NextBeaconRxAdjusted; + /*! + * Current symbol timeout. The node enlarges this variable in case of beacon + * loss. + */ + uint16_t SymbolTimeout; + /*! + * Specifies how much time the beacon window will be moved. + */ + TimerTime_t BeaconWindowMovement; + /*! + * Beacon timing channel for next beacon + */ + uint8_t BeaconTimingChannel; + /*! + * Delay for next beacon in ms + */ + TimerTime_t BeaconTimingDelay; +}BeaconContext_t; + +/*! + * Data structure which contains the callbacks + */ +typedef struct sLoRaMacClassBCallback +{ + /*! + * \brief Measures the temperature level + * + * \retval Temperature level + */ + float ( *GetTemperatureLevel )( void ); +}LoRaMacClassBCallback_t; + +/*! + * Data structure which pointers to the properties LoRaMAC + */ +typedef struct sLoRaMacClassBParams +{ + /*! + * Pointer to the MlmeIndication structure + */ + MlmeIndication_t *MlmeIndication; + /*! + * Pointer to the McpsIndication structure + */ + McpsIndication_t *McpsIndication; + /*! + * Pointer to the MlmeConfirm structure + */ + MlmeConfirm_t *MlmeConfirm; + /*! + * Pointer to the LoRaMacFlags structure + */ + LoRaMacFlags_t *LoRaMacFlags; + /*! + * Pointer to the LoRaMac device address + */ + uint32_t *LoRaMacDevAddr; + /*! + * Pointer to the LoRaMac region definition + */ + LoRaMacRegion_t *LoRaMacRegion; + /*! + * Pointer to the MacStateCheckTimer timer + */ + TimerEvent_t *MacStateCheckTimer; + /*! + * Pointer to the LoRaMacParams structure + */ + LoRaMacParams_t *LoRaMacParams; + /*! + * Pointer to the multicast channel list + */ + MulticastParams_t **MulticastChannels; +}LoRaMacClassBParams_t; + +/*! + * \brief Initialize LoRaWAN Class B + * + * \param [IN] classBParams Information and feedback parameter + * \param [IN] callbacks Contains the callback which the Class B implementation needs + */ +void LoRaMacClassBInit( LoRaMacClassBParams_t *classBParams, LoRaMacClassBCallback_t *callbacks ); + +/*! + * \brief Set the state of the beacon state machine + * + * \param [IN] beaconState Beacon state. + */ +void LoRaMacClassBSetBeaconState( BeaconState_t beaconState ); + +/*! + * \brief Set the state of the ping slot state machine + * + * \param [IN] pingSlotState Ping slot state. + */ +void LoRaMacClassBSetPingSlotState( PingSlotState_t pingSlotState ); + +/*! + * \brief Set the state of the multicast slot state machine + * + * \param [IN] pingSlotState multicast slot state. + */ +void LoRaMacClassBSetMulticastSlotState( PingSlotState_t multicastSlotState ); + +/*! + * \brief Verifies if an acquisition procedure is in progress + * + * \retval [true, if the acquisition is in progress; false, if not] + */ +bool LoRaMacClassBIsAcquisitionInProgress( void ); + +/*! + * \brief State machine of the Class B for beaconing + */ +void LoRaMacClassBBeaconTimerEvent( void ); + +/*! + * \brief State machine of the Class B for ping slots + */ +void LoRaMacClassBPingSlotTimerEvent( void ); + +/*! + * \brief State machine of the Class B for multicast slots + */ +void LoRaMacClassBMulticastSlotTimerEvent( void ); + +/*! + * \brief Receives and decodes the beacon frame + * + * \param [IN] payload Pointer to the payload + * \param [IN] size Size of the payload + * \retval [true, if the node has received a beacon; false, if not] + */ +bool LoRaMacClassBRxBeacon( uint8_t *payload, uint16_t size ); + +/*! + * \brief The function validates, if the node expects a beacon + * at the current time. + * + * \retval [true, if the node expects a beacon; false, if not] + */ +bool LoRaMacClassBIsBeaconExpected( void ); + +/*! + * \brief The function validates, if the node expects a ping slot + * at the current time. + * + * \retval [true, if the node expects a ping slot; false, if not] + */ +bool LoRaMacClassBIsPingExpected( void ); + +/*! + * \brief The function validates, if the node expects a multicast slot + * at the current time. + * + * \retval [true, if the node expects a multicast slot; false, if not] + */ +bool LoRaMacClassBIsMulticastExpected( void ); + +/*! + * \brief Verifies if the acquisition pending bit is set + * + * \retval [true, if the bit is set; false, if not] + */ +bool LoRaMacClassBIsAcquisitionPending( void ); + +/*! + * \brief Verifies if the beacon mode active bit is set + * + * \retval [true, if the bit is set; false, if not] + */ +bool LoRaMacClassBIsBeaconModeActive( void ); + +void LoRaMacClassBStop( void ); +/*! + * \brief Stops the beacon and ping slot operation + */ +void LoRaMacClassBHaltBeaconing( void ); + +/*! + * \brief Resumes the beacon and ping slot operation + */ +void LoRaMacClassBResumeBeaconing( void ); + +/*! + * \brief Sets the periodicity of the ping slots + * + * \param [IN] periodicity Periodicity + */ +void LoRaMacClassBSetPingSlotInfo( uint8_t periodicity ); + +/*! + * \brief Switches the device class + * + * \param [IN] nextClass Device class to switch to + * + * \retval LoRaMacStatus_t Status of the operation. + */ +LoRaMacStatus_t LoRaMacClassBSwitchClass( DeviceClass_t nextClass ); + +/*! + * \brief LoRaMAC ClassB MIB-Get + * + * \details The mac information base service to get attributes of the LoRaMac + * Class B layer. + * + * \param [IN] mibRequest - MIB-GET-Request to perform. Refer to \ref MibRequestConfirm_t. + * + * \retval LoRaMacStatus_t Status of the operation. Possible returns are: + * \ref LORAMAC_STATUS_OK, + * \ref LORAMAC_STATUS_SERVICE_UNKNOWN, + * \ref LORAMAC_STATUS_PARAMETER_INVALID. + */ +LoRaMacStatus_t LoRaMacClassBMibGetRequestConfirm( MibRequestConfirm_t *mibGet ); + +/*! + * \brief LoRaMAC Class B MIB-Set + * + * \details The mac information base service to set attributes of the LoRaMac + * Class B layer. + * + * \param [IN] mibRequest - MIB-SET-Request to perform. Refer to \ref MibRequestConfirm_t. + * + * \retval LoRaMacStatus_t Status of the operation. Possible returns are: + * \ref LORAMAC_STATUS_OK, + * \ref LORAMAC_STATUS_BUSY, + * \ref LORAMAC_STATUS_SERVICE_UNKNOWN, + * \ref LORAMAC_STATUS_PARAMETER_INVALID. + */ +LoRaMacStatus_t LoRaMacMibClassBSetRequestConfirm( MibRequestConfirm_t *mibSet ); + +/*! + * \brief This function handles the PING_SLOT_FREQ_ANS + */ +void LoRaMacClassBPingSlotInfoAns( void ); + +/*! + * \brief This function handles the PING_SLOT_CHANNEL_REQ + * + * \param [IN] datarate Device class to switch to + * \param [IN] frequency Device class to switch to + * + * \retval Status for the MAC answer. + */ +uint8_t LoRaMacClassBPingSlotChannelReq( uint8_t datarate, uint32_t frequency ); + +/*! + * \brief This function handles the BEACON_TIMING_ANS + * + * \param [IN] beaconTimingDelay The beacon timing delay + * \param [IN] beaconTimingChannel The beacon timing channel + */ +void LoRaMacClassBBeaconTimingAns( uint16_t beaconTimingDelay, uint8_t beaconTimingChannel ); + +/*! + * \brief This function handles the ClassB DEVICE_TIME_ANS + * + * \param [IN] currentTime The current time base in ms + */ +void LoRaMacClassBDeviceTimeAns( TimerTime_t currentTime ); + +/*! + * \brief This function handles the BEACON_FREQ_REQ + * + * \param [IN] frequency Frequency to set + * + * \retval [true, if MAC shall send an answer; false, if not] + */ +bool LoRaMacClassBBeaconFreqReq( uint32_t frequency ); + +/*! + * \brief Queries the ping slot window time + * + * \param [IN] txTimeOnAir TX time on air for the next uplink + * + * \retval Returns the time the uplink should be delayed + */ +TimerTime_t LoRaMacClassBIsUplinkCollision( TimerTime_t txTimeOnAir ); + +/*! + * \brief Stops the timers for the RX slots. This includes the + * timers for ping and multicast slots. + */ +void LoRaMacClassBStopRxSlots( void ); + +/*! + * \brief Starts the timers for the RX slots. This includes the + * timers for ping and multicast slots. + */ +void LoRaMacClassBStartRxSlots( void ); + +/*! + * \brief Starts the timers for the RX slots. This includes the + * timers for ping and multicast slots. + * + * \param [IN] periodicity Downlink periodicity + * + * \param [IN] multicastChannel Related multicast channel + */ +void LoRaMacClassBSetMulticastPeriodicity( MulticastParams_t* multicastChannel ); + +#endif // __LORAMACCLASSB_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacClassBConfig.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacClassBConfig.h new file mode 100644 index 00000000..b1b089c6 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacClassBConfig.h @@ -0,0 +1,115 @@ +/*! + * \file LoRaMacClassBConfig.h + * + * \brief LoRa MAC Class B configuration + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup LORAMACCLASSB LoRa MAC Class B configuration + * This header file contains parameters to configure the class b operation. + * By default, all parameters are set according to the specification. + * \{ + */ +#ifndef __LORAMACCLASSBCONFIG_H__ +#define __LORAMACCLASSBCONFIG_H__ + +/*! + * Defines the beacon interval in ms + */ +#define CLASSB_BEACON_INTERVAL 128000 + +/*! + * Beacon reserved time in ms + */ +#define CLASSB_BEACON_RESERVED 2120 + +/*! + * Beacon guard time in ms + */ +#define CLASSB_BEACON_GUARD 3000 + +/*! + * Beacon window time in ms + */ +#define CLASSB_BEACON_WINDOW 122880 + +/*! + * Beacon window time in numer of slots + */ +#define CLASSB_BEACON_WINDOW_SLOTS 4096 + +/*! + * Ping slot length time in ms + */ +#define CLASSB_PING_SLOT_WINDOW 30 + +/*! + * Maximum allowed beacon less time in ms + */ +#define CLASSB_MAX_BEACON_LESS_PERIOD 7200000 + +/*! + * Delay time for the BeaconTimingAns in ms + */ +#define CLASSB_BEACON_DELAY_BEACON_TIMING_ANS 30 + +/*! + * Default symbol timeout for beacons and ping slot windows + */ +#define CLASSB_BEACON_SYMBOL_TO_DEFAULT 8 + +/*! + * Maximum symbol timeout for beacons + */ +#define CLASSB_BEACON_SYMBOL_TO_EXPANSION_MAX 255 + +/*! + * Maximum symbol timeout for ping slots + */ +#define CLASSB_PING_SLOT_SYMBOL_TO_EXPANSION_MAX 30 + +/*! + * Symbol expansion value for beacon windows in case of beacon + * loss in symbols + */ +#define CLASSB_BEACON_SYMBOL_TO_EXPANSION_FACTOR 2 + +/*! + * Defines the default window movement time + */ +#define CLASSB_WINDOW_MOVE_DEFAULT 2 + +/*! + * Defines the maximum time for the beacon movement + */ +#define CLASSB_WINDOW_MOVE_EXPANSION_MAX 256 + +/*! + * Defines the expansion factor for the beacon movement + */ +#define CLASSB_WINDOW_MOVE_EXPANSION_FACTOR 2 + +#endif // __LORAMACCLASSBCONFIG_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacConfirmQueue.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacConfirmQueue.c new file mode 100644 index 00000000..436c01d4 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacConfirmQueue.c @@ -0,0 +1,292 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC confirm queue implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include + +#include "timer.h" +#include "utilities.h" +#include "LoRaMac.h" +#include "LoRaMacConfirmQueue.h" + + +static LoRaMacPrimitives_t* Primitives; + +/*! + * MlmeConfirm queue data structure + */ +static MlmeConfirmQueue_t MlmeConfirmQueue[LORA_MAC_MLME_CONFIRM_QUEUE_LEN]; + +/*! + * Counts the number of MlmeConfirms to process + */ +static uint8_t MlmeConfirmQueueCnt; + +/*! + * Pointer to the first element of the ring buffer + */ +MlmeConfirmQueue_t* BufferStart; + +/*! + * Pointer to the last element of the ring buffer + */ +MlmeConfirmQueue_t* BufferEnd; + +/*! + * Variable which holds a common status + */ +LoRaMacEventInfoStatus_t CommonStatus; + + +static MlmeConfirmQueue_t* IncreaseBufferPointer( MlmeConfirmQueue_t* bufferPointer ) +{ + if( bufferPointer == &MlmeConfirmQueue[LORA_MAC_MLME_CONFIRM_QUEUE_LEN - 1] ) + { + // Reset to the first element + bufferPointer = MlmeConfirmQueue; + } + else + { + // Increase + bufferPointer++; + } + return bufferPointer; +} + +static MlmeConfirmQueue_t* DecreaseBufferPointer( MlmeConfirmQueue_t* bufferPointer ) +{ + if( bufferPointer == MlmeConfirmQueue ) + { + // Reset to the last element + bufferPointer = &MlmeConfirmQueue[LORA_MAC_MLME_CONFIRM_QUEUE_LEN - 1]; + } + else + { + bufferPointer--; + } + return bufferPointer; +} + +static MlmeConfirmQueue_t* GetElement( Mlme_t request, MlmeConfirmQueue_t* bufferStart, MlmeConfirmQueue_t* bufferEnd ) +{ + MlmeConfirmQueue_t* element = bufferStart; + + do + { + if( element->Request == request ) + { + // We have found the element + return element; + } + else + { + element = IncreaseBufferPointer( element ); + } + }while( element != bufferEnd ); + + return NULL; +} + + +void LoRaMacConfirmQueueInit( LoRaMacPrimitives_t* primitives ) +{ + Primitives = primitives; + + // Init counter + MlmeConfirmQueueCnt = 0; + + // Init buffer + BufferStart = MlmeConfirmQueue; + BufferEnd = MlmeConfirmQueue; + + memset1( (uint8_t*) MlmeConfirmQueue, 0xFF, sizeof( MlmeConfirmQueue ) ); + + // Common status + CommonStatus = LORAMAC_EVENT_INFO_STATUS_ERROR; +} + +bool LoRaMacConfirmQueueAdd( MlmeConfirmQueue_t* mlmeConfirm ) +{ + if( MlmeConfirmQueueCnt >= LORA_MAC_MLME_CONFIRM_QUEUE_LEN ) + { + // Protect the buffer against overwrites + return false; + } + + // Add the element to the ring buffer + BufferEnd->Request = mlmeConfirm->Request; + BufferEnd->Status = mlmeConfirm->Status; + BufferEnd->RestrictCommonReadyToHandle = mlmeConfirm->RestrictCommonReadyToHandle; + BufferEnd->ReadyToHandle = false; + // Increase counter + MlmeConfirmQueueCnt++; + // Update end pointer + BufferEnd = IncreaseBufferPointer( BufferEnd ); + + return true; +} + +bool LoRaMacConfirmQueueRemoveLast( void ) +{ + if( MlmeConfirmQueueCnt == 0 ) + { + return false; + } + + // Increase counter + MlmeConfirmQueueCnt--; + // Update start pointer + BufferEnd = DecreaseBufferPointer( BufferEnd ); + + return true; +} + +bool LoRaMacConfirmQueueRemoveFirst( void ) +{ + if( MlmeConfirmQueueCnt == 0 ) + { + return false; + } + + // Increase counter + MlmeConfirmQueueCnt--; + // Update start pointer + BufferStart = IncreaseBufferPointer( BufferStart ); + + return true; +} + +void LoRaMacConfirmQueueSetStatus( LoRaMacEventInfoStatus_t status, Mlme_t request ) +{ + MlmeConfirmQueue_t* element = NULL; + + if( MlmeConfirmQueueCnt > 0 ) + { + element = GetElement( request, BufferStart, BufferEnd ); + if( element != NULL ) + { + element->Status = status; + element->ReadyToHandle = true; + } + } +} + +LoRaMacEventInfoStatus_t LoRaMacConfirmQueueGetStatus( Mlme_t request ) +{ + MlmeConfirmQueue_t* element = NULL; + + if( MlmeConfirmQueueCnt > 0 ) + { + element = GetElement( request, BufferStart, BufferEnd ); + if( element != NULL ) + { + return element->Status; + } + } + return LORAMAC_EVENT_INFO_STATUS_ERROR; +} + +void LoRaMacConfirmQueueSetStatusCmn( LoRaMacEventInfoStatus_t status ) +{ + MlmeConfirmQueue_t* element = BufferStart; + + CommonStatus = status; + + if( MlmeConfirmQueueCnt > 0 ) + { + do + { + element->Status = status; + // Set the status if it is allowed to set it with a call to + // LoRaMacConfirmQueueSetStatusCmn. + if( element->RestrictCommonReadyToHandle == false ) + { + element->ReadyToHandle = true; + } + element = IncreaseBufferPointer( element ); + }while( element != BufferEnd ); + } +} + +LoRaMacEventInfoStatus_t LoRaMacConfirmQueueGetStatusCmn( void ) +{ + return CommonStatus; +} + +bool LoRaMacConfirmQueueIsCmdActive( Mlme_t request ) +{ + if( GetElement( request, BufferStart, BufferEnd ) != NULL ) + { + return true; + } + return false; +} + +void LoRaMacConfirmQueueHandleCb( MlmeConfirm_t* mlmeConfirm ) +{ + uint8_t nbElements = MlmeConfirmQueueCnt; + bool readyToHandle = false; + MlmeConfirmQueue_t mlmeConfirmToStore; + + for( uint8_t i = 0; i < nbElements; i++ ) + { + mlmeConfirm->MlmeRequest = BufferStart->Request; + mlmeConfirm->Status = BufferStart->Status; + readyToHandle = BufferStart->ReadyToHandle; + + if( readyToHandle == true ) + { + Primitives->MacMlmeConfirm( mlmeConfirm ); + } + else + { + // The request is not processed yet. Store the state. + mlmeConfirmToStore.Request = BufferStart->Request; + mlmeConfirmToStore.Status = BufferStart->Status; + mlmeConfirmToStore.RestrictCommonReadyToHandle = BufferStart->RestrictCommonReadyToHandle; + } + + // Increase the pointer afterwards to prevent overwrites + LoRaMacConfirmQueueRemoveFirst( ); + + if( readyToHandle == false ) + { + // Add a request which has not been finished again to the queue + LoRaMacConfirmQueueAdd( &mlmeConfirmToStore ); + } + } +} + +uint8_t LoRaMacConfirmQueueGetCnt( void ) +{ + return MlmeConfirmQueueCnt; +} + +bool LoRaMacConfirmQueueIsFull( void ) +{ + if( MlmeConfirmQueueCnt >= LORA_MAC_MLME_CONFIRM_QUEUE_LEN ) + { + return true; + } + else + { + return false; + } +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacConfirmQueue.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacConfirmQueue.h new file mode 100644 index 00000000..d4fc2cf7 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacConfirmQueue.h @@ -0,0 +1,164 @@ +/*! + * \file LoRaMacConfirmQueue.h + * + * \brief LoRa MAC confirm queue implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup LORAMACCONFIRMQUEUE LoRa MAC confirm queue implementation + * This module specifies the API implementation of the LoRaMAC confirm queue. + * The confirm queue is implemented with as a ring buffer. The number of + * elements can be defined with \ref LORA_MAC_MLME_CONFIRM_QUEUE_LEN. The + * current implementation does not support multiple elements of the same + * Mlme_t type. + * \{ + */ +#ifndef __LORAMAC_CONFIRMQUEUE_H__ +#define __LORAMAC_CONFIRMQUEUE_H__ + + +/*! + * LoRaMac MLME-Confirm queue length + */ +#define LORA_MAC_MLME_CONFIRM_QUEUE_LEN 5 + +/*! + * Structure to hold multiple MLME request confirm data + */ +typedef struct sMlmeConfirmQueue +{ + /*! + * Holds the previously performed MLME-Request + */ + Mlme_t Request; + /*! + * Status of the operation + */ + LoRaMacEventInfoStatus_t Status; + /*! + * Set to true, if the request is ready to be handled + */ + bool ReadyToHandle; + /*! + * Set to true, if it is not permitted to set the ReadyToHandle variable + * with a function call to LoRaMacConfirmQueueSetStatusCmn. + */ + bool RestrictCommonReadyToHandle; +}MlmeConfirmQueue_t; + +/*! + * \brief Initializes the confirm queue + * + * \param [IN] primitives - Pointer to the LoRaMac primitives. + */ +void LoRaMacConfirmQueueInit( LoRaMacPrimitives_t* primitives ); + +/*! + * \brief Adds an element to the confirm queue. + * + * \param [IN] mlmeConfirm - Pointer to the element to add. + * + * \retval [true - operation was successful, false - operation failed] + */ +bool LoRaMacConfirmQueueAdd( MlmeConfirmQueue_t* mlmeConfirm ); + +/*! + * \brief Removes the last element which was added into the queue. + * + * \retval [true - operation was successful, false - operation failed] + */ +bool LoRaMacConfirmQueueRemoveLast( void ); + +/*! + * \brief Removes the first element which was added to the confirm queue. + * + * \retval [true - operation was successful, false - operation failed] + */ +bool LoRaMacConfirmQueueRemoveFirst( void ); + +/*! + * \brief Sets the status of an element. + * + * \param [IN] status - The status to set. + * + * \param [IN] request - The related request to set the status. + */ +void LoRaMacConfirmQueueSetStatus( LoRaMacEventInfoStatus_t status, Mlme_t request ); + +/*! + * \brief Gets the status of an element. + * + * \param [IN] request - The request to query the status. + * + * \retval The status of the related MlmeRequest. + */ +LoRaMacEventInfoStatus_t LoRaMacConfirmQueueGetStatus( Mlme_t request ); + +/*! + * \brief Sets a common status for all elements in the queue. + * + * \param [IN] status - The status to set. + */ +void LoRaMacConfirmQueueSetStatusCmn( LoRaMacEventInfoStatus_t status ); + +/*! + * \brief Gets the common status of all elements. + * + * \retval The common status of all elements. + */ +LoRaMacEventInfoStatus_t LoRaMacConfirmQueueGetStatusCmn( void ); + +/*! + * \brief Verifies if a request is in the queue and active. + * + * \param [IN] request - The request to verify. + * + * \retval [true - element is in the queue, false - element is not in the queue]. + */ +bool LoRaMacConfirmQueueIsCmdActive( Mlme_t request ); + +/*! + * \brief Handles all callbacks of active requests + * + * \param [IN] mlmeConfirm - Pointer to the generic mlmeConfirm structure. + */ +void LoRaMacConfirmQueueHandleCb( MlmeConfirm_t* mlmeConfirm ); + +/*! + * \brief Query number of elements in the queue. + * + * \retval Number of elements. + */ +uint8_t LoRaMacConfirmQueueGetCnt( void ); + +/*! + * \brief Verify if the confirm queue is full. + * + * \retval [true - queue is full, false - queue is not full]. + */ +bool LoRaMacConfirmQueueIsFull( void ); + +#endif // __LORAMAC_CONFIRMQUEUE_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacCrypto.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacCrypto.c new file mode 100644 index 00000000..c197dfca --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacCrypto.c @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC layer implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include "utilities.h" + +#include "aes.h" +#include "cmac.h" + +#include "LoRaMacCrypto.h" + +/*! + * CMAC/AES Message Integrity Code (MIC) Block B0 size + */ +#define LORAMAC_MIC_BLOCK_B0_SIZE 16 + +/*! + * MIC field computation initial data + */ +static uint8_t MicBlockB0[] = { 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + +/*! + * Contains the computed MIC field. + * + * \remark Only the 4 first bytes are used + */ +static uint8_t Mic[16]; + +/*! + * Encryption aBlock and sBlock + */ +static uint8_t aBlock[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; +static uint8_t sBlock[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + +/*! + * AES computation context variable + */ +static aes_context AesContext; + +/*! + * CMAC computation context variable + */ +static AES_CMAC_CTX AesCmacCtx[1]; + +/*! + * \brief Computes the LoRaMAC frame MIC field + * + * \param [IN] buffer Data buffer + * \param [IN] size Data buffer size + * \param [IN] key AES key to be used + * \param [IN] address Frame address + * \param [IN] dir Frame direction [0: uplink, 1: downlink] + * \param [IN] sequenceCounter Frame sequence counter + * \param [OUT] mic Computed MIC field + */ +void LoRaMacComputeMic( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t address, uint8_t dir, uint32_t sequenceCounter, uint32_t *mic ) +{ + MicBlockB0[5] = dir; + + MicBlockB0[6] = ( address ) & 0xFF; + MicBlockB0[7] = ( address >> 8 ) & 0xFF; + MicBlockB0[8] = ( address >> 16 ) & 0xFF; + MicBlockB0[9] = ( address >> 24 ) & 0xFF; + + MicBlockB0[10] = ( sequenceCounter ) & 0xFF; + MicBlockB0[11] = ( sequenceCounter >> 8 ) & 0xFF; + MicBlockB0[12] = ( sequenceCounter >> 16 ) & 0xFF; + MicBlockB0[13] = ( sequenceCounter >> 24 ) & 0xFF; + + MicBlockB0[15] = size & 0xFF; + + AES_CMAC_Init( AesCmacCtx ); + + AES_CMAC_SetKey( AesCmacCtx, key ); + + AES_CMAC_Update( AesCmacCtx, MicBlockB0, LORAMAC_MIC_BLOCK_B0_SIZE ); + + AES_CMAC_Update( AesCmacCtx, buffer, size & 0xFF ); + + AES_CMAC_Final( Mic, AesCmacCtx ); + + *mic = ( uint32_t )( ( uint32_t )Mic[3] << 24 | ( uint32_t )Mic[2] << 16 | ( uint32_t )Mic[1] << 8 | ( uint32_t )Mic[0] ); +} + +void LoRaMacPayloadEncrypt( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t address, uint8_t dir, uint32_t sequenceCounter, uint8_t *encBuffer ) +{ + uint16_t i; + uint8_t bufferIndex = 0; + uint16_t ctr = 1; + + memset1( AesContext.ksch, '\0', 240 ); + aes_set_key( key, 16, &AesContext ); + + aBlock[5] = dir; + + aBlock[6] = ( address ) & 0xFF; + aBlock[7] = ( address >> 8 ) & 0xFF; + aBlock[8] = ( address >> 16 ) & 0xFF; + aBlock[9] = ( address >> 24 ) & 0xFF; + + aBlock[10] = ( sequenceCounter ) & 0xFF; + aBlock[11] = ( sequenceCounter >> 8 ) & 0xFF; + aBlock[12] = ( sequenceCounter >> 16 ) & 0xFF; + aBlock[13] = ( sequenceCounter >> 24 ) & 0xFF; + + while( size >= 16 ) + { + aBlock[15] = ( ( ctr ) & 0xFF ); + ctr++; + aes_encrypt( aBlock, sBlock, &AesContext ); + for( i = 0; i < 16; i++ ) + { + encBuffer[bufferIndex + i] = buffer[bufferIndex + i] ^ sBlock[i]; + } + size -= 16; + bufferIndex += 16; + } + + if( size > 0 ) + { + aBlock[15] = ( ( ctr ) & 0xFF ); + aes_encrypt( aBlock, sBlock, &AesContext ); + for( i = 0; i < size; i++ ) + { + encBuffer[bufferIndex + i] = buffer[bufferIndex + i] ^ sBlock[i]; + } + } +} + +void LoRaMacPayloadDecrypt( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t address, uint8_t dir, uint32_t sequenceCounter, uint8_t *decBuffer ) +{ + LoRaMacPayloadEncrypt( buffer, size, key, address, dir, sequenceCounter, decBuffer ); +} + +void LoRaMacJoinComputeMic( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t *mic ) +{ + AES_CMAC_Init( AesCmacCtx ); + + AES_CMAC_SetKey( AesCmacCtx, key ); + + AES_CMAC_Update( AesCmacCtx, buffer, size & 0xFF ); + + AES_CMAC_Final( Mic, AesCmacCtx ); + + *mic = ( uint32_t )( ( uint32_t )Mic[3] << 24 | ( uint32_t )Mic[2] << 16 | ( uint32_t )Mic[1] << 8 | ( uint32_t )Mic[0] ); +} + +void LoRaMacJoinDecrypt( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint8_t *decBuffer ) +{ + memset1( AesContext.ksch, '\0', 240 ); + aes_set_key( key, 16, &AesContext ); + aes_encrypt( buffer, decBuffer, &AesContext ); + // Check if optional CFList is included + if( size >= 16 ) + { + aes_encrypt( buffer + 16, decBuffer + 16, &AesContext ); + } +} + +void LoRaMacJoinComputeSKeys( const uint8_t *key, const uint8_t *appNonce, uint16_t devNonce, uint8_t *nwkSKey, uint8_t *appSKey ) +{ + uint8_t nonce[16]; + uint8_t *pDevNonce = ( uint8_t * )&devNonce; + + memset1( AesContext.ksch, '\0', 240 ); + aes_set_key( key, 16, &AesContext ); + + memset1( nonce, 0, sizeof( nonce ) ); + nonce[0] = 0x01; + memcpy1( nonce + 1, appNonce, 6 ); + memcpy1( nonce + 7, pDevNonce, 2 ); + aes_encrypt( nonce, nwkSKey, &AesContext ); + + memset1( nonce, 0, sizeof( nonce ) ); + nonce[0] = 0x02; + memcpy1( nonce + 1, appNonce, 6 ); + memcpy1( nonce + 7, pDevNonce, 2 ); + aes_encrypt( nonce, appSKey, &AesContext ); +} + +void LoRaMacBeaconComputePingOffset( uint64_t beaconTime, uint32_t address, uint16_t pingPeriod, uint16_t *pingOffset ) +{ + uint8_t zeroKey[16]; + uint8_t buffer[16]; + uint8_t cipher[16]; + uint32_t result = 0; + /* Refer to chapter 15.2 of the LoRaWAN specification v1.1. The beacon time + * GPS time in seconds modulo 2^32 + */ + uint32_t time = ( beaconTime % ( ( ( uint64_t ) 1 ) << 32 ) ); + + memset1( zeroKey, 0, 16 ); + memset1( buffer, 0, 16 ); + memset1( cipher, 0, 16 ); + memset1( AesContext.ksch, '\0', 240 ); + + buffer[0] = ( time ) & 0xFF; + buffer[1] = ( time >> 8 ) & 0xFF; + buffer[2] = ( time >> 16 ) & 0xFF; + buffer[3] = ( time >> 24 ) & 0xFF; + + buffer[4] = ( address ) & 0xFF; + buffer[5] = ( address >> 8 ) & 0xFF; + buffer[6] = ( address >> 16 ) & 0xFF; + buffer[7] = ( address >> 24 ) & 0xFF; + + aes_set_key( zeroKey, 16, &AesContext ); + aes_encrypt( buffer, cipher, &AesContext ); + + result = ( ( ( uint32_t ) cipher[0] ) + ( ( ( uint32_t ) cipher[1] ) * 256 ) ); + + *pingOffset = ( uint16_t )( result % pingPeriod ); +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacCrypto.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacCrypto.h new file mode 100644 index 00000000..f4316e62 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacCrypto.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file LoRaMacCrypto.h + * + * \brief LoRa MAC layer cryptography implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup LORAMAC_CRYPTO LoRa MAC layer cryptography implementation + * This module covers the implementation of cryptographic functions + * of the LoRaMAC layer. + * \{ + */ +#ifndef __LORAMAC_CRYPTO_H__ +#define __LORAMAC_CRYPTO_H__ + +/*! + * Computes the LoRaMAC frame MIC field + * + * \param [IN] buffer - Data buffer + * \param [IN] size - Data buffer size + * \param [IN] key - AES key to be used + * \param [IN] address - Frame address + * \param [IN] dir - Frame direction [0: uplink, 1: downlink] + * \param [IN] sequenceCounter - Frame sequence counter + * \param [OUT] mic - Computed MIC field + */ +void LoRaMacComputeMic( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t address, uint8_t dir, uint32_t sequenceCounter, uint32_t *mic ); + +/*! + * Computes the LoRaMAC payload encryption + * + * \param [IN] buffer - Data buffer + * \param [IN] size - Data buffer size + * \param [IN] key - AES key to be used + * \param [IN] address - Frame address + * \param [IN] dir - Frame direction [0: uplink, 1: downlink] + * \param [IN] sequenceCounter - Frame sequence counter + * \param [OUT] encBuffer - Encrypted buffer + */ +void LoRaMacPayloadEncrypt( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t address, uint8_t dir, uint32_t sequenceCounter, uint8_t *encBuffer ); + +/*! + * Computes the LoRaMAC payload decryption + * + * \param [IN] buffer - Data buffer + * \param [IN] size - Data buffer size + * \param [IN] key - AES key to be used + * \param [IN] address - Frame address + * \param [IN] dir - Frame direction [0: uplink, 1: downlink] + * \param [IN] sequenceCounter - Frame sequence counter + * \param [OUT] decBuffer - Decrypted buffer + */ +void LoRaMacPayloadDecrypt( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t address, uint8_t dir, uint32_t sequenceCounter, uint8_t *decBuffer ); + +/*! + * Computes the LoRaMAC Join Request frame MIC field + * + * \param [IN] buffer - Data buffer + * \param [IN] size - Data buffer size + * \param [IN] key - AES key to be used + * \param [OUT] mic - Computed MIC field + */ +void LoRaMacJoinComputeMic( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint32_t *mic ); + +/*! + * Computes the LoRaMAC join frame decryption + * + * \param [IN] buffer - Data buffer + * \param [IN] size - Data buffer size + * \param [IN] key - AES key to be used + * \param [OUT] decBuffer - Decrypted buffer + */ +void LoRaMacJoinDecrypt( const uint8_t *buffer, uint16_t size, const uint8_t *key, uint8_t *decBuffer ); + +/*! + * Computes the LoRaMAC join frame decryption + * + * \param [IN] key - AES key to be used + * \param [IN] appNonce - Application nonce + * \param [IN] devNonce - Device nonce + * \param [OUT] nwkSKey - Network session key + * \param [OUT] appSKey - Application session key + */ +void LoRaMacJoinComputeSKeys( const uint8_t *key, const uint8_t *appNonce, uint16_t devNonce, uint8_t *nwkSKey, uint8_t *appSKey ); + +/*! + * Computes the LoRaMAC join frame decryption + * + * \param [IN] beaconTime - Time of the recent received beacon + * \param [IN] address - Frame address + * \param [IN] pingPeriod - Ping period of the node + * \param [OUT] pingOffset - Pseudo random ping offset + */ +void LoRaMacBeaconComputePingOffset( uint64_t beaconTime, uint32_t address, uint16_t pingPeriod, uint16_t *pingOffset ); + +/*! \} defgroup LORAMAC */ + +#endif // __LORAMAC_CRYPTO_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacTest.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacTest.h new file mode 100644 index 00000000..cdeb2a86 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/LoRaMacTest.h @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file LoRaMacTest.h + * + * \brief LoRa MAC layer test function implementation + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup LORAMACTEST LoRa MAC layer test function implementation + * This module specifies the API implementation of test function of the LoRaMAC layer. + * The functions in this file are only for testing purposes only. + * \{ + */ +#ifndef __LORAMACTEST_H__ +#define __LORAMACTEST_H__ + +/*! + * \brief Enabled or disables the reception windows + * + * \details This is a test function. It shall be used for testing purposes only. + * Changing this attribute may lead to a non-conformance LoRaMac operation. + * + * \param [IN] enable - Enabled or disables the reception windows + */ +void LoRaMacTestRxWindowsOn( bool enable ); + +/*! + * \brief Enables the MIC field test + * + * \details This is a test function. It shall be used for testing purposes only. + * Changing this attribute may lead to a non-conformance LoRaMac operation. + * + * \param [IN] txPacketCounter - Fixed Tx packet counter value + */ +void LoRaMacTestSetMic( uint16_t txPacketCounter ); + +/*! + * \brief Enabled or disables the duty cycle + * + * \details This is a test function. It shall be used for testing purposes only. + * Changing this attribute may lead to a non-conformance LoRaMac operation. + * + * \param [IN] enable - Enabled or disables the duty cycle + */ +void LoRaMacTestSetDutyCycleOn( bool enable ); + +/*! + * \brief Sets the channel index + * + * \details This is a test function. It shall be used for testing purposes only. + * Changing this attribute may lead to a non-conformance LoRaMac operation. + * + * \param [IN] channel - Channel index + */ +void LoRaMacTestSetChannel( uint8_t channel ); + +/*! \} defgroup LORAMACTEST */ + +#endif // __LORAMACTEST_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/Region.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/Region.c new file mode 100644 index 00000000..79b24b3d --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/Region.c @@ -0,0 +1,1161 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC region implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include + +//#include "timer.h" +#include "timeServer.h" +#include "LoRaMac.h" + + + +// Regional includes +#include "Region.h" + + + +// Setup regions +#ifdef REGION_AS923 +#include "RegionAS923.h" +#define AS923_CASE case LORAMAC_REGION_AS923: +#define AS923_IS_ACTIVE( ) AS923_CASE { return true; } +#define AS923_GET_PHY_PARAM( ) AS923_CASE { return RegionAS923GetPhyParam( getPhy ); } +#define AS923_SET_BAND_TX_DONE( ) AS923_CASE { RegionAS923SetBandTxDone( txDone ); break; } +#define AS923_INIT_DEFAULTS( ) AS923_CASE { RegionAS923InitDefaults( type ); break; } +#define AS923_VERIFY( ) AS923_CASE { return RegionAS923Verify( verify, phyAttribute ); } +#define AS923_APPLY_CF_LIST( ) AS923_CASE { RegionAS923ApplyCFList( applyCFList ); break; } +#define AS923_CHAN_MASK_SET( ) AS923_CASE { return RegionAS923ChanMaskSet( chanMaskSet ); } +#define AS923_ADR_NEXT( ) AS923_CASE { return RegionAS923AdrNext( adrNext, drOut, txPowOut, adrAckCounter ); } +#define AS923_COMPUTE_RX_WINDOW_PARAMETERS( ) AS923_CASE { RegionAS923ComputeRxWindowParameters( datarate, minRxSymbols, rxError, rxConfigParams ); break; } +#define AS923_RX_CONFIG( ) AS923_CASE { return RegionAS923RxConfig( rxConfig, datarate ); } +#define AS923_TX_CONFIG( ) AS923_CASE { return RegionAS923TxConfig( txConfig, txPower, txTimeOnAir ); } +#define AS923_LINK_ADR_REQ( ) AS923_CASE { return RegionAS923LinkAdrReq( linkAdrReq, drOut, txPowOut, nbRepOut, nbBytesParsed ); } +#define AS923_RX_PARAM_SETUP_REQ( ) AS923_CASE { return RegionAS923RxParamSetupReq( rxParamSetupReq ); } +#define AS923_NEW_CHANNEL_REQ( ) AS923_CASE { return RegionAS923NewChannelReq( newChannelReq ); } +#define AS923_TX_PARAM_SETUP_REQ( ) AS923_CASE { return RegionAS923TxParamSetupReq( txParamSetupReq ); } +#define AS923_DL_CHANNEL_REQ( ) AS923_CASE { return RegionAS923DlChannelReq( dlChannelReq ); } +#define AS923_ALTERNATE_DR( ) AS923_CASE { return RegionAS923AlternateDr( alternateDr ); } +#define AS923_CALC_BACKOFF( ) AS923_CASE { RegionAS923CalcBackOff( calcBackOff ); break; } +#define AS923_NEXT_CHANNEL( ) AS923_CASE { return RegionAS923NextChannel( nextChanParams, channel, time, aggregatedTimeOff ); } +#define AS923_CHANNEL_ADD( ) AS923_CASE { return RegionAS923ChannelAdd( channelAdd ); } +#define AS923_CHANNEL_REMOVE( ) AS923_CASE { return RegionAS923ChannelsRemove( channelRemove ); } +#define AS923_SET_CONTINUOUS_WAVE( ) AS923_CASE { RegionAS923SetContinuousWave( continuousWave ); break; } +#define AS923_APPLY_DR_OFFSET( ) AS923_CASE { return RegionAS923ApplyDrOffset( downlinkDwellTime, dr, drOffset ); } +#define AS923_RX_BEACON_SETUP( ) AS923_CASE { RegionAS923RxBeaconSetup( rxBeaconSetup, outDr ); } +#else +#define AS923_IS_ACTIVE( ) +#define AS923_GET_PHY_PARAM( ) +#define AS923_SET_BAND_TX_DONE( ) +#define AS923_INIT_DEFAULTS( ) +#define AS923_VERIFY( ) +#define AS923_APPLY_CF_LIST( ) +#define AS923_CHAN_MASK_SET( ) +#define AS923_ADR_NEXT( ) +#define AS923_COMPUTE_RX_WINDOW_PARAMETERS( ) +#define AS923_RX_CONFIG( ) +#define AS923_TX_CONFIG( ) +#define AS923_LINK_ADR_REQ( ) +#define AS923_RX_PARAM_SETUP_REQ( ) +#define AS923_NEW_CHANNEL_REQ( ) +#define AS923_TX_PARAM_SETUP_REQ( ) +#define AS923_DL_CHANNEL_REQ( ) +#define AS923_ALTERNATE_DR( ) +#define AS923_CALC_BACKOFF( ) +#define AS923_NEXT_CHANNEL( ) +#define AS923_CHANNEL_ADD( ) +#define AS923_CHANNEL_REMOVE( ) +#define AS923_SET_CONTINUOUS_WAVE( ) +#define AS923_APPLY_DR_OFFSET( ) +#define AS923_RX_BEACON_SETUP( ) +#endif + +#ifdef REGION_AU915 +#include "RegionAU915.h" +#define AU915_CASE case LORAMAC_REGION_AU915: +#define AU915_IS_ACTIVE( ) AU915_CASE { return true; } +#define AU915_GET_PHY_PARAM( ) AU915_CASE { return RegionAU915GetPhyParam( getPhy ); } +#define AU915_SET_BAND_TX_DONE( ) AU915_CASE { RegionAU915SetBandTxDone( txDone ); break; } +#define AU915_INIT_DEFAULTS( ) AU915_CASE { RegionAU915InitDefaults( type ); break; } +#define AU915_VERIFY( ) AU915_CASE { return RegionAU915Verify( verify, phyAttribute ); } +#define AU915_APPLY_CF_LIST( ) AU915_CASE { RegionAU915ApplyCFList( applyCFList ); break; } +#define AU915_CHAN_MASK_SET( ) AU915_CASE { return RegionAU915ChanMaskSet( chanMaskSet ); } +#define AU915_ADR_NEXT( ) AU915_CASE { return RegionAU915AdrNext( adrNext, drOut, txPowOut, adrAckCounter ); } +#define AU915_COMPUTE_RX_WINDOW_PARAMETERS( ) AU915_CASE { RegionAU915ComputeRxWindowParameters( datarate, minRxSymbols, rxError, rxConfigParams ); break; } +#define AU915_RX_CONFIG( ) AU915_CASE { return RegionAU915RxConfig( rxConfig, datarate ); } +#define AU915_TX_CONFIG( ) AU915_CASE { return RegionAU915TxConfig( txConfig, txPower, txTimeOnAir ); } +#define AU915_LINK_ADR_REQ( ) AU915_CASE { return RegionAU915LinkAdrReq( linkAdrReq, drOut, txPowOut, nbRepOut, nbBytesParsed ); } +#define AU915_RX_PARAM_SETUP_REQ( ) AU915_CASE { return RegionAU915RxParamSetupReq( rxParamSetupReq ); } +#define AU915_NEW_CHANNEL_REQ( ) AU915_CASE { return RegionAU915NewChannelReq( newChannelReq ); } +#define AU915_TX_PARAM_SETUP_REQ( ) AU915_CASE { return RegionAU915TxParamSetupReq( txParamSetupReq ); } +#define AU915_DL_CHANNEL_REQ( ) AU915_CASE { return RegionAU915DlChannelReq( dlChannelReq ); } +#define AU915_ALTERNATE_DR( ) AU915_CASE { return RegionAU915AlternateDr( alternateDr ); } +#define AU915_CALC_BACKOFF( ) AU915_CASE { RegionAU915CalcBackOff( calcBackOff ); break; } +#define AU915_NEXT_CHANNEL( ) AU915_CASE { return RegionAU915NextChannel( nextChanParams, channel, time, aggregatedTimeOff ); } +#define AU915_CHANNEL_ADD( ) AU915_CASE { return RegionAU915ChannelAdd( channelAdd ); } +#define AU915_CHANNEL_REMOVE( ) AU915_CASE { return RegionAU915ChannelsRemove( channelRemove ); } +#define AU915_SET_CONTINUOUS_WAVE( ) AU915_CASE { RegionAU915SetContinuousWave( continuousWave ); break; } +#define AU915_APPLY_DR_OFFSET( ) AU915_CASE { return RegionAU915ApplyDrOffset( downlinkDwellTime, dr, drOffset ); } +#define AU915_RX_BEACON_SETUP( ) AU915_CASE { RegionAU915RxBeaconSetup( rxBeaconSetup, outDr ); } +#else +#define AU915_IS_ACTIVE( ) +#define AU915_GET_PHY_PARAM( ) +#define AU915_SET_BAND_TX_DONE( ) +#define AU915_INIT_DEFAULTS( ) +#define AU915_VERIFY( ) +#define AU915_APPLY_CF_LIST( ) +#define AU915_CHAN_MASK_SET( ) +#define AU915_ADR_NEXT( ) +#define AU915_COMPUTE_RX_WINDOW_PARAMETERS( ) +#define AU915_RX_CONFIG( ) +#define AU915_TX_CONFIG( ) +#define AU915_LINK_ADR_REQ( ) +#define AU915_RX_PARAM_SETUP_REQ( ) +#define AU915_NEW_CHANNEL_REQ( ) +#define AU915_TX_PARAM_SETUP_REQ( ) +#define AU915_DL_CHANNEL_REQ( ) +#define AU915_ALTERNATE_DR( ) +#define AU915_CALC_BACKOFF( ) +#define AU915_NEXT_CHANNEL( ) +#define AU915_CHANNEL_ADD( ) +#define AU915_CHANNEL_REMOVE( ) +#define AU915_SET_CONTINUOUS_WAVE( ) +#define AU915_APPLY_DR_OFFSET( ) +#define AU915_RX_BEACON_SETUP( ) +#endif + +#ifdef REGION_CN470 +#include "RegionCN470.h" +#define CN470_CASE case LORAMAC_REGION_CN470: +#define CN470_IS_ACTIVE( ) CN470_CASE { return true; } +#define CN470_GET_PHY_PARAM( ) CN470_CASE { return RegionCN470GetPhyParam( getPhy ); } +#define CN470_SET_BAND_TX_DONE( ) CN470_CASE { RegionCN470SetBandTxDone( txDone ); break; } +#define CN470_INIT_DEFAULTS( ) CN470_CASE { RegionCN470InitDefaults( type ); break; } +#define CN470_VERIFY( ) CN470_CASE { return RegionCN470Verify( verify, phyAttribute ); } +#define CN470_APPLY_CF_LIST( ) CN470_CASE { RegionCN470ApplyCFList( applyCFList ); break; } +#define CN470_CHAN_MASK_SET( ) CN470_CASE { return RegionCN470ChanMaskSet( chanMaskSet ); } +#define CN470_ADR_NEXT( ) CN470_CASE { return RegionCN470AdrNext( adrNext, drOut, txPowOut, adrAckCounter ); } +#define CN470_COMPUTE_RX_WINDOW_PARAMETERS( ) CN470_CASE { RegionCN470ComputeRxWindowParameters( datarate, minRxSymbols, rxError, rxConfigParams ); break; } +#define CN470_RX_CONFIG( ) CN470_CASE { return RegionCN470RxConfig( rxConfig, datarate ); } +#define CN470_TX_CONFIG( ) CN470_CASE { return RegionCN470TxConfig( txConfig, txPower, txTimeOnAir ); } +#define CN470_LINK_ADR_REQ( ) CN470_CASE { return RegionCN470LinkAdrReq( linkAdrReq, drOut, txPowOut, nbRepOut, nbBytesParsed ); } +#define CN470_RX_PARAM_SETUP_REQ( ) CN470_CASE { return RegionCN470RxParamSetupReq( rxParamSetupReq ); } +#define CN470_NEW_CHANNEL_REQ( ) CN470_CASE { return RegionCN470NewChannelReq( newChannelReq ); } +#define CN470_TX_PARAM_SETUP_REQ( ) CN470_CASE { return RegionCN470TxParamSetupReq( txParamSetupReq ); } +#define CN470_DL_CHANNEL_REQ( ) CN470_CASE { return RegionCN470DlChannelReq( dlChannelReq ); } +#define CN470_ALTERNATE_DR( ) CN470_CASE { return RegionCN470AlternateDr( alternateDr ); } +#define CN470_CALC_BACKOFF( ) CN470_CASE { RegionCN470CalcBackOff( calcBackOff ); break; } +#define CN470_NEXT_CHANNEL( ) CN470_CASE { return RegionCN470NextChannel( nextChanParams, channel, time, aggregatedTimeOff ); } +#define CN470_CHANNEL_ADD( ) CN470_CASE { return RegionCN470ChannelAdd( channelAdd ); } +#define CN470_CHANNEL_REMOVE( ) CN470_CASE { return RegionCN470ChannelsRemove( channelRemove ); } +#define CN470_SET_CONTINUOUS_WAVE( ) CN470_CASE { RegionCN470SetContinuousWave( continuousWave ); break; } +#define CN470_APPLY_DR_OFFSET( ) CN470_CASE { return RegionCN470ApplyDrOffset( downlinkDwellTime, dr, drOffset ); } +#define CN470_RX_BEACON_SETUP( ) CN470_CASE { RegionCN470RxBeaconSetup( rxBeaconSetup, outDr ); } +#else +#define CN470_IS_ACTIVE( ) +#define CN470_GET_PHY_PARAM( ) +#define CN470_SET_BAND_TX_DONE( ) +#define CN470_INIT_DEFAULTS( ) +#define CN470_VERIFY( ) +#define CN470_APPLY_CF_LIST( ) +#define CN470_CHAN_MASK_SET( ) +#define CN470_ADR_NEXT( ) +#define CN470_COMPUTE_RX_WINDOW_PARAMETERS( ) +#define CN470_RX_CONFIG( ) +#define CN470_TX_CONFIG( ) +#define CN470_LINK_ADR_REQ( ) +#define CN470_RX_PARAM_SETUP_REQ( ) +#define CN470_NEW_CHANNEL_REQ( ) +#define CN470_TX_PARAM_SETUP_REQ( ) +#define CN470_DL_CHANNEL_REQ( ) +#define CN470_ALTERNATE_DR( ) +#define CN470_CALC_BACKOFF( ) +#define CN470_NEXT_CHANNEL( ) +#define CN470_CHANNEL_ADD( ) +#define CN470_CHANNEL_REMOVE( ) +#define CN470_SET_CONTINUOUS_WAVE( ) +#define CN470_APPLY_DR_OFFSET( ) +#define CN470_RX_BEACON_SETUP( ) +#endif + +#ifdef REGION_CN470A +#include "RegionCN470A.h" +#define CN470A_CASE case LORAMAC_REGION_CN470A: +#define CN470A_IS_ACTIVE( ) CN470A_CASE { return true; } +#define CN470A_GET_PHY_PARAM( ) CN470A_CASE { return RegionCN470AGetPhyParam( getPhy ); } +#define CN470A_SET_BAND_TX_DONE( ) CN470A_CASE { RegionCN470ASetBandTxDone( txDone ); break; } +#define CN470A_INIT_DEFAULTS( ) CN470A_CASE { RegionCN470AInitDefaults( type ); break; } +#define CN470A_VERIFY( ) CN470A_CASE { return RegionCN470AVerify( verify, phyAttribute ); } +#define CN470A_APPLY_CF_LIST( ) CN470A_CASE { RegionCN470AApplyCFList( applyCFList ); break; } +#define CN470A_CHAN_MASK_SET( ) CN470A_CASE { return RegionCN470AChanMaskSet( chanMaskSet ); } +#define CN470A_ADR_NEXT( ) CN470A_CASE { return RegionCN470AAdrNext( adrNext, drOut, txPowOut, adrAckCounter ); } +#define CN470A_COMPUTE_RX_WINDOW_PARAMETERS( ) CN470A_CASE { RegionCN470AComputeRxWindowParameters( datarate, minRxSymbols, rxError, rxConfigParams ); break; } +#define CN470A_RX_CONFIG( ) CN470A_CASE { return RegionCN470ARxConfig( rxConfig, datarate ); } +#define CN470A_TX_CONFIG( ) CN470A_CASE { return RegionCN470ATxConfig( txConfig, txPower, txTimeOnAir ); } +#define CN470A_LINK_ADR_REQ( ) CN470A_CASE { return RegionCN470ALinkAdrReq( linkAdrReq, drOut, txPowOut, nbRepOut, nbBytesParsed ); } +#define CN470A_RX_PARAM_SETUP_REQ( ) CN470A_CASE { return RegionCN470ARxParamSetupReq( rxParamSetupReq ); } +#define CN470A_NEW_CHANNEL_REQ( ) CN470A_CASE { return RegionCN470ANewChannelReq( newChannelReq ); } +#define CN470A_TX_PARAM_SETUP_REQ( ) CN470A_CASE { return RegionCN470ATxParamSetupReq( txParamSetupReq ); } +#define CN470A_DL_CHANNEL_REQ( ) CN470A_CASE { return RegionCN470ADlChannelReq( dlChannelReq ); } +#define CN470A_ALTERNATE_DR( ) CN470A_CASE { return RegionCN470AAlternateDr( alternateDr ); } +#define CN470A_CALC_BACKOFF( ) CN470A_CASE { RegionCN470ACalcBackOff( calcBackOff ); break; } +#define CN470A_NEXT_CHANNEL( ) CN470A_CASE { return RegionCN470ANextChannel( nextChanParams, channel, time, aggregatedTimeOff ); } +#define CN470A_CHANNEL_ADD( ) CN470A_CASE { return RegionCN470AChannelAdd( channelAdd ); } +#define CN470A_CHANNEL_REMOVE( ) CN470A_CASE { return RegionCN470AChannelsRemove( channelRemove ); } +#define CN470A_SET_CONTINUOUS_WAVE( ) CN470A_CASE { RegionCN470ASetContinuousWave( continuousWave ); break; } +#define CN470A_APPLY_DR_OFFSET( ) CN470A_CASE { return RegionCN470AApplyDrOffset( downlinkDwellTime, dr, drOffset ); } +#define CN470A_RX_BEACON_SETUP( ) CN470A_CASE { RegionCN470ARxBeaconSetup( rxBeaconSetup, outDr ); } +#else +#define CN470A_IS_ACTIVE( ) +#define CN470A_GET_PHY_PARAM( ) +#define CN470A_SET_BAND_TX_DONE( ) +#define CN470A_INIT_DEFAULTS( ) +#define CN470A_VERIFY( ) +#define CN470A_APPLY_CF_LIST( ) +#define CN470A_CHAN_MASK_SET( ) +#define CN470A_ADR_NEXT( ) +#define CN470A_COMPUTE_RX_WINDOW_PARAMETERS( ) +#define CN470A_RX_CONFIG( ) +#define CN470A_TX_CONFIG( ) +#define CN470A_LINK_ADR_REQ( ) +#define CN470A_RX_PARAM_SETUP_REQ( ) +#define CN470A_NEW_CHANNEL_REQ( ) +#define CN470A_TX_PARAM_SETUP_REQ( ) +#define CN470A_DL_CHANNEL_REQ( ) +#define CN470A_ALTERNATE_DR( ) +#define CN470A_CALC_BACKOFF( ) +#define CN470A_NEXT_CHANNEL( ) +#define CN470A_CHANNEL_ADD( ) +#define CN470A_CHANNEL_REMOVE( ) +#define CN470A_SET_CONTINUOUS_WAVE( ) +#define CN470A_APPLY_DR_OFFSET( ) +#define CN470A_RX_BEACON_SETUP( ) +#endif + +#ifdef REGION_CN779 +#include "RegionCN779.h" +#define CN779_CASE case LORAMAC_REGION_CN779: +#define CN779_IS_ACTIVE( ) CN779_CASE { return true; } +#define CN779_GET_PHY_PARAM( ) CN779_CASE { return RegionCN779GetPhyParam( getPhy ); } +#define CN779_SET_BAND_TX_DONE( ) CN779_CASE { RegionCN779SetBandTxDone( txDone ); break; } +#define CN779_INIT_DEFAULTS( ) CN779_CASE { RegionCN779InitDefaults( type ); break; } +#define CN779_VERIFY( ) CN779_CASE { return RegionCN779Verify( verify, phyAttribute ); } +#define CN779_APPLY_CF_LIST( ) CN779_CASE { RegionCN779ApplyCFList( applyCFList ); break; } +#define CN779_CHAN_MASK_SET( ) CN779_CASE { return RegionCN779ChanMaskSet( chanMaskSet ); } +#define CN779_ADR_NEXT( ) CN779_CASE { return RegionCN779AdrNext( adrNext, drOut, txPowOut, adrAckCounter ); } +#define CN779_COMPUTE_RX_WINDOW_PARAMETERS( ) CN779_CASE { RegionCN779ComputeRxWindowParameters( datarate, minRxSymbols, rxError, rxConfigParams ); break; } +#define CN779_RX_CONFIG( ) CN779_CASE { return RegionCN779RxConfig( rxConfig, datarate ); } +#define CN779_TX_CONFIG( ) CN779_CASE { return RegionCN779TxConfig( txConfig, txPower, txTimeOnAir ); } +#define CN779_LINK_ADR_REQ( ) CN779_CASE { return RegionCN779LinkAdrReq( linkAdrReq, drOut, txPowOut, nbRepOut, nbBytesParsed ); } +#define CN779_RX_PARAM_SETUP_REQ( ) CN779_CASE { return RegionCN779RxParamSetupReq( rxParamSetupReq ); } +#define CN779_NEW_CHANNEL_REQ( ) CN779_CASE { return RegionCN779NewChannelReq( newChannelReq ); } +#define CN779_TX_PARAM_SETUP_REQ( ) CN779_CASE { return RegionCN779TxParamSetupReq( txParamSetupReq ); } +#define CN779_DL_CHANNEL_REQ( ) CN779_CASE { return RegionCN779DlChannelReq( dlChannelReq ); } +#define CN779_ALTERNATE_DR( ) CN779_CASE { return RegionCN779AlternateDr( alternateDr ); } +#define CN779_CALC_BACKOFF( ) CN779_CASE { RegionCN779CalcBackOff( calcBackOff ); break; } +#define CN779_NEXT_CHANNEL( ) CN779_CASE { return RegionCN779NextChannel( nextChanParams, channel, time, aggregatedTimeOff ); } +#define CN779_CHANNEL_ADD( ) CN779_CASE { return RegionCN779ChannelAdd( channelAdd ); } +#define CN779_CHANNEL_REMOVE( ) CN779_CASE { return RegionCN779ChannelsRemove( channelRemove ); } +#define CN779_SET_CONTINUOUS_WAVE( ) CN779_CASE { RegionCN779SetContinuousWave( continuousWave ); break; } +#define CN779_APPLY_DR_OFFSET( ) CN779_CASE { return RegionCN779ApplyDrOffset( downlinkDwellTime, dr, drOffset ); } +#define CN779_RX_BEACON_SETUP( ) CN779_CASE { RegionCN779RxBeaconSetup( rxBeaconSetup, outDr ); } +#else +#define CN779_IS_ACTIVE( ) +#define CN779_GET_PHY_PARAM( ) +#define CN779_SET_BAND_TX_DONE( ) +#define CN779_INIT_DEFAULTS( ) +#define CN779_VERIFY( ) +#define CN779_APPLY_CF_LIST( ) +#define CN779_CHAN_MASK_SET( ) +#define CN779_ADR_NEXT( ) +#define CN779_COMPUTE_RX_WINDOW_PARAMETERS( ) +#define CN779_RX_CONFIG( ) +#define CN779_TX_CONFIG( ) +#define CN779_LINK_ADR_REQ( ) +#define CN779_RX_PARAM_SETUP_REQ( ) +#define CN779_NEW_CHANNEL_REQ( ) +#define CN779_TX_PARAM_SETUP_REQ( ) +#define CN779_DL_CHANNEL_REQ( ) +#define CN779_ALTERNATE_DR( ) +#define CN779_CALC_BACKOFF( ) +#define CN779_NEXT_CHANNEL( ) +#define CN779_CHANNEL_ADD( ) +#define CN779_CHANNEL_REMOVE( ) +#define CN779_SET_CONTINUOUS_WAVE( ) +#define CN779_APPLY_DR_OFFSET( ) +#define CN779_RX_BEACON_SETUP( ) +#endif + +#ifdef REGION_EU433 +#include "RegionEU433.h" +#define EU433_CASE case LORAMAC_REGION_EU433: +#define EU433_IS_ACTIVE( ) EU433_CASE { return true; } +#define EU433_GET_PHY_PARAM( ) EU433_CASE { return RegionEU433GetPhyParam( getPhy ); } +#define EU433_SET_BAND_TX_DONE( ) EU433_CASE { RegionEU433SetBandTxDone( txDone ); break; } +#define EU433_INIT_DEFAULTS( ) EU433_CASE { RegionEU433InitDefaults( type ); break; } +#define EU433_VERIFY( ) EU433_CASE { return RegionEU433Verify( verify, phyAttribute ); } +#define EU433_APPLY_CF_LIST( ) EU433_CASE { RegionEU433ApplyCFList( applyCFList ); break; } +#define EU433_CHAN_MASK_SET( ) EU433_CASE { return RegionEU433ChanMaskSet( chanMaskSet ); } +#define EU433_ADR_NEXT( ) EU433_CASE { return RegionEU433AdrNext( adrNext, drOut, txPowOut, adrAckCounter ); } +#define EU433_COMPUTE_RX_WINDOW_PARAMETERS( ) EU433_CASE { RegionEU433ComputeRxWindowParameters( datarate, minRxSymbols, rxError, rxConfigParams ); break; } +#define EU433_RX_CONFIG( ) EU433_CASE { return RegionEU433RxConfig( rxConfig, datarate ); } +#define EU433_TX_CONFIG( ) EU433_CASE { return RegionEU433TxConfig( txConfig, txPower, txTimeOnAir ); } +#define EU433_LINK_ADR_REQ( ) EU433_CASE { return RegionEU433LinkAdrReq( linkAdrReq, drOut, txPowOut, nbRepOut, nbBytesParsed ); } +#define EU433_RX_PARAM_SETUP_REQ( ) EU433_CASE { return RegionEU433RxParamSetupReq( rxParamSetupReq ); } +#define EU433_NEW_CHANNEL_REQ( ) EU433_CASE { return RegionEU433NewChannelReq( newChannelReq ); } +#define EU433_TX_PARAM_SETUP_REQ( ) EU433_CASE { return RegionEU433TxParamSetupReq( txParamSetupReq ); } +#define EU433_DL_CHANNEL_REQ( ) EU433_CASE { return RegionEU433DlChannelReq( dlChannelReq ); } +#define EU433_ALTERNATE_DR( ) EU433_CASE { return RegionEU433AlternateDr( alternateDr ); } +#define EU433_CALC_BACKOFF( ) EU433_CASE { RegionEU433CalcBackOff( calcBackOff ); break; } +#define EU433_NEXT_CHANNEL( ) EU433_CASE { return RegionEU433NextChannel( nextChanParams, channel, time, aggregatedTimeOff ); } +#define EU433_CHANNEL_ADD( ) EU433_CASE { return RegionEU433ChannelAdd( channelAdd ); } +#define EU433_CHANNEL_REMOVE( ) EU433_CASE { return RegionEU433ChannelsRemove( channelRemove ); } +#define EU433_SET_CONTINUOUS_WAVE( ) EU433_CASE { RegionEU433SetContinuousWave( continuousWave ); break; } +#define EU433_APPLY_DR_OFFSET( ) EU433_CASE { return RegionEU433ApplyDrOffset( downlinkDwellTime, dr, drOffset ); } +#define EU433_RX_BEACON_SETUP( ) EU433_CASE { RegionEU433RxBeaconSetup( rxBeaconSetup, outDr ); } +#else +#define EU433_IS_ACTIVE( ) +#define EU433_GET_PHY_PARAM( ) +#define EU433_SET_BAND_TX_DONE( ) +#define EU433_INIT_DEFAULTS( ) +#define EU433_VERIFY( ) +#define EU433_APPLY_CF_LIST( ) +#define EU433_CHAN_MASK_SET( ) +#define EU433_ADR_NEXT( ) +#define EU433_COMPUTE_RX_WINDOW_PARAMETERS( ) +#define EU433_RX_CONFIG( ) +#define EU433_TX_CONFIG( ) +#define EU433_LINK_ADR_REQ( ) +#define EU433_RX_PARAM_SETUP_REQ( ) +#define EU433_NEW_CHANNEL_REQ( ) +#define EU433_TX_PARAM_SETUP_REQ( ) +#define EU433_DL_CHANNEL_REQ( ) +#define EU433_ALTERNATE_DR( ) +#define EU433_CALC_BACKOFF( ) +#define EU433_NEXT_CHANNEL( ) +#define EU433_CHANNEL_ADD( ) +#define EU433_CHANNEL_REMOVE( ) +#define EU433_SET_CONTINUOUS_WAVE( ) +#define EU433_APPLY_DR_OFFSET( ) +#define EU433_RX_BEACON_SETUP( ) +#endif + +#ifdef REGION_EU868 +#include "RegionEU868.h" +#define EU868_CASE case LORAMAC_REGION_EU868: +#define EU868_IS_ACTIVE( ) EU868_CASE { return true; } +#define EU868_GET_PHY_PARAM( ) EU868_CASE { return RegionEU868GetPhyParam( getPhy ); } +#define EU868_SET_BAND_TX_DONE( ) EU868_CASE { RegionEU868SetBandTxDone( txDone ); break; } +#define EU868_INIT_DEFAULTS( ) EU868_CASE { RegionEU868InitDefaults( type ); break; } +#define EU868_VERIFY( ) EU868_CASE { return RegionEU868Verify( verify, phyAttribute ); } +#define EU868_APPLY_CF_LIST( ) EU868_CASE { RegionEU868ApplyCFList( applyCFList ); break; } +#define EU868_CHAN_MASK_SET( ) EU868_CASE { return RegionEU868ChanMaskSet( chanMaskSet ); } +#define EU868_ADR_NEXT( ) EU868_CASE { return RegionEU868AdrNext( adrNext, drOut, txPowOut, adrAckCounter ); } +#define EU868_COMPUTE_RX_WINDOW_PARAMETERS( ) EU868_CASE { RegionEU868ComputeRxWindowParameters( datarate, minRxSymbols, rxError, rxConfigParams ); break; } +#define EU868_RX_CONFIG( ) EU868_CASE { return RegionEU868RxConfig( rxConfig, datarate ); } +#define EU868_TX_CONFIG( ) EU868_CASE { return RegionEU868TxConfig( txConfig, txPower, txTimeOnAir ); } +#define EU868_LINK_ADR_REQ( ) EU868_CASE { return RegionEU868LinkAdrReq( linkAdrReq, drOut, txPowOut, nbRepOut, nbBytesParsed ); } +#define EU868_RX_PARAM_SETUP_REQ( ) EU868_CASE { return RegionEU868RxParamSetupReq( rxParamSetupReq ); } +#define EU868_NEW_CHANNEL_REQ( ) EU868_CASE { return RegionEU868NewChannelReq( newChannelReq ); } +#define EU868_TX_PARAM_SETUP_REQ( ) EU868_CASE { return RegionEU868TxParamSetupReq( txParamSetupReq ); } +#define EU868_DL_CHANNEL_REQ( ) EU868_CASE { return RegionEU868DlChannelReq( dlChannelReq ); } +#define EU868_ALTERNATE_DR( ) EU868_CASE { return RegionEU868AlternateDr( alternateDr ); } +#define EU868_CALC_BACKOFF( ) EU868_CASE { RegionEU868CalcBackOff( calcBackOff ); break; } +#define EU868_NEXT_CHANNEL( ) EU868_CASE { return RegionEU868NextChannel( nextChanParams, channel, time, aggregatedTimeOff ); } +#define EU868_CHANNEL_ADD( ) EU868_CASE { return RegionEU868ChannelAdd( channelAdd ); } +#define EU868_CHANNEL_REMOVE( ) EU868_CASE { return RegionEU868ChannelsRemove( channelRemove ); } +#define EU868_SET_CONTINUOUS_WAVE( ) EU868_CASE { RegionEU868SetContinuousWave( continuousWave ); break; } +#define EU868_APPLY_DR_OFFSET( ) EU868_CASE { return RegionEU868ApplyDrOffset( downlinkDwellTime, dr, drOffset ); } +#define EU868_RX_BEACON_SETUP( ) EU868_CASE { RegionEU868RxBeaconSetup( rxBeaconSetup, outDr ); } +#else +#define EU868_IS_ACTIVE( ) +#define EU868_GET_PHY_PARAM( ) +#define EU868_SET_BAND_TX_DONE( ) +#define EU868_INIT_DEFAULTS( ) +#define EU868_VERIFY( ) +#define EU868_APPLY_CF_LIST( ) +#define EU868_CHAN_MASK_SET( ) +#define EU868_ADR_NEXT( ) +#define EU868_COMPUTE_RX_WINDOW_PARAMETERS( ) +#define EU868_RX_CONFIG( ) +#define EU868_TX_CONFIG( ) +#define EU868_LINK_ADR_REQ( ) +#define EU868_RX_PARAM_SETUP_REQ( ) +#define EU868_NEW_CHANNEL_REQ( ) +#define EU868_TX_PARAM_SETUP_REQ( ) +#define EU868_DL_CHANNEL_REQ( ) +#define EU868_ALTERNATE_DR( ) +#define EU868_CALC_BACKOFF( ) +#define EU868_NEXT_CHANNEL( ) +#define EU868_CHANNEL_ADD( ) +#define EU868_CHANNEL_REMOVE( ) +#define EU868_SET_CONTINUOUS_WAVE( ) +#define EU868_APPLY_DR_OFFSET( ) +#define EU868_RX_BEACON_SETUP( ) +#endif + +#ifdef REGION_KR920 +#include "RegionKR920.h" +#define KR920_CASE case LORAMAC_REGION_KR920: +#define KR920_IS_ACTIVE( ) KR920_CASE { return true; } +#define KR920_GET_PHY_PARAM( ) KR920_CASE { return RegionKR920GetPhyParam( getPhy ); } +#define KR920_SET_BAND_TX_DONE( ) KR920_CASE { RegionKR920SetBandTxDone( txDone ); break; } +#define KR920_INIT_DEFAULTS( ) KR920_CASE { RegionKR920InitDefaults( type ); break; } +#define KR920_VERIFY( ) KR920_CASE { return RegionKR920Verify( verify, phyAttribute ); } +#define KR920_APPLY_CF_LIST( ) KR920_CASE { RegionKR920ApplyCFList( applyCFList ); break; } +#define KR920_CHAN_MASK_SET( ) KR920_CASE { return RegionKR920ChanMaskSet( chanMaskSet ); } +#define KR920_ADR_NEXT( ) KR920_CASE { return RegionKR920AdrNext( adrNext, drOut, txPowOut, adrAckCounter ); } +#define KR920_COMPUTE_RX_WINDOW_PARAMETERS( ) KR920_CASE { RegionKR920ComputeRxWindowParameters( datarate, minRxSymbols, rxError, rxConfigParams ); break; } +#define KR920_RX_CONFIG( ) KR920_CASE { return RegionKR920RxConfig( rxConfig, datarate ); } +#define KR920_TX_CONFIG( ) KR920_CASE { return RegionKR920TxConfig( txConfig, txPower, txTimeOnAir ); } +#define KR920_LINK_ADR_REQ( ) KR920_CASE { return RegionKR920LinkAdrReq( linkAdrReq, drOut, txPowOut, nbRepOut, nbBytesParsed ); } +#define KR920_RX_PARAM_SETUP_REQ( ) KR920_CASE { return RegionKR920RxParamSetupReq( rxParamSetupReq ); } +#define KR920_NEW_CHANNEL_REQ( ) KR920_CASE { return RegionKR920NewChannelReq( newChannelReq ); } +#define KR920_TX_PARAM_SETUP_REQ( ) KR920_CASE { return RegionKR920TxParamSetupReq( txParamSetupReq ); } +#define KR920_DL_CHANNEL_REQ( ) KR920_CASE { return RegionKR920DlChannelReq( dlChannelReq ); } +#define KR920_ALTERNATE_DR( ) KR920_CASE { return RegionKR920AlternateDr( alternateDr ); } +#define KR920_CALC_BACKOFF( ) KR920_CASE { RegionKR920CalcBackOff( calcBackOff ); break; } +#define KR920_NEXT_CHANNEL( ) KR920_CASE { return RegionKR920NextChannel( nextChanParams, channel, time, aggregatedTimeOff ); } +#define KR920_CHANNEL_ADD( ) KR920_CASE { return RegionKR920ChannelAdd( channelAdd ); } +#define KR920_CHANNEL_REMOVE( ) KR920_CASE { return RegionKR920ChannelsRemove( channelRemove ); } +#define KR920_SET_CONTINUOUS_WAVE( ) KR920_CASE { RegionKR920SetContinuousWave( continuousWave ); break; } +#define KR920_APPLY_DR_OFFSET( ) KR920_CASE { return RegionKR920ApplyDrOffset( downlinkDwellTime, dr, drOffset ); } +#define KR920_RX_BEACON_SETUP( ) KR920_CASE { RegionKR920RxBeaconSetup( rxBeaconSetup, outDr ); } +#else +#define KR920_IS_ACTIVE( ) +#define KR920_GET_PHY_PARAM( ) +#define KR920_SET_BAND_TX_DONE( ) +#define KR920_INIT_DEFAULTS( ) +#define KR920_VERIFY( ) +#define KR920_APPLY_CF_LIST( ) +#define KR920_CHAN_MASK_SET( ) +#define KR920_ADR_NEXT( ) +#define KR920_COMPUTE_RX_WINDOW_PARAMETERS( ) +#define KR920_RX_CONFIG( ) +#define KR920_TX_CONFIG( ) +#define KR920_LINK_ADR_REQ( ) +#define KR920_RX_PARAM_SETUP_REQ( ) +#define KR920_NEW_CHANNEL_REQ( ) +#define KR920_TX_PARAM_SETUP_REQ( ) +#define KR920_DL_CHANNEL_REQ( ) +#define KR920_ALTERNATE_DR( ) +#define KR920_CALC_BACKOFF( ) +#define KR920_NEXT_CHANNEL( ) +#define KR920_CHANNEL_ADD( ) +#define KR920_CHANNEL_REMOVE( ) +#define KR920_SET_CONTINUOUS_WAVE( ) +#define KR920_APPLY_DR_OFFSET( ) +#define KR920_RX_BEACON_SETUP( ) +#endif + +#ifdef REGION_IN865 +#include "RegionIN865.h" +#define IN865_CASE case LORAMAC_REGION_IN865: +#define IN865_IS_ACTIVE( ) IN865_CASE { return true; } +#define IN865_GET_PHY_PARAM( ) IN865_CASE { return RegionIN865GetPhyParam( getPhy ); } +#define IN865_SET_BAND_TX_DONE( ) IN865_CASE { RegionIN865SetBandTxDone( txDone ); break; } +#define IN865_INIT_DEFAULTS( ) IN865_CASE { RegionIN865InitDefaults( type ); break; } +#define IN865_VERIFY( ) IN865_CASE { return RegionIN865Verify( verify, phyAttribute ); } +#define IN865_APPLY_CF_LIST( ) IN865_CASE { RegionIN865ApplyCFList( applyCFList ); break; } +#define IN865_CHAN_MASK_SET( ) IN865_CASE { return RegionIN865ChanMaskSet( chanMaskSet ); } +#define IN865_ADR_NEXT( ) IN865_CASE { return RegionIN865AdrNext( adrNext, drOut, txPowOut, adrAckCounter ); } +#define IN865_COMPUTE_RX_WINDOW_PARAMETERS( ) IN865_CASE { RegionIN865ComputeRxWindowParameters( datarate, minRxSymbols, rxError, rxConfigParams ); break; } +#define IN865_RX_CONFIG( ) IN865_CASE { return RegionIN865RxConfig( rxConfig, datarate ); } +#define IN865_TX_CONFIG( ) IN865_CASE { return RegionIN865TxConfig( txConfig, txPower, txTimeOnAir ); } +#define IN865_LINK_ADR_REQ( ) IN865_CASE { return RegionIN865LinkAdrReq( linkAdrReq, drOut, txPowOut, nbRepOut, nbBytesParsed ); } +#define IN865_RX_PARAM_SETUP_REQ( ) IN865_CASE { return RegionIN865RxParamSetupReq( rxParamSetupReq ); } +#define IN865_NEW_CHANNEL_REQ( ) IN865_CASE { return RegionIN865NewChannelReq( newChannelReq ); } +#define IN865_TX_PARAM_SETUP_REQ( ) IN865_CASE { return RegionIN865TxParamSetupReq( txParamSetupReq ); } +#define IN865_DL_CHANNEL_REQ( ) IN865_CASE { return RegionIN865DlChannelReq( dlChannelReq ); } +#define IN865_ALTERNATE_DR( ) IN865_CASE { return RegionIN865AlternateDr( alternateDr ); } +#define IN865_CALC_BACKOFF( ) IN865_CASE { RegionIN865CalcBackOff( calcBackOff ); break; } +#define IN865_NEXT_CHANNEL( ) IN865_CASE { return RegionIN865NextChannel( nextChanParams, channel, time, aggregatedTimeOff ); } +#define IN865_CHANNEL_ADD( ) IN865_CASE { return RegionIN865ChannelAdd( channelAdd ); } +#define IN865_CHANNEL_REMOVE( ) IN865_CASE { return RegionIN865ChannelsRemove( channelRemove ); } +#define IN865_SET_CONTINUOUS_WAVE( ) IN865_CASE { RegionIN865SetContinuousWave( continuousWave ); break; } +#define IN865_APPLY_DR_OFFSET( ) IN865_CASE { return RegionIN865ApplyDrOffset( downlinkDwellTime, dr, drOffset ); } +#define IN865_RX_BEACON_SETUP( ) IN865_CASE { RegionIN865RxBeaconSetup( rxBeaconSetup, outDr ); } +#else +#define IN865_IS_ACTIVE( ) +#define IN865_GET_PHY_PARAM( ) +#define IN865_SET_BAND_TX_DONE( ) +#define IN865_INIT_DEFAULTS( ) +#define IN865_VERIFY( ) +#define IN865_APPLY_CF_LIST( ) +#define IN865_CHAN_MASK_SET( ) +#define IN865_ADR_NEXT( ) +#define IN865_COMPUTE_RX_WINDOW_PARAMETERS( ) +#define IN865_RX_CONFIG( ) +#define IN865_TX_CONFIG( ) +#define IN865_LINK_ADR_REQ( ) +#define IN865_RX_PARAM_SETUP_REQ( ) +#define IN865_NEW_CHANNEL_REQ( ) +#define IN865_TX_PARAM_SETUP_REQ( ) +#define IN865_DL_CHANNEL_REQ( ) +#define IN865_ALTERNATE_DR( ) +#define IN865_CALC_BACKOFF( ) +#define IN865_NEXT_CHANNEL( ) +#define IN865_CHANNEL_ADD( ) +#define IN865_CHANNEL_REMOVE( ) +#define IN865_SET_CONTINUOUS_WAVE( ) +#define IN865_APPLY_DR_OFFSET( ) +#define IN865_RX_BEACON_SETUP( ) +#endif + +#ifdef REGION_US915 +#include "RegionUS915.h" +#define US915_CASE case LORAMAC_REGION_US915: +#define US915_IS_ACTIVE( ) US915_CASE { return true; } +#define US915_GET_PHY_PARAM( ) US915_CASE { return RegionUS915GetPhyParam( getPhy ); } +#define US915_SET_BAND_TX_DONE( ) US915_CASE { RegionUS915SetBandTxDone( txDone ); break; } +#define US915_INIT_DEFAULTS( ) US915_CASE { RegionUS915InitDefaults( type ); break; } +#define US915_VERIFY( ) US915_CASE { return RegionUS915Verify( verify, phyAttribute ); } +#define US915_APPLY_CF_LIST( ) US915_CASE { RegionUS915ApplyCFList( applyCFList ); break; } +#define US915_CHAN_MASK_SET( ) US915_CASE { return RegionUS915ChanMaskSet( chanMaskSet ); } +#define US915_ADR_NEXT( ) US915_CASE { return RegionUS915AdrNext( adrNext, drOut, txPowOut, adrAckCounter ); } +#define US915_COMPUTE_RX_WINDOW_PARAMETERS( ) US915_CASE { RegionUS915ComputeRxWindowParameters( datarate, minRxSymbols, rxError, rxConfigParams ); break; } +#define US915_RX_CONFIG( ) US915_CASE { return RegionUS915RxConfig( rxConfig, datarate ); } +#define US915_TX_CONFIG( ) US915_CASE { return RegionUS915TxConfig( txConfig, txPower, txTimeOnAir ); } +#define US915_LINK_ADR_REQ( ) US915_CASE { return RegionUS915LinkAdrReq( linkAdrReq, drOut, txPowOut, nbRepOut, nbBytesParsed ); } +#define US915_RX_PARAM_SETUP_REQ( ) US915_CASE { return RegionUS915RxParamSetupReq( rxParamSetupReq ); } +#define US915_NEW_CHANNEL_REQ( ) US915_CASE { return RegionUS915NewChannelReq( newChannelReq ); } +#define US915_TX_PARAM_SETUP_REQ( ) US915_CASE { return RegionUS915TxParamSetupReq( txParamSetupReq ); } +#define US915_DL_CHANNEL_REQ( ) US915_CASE { return RegionUS915DlChannelReq( dlChannelReq ); } +#define US915_ALTERNATE_DR( ) US915_CASE { return RegionUS915AlternateDr( alternateDr ); } +#define US915_CALC_BACKOFF( ) US915_CASE { RegionUS915CalcBackOff( calcBackOff ); break; } +#define US915_NEXT_CHANNEL( ) US915_CASE { return RegionUS915NextChannel( nextChanParams, channel, time, aggregatedTimeOff ); } +#define US915_CHANNEL_ADD( ) US915_CASE { return RegionUS915ChannelAdd( channelAdd ); } +#define US915_CHANNEL_REMOVE( ) US915_CASE { return RegionUS915ChannelsRemove( channelRemove ); } +#define US915_SET_CONTINUOUS_WAVE( ) US915_CASE { RegionUS915SetContinuousWave( continuousWave ); break; } +#define US915_APPLY_DR_OFFSET( ) US915_CASE { return RegionUS915ApplyDrOffset( downlinkDwellTime, dr, drOffset ); } +#define US915_RX_BEACON_SETUP( ) US915_CASE { RegionUS915RxBeaconSetup( rxBeaconSetup, outDr ); } +#else +#define US915_IS_ACTIVE( ) +#define US915_GET_PHY_PARAM( ) +#define US915_SET_BAND_TX_DONE( ) +#define US915_INIT_DEFAULTS( ) +#define US915_VERIFY( ) +#define US915_APPLY_CF_LIST( ) +#define US915_CHAN_MASK_SET( ) +#define US915_ADR_NEXT( ) +#define US915_COMPUTE_RX_WINDOW_PARAMETERS( ) +#define US915_RX_CONFIG( ) +#define US915_TX_CONFIG( ) +#define US915_LINK_ADR_REQ( ) +#define US915_RX_PARAM_SETUP_REQ( ) +#define US915_NEW_CHANNEL_REQ( ) +#define US915_TX_PARAM_SETUP_REQ( ) +#define US915_DL_CHANNEL_REQ( ) +#define US915_ALTERNATE_DR( ) +#define US915_CALC_BACKOFF( ) +#define US915_NEXT_CHANNEL( ) +#define US915_CHANNEL_ADD( ) +#define US915_CHANNEL_REMOVE( ) +#define US915_SET_CONTINUOUS_WAVE( ) +#define US915_APPLY_DR_OFFSET( ) +#define US915_RX_BEACON_SETUP( ) +#endif + +#ifdef REGION_US915_HYBRID +#include "RegionUS915-Hybrid.h" +#define US915_HYBRID_CASE case LORAMAC_REGION_US915_HYBRID: +#define US915_HYBRID_IS_ACTIVE( ) US915_HYBRID_CASE { return true; } +#define US915_HYBRID_GET_PHY_PARAM( ) US915_HYBRID_CASE { return RegionUS915HybridGetPhyParam( getPhy ); } +#define US915_HYBRID_SET_BAND_TX_DONE( ) US915_HYBRID_CASE { RegionUS915HybridSetBandTxDone( txDone ); break; } +#define US915_HYBRID_INIT_DEFAULTS( ) US915_HYBRID_CASE { RegionUS915HybridInitDefaults( type ); break; } +#define US915_HYBRID_VERIFY( ) US915_HYBRID_CASE { return RegionUS915HybridVerify( verify, phyAttribute ); } +#define US915_HYBRID_APPLY_CF_LIST( ) US915_HYBRID_CASE { RegionUS915HybridApplyCFList( applyCFList ); break; } +#define US915_HYBRID_CHAN_MASK_SET( ) US915_HYBRID_CASE { return RegionUS915HybridChanMaskSet( chanMaskSet ); } +#define US915_HYBRID_ADR_NEXT( ) US915_HYBRID_CASE { return RegionUS915HybridAdrNext( adrNext, drOut, txPowOut, adrAckCounter ); } +#define US915_HYBRID_COMPUTE_RX_WINDOW_PARAMETERS( ) US915_HYBRID_CASE { RegionUS915HybridComputeRxWindowParameters( datarate, minRxSymbols, rxError, rxConfigParams ); break; } +#define US915_HYBRID_RX_CONFIG( ) US915_HYBRID_CASE { return RegionUS915HybridRxConfig( rxConfig, datarate ); } +#define US915_HYBRID_TX_CONFIG( ) US915_HYBRID_CASE { return RegionUS915HybridTxConfig( txConfig, txPower, txTimeOnAir ); } +#define US915_HYBRID_LINK_ADR_REQ( ) US915_HYBRID_CASE { return RegionUS915HybridLinkAdrReq( linkAdrReq, drOut, txPowOut, nbRepOut, nbBytesParsed ); } +#define US915_HYBRID_RX_PARAM_SETUP_REQ( ) US915_HYBRID_CASE { return RegionUS915HybridRxParamSetupReq( rxParamSetupReq ); } +#define US915_HYBRID_NEW_CHANNEL_REQ( ) US915_HYBRID_CASE { return RegionUS915HybridNewChannelReq( newChannelReq ); } +#define US915_HYBRID_TX_PARAM_SETUP_REQ( ) US915_HYBRID_CASE { return RegionUS915HybridTxParamSetupReq( txParamSetupReq ); } +#define US915_HYBRID_DL_CHANNEL_REQ( ) US915_HYBRID_CASE { return RegionUS915HybridDlChannelReq( dlChannelReq ); } +#define US915_HYBRID_ALTERNATE_DR( ) US915_HYBRID_CASE { return RegionUS915HybridAlternateDr( alternateDr ); } +#define US915_HYBRID_CALC_BACKOFF( ) US915_HYBRID_CASE { RegionUS915HybridCalcBackOff( calcBackOff ); break; } +#define US915_HYBRID_NEXT_CHANNEL( ) US915_HYBRID_CASE { return RegionUS915HybridNextChannel( nextChanParams, channel, time, aggregatedTimeOff ); } +#define US915_HYBRID_CHANNEL_ADD( ) US915_HYBRID_CASE { return RegionUS915HybridChannelAdd( channelAdd ); } +#define US915_HYBRID_CHANNEL_REMOVE( ) US915_HYBRID_CASE { return RegionUS915HybridChannelsRemove( channelRemove ); } +#define US915_HYBRID_SET_CONTINUOUS_WAVE( ) US915_HYBRID_CASE { RegionUS915HybridSetContinuousWave( continuousWave ); break; } +#define US915_HYBRID_APPLY_DR_OFFSET( ) US915_HYBRID_CASE { return RegionUS915HybridApplyDrOffset( downlinkDwellTime, dr, drOffset ); } +#define US915_HYBRID_RX_BEACON_SETUP( ) US915_HYBRID_CASE { RegionUS915HybridRxBeaconSetup( rxBeaconSetup, outDr ); } +#else +#define US915_HYBRID_IS_ACTIVE( ) +#define US915_HYBRID_GET_PHY_PARAM( ) +#define US915_HYBRID_SET_BAND_TX_DONE( ) +#define US915_HYBRID_INIT_DEFAULTS( ) +#define US915_HYBRID_VERIFY( ) +#define US915_HYBRID_APPLY_CF_LIST( ) +#define US915_HYBRID_CHAN_MASK_SET( ) +#define US915_HYBRID_ADR_NEXT( ) +#define US915_HYBRID_COMPUTE_RX_WINDOW_PARAMETERS( ) +#define US915_HYBRID_RX_CONFIG( ) +#define US915_HYBRID_TX_CONFIG( ) +#define US915_HYBRID_LINK_ADR_REQ( ) +#define US915_HYBRID_RX_PARAM_SETUP_REQ( ) +#define US915_HYBRID_NEW_CHANNEL_REQ( ) +#define US915_HYBRID_TX_PARAM_SETUP_REQ( ) +#define US915_HYBRID_DL_CHANNEL_REQ( ) +#define US915_HYBRID_ALTERNATE_DR( ) +#define US915_HYBRID_CALC_BACKOFF( ) +#define US915_HYBRID_NEXT_CHANNEL( ) +#define US915_HYBRID_CHANNEL_ADD( ) +#define US915_HYBRID_CHANNEL_REMOVE( ) +#define US915_HYBRID_SET_CONTINUOUS_WAVE( ) +#define US915_HYBRID_APPLY_DR_OFFSET( ) +#define US915_HYBRID_RX_BEACON_SETUP( ) +#endif + +bool RegionIsActive( LoRaMacRegion_t region ) +{ + switch( region ) + { + AS923_IS_ACTIVE( ); + AU915_IS_ACTIVE( ); + CN470_IS_ACTIVE( ); + CN470A_IS_ACTIVE( ); + CN779_IS_ACTIVE( ); + EU433_IS_ACTIVE( ); + EU868_IS_ACTIVE( ); + KR920_IS_ACTIVE( ); + IN865_IS_ACTIVE( ); + US915_IS_ACTIVE( ); + US915_HYBRID_IS_ACTIVE( ); + default: + { + return false; + } + } +} + +PhyParam_t RegionGetPhyParam( LoRaMacRegion_t region, GetPhyParams_t* getPhy ) +{ + PhyParam_t phyParam = { 0 }; + switch( region ) + { + AS923_GET_PHY_PARAM( ); + AU915_GET_PHY_PARAM( ); + CN470_GET_PHY_PARAM( ); + CN470A_GET_PHY_PARAM( ); + CN779_GET_PHY_PARAM( ); + EU433_GET_PHY_PARAM( ); + EU868_GET_PHY_PARAM( ); + KR920_GET_PHY_PARAM( ); + IN865_GET_PHY_PARAM( ); + US915_GET_PHY_PARAM( ); + US915_HYBRID_GET_PHY_PARAM( ); + default: + { + return phyParam; + } + } +} + +void RegionSetBandTxDone( LoRaMacRegion_t region, SetBandTxDoneParams_t* txDone ) +{ + switch( region ) + { + AS923_SET_BAND_TX_DONE( ); + AU915_SET_BAND_TX_DONE( ); + CN470_SET_BAND_TX_DONE( ); + CN470A_SET_BAND_TX_DONE( ); + CN779_SET_BAND_TX_DONE( ); + EU433_SET_BAND_TX_DONE( ); + EU868_SET_BAND_TX_DONE( ); + KR920_SET_BAND_TX_DONE( ); + IN865_SET_BAND_TX_DONE( ); + US915_SET_BAND_TX_DONE( ); + US915_HYBRID_SET_BAND_TX_DONE( ); + default: + { + return; + } + } +} + +void RegionInitDefaults( LoRaMacRegion_t region, InitType_t type ) +{ + switch( region ) + { + AS923_INIT_DEFAULTS( ); + AU915_INIT_DEFAULTS( ); + CN470_INIT_DEFAULTS( ); + CN470A_INIT_DEFAULTS( ); + CN779_INIT_DEFAULTS( ); + EU433_INIT_DEFAULTS( ); + EU868_INIT_DEFAULTS( ); + KR920_INIT_DEFAULTS( ); + IN865_INIT_DEFAULTS( ); + US915_INIT_DEFAULTS( ); + US915_HYBRID_INIT_DEFAULTS( ); + default: + { + break; + } + } +} + +bool RegionVerify( LoRaMacRegion_t region, VerifyParams_t* verify, PhyAttribute_t phyAttribute ) +{ + switch( region ) + { + AS923_VERIFY( ); + AU915_VERIFY( ); + CN470_VERIFY( ); + CN470A_VERIFY( ); + CN779_VERIFY( ); + EU433_VERIFY( ); + EU868_VERIFY( ); + KR920_VERIFY( ); + IN865_VERIFY( ); + US915_VERIFY( ); + US915_HYBRID_VERIFY( ); + default: + { + return false; + } + } +} + +void RegionApplyCFList( LoRaMacRegion_t region, ApplyCFListParams_t* applyCFList ) +{ + switch( region ) + { + AS923_APPLY_CF_LIST( ); + AU915_APPLY_CF_LIST( ); + CN470_APPLY_CF_LIST( ); + CN470A_APPLY_CF_LIST( ); + CN779_APPLY_CF_LIST( ); + EU433_APPLY_CF_LIST( ); + EU868_APPLY_CF_LIST( ); + KR920_APPLY_CF_LIST( ); + IN865_APPLY_CF_LIST( ); + US915_APPLY_CF_LIST( ); + US915_HYBRID_APPLY_CF_LIST( ); + default: + { + break; + } + } +} + +bool RegionChanMaskSet( LoRaMacRegion_t region, ChanMaskSetParams_t* chanMaskSet ) +{ + switch( region ) + { + AS923_CHAN_MASK_SET( ); + AU915_CHAN_MASK_SET( ); + CN470_CHAN_MASK_SET( ); + CN470A_CHAN_MASK_SET( ); + CN779_CHAN_MASK_SET( ); + EU433_CHAN_MASK_SET( ); + EU868_CHAN_MASK_SET( ); + KR920_CHAN_MASK_SET( ); + IN865_CHAN_MASK_SET( ); + US915_CHAN_MASK_SET( ); + US915_HYBRID_CHAN_MASK_SET( ); + default: + { + return false; + } + } +} + +bool RegionAdrNext( LoRaMacRegion_t region, AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ) +{ + switch( region ) + { + AS923_ADR_NEXT( ); + AU915_ADR_NEXT( ); + CN470_ADR_NEXT( ); + CN470A_ADR_NEXT( ); + CN779_ADR_NEXT( ); + EU433_ADR_NEXT( ); + EU868_ADR_NEXT( ); + KR920_ADR_NEXT( ); + IN865_ADR_NEXT( ); + US915_ADR_NEXT( ); + US915_HYBRID_ADR_NEXT( ); + default: + { + return false; + } + } +} + +void RegionComputeRxWindowParameters( LoRaMacRegion_t region, int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ) +{ + switch( region ) + { + AS923_COMPUTE_RX_WINDOW_PARAMETERS( ); + AU915_COMPUTE_RX_WINDOW_PARAMETERS( ); + CN470_COMPUTE_RX_WINDOW_PARAMETERS( ); + CN470A_COMPUTE_RX_WINDOW_PARAMETERS( ); + CN779_COMPUTE_RX_WINDOW_PARAMETERS( ); + EU433_COMPUTE_RX_WINDOW_PARAMETERS( ); + EU868_COMPUTE_RX_WINDOW_PARAMETERS( ); + KR920_COMPUTE_RX_WINDOW_PARAMETERS( ); + IN865_COMPUTE_RX_WINDOW_PARAMETERS( ); + US915_COMPUTE_RX_WINDOW_PARAMETERS( ); + US915_HYBRID_COMPUTE_RX_WINDOW_PARAMETERS( ); + default: + { + break; + } + } +} + +bool RegionRxConfig( LoRaMacRegion_t region, RxConfigParams_t* rxConfig, int8_t* datarate ) +{ + switch( region ) + { + AS923_RX_CONFIG( ); + AU915_RX_CONFIG( ); + CN470_RX_CONFIG( ); + CN470A_RX_CONFIG( ); + CN779_RX_CONFIG( ); + EU433_RX_CONFIG( ); + EU868_RX_CONFIG( ); + KR920_RX_CONFIG( ); + IN865_RX_CONFIG( ); + US915_RX_CONFIG( ); + US915_HYBRID_RX_CONFIG( ); + default: + { + return false; + } + } +} + +bool RegionTxConfig( LoRaMacRegion_t region, TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) +{ + switch( region ) + { + AS923_TX_CONFIG( ); + AU915_TX_CONFIG( ); + CN470_TX_CONFIG( ); + CN470A_TX_CONFIG( ); + CN779_TX_CONFIG( ); + EU433_TX_CONFIG( ); + EU868_TX_CONFIG( ); + KR920_TX_CONFIG( ); + IN865_TX_CONFIG( ); + US915_TX_CONFIG( ); + US915_HYBRID_TX_CONFIG( ); + default: + { + return false; + } + } +} + +uint8_t RegionLinkAdrReq( LoRaMacRegion_t region, LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ) +{ + switch( region ) + { + AS923_LINK_ADR_REQ( ); + AU915_LINK_ADR_REQ( ); + CN470_LINK_ADR_REQ( ); + CN470A_LINK_ADR_REQ( ); + CN779_LINK_ADR_REQ( ); + EU433_LINK_ADR_REQ( ); + EU868_LINK_ADR_REQ( ); + KR920_LINK_ADR_REQ( ); + IN865_LINK_ADR_REQ( ); + US915_LINK_ADR_REQ( ); + US915_HYBRID_LINK_ADR_REQ( ); + default: + { + return 0; + } + } +} + +uint8_t RegionRxParamSetupReq( LoRaMacRegion_t region, RxParamSetupReqParams_t* rxParamSetupReq ) +{ + switch( region ) + { + AS923_RX_PARAM_SETUP_REQ( ); + AU915_RX_PARAM_SETUP_REQ( ); + CN470_RX_PARAM_SETUP_REQ( ); + CN470A_RX_PARAM_SETUP_REQ( ); + CN779_RX_PARAM_SETUP_REQ( ); + EU433_RX_PARAM_SETUP_REQ( ); + EU868_RX_PARAM_SETUP_REQ( ); + KR920_RX_PARAM_SETUP_REQ( ); + IN865_RX_PARAM_SETUP_REQ( ); + US915_RX_PARAM_SETUP_REQ( ); + US915_HYBRID_RX_PARAM_SETUP_REQ( ); + default: + { + return 0; + } + } +} + +uint8_t RegionNewChannelReq( LoRaMacRegion_t region, NewChannelReqParams_t* newChannelReq ) +{ + switch( region ) + { + AS923_NEW_CHANNEL_REQ( ); + AU915_NEW_CHANNEL_REQ( ); + CN470_NEW_CHANNEL_REQ( ); + CN470A_NEW_CHANNEL_REQ( ); + CN779_NEW_CHANNEL_REQ( ); + EU433_NEW_CHANNEL_REQ( ); + EU868_NEW_CHANNEL_REQ( ); + KR920_NEW_CHANNEL_REQ( ); + IN865_NEW_CHANNEL_REQ( ); + US915_NEW_CHANNEL_REQ( ); + US915_HYBRID_NEW_CHANNEL_REQ( ); + default: + { + return 0; + } + } +} + +int8_t RegionTxParamSetupReq( LoRaMacRegion_t region, TxParamSetupReqParams_t* txParamSetupReq ) +{ + switch( region ) + { + AS923_TX_PARAM_SETUP_REQ( ); + AU915_TX_PARAM_SETUP_REQ( ); + CN470_TX_PARAM_SETUP_REQ( ); + CN470A_TX_PARAM_SETUP_REQ( ); + CN779_TX_PARAM_SETUP_REQ( ); + EU433_TX_PARAM_SETUP_REQ( ); + EU868_TX_PARAM_SETUP_REQ( ); + KR920_TX_PARAM_SETUP_REQ( ); + IN865_TX_PARAM_SETUP_REQ( ); + US915_TX_PARAM_SETUP_REQ( ); + US915_HYBRID_TX_PARAM_SETUP_REQ( ); + default: + { + return 0; + } + } +} + +uint8_t RegionDlChannelReq( LoRaMacRegion_t region, DlChannelReqParams_t* dlChannelReq ) +{ + switch( region ) + { + AS923_DL_CHANNEL_REQ( ); + AU915_DL_CHANNEL_REQ( ); + CN470_DL_CHANNEL_REQ( ); + CN470A_DL_CHANNEL_REQ( ); + CN779_DL_CHANNEL_REQ( ); + EU433_DL_CHANNEL_REQ( ); + EU868_DL_CHANNEL_REQ( ); + KR920_DL_CHANNEL_REQ( ); + IN865_DL_CHANNEL_REQ( ); + US915_DL_CHANNEL_REQ( ); + US915_HYBRID_DL_CHANNEL_REQ( ); + default: + { + return 0; + } + } +} + +int8_t RegionAlternateDr( LoRaMacRegion_t region, AlternateDrParams_t* alternateDr ) +{ + switch( region ) + { + AS923_ALTERNATE_DR( ); + AU915_ALTERNATE_DR( ); + CN470_ALTERNATE_DR( ); + CN470A_ALTERNATE_DR( ); + CN779_ALTERNATE_DR( ); + EU433_ALTERNATE_DR( ); + EU868_ALTERNATE_DR( ); + KR920_ALTERNATE_DR( ); + IN865_ALTERNATE_DR( ); + US915_ALTERNATE_DR( ); + US915_HYBRID_ALTERNATE_DR( ); + default: + { + return 0; + } + } +} + +void RegionCalcBackOff( LoRaMacRegion_t region, CalcBackOffParams_t* calcBackOff ) +{ + switch( region ) + { + AS923_CALC_BACKOFF( ); + AU915_CALC_BACKOFF( ); + CN470_CALC_BACKOFF( ); + CN470A_CALC_BACKOFF( ); + CN779_CALC_BACKOFF( ); + EU433_CALC_BACKOFF( ); + EU868_CALC_BACKOFF( ); + KR920_CALC_BACKOFF( ); + IN865_CALC_BACKOFF( ); + US915_CALC_BACKOFF( ); + US915_HYBRID_CALC_BACKOFF( ); + default: + { + break; + } + } +} + +bool RegionNextChannel( LoRaMacRegion_t region, NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ) +{ + switch( region ) + { + AS923_NEXT_CHANNEL( ); + AU915_NEXT_CHANNEL( ); + CN470_NEXT_CHANNEL( ); + CN470A_NEXT_CHANNEL( ); + CN779_NEXT_CHANNEL( ); + EU433_NEXT_CHANNEL( ); + EU868_NEXT_CHANNEL( ); + KR920_NEXT_CHANNEL( ); + IN865_NEXT_CHANNEL( ); + US915_NEXT_CHANNEL( ); + US915_HYBRID_NEXT_CHANNEL( ); + default: + { + return false; + } + } +} + +LoRaMacStatus_t RegionChannelAdd( LoRaMacRegion_t region, ChannelAddParams_t* channelAdd ) +{ + switch( region ) + { + AS923_CHANNEL_ADD( ); + AU915_CHANNEL_ADD( ); + CN470_CHANNEL_ADD( ); + CN470A_CHANNEL_ADD( ); + CN779_CHANNEL_ADD( ); + EU433_CHANNEL_ADD( ); + EU868_CHANNEL_ADD( ); + KR920_CHANNEL_ADD( ); + IN865_CHANNEL_ADD( ); + US915_CHANNEL_ADD( ); + US915_HYBRID_CHANNEL_ADD( ); + default: + { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + } +} + +bool RegionChannelsRemove( LoRaMacRegion_t region, ChannelRemoveParams_t* channelRemove ) +{ + switch( region ) + { + AS923_CHANNEL_REMOVE( ); + AU915_CHANNEL_REMOVE( ); + CN470_CHANNEL_REMOVE( ); + CN470A_CHANNEL_REMOVE( ); + CN779_CHANNEL_REMOVE( ); + EU433_CHANNEL_REMOVE( ); + EU868_CHANNEL_REMOVE( ); + KR920_CHANNEL_REMOVE( ); + IN865_CHANNEL_REMOVE( ); + US915_CHANNEL_REMOVE( ); + US915_HYBRID_CHANNEL_REMOVE( ); + default: + { + return false; + } + } +} + +void RegionSetContinuousWave( LoRaMacRegion_t region, ContinuousWaveParams_t* continuousWave ) +{ + switch( region ) + { + AS923_SET_CONTINUOUS_WAVE( ); + AU915_SET_CONTINUOUS_WAVE( ); + CN470_SET_CONTINUOUS_WAVE( ); + CN470A_SET_CONTINUOUS_WAVE( ); + CN779_SET_CONTINUOUS_WAVE( ); + EU433_SET_CONTINUOUS_WAVE( ); + EU868_SET_CONTINUOUS_WAVE( ); + KR920_SET_CONTINUOUS_WAVE( ); + IN865_SET_CONTINUOUS_WAVE( ); + US915_SET_CONTINUOUS_WAVE( ); + US915_HYBRID_SET_CONTINUOUS_WAVE( ); + default: + { + break; + } + } +} + +uint8_t RegionApplyDrOffset( LoRaMacRegion_t region, uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +{ + switch( region ) + { + AS923_APPLY_DR_OFFSET( ); + AU915_APPLY_DR_OFFSET( ); + CN470_APPLY_DR_OFFSET( ); + CN470A_APPLY_DR_OFFSET( ); + CN779_APPLY_DR_OFFSET( ); + EU433_APPLY_DR_OFFSET( ); + EU868_APPLY_DR_OFFSET( ); + KR920_APPLY_DR_OFFSET( ); + IN865_APPLY_DR_OFFSET( ); + US915_APPLY_DR_OFFSET( ); + US915_HYBRID_APPLY_DR_OFFSET( ); + default: + { + return dr; + } + } +} + +void RegionRxBeaconSetup( LoRaMacRegion_t region, RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ) +{ + switch( region ) + { + AS923_RX_BEACON_SETUP( ); + AU915_RX_BEACON_SETUP( ); + CN470_RX_BEACON_SETUP( ); + CN470A_RX_BEACON_SETUP( ); + CN779_RX_BEACON_SETUP( ); + EU433_RX_BEACON_SETUP( ); + EU868_RX_BEACON_SETUP( ); + KR920_RX_BEACON_SETUP( ); + IN865_RX_BEACON_SETUP( ); + US915_RX_BEACON_SETUP( ); + US915_HYBRID_RX_BEACON_SETUP( ); + default: + { + break; + } + } +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/Region.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/Region.h new file mode 100644 index 00000000..24883c69 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/Region.h @@ -0,0 +1,1627 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file Region.h + * + * \brief Region implementation. + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGION Region implementation + * This is the common API to access the specific + * regional implementations. + * + * Preprocessor options: + * - LoRaWAN regions can be activated by defining the related preprocessor + * definition. It is possible to define more than one region. + * The following regions are supported: + * - #define REGION_AS923 + * - #define REGION_AU915 + * - #define REGION_CN470 + * - #define REGION_CN779 + * - #define REGION_EU433 + * - #define REGION_EU868 + * - #define REGION_KR920 + * - #define REGION_IN865 + * - #define REGION_US915 + * - #define REGION_US915_HYBRID + * + * \{ + */ +#ifndef __REGION_H__ +#define __REGION_H__ + +/*! + * Macro to compute bit of a channel index. + */ +#define LC( channelIndex ) ( uint16_t )( 1 << ( channelIndex - 1 ) ) + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | SF12 - BW125 + * AU915 | SF10 - BW125 + * CN470 | SF12 - BW125 + * CN779 | SF12 - BW125 + * EU433 | SF12 - BW125 + * EU868 | SF12 - BW125 + * IN865 | SF12 - BW125 + * KR920 | SF12 - BW125 + * US915 | SF10 - BW125 + * US915_HYBRID | SF10 - BW125 + */ +#define DR_0 0 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | SF11 - BW125 + * AU915 | SF9 - BW125 + * CN470 | SF11 - BW125 + * CN779 | SF11 - BW125 + * EU433 | SF11 - BW125 + * EU868 | SF11 - BW125 + * IN865 | SF11 - BW125 + * KR920 | SF11 - BW125 + * US915 | SF9 - BW125 + * US915_HYBRID | SF9 - BW125 + */ +#define DR_1 1 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | SF10 - BW125 + * AU915 | SF8 - BW125 + * CN470 | SF10 - BW125 + * CN779 | SF10 - BW125 + * EU433 | SF10 - BW125 + * EU868 | SF10 - BW125 + * IN865 | SF10 - BW125 + * KR920 | SF10 - BW125 + * US915 | SF8 - BW125 + * US915_HYBRID | SF8 - BW125 + */ +#define DR_2 2 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | SF9 - BW125 + * AU915 | SF7 - BW125 + * CN470 | SF9 - BW125 + * CN779 | SF9 - BW125 + * EU433 | SF9 - BW125 + * EU868 | SF9 - BW125 + * IN865 | SF9 - BW125 + * KR920 | SF9 - BW125 + * US915 | SF7 - BW125 + * US915_HYBRID | SF7 - BW125 + */ +#define DR_3 3 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | SF8 - BW125 + * AU915 | SF8 - BW500 + * CN470 | SF8 - BW125 + * CN779 | SF8 - BW125 + * EU433 | SF8 - BW125 + * EU868 | SF8 - BW125 + * IN865 | SF8 - BW125 + * KR920 | SF8 - BW125 + * US915 | SF8 - BW500 + * US915_HYBRID | SF8 - BW500 + */ +#define DR_4 4 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | SF7 - BW125 + * AU915 | RFU + * CN470 | SF7 - BW125 + * CN779 | SF7 - BW125 + * EU433 | SF7 - BW125 + * EU868 | SF7 - BW125 + * IN865 | SF7 - BW125 + * KR920 | SF7 - BW125 + * US915 | RFU + * US915_HYBRID | RFU + */ +#define DR_5 5 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | SF7 - BW250 + * AU915 | RFU + * CN470 | SF12 - BW125 + * CN779 | SF7 - BW250 + * EU433 | SF7 - BW250 + * EU868 | SF7 - BW250 + * IN865 | SF7 - BW250 + * KR920 | RFU + * US915 | RFU + * US915_HYBRID | RFU + */ +#define DR_6 6 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | FSK + * AU915 | RFU + * CN470 | SF12 - BW125 + * CN779 | FSK + * EU433 | FSK + * EU868 | FSK + * IN865 | FSK + * KR920 | RFU + * US915 | RFU + * US915_HYBRID | RFU + */ +#define DR_7 7 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | RFU + * AU915 | SF12 - BW500 + * CN470 | RFU + * CN779 | RFU + * EU433 | RFU + * EU868 | RFU + * IN865 | RFU + * KR920 | RFU + * US915 | SF12 - BW500 + * US915_HYBRID | SF12 - BW500 + */ +#define DR_8 8 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | RFU + * AU915 | SF11 - BW500 + * CN470 | RFU + * CN779 | RFU + * EU433 | RFU + * EU868 | RFU + * IN865 | RFU + * KR920 | RFU + * US915 | SF11 - BW500 + * US915_HYBRID | SF11 - BW500 + */ +#define DR_9 9 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | RFU + * AU915 | SF10 - BW500 + * CN470 | RFU + * CN779 | RFU + * EU433 | RFU + * EU868 | RFU + * IN865 | RFU + * KR920 | RFU + * US915 | SF10 - BW500 + * US915_HYBRID | SF10 - BW500 + */ +#define DR_10 10 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | RFU + * AU915 | SF9 - BW500 + * CN470 | RFU + * CN779 | RFU + * EU433 | RFU + * EU868 | RFU + * IN865 | RFU + * KR920 | RFU + * US915 | SF9 - BW500 + * US915_HYBRID | SF9 - BW500 + */ +#define DR_11 11 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | RFU + * AU915 | SF8 - BW500 + * CN470 | RFU + * CN779 | RFU + * EU433 | RFU + * EU868 | RFU + * IN865 | RFU + * KR920 | RFU + * US915 | SF8 - BW500 + * US915_HYBRID | SF8 - BW500 + */ +#define DR_12 12 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | RFU + * AU915 | SF7 - BW500 + * CN470 | RFU + * CN779 | RFU + * EU433 | RFU + * EU868 | RFU + * IN865 | RFU + * KR920 | RFU + * US915 | SF7 - BW500 + * US915_HYBRID | SF7 - BW500 + */ +#define DR_13 13 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | RFU + * AU915 | RFU + * CN470 | RFU + * CN779 | RFU + * EU433 | RFU + * EU868 | RFU + * IN865 | RFU + * KR920 | RFU + * US915 | RFU + * US915_HYBRID | RFU + */ +#define DR_14 14 + +/*! + * Region | SF + * ------------ | :-----: + * AS923 | RFU + * AU915 | RFU + * CN470 | RFU + * CN779 | RFU + * EU433 | RFU + * EU868 | RFU + * IN865 | RFU + * KR920 | RFU + * US915 | RFU + * US915_HYBRID | RFU + */ +#define DR_15 15 + + + +/*! + * Region | dBM + * ------------ | :-----: + * AS923 | Max EIRP + * AU915 | Max EIRP + * CN470 | Max EIRP + * CN779 | Max EIRP + * EU433 | Max EIRP + * EU868 | Max EIRP + * IN865 | Max EIRP + * KR920 | Max EIRP + * US915 | Max ERP + * US915_HYBRID | Max ERP + */ +#define TX_POWER_0 0 + +/*! + * Region | dBM + * ------------ | :-----: + * AS923 | Max EIRP - 2 + * AU915 | Max EIRP - 2 + * CN470 | Max EIRP - 2 + * CN779 | Max EIRP - 2 + * EU433 | Max EIRP - 2 + * EU868 | Max EIRP - 2 + * IN865 | Max EIRP - 2 + * KR920 | Max EIRP - 2 + * US915 | Max ERP - 2 + * US915_HYBRID | Max ERP - 2 + */ +#define TX_POWER_1 1 + +/*! + * Region | dBM + * ------------ | :-----: + * AS923 | Max EIRP - 4 + * AU915 | Max EIRP - 4 + * CN470 | Max EIRP - 4 + * CN779 | Max EIRP - 4 + * EU433 | Max EIRP - 4 + * EU868 | Max EIRP - 4 + * IN865 | Max EIRP - 4 + * KR920 | Max EIRP - 4 + * US915 | Max ERP - 4 + * US915_HYBRID | Max ERP - 4 + */ +#define TX_POWER_2 2 + +/*! + * Region | dBM + * ------------ | :-----: + * AS923 | Max EIRP - 6 + * AU915 | Max EIRP - 6 + * CN470 | Max EIRP - 6 + * CN779 | Max EIRP - 6 + * EU433 | Max EIRP - 6 + * EU868 | Max EIRP - 6 + * IN865 | Max EIRP - 6 + * KR920 | Max EIRP - 6 + * US915 | Max ERP - 6 + * US915_HYBRID | Max ERP - 6 + */ +#define TX_POWER_3 3 + +/*! + * Region | dBM + * ------------ | :-----: + * AS923 | Max EIRP - 8 + * AU915 | Max EIRP - 8 + * CN470 | Max EIRP - 8 + * CN779 | Max EIRP - 8 + * EU433 | Max EIRP - 8 + * EU868 | Max EIRP - 8 + * IN865 | Max EIRP - 8 + * KR920 | Max EIRP - 8 + * US915 | Max ERP - 8 + * US915_HYBRID | Max ERP - 8 + */ +#define TX_POWER_4 4 + +/*! + * Region | dBM + * ------------ | :-----: + * AS923 | Max EIRP - 10 + * AU915 | Max EIRP - 10 + * CN470 | Max EIRP - 10 + * CN779 | Max EIRP - 10 + * EU433 | Max EIRP - 10 + * EU868 | Max EIRP - 10 + * IN865 | Max EIRP - 10 + * KR920 | Max EIRP - 10 + * US915 | Max ERP - 10 + * US915_HYBRID | Max ERP - 10 + */ +#define TX_POWER_5 5 + +/*! + * Region | dBM + * ------------ | :-----: + * AS923 | Max EIRP - 12 + * AU915 | Max EIRP - 12 + * CN470 | Max EIRP - 12 + * CN779 | - + * EU433 | - + * EU868 | Max EIRP - 12 + * IN865 | Max EIRP - 12 + * KR920 | Max EIRP - 12 + * US915 | Max ERP - 12 + * US915_HYBRID | Max ERP - 12 + */ +#define TX_POWER_6 6 + +/*! + * Region | dBM + * ------------ | :-----: + * AS923 | Max EIRP - 14 + * AU915 | Max EIRP - 14 + * CN470 | Max EIRP - 14 + * CN779 | - + * EU433 | - + * EU868 | Max EIRP - 14 + * IN865 | Max EIRP - 14 + * KR920 | Max EIRP - 14 + * US915 | Max ERP - 14 + * US915_HYBRID | Max ERP - 14 + */ +#define TX_POWER_7 7 + +/*! + * Region | dBM + * ------------ | :-----: + * AS923 | - + * AU915 | Max EIRP - 16 + * CN470 | - + * CN779 | - + * EU433 | - + * EU868 | - + * IN865 | Max EIRP - 16 + * KR920 | - + * US915 | Max ERP - 16 + * US915_HYBRID | Max ERP -16 + */ +#define TX_POWER_8 8 + +/*! + * Region | dBM + * ------------ | :-----: + * AS923 | - + * AU915 | Max EIRP - 18 + * CN470 | - + * CN779 | - + * EU433 | - + * EU868 | - + * IN865 | Max EIRP - 18 + * KR920 | - + * US915 | Max ERP - 16 + * US915_HYBRID | Max ERP - 16 + */ +#define TX_POWER_9 9 + +/*! + * Region | dBM + * ------------ | :-----: + * AS923 | - + * AU915 | Max EIRP - 20 + * CN470 | - + * CN779 | - + * EU433 | - + * EU868 | - + * IN865 | Max EIRP - 20 + * KR920 | - + * US915 | Max ERP - 10 + * US915_HYBRID | Max ERP - 10 + */ +#define TX_POWER_10 10 + +/*! + * RFU + */ +#define TX_POWER_11 11 + +/*! + * RFU + */ +#define TX_POWER_12 12 + +/*! + * RFU + */ +#define TX_POWER_13 13 + +/*! + * RFU + */ +#define TX_POWER_14 14 + +/*! + * RFU + */ +#define TX_POWER_15 15 + + + +/*! + * Enumeration of phy attributes. + */ +typedef enum ePhyAttribute { + /*! + * Minimum RX datarate. + */ + PHY_MIN_RX_DR, + /*! + * Minimum TX datarate. + */ + PHY_MIN_TX_DR, + /*! + * Maximum RX datarate. + */ + PHY_MAX_RX_DR, + /*! + * Maximum TX datarate. + */ + PHY_MAX_TX_DR, + /*! + * TX datarate. + */ + PHY_TX_DR, + /*! + * Default TX datarate. + */ + PHY_DEF_TX_DR, + /*! + * RX datarate. + */ + PHY_RX_DR, + /*! + * TX power. + */ + PHY_TX_POWER, + /*! + * Default TX power. + */ + PHY_DEF_TX_POWER, + /*! + * Maximum payload possible. + */ + PHY_MAX_PAYLOAD, + /*! + * Maximum payload possible when repeater support is enabled. + */ + PHY_MAX_PAYLOAD_REPEATER, + /*! + * Duty cycle. + */ + PHY_DUTY_CYCLE, + /*! + * Maximum receive window duration. + */ + PHY_MAX_RX_WINDOW, + /*! + * Receive delay for window 1. + */ + PHY_RECEIVE_DELAY1, + /*! + * Receive delay for window 2. + */ + PHY_RECEIVE_DELAY2, + /*! + * Join accept delay for window 1. + */ + PHY_JOIN_ACCEPT_DELAY1, + /*! + * Join accept delay for window 2. + */ + PHY_JOIN_ACCEPT_DELAY2, + /*! + * Maximum frame counter gap. + */ + PHY_MAX_FCNT_GAP, + /*! + * Acknowledgement time out. + */ + PHY_ACK_TIMEOUT, + /*! + * Default datarate offset for window 1. + */ + PHY_DEF_DR1_OFFSET, + /*! + * Default receive window 2 frequency. + */ + PHY_DEF_RX2_FREQUENCY, + /*! + * Default receive window 2 datarate. + */ + PHY_DEF_RX2_DR, + /*! + * Channels mask. + */ + PHY_CHANNELS_MASK, + /*! + * Channels default mask. + */ + PHY_CHANNELS_DEFAULT_MASK, + /*! + * Maximum number of supported channels + */ + PHY_MAX_NB_CHANNELS, + /*! + * Channels. + */ + PHY_CHANNELS, + /*! + * Default value of the uplink dwell time. + */ + PHY_DEF_UPLINK_DWELL_TIME, + /*! + * Default value of the downlink dwell time. + */ + PHY_DEF_DOWNLINK_DWELL_TIME, + /*! + * Default value of the MaxEIRP. + */ + PHY_DEF_MAX_EIRP, + /*! + * Default value of the antenna gain. + */ + PHY_DEF_ANTENNA_GAIN, + /*! + * Next lower datarate. + */ + PHY_NEXT_LOWER_TX_DR, + /*! + * Beacon interval in ms. + */ + PHY_BEACON_INTERVAL, + /*! + * Beacon reserved time in ms. + */ + PHY_BEACON_RESERVED, + /*! + * Beacon guard time in ms. + */ + PHY_BEACON_GUARD, + /*! + * Beacon window time in ms. + */ + PHY_BEACON_WINDOW, + /*! + * Beacon window time in numer of slots. + */ + PHY_BEACON_WINDOW_SLOTS, + /*! + * Ping slot length time in ms. + */ + PHY_PING_SLOT_WINDOW, + /*! + * Default symbol timeout for beacons and ping slot windows. + */ + PHY_BEACON_SYMBOL_TO_DEFAULT, + /*! + * Maximum symbol timeout for beacons. + */ + PHY_BEACON_SYMBOL_TO_EXPANSION_MAX, + /*! + * Maximum symbol timeout for ping slots. + */ + PHY_PING_SLOT_SYMBOL_TO_EXPANSION_MAX, + /*! + * Symbol expansion value for beacon windows in case of beacon + * loss in symbols. + */ + PHY_BEACON_SYMBOL_TO_EXPANSION_FACTOR, + /*! + * Symbol expansion value for ping slot windows in case of beacon + * loss in symbols. + */ + PHY_PING_SLOT_SYMBOL_TO_EXPANSION_FACTOR, + /*! + * Maximum allowed beacon less time in ms. + */ + PHY_MAX_BEACON_LESS_PERIOD, + /*! + * Delay time for the BeaconTimingAns in ms. + */ + PHY_BEACON_DELAY_BEACON_TIMING_ANS, + /*! + * Beacon channel frequency. + */ + PHY_BEACON_CHANNEL_FREQ, + /*! + * The format of the beacon. + */ + PHY_BEACON_FORMAT, + /*! + * The beacon channel datarate. + */ + PHY_BEACON_CHANNEL_DR, + /*! + * The frequency stepwidth between the beacon channels. + */ + PHY_BEACON_CHANNEL_STEPWIDTH, + /*! + * The number of channels for the beacon reception. + */ + PHY_BEACON_NB_CHANNELS, + /*! + * Value for the number of join trials. + */ + PHY_NB_JOIN_TRIALS, + /*! + * Default value for the number of join trials. + */ + PHY_DEF_NB_JOIN_TRIALS +} PhyAttribute_t; + +/*! + * Enumeration of initialization types. + */ +typedef enum eInitType { + /*! + * Performs an initialization and overwrites all existing data. + */ + INIT_TYPE_INIT, + /*! + * Restores default channels only. + */ + INIT_TYPE_RESTORE, + /*! + * Initializes the region specific data to the defaults which were set by + * the application. + */ + INIT_TYPE_APP_DEFAULTS +} InitType_t; + +typedef enum eChannelsMask { + /*! + * The channels mask. + */ + CHANNELS_MASK, + /*! + * The channels default mask. + */ + CHANNELS_DEFAULT_MASK +} ChannelsMask_t; + +/*! + * Structure containing the beacon format + */ +typedef struct sBeaconFormat +{ + /*! + * Size of the beacon + */ + uint8_t BeaconSize; + /*! + * Size of the RFU 1 data field + */ + uint8_t Rfu1Size; + /*! + * Size of the RFU 2 data field + */ + uint8_t Rfu2Size; +}BeaconFormat_t; + +/*! + * Union for the structure uGetPhyParams + */ +typedef union uPhyParam { + /*! + * A parameter value. + */ + uint32_t Value; + /*! + * A floating point value. + */ + float fValue; + /*! + * Pointer to the channels mask. + */ + uint16_t *ChannelsMask; + /*! + * Pointer to the channels. + */ + ChannelParams_t *Channels; + /*! + * Beacon format + */ + BeaconFormat_t BeaconFormat; +} PhyParam_t; + +/*! + * Parameter structure for the function RegionGetPhyParam. + */ +typedef struct sGetPhyParams { + /*! + * Setup the parameter to get. + */ + PhyAttribute_t Attribute; + /*! + * Datarate. + * The parameter is needed for the following queries: + * PHY_MAX_PAYLOAD, PHY_MAX_PAYLOAD_REPEATER, PHY_NEXT_LOWER_TX_DR. + */ + int8_t Datarate; + /*! + * Uplink dwell time. + * The parameter is needed for the following queries: + * PHY_MIN_TX_DR, PHY_MAX_PAYLOAD, PHY_MAX_PAYLOAD_REPEATER, PHY_NEXT_LOWER_TX_DR. + */ + uint8_t UplinkDwellTime; + /*! + * Downlink dwell time. + * The parameter is needed for the following queries: + * PHY_MIN_RX_DR, PHY_MAX_PAYLOAD, PHY_MAX_PAYLOAD_REPEATER. + */ + uint8_t DownlinkDwellTime; +} GetPhyParams_t; + +/*! + * Parameter structure for the function RegionSetBandTxDone. + */ +typedef struct sSetBandTxDoneParams { + /*! + * Channel to update. + */ + uint8_t Channel; + /*! + * Joined Set to true, if the node has joined the network + */ + bool Joined; + /*! + * Last TX done time. + */ + TimerTime_t LastTxDoneTime; +} SetBandTxDoneParams_t; + +/*! + * Parameter structure for the function RegionVerify. + */ +typedef union uVerifyParams { + /*! + * TX power to verify. + */ + int8_t TxPower; + /*! + * Set to true, if the duty cycle is enabled, otherwise false. + */ + bool DutyCycle; + /*! + * The number of join trials. + */ + uint8_t NbJoinTrials; + /*! + * Datarate to verify. + */ + struct sDatarateParams { + /*! + * Datarate to verify. + */ + int8_t Datarate; + /*! + * The downlink dwell time. + */ + uint8_t DownlinkDwellTime; + /*! + * The up link dwell time. + */ + uint8_t UplinkDwellTime; + } DatarateParams; +} VerifyParams_t; + +/*! + * Parameter structure for the function RegionApplyCFList. + */ +typedef struct sApplyCFListParams { + /*! + * Payload which contains the CF list. + */ + uint8_t *Payload; + /*! + * Size of the payload. + */ + uint8_t Size; +} ApplyCFListParams_t; + +/*! + * Parameter structure for the function RegionChanMaskSet. + */ +typedef struct sChanMaskSetParams { + /*! + * Pointer to the channels mask which should be set. + */ + uint16_t *ChannelsMaskIn; + /*! + * Pointer to the channels mask which should be set. + */ + ChannelsMask_t ChannelsMaskType; +} ChanMaskSetParams_t; + +/*! + * Parameter structure for the function RegionAdrNext. + */ +typedef struct sAdrNextParams { + /*! + * Set to true, if the function should update the channels mask. + */ + bool UpdateChanMask; + /*! + * Set to true, if ADR is enabled. + */ + bool AdrEnabled; + /*! + * ADR ack counter. + */ + uint32_t AdrAckCounter; + /*! + * Datarate used currently. + */ + int8_t Datarate; + /*! + * TX power used currently. + */ + int8_t TxPower; + /*! + * UplinkDwellTime + */ + uint8_t UplinkDwellTime; +} AdrNextParams_t; + +/*! + * Parameter structure for the function RegionRxConfig. + */ +typedef struct sRxConfigParams { + /*! + * The RX channel. + */ + uint8_t Channel; + /*! + * RX datarate. + */ + int8_t Datarate; + /*! + * RX bandwidth. + */ + uint8_t Bandwidth; + /*! + * RX datarate offset. + */ + int8_t DrOffset; + /*! + * RX frequency. + */ + uint32_t Frequency; + /*! + * RX window timeout + */ + uint32_t WindowTimeout; + /*! + * RX window offset + */ + int32_t WindowOffset; + /*! + * Downlink dwell time. + */ + uint8_t DownlinkDwellTime; + /*! + * Set to true, if a repeater is supported. + */ + bool RepeaterSupport; + /*! + * Set to true, if RX should be continuous. + */ + bool RxContinuous; + /*! + * Sets the RX window. + */ + LoRaMacRxSlot_t RxSlot; +#ifdef CONFIG_LINKWAN + /*! + * Node current Work Mode + */ + uint8_t NodeWorkMode; + /*! + * Repeater RX and Tx frequency + */ + uint32_t RepeaterFrequency; +#endif +} RxConfigParams_t; + +/*! + * Parameter structure for the function RegionTxConfig. + */ +typedef struct sTxConfigParams { + /*! + * The TX channel. + */ + uint8_t Channel; + /*! + * The TX datarate. + */ + int8_t Datarate; + /*! + * The TX power. + */ + int8_t TxPower; + /*! + * The Max EIRP, if applicable. + */ + float MaxEirp; + /*! + * The antenna gain, if applicable. + */ + float AntennaGain; + /*! + * Frame length to setup. + */ + uint16_t PktLen; +#ifdef CONFIG_LINKWAN + /*! + * Node current Work Mode + */ + uint8_t NodeWorkMode; + /*! + * Repeater RX and Tx frequency + */ + uint32_t RepeaterFrequency; +#endif +} TxConfigParams_t; + +/*! + * Parameter structure for the function RegionLinkAdrReq. + */ +typedef struct sLinkAdrReqParams { + /*! + * Pointer to the payload which contains the MAC commands. + */ + uint8_t *Payload; + /*! + * Size of the payload. + */ + uint8_t PayloadSize; + /*! + * Uplink dwell time. + */ + uint8_t UplinkDwellTime; + /*! + * Set to true, if ADR is enabled. + */ + bool AdrEnabled; + /*! + * The current datarate. + */ + int8_t CurrentDatarate; + /*! + * The current TX power. + */ + int8_t CurrentTxPower; + /*! + * The current number of repetitions. + */ + uint8_t CurrentNbRep; +} LinkAdrReqParams_t; + +/*! + * Parameter structure for the function RegionRxParamSetupReq. + */ +typedef struct sRxParamSetupReqParams { + /*! + * The datarate to setup. + */ + int8_t Datarate; + /*! + * Datarate offset. + */ + int8_t DrOffset; + /*! + * The frequency to setup. + */ + uint32_t Frequency; +} RxParamSetupReqParams_t; + +/*! + * Parameter structure for the function RegionNewChannelReq. + */ +typedef struct sNewChannelReqParams { + /*! + * Pointer to the new channels. + */ + ChannelParams_t *NewChannel; + /*! + * Channel id. + */ + int8_t ChannelId; +} NewChannelReqParams_t; + +/*! + * Parameter structure for the function RegionTxParamSetupReq. + */ +typedef struct sTxParamSetupReqParams { + /*! + * Uplink dwell time. + */ + uint8_t UplinkDwellTime; + /*! + * Downlink dwell time. + */ + uint8_t DownlinkDwellTime; + /*! + * Max EIRP. + */ + uint8_t MaxEirp; +} TxParamSetupReqParams_t; + +/*! + * Parameter structure for the function RegionDlChannelReq. + */ +typedef struct sDlChannelReqParams { + /*! + * Channel Id to add the frequency. + */ + uint8_t ChannelId; + /*! + * Alternative frequency for the Rx1 window. + */ + uint32_t Rx1Frequency; +} DlChannelReqParams_t; + +/*! + * Parameter structure for the function RegionAlternateDr. + */ +typedef struct sAlternateDrParams { + /*! + * Number of trials. + */ + uint16_t NbTrials; +#ifdef CONFIG_LINKWAN + int8_t datarate; + uint8_t joinmethod; +#endif +} AlternateDrParams_t; + +/*! + * Parameter structure for the function RegionCalcBackOff. + */ +typedef struct sCalcBackOffParams { + /*! + * Set to true, if the node has already joined a network, otherwise false. + */ + bool Joined; + /*! + * Joined Set to true, if the last uplink was a join request + */ + bool LastTxIsJoinRequest; + /*! + * Set to true, if the duty cycle is enabled, otherwise false. + */ + bool DutyCycleEnabled; + /*! + * Current channel index. + */ + uint8_t Channel; + /*! + * Elapsed time since the start of the node. + */ + TimerTime_t ElapsedTime; + /*! + * Time-on-air of the last transmission. + */ + TimerTime_t TxTimeOnAir; +} CalcBackOffParams_t; + +/*! + * Parameter structure for the function RegionNextChannel. + */ +typedef struct sNextChanParams { + /*! + * Aggregated time-off time. + */ + TimerTime_t AggrTimeOff; + /*! + * Time of the last aggregated TX. + */ + TimerTime_t LastAggrTx; + /*! + * Current datarate. + */ + int8_t Datarate; + /*! + * Set to true, if the node has already joined a network, otherwise false. + */ + bool Joined; + /*! + * Set to true, if the duty cycle is enabled, otherwise false. + */ + bool DutyCycleEnabled; + +#ifdef CONFIG_LINKWAN + uint8_t NextAvailableTxFreqBandNum; + uint8_t NextAvailableRxFreqBandNum; + uint8_t joinmethod; + uint32_t freqband; + bool update_freqband; +#endif +} NextChanParams_t; + +/*! + * Parameter structure for the function RegionChannelsAdd. + */ +typedef struct sChannelAddParams { + /*! + * Pointer to the new channel to add. + */ + ChannelParams_t *NewChannel; + /*! + * Channel id to add. + */ + uint8_t ChannelId; +} ChannelAddParams_t; + +/*! + * Parameter structure for the function RegionChannelsRemove. + */ +typedef struct sChannelRemoveParams { + /*! + * Channel id to remove. + */ + uint8_t ChannelId; +} ChannelRemoveParams_t; + +/*! + * Parameter structure for the function RegionContinuousWave. + */ +typedef struct sContinuousWaveParams { + /*! + * Current channel index. + */ + uint8_t Channel; + /*! + * Datarate. Used to limit the TX power. + */ + int8_t Datarate; + /*! + * The TX power to setup. + */ + int8_t TxPower; + /*! + * Max EIRP, if applicable. + */ + float MaxEirp; + /*! + * The antenna gain, if applicable. + */ + float AntennaGain; + /*! + * Specifies the time the radio will stay in CW mode. + */ + uint16_t Timeout; +} ContinuousWaveParams_t; + +/*! + * Parameter structure for the function RegionRxBeaconSetup + */ +typedef struct sRxBeaconSetupParams +{ + /*! + * Symbol timeout. + */ + uint16_t SymbolTimeout; + /*! + * Receive time. + */ + uint32_t RxTime; + /*! + * The frequency to setup. + */ + uint32_t Frequency; +}RxBeaconSetup_t; + + + +/*! + * \brief The function verifies if a region is active or not. If a region + * is not active, it cannot be used. + * + * \param [IN] region LoRaWAN region. + * + * \retval Return true, if the region is supported. + */ +bool RegionIsActive( LoRaMacRegion_t region ); + +/*! + * \brief The function gets a value of a specific phy attribute. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] getPhy Pointer to the function parameters. + * + * \retval Returns a structure containing the PHY parameter. + */ +PhyParam_t RegionGetPhyParam( LoRaMacRegion_t region, GetPhyParams_t *getPhy ); + +/*! + * \brief Updates the last TX done parameters of the current channel. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] txDone Pointer to the function parameters. + */ +void RegionSetBandTxDone( LoRaMacRegion_t region, SetBandTxDoneParams_t *txDone ); + +/*! + * \brief Initializes the channels masks and the channels. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] type Sets the initialization type. + */ +void RegionInitDefaults( LoRaMacRegion_t region, InitType_t type ); + +/*! + * \brief Verifies a parameter. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] verify Pointer to the function parameters. + * + * \param [IN] type Sets the initialization type. + * + * \retval Returns true, if the parameter is valid. + */ +bool RegionVerify( LoRaMacRegion_t region, VerifyParams_t *verify, PhyAttribute_t phyAttribute ); + +/*! + * \brief The function parses the input buffer and sets up the channels of the + * CF list. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] applyCFList Pointer to the function parameters. + */ +void RegionApplyCFList( LoRaMacRegion_t region, ApplyCFListParams_t *applyCFList ); + +/*! + * \brief Sets a channels mask. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] chanMaskSet Pointer to the function parameters. + * + * \retval Returns true, if the channels mask could be set. + */ +bool RegionChanMaskSet( LoRaMacRegion_t region, ChanMaskSetParams_t *chanMaskSet ); + +/*! + * \brief Calculates the next datarate to set, when ADR is on or off. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] adrNext Pointer to the function parameters. + * + * \param [OUT] drOut The calculated datarate for the next TX. + * + * \param [OUT] txPowOut The TX power for the next TX. + * + * \param [OUT] adrAckCounter The calculated ADR acknowledgement counter. + * + * \retval Returns true, if an ADR request should be performed. + */ +bool RegionAdrNext( LoRaMacRegion_t region, AdrNextParams_t *adrNext, int8_t *drOut, int8_t *txPowOut, + uint32_t *adrAckCounter ); + +/*! + * \brief Configuration of the RX windows. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] rxConfig Pointer to the function parameters. + * + * \param [OUT] datarate The datarate index which was set. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionRxConfig( LoRaMacRegion_t region, RxConfigParams_t *rxConfig, int8_t *datarate ); + +/* + * Rx window precise timing + * + * For more details please consult the following document, chapter 3.1.2. + * http://www.semtech.com/images/datasheet/SX1272_settings_for_LoRaWAN_v2.0.pdf + * or + * http://www.semtech.com/images/datasheet/SX1276_settings_for_LoRaWAN_v2.0.pdf + * + * Downlink start: T = Tx + 1s (+/- 20 us) + * | + * TRxEarly | TRxLate + * | | | + * | | +---+---+---+---+---+---+---+---+ + * | | | Latest Rx window | + * | | +---+---+---+---+---+---+---+---+ + * | | | + * +---+---+---+---+---+---+---+---+ + * | Earliest Rx window | + * +---+---+---+---+---+---+---+---+ + * | + * +---+---+---+---+---+---+---+---+ + *Downlink preamble 8 symbols | | | | | | | | | + * +---+---+---+---+---+---+---+---+ + * + * Worst case Rx window timings + * + * TRxLate = DEFAULT_MIN_RX_SYMBOLS * tSymbol - RADIO_WAKEUP_TIME + * TRxEarly = 8 - DEFAULT_MIN_RX_SYMBOLS * tSymbol - RxWindowTimeout - RADIO_WAKEUP_TIME + * + * TRxLate - TRxEarly = 2 * DEFAULT_SYSTEM_MAX_RX_ERROR + * + * RxOffset = ( TRxLate + TRxEarly ) / 2 + * + * RxWindowTimeout = ( 2 * DEFAULT_MIN_RX_SYMBOLS - 8 ) * tSymbol + 2 * DEFAULT_SYSTEM_MAX_RX_ERROR + * RxOffset = 4 * tSymbol - RxWindowTimeout / 2 - RADIO_WAKE_UP_TIME + * + * Minimal value of RxWindowTimeout must be 5 symbols which implies that the system always tolerates at least an error of 1.5 * tSymbol + */ +/*! + * Computes the Rx window timeout and offset. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] datarate Rx window datarate index to be used + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms + * interval around RxOffset + * + * \param [OUT]rxConfigParams Returns updated WindowTimeout and WindowOffset fields. + */ +void RegionComputeRxWindowParameters( LoRaMacRegion_t region, int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, + RxConfigParams_t *rxConfigParams ); + +/*! + * \brief TX configuration. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] txConfig Pointer to the function parameters. + * + * \param [OUT] txPower The tx power index which was set. + * + * \param [OUT] txTimeOnAir The time-on-air of the frame. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionTxConfig( LoRaMacRegion_t region, TxConfigParams_t *txConfig, int8_t *txPower, TimerTime_t *txTimeOnAir ); + +/*! + * \brief The function processes a Link ADR Request. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] linkAdrReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionLinkAdrReq( LoRaMacRegion_t region, LinkAdrReqParams_t *linkAdrReq, int8_t *drOut, int8_t *txPowOut, + uint8_t *nbRepOut, uint8_t *nbBytesParsed ); + +/*! + * \brief The function processes a RX Parameter Setup Request. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] rxParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionRxParamSetupReq( LoRaMacRegion_t region, RxParamSetupReqParams_t *rxParamSetupReq ); + +/*! + * \brief The function processes a New Channel Request. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] newChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionNewChannelReq( LoRaMacRegion_t region, NewChannelReqParams_t *newChannelReq ); + +/*! + * \brief The function processes a TX ParamSetup Request. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] txParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + * Returns -1, if the functionality is not implemented. In this case, the end node + * shall ignore the command. + */ +int8_t RegionTxParamSetupReq( LoRaMacRegion_t region, TxParamSetupReqParams_t *txParamSetupReq ); + +/*! + * \brief The function processes a DlChannel Request. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] dlChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionDlChannelReq( LoRaMacRegion_t region, DlChannelReqParams_t *dlChannelReq ); + +/*! + * \brief Alternates the datarate of the channel for the join request. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] alternateDr Pointer to the function parameters. + * + * \retval Datarate to apply. + */ +int8_t RegionAlternateDr( LoRaMacRegion_t region, AlternateDrParams_t *alternateDr ); + +/*! + * \brief Calculates the back-off time. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] calcBackOff Pointer to the function parameters. + */ +void RegionCalcBackOff( LoRaMacRegion_t region, CalcBackOffParams_t *calcBackOff ); + +/*! + * \brief Searches and set the next random available channel + * + * \param [IN] region LoRaWAN region. + * + * \param [OUT] channel Next channel to use for TX. + * + * \param [OUT] time Time to wait for the next transmission according to the duty + * cycle. + * + * \param [OUT] aggregatedTimeOff Updates the aggregated time off. + * + * \retval Function status [1: OK, 0: Unable to find a channel on the current datarate]. + */ +bool RegionNextChannel( LoRaMacRegion_t region, NextChanParams_t *nextChanParams, uint8_t *channel, TimerTime_t *time, + TimerTime_t *aggregatedTimeOff ); + +/*! + * \brief Adds a channel. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] channelAdd Pointer to the function parameters. + * + * \retval Status of the operation. + */ +LoRaMacStatus_t RegionChannelAdd( LoRaMacRegion_t region, ChannelAddParams_t *channelAdd ); + +/*! + * \brief Removes a channel. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] channelRemove Pointer to the function parameters. + * + * \retval Returns true, if the channel was removed successfully. + */ +bool RegionChannelsRemove( LoRaMacRegion_t region, ChannelRemoveParams_t *channelRemove ); + +/*! + * \brief Sets the radio into continuous wave mode. + * + * \param [IN] region LoRaWAN region. + * + * \param [IN] continuousWave Pointer to the function parameters. + */ +void RegionSetContinuousWave( LoRaMacRegion_t region, ContinuousWaveParams_t *continuousWave ); + +/*! + * \brief Computes new datarate according to the given offset + * + * \param [IN] downlinkDwellTime Downlink dwell time configuration. 0: No limit, 1: 400ms + * + * \param [IN] dr Current datarate + * + * \param [IN] drOffset Offset to be applied + * + * \retval newDr Computed datarate. + */ +uint8_t RegionApplyDrOffset( LoRaMacRegion_t region, uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ); + +/*! + * \brief Sets the radio into beacon reception mode + * + * \param [IN] rxBeaconSetup Pointer to the function parameters + * + * \param [out] outDr Datarate used to receive the beacon + */ +void RegionRxBeaconSetup( LoRaMacRegion_t region, RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ); + +/*! \} defgroup REGION */ + +#endif // __REGION_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAS923.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAS923.c new file mode 100644 index 00000000..5c62a9f5 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAS923.c @@ -0,0 +1,1149 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC region AS923 implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include +#include + +#include "radio.h" +//#include "timer.h" +#include "timeServer.h" +#include "LoRaMac.h" + +#include "utilities.h" + +#include "Region.h" +#include "RegionCommon.h" +#include "RegionAS923.h" +#include "debug.h" + +// Definitions +#define CHANNELS_MASK_SIZE 1 + +// Global attributes +/*! + * LoRaMAC channels + */ +static ChannelParams_t Channels[AS923_MAX_NB_CHANNELS]; + +/*! + * LoRaMac bands + */ +static Band_t Bands[AS923_MAX_NB_BANDS] = +{ + AS923_BAND0 +}; + +/*! + * LoRaMac channels mask + */ +static uint16_t ChannelsMask[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels default mask + */ +static uint16_t ChannelsDefaultMask[CHANNELS_MASK_SIZE]; + +// Static functions +static int8_t GetNextLowerTxDr( int8_t dr, int8_t minDr ) +{ + uint8_t nextLowerDr = 0; + + if( dr == minDr ) + { + nextLowerDr = minDr; + } + else + { + nextLowerDr = dr - 1; + } + return nextLowerDr; +} + +static uint32_t GetBandwidth( uint32_t drIndex ) +{ + switch( BandwidthsAS923[drIndex] ) + { + default: + case 125000: + return 0; + case 250000: + return 1; + case 500000: + return 2; + } +} + +static int8_t LimitTxPower( int8_t txPower, int8_t maxBandTxPower, int8_t datarate, uint16_t* channelsMask ) +{ + int8_t txPowerResult = txPower; + + // Limit tx power to the band max + txPowerResult = MAX( txPower, maxBandTxPower ); + + return txPowerResult; +} + +static bool VerifyTxFreq( uint32_t freq ) +{ + // Check radio driver support + if( Radio.CheckRfFrequency( freq ) == false ) + { + return false; + } + + if( ( freq < 915000000 ) || ( freq > 928000000 ) ) + { + return false; + } + return true; +} + +static uint8_t CountNbOfEnabledChannels( bool joined, uint8_t datarate, uint16_t* channelsMask, ChannelParams_t* channels, Band_t* bands, uint8_t* enabledChannels, uint8_t* delayTx ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTransmission = 0; + + for( uint8_t i = 0, k = 0; i < AS923_MAX_NB_CHANNELS; i += 16, k++ ) + { + for( uint8_t j = 0; j < 16; j++ ) + { + if( ( channelsMask[k] & ( 1 << j ) ) != 0 ) + { + if( channels[i + j].Frequency == 0 ) + { // Check if the channel is enabled + continue; + } + if( joined == false ) + { + if( ( AS923_JOIN_CHANNELS & ( 1 << j ) ) == 0 ) + { + continue; + } + } + if( RegionCommonValueInRange( datarate, channels[i + j].DrRange.Fields.Min, + channels[i + j].DrRange.Fields.Max ) == false ) + { // Check if the current channel selection supports the given datarate + continue; + } + if( bands[channels[i + j].Band].TimeOff > 0 ) + { // Check if the band is available for transmission + delayTransmission++; + continue; + } + enabledChannels[nbEnabledChannels++] = i + j; + } + } + } + + *delayTx = delayTransmission; + return nbEnabledChannels; +} + +PhyParam_t RegionAS923GetPhyParam( GetPhyParams_t* getPhy ) +{ + PhyParam_t phyParam = { 0 }; + + switch( getPhy->Attribute ) + { + case PHY_MIN_RX_DR: + { + if( getPhy->DownlinkDwellTime == 0 ) + { + phyParam.Value = AS923_RX_MIN_DATARATE; + } + else + { + phyParam.Value = AS923_DWELL_LIMIT_DATARATE; + } + break; + } + case PHY_MIN_TX_DR: + { + if( getPhy->UplinkDwellTime == 0 ) + { + phyParam.Value = AS923_TX_MIN_DATARATE; + } + else + { + phyParam.Value = AS923_DWELL_LIMIT_DATARATE; + } + break; + } + case PHY_DEF_TX_DR: + { + phyParam.Value = AS923_DEFAULT_DATARATE; + break; + } + case PHY_NEXT_LOWER_TX_DR: + { + if( getPhy->UplinkDwellTime == 0 ) + { + phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, AS923_TX_MIN_DATARATE ); + } + else + { + phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, AS923_DWELL_LIMIT_DATARATE ); + } + break; + } + case PHY_DEF_TX_POWER: + { + phyParam.Value = AS923_DEFAULT_TX_POWER; + break; + } + case PHY_MAX_PAYLOAD: + { + if( getPhy->UplinkDwellTime == 0 ) + { + phyParam.Value = MaxPayloadOfDatarateDwell0AS923[getPhy->Datarate]; + } + else + { + phyParam.Value = MaxPayloadOfDatarateDwell1UpAS923[getPhy->Datarate]; + } + break; + } + case PHY_MAX_PAYLOAD_REPEATER: + { + if( getPhy->UplinkDwellTime == 0 ) + { + phyParam.Value = MaxPayloadOfDatarateRepeaterDwell0AS923[getPhy->Datarate]; + } + else + { + phyParam.Value = MaxPayloadOfDatarateDwell1UpAS923[getPhy->Datarate]; + } + break; + } + case PHY_DUTY_CYCLE: + { + phyParam.Value = AS923_DUTY_CYCLE_ENABLED; + break; + } + case PHY_MAX_RX_WINDOW: + { + phyParam.Value = AS923_MAX_RX_WINDOW; + break; + } + case PHY_RECEIVE_DELAY1: + { + phyParam.Value = AS923_RECEIVE_DELAY1; + break; + } + case PHY_RECEIVE_DELAY2: + { + phyParam.Value = AS923_RECEIVE_DELAY2; + break; + } + case PHY_JOIN_ACCEPT_DELAY1: + { + phyParam.Value = AS923_JOIN_ACCEPT_DELAY1; + break; + } + case PHY_JOIN_ACCEPT_DELAY2: + { + phyParam.Value = AS923_JOIN_ACCEPT_DELAY2; + break; + } + case PHY_MAX_FCNT_GAP: + { + phyParam.Value = AS923_MAX_FCNT_GAP; + break; + } + case PHY_ACK_TIMEOUT: + { + phyParam.Value = ( AS923_ACKTIMEOUT + randr( -AS923_ACK_TIMEOUT_RND, AS923_ACK_TIMEOUT_RND ) ); + break; + } + case PHY_DEF_DR1_OFFSET: + { + phyParam.Value = AS923_DEFAULT_RX1_DR_OFFSET; + break; + } + case PHY_DEF_RX2_FREQUENCY: + { + phyParam.Value = AS923_RX_WND_2_FREQ; + break; + } + case PHY_DEF_RX2_DR: + { + phyParam.Value = AS923_RX_WND_2_DR; + break; + } + case PHY_CHANNELS_MASK: + { + phyParam.ChannelsMask = ChannelsMask; + break; + } + case PHY_CHANNELS_DEFAULT_MASK: + { + phyParam.ChannelsMask = ChannelsDefaultMask; + break; + } + case PHY_MAX_NB_CHANNELS: + { + phyParam.Value = AS923_MAX_NB_CHANNELS; + break; + } + case PHY_CHANNELS: + { + phyParam.Channels = Channels; + break; + } + case PHY_DEF_UPLINK_DWELL_TIME: + { + phyParam.Value = AS923_DEFAULT_UPLINK_DWELL_TIME; + break; + } + case PHY_DEF_DOWNLINK_DWELL_TIME: + { + phyParam.Value = AS923_DEFAULT_DOWNLINK_DWELL_TIME; + break; + } + case PHY_DEF_MAX_EIRP: + { + phyParam.fValue = AS923_DEFAULT_MAX_EIRP; + break; + } + case PHY_DEF_ANTENNA_GAIN: + { + phyParam.fValue = AS923_DEFAULT_ANTENNA_GAIN; + break; + } + case PHY_NB_JOIN_TRIALS: + case PHY_DEF_NB_JOIN_TRIALS: + { + phyParam.Value = 1; + break; + } + case PHY_BEACON_CHANNEL_FREQ: + { + phyParam.Value = AS923_BEACON_CHANNEL_FREQ; + break; + } + case PHY_BEACON_FORMAT: + { + phyParam.BeaconFormat.BeaconSize = AS923_BEACON_SIZE; + phyParam.BeaconFormat.Rfu1Size = AS923_RFU1_SIZE; + phyParam.BeaconFormat.Rfu2Size = AS923_RFU2_SIZE; + break; + } + case PHY_BEACON_CHANNEL_DR: + { + phyParam.Value = AS923_BEACON_CHANNEL_DR; + break; + } + default: + { + break; + } + } + + return phyParam; +} + +void RegionAS923SetBandTxDone( SetBandTxDoneParams_t* txDone ) +{ + RegionCommonSetBandTxDone( txDone->Joined, &Bands[Channels[txDone->Channel].Band], txDone->LastTxDoneTime ); +} + +void RegionAS923InitDefaults( InitType_t type ) +{ + switch( type ) + { + case INIT_TYPE_INIT: + { + // Channels + Channels[0] = ( ChannelParams_t ) AS923_LC1; + Channels[1] = ( ChannelParams_t ) AS923_LC2; + + // Initialize the channels default mask + ChannelsDefaultMask[0] = LC( 1 ) + LC( 2 ); + // Update the channels mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 1 ); + break; + } + case INIT_TYPE_RESTORE: + { + // Restore channels default mask + ChannelsMask[0] |= ChannelsDefaultMask[0]; + break; + } + default: + { + break; + } + } +} + +bool RegionAS923Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ) +{ + switch( phyAttribute ) + { + case PHY_TX_DR: + { + if( verify->DatarateParams.UplinkDwellTime == 0 ) + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, AS923_TX_MIN_DATARATE, AS923_TX_MAX_DATARATE ); + } + else + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, AS923_DWELL_LIMIT_DATARATE, AS923_TX_MAX_DATARATE ); + } + } + case PHY_DEF_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, DR_0, DR_5 ); + } + case PHY_RX_DR: + { + if( verify->DatarateParams.DownlinkDwellTime == 0 ) + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, AS923_RX_MIN_DATARATE, AS923_RX_MAX_DATARATE ); + } + else + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, AS923_DWELL_LIMIT_DATARATE, AS923_RX_MAX_DATARATE ); + } + } + case PHY_DEF_TX_POWER: + case PHY_TX_POWER: + { + // Remark: switched min and max! + return RegionCommonValueInRange( verify->TxPower, AS923_MAX_TX_POWER, AS923_MIN_TX_POWER ); + } + case PHY_DUTY_CYCLE: + { + return AS923_DUTY_CYCLE_ENABLED; + } + case PHY_NB_JOIN_TRIALS: + { + return true; + } + default: + return false; + } +} + +void RegionAS923ApplyCFList( ApplyCFListParams_t* applyCFList ) +{ + ChannelParams_t newChannel; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + // Setup default datarate range + newChannel.DrRange.Value = ( DR_5 << 4 ) | DR_0; + + // Size of the optional CF list + if( applyCFList->Size != 16 ) + { + return; + } + + // Last byte is RFU, don't take it into account + for( uint8_t i = 0, chanIdx = AS923_NUMB_DEFAULT_CHANNELS; chanIdx < AS923_MAX_NB_CHANNELS; i+=3, chanIdx++ ) + { + if( chanIdx < ( AS923_NUMB_CHANNELS_CF_LIST + AS923_NUMB_DEFAULT_CHANNELS ) ) + { + // Channel frequency + newChannel.Frequency = (uint32_t) applyCFList->Payload[i]; + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 1] << 8 ); + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 2] << 16 ); + newChannel.Frequency *= 100; + + // Initialize alternative frequency to 0 + newChannel.Rx1Frequency = 0; + } + else + { + newChannel.Frequency = 0; + newChannel.DrRange.Value = 0; + newChannel.Rx1Frequency = 0; + } + + if( newChannel.Frequency != 0 ) + { + channelAdd.NewChannel = &newChannel; + channelAdd.ChannelId = chanIdx; + + // Try to add all channels + RegionAS923ChannelAdd( &channelAdd ); + } + else + { + channelRemove.ChannelId = chanIdx; + + RegionAS923ChannelsRemove( &channelRemove ); + } + } +} + +bool RegionAS923ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ) +{ + switch( chanMaskSet->ChannelsMaskType ) + { + case CHANNELS_MASK: + { + RegionCommonChanMaskCopy( ChannelsMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + case CHANNELS_DEFAULT_MASK: + { + RegionCommonChanMaskCopy( ChannelsDefaultMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + default: + return false; + } + return true; +} + +bool RegionAS923AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ) +{ + bool adrAckReq = false; + int8_t datarate = adrNext->Datarate; + int8_t minTxDatarate = 0; + int8_t txPower = adrNext->TxPower; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + // Get the minimum possible datarate + getPhy.Attribute = PHY_MIN_TX_DR; + getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + phyParam = RegionAS923GetPhyParam( &getPhy ); + minTxDatarate = phyParam.Value; + + // Report back the adr ack counter + *adrAckCounter = adrNext->AdrAckCounter; + + // Apply the minimum possible datarate. + datarate = MAX( datarate, minTxDatarate ); + + if( adrNext->AdrEnabled == true ) + { + if( datarate == minTxDatarate ) + { + *adrAckCounter = 0; + adrAckReq = false; + } + else + { + if( adrNext->AdrAckCounter >= AS923_ADR_ACK_LIMIT ) + { + adrAckReq = true; + txPower = AS923_MAX_TX_POWER; + } + else + { + adrAckReq = false; + } + if( adrNext->AdrAckCounter >= ( AS923_ADR_ACK_LIMIT + AS923_ADR_ACK_DELAY ) ) + { + if( ( adrNext->AdrAckCounter % AS923_ADR_ACK_DELAY ) == 1 ) + { + // Decrease the datarate + getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + getPhy.Datarate = datarate; + getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + phyParam = RegionAS923GetPhyParam( &getPhy ); + datarate = phyParam.Value; + + if( datarate == minTxDatarate ) + { + // We must set adrAckReq to false as soon as we reach the lowest datarate + adrAckReq = false; + if( adrNext->UpdateChanMask == true ) + { + // Re-enable default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ); + } + } + } + } + } + } + + *drOut = datarate; + *txPowOut = txPower; + return adrAckReq; +} + +void RegionAS923ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ) +{ + double tSymbol = 0.0; + uint32_t radioWakeUpTime; + + rxConfigParams->Datarate = datarate; + rxConfigParams->Bandwidth = GetBandwidth( datarate ); + + if( datarate == DR_7 ) + { // FSK + tSymbol = RegionCommonComputeSymbolTimeFsk( DataratesAS923[datarate] ); + } + else + { // LoRa + tSymbol = RegionCommonComputeSymbolTimeLoRa( DataratesAS923[datarate], BandwidthsAS923[datarate] ); + } + + radioWakeUpTime = Radio.GetWakeupTime( ); + RegionCommonComputeRxWindowParameters( tSymbol, minRxSymbols, rxError, radioWakeUpTime, &rxConfigParams->WindowTimeout, &rxConfigParams->WindowOffset ); +} + +bool RegionAS923RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ) +{ + RadioModems_t modem; + int8_t dr = rxConfig->Datarate; + uint8_t maxPayload = 0; + int8_t phyDr = 0; + uint32_t frequency = rxConfig->Frequency; + + if( Radio.GetStatus( ) != RF_IDLE ) + { + return false; + } + + if( rxConfig->RxSlot == RX_SLOT_WIN_1 ) + { + // Apply window 1 frequency + frequency = Channels[rxConfig->Channel].Frequency; + // Apply the alternative RX 1 window frequency, if it is available + if( Channels[rxConfig->Channel].Rx1Frequency != 0 ) + { + frequency = Channels[rxConfig->Channel].Rx1Frequency; + } + } + + // Read the physical datarate from the datarates table + phyDr = DataratesAS923[dr]; + + Radio.SetChannel( frequency ); + + // Radio configuration + if( dr == DR_7 ) + { + modem = MODEM_FSK; + Radio.SetRxConfig( modem, 50000, phyDr * 1000, 0, 83333, 5, rxConfig->WindowTimeout, false, 0, true, 0, 0, false, rxConfig->RxContinuous ); + } + else + { + modem = MODEM_LORA; + Radio.SetRxConfig( modem, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, false, 0, false, 0, 0, true, rxConfig->RxContinuous ); + } + + // Check for repeater support + if( rxConfig->RepeaterSupport == true ) + { + maxPayload = MaxPayloadOfDatarateRepeaterDwell0AS923[dr]; + } + else + { + maxPayload = MaxPayloadOfDatarateDwell0AS923[dr]; + } + + Radio.SetMaxPayloadLength( modem, maxPayload + LORA_MAC_FRMPAYLOAD_OVERHEAD ); + DBG_PRINTF("RX on freq %u Hz at DR %d\n\r", (unsigned int)frequency, dr); + + *datarate = (uint8_t) dr; + return true; +} + +bool RegionAS923TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) +{ + RadioModems_t modem; + int8_t phyDr = DataratesAS923[txConfig->Datarate]; + int8_t txPowerLimited = LimitTxPower( txConfig->TxPower, Bands[Channels[txConfig->Channel].Band].TxMaxPower, txConfig->Datarate, ChannelsMask ); + uint32_t bandwidth = GetBandwidth( txConfig->Datarate ); + int8_t phyTxPower = 0; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, txConfig->MaxEirp, txConfig->AntennaGain ); + + // Setup the radio frequency + Radio.SetChannel( Channels[txConfig->Channel].Frequency ); + + if( txConfig->Datarate == DR_7 ) + { // High Speed FSK channel + modem = MODEM_FSK; + Radio.SetTxConfig( modem, phyTxPower, 25000, bandwidth, phyDr * 1000, 0, 5, false, true, 0, 0, false, 3000 ); + } + else + { + modem = MODEM_LORA; + Radio.SetTxConfig( modem, phyTxPower, 0, bandwidth, phyDr, 1, 8, false, true, 0, 0, false, 3e3 ); + } + DBG_PRINTF("TX on freq %u Hz at DR %d\n\r", (unsigned int)Channels[txConfig->Channel].Frequency, txConfig->Datarate); + // Setup maximum payload lenght of the radio driver + Radio.SetMaxPayloadLength( modem, txConfig->PktLen ); + // Get the time-on-air of the next tx frame + *txTimeOnAir = Radio.TimeOnAir( modem, txConfig->PktLen ); + + *txPower = txPowerLimited; + return true; +} + +uint8_t RegionAS923LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ) +{ + uint8_t status = 0x07; + LinkAdrParams_t linkAdrParams; + uint8_t nextIndex = 0; + uint8_t bytesProcessed = 0; + uint16_t chMask = 0; + + while( bytesProcessed < linkAdrReq->PayloadSize ) + { + // Get ADR request parameters + nextIndex = RegionCommonParseLinkAdrReq( &( linkAdrReq->Payload[bytesProcessed] ), &linkAdrParams ); + + if( nextIndex == 0 ) + break; // break loop, since no more request has been found + + // Update bytes processed + bytesProcessed += nextIndex; + + // Revert status, as we only check the last ADR request for the channel mask KO + status = 0x07; + + // Setup temporary channels mask + chMask = linkAdrParams.ChMask; + + // Verify channels mask + if( ( linkAdrParams.ChMaskCtrl == 0 ) && ( chMask == 0 ) ) + { + status &= 0xFE; // Channel mask KO + } + else if( ( ( linkAdrParams.ChMaskCtrl >= 1 ) && ( linkAdrParams.ChMaskCtrl <= 5 )) || + ( linkAdrParams.ChMaskCtrl >= 7 ) ) + { + // RFU + status &= 0xFE; // Channel mask KO + } + else + { + for( uint8_t i = 0; i < AS923_MAX_NB_CHANNELS; i++ ) + { + if( linkAdrParams.ChMaskCtrl == 6 ) + { + if( Channels[i].Frequency != 0 ) + { + chMask |= 1 << i; + } + } + else + { + if( ( ( chMask & ( 1 << i ) ) != 0 ) && + ( Channels[i].Frequency == 0 ) ) + {// Trying to enable an undefined channel + status &= 0xFE; // Channel mask KO + } + } + } + } + } + + // Verify datarate + if( RegionCommonChanVerifyDr( AS923_MAX_NB_CHANNELS, &chMask, linkAdrParams.Datarate, AS923_TX_MIN_DATARATE, AS923_TX_MAX_DATARATE, Channels ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify tx power + if( RegionCommonValueInRange( linkAdrParams.TxPower, AS923_MAX_TX_POWER, AS923_MIN_TX_POWER ) == 0 ) + { + // Verify if the maximum TX power is exceeded + if( AS923_MAX_TX_POWER > linkAdrParams.TxPower ) + { // Apply maximum TX power. Accept TX power. + linkAdrParams.TxPower = AS923_MAX_TX_POWER; + } + else + { + status &= 0xFB; // TxPower KO + } + } + + // Update channelsMask if everything is correct + if( status == 0x07 ) + { + if( linkAdrParams.NbRep == 0 ) + { // Value of 0 is not allowed, revert to default. + linkAdrParams.NbRep = 1; + } + + // Set the channels mask to a default value + memset( ChannelsMask, 0, sizeof( ChannelsMask ) ); + // Update the channels mask + ChannelsMask[0] = chMask; + } + + // Update status variables + *drOut = linkAdrParams.Datarate; + *txPowOut = linkAdrParams.TxPower; + *nbRepOut = linkAdrParams.NbRep; + *nbBytesParsed = bytesProcessed; + + return status; +} + +uint8_t RegionAS923RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ) +{ + uint8_t status = 0x07; + + // Verify radio frequency + if( Radio.CheckRfFrequency( rxParamSetupReq->Frequency ) == false ) + { + status &= 0xFE; // Channel frequency KO + } + + // Verify datarate + if( RegionCommonValueInRange( rxParamSetupReq->Datarate, AS923_RX_MIN_DATARATE, AS923_RX_MAX_DATARATE ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify datarate offset + if( RegionCommonValueInRange( rxParamSetupReq->DrOffset, AS923_MIN_RX1_DR_OFFSET, AS923_MAX_RX1_DR_OFFSET ) == false ) + { + status &= 0xFB; // Rx1DrOffset range KO + } + + return status; +} + +uint8_t RegionAS923NewChannelReq( NewChannelReqParams_t* newChannelReq ) +{ + uint8_t status = 0x03; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + if( newChannelReq->NewChannel->Frequency == 0 ) + { + channelRemove.ChannelId = newChannelReq->ChannelId; + + // Remove + if( RegionAS923ChannelsRemove( &channelRemove ) == false ) + { + status &= 0xFC; + } + } + else + { + channelAdd.NewChannel = newChannelReq->NewChannel; + channelAdd.ChannelId = newChannelReq->ChannelId; + + switch( RegionAS923ChannelAdd( &channelAdd ) ) + { + case LORAMAC_STATUS_OK: + { + break; + } + case LORAMAC_STATUS_FREQUENCY_INVALID: + { + status &= 0xFE; + break; + } + case LORAMAC_STATUS_DATARATE_INVALID: + { + status &= 0xFD; + break; + } + case LORAMAC_STATUS_FREQ_AND_DR_INVALID: + { + status &= 0xFC; + break; + } + default: + { + status &= 0xFC; + break; + } + } + } + + return status; +} + +int8_t RegionAS923TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ) +{ + // Accept the request + return 0; +} + +uint8_t RegionAS923DlChannelReq( DlChannelReqParams_t* dlChannelReq ) +{ + uint8_t status = 0x03; + + // Verify if the frequency is supported + if( VerifyTxFreq( dlChannelReq->Rx1Frequency ) == false ) + { + status &= 0xFE; + } + + // Verify if an uplink frequency exists + if( Channels[dlChannelReq->ChannelId].Frequency == 0 ) + { + status &= 0xFD; + } + + // Apply Rx1 frequency, if the status is OK + if( status == 0x03 ) + { + Channels[dlChannelReq->ChannelId].Rx1Frequency = dlChannelReq->Rx1Frequency; + } + + return status; +} + +int8_t RegionAS923AlternateDr( AlternateDrParams_t* alternateDr ) +{ + // Only AS923_DWELL_LIMIT_DATARATE is supported + return AS923_DWELL_LIMIT_DATARATE; +} + +void RegionAS923CalcBackOff( CalcBackOffParams_t* calcBackOff ) +{ + uint8_t channel = calcBackOff->Channel; + uint16_t dutyCycle = Bands[Channels[channel].Band].DCycle; + uint16_t joinDutyCycle = 0; + + // Reset time-off to initial value. + Bands[Channels[channel].Band].TimeOff = 0; + + if( calcBackOff->Joined == false ) + { + // Get the join duty cycle + joinDutyCycle = RegionCommonGetJoinDc( calcBackOff->ElapsedTime ); + // Apply the most restricting duty cycle + dutyCycle = MAX( dutyCycle, joinDutyCycle ); + // Apply band time-off. + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + else + { + if( calcBackOff->DutyCycleEnabled == true ) + { + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + } +} + +bool RegionAS923NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ) +{ + uint8_t channelNext = 0; + uint8_t nbEnabledChannels = 0; + uint8_t delayTx = 0; + uint8_t enabledChannels[AS923_MAX_NB_CHANNELS] = { 0 }; + TimerTime_t nextTxDelay = 0; + + if( RegionCommonCountChannels( ChannelsMask, 0, 1 ) == 0 ) + { // Reactivate default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ); + } + + if( nextChanParams->AggrTimeOff <= TimerGetElapsedTime( nextChanParams->LastAggrTx ) ) + { + // Reset Aggregated time off + *aggregatedTimeOff = 0; + + // Update bands Time OFF + nextTxDelay = RegionCommonUpdateBandTimeOff( nextChanParams->Joined, nextChanParams->DutyCycleEnabled, Bands, AS923_MAX_NB_BANDS ); + + // Search how many channels are enabled + nbEnabledChannels = CountNbOfEnabledChannels( nextChanParams->Joined, nextChanParams->Datarate, + ChannelsMask, Channels, + Bands, enabledChannels, &delayTx ); + } + else + { + delayTx++; + nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx ); + } + + if( nbEnabledChannels > 0 ) + { + for( uint8_t i = 0, j = randr( 0, nbEnabledChannels - 1 ); i < AS923_MAX_NB_CHANNELS; i++ ) + { + channelNext = enabledChannels[j]; + j = ( j + 1 ) % nbEnabledChannels; + + // Perform carrier sense for AS923_CARRIER_SENSE_TIME + // If the channel is free, we can stop the LBT mechanism + if( Radio.IsChannelFree( MODEM_LORA, Channels[channelNext].Frequency, AS923_RSSI_FREE_TH, AS923_CARRIER_SENSE_TIME ) == true ) + { + // Free channel found + *channel = channelNext; + *time = 0; + return true; + } + } + return false; + } + else + { + if( delayTx > 0 ) + { + // Delay transmission due to AggregatedTimeOff or to a band time off + *time = nextTxDelay; + return true; + } + // Datarate not supported by any channel, restore defaults + ChannelsMask[0] |= LC( 1 ) + LC( 2 ); + *time = 0; + return false; + } +} + +LoRaMacStatus_t RegionAS923ChannelAdd( ChannelAddParams_t* channelAdd ) +{ + uint8_t band = 0; + bool drInvalid = false; + bool freqInvalid = false; + uint8_t id = channelAdd->ChannelId; + + if( id >= AS923_MAX_NB_CHANNELS ) + { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + + // Validate the datarate range + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Min, AS923_TX_MIN_DATARATE, AS923_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, AS923_TX_MIN_DATARATE, AS923_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( channelAdd->NewChannel->DrRange.Fields.Min > channelAdd->NewChannel->DrRange.Fields.Max ) + { + drInvalid = true; + } + + // Default channels don't accept all values + if( id < AS923_NUMB_DEFAULT_CHANNELS ) + { + // Validate the datarate range for min: must be DR_0 + if( channelAdd->NewChannel->DrRange.Fields.Min > DR_0 ) + { + drInvalid = true; + } + // Validate the datarate range for max: must be DR_5 <= Max <= TX_MAX_DATARATE + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, DR_5, AS923_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + // We are not allowed to change the frequency + if( channelAdd->NewChannel->Frequency != Channels[id].Frequency ) + { + freqInvalid = true; + } + } + + // Check frequency + if( freqInvalid == false ) + { + if( VerifyTxFreq( channelAdd->NewChannel->Frequency ) == false ) + { + freqInvalid = true; + } + } + + // Check status + if( ( drInvalid == true ) && ( freqInvalid == true ) ) + { + return LORAMAC_STATUS_FREQ_AND_DR_INVALID; + } + if( drInvalid == true ) + { + return LORAMAC_STATUS_DATARATE_INVALID; + } + if( freqInvalid == true ) + { + return LORAMAC_STATUS_FREQUENCY_INVALID; + } + + memcpy( &(Channels[id]), channelAdd->NewChannel, sizeof( Channels[id] ) ); + Channels[id].Band = band; + ChannelsMask[0] |= ( 1 << id ); + return LORAMAC_STATUS_OK; +} + +bool RegionAS923ChannelsRemove( ChannelRemoveParams_t* channelRemove ) +{ + uint8_t id = channelRemove->ChannelId; + + if( id < AS923_NUMB_DEFAULT_CHANNELS ) + { + return false; + } + + // Remove the channel from the list of channels + Channels[id] = ( ChannelParams_t ){ 0, 0, { 0 }, 0 }; + + return RegionCommonChanDisable( ChannelsMask, id, AS923_MAX_NB_CHANNELS ); +} + +void RegionAS923SetContinuousWave( ContinuousWaveParams_t* continuousWave ) +{ + int8_t txPowerLimited = LimitTxPower( continuousWave->TxPower, Bands[Channels[continuousWave->Channel].Band].TxMaxPower, continuousWave->Datarate, ChannelsMask ); + int8_t phyTxPower = 0; + uint32_t frequency = Channels[continuousWave->Channel].Frequency; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, continuousWave->MaxEirp, continuousWave->AntennaGain ); + + Radio.SetTxContinuousWave( frequency, phyTxPower, continuousWave->Timeout ); +} + +uint8_t RegionAS923ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +{ + // Initialize minDr for a downlink dwell time configuration of 0 + int8_t minDr = DR_0; + + // Update the minDR for a downlink dwell time configuration of 1 + if( downlinkDwellTime == 1 ) + { + minDr = AS923_DWELL_LIMIT_DATARATE; + } + + // Apply offset formula + return MIN( DR_5, MAX( minDr, dr - EffectiveRx1DrOffsetAS923[drOffset] ) ); +} + +void RegionAS923RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ) +{ + RegionCommonRxBeaconSetupParams_t regionCommonRxBeaconSetup; + + regionCommonRxBeaconSetup.Datarates = DataratesAS923; + regionCommonRxBeaconSetup.Frequency = rxBeaconSetup->Frequency; + regionCommonRxBeaconSetup.BeaconSize = AS923_BEACON_SIZE; + regionCommonRxBeaconSetup.BeaconDatarate = AS923_BEACON_CHANNEL_DR; + regionCommonRxBeaconSetup.BeaconChannelBW = AS923_BEACON_CHANNEL_BW; + regionCommonRxBeaconSetup.RxTime = rxBeaconSetup->RxTime; + regionCommonRxBeaconSetup.SymbolTimeout = rxBeaconSetup->SymbolTimeout; + + RegionCommonRxBeaconSetup( ®ionCommonRxBeaconSetup ); + + // Store downlink datarate + *outDr = AS923_BEACON_CHANNEL_DR; +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAS923.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAS923.h new file mode 100644 index 00000000..558b3ce2 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAS923.h @@ -0,0 +1,549 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file RegionAS923.h + * + * \brief Region definition for AS923 + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGIONAS923 Region AS923 + * Implementation according to LoRaWAN Specification v1.0.2. + * \{ + */ +#ifndef __REGION_AS923_H__ +#define __REGION_AS923_H__ + +#include "LoRaMac.h" + +/*! + * LoRaMac maximum number of channels + */ +#define AS923_MAX_NB_CHANNELS 16 + +/*! + * Number of default channels + */ +#define AS923_NUMB_DEFAULT_CHANNELS 2 + +/*! + * Number of channels to apply for the CF list + */ +#define AS923_NUMB_CHANNELS_CF_LIST 5 + +/*! + * Minimal datarate that can be used by the node + */ +#define AS923_TX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define AS923_TX_MAX_DATARATE DR_7 + +/*! + * Minimal datarate that can be used by the node + */ +#define AS923_RX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define AS923_RX_MAX_DATARATE DR_7 + +/*! + * Default datarate used by the node + */ +#define AS923_DEFAULT_DATARATE DR_2 + +/*! + * The minimum datarate which is used when the + * dwell time is limited. + */ +#define AS923_DWELL_LIMIT_DATARATE DR_2 + +/*! + * Minimal Rx1 receive datarate offset + */ +#define AS923_MIN_RX1_DR_OFFSET 0 + +/*! + * Maximal Rx1 receive datarate offset + */ +#define AS923_MAX_RX1_DR_OFFSET 7 + +/*! + * Default Rx1 receive datarate offset + */ +#define AS923_DEFAULT_RX1_DR_OFFSET 0 + +/*! + * Minimal Tx output power that can be used by the node + */ +#define AS923_MIN_TX_POWER TX_POWER_7 + +/*! + * Maximal Tx output power that can be used by the node + */ +#define AS923_MAX_TX_POWER TX_POWER_0 + +/*! + * Default Tx output power used by the node + */ +#define AS923_DEFAULT_TX_POWER TX_POWER_0 + +/*! + * Default uplink dwell time configuration + */ +#define AS923_DEFAULT_UPLINK_DWELL_TIME 1 + +/*! + * Default downlink dwell time configuration + */ +#define AS923_DEFAULT_DOWNLINK_DWELL_TIME 1 + +/*! + * Default Max EIRP + */ +#define AS923_DEFAULT_MAX_EIRP 16.0f + +/*! + * Default antenna gain + */ +#define AS923_DEFAULT_ANTENNA_GAIN 2.15f + +/*! + * ADR Ack limit + */ +#define AS923_ADR_ACK_LIMIT 64 + +/*! + * ADR Ack delay + */ +#define AS923_ADR_ACK_DELAY 32 + +/*! + * Enabled or disabled the duty cycle + */ +#define AS923_DUTY_CYCLE_ENABLED 0 + +/*! + * Maximum RX window duration + */ +#define AS923_MAX_RX_WINDOW 3000 + +/*! + * Receive delay 1 + */ +#define AS923_RECEIVE_DELAY1 1000 + +/*! + * Receive delay 2 + */ +#define AS923_RECEIVE_DELAY2 2000 + +/*! + * Join accept delay 1 + */ +#define AS923_JOIN_ACCEPT_DELAY1 5000 + +/*! + * Join accept delay 2 + */ +#define AS923_JOIN_ACCEPT_DELAY2 6000 + +/*! + * Maximum frame counter gap + */ +#define AS923_MAX_FCNT_GAP 16384 + +/*! + * Ack timeout + */ +#define AS923_ACKTIMEOUT 2000 + +/*! + * Random ack timeout limits + */ +#define AS923_ACK_TIMEOUT_RND 1000 + +#if ( AS923_DEFAULT_DATARATE > DR_5 ) +#error "A default DR higher than DR_5 may lead to connectivity loss." +#endif + +/*! + * Second reception window channel frequency definition. + */ +#define AS923_RX_WND_2_FREQ 923200000 + +/*! + * Second reception window channel datarate definition. + */ +#define AS923_RX_WND_2_DR DR_2 + +/* + * CLASS B + */ +/*! + * Beacon frequency + */ +#define AS923_BEACON_CHANNEL_FREQ 923400000 + +/*! + * Payload size of a beacon frame + */ +#define AS923_BEACON_SIZE 17 + +/*! + * Size of RFU 1 field + */ +#define AS923_RFU1_SIZE 2 + +/*! + * Size of RFU 2 field + */ +#define AS923_RFU2_SIZE 0 + +/*! + * Datarate of the beacon channel + */ +#define AS923_BEACON_CHANNEL_DR DR_3 + +/*! + * Bandwith of the beacon channel + */ +#define AS923_BEACON_CHANNEL_BW 0 + +/*! + * Maximum number of bands + */ +#define AS923_MAX_NB_BANDS 1 + +/*! + * Band 0 definition + * { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define AS923_BAND0 { 100, AS923_MAX_TX_POWER, 0, 0 } // 1.0 % + +/*! + * LoRaMac default channel 1 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define AS923_LC1 { 923200000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac default channel 2 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define AS923_LC2 { 923400000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac channels which are allowed for the join procedure + */ +#define AS923_JOIN_CHANNELS ( uint16_t )( LC( 1 ) | LC( 2 ) ) + +/*! + * RSSI threshold for a free channel [dBm] + */ +#define AS923_RSSI_FREE_TH -85 + +/*! + * Specifies the time the node performs a carrier sense + */ +#define AS923_CARRIER_SENSE_TIME 6 + +/*! + * Data rates table definition + */ +static const uint8_t DataratesAS923[] = { 12, 11, 10, 9, 8, 7, 7, 50 }; + +/*! + * Bandwidths table definition in Hz + */ +static const uint32_t BandwidthsAS923[] = { 125000, 125000, 125000, 125000, 125000, 125000, 250000, 0 }; + +/*! + * Maximum payload with respect to the datarate index. Cannot operate with repeater. + * The table is valid for the dwell time configuration of 0 for uplinks and downlinks. + */ +static const uint8_t MaxPayloadOfDatarateDwell0AS923[] = { 51, 51, 51, 115, 242, 242, 242, 242 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with repeater. + * The table is valid for the dwell time configuration of 0 for uplinks and downlinks. The table provides + * repeater support. + */ +static const uint8_t MaxPayloadOfDatarateRepeaterDwell0AS923[] = { 51, 51, 51, 115, 222, 222, 222, 222 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with and without repeater. + * The table proides repeater support. The table is only valid for uplinks. + */ +static const uint8_t MaxPayloadOfDatarateDwell1UpAS923[] = { 0, 0, 11, 53, 125, 242, 242, 242 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with and without repeater. + * The table proides repeater support. The table is only valid for downlinks. + */ +static const uint8_t MaxPayloadOfDatarateDwell1DownAS923[] = { 0, 0, 11, 53, 126, 242, 242, 242 }; + +/*! + * Effective datarate offsets for receive window 1. + */ +static const int8_t EffectiveRx1DrOffsetAS923[] = { 0, 1, 2, 3, 4, 5, -1, -2 }; + +/*! + * \brief The function gets a value of a specific phy attribute. + * + * \param [IN] getPhy Pointer to the function parameters. + * + * \retval Returns a structure containing the PHY parameter. + */ +PhyParam_t RegionAS923GetPhyParam( GetPhyParams_t* getPhy ); + +/*! + * \brief Updates the last TX done parameters of the current channel. + * + * \param [IN] txDone Pointer to the function parameters. + */ +void RegionAS923SetBandTxDone( SetBandTxDoneParams_t* txDone ); + +/*! + * \brief Initializes the channels masks and the channels. + * + * \param [IN] type Sets the initialization type. + */ +void RegionAS923InitDefaults( InitType_t type ); + +/*! + * \brief Verifies a parameter. + * + * \param [IN] verify Pointer to the function parameters. + * + * \param [IN] type Sets the initialization type. + * + * \retval Returns true, if the parameter is valid. + */ +bool RegionAS923Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ); + +/*! + * \brief The function parses the input buffer and sets up the channels of the + * CF list. + * + * \param [IN] applyCFList Pointer to the function parameters. + */ +void RegionAS923ApplyCFList( ApplyCFListParams_t* applyCFList ); + +/*! + * \brief Sets a channels mask. + * + * \param [IN] chanMaskSet Pointer to the function parameters. + * + * \retval Returns true, if the channels mask could be set. + */ +bool RegionAS923ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ); + +/*! + * \brief Calculates the next datarate to set, when ADR is on or off. + * + * \param [IN] adrNext Pointer to the function parameters. + * + * \param [OUT] drOut The calculated datarate for the next TX. + * + * \param [OUT] txPowOut The TX power for the next TX. + * + * \param [OUT] adrAckCounter The calculated ADR acknowledgement counter. + * + * \retval Returns true, if an ADR request should be performed. + */ +bool RegionAS923AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ); + +/*! + * Computes the Rx window timeout and offset. + * + * \param [IN] datarate Rx window datarate index to be used + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms + * interval around RxOffset + * + * \param [OUT]rxConfigParams Returns updated WindowTimeout and WindowOffset fields. + */ +void RegionAS923ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ); + +/*! + * \brief Configuration of the RX windows. + * + * \param [IN] rxConfig Pointer to the function parameters. + * + * \param [OUT] datarate The datarate index which was set. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionAS923RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ); + +/*! + * \brief TX configuration. + * + * \param [IN] txConfig Pointer to the function parameters. + * + * \param [OUT] txPower The tx power index which was set. + * + * \param [OUT] txTimeOnAir The time-on-air of the frame. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionAS923TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ); + +/*! + * \brief The function processes a Link ADR Request. + * + * \param [IN] linkAdrReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionAS923LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ); + +/*! + * \brief The function processes a RX Parameter Setup Request. + * + * \param [IN] rxParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionAS923RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ); + +/*! + * \brief The function processes a Channel Request. + * + * \param [IN] newChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionAS923NewChannelReq( NewChannelReqParams_t* newChannelReq ); + +/*! + * \brief The function processes a TX ParamSetup Request. + * + * \param [IN] txParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + * Returns -1, if the functionality is not implemented. In this case, the end node + * shall not process the command. + */ +int8_t RegionAS923TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ); + +/*! + * \brief The function processes a DlChannel Request. + * + * \param [IN] dlChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionAS923DlChannelReq( DlChannelReqParams_t* dlChannelReq ); + +/*! + * \brief Alternates the datarate of the channel for the join request. + * + * \param [IN] alternateDr Pointer to the function parameters. + * + * \retval Datarate to apply. + */ +int8_t RegionAS923AlternateDr( AlternateDrParams_t* alternateDr ); + +/*! + * \brief Calculates the back-off time. + * + * \param [IN] calcBackOff Pointer to the function parameters. + */ +void RegionAS923CalcBackOff( CalcBackOffParams_t* calcBackOff ); + +/*! + * \brief Searches and set the next random available channel + * + * \param [OUT] channel Next channel to use for TX. + * + * \param [OUT] time Time to wait for the next transmission according to the duty + * cycle. + * + * \param [OUT] aggregatedTimeOff Updates the aggregated time off. + * + * \retval Function status [1: OK, 0: Unable to find a channel on the current datarate] + */ +bool RegionAS923NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ); + +/*! + * \brief Adds a channel. + * + * \param [IN] channelAdd Pointer to the function parameters. + * + * \retval Status of the operation. + */ +LoRaMacStatus_t RegionAS923ChannelAdd( ChannelAddParams_t* channelAdd ); + +/*! + * \brief Removes a channel. + * + * \param [IN] channelRemove Pointer to the function parameters. + * + * \retval Returns true, if the channel was removed successfully. + */ +bool RegionAS923ChannelsRemove( ChannelRemoveParams_t* channelRemove ); + +/*! + * \brief Sets the radio into continuous wave mode. + * + * \param [IN] continuousWave Pointer to the function parameters. + */ +void RegionAS923SetContinuousWave( ContinuousWaveParams_t* continuousWave ); + +/*! + * \brief Computes new datarate according to the given offset + * + * \param [IN] downlinkDwellTime Downlink dwell time configuration. 0: No limit, 1: 400ms + * + * \param [IN] dr Current datarate + * + * \param [IN] drOffset Offset to be applied + * + * \retval newDr Computed datarate. + */ +uint8_t RegionAS923ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ); + +/*! + * \brief Sets the radio into beacon reception mode + * + * \param [IN] rxBeaconSetup Pointer to the function parameters + */ + void RegionAS923RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ); + +/*! \} defgroup REGIONAS923 */ + +#endif // __REGION_AS923_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAU915.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAU915.c new file mode 100644 index 00000000..f8e87b4b --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAU915.c @@ -0,0 +1,908 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC region AU915 implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include +#include + +#include "radio.h" +//#include "timer.h" +#include "timeServer.h" +#include "LoRaMac.h" + +#include "utilities.h" + +#include "Region.h" +#include "RegionCommon.h" +#include "RegionAU915.h" +#include "debug.h" + +// Definitions +#define CHANNELS_MASK_SIZE 6 + +// Global attributes +/*! + * LoRaMAC channels + */ +static ChannelParams_t Channels[AU915_MAX_NB_CHANNELS]; + +/*! + * LoRaMac bands + */ +static Band_t Bands[AU915_MAX_NB_BANDS] = +{ + AU915_BAND0 +}; + +/*! + * LoRaMac channels mask + */ +static uint16_t ChannelsMask[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels remaining + */ +static uint16_t ChannelsMaskRemaining[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels default mask + */ +static uint16_t ChannelsDefaultMask[CHANNELS_MASK_SIZE]; + +// Static functions +static int8_t GetNextLowerTxDr( int8_t dr, int8_t minDr ) +{ + uint8_t nextLowerDr = 0; + + if( dr == minDr ) + { + nextLowerDr = minDr; + } + else + { + nextLowerDr = dr - 1; + } + return nextLowerDr; +} + +static uint32_t GetBandwidth( uint32_t drIndex ) +{ + switch( BandwidthsAU915[drIndex] ) + { + default: + case 125000: + return 0; + case 250000: + return 1; + case 500000: + return 2; + } +} + +static int8_t LimitTxPower( int8_t txPower, int8_t maxBandTxPower, int8_t datarate, uint16_t* channelsMask ) +{ + int8_t txPowerResult = txPower; + + // Limit tx power to the band max + txPowerResult = MAX( txPower, maxBandTxPower ); + + return txPowerResult; +} + +static uint8_t CountNbOfEnabledChannels( uint8_t datarate, uint16_t* channelsMask, ChannelParams_t* channels, Band_t* bands, uint8_t* enabledChannels, uint8_t* delayTx ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTransmission = 0; + + for( uint8_t i = 0, k = 0; i < AU915_MAX_NB_CHANNELS; i += 16, k++ ) + { + for( uint8_t j = 0; j < 16; j++ ) + { + if( ( channelsMask[k] & ( 1 << j ) ) != 0 ) + { + if( channels[i + j].Frequency == 0 ) + { // Check if the channel is enabled + continue; + } + if( RegionCommonValueInRange( datarate, channels[i + j].DrRange.Fields.Min, + channels[i + j].DrRange.Fields.Max ) == false ) + { // Check if the current channel selection supports the given datarate + continue; + } + if( bands[channels[i + j].Band].TimeOff > 0 ) + { // Check if the band is available for transmission + delayTransmission++; + continue; + } + enabledChannels[nbEnabledChannels++] = i + j; + } + } + } + + *delayTx = delayTransmission; + return nbEnabledChannels; +} + +PhyParam_t RegionAU915GetPhyParam( GetPhyParams_t* getPhy ) +{ + PhyParam_t phyParam = { 0 }; + + switch( getPhy->Attribute ) + { + case PHY_MIN_RX_DR: + { + phyParam.Value = AU915_RX_MIN_DATARATE; + break; + } + case PHY_MIN_TX_DR: + { + phyParam.Value = AU915_TX_MIN_DATARATE; + break; + } + case PHY_DEF_TX_DR: + { + phyParam.Value = AU915_DEFAULT_DATARATE; + break; + } + case PHY_NEXT_LOWER_TX_DR: + { + phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, AU915_TX_MIN_DATARATE ); + break; + } + case PHY_DEF_TX_POWER: + { + phyParam.Value = AU915_DEFAULT_TX_POWER; + break; + } + case PHY_MAX_PAYLOAD: + { + phyParam.Value = MaxPayloadOfDatarateAU915[getPhy->Datarate]; + break; + } + case PHY_MAX_PAYLOAD_REPEATER: + { + phyParam.Value = MaxPayloadOfDatarateRepeaterAU915[getPhy->Datarate]; + break; + } + case PHY_DUTY_CYCLE: + { + phyParam.Value = AU915_DUTY_CYCLE_ENABLED; + break; + } + case PHY_MAX_RX_WINDOW: + { + phyParam.Value = AU915_MAX_RX_WINDOW; + break; + } + case PHY_RECEIVE_DELAY1: + { + phyParam.Value = AU915_RECEIVE_DELAY1; + break; + } + case PHY_RECEIVE_DELAY2: + { + phyParam.Value = AU915_RECEIVE_DELAY2; + break; + } + case PHY_JOIN_ACCEPT_DELAY1: + { + phyParam.Value = AU915_JOIN_ACCEPT_DELAY1; + break; + } + case PHY_JOIN_ACCEPT_DELAY2: + { + phyParam.Value = AU915_JOIN_ACCEPT_DELAY2; + break; + } + case PHY_MAX_FCNT_GAP: + { + phyParam.Value = AU915_MAX_FCNT_GAP; + break; + } + case PHY_ACK_TIMEOUT: + { + phyParam.Value = ( AU915_ACKTIMEOUT + randr( -AU915_ACK_TIMEOUT_RND, AU915_ACK_TIMEOUT_RND ) ); + break; + } + case PHY_DEF_DR1_OFFSET: + { + phyParam.Value = AU915_DEFAULT_RX1_DR_OFFSET; + break; + } + case PHY_DEF_RX2_FREQUENCY: + { + phyParam.Value = AU915_RX_WND_2_FREQ; + break; + } + case PHY_DEF_RX2_DR: + { + phyParam.Value = AU915_RX_WND_2_DR; + break; + } + case PHY_CHANNELS_MASK: + { + phyParam.ChannelsMask = ChannelsMask; + break; + } + case PHY_CHANNELS_DEFAULT_MASK: + { + phyParam.ChannelsMask = ChannelsDefaultMask; + break; + } + case PHY_MAX_NB_CHANNELS: + { + phyParam.Value = AU915_MAX_NB_CHANNELS; + break; + } + case PHY_CHANNELS: + { + phyParam.Channels = Channels; + break; + } + case PHY_DEF_UPLINK_DWELL_TIME: + case PHY_DEF_DOWNLINK_DWELL_TIME: + { + phyParam.Value = 0; + break; + } + case PHY_DEF_MAX_EIRP: + { + phyParam.fValue = AU915_DEFAULT_MAX_EIRP; + break; + } + case PHY_DEF_ANTENNA_GAIN: + { + phyParam.fValue = AU915_DEFAULT_ANTENNA_GAIN; + break; + } + case PHY_NB_JOIN_TRIALS: + case PHY_DEF_NB_JOIN_TRIALS: + { + phyParam.Value = 2; + break; + } + case PHY_BEACON_FORMAT: + { + phyParam.BeaconFormat.BeaconSize = AU915_BEACON_SIZE; + phyParam.BeaconFormat.Rfu1Size = AU915_RFU1_SIZE; + phyParam.BeaconFormat.Rfu2Size = AU915_RFU2_SIZE; + break; + } + case PHY_BEACON_CHANNEL_DR: + { + phyParam.Value = AU915_BEACON_CHANNEL_DR; + break; + } + case PHY_BEACON_CHANNEL_STEPWIDTH: + { + phyParam.Value = AU915_BEACON_CHANNEL_STEPWIDTH; + break; + } + case PHY_BEACON_NB_CHANNELS: + { + phyParam.Value = AU915_BEACON_NB_CHANNELS; + break; + } + default: + { + break; + } + } + + return phyParam; +} + +void RegionAU915SetBandTxDone( SetBandTxDoneParams_t* txDone ) +{ + RegionCommonSetBandTxDone( txDone->Joined, &Bands[Channels[txDone->Channel].Band], txDone->LastTxDoneTime ); +} + +void RegionAU915InitDefaults( InitType_t type ) +{ + switch( type ) + { + case INIT_TYPE_INIT: + { + // Channels + // 125 kHz channels + for( uint8_t i = 0; i < AU915_MAX_NB_CHANNELS - 8; i++ ) + { + Channels[i].Frequency = 915200000 + i * 200000; + Channels[i].DrRange.Value = ( DR_5 << 4 ) | DR_0; + Channels[i].Band = 0; + } + // 500 kHz channels + for( uint8_t i = AU915_MAX_NB_CHANNELS - 8; i < AU915_MAX_NB_CHANNELS; i++ ) + { + Channels[i].Frequency = 915900000 + ( i - ( AU915_MAX_NB_CHANNELS - 8 ) ) * 1600000; + Channels[i].DrRange.Value = ( DR_6 << 4 ) | DR_6; + Channels[i].Band = 0; + } + + // Initialize channels default mask + ChannelsDefaultMask[0] = 0xFFFF; + ChannelsDefaultMask[1] = 0xFFFF; + ChannelsDefaultMask[2] = 0xFFFF; + ChannelsDefaultMask[3] = 0xFFFF; + ChannelsDefaultMask[4] = 0x00FF; + ChannelsDefaultMask[5] = 0x0000; + + // Copy channels default mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 6 ); + + // Copy into channels mask remaining + RegionCommonChanMaskCopy( ChannelsMaskRemaining, ChannelsMask, 6 ); + break; + } + case INIT_TYPE_RESTORE: + { + // Copy channels default mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 6 ); + + for( uint8_t i = 0; i < 6; i++ ) + { // Copy-And the channels mask + ChannelsMaskRemaining[i] &= ChannelsMask[i]; + } + break; + } + default: + { + break; + } + } +} + +bool RegionAU915Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ) +{ + switch( phyAttribute ) + { + case PHY_TX_DR: + case PHY_DEF_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, AU915_TX_MIN_DATARATE, AU915_TX_MAX_DATARATE ); + } + case PHY_RX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, AU915_RX_MIN_DATARATE, AU915_RX_MAX_DATARATE ); + } + case PHY_DEF_TX_POWER: + case PHY_TX_POWER: + { + // Remark: switched min and max! + return RegionCommonValueInRange( verify->TxPower, AU915_MAX_TX_POWER, AU915_MIN_TX_POWER ); + } + case PHY_DUTY_CYCLE: + { + return AU915_DUTY_CYCLE_ENABLED; + } + case PHY_NB_JOIN_TRIALS: + { + if( verify->NbJoinTrials < 2 ) + { + return false; + } + break; + } + default: + return false; + } + return true; +} + +void RegionAU915ApplyCFList( ApplyCFListParams_t* applyCFList ) +{ + return; +} + +bool RegionAU915ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ) +{ + uint8_t nbChannels = RegionCommonCountChannels( chanMaskSet->ChannelsMaskIn, 0, 4 ); + + // Check the number of active channels + // According to ACMA regulation, we require at least 20 125KHz channels, if + // the node shall utilize 125KHz channels. + if( ( nbChannels < 20 ) && + ( nbChannels > 0 ) ) + { + return false; + } + + switch( chanMaskSet->ChannelsMaskType ) + { + case CHANNELS_MASK: + { + RegionCommonChanMaskCopy( ChannelsMask, chanMaskSet->ChannelsMaskIn, 6 ); + + for( uint8_t i = 0; i < 6; i++ ) + { // Copy-And the channels mask + ChannelsMaskRemaining[i] &= ChannelsMask[i]; + } + break; + } + case CHANNELS_DEFAULT_MASK: + { + RegionCommonChanMaskCopy( ChannelsDefaultMask, chanMaskSet->ChannelsMaskIn, 6 ); + break; + } + default: + return false; + } + return true; +} + +bool RegionAU915AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ) +{ + bool adrAckReq = false; + int8_t datarate = adrNext->Datarate; + int8_t txPower = adrNext->TxPower; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + // Report back the adr ack counter + *adrAckCounter = adrNext->AdrAckCounter; + + if( adrNext->AdrEnabled == true ) + { + if( datarate == AU915_TX_MIN_DATARATE ) + { + *adrAckCounter = 0; + adrAckReq = false; + } + else + { + if( adrNext->AdrAckCounter >= AU915_ADR_ACK_LIMIT ) + { + adrAckReq = true; + txPower = AU915_MAX_TX_POWER; + } + else + { + adrAckReq = false; + } + if( adrNext->AdrAckCounter >= ( AU915_ADR_ACK_LIMIT + AU915_ADR_ACK_DELAY ) ) + { + if( ( adrNext->AdrAckCounter % AU915_ADR_ACK_DELAY ) == 1 ) + { + // Decrease the datarate + getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + getPhy.Datarate = datarate; + getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + phyParam = RegionAU915GetPhyParam( &getPhy ); + datarate = phyParam.Value; + + if( datarate == AU915_TX_MIN_DATARATE ) + { + // We must set adrAckReq to false as soon as we reach the lowest datarate + adrAckReq = false; + if( adrNext->UpdateChanMask == true ) + { + // Re-enable default channels + ChannelsMask[0] = 0xFFFF; + ChannelsMask[1] = 0xFFFF; + ChannelsMask[2] = 0xFFFF; + ChannelsMask[3] = 0xFFFF; + ChannelsMask[4] = 0x00FF; + ChannelsMask[5] = 0x0000; + } + } + } + } + } + } + + *drOut = datarate; + *txPowOut = txPower; + return adrAckReq; +} + +void RegionAU915ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ) +{ + double tSymbol = 0.0; + uint32_t radioWakeUpTime; + + rxConfigParams->Datarate = datarate; + rxConfigParams->Bandwidth = GetBandwidth( datarate ); + + if( datarate == DR_7 ) + { // FSK + tSymbol = RegionCommonComputeSymbolTimeFsk( DataratesAU915[datarate] ); + } + else + { // LoRa + tSymbol = RegionCommonComputeSymbolTimeLoRa( DataratesAU915[datarate], BandwidthsAU915[datarate] ); + } + + radioWakeUpTime = Radio.GetWakeupTime( ); + RegionCommonComputeRxWindowParameters( tSymbol, minRxSymbols, rxError, radioWakeUpTime, &rxConfigParams->WindowTimeout, &rxConfigParams->WindowOffset ); +} + +bool RegionAU915RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ) +{ + int8_t dr = rxConfig->Datarate; + uint8_t maxPayload = 0; + int8_t phyDr = 0; + uint32_t frequency = rxConfig->Frequency; + + if( Radio.GetStatus( ) != RF_IDLE ) + { + return false; + } + + if( rxConfig->RxSlot == RX_SLOT_WIN_1 ) + { + // Apply window 1 frequency + frequency = AU915_FIRST_RX1_CHANNEL + ( rxConfig->Channel % 8 ) * AU915_STEPWIDTH_RX1_CHANNEL; + } + + // Read the physical datarate from the datarates table + phyDr = DataratesAU915[dr]; + + Radio.SetChannel( frequency ); + + // Radio configuration + Radio.SetRxConfig( MODEM_LORA, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, false, 0, false, 0, 0, true, rxConfig->RxContinuous ); + + if( rxConfig->RepeaterSupport == true ) + { + maxPayload = MaxPayloadOfDatarateRepeaterAU915[dr]; + } + else + { + maxPayload = MaxPayloadOfDatarateAU915[dr]; + } + Radio.SetMaxPayloadLength( MODEM_LORA, maxPayload + LORA_MAC_FRMPAYLOAD_OVERHEAD ); + DBG_PRINTF("RX on freq %u Hz at DR %d\n\r", (unsigned int)frequency, dr); + + *datarate = (uint8_t) dr; + return true; +} + +bool RegionAU915TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) +{ + int8_t phyDr = DataratesAU915[txConfig->Datarate]; + int8_t txPowerLimited = LimitTxPower( txConfig->TxPower, Bands[Channels[txConfig->Channel].Band].TxMaxPower, txConfig->Datarate, ChannelsMask ); + uint32_t bandwidth = GetBandwidth( txConfig->Datarate ); + int8_t phyTxPower = 0; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, txConfig->MaxEirp, txConfig->AntennaGain ); + + Radio.SetChannel( Channels[txConfig->Channel].Frequency ); + + Radio.SetMaxPayloadLength( MODEM_LORA, txConfig->PktLen ); + Radio.SetTxConfig( MODEM_LORA, phyTxPower, 0, bandwidth, phyDr, 1, 8, false, true, 0, 0, false, 3e3 ); + DBG_PRINTF("TX on freq %u Hz at DR %d\n\r", (unsigned int)Channels[txConfig->Channel].Frequency, txConfig->Datarate); + + *txTimeOnAir = Radio.TimeOnAir( MODEM_LORA, txConfig->PktLen ); + *txPower = txPowerLimited; + + return true; +} + +uint8_t RegionAU915LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ) +{ + uint8_t status = 0x07; + LinkAdrParams_t linkAdrParams; + uint8_t nextIndex = 0; + uint8_t bytesProcessed = 0; + uint16_t channelsMask[6] = { 0, 0, 0, 0, 0, 0 }; + + // Initialize local copy of channels mask + RegionCommonChanMaskCopy( channelsMask, ChannelsMask, 6 ); + + while( bytesProcessed < linkAdrReq->PayloadSize ) + { + nextIndex = RegionCommonParseLinkAdrReq( &( linkAdrReq->Payload[bytesProcessed] ), &linkAdrParams ); + + if( nextIndex == 0 ) + break; // break loop, since no more request has been found + + // Update bytes processed + bytesProcessed += nextIndex; + + // Revert status, as we only check the last ADR request for the channel mask KO + status = 0x07; + + if( linkAdrParams.ChMaskCtrl == 6 ) + { + // Enable all 125 kHz channels + channelsMask[0] = 0xFFFF; + channelsMask[1] = 0xFFFF; + channelsMask[2] = 0xFFFF; + channelsMask[3] = 0xFFFF; + // Apply chMask to channels 64 to 71 + channelsMask[4] = linkAdrParams.ChMask; + } + else if( linkAdrParams.ChMaskCtrl == 7 ) + { + // Disable all 125 kHz channels + channelsMask[0] = 0x0000; + channelsMask[1] = 0x0000; + channelsMask[2] = 0x0000; + channelsMask[3] = 0x0000; + // Apply chMask to channels 64 to 71 + channelsMask[4] = linkAdrParams.ChMask; + } + else if( linkAdrParams.ChMaskCtrl == 5 ) + { + // RFU + status &= 0xFE; // Channel mask KO + } + else + { + channelsMask[linkAdrParams.ChMaskCtrl] = linkAdrParams.ChMask; + } + } + + // FCC 15.247 paragraph F mandates to hop on at least 2 125 kHz channels + if( ( linkAdrParams.Datarate < DR_4 ) && ( RegionCommonCountChannels( channelsMask, 0, 4 ) < 2 ) ) + { + status &= 0xFE; // Channel mask KO + } + + // Verify datarate + if( RegionCommonChanVerifyDr( AU915_MAX_NB_CHANNELS, channelsMask, linkAdrParams.Datarate, AU915_TX_MIN_DATARATE, AU915_TX_MAX_DATARATE, Channels ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify tx power + if( RegionCommonValueInRange( linkAdrParams.TxPower, AU915_MAX_TX_POWER, AU915_MIN_TX_POWER ) == 0 ) + { + // Verify if the maximum TX power is exceeded + if( AU915_MAX_TX_POWER > linkAdrParams.TxPower ) + { // Apply maximum TX power. Accept TX power. + linkAdrParams.TxPower = AU915_MAX_TX_POWER; + } + else + { + status &= 0xFB; // TxPower KO + } + } + + // Update channelsMask if everything is correct + if( status == 0x07 ) + { + if( linkAdrParams.NbRep == 0 ) + { // Value of 0 is not allowed, revert to default. + linkAdrParams.NbRep = 1; + } + + // Copy Mask + RegionCommonChanMaskCopy( ChannelsMask, channelsMask, 6 ); + + ChannelsMaskRemaining[0] &= ChannelsMask[0]; + ChannelsMaskRemaining[1] &= ChannelsMask[1]; + ChannelsMaskRemaining[2] &= ChannelsMask[2]; + ChannelsMaskRemaining[3] &= ChannelsMask[3]; + ChannelsMaskRemaining[4] = ChannelsMask[4]; + ChannelsMaskRemaining[5] = ChannelsMask[5]; + } + + // Update status variables + *drOut = linkAdrParams.Datarate; + *txPowOut = linkAdrParams.TxPower; + *nbRepOut = linkAdrParams.NbRep; + *nbBytesParsed = bytesProcessed; + + return status; +} + +uint8_t RegionAU915RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ) +{ + uint8_t status = 0x07; + uint32_t freq = rxParamSetupReq->Frequency; + + // Verify radio frequency + if( ( Radio.CheckRfFrequency( freq ) == false ) || + ( freq < AU915_FIRST_RX1_CHANNEL ) || + ( freq > AU915_LAST_RX1_CHANNEL ) || + ( ( ( freq - ( uint32_t ) AU915_FIRST_RX1_CHANNEL ) % ( uint32_t ) AU915_STEPWIDTH_RX1_CHANNEL ) != 0 ) ) + { + status &= 0xFE; // Channel frequency KO + } + + // Verify datarate + if( RegionCommonValueInRange( rxParamSetupReq->Datarate, AU915_RX_MIN_DATARATE, AU915_RX_MAX_DATARATE ) == false ) + { + status &= 0xFD; // Datarate KO + } + if( ( RegionCommonValueInRange( rxParamSetupReq->Datarate, DR_5, DR_7 ) == true ) || + ( rxParamSetupReq->Datarate > DR_13 ) ) + { + status &= 0xFD; // Datarate KO + } + + // Verify datarate offset + if( RegionCommonValueInRange( rxParamSetupReq->DrOffset, AU915_MIN_RX1_DR_OFFSET, AU915_MAX_RX1_DR_OFFSET ) == false ) + { + status &= 0xFB; // Rx1DrOffset range KO + } + + return status; +} + +uint8_t RegionAU915NewChannelReq( NewChannelReqParams_t* newChannelReq ) +{ + // Datarate and frequency KO + return 0; +} + +int8_t RegionAU915TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ) +{ + return -1; +} + +uint8_t RegionAU915DlChannelReq( DlChannelReqParams_t* dlChannelReq ) +{ + return 0; +} + +int8_t RegionAU915AlternateDr( AlternateDrParams_t* alternateDr ) +{ + int8_t datarate = 0; + + // Re-enable 500 kHz default channels + ChannelsMask[4] = 0x00FF; + + if( ( alternateDr->NbTrials & 0x01 ) == 0x01 ) + { + datarate = DR_4; + } + else + { + datarate = DR_0; + } + return datarate; +} + +void RegionAU915CalcBackOff( CalcBackOffParams_t* calcBackOff ) +{ + uint8_t channel = calcBackOff->Channel; + uint16_t joinDutyCycle = 0; + + if( calcBackOff->Joined == false ) + { + // Get the join duty cycle + joinDutyCycle = RegionCommonGetJoinDc( calcBackOff->ElapsedTime ); + // Apply band time-off. + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * joinDutyCycle - calcBackOff->TxTimeOnAir; + } + else + { + Bands[Channels[channel].Band].TimeOff = 0; + } +} + +bool RegionAU915NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTx = 0; + uint8_t enabledChannels[AU915_MAX_NB_CHANNELS] = { 0 }; + TimerTime_t nextTxDelay = 0; + + // Count 125kHz channels + if( RegionCommonCountChannels( ChannelsMaskRemaining, 0, 4 ) == 0 ) + { // Reactivate default channels + RegionCommonChanMaskCopy( ChannelsMaskRemaining, ChannelsMask, 4 ); + } + // Check other channels + if( nextChanParams->Datarate >= DR_4 ) + { + if( ( ChannelsMaskRemaining[4] & 0x00FF ) == 0 ) + { + ChannelsMaskRemaining[4] = ChannelsMask[4]; + } + } + + if( nextChanParams->AggrTimeOff <= TimerGetElapsedTime( nextChanParams->LastAggrTx ) ) + { + // Reset Aggregated time off + *aggregatedTimeOff = 0; + + // Search how many channels are enabled + nbEnabledChannels = CountNbOfEnabledChannels( nextChanParams->Datarate, + ChannelsMaskRemaining, Channels, + Bands, enabledChannels, &delayTx ); + } + else + { + delayTx++; + nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx ); + } + + if( nbEnabledChannels > 0 ) + { + // We found a valid channel + *channel = enabledChannels[randr( 0, nbEnabledChannels - 1 )]; + // Disable the channel in the mask + RegionCommonChanDisable( ChannelsMaskRemaining, *channel, AU915_MAX_NB_CHANNELS - 8 ); + + *time = 0; + return true; + } + else + { + if( delayTx > 0 ) + { + // Delay transmission due to AggregatedTimeOff or to a band time off + *time = nextTxDelay; + return true; + } + // Datarate not supported by any channel + *time = 0; + return false; + } +} + +LoRaMacStatus_t RegionAU915ChannelAdd( ChannelAddParams_t* channelAdd ) +{ + return LORAMAC_STATUS_PARAMETER_INVALID; +} + +bool RegionAU915ChannelsRemove( ChannelRemoveParams_t* channelRemove ) +{ + return LORAMAC_STATUS_PARAMETER_INVALID; +} + +void RegionAU915SetContinuousWave( ContinuousWaveParams_t* continuousWave ) +{ + int8_t txPowerLimited = LimitTxPower( continuousWave->TxPower, Bands[Channels[continuousWave->Channel].Band].TxMaxPower, continuousWave->Datarate, ChannelsMask ); + int8_t phyTxPower = 0; + uint32_t frequency = Channels[continuousWave->Channel].Frequency; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, continuousWave->MaxEirp, continuousWave->AntennaGain ); + + Radio.SetTxContinuousWave( frequency, phyTxPower, continuousWave->Timeout ); +} + +uint8_t RegionAU915ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +{ + int8_t datarate = DatarateOffsetsAU915[dr][drOffset]; + + if( datarate < 0 ) + { + datarate = DR_0; + } + return datarate; +} + +void RegionAU915RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ) +{ + RegionCommonRxBeaconSetupParams_t regionCommonRxBeaconSetup; + + regionCommonRxBeaconSetup.Datarates = DataratesAU915; + regionCommonRxBeaconSetup.Frequency = rxBeaconSetup->Frequency; + regionCommonRxBeaconSetup.BeaconSize = AU915_BEACON_SIZE; + regionCommonRxBeaconSetup.BeaconDatarate = AU915_BEACON_CHANNEL_DR; + regionCommonRxBeaconSetup.BeaconChannelBW = AU915_BEACON_CHANNEL_BW; + regionCommonRxBeaconSetup.RxTime = rxBeaconSetup->RxTime; + regionCommonRxBeaconSetup.SymbolTimeout = rxBeaconSetup->SymbolTimeout; + + RegionCommonRxBeaconSetup( ®ionCommonRxBeaconSetup ); + + // Store downlink datarate + *outDr = AU915_BEACON_CHANNEL_DR; +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAU915.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAU915.h new file mode 100644 index 00000000..ca9ab339 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionAU915.h @@ -0,0 +1,511 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file RegionAU915.h + * + * \brief Region definition for AU915 + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGIONAU915 Region AU915 + * Implementation according to LoRaWAN Specification v1.0.2. + * \{ + */ +#ifndef __REGION_AU915_H__ +#define __REGION_AU915_H__ + +#include "LoRaMac.h" + +/*! + * LoRaMac maximum number of channels + */ +#define AU915_MAX_NB_CHANNELS 72 + +/*! + * Minimal datarate that can be used by the node + */ +#define AU915_TX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define AU915_TX_MAX_DATARATE DR_6 + +/*! + * Minimal datarate that can be used by the node + */ +#define AU915_RX_MIN_DATARATE DR_8 + +/*! + * Maximal datarate that can be used by the node + */ +#define AU915_RX_MAX_DATARATE DR_13 + +/*! + * Default datarate used by the node + */ +#define AU915_DEFAULT_DATARATE DR_0 + +/*! + * Minimal Rx1 receive datarate offset + */ +#define AU915_MIN_RX1_DR_OFFSET 0 + +/*! + * Maximal Rx1 receive datarate offset + */ +#define AU915_MAX_RX1_DR_OFFSET 6 + +/*! + * Default Rx1 receive datarate offset + */ +#define AU915_DEFAULT_RX1_DR_OFFSET 0 + +/*! + * Minimal Tx output power that can be used by the node + */ +#define AU915_MIN_TX_POWER TX_POWER_10 + +/*! + * Maximal Tx output power that can be used by the node + */ +#define AU915_MAX_TX_POWER TX_POWER_0 + +/*! + * Default Tx output power used by the node + */ +#define AU915_DEFAULT_TX_POWER TX_POWER_0 + +/*! + * Default Max EIRP + */ +#define AU915_DEFAULT_MAX_EIRP 30.0f + +/*! + * Default antenna gain + */ +#define AU915_DEFAULT_ANTENNA_GAIN 2.15f + +/*! + * ADR Ack limit + */ +#define AU915_ADR_ACK_LIMIT 64 + +/*! + * ADR Ack delay + */ +#define AU915_ADR_ACK_DELAY 32 + +/*! + * Enabled or disabled the duty cycle + */ +#define AU915_DUTY_CYCLE_ENABLED 0 + +/*! + * Maximum RX window duration + */ +#define AU915_MAX_RX_WINDOW 3000 + +/*! + * Receive delay 1 + */ +#define AU915_RECEIVE_DELAY1 1000 + +/*! + * Receive delay 2 + */ +#define AU915_RECEIVE_DELAY2 2000 + +/*! + * Join accept delay 1 + */ +#define AU915_JOIN_ACCEPT_DELAY1 5000 + +/*! + * Join accept delay 2 + */ +#define AU915_JOIN_ACCEPT_DELAY2 6000 + +/*! + * Maximum frame counter gap + */ +#define AU915_MAX_FCNT_GAP 16384 + +/*! + * Ack timeout + */ +#define AU915_ACKTIMEOUT 2000 + +/*! + * Random ack timeout limits + */ +#define AU915_ACK_TIMEOUT_RND 1000 + +/*! + * Second reception window channel frequency definition. + */ +#define AU915_RX_WND_2_FREQ 923300000 + +/*! + * Second reception window channel datarate definition. + */ +#define AU915_RX_WND_2_DR DR_8 + +/* + * CLASS B + */ +/*! + * Beacon frequency + */ +#define AU915_BEACON_CHANNEL_FREQ 923300000 + +/*! + * Beacon frequency channel stepwidth + */ +#define AU915_BEACON_CHANNEL_STEPWIDTH 600000 + +/*! + * Number of possible beacon channels + */ +#define AU915_BEACON_NB_CHANNELS 8 + +/*! + * Payload size of a beacon frame + */ +#define AU915_BEACON_SIZE 19 + +/*! + * Size of RFU 1 field + */ +#define AU915_RFU1_SIZE 3 + +/*! + * Size of RFU 2 field + */ +#define AU915_RFU2_SIZE 1 + +/*! + * Datarate of the beacon channel + */ +#define AU915_BEACON_CHANNEL_DR DR_10 + +/*! + * Bandwith of the beacon channel + */ +#define AU915_BEACON_CHANNEL_BW 2 + +/*! + * LoRaMac maximum number of bands + */ +#define AU915_MAX_NB_BANDS 1 + +/*! + * Band 0 definition + * { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define AU915_BAND0 { 1, AU915_MAX_TX_POWER, 0, 0 } // 100.0 % + +/*! + * Defines the first channel for RX window 1 for US band + */ +#define AU915_FIRST_RX1_CHANNEL ( (uint32_t) 923300000 ) + +/*! + * Defines the last channel for RX window 1 for US band + */ +#define AU915_LAST_RX1_CHANNEL ( (uint32_t) 927500000 ) + +/*! + * Defines the step width of the channels for RX window 1 + */ +#define AU915_STEPWIDTH_RX1_CHANNEL ( (uint32_t) 600000 ) + +/*! + * Data rates table definition + */ +static const uint8_t DataratesAU915[] = { 12, 11, 10, 9, 8, 7, 8, 0, 12, 11, 10, 9, 8, 7, 0, 0 }; + +/*! + * Bandwidths table definition in Hz + */ +static const uint32_t BandwidthsAU915[] = { 125000, 125000, 125000, 125000, 125000, 125000, 500000, 0, 500000, 500000, 500000, 500000, 500000, 500000, 0, 0 }; + +/*! + * Up/Down link data rates offset definition + */ +static const int8_t DatarateOffsetsAU915[7][6] = +{ + { DR_8 , DR_8 , DR_8 , DR_8 , DR_8 , DR_8 }, // DR_0 + { DR_9 , DR_8 , DR_8 , DR_8 , DR_8 , DR_8 }, // DR_1 + { DR_10, DR_9 , DR_8 , DR_8 , DR_8 , DR_8 }, // DR_2 + { DR_11, DR_10, DR_9 , DR_8 , DR_8 , DR_8 }, // DR_3 + { DR_12, DR_11, DR_10, DR_9 , DR_8 , DR_8 }, // DR_4 + { DR_13, DR_12, DR_11, DR_10, DR_9 , DR_8 }, // DR_5 + { DR_13, DR_13, DR_12, DR_11, DR_10, DR_9 }, // DR_6 +}; + +/*! + * Maximum payload with respect to the datarate index. Cannot operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateAU915[] = { 51, 51, 51, 115, 242, 242, 242, 0, 53, 129, 242, 242, 242, 242, 0, 0 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateRepeaterAU915[] = { 51, 51, 51, 115, 222, 222, 222, 0, 33, 109, 222, 222, 222, 222, 0, 0 }; + +/*! + * \brief The function gets a value of a specific phy attribute. + * + * \param [IN] getPhy Pointer to the function parameters. + * + * \retval Returns a structure containing the PHY parameter. + */ +PhyParam_t RegionAU915GetPhyParam( GetPhyParams_t* getPhy ); + +/*! + * \brief Updates the last TX done parameters of the current channel. + * + * \param [IN] txDone Pointer to the function parameters. + */ +void RegionAU915SetBandTxDone( SetBandTxDoneParams_t* txDone ); + +/*! + * \brief Initializes the channels masks and the channels. + * + * \param [IN] type Sets the initialization type. + */ +void RegionAU915InitDefaults( InitType_t type ); + +/*! + * \brief Verifies a parameter. + * + * \param [IN] verify Pointer to the function parameters. + * + * \param [IN] type Sets the initialization type. + * + * \retval Returns true, if the parameter is valid. + */ +bool RegionAU915Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ); + +/*! + * \brief The function parses the input buffer and sets up the channels of the + * CF list. + * + * \param [IN] applyCFList Pointer to the function parameters. + */ +void RegionAU915ApplyCFList( ApplyCFListParams_t* applyCFList ); + +/*! + * \brief Sets a channels mask. + * + * \param [IN] chanMaskSet Pointer to the function parameters. + * + * \retval Returns true, if the channels mask could be set. + */ +bool RegionAU915ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ); + +/*! + * \brief Calculates the next datarate to set, when ADR is on or off. + * + * \param [IN] adrNext Pointer to the function parameters. + * + * \param [OUT] drOut The calculated datarate for the next TX. + * + * \param [OUT] txPowOut The TX power for the next TX. + * + * \param [OUT] adrAckCounter The calculated ADR acknowledgement counter. + * + * \retval Returns true, if an ADR request should be performed. + */ +bool RegionAU915AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ); + +/*! + * Computes the Rx window timeout and offset. + * + * \param [IN] datarate Rx window datarate index to be used + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms + * interval around RxOffset + * + * \param [OUT]rxConfigParams Returns updated WindowTimeout and WindowOffset fields. + */ +void RegionAU915ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ); + +/*! + * \brief Configuration of the RX windows. + * + * \param [IN] rxConfig Pointer to the function parameters. + * + * \param [OUT] datarate The datarate index which was set. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionAU915RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ); + +/*! + * \brief TX configuration. + * + * \param [IN] txConfig Pointer to the function parameters. + * + * \param [OUT] txPower The tx power index which was set. + * + * \param [OUT] txTimeOnAir The time-on-air of the frame. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionAU915TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ); + +/*! + * \brief The function processes a Link ADR Request. + * + * \param [IN] linkAdrReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionAU915LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ); + +/*! + * \brief The function processes a RX Parameter Setup Request. + * + * \param [IN] rxParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionAU915RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ); + +/*! + * \brief The function processes a Channel Request. + * + * \param [IN] newChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionAU915NewChannelReq( NewChannelReqParams_t* newChannelReq ); + +/*! + * \brief The function processes a TX ParamSetup Request. + * + * \param [IN] txParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + * Returns -1, if the functionality is not implemented. In this case, the end node + * shall not process the command. + */ +int8_t RegionAU915TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ); + +/*! + * \brief The function processes a DlChannel Request. + * + * \param [IN] dlChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionAU915DlChannelReq( DlChannelReqParams_t* dlChannelReq ); + +/*! + * \brief Alternates the datarate of the channel for the join request. + * + * \param [IN] alternateDr Pointer to the function parameters. + * + * \retval Datarate to apply. + */ +int8_t RegionAU915AlternateDr( AlternateDrParams_t* alternateDr ); + +/*! + * \brief Calculates the back-off time. + * + * \param [IN] calcBackOff Pointer to the function parameters. + */ +void RegionAU915CalcBackOff( CalcBackOffParams_t* calcBackOff ); + +/*! + * \brief Searches and set the next random available channel + * + * \param [OUT] channel Next channel to use for TX. + * + * \param [OUT] time Time to wait for the next transmission according to the duty + * cycle. + * + * \param [OUT] aggregatedTimeOff Updates the aggregated time off. + * + * \retval Function status [1: OK, 0: Unable to find a channel on the current datarate] + */ +bool RegionAU915NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ); + +/*! + * \brief Adds a channel. + * + * \param [IN] channelAdd Pointer to the function parameters. + * + * \retval Status of the operation. + */ +LoRaMacStatus_t RegionAU915ChannelAdd( ChannelAddParams_t* channelAdd ); + +/*! + * \brief Removes a channel. + * + * \param [IN] channelRemove Pointer to the function parameters. + * + * \retval Returns true, if the channel was removed successfully. + */ +bool RegionAU915ChannelsRemove( ChannelRemoveParams_t* channelRemove ); + +/*! + * \brief Sets the radio into continuous wave mode. + * + * \param [IN] continuousWave Pointer to the function parameters. + */ +void RegionAU915SetContinuousWave( ContinuousWaveParams_t* continuousWave ); + +/*! + * \brief Computes new datarate according to the given offset + * + * \param [IN] downlinkDwellTime Downlink dwell time configuration. 0: No limit, 1: 400ms + * + * \param [IN] dr Current datarate + * + * \param [IN] drOffset Offset to be applied + * + * \retval newDr Computed datarate. + */ +uint8_t RegionAU915ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ); + +/*! + * \brief Sets the radio into beacon reception mode + * + * \param [IN] rxBeaconSetup Pointer to the function parameters + */ + void RegionAU915RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ); + +/*! \} defgroup REGIONAU915 */ + +#endif // __REGION_AU915_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN470.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN470.c new file mode 100644 index 00000000..1dc33b5d --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN470.c @@ -0,0 +1,853 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC region CN470 implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include +#include + +#include "radio.h" +//#include "timer.h" +#include "timeServer.h" +#include "LoRaMac.h" + +#include "utilities.h" + +#include "Region.h" +#include "RegionCommon.h" +#include "RegionCN470.h" +#include "debug.h" + +// Definitions +#define CHANNELS_MASK_SIZE 6 + +// Global attributes +/*! + * LoRaMAC channels + */ +static ChannelParams_t Channels[CN470_MAX_NB_CHANNELS]; + +/*! + * LoRaMac bands + */ +static Band_t Bands[CN470_MAX_NB_BANDS] = +{ + CN470_BAND0 +}; + +/*! + * LoRaMac channels mask + */ +static uint16_t ChannelsMask[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels default mask + */ +static uint16_t ChannelsDefaultMask[CHANNELS_MASK_SIZE]; + +// Static functions +static int8_t GetNextLowerTxDr( int8_t dr, int8_t minDr ) +{ + uint8_t nextLowerDr = 0; + + if( dr == minDr ) + { + nextLowerDr = minDr; + } + else + { + nextLowerDr = dr - 1; + } + return nextLowerDr; +} + +static uint32_t GetBandwidth( uint32_t drIndex ) +{ + switch( BandwidthsCN470[drIndex] ) + { + default: + case 125000: + return 0; + case 250000: + return 1; + case 500000: + return 2; + } +} + +static int8_t LimitTxPower( int8_t txPower, int8_t maxBandTxPower, int8_t datarate, uint16_t* channelsMask ) +{ + int8_t txPowerResult = txPower; + + // Limit tx power to the band max + txPowerResult = MAX( txPower, maxBandTxPower ); + + return txPowerResult; +} + +static uint8_t CountNbOfEnabledChannels( uint8_t datarate, uint16_t* channelsMask, ChannelParams_t* channels, Band_t* bands, uint8_t* enabledChannels, uint8_t* delayTx ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTransmission = 0; + + for( uint8_t i = 0, k = 0; i < CN470_MAX_NB_CHANNELS; i += 16, k++ ) + { + for( uint8_t j = 0; j < 16; j++ ) + { + if( ( channelsMask[k] & ( 1 << j ) ) != 0 ) + { + if( channels[i + j].Frequency == 0 ) + { // Check if the channel is enabled + continue; + } + if( RegionCommonValueInRange( datarate, channels[i + j].DrRange.Fields.Min, + channels[i + j].DrRange.Fields.Max ) == false ) + { // Check if the current channel selection supports the given datarate + continue; + } + if( bands[channels[i + j].Band].TimeOff > 0 ) + { // Check if the band is available for transmission + delayTransmission++; + continue; + } + enabledChannels[nbEnabledChannels++] = i + j; + } + } + } + //printf("nbEnabledChannels: %d ",nbEnabledChannels); + *delayTx = delayTransmission; + return nbEnabledChannels; +} + +PhyParam_t RegionCN470GetPhyParam( GetPhyParams_t* getPhy ) +{ + PhyParam_t phyParam = { 0 }; + + switch( getPhy->Attribute ) + { + case PHY_MIN_RX_DR: + { + phyParam.Value = CN470_RX_MIN_DATARATE; + break; + } + case PHY_MIN_TX_DR: + { + phyParam.Value = CN470_TX_MIN_DATARATE; + break; + } + case PHY_DEF_TX_DR: + { + phyParam.Value = CN470_DEFAULT_DATARATE; + break; + } + case PHY_NEXT_LOWER_TX_DR: + { + phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, CN470_TX_MIN_DATARATE ); + break; + } + case PHY_DEF_TX_POWER: + { + phyParam.Value = CN470_DEFAULT_TX_POWER; + break; + } + case PHY_MAX_PAYLOAD: + { + phyParam.Value = MaxPayloadOfDatarateCN470[getPhy->Datarate]; + break; + } + case PHY_MAX_PAYLOAD_REPEATER: + { + phyParam.Value = MaxPayloadOfDatarateRepeaterCN470[getPhy->Datarate]; + break; + } + case PHY_DUTY_CYCLE: + { + phyParam.Value = CN470_DUTY_CYCLE_ENABLED; + break; + } + case PHY_MAX_RX_WINDOW: + { + phyParam.Value = CN470_MAX_RX_WINDOW; + break; + } + case PHY_RECEIVE_DELAY1: + { + phyParam.Value = CN470_RECEIVE_DELAY1; + break; + } + case PHY_RECEIVE_DELAY2: + { + phyParam.Value = CN470_RECEIVE_DELAY2; + break; + } + case PHY_JOIN_ACCEPT_DELAY1: + { + phyParam.Value = CN470_JOIN_ACCEPT_DELAY1; + break; + } + case PHY_JOIN_ACCEPT_DELAY2: + { + phyParam.Value = CN470_JOIN_ACCEPT_DELAY2; + break; + } + case PHY_MAX_FCNT_GAP: + { + phyParam.Value = CN470_MAX_FCNT_GAP; + break; + } + case PHY_ACK_TIMEOUT: + { + phyParam.Value = ( CN470_ACKTIMEOUT + randr( -CN470_ACK_TIMEOUT_RND, CN470_ACK_TIMEOUT_RND ) ); + break; + } + case PHY_DEF_DR1_OFFSET: + { + phyParam.Value = CN470_DEFAULT_RX1_DR_OFFSET; + break; + } + case PHY_DEF_RX2_FREQUENCY: + { + phyParam.Value = CN470_RX_WND_2_FREQ; + break; + } + case PHY_DEF_RX2_DR: + { + phyParam.Value = CN470_RX_WND_2_DR; + break; + } + case PHY_CHANNELS_MASK: + { + phyParam.ChannelsMask = ChannelsMask; + break; + } + case PHY_CHANNELS_DEFAULT_MASK: + { + phyParam.ChannelsMask = ChannelsDefaultMask; + break; + } + case PHY_MAX_NB_CHANNELS: + { + phyParam.Value = CN470_MAX_NB_CHANNELS; + break; + } + case PHY_CHANNELS: + { + phyParam.Channels = Channels; + break; + } + case PHY_DEF_UPLINK_DWELL_TIME: + case PHY_DEF_DOWNLINK_DWELL_TIME: + { + phyParam.Value = 0; + break; + } + case PHY_DEF_MAX_EIRP: + { + phyParam.fValue = CN470_DEFAULT_MAX_EIRP; + break; + } + case PHY_DEF_ANTENNA_GAIN: + { + phyParam.fValue = CN470_DEFAULT_ANTENNA_GAIN; + break; + } + case PHY_NB_JOIN_TRIALS: + case PHY_DEF_NB_JOIN_TRIALS: + { + phyParam.Value = 48; + break; + } + case PHY_BEACON_FORMAT: + { + phyParam.BeaconFormat.BeaconSize = CN470_BEACON_SIZE; + phyParam.BeaconFormat.Rfu1Size = CN470_RFU1_SIZE; + phyParam.BeaconFormat.Rfu2Size = CN470_RFU2_SIZE; + break; + } + case PHY_BEACON_CHANNEL_DR: + { + phyParam.Value = CN470_BEACON_CHANNEL_DR; + break; + } + case PHY_BEACON_CHANNEL_STEPWIDTH: + { + phyParam.Value = CN470_BEACON_CHANNEL_STEPWIDTH; + break; + } + case PHY_BEACON_NB_CHANNELS: + { + phyParam.Value = CN470_BEACON_NB_CHANNELS; + break; + } + default: + { + break; + } + } + + return phyParam; +} + +void RegionCN470SetBandTxDone( SetBandTxDoneParams_t* txDone ) +{ + RegionCommonSetBandTxDone( txDone->Joined, &Bands[Channels[txDone->Channel].Band], txDone->LastTxDoneTime ); +} + +void RegionCN470InitDefaults( InitType_t type ) +{ + switch( type ) + { + case INIT_TYPE_INIT: + { + // Channels + // 125 kHz channels + for( uint8_t i = 0; i < CN470_MAX_NB_CHANNELS; i++ ) + { + Channels[i].Frequency = 470300000 + i * 200000; + Channels[i].DrRange.Value = ( DR_5 << 4 ) | DR_0; + Channels[i].Band = 0; + } + + // Initialize the channels default mask + ChannelsDefaultMask[0] = 0xFFFF; + ChannelsDefaultMask[1] = 0xFFFF; + ChannelsDefaultMask[2] = 0xFFFF; + ChannelsDefaultMask[3] = 0xFFFF; + ChannelsDefaultMask[4] = 0xFFFF; + ChannelsDefaultMask[5] = 0xFFFF; + + // Update the channels mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 6 ); + break; + } + case INIT_TYPE_RESTORE: + { + // Restore channels default mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 6 ); + break; + } + default: + { + break; + } + } +} + +bool RegionCN470Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ) +{ + switch( phyAttribute ) + { + case PHY_TX_DR: + case PHY_DEF_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, CN470_TX_MIN_DATARATE, CN470_TX_MAX_DATARATE ); + } + case PHY_RX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, CN470_RX_MIN_DATARATE, CN470_RX_MAX_DATARATE ); + } + case PHY_DEF_TX_POWER: + case PHY_TX_POWER: + { + // Remark: switched min and max! + return RegionCommonValueInRange( verify->TxPower, CN470_MAX_TX_POWER, CN470_MIN_TX_POWER ); + } + case PHY_DUTY_CYCLE: + { + return CN470_DUTY_CYCLE_ENABLED; + } + case PHY_NB_JOIN_TRIALS: + { + if( verify->NbJoinTrials < 48 ) + { + return false; + } + break; + } + default: + return false; + } + return true; +} + +void RegionCN470ApplyCFList( ApplyCFListParams_t* applyCFList ) +{ + return; +} + +bool RegionCN470ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ) +{ + switch( chanMaskSet->ChannelsMaskType ) + { + case CHANNELS_MASK: + { + RegionCommonChanMaskCopy( ChannelsMask, chanMaskSet->ChannelsMaskIn, 6 ); + break; + } + case CHANNELS_DEFAULT_MASK: + { + RegionCommonChanMaskCopy( ChannelsDefaultMask, chanMaskSet->ChannelsMaskIn, 6 ); + break; + } + default: + return false; + } + return true; +} + +bool RegionCN470AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ) +{ + bool adrAckReq = false; + int8_t datarate = adrNext->Datarate; + int8_t txPower = adrNext->TxPower; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + // Report back the adr ack counter + *adrAckCounter = adrNext->AdrAckCounter; + + if( adrNext->AdrEnabled == true ) + { + if( datarate == CN470_TX_MIN_DATARATE ) + { + *adrAckCounter = 0; + adrAckReq = false; + } + else + { + if( adrNext->AdrAckCounter >= CN470_ADR_ACK_LIMIT ) + { + adrAckReq = true; + txPower = CN470_MAX_TX_POWER; + } + else + { + adrAckReq = false; + } + if( adrNext->AdrAckCounter >= ( CN470_ADR_ACK_LIMIT + CN470_ADR_ACK_DELAY ) ) + { + if( ( adrNext->AdrAckCounter % CN470_ADR_ACK_DELAY ) == 1 ) + { + // Decrease the datarate + getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + getPhy.Datarate = datarate; + getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + phyParam = RegionCN470GetPhyParam( &getPhy ); + datarate = phyParam.Value; + + if( datarate == CN470_TX_MIN_DATARATE ) + { + // We must set adrAckReq to false as soon as we reach the lowest datarate + adrAckReq = false; + if( adrNext->UpdateChanMask == true ) + { + // Re-enable default channels + ChannelsMask[0] = 0xFFFF; + ChannelsMask[1] = 0xFFFF; + ChannelsMask[2] = 0xFFFF; + ChannelsMask[3] = 0xFFFF; + ChannelsMask[4] = 0xFFFF; + ChannelsMask[5] = 0xFFFF; + } + } + } + } + } + } + + *drOut = datarate; + *txPowOut = txPower; + return adrAckReq; +} + +void RegionCN470ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ) +{ + double tSymbol = 0.0; + uint32_t radioWakeUpTime; + + rxConfigParams->Datarate = datarate; + rxConfigParams->Bandwidth = GetBandwidth( datarate ); + + tSymbol = RegionCommonComputeSymbolTimeLoRa( DataratesCN470[datarate], BandwidthsCN470[datarate] ); + + radioWakeUpTime = Radio.GetWakeupTime( ); + RegionCommonComputeRxWindowParameters( tSymbol, minRxSymbols, rxError, radioWakeUpTime, &rxConfigParams->WindowTimeout, &rxConfigParams->WindowOffset ); +} + +bool RegionCN470RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ) +{ + int8_t dr = rxConfig->Datarate; + uint8_t maxPayload = 0; + int8_t phyDr = 0; + uint32_t frequency = rxConfig->Frequency; + + if( Radio.GetStatus( ) != RF_IDLE ) + { + return false; + } + + if( rxConfig->RxSlot == RX_SLOT_WIN_1 ) + { + // Apply window 1 frequency + frequency = CN470_FIRST_RX1_CHANNEL + ( rxConfig->Channel % 48 ) * CN470_STEPWIDTH_RX1_CHANNEL; + } + + // Read the physical datarate from the datarates table + phyDr = DataratesCN470[dr]; + + Radio.SetChannel( frequency ); + + // Radio configuration + Radio.SetRxConfig( MODEM_LORA, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, false, 0, false, 0, 0, true, rxConfig->RxContinuous ); + + if( rxConfig->RepeaterSupport == true ) + { + maxPayload = MaxPayloadOfDatarateRepeaterCN470[dr]; + } + else + { + maxPayload = MaxPayloadOfDatarateCN470[dr]; + } + Radio.SetMaxPayloadLength( MODEM_LORA, maxPayload + LORA_MAC_FRMPAYLOAD_OVERHEAD ); + + *datarate = (uint8_t) dr; + return true; +} + +bool RegionCN470TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) +{ + int8_t phyDr = DataratesCN470[txConfig->Datarate]; + int8_t txPowerLimited = LimitTxPower( txConfig->TxPower, Bands[Channels[txConfig->Channel].Band].TxMaxPower, txConfig->Datarate, ChannelsMask ); + int8_t phyTxPower = 0; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, txConfig->MaxEirp, txConfig->AntennaGain ); + //printf("\r\ntx Power: %d freq: %d\r\n",txPowerLimited,Channels[txConfig->Channel].Frequency); + // Setup the radio frequency + Radio.SetChannel( Channels[txConfig->Channel].Frequency ); + + Radio.SetTxConfig( MODEM_LORA, phyTxPower, 0, 0, phyDr, 1, 8, false, true, 0, 0, false, 3000 ); + // Setup maximum payload lenght of the radio driver + Radio.SetMaxPayloadLength( MODEM_LORA, txConfig->PktLen ); + // Get the time-on-air of the next tx frame + *txTimeOnAir = Radio.TimeOnAir( MODEM_LORA, txConfig->PktLen ); + *txPower = txPowerLimited; + + return true; +} + +uint8_t RegionCN470LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ) +{ + uint8_t status = 0x07; + LinkAdrParams_t linkAdrParams; + uint8_t nextIndex = 0; + uint8_t bytesProcessed = 0; + uint16_t channelsMask[6] = { 0, 0, 0, 0, 0, 0 }; + + // Initialize local copy of channels mask + RegionCommonChanMaskCopy( channelsMask, ChannelsMask, 6 ); + + while( bytesProcessed < linkAdrReq->PayloadSize ) + { + // Get ADR request parameters + nextIndex = RegionCommonParseLinkAdrReq( &( linkAdrReq->Payload[bytesProcessed] ), &linkAdrParams ); + + if( nextIndex == 0 ) + break; // break loop, since no more request has been found + + // Update bytes processed + bytesProcessed += nextIndex; + + // Revert status, as we only check the last ADR request for the channel mask KO + status = 0x07; + + if( linkAdrParams.ChMaskCtrl == 6 ) + { + // Enable all 125 kHz channels + channelsMask[0] = 0xFFFF; + channelsMask[1] = 0xFFFF; + channelsMask[2] = 0xFFFF; + channelsMask[3] = 0xFFFF; + channelsMask[4] = 0xFFFF; + channelsMask[5] = 0xFFFF; + } + else if( linkAdrParams.ChMaskCtrl == 7 ) + { + status &= 0xFE; // Channel mask KO + } + else + { + //printf("linkAdrParams.ChMaskCtrl:%d ",linkAdrParams.ChMaskCtrl); + for( uint8_t i = 0; i < 16; i++ ) + { + if( ( ( linkAdrParams.ChMask & ( 1 << i ) ) != 0 ) && + ( Channels[linkAdrParams.ChMaskCtrl * 16 + i].Frequency == 0 ) ) + {// Trying to enable an undefined channel + status &= 0xFE; // Channel mask KO + } + } + channelsMask[linkAdrParams.ChMaskCtrl] = linkAdrParams.ChMask; + } + } + // Verify datarate + if( RegionCommonChanVerifyDr( CN470_MAX_NB_CHANNELS, channelsMask, linkAdrParams.Datarate, CN470_TX_MIN_DATARATE, CN470_TX_MAX_DATARATE, Channels ) == false ) + { + status &= 0xFD; // Datarate KO + } + // Verify tx power + if( RegionCommonValueInRange( linkAdrParams.TxPower, CN470_MAX_TX_POWER, CN470_MIN_TX_POWER ) == 0 ) + { + // Verify if the maximum TX power is exceeded + if( CN470_MAX_TX_POWER > linkAdrParams.TxPower ) + { // Apply maximum TX power. Accept TX power. + linkAdrParams.TxPower = CN470_MAX_TX_POWER; + } + else + { + status &= 0xFB; // TxPower KO + } + } + // Update channelsMask if everything is correct + if( status == 0x07 ) + { + if( linkAdrParams.NbRep == 0 ) + { // Value of 0 is not allowed, revert to default. + linkAdrParams.NbRep = 1; + } + + // Copy Mask + RegionCommonChanMaskCopy( ChannelsMask, channelsMask, 6 ); + } + //printf("status:%d\r\n",status); + // Update status variables + *drOut = linkAdrParams.Datarate; + *txPowOut = linkAdrParams.TxPower; + *nbRepOut = linkAdrParams.NbRep; + *nbBytesParsed = bytesProcessed; + + return status; +} + +uint8_t RegionCN470RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ) +{ + uint8_t status = 0x07; + uint32_t freq = rxParamSetupReq->Frequency; + + // Verify radio frequency + if( ( Radio.CheckRfFrequency( freq ) == false ) || + ( freq < CN470_FIRST_RX1_CHANNEL ) || + ( freq > CN470_LAST_RX1_CHANNEL ) || + ( ( ( freq - ( uint32_t ) CN470_FIRST_RX1_CHANNEL ) % ( uint32_t ) CN470_STEPWIDTH_RX1_CHANNEL ) != 0 ) ) + { + status &= 0xFE; // Channel frequency KO + } + + // Verify datarate + if( RegionCommonValueInRange( rxParamSetupReq->Datarate, CN470_RX_MIN_DATARATE, CN470_RX_MAX_DATARATE ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify datarate offset + if( RegionCommonValueInRange( rxParamSetupReq->DrOffset, CN470_MIN_RX1_DR_OFFSET, CN470_MAX_RX1_DR_OFFSET ) == false ) + { + status &= 0xFB; // Rx1DrOffset range KO + } + + return status; +} + +uint8_t RegionCN470NewChannelReq( NewChannelReqParams_t* newChannelReq ) +{ + // Datarate and frequency KO + return 0; +} + +int8_t RegionCN470TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ) +{ + return -1; +} + +uint8_t RegionCN470DlChannelReq( DlChannelReqParams_t* dlChannelReq ) +{ + return 0; +} + +int8_t RegionCN470AlternateDr( AlternateDrParams_t* alternateDr ) +{ + int8_t datarate = 0; + + if( ( alternateDr->NbTrials % 48 ) == 0 ) + { + datarate = DR_0; + } + else if( ( alternateDr->NbTrials % 32 ) == 0 ) + { + datarate = DR_1; + } + else if( ( alternateDr->NbTrials % 24 ) == 0 ) + { + datarate = DR_2; + } + else if( ( alternateDr->NbTrials % 16 ) == 0 ) + { + datarate = DR_3; + } + else if( ( alternateDr->NbTrials % 8 ) == 0 ) + { + datarate = DR_4; + } + else + { + datarate = DR_5; + } + return datarate; +} + +void RegionCN470CalcBackOff( CalcBackOffParams_t* calcBackOff ) +{ + uint8_t channel = calcBackOff->Channel; + uint16_t joinDutyCycle = 0; + + if( calcBackOff->Joined == false ) + { + // Get the join duty cycle + joinDutyCycle = RegionCommonGetJoinDc( calcBackOff->ElapsedTime ); + // Apply band time-off. + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * joinDutyCycle - calcBackOff->TxTimeOnAir; + } + else + { + Bands[Channels[channel].Band].TimeOff = 0; + } +} + +bool RegionCN470NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTx = 0; + uint8_t enabledChannels[CN470_MAX_NB_CHANNELS] = { 0 }; + TimerTime_t nextTxDelay = 0; + + // Count 125kHz channels + if( RegionCommonCountChannels( ChannelsMask, 0, 6 ) == 0 ) + { // Reactivate default channels + ChannelsMask[0] = 0xFFFF; + ChannelsMask[1] = 0xFFFF; + ChannelsMask[2] = 0xFFFF; + ChannelsMask[3] = 0xFFFF; + ChannelsMask[4] = 0xFFFF; + ChannelsMask[5] = 0xFFFF; + } + + if( nextChanParams->AggrTimeOff <= TimerGetElapsedTime( nextChanParams->LastAggrTx ) ) + { + // Reset Aggregated time off + *aggregatedTimeOff = 0; + + // Update bands Time OFF + nextTxDelay = RegionCommonUpdateBandTimeOff( nextChanParams->Joined, nextChanParams->DutyCycleEnabled, Bands, CN470_MAX_NB_BANDS ); + + // Search how many channels are enabled + nbEnabledChannels = CountNbOfEnabledChannels( nextChanParams->Datarate, + ChannelsMask, Channels, + Bands, enabledChannels, &delayTx ); + } + else + { + delayTx++; + nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx ); + } + + if( nbEnabledChannels > 0 ) + { + // We found a valid channel + *channel = enabledChannels[randr( 0, nbEnabledChannels - 1 )]; + + *time = 0; + return true; + } + else + { + if( delayTx > 0 ) + { + // Delay transmission due to AggregatedTimeOff or to a band time off + *time = nextTxDelay; + return true; + } + // Datarate not supported by any channel + *time = 0; + return false; + } +} + +LoRaMacStatus_t RegionCN470ChannelAdd( ChannelAddParams_t* channelAdd ) +{ + return LORAMAC_STATUS_PARAMETER_INVALID; +} + +bool RegionCN470ChannelsRemove( ChannelRemoveParams_t* channelRemove ) +{ + return LORAMAC_STATUS_PARAMETER_INVALID; +} + +void RegionCN470SetContinuousWave( ContinuousWaveParams_t* continuousWave ) +{ + int8_t txPowerLimited = LimitTxPower( continuousWave->TxPower, Bands[Channels[continuousWave->Channel].Band].TxMaxPower, continuousWave->Datarate, ChannelsMask ); + int8_t phyTxPower = 0; + uint32_t frequency = Channels[continuousWave->Channel].Frequency; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, continuousWave->MaxEirp, continuousWave->AntennaGain ); + + Radio.SetTxContinuousWave( frequency, phyTxPower, continuousWave->Timeout ); +} + +uint8_t RegionCN470ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +{ + int8_t datarate = dr - drOffset; + + if( datarate < 0 ) + { + datarate = DR_0; + } + return datarate; +} + +void RegionCN470RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ) +{ + RegionCommonRxBeaconSetupParams_t regionCommonRxBeaconSetup; + + regionCommonRxBeaconSetup.Datarates = DataratesCN470; + regionCommonRxBeaconSetup.Frequency = rxBeaconSetup->Frequency; + regionCommonRxBeaconSetup.BeaconSize = CN470_BEACON_SIZE; + regionCommonRxBeaconSetup.BeaconDatarate = CN470_BEACON_CHANNEL_DR; + regionCommonRxBeaconSetup.BeaconChannelBW = CN470_BEACON_CHANNEL_BW; + regionCommonRxBeaconSetup.RxTime = rxBeaconSetup->RxTime; + regionCommonRxBeaconSetup.SymbolTimeout = rxBeaconSetup->SymbolTimeout; + + RegionCommonRxBeaconSetup( ®ionCommonRxBeaconSetup ); + + // Store downlink datarate + *outDr = CN470_BEACON_CHANNEL_DR; +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN470.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN470.h new file mode 100644 index 00000000..61bf1a2c --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN470.h @@ -0,0 +1,497 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file RegionCN470.h + * + * \brief Region definition for CN470 + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGIONCN470 Region CN470 + * Implementation according to LoRaWAN Specification v1.0.2. + * \{ + */ +#ifndef __REGION_CN470_H__ +#define __REGION_CN470_H__ + +#include "LoRaMac.h" + +/*! + * LoRaMac maximum number of channels + */ +#define CN470_MAX_NB_CHANNELS 96 + +/*! + * Minimal datarate that can be used by the node + */ +#define CN470_TX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define CN470_TX_MAX_DATARATE DR_5 + +/*! + * Minimal datarate that can be used by the node + */ +#define CN470_RX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define CN470_RX_MAX_DATARATE DR_5 + +/*! + * Default datarate used by the node + */ +#define CN470_DEFAULT_DATARATE DR_0 + +/*! + * Minimal Rx1 receive datarate offset + */ +#define CN470_MIN_RX1_DR_OFFSET 0 + +/*! + * Maximal Rx1 receive datarate offset + */ +#define CN470_MAX_RX1_DR_OFFSET 3 + +/*! + * Default Rx1 receive datarate offset + */ +#define CN470_DEFAULT_RX1_DR_OFFSET 0 + +/*! + * Minimal Tx output power that can be used by the node + */ +#define CN470_MIN_TX_POWER TX_POWER_7 + +/*! + * Maximal Tx output power that can be used by the node + */ +#define CN470_MAX_TX_POWER TX_POWER_0 + +/*! + * Default Tx output power used by the node + */ +#define CN470_DEFAULT_TX_POWER TX_POWER_0 + +/*! + * Default Max EIRP + */ +#define CN470_DEFAULT_MAX_EIRP 19.15f + +/*! + * Default antenna gain + */ +#define CN470_DEFAULT_ANTENNA_GAIN 2.15f + +/*! + * ADR Ack limit + */ +#define CN470_ADR_ACK_LIMIT 64 + +/*! + * ADR Ack delay + */ +#define CN470_ADR_ACK_DELAY 32 + +/*! + * Enabled or disabled the duty cycle + */ +#define CN470_DUTY_CYCLE_ENABLED 0 + +/*! + * Maximum RX window duration + */ +#define CN470_MAX_RX_WINDOW 3000 + +/*! + * Receive delay 1 + */ +#define CN470_RECEIVE_DELAY1 1000 + +/*! + * Receive delay 2 + */ +#define CN470_RECEIVE_DELAY2 2000 + +/*! + * Join accept delay 1 + */ +#define CN470_JOIN_ACCEPT_DELAY1 5000 + +/*! + * Join accept delay 2 + */ +#define CN470_JOIN_ACCEPT_DELAY2 6000 + +/*! + * Maximum frame counter gap + */ +#define CN470_MAX_FCNT_GAP 16384 + +/*! + * Ack timeout + */ +#define CN470_ACKTIMEOUT 2000 + +/*! + * Random ack timeout limits + */ +#define CN470_ACK_TIMEOUT_RND 1000 + +/*! + * Second reception window channel frequency definition. + */ +#define CN470_RX_WND_2_FREQ 505300000 + +/*! + * Second reception window channel datarate definition. + */ +#define CN470_RX_WND_2_DR DR_0 + +/* + * CLASS B + */ +/*! + * Beacon frequency + */ +#define CN470_BEACON_CHANNEL_FREQ 508300000 + +/*! + * Beacon frequency channel stepwidth + */ +#define CN470_BEACON_CHANNEL_STEPWIDTH 200000 + +/*! + * Number of possible beacon channels + */ +#define CN470_BEACON_NB_CHANNELS 8 + +/*! + * Payload size of a beacon frame + */ +#define CN470_BEACON_SIZE 19 + +/*! + * Size of RFU 1 field + */ +#define CN470_RFU1_SIZE 3 + +/*! + * Size of RFU 2 field + */ +#define CN470_RFU2_SIZE 1 + +/*! + * Datarate of the beacon channel + */ +#define CN470_BEACON_CHANNEL_DR DR_2 + +/*! + * Bandwith of the beacon channel + */ +#define CN470_BEACON_CHANNEL_BW 0 + +/*! + * LoRaMac maximum number of bands + */ +#define CN470_MAX_NB_BANDS 1 + +/*! + * Band 0 definition + * { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define CN470_BAND0 { 1, CN470_MAX_TX_POWER, 0, 0 } // 100.0 % + +/*! + * Defines the first channel for RX window 1 for CN470 band + */ +#define CN470_FIRST_RX1_CHANNEL ( (uint32_t) 500.3e6 ) + +/*! + * Defines the last channel for RX window 1 for CN470 band + */ +#define CN470_LAST_RX1_CHANNEL ( (uint32_t) 509.7e6 ) + +/*! + * Defines the step width of the channels for RX window 1 + */ +#define CN470_STEPWIDTH_RX1_CHANNEL ( (uint32_t) 200e3 ) + +/*! + * Data rates table definition + */ +static const uint8_t DataratesCN470[] = { 12, 11, 10, 9, 8, 7 }; + +/*! + * Bandwidths table definition in Hz + */ +static const uint32_t BandwidthsCN470[] = { 125e3, 125e3, 125e3, 125e3, 125e3, 125e3 }; + +/*! + * Maximum payload with respect to the datarate index. Cannot operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateCN470[] = { 51, 51, 51, 115, 222, 222 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateRepeaterCN470[] = { 51, 51, 51, 115, 222, 222 }; + +/*! + * \brief The function gets a value of a specific phy attribute. + * + * \param [IN] getPhy Pointer to the function parameters. + * + * \retval Returns a structure containing the PHY parameter. + */ +PhyParam_t RegionCN470GetPhyParam( GetPhyParams_t* getPhy ); + +/*! + * \brief Updates the last TX done parameters of the current channel. + * + * \param [IN] txDone Pointer to the function parameters. + */ +void RegionCN470SetBandTxDone( SetBandTxDoneParams_t* txDone ); + +/*! + * \brief Initializes the channels masks and the channels. + * + * \param [IN] type Sets the initialization type. + */ +void RegionCN470InitDefaults( InitType_t type ); + +/*! + * \brief Verifies a parameter. + * + * \param [IN] verify Pointer to the function parameters. + * + * \param [IN] type Sets the initialization type. + * + * \retval Returns true, if the parameter is valid. + */ +bool RegionCN470Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ); + +/*! + * \brief The function parses the input buffer and sets up the channels of the + * CF list. + * + * \param [IN] applyCFList Pointer to the function parameters. + */ +void RegionCN470ApplyCFList( ApplyCFListParams_t* applyCFList ); + +/*! + * \brief Sets a channels mask. + * + * \param [IN] chanMaskSet Pointer to the function parameters. + * + * \retval Returns true, if the channels mask could be set. + */ +bool RegionCN470ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ); + +/*! + * \brief Calculates the next datarate to set, when ADR is on or off. + * + * \param [IN] adrNext Pointer to the function parameters. + * + * \param [OUT] drOut The calculated datarate for the next TX. + * + * \param [OUT] txPowOut The TX power for the next TX. + * + * \param [OUT] adrAckCounter The calculated ADR acknowledgement counter. + * + * \retval Returns true, if an ADR request should be performed. + */ +bool RegionCN470AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ); + +/*! + * Computes the Rx window timeout and offset. + * + * \param [IN] datarate Rx window datarate index to be used + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms + * interval around RxOffset + * + * \param [OUT]rxConfigParams Returns updated WindowTimeout and WindowOffset fields. + */ +void RegionCN470ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ); + +/*! + * \brief Configuration of the RX windows. + * + * \param [IN] rxConfig Pointer to the function parameters. + * + * \param [OUT] datarate The datarate index which was set. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionCN470RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ); + +/*! + * \brief TX configuration. + * + * \param [IN] txConfig Pointer to the function parameters. + * + * \param [OUT] txPower The tx power index which was set. + * + * \param [OUT] txTimeOnAir The time-on-air of the frame. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionCN470TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ); + +/*! + * \brief The function processes a Link ADR Request. + * + * \param [IN] linkAdrReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionCN470LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ); + +/*! + * \brief The function processes a RX Parameter Setup Request. + * + * \param [IN] rxParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionCN470RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ); + +/*! + * \brief The function processes a Channel Request. + * + * \param [IN] newChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionCN470NewChannelReq( NewChannelReqParams_t* newChannelReq ); + +/*! + * \brief The function processes a TX ParamSetup Request. + * + * \param [IN] txParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + * Returns -1, if the functionality is not implemented. In this case, the end node + * shall not process the command. + */ +int8_t RegionCN470TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ); + +/*! + * \brief The function processes a DlChannel Request. + * + * \param [IN] dlChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionCN470DlChannelReq( DlChannelReqParams_t* dlChannelReq ); + +/* + * \brief Alternates the datarate of the channel for the join request. + * + * \param [IN] alternateDr Pointer to the function parameters. + * + * \retval Datarate to apply. + */ +int8_t RegionCN470AlternateDr( AlternateDrParams_t* alternateDr ); + +/*! + * \brief Calculates the back-off time. + * + * \param [IN] calcBackOff Pointer to the function parameters. + */ +void RegionCN470CalcBackOff( CalcBackOffParams_t* calcBackOff ); + +/*! + * \brief Searches and set the next random available channel + * + * \param [OUT] channel Next channel to use for TX. + * + * \param [OUT] time Time to wait for the next transmission according to the duty + * cycle. + * + * \param [OUT] aggregatedTimeOff Updates the aggregated time off. + * + * \retval Function status [1: OK, 0: Unable to find a channel on the current datarate] + */ +bool RegionCN470NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ); + +/*! + * \brief Adds a channel. + * + * \param [IN] channelAdd Pointer to the function parameters. + * + * \retval Status of the operation. + */ +LoRaMacStatus_t RegionCN470ChannelAdd( ChannelAddParams_t* channelAdd ); + +/*! + * \brief Removes a channel. + * + * \param [IN] channelRemove Pointer to the function parameters. + * + * \retval Returns true, if the channel was removed successfully. + */ +bool RegionCN470ChannelsRemove( ChannelRemoveParams_t* channelRemove ); + +/*! + * \brief Sets the radio into continuous wave mode. + * + * \param [IN] continuousWave Pointer to the function parameters. + */ +void RegionCN470SetContinuousWave( ContinuousWaveParams_t* continuousWave ); + +/*! + * \brief Computes new datarate according to the given offset + * + * \param [IN] downlinkDwellTime Downlink dwell time configuration. 0: No limit, 1: 400ms + * + * \param [IN] dr Current datarate + * + * \param [IN] drOffset Offset to be applied + * + * \retval newDr Computed datarate. + */ +uint8_t RegionCN470ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ); + +/*! + * \brief Sets the radio into beacon reception mode + * + * \param [IN] rxBeaconSetup Pointer to the function parameters + */ + void RegionCN470RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ); + +/*! \} defgroup REGIONCN470 */ + +#endif // __REGION_CN470_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN779.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN779.c new file mode 100644 index 00000000..020fe8f4 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN779.c @@ -0,0 +1,1098 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC region CN779 implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include +#include + +#include "radio.h" +//#include "timer.h" +#include "timeServer.h" +#include "LoRaMac.h" + +#include "utilities.h" + +#include "Region.h" +#include "RegionCommon.h" +#include "RegionCN779.h" +#include "debug.h" + +// Definitions +#define CHANNELS_MASK_SIZE 1 + +// Global attributes +/*! + * LoRaMAC channels + */ +static ChannelParams_t Channels[CN779_MAX_NB_CHANNELS]; + +/*! + * LoRaMac bands + */ +static Band_t Bands[CN779_MAX_NB_BANDS] = +{ + CN779_BAND0 +}; + +/*! + * LoRaMac channels mask + */ +static uint16_t ChannelsMask[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels default mask + */ +static uint16_t ChannelsDefaultMask[CHANNELS_MASK_SIZE]; + +// Static functions +static int8_t GetNextLowerTxDr( int8_t dr, int8_t minDr ) +{ + uint8_t nextLowerDr = 0; + + if( dr == minDr ) + { + nextLowerDr = minDr; + } + else + { + nextLowerDr = dr - 1; + } + return nextLowerDr; +} + +static uint32_t GetBandwidth( uint32_t drIndex ) +{ + switch( BandwidthsCN779[drIndex] ) + { + default: + case 125000: + return 0; + case 250000: + return 1; + case 500000: + return 2; + } +} + +static int8_t LimitTxPower( int8_t txPower, int8_t maxBandTxPower, int8_t datarate, uint16_t* channelsMask ) +{ + int8_t txPowerResult = txPower; + + // Limit tx power to the band max + txPowerResult = MAX( txPower, maxBandTxPower ); + + return txPowerResult; +} + +static bool VerifyTxFreq( uint32_t freq ) +{ + // Check radio driver support + if( Radio.CheckRfFrequency( freq ) == false ) + { + return false; + } + + if( ( freq < 779500000 ) || ( freq > 786500000 ) ) + { + return false; + } + return true; +} + +static uint8_t CountNbOfEnabledChannels( bool joined, uint8_t datarate, uint16_t* channelsMask, ChannelParams_t* channels, Band_t* bands, uint8_t* enabledChannels, uint8_t* delayTx ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTransmission = 0; + + for( uint8_t i = 0, k = 0; i < CN779_MAX_NB_CHANNELS; i += 16, k++ ) + { + for( uint8_t j = 0; j < 16; j++ ) + { + if( ( channelsMask[k] & ( 1 << j ) ) != 0 ) + { + if( channels[i + j].Frequency == 0 ) + { // Check if the channel is enabled + continue; + } + if( joined == false ) + { + if( ( CN779_JOIN_CHANNELS & ( 1 << j ) ) == 0 ) + { + continue; + } + } + if( RegionCommonValueInRange( datarate, channels[i + j].DrRange.Fields.Min, + channels[i + j].DrRange.Fields.Max ) == false ) + { // Check if the current channel selection supports the given datarate + continue; + } + if( bands[channels[i + j].Band].TimeOff > 0 ) + { // Check if the band is available for transmission + delayTransmission++; + continue; + } + enabledChannels[nbEnabledChannels++] = i + j; + } + } + } + + *delayTx = delayTransmission; + return nbEnabledChannels; +} + +PhyParam_t RegionCN779GetPhyParam( GetPhyParams_t* getPhy ) +{ + PhyParam_t phyParam = { 0 }; + + switch( getPhy->Attribute ) + { + case PHY_MIN_RX_DR: + { + phyParam.Value = CN779_RX_MIN_DATARATE; + break; + } + case PHY_MIN_TX_DR: + { + phyParam.Value = CN779_TX_MIN_DATARATE; + break; + } + case PHY_DEF_TX_DR: + { + phyParam.Value = CN779_DEFAULT_DATARATE; + break; + } + case PHY_NEXT_LOWER_TX_DR: + { + phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, CN779_TX_MIN_DATARATE ); + break; + } + case PHY_DEF_TX_POWER: + { + phyParam.Value = CN779_DEFAULT_TX_POWER; + break; + } + case PHY_MAX_PAYLOAD: + { + phyParam.Value = MaxPayloadOfDatarateCN779[getPhy->Datarate]; + break; + } + case PHY_MAX_PAYLOAD_REPEATER: + { + phyParam.Value = MaxPayloadOfDatarateRepeaterCN779[getPhy->Datarate]; + break; + } + case PHY_DUTY_CYCLE: + { + phyParam.Value = CN779_DUTY_CYCLE_ENABLED; + break; + } + case PHY_MAX_RX_WINDOW: + { + phyParam.Value = CN779_MAX_RX_WINDOW; + break; + } + case PHY_RECEIVE_DELAY1: + { + phyParam.Value = CN779_RECEIVE_DELAY1; + break; + } + case PHY_RECEIVE_DELAY2: + { + phyParam.Value = CN779_RECEIVE_DELAY2; + break; + } + case PHY_JOIN_ACCEPT_DELAY1: + { + phyParam.Value = CN779_JOIN_ACCEPT_DELAY1; + break; + } + case PHY_JOIN_ACCEPT_DELAY2: + { + phyParam.Value = CN779_JOIN_ACCEPT_DELAY2; + break; + } + case PHY_MAX_FCNT_GAP: + { + phyParam.Value = CN779_MAX_FCNT_GAP; + break; + } + case PHY_ACK_TIMEOUT: + { + phyParam.Value = ( CN779_ACKTIMEOUT + randr( -CN779_ACK_TIMEOUT_RND, CN779_ACK_TIMEOUT_RND ) ); + break; + } + case PHY_DEF_DR1_OFFSET: + { + phyParam.Value = CN779_DEFAULT_RX1_DR_OFFSET; + break; + } + case PHY_DEF_RX2_FREQUENCY: + { + phyParam.Value = CN779_RX_WND_2_FREQ; + break; + } + case PHY_DEF_RX2_DR: + { + phyParam.Value = CN779_RX_WND_2_DR; + break; + } + case PHY_CHANNELS_MASK: + { + phyParam.ChannelsMask = ChannelsMask; + break; + } + case PHY_CHANNELS_DEFAULT_MASK: + { + phyParam.ChannelsMask = ChannelsDefaultMask; + break; + } + case PHY_MAX_NB_CHANNELS: + { + phyParam.Value = CN779_MAX_NB_CHANNELS; + break; + } + case PHY_CHANNELS: + { + phyParam.Channels = Channels; + break; + } + case PHY_DEF_UPLINK_DWELL_TIME: + case PHY_DEF_DOWNLINK_DWELL_TIME: + { + phyParam.Value = 0; + break; + } + case PHY_DEF_MAX_EIRP: + { + phyParam.fValue = CN779_DEFAULT_MAX_EIRP; + break; + } + case PHY_DEF_ANTENNA_GAIN: + { + phyParam.fValue = CN779_DEFAULT_ANTENNA_GAIN; + break; + } + case PHY_NB_JOIN_TRIALS: + case PHY_DEF_NB_JOIN_TRIALS: + { + phyParam.Value = 48; + break; + } + case PHY_BEACON_CHANNEL_FREQ: + { + phyParam.Value = CN779_BEACON_CHANNEL_FREQ; + break; + } + case PHY_BEACON_FORMAT: + { + phyParam.BeaconFormat.BeaconSize = CN779_BEACON_SIZE; + phyParam.BeaconFormat.Rfu1Size = CN779_RFU1_SIZE; + phyParam.BeaconFormat.Rfu2Size = CN779_RFU2_SIZE; + break; + } + case PHY_BEACON_CHANNEL_DR: + { + phyParam.Value = CN779_BEACON_CHANNEL_DR; + break; + } + default: + { + break; + } + } + + return phyParam; +} + +void RegionCN779SetBandTxDone( SetBandTxDoneParams_t* txDone ) +{ + RegionCommonSetBandTxDone( txDone->Joined, &Bands[Channels[txDone->Channel].Band], txDone->LastTxDoneTime ); +} + +void RegionCN779InitDefaults( InitType_t type ) +{ + switch( type ) + { + case INIT_TYPE_INIT: + { + // Channels + Channels[0] = ( ChannelParams_t ) CN779_LC1; + Channels[1] = ( ChannelParams_t ) CN779_LC2; + Channels[2] = ( ChannelParams_t ) CN779_LC3; + + // Initialize the channels default mask + ChannelsDefaultMask[0] = LC( 1 ) + LC( 2 ) + LC( 3 ); + // Update the channels mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 1 ); + break; + } + case INIT_TYPE_RESTORE: + { + // Restore channels default mask + ChannelsMask[0] |= ChannelsDefaultMask[0]; + break; + } + default: + { + break; + } + } +} + +bool RegionCN779Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ) +{ + switch( phyAttribute ) + { + case PHY_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, CN779_TX_MIN_DATARATE, CN779_TX_MAX_DATARATE ); + } + case PHY_DEF_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, DR_0, DR_5 ); + } + case PHY_RX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, CN779_RX_MIN_DATARATE, CN779_RX_MAX_DATARATE ); + } + case PHY_DEF_TX_POWER: + case PHY_TX_POWER: + { + // Remark: switched min and max! + return RegionCommonValueInRange( verify->TxPower, CN779_MAX_TX_POWER, CN779_MIN_TX_POWER ); + } + case PHY_DUTY_CYCLE: + { + return CN779_DUTY_CYCLE_ENABLED; + } + case PHY_NB_JOIN_TRIALS: + { + if( verify->NbJoinTrials < 48 ) + { + return false; + } + break; + } + default: + return false; + } + return true; +} + +void RegionCN779ApplyCFList( ApplyCFListParams_t* applyCFList ) +{ + ChannelParams_t newChannel; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + // Setup default datarate range + newChannel.DrRange.Value = ( DR_5 << 4 ) | DR_0; + + // Size of the optional CF list + if( applyCFList->Size != 16 ) + { + return; + } + + // Last byte is RFU, don't take it into account + for( uint8_t i = 0, chanIdx = CN779_NUMB_DEFAULT_CHANNELS; chanIdx < CN779_MAX_NB_CHANNELS; i+=3, chanIdx++ ) + { + if( chanIdx < ( CN779_NUMB_CHANNELS_CF_LIST + CN779_NUMB_DEFAULT_CHANNELS ) ) + { + // Channel frequency + newChannel.Frequency = (uint32_t) applyCFList->Payload[i]; + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 1] << 8 ); + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 2] << 16 ); + newChannel.Frequency *= 100; + + // Initialize alternative frequency to 0 + newChannel.Rx1Frequency = 0; + } + else + { + newChannel.Frequency = 0; + newChannel.DrRange.Value = 0; + newChannel.Rx1Frequency = 0; + } + + if( newChannel.Frequency != 0 ) + { + channelAdd.NewChannel = &newChannel; + channelAdd.ChannelId = chanIdx; + + // Try to add all channels + RegionCN779ChannelAdd( &channelAdd ); + } + else + { + channelRemove.ChannelId = chanIdx; + + RegionCN779ChannelsRemove( &channelRemove ); + } + } +} + +bool RegionCN779ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ) +{ + switch( chanMaskSet->ChannelsMaskType ) + { + case CHANNELS_MASK: + { + RegionCommonChanMaskCopy( ChannelsMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + case CHANNELS_DEFAULT_MASK: + { + RegionCommonChanMaskCopy( ChannelsDefaultMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + default: + return false; + } + return true; +} + +bool RegionCN779AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ) +{ + bool adrAckReq = false; + int8_t datarate = adrNext->Datarate; + int8_t txPower = adrNext->TxPower; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + // Report back the adr ack counter + *adrAckCounter = adrNext->AdrAckCounter; + + if( adrNext->AdrEnabled == true ) + { + if( datarate == CN779_TX_MIN_DATARATE ) + { + *adrAckCounter = 0; + adrAckReq = false; + } + else + { + if( adrNext->AdrAckCounter >= CN779_ADR_ACK_LIMIT ) + { + adrAckReq = true; + txPower = CN779_MAX_TX_POWER; + } + else + { + adrAckReq = false; + } + if( adrNext->AdrAckCounter >= ( CN779_ADR_ACK_LIMIT + CN779_ADR_ACK_DELAY ) ) + { + if( ( adrNext->AdrAckCounter % CN779_ADR_ACK_DELAY ) == 1 ) + { + // Decrease the datarate + getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + getPhy.Datarate = datarate; + getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + phyParam = RegionCN779GetPhyParam( &getPhy ); + datarate = phyParam.Value; + + if( datarate == CN779_TX_MIN_DATARATE ) + { + // We must set adrAckReq to false as soon as we reach the lowest datarate + adrAckReq = false; + if( adrNext->UpdateChanMask == true ) + { + // Re-enable default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + } + } + } + } + } + } + + *drOut = datarate; + *txPowOut = txPower; + return adrAckReq; +} + +void RegionCN779ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ) +{ + double tSymbol = 0.0; + uint32_t radioWakeUpTime; + + rxConfigParams->Datarate = datarate; + rxConfigParams->Bandwidth = GetBandwidth( datarate ); + + if( datarate == DR_7 ) + { // FSK + tSymbol = RegionCommonComputeSymbolTimeFsk( DataratesCN779[datarate] ); + } + else + { // LoRa + tSymbol = RegionCommonComputeSymbolTimeLoRa( DataratesCN779[datarate], BandwidthsCN779[datarate] ); + } + + radioWakeUpTime = Radio.GetWakeupTime( ); + RegionCommonComputeRxWindowParameters( tSymbol, minRxSymbols, rxError, radioWakeUpTime, &rxConfigParams->WindowTimeout, &rxConfigParams->WindowOffset ); +} + +bool RegionCN779RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ) +{ + RadioModems_t modem; + int8_t dr = rxConfig->Datarate; + uint8_t maxPayload = 0; + int8_t phyDr = 0; + uint32_t frequency = rxConfig->Frequency; + + if( Radio.GetStatus( ) != RF_IDLE ) + { + return false; + } + + if( rxConfig->RxSlot == RX_SLOT_WIN_1 ) + { + // Apply window 1 frequency + frequency = Channels[rxConfig->Channel].Frequency; + // Apply the alternative RX 1 window frequency, if it is available + if( Channels[rxConfig->Channel].Rx1Frequency != 0 ) + { + frequency = Channels[rxConfig->Channel].Rx1Frequency; + } + } + + // Read the physical datarate from the datarates table + phyDr = DataratesCN779[dr]; + + Radio.SetChannel( frequency ); + + // Radio configuration + if( dr == DR_7 ) + { + modem = MODEM_FSK; + Radio.SetRxConfig( modem, 50000, phyDr * 1000, 0, 83333, 5, rxConfig->WindowTimeout, false, 0, true, 0, 0, false, rxConfig->RxContinuous ); + } + else + { + modem = MODEM_LORA; + Radio.SetRxConfig( modem, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, false, 0, false, 0, 0, true, rxConfig->RxContinuous ); + } + + if( rxConfig->RepeaterSupport == true ) + { + maxPayload = MaxPayloadOfDatarateRepeaterCN779[dr]; + } + else + { + maxPayload = MaxPayloadOfDatarateCN779[dr]; + } + Radio.SetMaxPayloadLength( modem, maxPayload + LORA_MAC_FRMPAYLOAD_OVERHEAD ); + DBG_PRINTF("RX on freq %u Hz at DR %d\n\r", (unsigned int)frequency, dr); + + *datarate = (uint8_t) dr; + return true; +} + +bool RegionCN779TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) +{ + RadioModems_t modem; + int8_t phyDr = DataratesCN779[txConfig->Datarate]; + int8_t txPowerLimited = LimitTxPower( txConfig->TxPower, Bands[Channels[txConfig->Channel].Band].TxMaxPower, txConfig->Datarate, ChannelsMask ); + uint32_t bandwidth = GetBandwidth( txConfig->Datarate ); + int8_t phyTxPower = 0; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, txConfig->MaxEirp, txConfig->AntennaGain ); + + // Setup the radio frequency + Radio.SetChannel( Channels[txConfig->Channel].Frequency ); + + if( txConfig->Datarate == DR_7 ) + { // High Speed FSK channel + modem = MODEM_FSK; + Radio.SetTxConfig( modem, phyTxPower, 25000, bandwidth, phyDr * 1000, 0, 5, false, true, 0, 0, false, 3000 ); + } + else + { + modem = MODEM_LORA; + Radio.SetTxConfig( modem, phyTxPower, 0, bandwidth, phyDr, 1, 8, false, true, 0, 0, false, 3e3 ); + } + DBG_PRINTF("TX on freq %u Hz at DR %d\n\r", (unsigned int)Channels[txConfig->Channel].Frequency, txConfig->Datarate); + // Setup maximum payload lenght of the radio driver + Radio.SetMaxPayloadLength( modem, txConfig->PktLen ); + // Get the time-on-air of the next tx frame + *txTimeOnAir = Radio.TimeOnAir( modem, txConfig->PktLen ); + + *txPower = txConfig->TxPower; + return true; +} + +uint8_t RegionCN779LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ) +{ + uint8_t status = 0x07; + LinkAdrParams_t linkAdrParams; + uint8_t nextIndex = 0; + uint8_t bytesProcessed = 0; + uint16_t chMask = 0; + + while( bytesProcessed < linkAdrReq->PayloadSize ) + { + // Get ADR request parameters + nextIndex = RegionCommonParseLinkAdrReq( &( linkAdrReq->Payload[bytesProcessed] ), &linkAdrParams ); + + if( nextIndex == 0 ) + break; // break loop, since no more request has been found + + // Update bytes processed + bytesProcessed += nextIndex; + + // Revert status, as we only check the last ADR request for the channel mask KO + status = 0x07; + + // Setup temporary channels mask + chMask = linkAdrParams.ChMask; + + // Verify channels mask + if( ( linkAdrParams.ChMaskCtrl == 0 ) && ( chMask == 0 ) ) + { + status &= 0xFE; // Channel mask KO + } + else if( ( ( linkAdrParams.ChMaskCtrl >= 1 ) && ( linkAdrParams.ChMaskCtrl <= 5 )) || + ( linkAdrParams.ChMaskCtrl >= 7 ) ) + { + // RFU + status &= 0xFE; // Channel mask KO + } + else + { + for( uint8_t i = 0; i < CN779_MAX_NB_CHANNELS; i++ ) + { + if( linkAdrParams.ChMaskCtrl == 6 ) + { + if( Channels[i].Frequency != 0 ) + { + chMask |= 1 << i; + } + } + else + { + if( ( ( chMask & ( 1 << i ) ) != 0 ) && + ( Channels[i].Frequency == 0 ) ) + {// Trying to enable an undefined channel + status &= 0xFE; // Channel mask KO + } + } + } + } + } + + // Verify datarate + if( RegionCommonChanVerifyDr( CN779_MAX_NB_CHANNELS, &chMask, linkAdrParams.Datarate, CN779_TX_MIN_DATARATE, CN779_TX_MAX_DATARATE, Channels ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify tx power + if( RegionCommonValueInRange( linkAdrParams.TxPower, CN779_MAX_TX_POWER, CN779_MIN_TX_POWER ) == 0 ) + { + // Verify if the maximum TX power is exceeded + if( CN779_MAX_TX_POWER > linkAdrParams.TxPower ) + { // Apply maximum TX power. Accept TX power. + linkAdrParams.TxPower = CN779_MAX_TX_POWER; + } + else + { + status &= 0xFB; // TxPower KO + } + } + + // Update channelsMask if everything is correct + if( status == 0x07 ) + { + if( linkAdrParams.NbRep == 0 ) + { // Value of 0 is not allowed, revert to default. + linkAdrParams.NbRep = 1; + } + + // Set the channels mask to a default value + memset( ChannelsMask, 0, sizeof( ChannelsMask ) ); + // Update the channels mask + ChannelsMask[0] = chMask; + } + + // Update status variables + *drOut = linkAdrParams.Datarate; + *txPowOut = linkAdrParams.TxPower; + *nbRepOut = linkAdrParams.NbRep; + *nbBytesParsed = bytesProcessed; + + return status; +} + +uint8_t RegionCN779RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ) +{ + uint8_t status = 0x07; + + // Verify radio frequency + if( Radio.CheckRfFrequency( rxParamSetupReq->Frequency ) == false ) + { + status &= 0xFE; // Channel frequency KO + } + + // Verify datarate + if( RegionCommonValueInRange( rxParamSetupReq->Datarate, CN779_RX_MIN_DATARATE, CN779_RX_MAX_DATARATE ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify datarate offset + if( RegionCommonValueInRange( rxParamSetupReq->DrOffset, CN779_MIN_RX1_DR_OFFSET, CN779_MAX_RX1_DR_OFFSET ) == false ) + { + status &= 0xFB; // Rx1DrOffset range KO + } + + return status; +} + +uint8_t RegionCN779NewChannelReq( NewChannelReqParams_t* newChannelReq ) +{ + uint8_t status = 0x03; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + if( newChannelReq->NewChannel->Frequency == 0 ) + { + channelRemove.ChannelId = newChannelReq->ChannelId; + + // Remove + if( RegionCN779ChannelsRemove( &channelRemove ) == false ) + { + status &= 0xFC; + } + } + else + { + channelAdd.NewChannel = newChannelReq->NewChannel; + channelAdd.ChannelId = newChannelReq->ChannelId; + + switch( RegionCN779ChannelAdd( &channelAdd ) ) + { + case LORAMAC_STATUS_OK: + { + break; + } + case LORAMAC_STATUS_FREQUENCY_INVALID: + { + status &= 0xFE; + break; + } + case LORAMAC_STATUS_DATARATE_INVALID: + { + status &= 0xFD; + break; + } + case LORAMAC_STATUS_FREQ_AND_DR_INVALID: + { + status &= 0xFC; + break; + } + default: + { + status &= 0xFC; + break; + } + } + } + + return status; +} + +int8_t RegionCN779TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ) +{ + return -1; +} + +uint8_t RegionCN779DlChannelReq( DlChannelReqParams_t* dlChannelReq ) +{ + uint8_t status = 0x03; + + // Verify if the frequency is supported + if( VerifyTxFreq( dlChannelReq->Rx1Frequency ) == false ) + { + status &= 0xFE; + } + + // Verify if an uplink frequency exists + if( Channels[dlChannelReq->ChannelId].Frequency == 0 ) + { + status &= 0xFD; + } + + // Apply Rx1 frequency, if the status is OK + if( status == 0x03 ) + { + Channels[dlChannelReq->ChannelId].Rx1Frequency = dlChannelReq->Rx1Frequency; + } + + return status; +} + +int8_t RegionCN779AlternateDr( AlternateDrParams_t* alternateDr ) +{ + int8_t datarate = 0; + + if( ( alternateDr->NbTrials % 48 ) == 0 ) + { + datarate = DR_0; + } + else if( ( alternateDr->NbTrials % 32 ) == 0 ) + { + datarate = DR_1; + } + else if( ( alternateDr->NbTrials % 24 ) == 0 ) + { + datarate = DR_2; + } + else if( ( alternateDr->NbTrials % 16 ) == 0 ) + { + datarate = DR_3; + } + else if( ( alternateDr->NbTrials % 8 ) == 0 ) + { + datarate = DR_4; + } + else + { + datarate = DR_5; + } + return datarate; +} + +void RegionCN779CalcBackOff( CalcBackOffParams_t* calcBackOff ) +{ + uint8_t channel = calcBackOff->Channel; + uint16_t dutyCycle = Bands[Channels[channel].Band].DCycle; + uint16_t joinDutyCycle = 0; + + // Reset time-off to initial value. + Bands[Channels[channel].Band].TimeOff = 0; + + if( calcBackOff->Joined == false ) + { + // Get the join duty cycle + joinDutyCycle = RegionCommonGetJoinDc( calcBackOff->ElapsedTime ); + // Apply the most restricting duty cycle + dutyCycle = MAX( dutyCycle, joinDutyCycle ); + // Apply band time-off. + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + else + { + if( calcBackOff->DutyCycleEnabled == true ) + { + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + } +} + +bool RegionCN779NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTx = 0; + uint8_t enabledChannels[CN779_MAX_NB_CHANNELS] = { 0 }; + TimerTime_t nextTxDelay = 0; + + if( RegionCommonCountChannels( ChannelsMask, 0, 1 ) == 0 ) + { // Reactivate default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + } + + if( nextChanParams->AggrTimeOff <= TimerGetElapsedTime( nextChanParams->LastAggrTx ) ) + { + // Reset Aggregated time off + *aggregatedTimeOff = 0; + + // Update bands Time OFF + nextTxDelay = RegionCommonUpdateBandTimeOff( nextChanParams->Joined, nextChanParams->DutyCycleEnabled, Bands, CN779_MAX_NB_BANDS ); + + // Search how many channels are enabled + nbEnabledChannels = CountNbOfEnabledChannels( nextChanParams->Joined, nextChanParams->Datarate, + ChannelsMask, Channels, + Bands, enabledChannels, &delayTx ); + } + else + { + delayTx++; + nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx ); + } + + if( nbEnabledChannels > 0 ) + { + // We found a valid channel + *channel = enabledChannels[randr( 0, nbEnabledChannels - 1 )]; + + *time = 0; + return true; + } + else + { + if( delayTx > 0 ) + { + // Delay transmission due to AggregatedTimeOff or to a band time off + *time = nextTxDelay; + return true; + } + // Datarate not supported by any channel, restore defaults + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + *time = 0; + return false; + } +} + +LoRaMacStatus_t RegionCN779ChannelAdd( ChannelAddParams_t* channelAdd ) +{ + uint8_t band = 0; + bool drInvalid = false; + bool freqInvalid = false; + uint8_t id = channelAdd->ChannelId; + + if( id >= CN779_MAX_NB_CHANNELS ) + { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + + // Validate the datarate range + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Min, CN779_TX_MIN_DATARATE, CN779_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, CN779_TX_MIN_DATARATE, CN779_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( channelAdd->NewChannel->DrRange.Fields.Min > channelAdd->NewChannel->DrRange.Fields.Max ) + { + drInvalid = true; + } + + // Default channels don't accept all values + if( id < CN779_NUMB_DEFAULT_CHANNELS ) + { + // Validate the datarate range for min: must be DR_0 + if( channelAdd->NewChannel->DrRange.Fields.Min > DR_0 ) + { + drInvalid = true; + } + // Validate the datarate range for max: must be DR_5 <= Max <= TX_MAX_DATARATE + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, DR_5, CN779_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + // We are not allowed to change the frequency + if( channelAdd->NewChannel->Frequency != Channels[id].Frequency ) + { + freqInvalid = true; + } + } + + // Check frequency + if( freqInvalid == false ) + { + if( VerifyTxFreq( channelAdd->NewChannel->Frequency ) == false ) + { + freqInvalid = true; + } + } + + // Check status + if( ( drInvalid == true ) && ( freqInvalid == true ) ) + { + return LORAMAC_STATUS_FREQ_AND_DR_INVALID; + } + if( drInvalid == true ) + { + return LORAMAC_STATUS_DATARATE_INVALID; + } + if( freqInvalid == true ) + { + return LORAMAC_STATUS_FREQUENCY_INVALID; + } + + memcpy( &(Channels[id]), channelAdd->NewChannel, sizeof( Channels[id] ) ); + Channels[id].Band = band; + ChannelsMask[0] |= ( 1 << id ); + return LORAMAC_STATUS_OK; +} + +bool RegionCN779ChannelsRemove( ChannelRemoveParams_t* channelRemove ) +{ + uint8_t id = channelRemove->ChannelId; + + if( id < CN779_NUMB_DEFAULT_CHANNELS ) + { + return false; + } + + // Remove the channel from the list of channels + Channels[id] = ( ChannelParams_t ){ 0, 0, { 0 }, 0 }; + + return RegionCommonChanDisable( ChannelsMask, id, CN779_MAX_NB_CHANNELS ); +} + +void RegionCN779SetContinuousWave( ContinuousWaveParams_t* continuousWave ) +{ + int8_t txPowerLimited = LimitTxPower( continuousWave->TxPower, Bands[Channels[continuousWave->Channel].Band].TxMaxPower, continuousWave->Datarate, ChannelsMask ); + int8_t phyTxPower = 0; + uint32_t frequency = Channels[continuousWave->Channel].Frequency; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, continuousWave->MaxEirp, continuousWave->AntennaGain ); + + Radio.SetTxContinuousWave( frequency, phyTxPower, continuousWave->Timeout ); +} + +uint8_t RegionCN779ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +{ + int8_t datarate = dr - drOffset; + + if( datarate < 0 ) + { + datarate = DR_0; + } + return datarate; +} + +void RegionCN779RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ) +{ + RegionCommonRxBeaconSetupParams_t regionCommonRxBeaconSetup; + + regionCommonRxBeaconSetup.Datarates = DataratesCN779; + regionCommonRxBeaconSetup.Frequency = rxBeaconSetup->Frequency; + regionCommonRxBeaconSetup.BeaconSize = CN779_BEACON_SIZE; + regionCommonRxBeaconSetup.BeaconDatarate = CN779_BEACON_CHANNEL_DR; + regionCommonRxBeaconSetup.BeaconChannelBW = CN779_BEACON_CHANNEL_BW; + regionCommonRxBeaconSetup.RxTime = rxBeaconSetup->RxTime; + regionCommonRxBeaconSetup.SymbolTimeout = rxBeaconSetup->SymbolTimeout; + + RegionCommonRxBeaconSetup( ®ionCommonRxBeaconSetup ); + + // Store downlink datarate + *outDr = CN779_BEACON_CHANNEL_DR; +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN779.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN779.h new file mode 100644 index 00000000..d6b227ac --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCN779.h @@ -0,0 +1,511 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file RegionCN779.h + * + * \brief Region definition for CN779 + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGIONCN779 Region CN779 + * Implementation according to LoRaWAN Specification v1.0.2. + * \{ + */ +#ifndef __REGION_CN779_H__ +#define __REGION_CN779_H__ + +#include "LoRaMac.h" + +/*! + * LoRaMac maximum number of channels + */ +#define CN779_MAX_NB_CHANNELS 16 + +/*! + * Number of default channels + */ +#define CN779_NUMB_DEFAULT_CHANNELS 3 + +/*! + * Number of channels to apply for the CF list + */ +#define CN779_NUMB_CHANNELS_CF_LIST 5 + +/*! + * Minimal datarate that can be used by the node + */ +#define CN779_TX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define CN779_TX_MAX_DATARATE DR_7 + +/*! + * Minimal datarate that can be used by the node + */ +#define CN779_RX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define CN779_RX_MAX_DATARATE DR_7 + +/*! + * Default datarate used by the node + */ +#define CN779_DEFAULT_DATARATE DR_0 + +/*! + * Minimal Rx1 receive datarate offset + */ +#define CN779_MIN_RX1_DR_OFFSET 0 + +/*! + * Maximal Rx1 receive datarate offset + */ +#define CN779_MAX_RX1_DR_OFFSET 5 + +/*! + * Default Rx1 receive datarate offset + */ +#define CN779_DEFAULT_RX1_DR_OFFSET 0 + +/*! + * Minimal Tx output power that can be used by the node + */ +#define CN779_MIN_TX_POWER TX_POWER_5 + +/*! + * Maximal Tx output power that can be used by the node + */ +#define CN779_MAX_TX_POWER TX_POWER_0 + +/*! + * Default Tx output power used by the node + */ +#define CN779_DEFAULT_TX_POWER TX_POWER_0 + +/*! + * Default Max EIRP + */ +#define CN779_DEFAULT_MAX_EIRP 12.15f + +/*! + * Default antenna gain + */ +#define CN779_DEFAULT_ANTENNA_GAIN 2.15f + +/*! + * ADR Ack limit + */ +#define CN779_ADR_ACK_LIMIT 64 + +/*! + * ADR Ack delay + */ +#define CN779_ADR_ACK_DELAY 32 + +/*! + * Enabled or disabled the duty cycle + */ +#define CN779_DUTY_CYCLE_ENABLED 1 + +/*! + * Maximum RX window duration + */ +#define CN779_MAX_RX_WINDOW 3000 + +/*! + * Receive delay 1 + */ +#define CN779_RECEIVE_DELAY1 1000 + +/*! + * Receive delay 2 + */ +#define CN779_RECEIVE_DELAY2 2000 + +/*! + * Join accept delay 1 + */ +#define CN779_JOIN_ACCEPT_DELAY1 5000 + +/*! + * Join accept delay 2 + */ +#define CN779_JOIN_ACCEPT_DELAY2 6000 + +/*! + * Maximum frame counter gap + */ +#define CN779_MAX_FCNT_GAP 16384 + +/*! + * Ack timeout + */ +#define CN779_ACKTIMEOUT 2000 + +/*! + * Random ack timeout limits + */ +#define CN779_ACK_TIMEOUT_RND 1000 + +/*! + * Verification of default datarate + */ +#if ( CN779_DEFAULT_DATARATE > DR_5 ) +#error "A default DR higher than DR_5 may lead to connectivity loss." +#endif + +/*! + * Second reception window channel frequency definition. + */ +#define CN779_RX_WND_2_FREQ 786000000 + +/*! + * Second reception window channel datarate definition. + */ +#define CN779_RX_WND_2_DR DR_0 + +/* + * CLASS B + */ +/*! + * Beacon frequency + */ +#define CN779_BEACON_CHANNEL_FREQ 785000000 + +/*! + * Payload size of a beacon frame + */ +#define CN779_BEACON_SIZE 17 + +/*! + * Size of RFU 1 field + */ +#define CN779_RFU1_SIZE 2 + +/*! + * Size of RFU 2 field + */ +#define CN779_RFU2_SIZE 0 + +/*! + * Datarate of the beacon channel + */ +#define CN779_BEACON_CHANNEL_DR DR_3 + +/*! + * Bandwith of the beacon channel + */ +#define CN779_BEACON_CHANNEL_BW 0 + +/*! + * LoRaMac maximum number of bands + */ +#define CN779_MAX_NB_BANDS 1 + +/*! + * Band 0 definition + * { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define CN779_BAND0 { 100, CN779_MAX_TX_POWER, 0, 0 } // 1.0 % + +/*! + * LoRaMac default channel 1 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define CN779_LC1 { 779500000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } +/*! + * LoRaMac default channel 2 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define CN779_LC2 { 779700000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac default channel 3 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define CN779_LC3 { 779900000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac channels which are allowed for the join procedure + */ +#define CN779_JOIN_CHANNELS ( uint16_t )( LC( 1 ) | LC( 2 ) | LC( 3 ) ) + +/*! + * Data rates table definition + */ +static const uint8_t DataratesCN779[] = { 12, 11, 10, 9, 8, 7, 7, 50 }; + +/*! + * Bandwidths table definition in Hz + */ +static const uint32_t BandwidthsCN779[] = { 125000, 125000, 125000, 125000, 125000, 125000, 250000, 0 }; + +/*! + * Maximum payload with respect to the datarate index. Cannot operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateCN779[] = { 51, 51, 51, 115, 242, 242, 242, 242 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateRepeaterCN779[] = { 51, 51, 51, 115, 222, 222, 222, 222 }; + +/*! + * \brief The function gets a value of a specific phy attribute. + * + * \param [IN] getPhy Pointer to the function parameters. + * + * \retval Returns a structure containing the PHY parameter. + */ +PhyParam_t RegionCN779GetPhyParam( GetPhyParams_t* getPhy ); + +/*! + * \brief Updates the last TX done parameters of the current channel. + * + * \param [IN] txDone Pointer to the function parameters. + */ +void RegionCN779SetBandTxDone( SetBandTxDoneParams_t* txDone ); + +/*! + * \brief Initializes the channels masks and the channels. + * + * \param [IN] type Sets the initialization type. + */ +void RegionCN779InitDefaults( InitType_t type ); + +/*! + * \brief Verifies a parameter. + * + * \param [IN] verify Pointer to the function parameters. + * + * \param [IN] type Sets the initialization type. + * + * \retval Returns true, if the parameter is valid. + */ +bool RegionCN779Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ); + +/*! + * \brief The function parses the input buffer and sets up the channels of the + * CF list. + * + * \param [IN] applyCFList Pointer to the function parameters. + */ +void RegionCN779ApplyCFList( ApplyCFListParams_t* applyCFList ); + +/*! + * \brief Sets a channels mask. + * + * \param [IN] chanMaskSet Pointer to the function parameters. + * + * \retval Returns true, if the channels mask could be set. + */ +bool RegionCN779ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ); + +/*! + * \brief Calculates the next datarate to set, when ADR is on or off. + * + * \param [IN] adrNext Pointer to the function parameters. + * + * \param [OUT] drOut The calculated datarate for the next TX. + * + * \param [OUT] txPowOut The TX power for the next TX. + * + * \param [OUT] adrAckCounter The calculated ADR acknowledgement counter. + * + * \retval Returns true, if an ADR request should be performed. + */ +bool RegionCN779AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ); + +/*! + * Computes the Rx window timeout and offset. + * + * \param [IN] datarate Rx window datarate index to be used + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms + * interval around RxOffset + * + * \param [OUT]rxConfigParams Returns updated WindowTimeout and WindowOffset fields. + */ +void RegionCN779ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ); + +/*! + * \brief Configuration of the RX windows. + * + * \param [IN] rxConfig Pointer to the function parameters. + * + * \param [OUT] datarate The datarate index which was set. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionCN779RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ); + +/*! + * \brief TX configuration. + * + * \param [IN] txConfig Pointer to the function parameters. + * + * \param [OUT] txPower The tx power index which was set. + * + * \param [OUT] txTimeOnAir The time-on-air of the frame. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionCN779TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ); + +/*! + * \brief The function processes a Link ADR Request. + * + * \param [IN] linkAdrReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionCN779LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ); + +/*! + * \brief The function processes a RX Parameter Setup Request. + * + * \param [IN] rxParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionCN779RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ); + +/*! + * \brief The function processes a Channel Request. + * + * \param [IN] newChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionCN779NewChannelReq( NewChannelReqParams_t* newChannelReq ); + +/*! + * \brief The function processes a TX ParamSetup Request. + * + * \param [IN] txParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + * Returns -1, if the functionality is not implemented. In this case, the end node + * shall not process the command. + */ +int8_t RegionCN779TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ); + +/*! + * \brief The function processes a DlChannel Request. + * + * \param [IN] dlChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionCN779DlChannelReq( DlChannelReqParams_t* dlChannelReq ); + +/*! + * \brief Alternates the datarate of the channel for the join request. + * + * \param [IN] alternateDr Pointer to the function parameters. + * + * \retval Datarate to apply. + */ +int8_t RegionCN779AlternateDr( AlternateDrParams_t* alternateDr ); + +/*! + * \brief Calculates the back-off time. + * + * \param [IN] calcBackOff Pointer to the function parameters. + */ +void RegionCN779CalcBackOff( CalcBackOffParams_t* calcBackOff ); + +/*! + * \brief Searches and set the next random available channel + * + * \param [OUT] channel Next channel to use for TX. + * + * \param [OUT] time Time to wait for the next transmission according to the duty + * cycle. + * + * \param [OUT] aggregatedTimeOff Updates the aggregated time off. + * + * \retval Function status [1: OK, 0: Unable to find a channel on the current datarate] + */ +bool RegionCN779NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ); + +/*! + * \brief Adds a channel. + * + * \param [IN] channelAdd Pointer to the function parameters. + * + * \retval Status of the operation. + */ +LoRaMacStatus_t RegionCN779ChannelAdd( ChannelAddParams_t* channelAdd ); + +/*! + * \brief Removes a channel. + * + * \param [IN] channelRemove Pointer to the function parameters. + * + * \retval Returns true, if the channel was removed successfully. + */ +bool RegionCN779ChannelsRemove( ChannelRemoveParams_t* channelRemove ); + +/*! + * \brief Sets the radio into continuous wave mode. + * + * \param [IN] continuousWave Pointer to the function parameters. + */ +void RegionCN779SetContinuousWave( ContinuousWaveParams_t* continuousWave ); + +/*! + * \brief Computes new datarate according to the given offset + * + * \param [IN] downlinkDwellTime Downlink dwell time configuration. 0: No limit, 1: 400ms + * + * \param [IN] dr Current datarate + * + * \param [IN] drOffset Offset to be applied + * + * \retval newDr Computed datarate. + */ +uint8_t RegionCN779ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ); + +/*! + * \brief Sets the radio into beacon reception mode + * + * \param [IN] rxBeaconSetup Pointer to the function parameters + */ + void RegionCN779RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ); + +/*! \} defgroup REGIONCN779 */ + +#endif // __REGION_CN779_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCommon.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCommon.c new file mode 100644 index 00000000..777ffaff --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCommon.c @@ -0,0 +1,293 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC common region implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ + +#include +#include +#include +#include + +//#include "timer.h" +#include "timeServer.h" +#include "utilities.h" +#include "LoRaMac.h" +#include "RegionCommon.h" + + + +#define BACKOFF_DC_1_HOUR 1 +#define BACKOFF_DC_10_HOURS 2 +#define BACKOFF_DC_24_HOURS 3 + + + +static uint8_t CountChannels( uint16_t mask, uint8_t nbBits ) +{ + uint8_t nbActiveBits = 0; + + for( uint8_t j = 0; j < nbBits; j++ ) + { + if( ( mask & ( 1 << j ) ) == ( 1 << j ) ) + { + nbActiveBits++; + } + } + return nbActiveBits; +} + + + +uint16_t RegionCommonGetJoinDc( TimerTime_t elapsedTime ) +{ + uint16_t dutyCycle = 0; + + if( elapsedTime < 3600000 ) + { + dutyCycle = BACKOFF_DC_1_HOUR; + } + else if( elapsedTime < ( 3600000 + 36000000 ) ) + { + dutyCycle = BACKOFF_DC_10_HOURS; + } + else + { + dutyCycle = BACKOFF_DC_24_HOURS; + } + return dutyCycle; +} + +bool RegionCommonChanVerifyDr( uint8_t nbChannels, uint16_t* channelsMask, int8_t dr, int8_t minDr, int8_t maxDr, ChannelParams_t* channels ) +{ + if( RegionCommonValueInRange( dr, minDr, maxDr ) == 0 ) + { + return false; + } + + for( uint8_t i = 0, k = 0; i < nbChannels; i += 16, k++ ) + { + //4.29 workaround for when disable all channles not return server 0306 but return 0304 + if (channelsMask[k] == 0) + return true; + for( uint8_t j = 0; j < 16; j++ ) + { + if( ( ( channelsMask[k] & ( 1 << j ) ) != 0 ) ) + {// Check datarate validity for enabled channels +#ifdef CONFIG_LINKWAN + if( RegionCommonValueInRange( dr, ( channels[(i + j) % 8].DrRange.Fields.Min & 0x0F ), + ( channels[(i + j) % 8].DrRange.Fields.Max & 0x0F ) ) == 1 ) +#else + if( RegionCommonValueInRange( dr, ( channels[i + j].DrRange.Fields.Min & 0x0F ), + ( channels[i + j].DrRange.Fields.Max & 0x0F ) ) == 1 ) +#endif + { + // At least 1 channel has been found we can return OK. + return true; + } + } + } + } + return false; +} + +uint8_t RegionCommonValueInRange( int8_t value, int8_t min, int8_t max ) +{ + if( ( value >= min ) && ( value <= max ) ) + { + return 1; + } + return 0; +} + +bool RegionCommonChanDisable( uint16_t* channelsMask, uint8_t id, uint8_t maxChannels ) +{ + uint8_t index = id / 16; + + if( ( index > ( maxChannels / 16 ) ) || ( id >= maxChannels ) ) + { + return false; + } + + // Deactivate channel + channelsMask[index] &= ~( 1 << ( id % 16 ) ); + + return true; +} + +uint8_t RegionCommonCountChannels( uint16_t* channelsMask, uint8_t startIdx, uint8_t stopIdx ) +{ + uint8_t nbChannels = 0; + + if( channelsMask == NULL ) + { + return 0; + } + + for( uint8_t i = startIdx; i < stopIdx; i++ ) + { + nbChannels += CountChannels( channelsMask[i], 16 ); + } + + return nbChannels; +} + +void RegionCommonChanMaskCopy( uint16_t* channelsMaskDest, uint16_t* channelsMaskSrc, uint8_t len ) +{ + if( ( channelsMaskDest != NULL ) && ( channelsMaskSrc != NULL ) ) + { + for( uint8_t i = 0; i < len; i++ ) + { + channelsMaskDest[i] = channelsMaskSrc[i]; + } + } +} + +void RegionCommonSetBandTxDone( bool joined, Band_t* band, TimerTime_t lastTxDone ) +{ + if (joined == true) { + band->LastTxDoneTime = lastTxDone; + } else { + band->LastTxDoneTime = lastTxDone; + band->LastJoinTxDoneTime = lastTxDone; + } +} + +TimerTime_t RegionCommonUpdateBandTimeOff( bool joined, bool dutyCycle, Band_t* bands, uint8_t nbBands ) +{ + TimerTime_t nextTxDelay = ( TimerTime_t )( -1 ); + + // Update bands Time OFF + for( uint8_t i = 0; i < nbBands; i++ ) + { + if( joined == false ) + { + uint32_t txDoneTime = MAX( TimerGetElapsedTime( bands[i].LastJoinTxDoneTime ), + ( dutyCycle == true ) ? TimerGetElapsedTime( bands[i].LastTxDoneTime ) : 0 ); + + if( bands[i].TimeOff <= txDoneTime ) + { + bands[i].TimeOff = 0; + } + if( bands[i].TimeOff != 0 ) + { + nextTxDelay = MIN( bands[i].TimeOff - txDoneTime, nextTxDelay ); + } + } + else + { + if( dutyCycle == true ) + { + if( bands[i].TimeOff <= TimerGetElapsedTime( bands[i].LastTxDoneTime ) ) + { + bands[i].TimeOff = 0; + } + if( bands[i].TimeOff != 0 ) + { + nextTxDelay = MIN( bands[i].TimeOff - TimerGetElapsedTime( bands[i].LastTxDoneTime ), + nextTxDelay ); + } + } + else + { + nextTxDelay = 0; + bands[i].TimeOff = 0; + } + } + } + return nextTxDelay; +} + +uint8_t RegionCommonParseLinkAdrReq( uint8_t* payload, LinkAdrParams_t* linkAdrParams ) +{ + uint8_t retIndex = 0; + + if( payload[0] == SRV_MAC_LINK_ADR_REQ ) + { + // Parse datarate and tx power + linkAdrParams->Datarate = payload[1]; + linkAdrParams->TxPower = linkAdrParams->Datarate & 0x0F; + linkAdrParams->Datarate = ( linkAdrParams->Datarate >> 4 ) & 0x0F; + // Parse ChMask + linkAdrParams->ChMask = ( uint16_t )payload[2]; + linkAdrParams->ChMask |= ( uint16_t )payload[3] << 8; + // Parse ChMaskCtrl and nbRep + linkAdrParams->NbRep = payload[4]; + linkAdrParams->ChMaskCtrl = ( linkAdrParams->NbRep >> 4 ) & 0x07; + linkAdrParams->NbRep &= 0x0F; + + // LinkAdrReq has 4 bytes length + 1 byte CMD + retIndex = 5; + } + return retIndex; +} + +double RegionCommonComputeSymbolTimeLoRa( uint8_t phyDr, uint32_t bandwidth ) +{ + return ( ( double )( 1 << phyDr ) / ( double )bandwidth ) * 1000; +} + +double RegionCommonComputeSymbolTimeFsk( uint8_t phyDr ) +{ + return ( 8.0 / ( double )phyDr ); // 1 symbol equals 1 byte +} + +void RegionCommonComputeRxWindowParameters( double tSymbol, uint8_t minRxSymbols, uint32_t rxError, uint32_t wakeUpTime, uint32_t* windowTimeout, int32_t* windowOffset ) +{ + *windowTimeout = MAX( ( uint32_t )ceil( ( ( 2 * minRxSymbols - 8 ) * tSymbol + 2 * rxError ) / tSymbol ), minRxSymbols ); // Computed number of symbols + *windowOffset = ( int32_t )ceil( ( 4.0 * tSymbol ) - ( ( *windowTimeout * tSymbol ) / 2.0 ) - wakeUpTime ); +} + +int8_t RegionCommonComputeTxPower( int8_t txPowerIndex, float maxEirp, float antennaGain ) +{ + int8_t phyTxPower = 0; + + phyTxPower = ( int8_t )floor( ( maxEirp - ( txPowerIndex * 2U ) ) - antennaGain ); + + return phyTxPower; +} +void RegionCommonRxBeaconSetup( RegionCommonRxBeaconSetupParams_t* rxBeaconSetupParams ) +{ + bool rxContinuous = true; + uint8_t datarate; + + // Set the radio into sleep mode + Radio.Sleep( ); + + // Setup frequency and payload length + Radio.SetChannel( rxBeaconSetupParams->Frequency ); + Radio.SetMaxPayloadLength( MODEM_LORA, rxBeaconSetupParams->BeaconSize ); + + // Check the RX continuous mode + if( rxBeaconSetupParams->RxTime != 0 ) + { + rxContinuous = false; + } + + // Get region specific datarate + datarate = rxBeaconSetupParams->Datarates[rxBeaconSetupParams->BeaconDatarate]; + + // Setup radio + Radio.SetRxConfig( MODEM_LORA, rxBeaconSetupParams->BeaconChannelBW, datarate, + 1, 0, 10, rxBeaconSetupParams->SymbolTimeout, true, rxBeaconSetupParams->BeaconSize, false, 0, 0, false, rxContinuous ); + + Radio.Rx( rxBeaconSetupParams->RxTime ); +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCommon.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCommon.h new file mode 100644 index 00000000..5026dc17 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionCommon.h @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file RegionCommon.h + * + * \brief Region independent implementations which are common to all regions. + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGIONCOMMON Common region implementation + * Region independent implementations which are common to all regions. + * \{ + */ +#ifndef __REGIONCOMMON_H__ +#define __REGIONCOMMON_H__ + +typedef struct sLinkAdrParams +{ + /*! + * Number of repetitions. + */ + uint8_t NbRep; + /*! + * Datarate. + */ + int8_t Datarate; + /*! + * Tx power. + */ + int8_t TxPower; + /*! + * Channels mask control field. + */ + uint8_t ChMaskCtrl; + /*! + * Channels mask field. + */ + uint16_t ChMask; +}LinkAdrParams_t; +typedef struct sRegionCommonRxBeaconSetupParams +{ + /*! + * A pointer to the available datarates. + */ + const uint8_t* Datarates; + /*! + * Frequency + */ + uint32_t Frequency; + /*! + * The size of the beacon frame. + */ + uint8_t BeaconSize; + /*! + * The datarate of the beacon. + */ + uint8_t BeaconDatarate; + /*! + * The channel bandwidth of the beacon. + */ + uint8_t BeaconChannelBW; + /*! + * The RX time. + */ + uint32_t RxTime; + /*! + * The symbol timeout of the RX procedure. + */ + uint16_t SymbolTimeout; +}RegionCommonRxBeaconSetupParams_t; + +/*! + * \brief Calculates the join duty cycle. + * This is a generic function and valid for all regions. + * + * \param [IN] elapsedTime Elapsed time since the start of the device. + * + * \retval Duty cycle restriction. + */ +uint16_t RegionCommonGetJoinDc( TimerTime_t elapsedTime ); + +/*! + * \brief Verifies, if a value is in a given range. + * This is a generic function and valid for all regions. + * + * \param [IN] value Value to verify, if it is in range. + * + * \param [IN] min Minimum possible value. + * + * \param [IN] max Maximum possible value. + * + * \retval Returns 1 if the value is in range, otherwise 0. + */ +uint8_t RegionCommonValueInRange( int8_t value, int8_t min, int8_t max ); + +/*! + * \brief Verifies, if a datarate is available on an active channel. + * This is a generic function and valid for all regions. + * + * \param [IN] nbChannels Number of channels. + * + * \param [IN] channelsMask The channels mask of the region. + * + * \param [IN] dr The datarate to verify. + * + * \param [IN] minDr Minimum datarate. + * + * \param [IN] maxDr Maximum datarate. + * + * \param [IN] channels The channels of the region. + * + * \retval Returns true if the datarate is supported, false if not. + */ +bool RegionCommonChanVerifyDr( uint8_t nbChannels, uint16_t* channelsMask, int8_t dr, + int8_t minDr, int8_t maxDr, ChannelParams_t* channels ); + +/*! + * \brief Disables a channel in a given channels mask. + * This is a generic function and valid for all regions. + * + * \param [IN] channelsMask The channels mask of the region. + * + * \param [IN] id The id of the channels mask to disable. + * + * \param [IN] maxChannels Maximum number of channels. + * + * \retval Returns true if the channel could be disabled, false if not. + */ +bool RegionCommonChanDisable( uint16_t* channelsMask, uint8_t id, uint8_t maxChannels ); + +/*! + * \brief Counts the number of active channels in a given channels mask. + * This is a generic function and valid for all regions. + * + * \param [IN] channelsMask The channels mask of the region. + * + * \param [IN] startIdx Start index. + * + * \param [IN] stopIdx Stop index ( the channels of this index will not be counted ). + * + * \retval Returns the number of active channels. + */ +uint8_t RegionCommonCountChannels( uint16_t* channelsMask, uint8_t startIdx, uint8_t stopIdx ); + +/*! + * \brief Copy a channels mask. + * This is a generic function and valid for all regions. + * + * \param [IN] channelsMaskDest The destination channels mask. + * + * \param [IN] channelsMaskSrc The source channels mask. + * + * \param [IN] len The index length to copy. + */ +void RegionCommonChanMaskCopy( uint16_t* channelsMaskDest, uint16_t* channelsMaskSrc, uint8_t len ); + +/*! + * \brief Sets the last tx done property. + * This is a generic function and valid for all regions. + * + * \param [IN] joined Set to true, if the node has joined the network + * + * \param [IN] band The band to be updated. + * + * \param [IN] lastTxDone The time of the last TX done. + */ +void RegionCommonSetBandTxDone( bool joined, Band_t* band, TimerTime_t lastTxDone ); + +/*! + * \brief Updates the time-offs of the bands. + * This is a generic function and valid for all regions. + * + * \param [IN] joined Set to true, if the node has joined the network + * + * \param [IN] dutyCycle Set to true, if the duty cycle is enabled. + * + * \param [IN] bands A pointer to the bands. + * + * \param [IN] nbBands The number of bands available. + * + * \retval Returns the time which must be waited to perform the next uplink. + */ +TimerTime_t RegionCommonUpdateBandTimeOff( bool joined, bool dutyCycle, Band_t* bands, uint8_t nbBands ); + +/*! + * \brief Parses the parameter of an LinkAdrRequest. + * This is a generic function and valid for all regions. + * + * \param [IN] payload Pointer to the payload containing the MAC commands. The payload + * must contain the CMD identifier, following by the parameters. + * + * \param [OUT] parseLinkAdr The function fills the structure with the ADR parameters. + * + * \retval Returns the length of the ADR request, if a request was found. Otherwise, the + * function returns 0. + */ +uint8_t RegionCommonParseLinkAdrReq( uint8_t* payload, LinkAdrParams_t* parseLinkAdr ); + +/*! + * \brief Computes the symbol time for LoRa modulation. + * + * \param [IN] phyDr Physical datarate to use. + * + * \param [IN] bandwidth Bandwidth to use. + * + * \retval Returns the symbol time. + */ +double RegionCommonComputeSymbolTimeLoRa( uint8_t phyDr, uint32_t bandwidth ); + +/*! + * \brief Computes the symbol time for FSK modulation. + * + * \param [IN] phyDr Physical datarate to use. + * + * \param [IN] bandwidth Bandwidth to use. + * + * \retval Returns the symbol time. + */ +double RegionCommonComputeSymbolTimeFsk( uint8_t phyDr ); + +/*! + * \brief Computes the RX window timeout and the RX window offset. + * + * \param [IN] tSymbol Symbol timeout. + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms interval around RxOffset. + * + * \param [IN] wakeUpTime Wakeup time of the system. + * + * \param [OUT] windowTimeout RX window timeout. + * + * \param [OUT] windowOffset RX window time offset to be applied to the RX delay. + */ +void RegionCommonComputeRxWindowParameters( double tSymbol, uint8_t minRxSymbols, uint32_t rxError, uint32_t wakeUpTime, uint32_t* windowTimeout, int32_t* windowOffset ); + +/*! + * \brief Computes the txPower, based on the max EIRP and the antenna gain. + * + * \param [IN] txPower TX power index. + * + * \param [IN] maxEirp Maximum EIRP. + * + * \param [IN] antennaGain Antenna gain. + * + * \retval Returns the physical TX power. + */ +int8_t RegionCommonComputeTxPower( int8_t txPowerIndex, float maxEirp, float antennaGain ); + +/*! + * \brief Sets up the radio into RX beacon mode. + * + * \param [IN] rxBeaconSetupParams A pointer to the input parameters. + */ +void RegionCommonRxBeaconSetup( RegionCommonRxBeaconSetupParams_t* rxBeaconSetupParams ); + +/*! \} defgroup REGIONCOMMON */ + +#endif // __REGIONCOMMON_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU433.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU433.c new file mode 100644 index 00000000..47e4979a --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU433.c @@ -0,0 +1,1098 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC region EU433 implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include +#include + +#include "radio.h" +//#include "timer.h" +#include "timeServer.h" +#include "LoRaMac.h" + +#include "utilities.h" + +#include "Region.h" +#include "RegionCommon.h" +#include "RegionEU433.h" +#include "debug.h" + +// Definitions +#define CHANNELS_MASK_SIZE 1 + +// Global attributes +/*! + * LoRaMAC channels + */ +static ChannelParams_t Channels[EU433_MAX_NB_CHANNELS]; + +/*! + * LoRaMac bands + */ +static Band_t Bands[EU433_MAX_NB_BANDS] = +{ + EU433_BAND0 +}; + +/*! + * LoRaMac channels mask + */ +static uint16_t ChannelsMask[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels default mask + */ +static uint16_t ChannelsDefaultMask[CHANNELS_MASK_SIZE]; + +// Static functions +static int8_t GetNextLowerTxDr( int8_t dr, int8_t minDr ) +{ + uint8_t nextLowerDr = 0; + + if( dr == minDr ) + { + nextLowerDr = minDr; + } + else + { + nextLowerDr = dr - 1; + } + return nextLowerDr; +} + +static uint32_t GetBandwidth( uint32_t drIndex ) +{ + switch( BandwidthsEU433[drIndex] ) + { + default: + case 125000: + return 0; + case 250000: + return 1; + case 500000: + return 2; + } +} + +static int8_t LimitTxPower( int8_t txPower, int8_t maxBandTxPower, int8_t datarate, uint16_t* channelsMask ) +{ + int8_t txPowerResult = txPower; + + // Limit tx power to the band max + txPowerResult = MAX( txPower, maxBandTxPower ); + + return txPowerResult; +} + +static bool VerifyTxFreq( uint32_t freq ) +{ + // Check radio driver support + if( Radio.CheckRfFrequency( freq ) == false ) + { + return false; + } + + if( ( freq < 433175000 ) || ( freq > 434665000 ) ) + { + return false; + } + return true; +} + +static uint8_t CountNbOfEnabledChannels( bool joined, uint8_t datarate, uint16_t* channelsMask, ChannelParams_t* channels, Band_t* bands, uint8_t* enabledChannels, uint8_t* delayTx ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTransmission = 0; + + for( uint8_t i = 0, k = 0; i < EU433_MAX_NB_CHANNELS; i += 16, k++ ) + { + for( uint8_t j = 0; j < 16; j++ ) + { + if( ( channelsMask[k] & ( 1 << j ) ) != 0 ) + { + if( channels[i + j].Frequency == 0 ) + { // Check if the channel is enabled + continue; + } + if( joined == false ) + { + if( ( EU433_JOIN_CHANNELS & ( 1 << j ) ) == 0 ) + { + continue; + } + } + if( RegionCommonValueInRange( datarate, channels[i + j].DrRange.Fields.Min, + channels[i + j].DrRange.Fields.Max ) == false ) + { // Check if the current channel selection supports the given datarate + continue; + } + if( bands[channels[i + j].Band].TimeOff > 0 ) + { // Check if the band is available for transmission + delayTransmission++; + continue; + } + enabledChannels[nbEnabledChannels++] = i + j; + } + } + } + + *delayTx = delayTransmission; + return nbEnabledChannels; +} + +PhyParam_t RegionEU433GetPhyParam( GetPhyParams_t* getPhy ) +{ + PhyParam_t phyParam = { 0 }; + + switch( getPhy->Attribute ) + { + case PHY_MIN_RX_DR: + { + phyParam.Value = EU433_RX_MIN_DATARATE; + break; + } + case PHY_MIN_TX_DR: + { + phyParam.Value = EU433_TX_MIN_DATARATE; + break; + } + case PHY_DEF_TX_DR: + { + phyParam.Value = EU433_DEFAULT_DATARATE; + break; + } + case PHY_NEXT_LOWER_TX_DR: + { + phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, EU433_TX_MIN_DATARATE ); + break; + } + case PHY_DEF_TX_POWER: + { + phyParam.Value = EU433_DEFAULT_TX_POWER; + break; + } + case PHY_MAX_PAYLOAD: + { + phyParam.Value = MaxPayloadOfDatarateEU433[getPhy->Datarate]; + break; + } + case PHY_MAX_PAYLOAD_REPEATER: + { + phyParam.Value = MaxPayloadOfDatarateRepeaterEU433[getPhy->Datarate]; + break; + } + case PHY_DUTY_CYCLE: + { + phyParam.Value = EU433_DUTY_CYCLE_ENABLED; + break; + } + case PHY_MAX_RX_WINDOW: + { + phyParam.Value = EU433_MAX_RX_WINDOW; + break; + } + case PHY_RECEIVE_DELAY1: + { + phyParam.Value = EU433_RECEIVE_DELAY1; + break; + } + case PHY_RECEIVE_DELAY2: + { + phyParam.Value = EU433_RECEIVE_DELAY2; + break; + } + case PHY_JOIN_ACCEPT_DELAY1: + { + phyParam.Value = EU433_JOIN_ACCEPT_DELAY1; + break; + } + case PHY_JOIN_ACCEPT_DELAY2: + { + phyParam.Value = EU433_JOIN_ACCEPT_DELAY2; + break; + } + case PHY_MAX_FCNT_GAP: + { + phyParam.Value = EU433_MAX_FCNT_GAP; + break; + } + case PHY_ACK_TIMEOUT: + { + phyParam.Value = ( EU433_ACKTIMEOUT + randr( -EU433_ACK_TIMEOUT_RND, EU433_ACK_TIMEOUT_RND ) ); + break; + } + case PHY_DEF_DR1_OFFSET: + { + phyParam.Value = EU433_DEFAULT_RX1_DR_OFFSET; + break; + } + case PHY_DEF_RX2_FREQUENCY: + { + phyParam.Value = EU433_RX_WND_2_FREQ; + break; + } + case PHY_DEF_RX2_DR: + { + phyParam.Value = EU433_RX_WND_2_DR; + break; + } + case PHY_CHANNELS_MASK: + { + phyParam.ChannelsMask = ChannelsMask; + break; + } + case PHY_CHANNELS_DEFAULT_MASK: + { + phyParam.ChannelsMask = ChannelsDefaultMask; + break; + } + case PHY_MAX_NB_CHANNELS: + { + phyParam.Value = EU433_MAX_NB_CHANNELS; + break; + } + case PHY_CHANNELS: + { + phyParam.Channels = Channels; + break; + } + case PHY_DEF_UPLINK_DWELL_TIME: + case PHY_DEF_DOWNLINK_DWELL_TIME: + { + phyParam.Value = 0; + break; + } + case PHY_DEF_MAX_EIRP: + { + phyParam.fValue = EU433_DEFAULT_MAX_EIRP; + break; + } + case PHY_DEF_ANTENNA_GAIN: + { + phyParam.fValue = EU433_DEFAULT_ANTENNA_GAIN; + break; + } + case PHY_NB_JOIN_TRIALS: + case PHY_DEF_NB_JOIN_TRIALS: + { + phyParam.Value = 48; + break; + } + case PHY_BEACON_CHANNEL_FREQ: + { + phyParam.Value = EU433_BEACON_CHANNEL_FREQ; + break; + } + case PHY_BEACON_FORMAT: + { + phyParam.BeaconFormat.BeaconSize = EU433_BEACON_SIZE; + phyParam.BeaconFormat.Rfu1Size = EU433_RFU1_SIZE; + phyParam.BeaconFormat.Rfu2Size = EU433_RFU2_SIZE; + break; + } + case PHY_BEACON_CHANNEL_DR: + { + phyParam.Value = EU433_BEACON_CHANNEL_DR; + break; + } + default: + { + break; + } + } + + return phyParam; +} + +void RegionEU433SetBandTxDone( SetBandTxDoneParams_t* txDone ) +{ + RegionCommonSetBandTxDone( txDone->Joined, &Bands[Channels[txDone->Channel].Band], txDone->LastTxDoneTime ); +} + +void RegionEU433InitDefaults( InitType_t type ) +{ + switch( type ) + { + case INIT_TYPE_INIT: + { + // Channels + Channels[0] = ( ChannelParams_t ) EU433_LC1; + Channels[1] = ( ChannelParams_t ) EU433_LC2; + Channels[2] = ( ChannelParams_t ) EU433_LC3; + + // Initialize the channels default mask + ChannelsDefaultMask[0] = LC( 1 ) + LC( 2 ) + LC( 3 ); + // Update the channels mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 1 ); + break; + } + case INIT_TYPE_RESTORE: + { + // Restore channels default mask + ChannelsMask[0] |= ChannelsDefaultMask[0]; + break; + } + default: + { + break; + } + } +} + +bool RegionEU433Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ) +{ + switch( phyAttribute ) + { + case PHY_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, EU433_TX_MIN_DATARATE, EU433_TX_MAX_DATARATE ); + } + case PHY_DEF_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, DR_0, DR_5 ); + } + case PHY_RX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, EU433_RX_MIN_DATARATE, EU433_RX_MAX_DATARATE ); + } + case PHY_DEF_TX_POWER: + case PHY_TX_POWER: + { + // Remark: switched min and max! + return RegionCommonValueInRange( verify->TxPower, EU433_MAX_TX_POWER, EU433_MIN_TX_POWER ); + } + case PHY_DUTY_CYCLE: + { + return EU433_DUTY_CYCLE_ENABLED; + } + case PHY_NB_JOIN_TRIALS: + { + if( verify->NbJoinTrials < 48 ) + { + return false; + } + break; + } + default: + return false; + } + return true; +} + +void RegionEU433ApplyCFList( ApplyCFListParams_t* applyCFList ) +{ + ChannelParams_t newChannel; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + // Setup default datarate range + newChannel.DrRange.Value = ( DR_5 << 4 ) | DR_0; + + // Size of the optional CF list + if( applyCFList->Size != 16 ) + { + return; + } + + // Last byte is RFU, don't take it into account + for( uint8_t i = 0, chanIdx = EU433_NUMB_DEFAULT_CHANNELS; chanIdx < EU433_MAX_NB_CHANNELS; i+=3, chanIdx++ ) + { + if( chanIdx < ( EU433_NUMB_CHANNELS_CF_LIST + EU433_NUMB_DEFAULT_CHANNELS ) ) + { + // Channel frequency + newChannel.Frequency = (uint32_t) applyCFList->Payload[i]; + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 1] << 8 ); + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 2] << 16 ); + newChannel.Frequency *= 100; + + // Initialize alternative frequency to 0 + newChannel.Rx1Frequency = 0; + } + else + { + newChannel.Frequency = 0; + newChannel.DrRange.Value = 0; + newChannel.Rx1Frequency = 0; + } + + if( newChannel.Frequency != 0 ) + { + channelAdd.NewChannel = &newChannel; + channelAdd.ChannelId = chanIdx; + + // Try to add all channels + RegionEU433ChannelAdd( &channelAdd ); + } + else + { + channelRemove.ChannelId = chanIdx; + + RegionEU433ChannelsRemove( &channelRemove ); + } + } +} + +bool RegionEU433ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ) +{ + switch( chanMaskSet->ChannelsMaskType ) + { + case CHANNELS_MASK: + { + RegionCommonChanMaskCopy( ChannelsMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + case CHANNELS_DEFAULT_MASK: + { + RegionCommonChanMaskCopy( ChannelsDefaultMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + default: + return false; + } + return true; +} + +bool RegionEU433AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ) +{ + bool adrAckReq = false; + int8_t datarate = adrNext->Datarate; + int8_t txPower = adrNext->TxPower; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + // Report back the adr ack counter + *adrAckCounter = adrNext->AdrAckCounter; + + if( adrNext->AdrEnabled == true ) + { + if( datarate == EU433_TX_MIN_DATARATE ) + { + *adrAckCounter = 0; + adrAckReq = false; + } + else + { + if( adrNext->AdrAckCounter >= EU433_ADR_ACK_LIMIT ) + { + adrAckReq = true; + txPower = EU433_MAX_TX_POWER; + } + else + { + adrAckReq = false; + } + if( adrNext->AdrAckCounter >= ( EU433_ADR_ACK_LIMIT + EU433_ADR_ACK_DELAY ) ) + { + if( ( adrNext->AdrAckCounter % EU433_ADR_ACK_DELAY ) == 1 ) + { + // Decrease the datarate + getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + getPhy.Datarate = datarate; + getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + phyParam = RegionEU433GetPhyParam( &getPhy ); + datarate = phyParam.Value; + + if( datarate == EU433_TX_MIN_DATARATE ) + { + // We must set adrAckReq to false as soon as we reach the lowest datarate + adrAckReq = false; + if( adrNext->UpdateChanMask == true ) + { + // Re-enable default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + } + } + } + } + } + } + + *drOut = datarate; + *txPowOut = txPower; + return adrAckReq; +} + +void RegionEU433ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ) +{ + double tSymbol = 0.0; + uint32_t radioWakeUpTime; + + rxConfigParams->Datarate = datarate; + rxConfigParams->Bandwidth = GetBandwidth( datarate ); + + if( datarate == DR_7 ) + { // FSK + tSymbol = RegionCommonComputeSymbolTimeFsk( DataratesEU433[datarate] ); + } + else + { // LoRa + tSymbol = RegionCommonComputeSymbolTimeLoRa( DataratesEU433[datarate], BandwidthsEU433[datarate] ); + } + + radioWakeUpTime = Radio.GetWakeupTime( ); + RegionCommonComputeRxWindowParameters( tSymbol, minRxSymbols, rxError, radioWakeUpTime, &rxConfigParams->WindowTimeout, &rxConfigParams->WindowOffset ); +} + +bool RegionEU433RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ) +{ + RadioModems_t modem; + int8_t dr = rxConfig->Datarate; + uint8_t maxPayload = 0; + int8_t phyDr = 0; + uint32_t frequency = rxConfig->Frequency; + + if( Radio.GetStatus( ) != RF_IDLE ) + { + return false; + } + + if( rxConfig->RxSlot == RX_SLOT_WIN_1 ) + { + // Apply window 1 frequency + frequency = Channels[rxConfig->Channel].Frequency; + // Apply the alternative RX 1 window frequency, if it is available + if( Channels[rxConfig->Channel].Rx1Frequency != 0 ) + { + frequency = Channels[rxConfig->Channel].Rx1Frequency; + } + } + + // Read the physical datarate from the datarates table + phyDr = DataratesEU433[dr]; + + Radio.SetChannel( frequency ); + + // Radio configuration + if( dr == DR_7 ) + { + modem = MODEM_FSK; + Radio.SetRxConfig( modem, 50000, phyDr * 1000, 0, 83333, 5, rxConfig->WindowTimeout, false, 0, true, 0, 0, false, rxConfig->RxContinuous ); + } + else + { + modem = MODEM_LORA; + Radio.SetRxConfig( modem, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, false, 0, false, 0, 0, true, rxConfig->RxContinuous ); + } + + if( rxConfig->RepeaterSupport == true ) + { + maxPayload = MaxPayloadOfDatarateRepeaterEU433[dr]; + } + else + { + maxPayload = MaxPayloadOfDatarateEU433[dr]; + } + Radio.SetMaxPayloadLength( modem, maxPayload + LORA_MAC_FRMPAYLOAD_OVERHEAD ); + DBG_PRINTF("RX on freq %u Hz at DR %d\n\r", (unsigned int)frequency, dr); + + *datarate = (uint8_t) dr; + return true; +} + +bool RegionEU433TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) +{ + RadioModems_t modem; + int8_t phyDr = DataratesEU433[txConfig->Datarate]; + int8_t txPowerLimited = LimitTxPower( txConfig->TxPower, Bands[Channels[txConfig->Channel].Band].TxMaxPower, txConfig->Datarate, ChannelsMask ); + uint32_t bandwidth = GetBandwidth( txConfig->Datarate ); + int8_t phyTxPower = 0; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, txConfig->MaxEirp, txConfig->AntennaGain ); + + // Setup the radio frequency + Radio.SetChannel( Channels[txConfig->Channel].Frequency ); + + if( txConfig->Datarate == DR_7 ) + { // High Speed FSK channel + modem = MODEM_FSK; + Radio.SetTxConfig( modem, phyTxPower, 25000, bandwidth, phyDr * 1000, 0, 5, false, true, 0, 0, false, 3000 ); + } + else + { + modem = MODEM_LORA; + Radio.SetTxConfig( modem, phyTxPower, 0, bandwidth, phyDr, 1, 8, false, true, 0, 0, false, 3e3 ); + } + DBG_PRINTF("TX on freq %u Hz at DR %d\n\r", (unsigned int)Channels[txConfig->Channel].Frequency, txConfig->Datarate); + // Setup maximum payload lenght of the radio driver + Radio.SetMaxPayloadLength( modem, txConfig->PktLen ); + // Get the time-on-air of the next tx frame + *txTimeOnAir = Radio.TimeOnAir( modem, txConfig->PktLen ); + + *txPower = txConfig->TxPower; + return true; +} + +uint8_t RegionEU433LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ) +{ + uint8_t status = 0x07; + LinkAdrParams_t linkAdrParams; + uint8_t nextIndex = 0; + uint8_t bytesProcessed = 0; + uint16_t chMask = 0; + + while( bytesProcessed < linkAdrReq->PayloadSize ) + { + // Get ADR request parameters + nextIndex = RegionCommonParseLinkAdrReq( &( linkAdrReq->Payload[bytesProcessed] ), &linkAdrParams ); + + if( nextIndex == 0 ) + break; // break loop, since no more request has been found + + // Update bytes processed + bytesProcessed += nextIndex; + + // Revert status, as we only check the last ADR request for the channel mask KO + status = 0x07; + + // Setup temporary channels mask + chMask = linkAdrParams.ChMask; + + // Verify channels mask + if( ( linkAdrParams.ChMaskCtrl == 0 ) && ( chMask == 0 ) ) + { + status &= 0xFE; // Channel mask KO + } + else if( ( ( linkAdrParams.ChMaskCtrl >= 1 ) && ( linkAdrParams.ChMaskCtrl <= 5 )) || + ( linkAdrParams.ChMaskCtrl >= 7 ) ) + { + // RFU + status &= 0xFE; // Channel mask KO + } + else + { + for( uint8_t i = 0; i < EU433_MAX_NB_CHANNELS; i++ ) + { + if( linkAdrParams.ChMaskCtrl == 6 ) + { + if( Channels[i].Frequency != 0 ) + { + chMask |= 1 << i; + } + } + else + { + if( ( ( chMask & ( 1 << i ) ) != 0 ) && + ( Channels[i].Frequency == 0 ) ) + {// Trying to enable an undefined channel + status &= 0xFE; // Channel mask KO + } + } + } + } + } + + // Verify datarate + if( RegionCommonChanVerifyDr( EU433_MAX_NB_CHANNELS, &chMask, linkAdrParams.Datarate, EU433_TX_MIN_DATARATE, EU433_TX_MAX_DATARATE, Channels ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify tx power + if( RegionCommonValueInRange( linkAdrParams.TxPower, EU433_MAX_TX_POWER, EU433_MIN_TX_POWER ) == 0 ) + { + // Verify if the maximum TX power is exceeded + if( EU433_MAX_TX_POWER > linkAdrParams.TxPower ) + { // Apply maximum TX power. Accept TX power. + linkAdrParams.TxPower = EU433_MAX_TX_POWER; + } + else + { + status &= 0xFB; // TxPower KO + } + } + + // Update channelsMask if everything is correct + if( status == 0x07 ) + { + if( linkAdrParams.NbRep == 0 ) + { // Value of 0 is not allowed, revert to default. + linkAdrParams.NbRep = 1; + } + + // Set the channels mask to a default value + memset( ChannelsMask, 0, sizeof( ChannelsMask ) ); + // Update the channels mask + ChannelsMask[0] = chMask; + } + + // Update status variables + *drOut = linkAdrParams.Datarate; + *txPowOut = linkAdrParams.TxPower; + *nbRepOut = linkAdrParams.NbRep; + *nbBytesParsed = bytesProcessed; + + return status; +} + +uint8_t RegionEU433RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ) +{ + uint8_t status = 0x07; + + // Verify radio frequency + if( Radio.CheckRfFrequency( rxParamSetupReq->Frequency ) == false ) + { + status &= 0xFE; // Channel frequency KO + } + + // Verify datarate + if( RegionCommonValueInRange( rxParamSetupReq->Datarate, EU433_RX_MIN_DATARATE, EU433_RX_MAX_DATARATE ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify datarate offset + if( RegionCommonValueInRange( rxParamSetupReq->DrOffset, EU433_MIN_RX1_DR_OFFSET, EU433_MAX_RX1_DR_OFFSET ) == false ) + { + status &= 0xFB; // Rx1DrOffset range KO + } + + return status; +} + +uint8_t RegionEU433NewChannelReq( NewChannelReqParams_t* newChannelReq ) +{ + uint8_t status = 0x03; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + if( newChannelReq->NewChannel->Frequency == 0 ) + { + channelRemove.ChannelId = newChannelReq->ChannelId; + + // Remove + if( RegionEU433ChannelsRemove( &channelRemove ) == false ) + { + status &= 0xFC; + } + } + else + { + channelAdd.NewChannel = newChannelReq->NewChannel; + channelAdd.ChannelId = newChannelReq->ChannelId; + + switch( RegionEU433ChannelAdd( &channelAdd ) ) + { + case LORAMAC_STATUS_OK: + { + break; + } + case LORAMAC_STATUS_FREQUENCY_INVALID: + { + status &= 0xFE; + break; + } + case LORAMAC_STATUS_DATARATE_INVALID: + { + status &= 0xFD; + break; + } + case LORAMAC_STATUS_FREQ_AND_DR_INVALID: + { + status &= 0xFC; + break; + } + default: + { + status &= 0xFC; + break; + } + } + } + + return status; +} + +int8_t RegionEU433TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ) +{ + return -1; +} + +uint8_t RegionEU433DlChannelReq( DlChannelReqParams_t* dlChannelReq ) +{ + uint8_t status = 0x03; + + // Verify if the frequency is supported + if( VerifyTxFreq( dlChannelReq->Rx1Frequency ) == false ) + { + status &= 0xFE; + } + + // Verify if an uplink frequency exists + if( Channels[dlChannelReq->ChannelId].Frequency == 0 ) + { + status &= 0xFD; + } + + // Apply Rx1 frequency, if the status is OK + if( status == 0x03 ) + { + Channels[dlChannelReq->ChannelId].Rx1Frequency = dlChannelReq->Rx1Frequency; + } + + return status; +} + +int8_t RegionEU433AlternateDr( AlternateDrParams_t* alternateDr ) +{ + int8_t datarate = 0; + + if( ( alternateDr->NbTrials % 48 ) == 0 ) + { + datarate = DR_0; + } + else if( ( alternateDr->NbTrials % 32 ) == 0 ) + { + datarate = DR_1; + } + else if( ( alternateDr->NbTrials % 24 ) == 0 ) + { + datarate = DR_2; + } + else if( ( alternateDr->NbTrials % 16 ) == 0 ) + { + datarate = DR_3; + } + else if( ( alternateDr->NbTrials % 8 ) == 0 ) + { + datarate = DR_4; + } + else + { + datarate = DR_5; + } + return datarate; +} + +void RegionEU433CalcBackOff( CalcBackOffParams_t* calcBackOff ) +{ + uint8_t channel = calcBackOff->Channel; + uint16_t dutyCycle = Bands[Channels[channel].Band].DCycle; + uint16_t joinDutyCycle = 0; + + // Reset time-off to initial value. + Bands[Channels[channel].Band].TimeOff = 0; + + if( calcBackOff->Joined == false ) + { + // Get the join duty cycle + joinDutyCycle = RegionCommonGetJoinDc( calcBackOff->ElapsedTime ); + // Apply the most restricting duty cycle + dutyCycle = MAX( dutyCycle, joinDutyCycle ); + // Apply band time-off. + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + else + { + if( calcBackOff->DutyCycleEnabled == true ) + { + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + } +} + +bool RegionEU433NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTx = 0; + uint8_t enabledChannels[EU433_MAX_NB_CHANNELS] = { 0 }; + TimerTime_t nextTxDelay = 0; + + if( RegionCommonCountChannels( ChannelsMask, 0, 1 ) == 0 ) + { // Reactivate default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + } + + if( nextChanParams->AggrTimeOff <= TimerGetElapsedTime( nextChanParams->LastAggrTx ) ) + { + // Reset Aggregated time off + *aggregatedTimeOff = 0; + + // Update bands Time OFF + nextTxDelay = RegionCommonUpdateBandTimeOff( nextChanParams->Joined, nextChanParams->DutyCycleEnabled, Bands, EU433_MAX_NB_BANDS ); + + // Search how many channels are enabled + nbEnabledChannels = CountNbOfEnabledChannels( nextChanParams->Joined, nextChanParams->Datarate, + ChannelsMask, Channels, + Bands, enabledChannels, &delayTx ); + } + else + { + delayTx++; + nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx ); + } + + if( nbEnabledChannels > 0 ) + { + // We found a valid channel + *channel = enabledChannels[randr( 0, nbEnabledChannels - 1 )]; + + *time = 0; + return true; + } + else + { + if( delayTx > 0 ) + { + // Delay transmission due to AggregatedTimeOff or to a band time off + *time = nextTxDelay; + return true; + } + // Datarate not supported by any channel, restore defaults + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + *time = 0; + return false; + } +} + +LoRaMacStatus_t RegionEU433ChannelAdd( ChannelAddParams_t* channelAdd ) +{ + uint8_t band = 0; + bool drInvalid = false; + bool freqInvalid = false; + uint8_t id = channelAdd->ChannelId; + + if( id >= EU433_MAX_NB_CHANNELS ) + { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + + // Validate the datarate range + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Min, EU433_TX_MIN_DATARATE, EU433_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, EU433_TX_MIN_DATARATE, EU433_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( channelAdd->NewChannel->DrRange.Fields.Min > channelAdd->NewChannel->DrRange.Fields.Max ) + { + drInvalid = true; + } + + // Default channels don't accept all values + if( id < EU433_NUMB_DEFAULT_CHANNELS ) + { + // Validate the datarate range for min: must be DR_0 + if( channelAdd->NewChannel->DrRange.Fields.Min > DR_0 ) + { + drInvalid = true; + } + // Validate the datarate range for max: must be DR_5 <= Max <= TX_MAX_DATARATE + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, DR_5, EU433_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + // We are not allowed to change the frequency + if( channelAdd->NewChannel->Frequency != Channels[id].Frequency ) + { + freqInvalid = true; + } + } + + // Check frequency + if( freqInvalid == false ) + { + if( VerifyTxFreq( channelAdd->NewChannel->Frequency ) == false ) + { + freqInvalid = true; + } + } + + // Check status + if( ( drInvalid == true ) && ( freqInvalid == true ) ) + { + return LORAMAC_STATUS_FREQ_AND_DR_INVALID; + } + if( drInvalid == true ) + { + return LORAMAC_STATUS_DATARATE_INVALID; + } + if( freqInvalid == true ) + { + return LORAMAC_STATUS_FREQUENCY_INVALID; + } + + memcpy( &(Channels[id]), channelAdd->NewChannel, sizeof( Channels[id] ) ); + Channels[id].Band = band; + ChannelsMask[0] |= ( 1 << id ); + return LORAMAC_STATUS_OK; +} + +bool RegionEU433ChannelsRemove( ChannelRemoveParams_t* channelRemove ) +{ + uint8_t id = channelRemove->ChannelId; + + if( id < EU433_NUMB_DEFAULT_CHANNELS ) + { + return false; + } + + // Remove the channel from the list of channels + Channels[id] = ( ChannelParams_t ){ 0, 0, { 0 }, 0 }; + + return RegionCommonChanDisable( ChannelsMask, id, EU433_MAX_NB_CHANNELS ); +} + +void RegionEU433SetContinuousWave( ContinuousWaveParams_t* continuousWave ) +{ + int8_t txPowerLimited = LimitTxPower( continuousWave->TxPower, Bands[Channels[continuousWave->Channel].Band].TxMaxPower, continuousWave->Datarate, ChannelsMask ); + int8_t phyTxPower = 0; + uint32_t frequency = Channels[continuousWave->Channel].Frequency; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, continuousWave->MaxEirp, continuousWave->AntennaGain ); + + Radio.SetTxContinuousWave( frequency, phyTxPower, continuousWave->Timeout ); +} + +uint8_t RegionEU433ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +{ + int8_t datarate = dr - drOffset; + + if( datarate < 0 ) + { + datarate = DR_0; + } + return datarate; +} + +void RegionEU433RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ) +{ + RegionCommonRxBeaconSetupParams_t regionCommonRxBeaconSetup; + + regionCommonRxBeaconSetup.Datarates = DataratesEU433; + regionCommonRxBeaconSetup.Frequency = rxBeaconSetup->Frequency; + regionCommonRxBeaconSetup.BeaconSize = EU433_BEACON_SIZE; + regionCommonRxBeaconSetup.BeaconDatarate = EU433_BEACON_CHANNEL_DR; + regionCommonRxBeaconSetup.BeaconChannelBW = EU433_BEACON_CHANNEL_BW; + regionCommonRxBeaconSetup.RxTime = rxBeaconSetup->RxTime; + regionCommonRxBeaconSetup.SymbolTimeout = rxBeaconSetup->SymbolTimeout; + + RegionCommonRxBeaconSetup( ®ionCommonRxBeaconSetup ); + + // Store downlink datarate + *outDr = EU433_BEACON_CHANNEL_DR; +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU433.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU433.h new file mode 100644 index 00000000..9d430b60 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU433.h @@ -0,0 +1,512 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file RegionEU433.h + * + * \brief Region definition for EU433 + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGIONEU433 Region EU433 + * Implementation according to LoRaWAN Specification v1.0.2. + * \{ + */ +#ifndef __REGION_EU433_H__ +#define __REGION_EU433_H__ + +#include "LoRaMac.h" + +/*! + * LoRaMac maximum number of channels + */ +#define EU433_MAX_NB_CHANNELS 16 + +/*! + * Number of default channels + */ +#define EU433_NUMB_DEFAULT_CHANNELS 3 + +/*! + * Number of channels to apply for the CF list + */ +#define EU433_NUMB_CHANNELS_CF_LIST 5 + +/*! + * Minimal datarate that can be used by the node + */ +#define EU433_TX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define EU433_TX_MAX_DATARATE DR_7 + +/*! + * Minimal datarate that can be used by the node + */ +#define EU433_RX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define EU433_RX_MAX_DATARATE DR_7 + +/*! + * Default datarate used by the node + */ +#define EU433_DEFAULT_DATARATE DR_0 + +/*! + * Minimal Rx1 receive datarate offset + */ +#define EU433_MIN_RX1_DR_OFFSET 0 + +/*! + * Maximal Rx1 receive datarate offset + */ +#define EU433_MAX_RX1_DR_OFFSET 5 + +/*! + * Default Rx1 receive datarate offset + */ +#define EU433_DEFAULT_RX1_DR_OFFSET 0 + +/*! + * Minimal Tx output power that can be used by the node + */ +#define EU433_MIN_TX_POWER TX_POWER_5 + +/*! + * Maximal Tx output power that can be used by the node + */ +#define EU433_MAX_TX_POWER TX_POWER_0 + +/*! + * Default Tx output power used by the node + */ +#define EU433_DEFAULT_TX_POWER TX_POWER_0 + +/*! + * Default Max EIRP + */ +#define EU433_DEFAULT_MAX_EIRP 12.15f + +/*! + * Default antenna gain + */ +#define EU433_DEFAULT_ANTENNA_GAIN 2.15f + +/*! + * ADR Ack limit + */ +#define EU433_ADR_ACK_LIMIT 64 + +/*! + * ADR Ack delay + */ +#define EU433_ADR_ACK_DELAY 32 + +/*! + * Enabled or disabled the duty cycle + */ +#define EU433_DUTY_CYCLE_ENABLED 1 + +/*! + * Maximum RX window duration + */ +#define EU433_MAX_RX_WINDOW 3000 + +/*! + * Receive delay 1 + */ +#define EU433_RECEIVE_DELAY1 1000 + +/*! + * Receive delay 2 + */ +#define EU433_RECEIVE_DELAY2 2000 + +/*! + * Join accept delay 1 + */ +#define EU433_JOIN_ACCEPT_DELAY1 5000 + +/*! + * Join accept delay 2 + */ +#define EU433_JOIN_ACCEPT_DELAY2 6000 + +/*! + * Maximum frame counter gap + */ +#define EU433_MAX_FCNT_GAP 16384 + +/*! + * Ack timeout + */ +#define EU433_ACKTIMEOUT 2000 + +/*! + * Random ack timeout limits + */ +#define EU433_ACK_TIMEOUT_RND 1000 + +/*! + * Verification of default datarate + */ +#if ( EU433_DEFAULT_DATARATE > DR_5 ) +#error "A default DR higher than DR_5 may lead to connectivity loss." +#endif + +/*! + * Second reception window channel frequency definition. + */ +#define EU433_RX_WND_2_FREQ 434665000 + +/*! + * Second reception window channel datarate definition. + */ +#define EU433_RX_WND_2_DR DR_0 + +/*! + * LoRaMac maximum number of bands + */ +#define EU433_MAX_NB_BANDS 1 + +/* + * CLASS B + */ +/*! + * Beacon frequency + */ +#define EU433_BEACON_CHANNEL_FREQ 434665000 + +/*! + * Payload size of a beacon frame + */ +#define EU433_BEACON_SIZE 17 + +/*! + * Size of RFU 1 field + */ +#define EU433_RFU1_SIZE 2 + +/*! + * Size of RFU 2 field + */ +#define EU433_RFU2_SIZE 0 + +/*! + * Datarate of the beacon channel + */ +#define EU433_BEACON_CHANNEL_DR DR_3 + +/*! + * Bandwith of the beacon channel + */ +#define EU433_BEACON_CHANNEL_BW 0 + +/*! + * Band 0 definition + * { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define EU433_BAND0 { 100, EU433_MAX_TX_POWER, 0, 0 } // 1.0 % + +/*! + * LoRaMac default channel 1 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define EU433_LC1 { 433175000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac default channel 2 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define EU433_LC2 { 433375000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac default channel 3 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define EU433_LC3 { 433575000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac channels which are allowed for the join procedure + */ +#define EU433_JOIN_CHANNELS ( uint16_t )( LC( 1 ) | LC( 2 ) | LC( 3 ) ) + +/*! + * Data rates table definition + */ +static const uint8_t DataratesEU433[] = { 12, 11, 10, 9, 8, 7, 7, 50 }; + +/*! + * Bandwidths table definition in Hz + */ +static const uint32_t BandwidthsEU433[] = { 125000, 125000, 125000, 125000, 125000, 125000, 250000, 0 }; + +/*! + * Maximum payload with respect to the datarate index. Cannot operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateEU433[] = { 51, 51, 51, 115, 242, 242, 242, 242 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateRepeaterEU433[] = { 51, 51, 51, 115, 222, 222, 222, 222 }; + +/*! + * \brief The function gets a value of a specific phy attribute. + * + * \param [IN] getPhy Pointer to the function parameters. + * + * \retval Returns a structure containing the PHY parameter. + */ +PhyParam_t RegionEU433GetPhyParam( GetPhyParams_t* getPhy ); + +/*! + * \brief Updates the last TX done parameters of the current channel. + * + * \param [IN] txDone Pointer to the function parameters. + */ +void RegionEU433SetBandTxDone( SetBandTxDoneParams_t* txDone ); + +/*! + * \brief Initializes the channels masks and the channels. + * + * \param [IN] type Sets the initialization type. + */ +void RegionEU433InitDefaults( InitType_t type ); + +/*! + * \brief Verifies a parameter. + * + * \param [IN] verify Pointer to the function parameters. + * + * \param [IN] type Sets the initialization type. + * + * \retval Returns true, if the parameter is valid. + */ +bool RegionEU433Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ); + +/*! + * \brief The function parses the input buffer and sets up the channels of the + * CF list. + * + * \param [IN] applyCFList Pointer to the function parameters. + */ +void RegionEU433ApplyCFList( ApplyCFListParams_t* applyCFList ); + +/*! + * \brief Sets a channels mask. + * + * \param [IN] chanMaskSet Pointer to the function parameters. + * + * \retval Returns true, if the channels mask could be set. + */ +bool RegionEU433ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ); + +/*! + * \brief Calculates the next datarate to set, when ADR is on or off. + * + * \param [IN] adrNext Pointer to the function parameters. + * + * \param [OUT] drOut The calculated datarate for the next TX. + * + * \param [OUT] txPowOut The TX power for the next TX. + * + * \param [OUT] adrAckCounter The calculated ADR acknowledgement counter. + * + * \retval Returns true, if an ADR request should be performed. + */ +bool RegionEU433AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ); + +/*! + * Computes the Rx window timeout and offset. + * + * \param [IN] datarate Rx window datarate index to be used + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms + * interval around RxOffset + * + * \param [OUT]rxConfigParams Returns updated WindowTimeout and WindowOffset fields. + */ +void RegionEU433ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ); + +/*! + * \brief Configuration of the RX windows. + * + * \param [IN] rxConfig Pointer to the function parameters. + * + * \param [OUT] datarate The datarate index which was set. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionEU433RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ); + +/*! + * \brief TX configuration. + * + * \param [IN] txConfig Pointer to the function parameters. + * + * \param [OUT] txPower The tx power index which was set. + * + * \param [OUT] txTimeOnAir The time-on-air of the frame. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionEU433TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ); + +/*! + * \brief The function processes a Link ADR Request. + * + * \param [IN] linkAdrReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionEU433LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ); + +/*! + * \brief The function processes a RX Parameter Setup Request. + * + * \param [IN] rxParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionEU433RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ); + +/*! + * \brief The function processes a Channel Request. + * + * \param [IN] newChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionEU433NewChannelReq( NewChannelReqParams_t* newChannelReq ); + +/*! + * \brief The function processes a TX ParamSetup Request. + * + * \param [IN] txParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + * Returns -1, if the functionality is not implemented. In this case, the end node + * shall not process the command. + */ +int8_t RegionEU433TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ); + +/*! + * \brief The function processes a DlChannel Request. + * + * \param [IN] dlChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionEU433DlChannelReq( DlChannelReqParams_t* dlChannelReq ); + +/*! + * \brief Alternates the datarate of the channel for the join request. + * + * \param [IN] alternateDr Pointer to the function parameters. + * + * \retval Datarate to apply. + */ +int8_t RegionEU433AlternateDr( AlternateDrParams_t* alternateDr ); + +/*! + * \brief Calculates the back-off time. + * + * \param [IN] calcBackOff Pointer to the function parameters. + */ +void RegionEU433CalcBackOff( CalcBackOffParams_t* calcBackOff ); + +/*! + * \brief Searches and set the next random available channel + * + * \param [OUT] channel Next channel to use for TX. + * + * \param [OUT] time Time to wait for the next transmission according to the duty + * cycle. + * + * \param [OUT] aggregatedTimeOff Updates the aggregated time off. + * + * \retval Function status [1: OK, 0: Unable to find a channel on the current datarate] + */ +bool RegionEU433NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ); + +/*! + * \brief Adds a channel. + * + * \param [IN] channelAdd Pointer to the function parameters. + * + * \retval Status of the operation. + */ +LoRaMacStatus_t RegionEU433ChannelAdd( ChannelAddParams_t* channelAdd ); + +/*! + * \brief Removes a channel. + * + * \param [IN] channelRemove Pointer to the function parameters. + * + * \retval Returns true, if the channel was removed successfully. + */ +bool RegionEU433ChannelsRemove( ChannelRemoveParams_t* channelRemove ); + +/*! + * \brief Sets the radio into continuous wave mode. + * + * \param [IN] continuousWave Pointer to the function parameters. + */ +void RegionEU433SetContinuousWave( ContinuousWaveParams_t* continuousWave ); + +/*! + * \brief Computes new datarate according to the given offset + * + * \param [IN] downlinkDwellTime Downlink dwell time configuration. 0: No limit, 1: 400ms + * + * \param [IN] dr Current datarate + * + * \param [IN] drOffset Offset to be applied + * + * \retval newDr Computed datarate. + */ +uint8_t RegionEU433ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ); + +/*! + * \brief Sets the radio into beacon reception mode + * + * \param [IN] rxBeaconSetup Pointer to the function parameters + */ + void RegionEU433RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ); + +/*! \} defgroup REGIONEU433 */ + +#endif // __REGION_EU433_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU868.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU868.c new file mode 100644 index 00000000..e21078a0 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU868.c @@ -0,0 +1,1129 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC region EU868 implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include +#include + +#include "radio.h" +//#include "timer.h" +#include "timeServer.h" +#include "LoRaMac.h" + +#include "utilities.h" + +#include "Region.h" +#include "RegionCommon.h" +#include "RegionEU868.h" +#include "debug.h" + +// Definitions +#define CHANNELS_MASK_SIZE 1 + +// Global attributes +/*! + * LoRaMAC channels + */ +static ChannelParams_t Channels[EU868_MAX_NB_CHANNELS]; + +/*! + * LoRaMac bands + */ +static Band_t Bands[EU868_MAX_NB_BANDS] = +{ + EU868_BAND0, + EU868_BAND1, + EU868_BAND2, + EU868_BAND3, + EU868_BAND4, +}; + +/*! + * LoRaMac channels mask + */ +static uint16_t ChannelsMask[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels default mask + */ +static uint16_t ChannelsDefaultMask[CHANNELS_MASK_SIZE]; + +// Static functions +static int8_t GetNextLowerTxDr( int8_t dr, int8_t minDr ) +{ + uint8_t nextLowerDr = 0; + + if( dr == minDr ) + { + nextLowerDr = minDr; + } + else + { + nextLowerDr = dr - 1; + } + return nextLowerDr; +} + +static uint32_t GetBandwidth( uint32_t drIndex ) +{ + switch( BandwidthsEU868[drIndex] ) + { + default: + case 125000: + return 0; + case 250000: + return 1; + case 500000: + return 2; + } +} + +static int8_t LimitTxPower( int8_t txPower, int8_t maxBandTxPower, int8_t datarate, uint16_t* channelsMask ) +{ + int8_t txPowerResult = txPower; + + // Limit tx power to the band max + txPowerResult = MAX( txPower, maxBandTxPower ); + + return txPowerResult; +} + +static bool VerifyTxFreq( uint32_t freq, uint8_t *band ) +{ + // Check radio driver support + if( Radio.CheckRfFrequency( freq ) == false ) + { + return false; + } + + // Check frequency bands + if( ( freq >= 863000000 ) && ( freq < 865000000 ) ) + { + *band = 2; + } + else if( ( freq >= 865000000 ) && ( freq <= 868000000 ) ) + { + *band = 0; + } + else if( ( freq > 868000000 ) && ( freq <= 868600000 ) ) + { + *band = 1; + } + else if( ( freq >= 868700000 ) && ( freq <= 869200000 ) ) + { + *band = 2; + } + else if( ( freq >= 869400000 ) && ( freq <= 869650000 ) ) + { + *band = 3; + } + else if( ( freq >= 869700000 ) && ( freq <= 870000000 ) ) + { + *band = 4; + } + else + { + return false; + } + return true; +} + +static uint8_t CountNbOfEnabledChannels( bool joined, uint8_t datarate, uint16_t* channelsMask, ChannelParams_t* channels, Band_t* bands, uint8_t* enabledChannels, uint8_t* delayTx ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTransmission = 0; + + for( uint8_t i = 0, k = 0; i < EU868_MAX_NB_CHANNELS; i += 16, k++ ) + { + for( uint8_t j = 0; j < 16; j++ ) + { + if( ( channelsMask[k] & ( 1 << j ) ) != 0 ) + { + if( channels[i + j].Frequency == 0 ) + { // Check if the channel is enabled + continue; + } + if( joined == false ) + { + if( ( EU868_JOIN_CHANNELS & ( 1 << j ) ) == 0 ) + { + continue; + } + } + if( RegionCommonValueInRange( datarate, channels[i + j].DrRange.Fields.Min, + channels[i + j].DrRange.Fields.Max ) == false ) + { // Check if the current channel selection supports the given datarate + continue; + } + if( bands[channels[i + j].Band].TimeOff > 0 ) + { // Check if the band is available for transmission + delayTransmission++; + continue; + } + enabledChannels[nbEnabledChannels++] = i + j; + } + } + } + + *delayTx = delayTransmission; + return nbEnabledChannels; +} + +PhyParam_t RegionEU868GetPhyParam( GetPhyParams_t* getPhy ) +{ + PhyParam_t phyParam = { 0 }; + + switch( getPhy->Attribute ) + { + case PHY_MIN_RX_DR: + { + phyParam.Value = EU868_RX_MIN_DATARATE; + break; + } + case PHY_MIN_TX_DR: + { + phyParam.Value = EU868_TX_MIN_DATARATE; + break; + } + case PHY_DEF_TX_DR: + { + phyParam.Value = EU868_DEFAULT_DATARATE; + break; + } + case PHY_NEXT_LOWER_TX_DR: + { + phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, EU868_TX_MIN_DATARATE ); + break; + } + case PHY_DEF_TX_POWER: + { + phyParam.Value = EU868_DEFAULT_TX_POWER; + break; + } + case PHY_MAX_PAYLOAD: + { + phyParam.Value = MaxPayloadOfDatarateEU868[getPhy->Datarate]; + break; + } + case PHY_MAX_PAYLOAD_REPEATER: + { + phyParam.Value = MaxPayloadOfDatarateRepeaterEU868[getPhy->Datarate]; + break; + } + case PHY_DUTY_CYCLE: + { + phyParam.Value = EU868_DUTY_CYCLE_ENABLED; + break; + } + case PHY_MAX_RX_WINDOW: + { + phyParam.Value = EU868_MAX_RX_WINDOW; + break; + } + case PHY_RECEIVE_DELAY1: + { + phyParam.Value = EU868_RECEIVE_DELAY1; + break; + } + case PHY_RECEIVE_DELAY2: + { + phyParam.Value = EU868_RECEIVE_DELAY2; + break; + } + case PHY_JOIN_ACCEPT_DELAY1: + { + phyParam.Value = EU868_JOIN_ACCEPT_DELAY1; + break; + } + case PHY_JOIN_ACCEPT_DELAY2: + { + phyParam.Value = EU868_JOIN_ACCEPT_DELAY2; + break; + } + case PHY_MAX_FCNT_GAP: + { + phyParam.Value = EU868_MAX_FCNT_GAP; + break; + } + case PHY_ACK_TIMEOUT: + { + phyParam.Value = ( EU868_ACKTIMEOUT + randr( -EU868_ACK_TIMEOUT_RND, EU868_ACK_TIMEOUT_RND ) ); + break; + } + case PHY_DEF_DR1_OFFSET: + { + phyParam.Value = EU868_DEFAULT_RX1_DR_OFFSET; + break; + } + case PHY_DEF_RX2_FREQUENCY: + { + phyParam.Value = EU868_RX_WND_2_FREQ; + break; + } + case PHY_DEF_RX2_DR: + { + phyParam.Value = EU868_RX_WND_2_DR; + break; + } + case PHY_CHANNELS_MASK: + { + phyParam.ChannelsMask = ChannelsMask; + break; + } + case PHY_CHANNELS_DEFAULT_MASK: + { + phyParam.ChannelsMask = ChannelsDefaultMask; + break; + } + case PHY_MAX_NB_CHANNELS: + { + phyParam.Value = EU868_MAX_NB_CHANNELS; + break; + } + case PHY_CHANNELS: + { + phyParam.Channels = Channels; + break; + } + case PHY_DEF_UPLINK_DWELL_TIME: + case PHY_DEF_DOWNLINK_DWELL_TIME: + { + phyParam.Value = 0; + break; + } + case PHY_DEF_MAX_EIRP: + { + phyParam.fValue = EU868_DEFAULT_MAX_EIRP; + break; + } + case PHY_DEF_ANTENNA_GAIN: + { + phyParam.fValue = EU868_DEFAULT_ANTENNA_GAIN; + break; + } + case PHY_NB_JOIN_TRIALS: + case PHY_DEF_NB_JOIN_TRIALS: + { + phyParam.Value = 48; + break; + } + case PHY_BEACON_CHANNEL_FREQ: + { + phyParam.Value = EU868_BEACON_CHANNEL_FREQ; + break; + } + case PHY_BEACON_FORMAT: + { + phyParam.BeaconFormat.BeaconSize = EU868_BEACON_SIZE; + phyParam.BeaconFormat.Rfu1Size = EU868_RFU1_SIZE; + phyParam.BeaconFormat.Rfu2Size = EU868_RFU2_SIZE; + break; + } + case PHY_BEACON_CHANNEL_DR: + { + phyParam.Value = EU868_BEACON_CHANNEL_DR; + break; + } + default: + { + break; + } + } + + return phyParam; +} + +void RegionEU868SetBandTxDone( SetBandTxDoneParams_t* txDone ) +{ + RegionCommonSetBandTxDone( txDone->Joined, &Bands[Channels[txDone->Channel].Band], txDone->LastTxDoneTime ); +} + +void RegionEU868InitDefaults( InitType_t type ) +{ + switch( type ) + { + case INIT_TYPE_INIT: + { + // Channels + Channels[0] = ( ChannelParams_t ) EU868_LC1; + Channels[1] = ( ChannelParams_t ) EU868_LC2; + Channels[2] = ( ChannelParams_t ) EU868_LC3; + + // Initialize the channels default mask + ChannelsDefaultMask[0] = LC( 1 ) + LC( 2 ) + LC( 3 ); + // Update the channels mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 1 ); + break; + } + case INIT_TYPE_RESTORE: + { + // Restore channels default mask + ChannelsMask[0] |= ChannelsDefaultMask[0]; + break; + } + default: + { + break; + } + } +} + +bool RegionEU868Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ) +{ + switch( phyAttribute ) + { + case PHY_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, EU868_TX_MIN_DATARATE, EU868_TX_MAX_DATARATE ); + } + case PHY_DEF_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, DR_0, DR_5 ); + } + case PHY_RX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, EU868_RX_MIN_DATARATE, EU868_RX_MAX_DATARATE ); + } + case PHY_DEF_TX_POWER: + case PHY_TX_POWER: + { + // Remark: switched min and max! + return RegionCommonValueInRange( verify->TxPower, EU868_MAX_TX_POWER, EU868_MIN_TX_POWER ); + } + case PHY_DUTY_CYCLE: + { + return EU868_DUTY_CYCLE_ENABLED; + } + case PHY_NB_JOIN_TRIALS: + { + if( verify->NbJoinTrials < 48 ) + { + return false; + } + break; + } + default: + return false; + } + return true; +} + +void RegionEU868ApplyCFList( ApplyCFListParams_t* applyCFList ) +{ + ChannelParams_t newChannel; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + // Setup default datarate range + newChannel.DrRange.Value = ( DR_5 << 4 ) | DR_0; + + // Size of the optional CF list + if( applyCFList->Size != 16 ) + { + return; + } + + // Last byte is RFU, don't take it into account + for( uint8_t i = 0, chanIdx = EU868_NUMB_DEFAULT_CHANNELS; chanIdx < EU868_MAX_NB_CHANNELS; i+=3, chanIdx++ ) + { + if( chanIdx < ( EU868_NUMB_CHANNELS_CF_LIST + EU868_NUMB_DEFAULT_CHANNELS ) ) + { + // Channel frequency + newChannel.Frequency = (uint32_t) applyCFList->Payload[i]; + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 1] << 8 ); + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 2] << 16 ); + newChannel.Frequency *= 100; + + // Initialize alternative frequency to 0 + newChannel.Rx1Frequency = 0; + } + else + { + newChannel.Frequency = 0; + newChannel.DrRange.Value = 0; + newChannel.Rx1Frequency = 0; + } + + if( newChannel.Frequency != 0 ) + { + channelAdd.NewChannel = &newChannel; + channelAdd.ChannelId = chanIdx; + + // Try to add all channels + RegionEU868ChannelAdd( &channelAdd ); + } + else + { + channelRemove.ChannelId = chanIdx; + + RegionEU868ChannelsRemove( &channelRemove ); + } + } +} + +bool RegionEU868ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ) +{ + switch( chanMaskSet->ChannelsMaskType ) + { + case CHANNELS_MASK: + { + RegionCommonChanMaskCopy( ChannelsMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + case CHANNELS_DEFAULT_MASK: + { + RegionCommonChanMaskCopy( ChannelsDefaultMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + default: + return false; + } + return true; +} + +bool RegionEU868AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ) +{ + bool adrAckReq = false; + int8_t datarate = adrNext->Datarate; + int8_t txPower = adrNext->TxPower; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + // Report back the adr ack counter + *adrAckCounter = adrNext->AdrAckCounter; + + if( adrNext->AdrEnabled == true ) + { + if( datarate == EU868_TX_MIN_DATARATE ) + { + *adrAckCounter = 0; + adrAckReq = false; + } + else + { + if( adrNext->AdrAckCounter >= EU868_ADR_ACK_LIMIT ) + { + adrAckReq = true; + txPower = EU868_MAX_TX_POWER; + } + else + { + adrAckReq = false; + } + if( adrNext->AdrAckCounter >= ( EU868_ADR_ACK_LIMIT + EU868_ADR_ACK_DELAY ) ) + { + if( ( adrNext->AdrAckCounter % EU868_ADR_ACK_DELAY ) == 1 ) + { + // Decrease the datarate + getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + getPhy.Datarate = datarate; + getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + phyParam = RegionEU868GetPhyParam( &getPhy ); + datarate = phyParam.Value; + + if( datarate == EU868_TX_MIN_DATARATE ) + { + // We must set adrAckReq to false as soon as we reach the lowest datarate + adrAckReq = false; + if( adrNext->UpdateChanMask == true ) + { + // Re-enable default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + } + } + } + } + } + } + + *drOut = datarate; + *txPowOut = txPower; + return adrAckReq; +} + +void RegionEU868ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ) +{ + double tSymbol = 0.0; + uint32_t radioWakeUpTime; + + rxConfigParams->Datarate = datarate; + rxConfigParams->Bandwidth = GetBandwidth( datarate ); + + if( datarate == DR_7 ) + { // FSK + tSymbol = RegionCommonComputeSymbolTimeFsk( DataratesEU868[datarate] ); + } + else + { // LoRa + tSymbol = RegionCommonComputeSymbolTimeLoRa( DataratesEU868[datarate], BandwidthsEU868[datarate] ); + } + + radioWakeUpTime = Radio.GetWakeupTime(); + RegionCommonComputeRxWindowParameters( tSymbol, minRxSymbols, rxError, radioWakeUpTime, &rxConfigParams->WindowTimeout, &rxConfigParams->WindowOffset ); +} + +bool RegionEU868RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ) +{ + RadioModems_t modem; + int8_t dr = rxConfig->Datarate; + uint8_t maxPayload = 0; + int8_t phyDr = 0; + uint32_t frequency = rxConfig->Frequency; + + if( Radio.GetStatus( ) != RF_IDLE ) + { + return false; + } + + if( rxConfig->RxSlot == RX_SLOT_WIN_1 ) + { + // Apply window 1 frequency + frequency = Channels[rxConfig->Channel].Frequency; + // Apply the alternative RX 1 window frequency, if it is available + if( Channels[rxConfig->Channel].Rx1Frequency != 0 ) + { + frequency = Channels[rxConfig->Channel].Rx1Frequency; + } + } + + // Read the physical datarate from the datarates table + phyDr = DataratesEU868[dr]; + + Radio.SetChannel( frequency ); + + // Radio configuration + if( dr == DR_7 ) + { + modem = MODEM_FSK; + Radio.SetRxConfig( modem, 50000, phyDr * 1000, 0, 83333, 5, rxConfig->WindowTimeout, false, 0, true, 0, 0, false, rxConfig->RxContinuous ); + } + else + { + modem = MODEM_LORA; + Radio.SetRxConfig( modem, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, false, 0, false, 0, 0, true, rxConfig->RxContinuous ); + } + + if( rxConfig->RepeaterSupport == true ) + { + maxPayload = MaxPayloadOfDatarateRepeaterEU868[dr]; + } + else + { + maxPayload = MaxPayloadOfDatarateEU868[dr]; + } + + Radio.SetMaxPayloadLength( modem, maxPayload + LORA_MAC_FRMPAYLOAD_OVERHEAD ); + DBG_PRINTF("RX on freq %u Hz at DR %d\n\r", (unsigned int)frequency, dr); + + *datarate = (uint8_t) dr; + return true; +} + +bool RegionEU868TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) +{ + RadioModems_t modem; + int8_t phyDr = DataratesEU868[txConfig->Datarate]; + int8_t txPowerLimited = LimitTxPower( txConfig->TxPower, Bands[Channels[txConfig->Channel].Band].TxMaxPower, txConfig->Datarate, ChannelsMask ); + uint32_t bandwidth = GetBandwidth( txConfig->Datarate ); + int8_t phyTxPower = 0; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, txConfig->MaxEirp, txConfig->AntennaGain ); + + // Setup the radio frequency + Radio.SetChannel( Channels[txConfig->Channel].Frequency ); + + if( txConfig->Datarate == DR_7 ) + { // High Speed FSK channel + modem = MODEM_FSK; + Radio.SetTxConfig( modem, phyTxPower, 25000, bandwidth, phyDr * 1000, 0, 5, false, true, 0, 0, false, 3000 ); + } + else + { + modem = MODEM_LORA; + Radio.SetTxConfig( modem, phyTxPower, 0, bandwidth, phyDr, 1, 8, false, true, 0, 0, false, 3000 ); + } + DBG_PRINTF("TX on freq %u Hz at DR %d\n\r", (unsigned int)Channels[txConfig->Channel].Frequency, txConfig->Datarate); + // Setup maximum payload lenght of the radio driver + Radio.SetMaxPayloadLength( modem, txConfig->PktLen ); + // Get the time-on-air of the next tx frame + *txTimeOnAir = Radio.TimeOnAir( modem, txConfig->PktLen ); + + *txPower = txPowerLimited; + return true; +} + +uint8_t RegionEU868LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ) +{ + uint8_t status = 0x07; + LinkAdrParams_t linkAdrParams; + uint8_t nextIndex = 0; + uint8_t bytesProcessed = 0; + uint16_t chMask = 0; + + while( bytesProcessed < linkAdrReq->PayloadSize ) + { + // Get ADR request parameters + nextIndex = RegionCommonParseLinkAdrReq( &( linkAdrReq->Payload[bytesProcessed] ), &linkAdrParams ); + + if( nextIndex == 0 ) + break; // break loop, since no more request has been found + + // Update bytes processed + bytesProcessed += nextIndex; + + // Revert status, as we only check the last ADR request for the channel mask KO + status = 0x07; + + // Setup temporary channels mask + chMask = linkAdrParams.ChMask; + + // Verify channels mask + if( ( linkAdrParams.ChMaskCtrl == 0 ) && ( chMask == 0 ) ) + { + status &= 0xFE; // Channel mask KO + } + else if( ( ( linkAdrParams.ChMaskCtrl >= 1 ) && ( linkAdrParams.ChMaskCtrl <= 5 )) || + ( linkAdrParams.ChMaskCtrl >= 7 ) ) + { + // RFU + status &= 0xFE; // Channel mask KO + } + else + { + for( uint8_t i = 0; i < EU868_MAX_NB_CHANNELS; i++ ) + { + if( linkAdrParams.ChMaskCtrl == 6 ) + { + if( Channels[i].Frequency != 0 ) + { + chMask |= 1 << i; + } + } + else + { + if( ( ( chMask & ( 1 << i ) ) != 0 ) && + ( Channels[i].Frequency == 0 ) ) + {// Trying to enable an undefined channel + status &= 0xFE; // Channel mask KO + } + } + } + } + } + + // Verify datarate + if( RegionCommonChanVerifyDr( EU868_MAX_NB_CHANNELS, &chMask, linkAdrParams.Datarate, EU868_TX_MIN_DATARATE, EU868_TX_MAX_DATARATE, Channels ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify tx power + if( RegionCommonValueInRange( linkAdrParams.TxPower, EU868_MAX_TX_POWER, EU868_MIN_TX_POWER ) == 0 ) + { + // Verify if the maximum TX power is exceeded + if( EU868_MAX_TX_POWER > linkAdrParams.TxPower ) + { // Apply maximum TX power. Accept TX power. + linkAdrParams.TxPower = EU868_MAX_TX_POWER; + } + else + { + status &= 0xFB; // TxPower KO + } + } + + // Update channelsMask if everything is correct + if( status == 0x07 ) + { + if( linkAdrParams.NbRep == 0 ) + { // Value of 0 is not allowed, revert to default. + linkAdrParams.NbRep = 1; + } + + // Set the channels mask to a default value + memset( ChannelsMask, 0, sizeof( ChannelsMask ) ); + // Update the channels mask + ChannelsMask[0] = chMask; + } + + // Update status variables + *drOut = linkAdrParams.Datarate; + *txPowOut = linkAdrParams.TxPower; + *nbRepOut = linkAdrParams.NbRep; + *nbBytesParsed = bytesProcessed; + + return status; +} + +uint8_t RegionEU868RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ) +{ + uint8_t status = 0x07; + + // Verify radio frequency + if( Radio.CheckRfFrequency( rxParamSetupReq->Frequency ) == false ) + { + status &= 0xFE; // Channel frequency KO + } + + // Verify datarate + if( RegionCommonValueInRange( rxParamSetupReq->Datarate, EU868_RX_MIN_DATARATE, EU868_RX_MAX_DATARATE ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify datarate offset + if( RegionCommonValueInRange( rxParamSetupReq->DrOffset, EU868_MIN_RX1_DR_OFFSET, EU868_MAX_RX1_DR_OFFSET ) == false ) + { + status &= 0xFB; // Rx1DrOffset range KO + } + + return status; +} + +uint8_t RegionEU868NewChannelReq( NewChannelReqParams_t* newChannelReq ) +{ + uint8_t status = 0x03; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + if( newChannelReq->NewChannel->Frequency == 0 ) + { + channelRemove.ChannelId = newChannelReq->ChannelId; + + // Remove + if( RegionEU868ChannelsRemove( &channelRemove ) == false ) + { + status &= 0xFC; + } + } + else + { + channelAdd.NewChannel = newChannelReq->NewChannel; + channelAdd.ChannelId = newChannelReq->ChannelId; + + switch( RegionEU868ChannelAdd( &channelAdd ) ) + { + case LORAMAC_STATUS_OK: + { + break; + } + case LORAMAC_STATUS_FREQUENCY_INVALID: + { + status &= 0xFE; + break; + } + case LORAMAC_STATUS_DATARATE_INVALID: + { + status &= 0xFD; + break; + } + case LORAMAC_STATUS_FREQ_AND_DR_INVALID: + { + status &= 0xFC; + break; + } + default: + { + status &= 0xFC; + break; + } + } + } + + return status; +} + +int8_t RegionEU868TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ) +{ + return -1; +} + +uint8_t RegionEU868DlChannelReq( DlChannelReqParams_t* dlChannelReq ) +{ + uint8_t status = 0x03; + uint8_t band = 0; + + // Verify if the frequency is supported + if( VerifyTxFreq( dlChannelReq->Rx1Frequency, &band ) == false ) + { + status &= 0xFE; + } + + // Verify if an uplink frequency exists + if( Channels[dlChannelReq->ChannelId].Frequency == 0 ) + { + status &= 0xFD; + } + + // Apply Rx1 frequency, if the status is OK + if( status == 0x03 ) + { + Channels[dlChannelReq->ChannelId].Rx1Frequency = dlChannelReq->Rx1Frequency; + } + + return status; +} + +int8_t RegionEU868AlternateDr( AlternateDrParams_t* alternateDr ) +{ + int8_t datarate = 0; + + if( ( alternateDr->NbTrials % 48 ) == 0 ) + { + datarate = DR_0; + } + else if( ( alternateDr->NbTrials % 32 ) == 0 ) + { + datarate = DR_1; + } + else if( ( alternateDr->NbTrials % 24 ) == 0 ) + { + datarate = DR_2; + } + else if( ( alternateDr->NbTrials % 16 ) == 0 ) + { + datarate = DR_3; + } + else if( ( alternateDr->NbTrials % 8 ) == 0 ) + { + datarate = DR_4; + } + else + { + datarate = DR_5; + } + return datarate; +} + +void RegionEU868CalcBackOff( CalcBackOffParams_t* calcBackOff ) +{ + uint8_t channel = calcBackOff->Channel; + uint16_t dutyCycle = Bands[Channels[channel].Band].DCycle; + uint16_t joinDutyCycle = 0; + + // Reset time-off to initial value. + Bands[Channels[channel].Band].TimeOff = 0; + + if( calcBackOff->Joined == false ) + { + // Get the join duty cycle + joinDutyCycle = RegionCommonGetJoinDc( calcBackOff->ElapsedTime ); + // Apply the most restricting duty cycle + dutyCycle = MAX( dutyCycle, joinDutyCycle ); + // Apply band time-off. + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + else + { + if( calcBackOff->DutyCycleEnabled == true ) + { + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + } +} + +bool RegionEU868NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTx = 0; + uint8_t enabledChannels[EU868_MAX_NB_CHANNELS] = { 0 }; + TimerTime_t nextTxDelay = 0; + + if( RegionCommonCountChannels( ChannelsMask, 0, 1 ) == 0 ) + { // Reactivate default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + } + + if( nextChanParams->AggrTimeOff <= TimerGetElapsedTime( nextChanParams->LastAggrTx ) ) + { + // Reset Aggregated time off + *aggregatedTimeOff = 0; + + // Update bands Time OFF + nextTxDelay = RegionCommonUpdateBandTimeOff( nextChanParams->Joined, nextChanParams->DutyCycleEnabled, Bands, EU868_MAX_NB_BANDS ); + + // Search how many channels are enabled + nbEnabledChannels = CountNbOfEnabledChannels( nextChanParams->Joined, nextChanParams->Datarate, + ChannelsMask, Channels, + Bands, enabledChannels, &delayTx ); + } + else + { + delayTx++; + nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx ); + } + + if( nbEnabledChannels > 0 ) + { + // We found a valid channel + *channel = enabledChannels[randr( 0, nbEnabledChannels - 1 )]; + + *time = 0; + return true; + } + else + { + if( delayTx > 0 ) + { + // Delay transmission due to AggregatedTimeOff or to a band time off + *time = nextTxDelay; + return true; + } + // Datarate not supported by any channel, restore defaults + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + *time = 0; + return false; + } +} + +LoRaMacStatus_t RegionEU868ChannelAdd( ChannelAddParams_t* channelAdd ) +{ + uint8_t band = 0; + bool drInvalid = false; + bool freqInvalid = false; + uint8_t id = channelAdd->ChannelId; + + if( id >= EU868_MAX_NB_CHANNELS ) + { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + + // Validate the datarate range + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Min, EU868_TX_MIN_DATARATE, EU868_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, EU868_TX_MIN_DATARATE, EU868_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( channelAdd->NewChannel->DrRange.Fields.Min > channelAdd->NewChannel->DrRange.Fields.Max ) + { + drInvalid = true; + } + + // Default channels don't accept all values + if( id < EU868_NUMB_DEFAULT_CHANNELS ) + { + // Validate the datarate range for min: must be DR_0 + if( channelAdd->NewChannel->DrRange.Fields.Min > DR_0 ) + { + drInvalid = true; + } + // Validate the datarate range for max: must be DR_5 <= Max <= TX_MAX_DATARATE + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, DR_5, EU868_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + // We are not allowed to change the frequency + if( channelAdd->NewChannel->Frequency != Channels[id].Frequency ) + { + freqInvalid = true; + } + } + + // Check frequency + if( freqInvalid == false ) + { + if( VerifyTxFreq( channelAdd->NewChannel->Frequency, &band ) == false ) + { + freqInvalid = true; + } + } + + // Check status + if( ( drInvalid == true ) && ( freqInvalid == true ) ) + { + return LORAMAC_STATUS_FREQ_AND_DR_INVALID; + } + if( drInvalid == true ) + { + return LORAMAC_STATUS_DATARATE_INVALID; + } + if( freqInvalid == true ) + { + return LORAMAC_STATUS_FREQUENCY_INVALID; + } + + memcpy( &(Channels[id]), channelAdd->NewChannel, sizeof( Channels[id] ) ); + Channels[id].Band = band; + ChannelsMask[0] |= ( 1 << id ); + return LORAMAC_STATUS_OK; +} + +bool RegionEU868ChannelsRemove( ChannelRemoveParams_t* channelRemove ) +{ + uint8_t id = channelRemove->ChannelId; + + if( id < EU868_NUMB_DEFAULT_CHANNELS ) + { + return false; + } + + // Remove the channel from the list of channels + Channels[id] = ( ChannelParams_t ){ 0, 0, { 0 }, 0 }; + + return RegionCommonChanDisable( ChannelsMask, id, EU868_MAX_NB_CHANNELS ); +} + +void RegionEU868SetContinuousWave( ContinuousWaveParams_t* continuousWave ) +{ + int8_t txPowerLimited = LimitTxPower( continuousWave->TxPower, Bands[Channels[continuousWave->Channel].Band].TxMaxPower, continuousWave->Datarate, ChannelsMask ); + int8_t phyTxPower = 0; + uint32_t frequency = Channels[continuousWave->Channel].Frequency; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, continuousWave->MaxEirp, continuousWave->AntennaGain ); + + Radio.SetTxContinuousWave( frequency, phyTxPower, continuousWave->Timeout ); +} + +uint8_t RegionEU868ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +{ + int8_t datarate = dr - drOffset; + + if( datarate < 0 ) + { + datarate = DR_0; + } + return datarate; +} + +void RegionEU868RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ) +{ + RegionCommonRxBeaconSetupParams_t regionCommonRxBeaconSetup; + + regionCommonRxBeaconSetup.Datarates = DataratesEU868; + regionCommonRxBeaconSetup.Frequency = rxBeaconSetup->Frequency; + regionCommonRxBeaconSetup.BeaconSize = EU868_BEACON_SIZE; + regionCommonRxBeaconSetup.BeaconDatarate = EU868_BEACON_CHANNEL_DR; + regionCommonRxBeaconSetup.BeaconChannelBW = EU868_BEACON_CHANNEL_BW; + regionCommonRxBeaconSetup.RxTime = rxBeaconSetup->RxTime; + regionCommonRxBeaconSetup.SymbolTimeout = rxBeaconSetup->SymbolTimeout; + + RegionCommonRxBeaconSetup( ®ionCommonRxBeaconSetup ); + + // Store downlink datarate + *outDr = EU868_BEACON_CHANNEL_DR; +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU868.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU868.h new file mode 100644 index 00000000..fb08d40b --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionEU868.h @@ -0,0 +1,533 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file RegionEU868.h + * + * \brief Region definition for EU868 + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGIONEU868 Region EU868 + * Implementation according to LoRaWAN Specification v1.0.2. + * \{ + */ +#ifndef __REGION_EU868_H__ +#define __REGION_EU868_H__ + +#include "LoRaMac.h" + +/*! + * LoRaMac maximum number of channels + */ +#define EU868_MAX_NB_CHANNELS 16 + +/*! + * Number of default channels + */ +#define EU868_NUMB_DEFAULT_CHANNELS 3 + +/*! + * Number of channels to apply for the CF list + */ +#define EU868_NUMB_CHANNELS_CF_LIST 5 + +/*! + * Minimal datarate that can be used by the node + */ +#define EU868_TX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define EU868_TX_MAX_DATARATE DR_7 + +/*! + * Minimal datarate that can be used by the node + */ +#define EU868_RX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define EU868_RX_MAX_DATARATE DR_7 + +/*! + * Default datarate used by the node + */ +#define EU868_DEFAULT_DATARATE DR_0 + +/*! + * Minimal Rx1 receive datarate offset + */ +#define EU868_MIN_RX1_DR_OFFSET 0 + +/*! + * Maximal Rx1 receive datarate offset + */ +#define EU868_MAX_RX1_DR_OFFSET 5 + +/*! + * Default Rx1 receive datarate offset + */ +#define EU868_DEFAULT_RX1_DR_OFFSET 0 + +/*! + * Minimal Tx output power that can be used by the node + */ +#define EU868_MIN_TX_POWER TX_POWER_7 + +/*! + * Maximal Tx output power that can be used by the node + */ +#define EU868_MAX_TX_POWER TX_POWER_0 + +/*! + * Default Tx output power used by the node + */ +#define EU868_DEFAULT_TX_POWER TX_POWER_0 + +/*! + * Default Max EIRP + */ +#define EU868_DEFAULT_MAX_EIRP 16.0f + +/*! + * Default antenna gain + */ +#define EU868_DEFAULT_ANTENNA_GAIN 2.15f + +/*! + * ADR Ack limit + */ +#define EU868_ADR_ACK_LIMIT 64 + +/*! + * ADR Ack delay + */ +#define EU868_ADR_ACK_DELAY 32 + +/*! + * Enabled or disabled the duty cycle + */ +#define EU868_DUTY_CYCLE_ENABLED 1 + +/*! + * Maximum RX window duration + */ +#define EU868_MAX_RX_WINDOW 3000 + +/*! + * Receive delay 1 + */ +#define EU868_RECEIVE_DELAY1 1000 + +/*! + * Receive delay 2 + */ +#define EU868_RECEIVE_DELAY2 2000 + +/*! + * Join accept delay 1 + */ +#define EU868_JOIN_ACCEPT_DELAY1 5000 + +/*! + * Join accept delay 2 + */ +#define EU868_JOIN_ACCEPT_DELAY2 6000 + +/*! + * Maximum frame counter gap + */ +#define EU868_MAX_FCNT_GAP 16384 + +/*! + * Ack timeout + */ +#define EU868_ACKTIMEOUT 2000 + +/*! + * Random ack timeout limits + */ +#define EU868_ACK_TIMEOUT_RND 1000 + +#if ( EU868_DEFAULT_DATARATE > DR_5 ) +#error "A default DR higher than DR_5 may lead to connectivity loss." +#endif + +/*! + * Second reception window channel frequency definition. + */ +#define EU868_RX_WND_2_FREQ 869525000 + +/*! + * Second reception window channel datarate definition. + */ +#define EU868_RX_WND_2_DR DR_0 + +/* + * CLASS B + */ +/*! + * Beacon frequency + */ +#define EU868_BEACON_CHANNEL_FREQ 869525000 + +/*! + * Payload size of a beacon frame + */ +#define EU868_BEACON_SIZE 17 + +/*! + * Size of RFU 1 field + */ +#define EU868_RFU1_SIZE 2 + +/*! + * Size of RFU 2 field + */ +#define EU868_RFU2_SIZE 0 + +/*! + * Datarate of the beacon channel + */ +#define EU868_BEACON_CHANNEL_DR DR_3 + +/*! + * Bandwith of the beacon channel + */ +#define EU868_BEACON_CHANNEL_BW 0 + +/*! + * Maximum number of bands + */ +#define EU868_MAX_NB_BANDS 5 + +/*! + * Band 0 definition + * { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define EU868_BAND0 { 100 , EU868_MAX_TX_POWER, 0, 0 } // 1.0 % + +/*! + * Band 1 definition + * { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define EU868_BAND1 { 100 , EU868_MAX_TX_POWER, 0, 0 } // 1.0 % + +/*! + * Band 2 definition + * Band = { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define EU868_BAND2 { 1000, EU868_MAX_TX_POWER, 0, 0 } // 0.1 % + +/*! + * Band 2 definition + * Band = { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define EU868_BAND3 { 10 , EU868_MAX_TX_POWER, 0, 0 } // 10.0 % + +/*! + * Band 2 definition + * Band = { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define EU868_BAND4 { 100 , EU868_MAX_TX_POWER, 0, 0 } // 1.0 % + +/*! + * LoRaMac default channel 1 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define EU868_LC1 { 868100000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 1 } + +/*! + * LoRaMac default channel 2 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define EU868_LC2 { 868300000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 1 } + +/*! + * LoRaMac default channel 3 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define EU868_LC3 { 868500000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 1 } + +/*! + * LoRaMac channels which are allowed for the join procedure + */ +#define EU868_JOIN_CHANNELS ( uint16_t )( LC( 1 ) | LC( 2 ) | LC( 3 ) ) + +/*! + * Data rates table definition + */ +static const uint8_t DataratesEU868[] = { 12, 11, 10, 9, 8, 7, 7, 50 }; + +/*! + * Bandwidths table definition in Hz + */ +static const uint32_t BandwidthsEU868[] = { 125000, 125000, 125000, 125000, 125000, 125000, 250000, 0 }; + +/*! + * Maximum payload with respect to the datarate index. Cannot operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateEU868[] = { 51, 51, 51, 115, 242, 242, 242, 242 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateRepeaterEU868[] = { 51, 51, 51, 115, 222, 222, 222, 222 }; + +/*! + * \brief The function gets a value of a specific phy attribute. + * + * \param [IN] getPhy Pointer to the function parameters. + * + * \retval Returns a structure containing the PHY parameter. + */ +PhyParam_t RegionEU868GetPhyParam( GetPhyParams_t* getPhy ); + +/*! + * \brief Updates the last TX done parameters of the current channel. + * + * \param [IN] txDone Pointer to the function parameters. + */ +void RegionEU868SetBandTxDone( SetBandTxDoneParams_t* txDone ); + +/*! + * \brief Initializes the channels masks and the channels. + * + * \param [IN] type Sets the initialization type. + */ +void RegionEU868InitDefaults( InitType_t type ); + +/*! + * \brief Verifies a parameter. + * + * \param [IN] verify Pointer to the function parameters. + * + * \param [IN] type Sets the initialization type. + * + * \retval Returns true, if the parameter is valid. + */ +bool RegionEU868Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ); + +/*! + * \brief The function parses the input buffer and sets up the channels of the + * CF list. + * + * \param [IN] applyCFList Pointer to the function parameters. + */ +void RegionEU868ApplyCFList( ApplyCFListParams_t* applyCFList ); + +/*! + * \brief Sets a channels mask. + * + * \param [IN] chanMaskSet Pointer to the function parameters. + * + * \retval Returns true, if the channels mask could be set. + */ +bool RegionEU868ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ); + +/*! + * \brief Calculates the next datarate to set, when ADR is on or off. + * + * \param [IN] adrNext Pointer to the function parameters. + * + * \param [OUT] drOut The calculated datarate for the next TX. + * + * \param [OUT] txPowOut The TX power for the next TX. + * + * \param [OUT] adrAckCounter The calculated ADR acknowledgement counter. + * + * \retval Returns true, if an ADR request should be performed. + */ +bool RegionEU868AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ); + +/*! + * Computes the Rx window timeout and offset. + * + * \param [IN] datarate Rx window datarate index to be used + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms + * interval around RxOffset + * + * \param [OUT]rxConfigParams Returns updated WindowTimeout and WindowOffset fields. + */ +void RegionEU868ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ); + +/*! + * \brief Configuration of the RX windows. + * + * \param [IN] rxConfig Pointer to the function parameters. + * + * \param [OUT] datarate The datarate index which was set. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionEU868RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ); + +/*! + * \brief TX configuration. + * + * \param [IN] txConfig Pointer to the function parameters. + * + * \param [OUT] txPower The tx power index which was set. + * + * \param [OUT] txTimeOnAir The time-on-air of the frame. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionEU868TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ); + +/*! + * \brief The function processes a Link ADR Request. + * + * \param [IN] linkAdrReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionEU868LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ); + +/*! + * \brief The function processes a RX Parameter Setup Request. + * + * \param [IN] rxParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionEU868RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ); + +/*! + * \brief The function processes a Channel Request. + * + * \param [IN] newChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionEU868NewChannelReq( NewChannelReqParams_t* newChannelReq ); + +/*! + * \brief The function processes a TX ParamSetup Request. + * + * \param [IN] txParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + * Returns -1, if the functionality is not implemented. In this case, the end node + * shall not process the command. + */ +int8_t RegionEU868TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ); + +/*! + * \brief The function processes a DlChannel Request. + * + * \param [IN] dlChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionEU868DlChannelReq( DlChannelReqParams_t* dlChannelReq ); + +/*! + * \brief Alternates the datarate of the channel for the join request. + * + * \param [IN] alternateDr Pointer to the function parameters. + * + * \retval Datarate to apply. + */ +int8_t RegionEU868AlternateDr( AlternateDrParams_t* alternateDr ); + +/*! + * \brief Calculates the back-off time. + * + * \param [IN] calcBackOff Pointer to the function parameters. + */ +void RegionEU868CalcBackOff( CalcBackOffParams_t* calcBackOff ); + +/*! + * \brief Searches and set the next random available channel + * + * \param [OUT] channel Next channel to use for TX. + * + * \param [OUT] time Time to wait for the next transmission according to the duty + * cycle. + * + * \param [OUT] aggregatedTimeOff Updates the aggregated time off. + * + * \retval Function status [1: OK, 0: Unable to find a channel on the current datarate] + */ +bool RegionEU868NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ); + +/*! + * \brief Adds a channel. + * + * \param [IN] channelAdd Pointer to the function parameters. + * + * \retval Status of the operation. + */ +LoRaMacStatus_t RegionEU868ChannelAdd( ChannelAddParams_t* channelAdd ); + +/*! + * \brief Removes a channel. + * + * \param [IN] channelRemove Pointer to the function parameters. + * + * \retval Returns true, if the channel was removed successfully. + */ +bool RegionEU868ChannelsRemove( ChannelRemoveParams_t* channelRemove ); + +/*! + * \brief Sets the radio into continuous wave mode. + * + * \param [IN] continuousWave Pointer to the function parameters. + */ +void RegionEU868SetContinuousWave( ContinuousWaveParams_t* continuousWave ); + +/*! + * \brief Computes new datarate according to the given offset + * + * \param [IN] downlinkDwellTime Downlink dwell time configuration. 0: No limit, 1: 400ms + * + * \param [IN] dr Current datarate + * + * \param [IN] drOffset Offset to be applied + * + * \retval newDr Computed datarate. + */ +uint8_t RegionEU868ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ); + +/*! + * \brief Sets the radio into beacon reception mode + * + * \param [IN] rxBeaconSetup Pointer to the function parameters + */ +void RegionEU868RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ); + +/*! \} defgroup REGIONEU868 */ + +#endif // __REGION_EU868_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionIN865.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionIN865.c new file mode 100644 index 00000000..ebcdb321 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionIN865.c @@ -0,0 +1,1098 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC region IN865 implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include +#include + +#include "radio.h" +//#include "timer.h" +#include "timeServer.h" +#include "LoRaMac.h" + +#include "utilities.h" + +#include "Region.h" +#include "RegionCommon.h" +#include "RegionIN865.h" +#include "debug.h" + +// Definitions +#define CHANNELS_MASK_SIZE 1 + +// Global attributes +/*! + * LoRaMAC channels + */ +static ChannelParams_t Channels[IN865_MAX_NB_CHANNELS]; + +/*! + * LoRaMac bands + */ +static Band_t Bands[IN865_MAX_NB_BANDS] = +{ + IN865_BAND0 +}; + +/*! + * LoRaMac channels mask + */ +static uint16_t ChannelsMask[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels default mask + */ +static uint16_t ChannelsDefaultMask[CHANNELS_MASK_SIZE]; + +// Static functions +static int8_t GetNextLowerTxDr( int8_t dr, int8_t minDr ) +{ + uint8_t nextLowerDr = 0; + + if( dr == minDr ) + { + nextLowerDr = minDr; + } + else if( dr == DR_7 ) + { + nextLowerDr = DR_5; + } + else + { + nextLowerDr = dr - 1; + } + return nextLowerDr; +} + +static uint32_t GetBandwidth( uint32_t drIndex ) +{ + switch( BandwidthsIN865[drIndex] ) + { + default: + case 125000: + return 0; + case 250000: + return 1; + case 500000: + return 2; + } +} + +static int8_t LimitTxPower( int8_t txPower, int8_t maxBandTxPower, int8_t datarate, uint16_t* channelsMask ) +{ + int8_t txPowerResult = txPower; + + // Limit tx power to the band max + txPowerResult = MAX( txPower, maxBandTxPower ); + + return txPowerResult; +} + +static bool VerifyTxFreq( uint32_t freq, uint8_t *band ) +{ + // Check radio driver support + if( Radio.CheckRfFrequency( freq ) == false ) + { + return false; + } + + if( ( freq < 865000000 ) || ( freq > 867000000 ) ) + { + return false; + } + return true; +} + +static uint8_t CountNbOfEnabledChannels( bool joined, uint8_t datarate, uint16_t* channelsMask, ChannelParams_t* channels, Band_t* bands, uint8_t* enabledChannels, uint8_t* delayTx ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTransmission = 0; + + for( uint8_t i = 0, k = 0; i < IN865_MAX_NB_CHANNELS; i += 16, k++ ) + { + for( uint8_t j = 0; j < 16; j++ ) + { + if( ( channelsMask[k] & ( 1 << j ) ) != 0 ) + { + if( channels[i + j].Frequency == 0 ) + { // Check if the channel is enabled + continue; + } + if( joined == false ) + { + if( ( IN865_JOIN_CHANNELS & ( 1 << j ) ) == 0 ) + { + continue; + } + } + if( RegionCommonValueInRange( datarate, channels[i + j].DrRange.Fields.Min, + channels[i + j].DrRange.Fields.Max ) == false ) + { // Check if the current channel selection supports the given datarate + continue; + } + if( bands[channels[i + j].Band].TimeOff > 0 ) + { // Check if the band is available for transmission + delayTransmission++; + continue; + } + enabledChannels[nbEnabledChannels++] = i + j; + } + } + } + + *delayTx = delayTransmission; + return nbEnabledChannels; +} + +PhyParam_t RegionIN865GetPhyParam( GetPhyParams_t* getPhy ) +{ + PhyParam_t phyParam = { 0 }; + + switch( getPhy->Attribute ) + { + case PHY_MIN_RX_DR: + { + phyParam.Value = IN865_RX_MIN_DATARATE; + break; + } + case PHY_MIN_TX_DR: + { + phyParam.Value = IN865_TX_MIN_DATARATE; + break; + } + case PHY_DEF_TX_DR: + { + phyParam.Value = IN865_DEFAULT_DATARATE; + break; + } + case PHY_NEXT_LOWER_TX_DR: + { + phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, IN865_TX_MIN_DATARATE ); + break; + } + case PHY_DEF_TX_POWER: + { + phyParam.Value = IN865_DEFAULT_TX_POWER; + break; + } + case PHY_MAX_PAYLOAD: + { + phyParam.Value = MaxPayloadOfDatarateIN865[getPhy->Datarate]; + break; + } + case PHY_MAX_PAYLOAD_REPEATER: + { + phyParam.Value = MaxPayloadOfDatarateRepeaterIN865[getPhy->Datarate]; + break; + } + case PHY_DUTY_CYCLE: + { + phyParam.Value = IN865_DUTY_CYCLE_ENABLED; + break; + } + case PHY_MAX_RX_WINDOW: + { + phyParam.Value = IN865_MAX_RX_WINDOW; + break; + } + case PHY_RECEIVE_DELAY1: + { + phyParam.Value = IN865_RECEIVE_DELAY1; + break; + } + case PHY_RECEIVE_DELAY2: + { + phyParam.Value = IN865_RECEIVE_DELAY2; + break; + } + case PHY_JOIN_ACCEPT_DELAY1: + { + phyParam.Value = IN865_JOIN_ACCEPT_DELAY1; + break; + } + case PHY_JOIN_ACCEPT_DELAY2: + { + phyParam.Value = IN865_JOIN_ACCEPT_DELAY2; + break; + } + case PHY_MAX_FCNT_GAP: + { + phyParam.Value = IN865_MAX_FCNT_GAP; + break; + } + case PHY_ACK_TIMEOUT: + { + phyParam.Value = ( IN865_ACKTIMEOUT + randr( -IN865_ACK_TIMEOUT_RND, IN865_ACK_TIMEOUT_RND ) ); + break; + } + case PHY_DEF_DR1_OFFSET: + { + phyParam.Value = IN865_DEFAULT_RX1_DR_OFFSET; + break; + } + case PHY_DEF_RX2_FREQUENCY: + { + phyParam.Value = IN865_RX_WND_2_FREQ; + break; + } + case PHY_DEF_RX2_DR: + { + phyParam.Value = IN865_RX_WND_2_DR; + break; + } + case PHY_CHANNELS_MASK: + { + phyParam.ChannelsMask = ChannelsMask; + break; + } + case PHY_CHANNELS_DEFAULT_MASK: + { + phyParam.ChannelsMask = ChannelsDefaultMask; + break; + } + case PHY_MAX_NB_CHANNELS: + { + phyParam.Value = IN865_MAX_NB_CHANNELS; + break; + } + case PHY_CHANNELS: + { + phyParam.Channels = Channels; + break; + } + case PHY_DEF_UPLINK_DWELL_TIME: + case PHY_DEF_DOWNLINK_DWELL_TIME: + { + phyParam.Value = 0; + break; + } + case PHY_DEF_MAX_EIRP: + { + phyParam.fValue = IN865_DEFAULT_MAX_EIRP; + break; + } + case PHY_DEF_ANTENNA_GAIN: + { + phyParam.fValue = IN865_DEFAULT_ANTENNA_GAIN; + break; + } + case PHY_NB_JOIN_TRIALS: + case PHY_DEF_NB_JOIN_TRIALS: + { + phyParam.Value = 48; + break; + } + case PHY_BEACON_CHANNEL_FREQ: + { + phyParam.Value = IN865_BEACON_CHANNEL_FREQ; + break; + } + case PHY_BEACON_FORMAT: + { + phyParam.BeaconFormat.BeaconSize = IN865_BEACON_SIZE; + phyParam.BeaconFormat.Rfu1Size = IN865_RFU1_SIZE; + phyParam.BeaconFormat.Rfu2Size = IN865_RFU2_SIZE; + break; + } + case PHY_BEACON_CHANNEL_DR: + { + phyParam.Value = IN865_BEACON_CHANNEL_DR; + break; + } + default: + { + break; + } + } + + return phyParam; +} + +void RegionIN865SetBandTxDone( SetBandTxDoneParams_t* txDone ) +{ + RegionCommonSetBandTxDone( txDone->Joined, &Bands[Channels[txDone->Channel].Band], txDone->LastTxDoneTime ); +} + +void RegionIN865InitDefaults( InitType_t type ) +{ + switch( type ) + { + case INIT_TYPE_INIT: + { + // Channels + Channels[0] = ( ChannelParams_t ) IN865_LC1; + Channels[1] = ( ChannelParams_t ) IN865_LC2; + Channels[2] = ( ChannelParams_t ) IN865_LC3; + + // Initialize the channels default mask + ChannelsDefaultMask[0] = LC( 1 ) + LC( 2 ) + LC( 3 ); + // Update the channels mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 1 ); + break; + } + case INIT_TYPE_RESTORE: + { + // Restore channels default mask + ChannelsMask[0] |= ChannelsDefaultMask[0]; + break; + } + default: + { + break; + } + } +} + +bool RegionIN865Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ) +{ + switch( phyAttribute ) + { + case PHY_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, IN865_TX_MIN_DATARATE, IN865_TX_MAX_DATARATE ); + } + case PHY_DEF_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, DR_0, DR_5 ); + } + case PHY_RX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, IN865_RX_MIN_DATARATE, IN865_RX_MAX_DATARATE ); + } + case PHY_DEF_TX_POWER: + case PHY_TX_POWER: + { + // Remark: switched min and max! + return RegionCommonValueInRange( verify->TxPower, IN865_MAX_TX_POWER, IN865_MIN_TX_POWER ); + } + case PHY_DUTY_CYCLE: + { + return IN865_DUTY_CYCLE_ENABLED; + } + case PHY_NB_JOIN_TRIALS: + { + if( verify->NbJoinTrials < 48 ) + { + return false; + } + break; + } + default: + return false; + } + return true; +} + +void RegionIN865ApplyCFList( ApplyCFListParams_t* applyCFList ) +{ + ChannelParams_t newChannel; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + // Setup default datarate range + newChannel.DrRange.Value = ( DR_5 << 4 ) | DR_0; + + // Size of the optional CF list + if( applyCFList->Size != 16 ) + { + return; + } + + // Last byte is RFU, don't take it into account + for( uint8_t i = 0, chanIdx = IN865_NUMB_DEFAULT_CHANNELS; chanIdx < IN865_MAX_NB_CHANNELS; i+=3, chanIdx++ ) + { + if( chanIdx < ( IN865_NUMB_CHANNELS_CF_LIST + IN865_NUMB_DEFAULT_CHANNELS ) ) + { + // Channel frequency + newChannel.Frequency = (uint32_t) applyCFList->Payload[i]; + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 1] << 8 ); + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 2] << 16 ); + newChannel.Frequency *= 100; + + // Initialize alternative frequency to 0 + newChannel.Rx1Frequency = 0; + } + else + { + newChannel.Frequency = 0; + newChannel.DrRange.Value = 0; + newChannel.Rx1Frequency = 0; + } + + if( newChannel.Frequency != 0 ) + { + channelAdd.NewChannel = &newChannel; + channelAdd.ChannelId = chanIdx; + + // Try to add all channels + RegionIN865ChannelAdd( &channelAdd ); + } + else + { + channelRemove.ChannelId = chanIdx; + + RegionIN865ChannelsRemove( &channelRemove ); + } + } +} + +bool RegionIN865ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ) +{ + switch( chanMaskSet->ChannelsMaskType ) + { + case CHANNELS_MASK: + { + RegionCommonChanMaskCopy( ChannelsMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + case CHANNELS_DEFAULT_MASK: + { + RegionCommonChanMaskCopy( ChannelsDefaultMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + default: + return false; + } + return true; +} + +bool RegionIN865AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ) +{ + bool adrAckReq = false; + int8_t datarate = adrNext->Datarate; + int8_t txPower = adrNext->TxPower; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + // Report back the adr ack counter + *adrAckCounter = adrNext->AdrAckCounter; + + if( adrNext->AdrEnabled == true ) + { + if( datarate == IN865_TX_MIN_DATARATE ) + { + *adrAckCounter = 0; + adrAckReq = false; + } + else + { + if( adrNext->AdrAckCounter >= IN865_ADR_ACK_LIMIT ) + { + adrAckReq = true; + txPower = IN865_MAX_TX_POWER; + } + else + { + adrAckReq = false; + } + if( adrNext->AdrAckCounter >= ( IN865_ADR_ACK_LIMIT + IN865_ADR_ACK_DELAY ) ) + { + if( ( adrNext->AdrAckCounter % IN865_ADR_ACK_DELAY ) == 1 ) + { + // Decrease the datarate + getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + getPhy.Datarate = datarate; + getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + phyParam = RegionIN865GetPhyParam( &getPhy ); + datarate = phyParam.Value; + + if( datarate == IN865_TX_MIN_DATARATE ) + { + // We must set adrAckReq to false as soon as we reach the lowest datarate + adrAckReq = false; + if( adrNext->UpdateChanMask == true ) + { + // Re-enable default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + } + } + } + } + } + } + + *drOut = datarate; + *txPowOut = txPower; + return adrAckReq; +} + +void RegionIN865ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ) +{ + double tSymbol = 0.0; + uint32_t radioWakeUpTime; + + rxConfigParams->Datarate = datarate; + rxConfigParams->Bandwidth = GetBandwidth( datarate ); + + if( datarate == DR_7 ) + { // FSK + tSymbol = RegionCommonComputeSymbolTimeFsk( DataratesIN865[datarate] ); + } + else + { // LoRa + tSymbol = RegionCommonComputeSymbolTimeLoRa( DataratesIN865[datarate], BandwidthsIN865[datarate] ); + } + + radioWakeUpTime = Radio.GetWakeupTime( ); + RegionCommonComputeRxWindowParameters( tSymbol, minRxSymbols, rxError, radioWakeUpTime, &rxConfigParams->WindowTimeout, &rxConfigParams->WindowOffset ); +} + +bool RegionIN865RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ) +{ + RadioModems_t modem; + int8_t dr = rxConfig->Datarate; + uint8_t maxPayload = 0; + int8_t phyDr = 0; + uint32_t frequency = rxConfig->Frequency; + + if( Radio.GetStatus( ) != RF_IDLE ) + { + return false; + } + + if( rxConfig->RxSlot == RX_SLOT_WIN_1 ) + { + // Apply window 1 frequency + frequency = Channels[rxConfig->Channel].Frequency; + // Apply the alternative RX 1 window frequency, if it is available + if( Channels[rxConfig->Channel].Rx1Frequency != 0 ) + { + frequency = Channels[rxConfig->Channel].Rx1Frequency; + } + } + + // Read the physical datarate from the datarates table + phyDr = DataratesIN865[dr]; + + Radio.SetChannel( frequency ); + + // Radio configuration + if( dr == DR_7 ) + { + modem = MODEM_FSK; + Radio.SetRxConfig( modem, 50000, phyDr * 1000, 0, 83333, 5, rxConfig->WindowTimeout, false, 0, true, 0, 0, false, rxConfig->RxContinuous ); + } + else + { + modem = MODEM_LORA; + Radio.SetRxConfig( modem, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, false, 0, false, 0, 0, true, rxConfig->RxContinuous ); + } + + if( rxConfig->RepeaterSupport == true ) + { + maxPayload = MaxPayloadOfDatarateRepeaterIN865[dr]; + } + else + { + maxPayload = MaxPayloadOfDatarateIN865[dr]; + } + Radio.SetMaxPayloadLength( modem, maxPayload + LORA_MAC_FRMPAYLOAD_OVERHEAD ); + DBG_PRINTF("RX on freq %u Hz at DR %d\n\r", (unsigned int)frequency, dr); + + *datarate = (uint8_t) dr; + return true; +} + +bool RegionIN865TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) +{ + RadioModems_t modem; + int8_t phyDr = DataratesIN865[txConfig->Datarate]; + int8_t txPowerLimited = LimitTxPower( txConfig->TxPower, Bands[Channels[txConfig->Channel].Band].TxMaxPower, txConfig->Datarate, ChannelsMask ); + uint32_t bandwidth = GetBandwidth( txConfig->Datarate ); + int8_t phyTxPower = 0; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, txConfig->MaxEirp, txConfig->AntennaGain ); + + // Setup the radio frequency + Radio.SetChannel( Channels[txConfig->Channel].Frequency ); + + if( txConfig->Datarate == DR_7 ) + { // High Speed FSK channel + modem = MODEM_FSK; + Radio.SetTxConfig( modem, phyTxPower, 25000, bandwidth, phyDr * 1000, 0, 5, false, true, 0, 0, false, 3000 ); + } + else + { + modem = MODEM_LORA; + Radio.SetTxConfig( modem, phyTxPower, 0, bandwidth, phyDr, 1, 8, false, true, 0, 0, false, 3e3 ); + } + DBG_PRINTF("TX on freq %u Hz at DR %d\n\r", (unsigned int)Channels[txConfig->Channel].Frequency, txConfig->Datarate); + // Setup maximum payload lenght of the radio driver + Radio.SetMaxPayloadLength( modem, txConfig->PktLen ); + // Get the time-on-air of the next tx frame + *txTimeOnAir = Radio.TimeOnAir( modem, txConfig->PktLen ); + + *txPower = txPowerLimited; + return true; +} + +uint8_t RegionIN865LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ) +{ + uint8_t status = 0x07; + LinkAdrParams_t linkAdrParams; + uint8_t nextIndex = 0; + uint8_t bytesProcessed = 0; + uint16_t chMask = 0; + + while( bytesProcessed < linkAdrReq->PayloadSize ) + { + // Get ADR request parameters + nextIndex = RegionCommonParseLinkAdrReq( &( linkAdrReq->Payload[bytesProcessed] ), &linkAdrParams ); + + if( nextIndex == 0 ) + break; // break loop, since no more request has been found + + // Update bytes processed + bytesProcessed += nextIndex; + + // Revert status, as we only check the last ADR request for the channel mask KO + status = 0x07; + + // Setup temporary channels mask + chMask = linkAdrParams.ChMask; + + // Verify channels mask + if( ( linkAdrParams.ChMaskCtrl == 0 ) && ( chMask == 0 ) ) + { + status &= 0xFE; // Channel mask KO + } + else if( ( ( linkAdrParams.ChMaskCtrl >= 1 ) && ( linkAdrParams.ChMaskCtrl <= 5 )) || + ( linkAdrParams.ChMaskCtrl >= 7 ) ) + { + // RFU + status &= 0xFE; // Channel mask KO + } + else + { + for( uint8_t i = 0; i < IN865_MAX_NB_CHANNELS; i++ ) + { + if( linkAdrParams.ChMaskCtrl == 6 ) + { + if( Channels[i].Frequency != 0 ) + { + chMask |= 1 << i; + } + } + else + { + if( ( ( chMask & ( 1 << i ) ) != 0 ) && + ( Channels[i].Frequency == 0 ) ) + {// Trying to enable an undefined channel + status &= 0xFE; // Channel mask KO + } + } + } + } + } + + // Verify datarate + if( RegionCommonChanVerifyDr( IN865_MAX_NB_CHANNELS, &chMask, linkAdrParams.Datarate, IN865_TX_MIN_DATARATE, IN865_TX_MAX_DATARATE, Channels ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify tx power + if( RegionCommonValueInRange( linkAdrParams.TxPower, IN865_MAX_TX_POWER, IN865_MIN_TX_POWER ) == 0 ) + { + // Verify if the maximum TX power is exceeded + if( IN865_MAX_TX_POWER > linkAdrParams.TxPower ) + { // Apply maximum TX power. Accept TX power. + linkAdrParams.TxPower = IN865_MAX_TX_POWER; + } + else + { + status &= 0xFB; // TxPower KO + } + } + + // Update channelsMask if everything is correct + if( status == 0x07 ) + { + if( linkAdrParams.NbRep == 0 ) + { // Value of 0 is not allowed, revert to default. + linkAdrParams.NbRep = 1; + } + + // Set the channels mask to a default value + memset( ChannelsMask, 0, sizeof( ChannelsMask ) ); + // Update the channels mask + ChannelsMask[0] = chMask; + } + + // Update status variables + *drOut = linkAdrParams.Datarate; + *txPowOut = linkAdrParams.TxPower; + *nbRepOut = linkAdrParams.NbRep; + *nbBytesParsed = bytesProcessed; + + return status; +} + +uint8_t RegionIN865RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ) +{ + uint8_t status = 0x07; + + // Verify radio frequency + if( Radio.CheckRfFrequency( rxParamSetupReq->Frequency ) == false ) + { + status &= 0xFE; // Channel frequency KO + } + + // Verify datarate + if( RegionCommonValueInRange( rxParamSetupReq->Datarate, IN865_RX_MIN_DATARATE, IN865_RX_MAX_DATARATE ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify datarate offset + if( RegionCommonValueInRange( rxParamSetupReq->DrOffset, IN865_MIN_RX1_DR_OFFSET, IN865_MAX_RX1_DR_OFFSET ) == false ) + { + status &= 0xFB; // Rx1DrOffset range KO + } + + return status; +} + +uint8_t RegionIN865NewChannelReq( NewChannelReqParams_t* newChannelReq ) +{ + uint8_t status = 0x03; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + if( newChannelReq->NewChannel->Frequency == 0 ) + { + channelRemove.ChannelId = newChannelReq->ChannelId; + + // Remove + if( RegionIN865ChannelsRemove( &channelRemove ) == false ) + { + status &= 0xFC; + } + } + else + { + channelAdd.NewChannel = newChannelReq->NewChannel; + channelAdd.ChannelId = newChannelReq->ChannelId; + + switch( RegionIN865ChannelAdd( &channelAdd ) ) + { + case LORAMAC_STATUS_OK: + { + break; + } + case LORAMAC_STATUS_FREQUENCY_INVALID: + { + status &= 0xFE; + break; + } + case LORAMAC_STATUS_DATARATE_INVALID: + { + status &= 0xFD; + break; + } + case LORAMAC_STATUS_FREQ_AND_DR_INVALID: + { + status &= 0xFC; + break; + } + default: + { + status &= 0xFC; + break; + } + } + } + + return status; +} + +int8_t RegionIN865TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ) +{ + return -1; +} + +uint8_t RegionIN865DlChannelReq( DlChannelReqParams_t* dlChannelReq ) +{ + uint8_t status = 0x03; + uint8_t band = 0; + + // Verify if the frequency is supported + if( VerifyTxFreq( dlChannelReq->Rx1Frequency, &band ) == false ) + { + status &= 0xFE; + } + + // Verify if an uplink frequency exists + if( Channels[dlChannelReq->ChannelId].Frequency == 0 ) + { + status &= 0xFD; + } + + // Apply Rx1 frequency, if the status is OK + if( status == 0x03 ) + { + Channels[dlChannelReq->ChannelId].Rx1Frequency = dlChannelReq->Rx1Frequency; + } + + return status; +} + +int8_t RegionIN865AlternateDr( AlternateDrParams_t* alternateDr ) +{ + int8_t datarate = 0; + + if( ( alternateDr->NbTrials % 48 ) == 0 ) + { + datarate = DR_0; + } + else if( ( alternateDr->NbTrials % 32 ) == 0 ) + { + datarate = DR_1; + } + else if( ( alternateDr->NbTrials % 24 ) == 0 ) + { + datarate = DR_2; + } + else if( ( alternateDr->NbTrials % 16 ) == 0 ) + { + datarate = DR_3; + } + else if( ( alternateDr->NbTrials % 8 ) == 0 ) + { + datarate = DR_4; + } + else + { + datarate = DR_5; + } + return datarate; +} + +void RegionIN865CalcBackOff( CalcBackOffParams_t* calcBackOff ) +{ + uint8_t channel = calcBackOff->Channel; + uint16_t dutyCycle = Bands[Channels[channel].Band].DCycle; + uint16_t joinDutyCycle = 0; + + // Reset time-off to initial value. + Bands[Channels[channel].Band].TimeOff = 0; + + if( calcBackOff->Joined == false ) + { + // Get the join duty cycle + joinDutyCycle = RegionCommonGetJoinDc( calcBackOff->ElapsedTime ); + // Apply the most restricting duty cycle + dutyCycle = MAX( dutyCycle, joinDutyCycle ); + // Apply band time-off. + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + else + { + if( calcBackOff->DutyCycleEnabled == true ) + { + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + } +} + +bool RegionIN865NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTx = 0; + uint8_t enabledChannels[IN865_MAX_NB_CHANNELS] = { 0 }; + TimerTime_t nextTxDelay = 0; + + if( RegionCommonCountChannels( ChannelsMask, 0, 1 ) == 0 ) + { // Reactivate default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + } + + if( nextChanParams->AggrTimeOff <= TimerGetElapsedTime( nextChanParams->LastAggrTx ) ) + { + // Reset Aggregated time off + *aggregatedTimeOff = 0; + + // Update bands Time OFF + nextTxDelay = RegionCommonUpdateBandTimeOff( nextChanParams->Joined, nextChanParams->DutyCycleEnabled, Bands, IN865_MAX_NB_BANDS ); + + // Search how many channels are enabled + nbEnabledChannels = CountNbOfEnabledChannels( nextChanParams->Joined, nextChanParams->Datarate, + ChannelsMask, Channels, + Bands, enabledChannels, &delayTx ); + } + else + { + delayTx++; + nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx ); + } + + if( nbEnabledChannels > 0 ) + { + // We found a valid channel + *channel = enabledChannels[randr( 0, nbEnabledChannels - 1 )]; + + *time = 0; + return true; + } + else + { + if( delayTx > 0 ) + { + // Delay transmission due to AggregatedTimeOff or to a band time off + *time = nextTxDelay; + return true; + } + // Datarate not supported by any channel, restore defaults + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + *time = 0; + return false; + } +} + +LoRaMacStatus_t RegionIN865ChannelAdd( ChannelAddParams_t* channelAdd ) +{ + uint8_t band = 0; + bool drInvalid = false; + bool freqInvalid = false; + uint8_t id = channelAdd->ChannelId; + + if( id >= IN865_MAX_NB_CHANNELS ) + { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + + // Validate the datarate range + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Min, IN865_TX_MIN_DATARATE, IN865_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, IN865_TX_MIN_DATARATE, IN865_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( channelAdd->NewChannel->DrRange.Fields.Min > channelAdd->NewChannel->DrRange.Fields.Max ) + { + drInvalid = true; + } + + // Default channels don't accept all values + if( id < IN865_NUMB_DEFAULT_CHANNELS ) + { + // Validate the datarate range for min: must be DR_0 + if( channelAdd->NewChannel->DrRange.Fields.Min > DR_0 ) + { + drInvalid = true; + } + // Validate the datarate range for max: must be DR_5 <= Max <= TX_MAX_DATARATE + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, DR_5, IN865_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + // We are not allowed to change the frequency + if( channelAdd->NewChannel->Frequency != Channels[id].Frequency ) + { + freqInvalid = true; + } + } + + // Check frequency + if( freqInvalid == false ) + { + if( VerifyTxFreq( channelAdd->NewChannel->Frequency, &band ) == false ) + { + freqInvalid = true; + } + } + + // Check status + if( ( drInvalid == true ) && ( freqInvalid == true ) ) + { + return LORAMAC_STATUS_FREQ_AND_DR_INVALID; + } + if( drInvalid == true ) + { + return LORAMAC_STATUS_DATARATE_INVALID; + } + if( freqInvalid == true ) + { + return LORAMAC_STATUS_FREQUENCY_INVALID; + } + + memcpy( &(Channels[id]), channelAdd->NewChannel, sizeof( Channels[id] ) ); + Channels[id].Band = band; + ChannelsMask[0] |= ( 1 << id ); + return LORAMAC_STATUS_OK; +} + +bool RegionIN865ChannelsRemove( ChannelRemoveParams_t* channelRemove ) +{ + uint8_t id = channelRemove->ChannelId; + + if( id < IN865_NUMB_DEFAULT_CHANNELS ) + { + return false; + } + + // Remove the channel from the list of channels + Channels[id] = ( ChannelParams_t ){ 0, 0, { 0 }, 0 }; + + return RegionCommonChanDisable( ChannelsMask, id, IN865_MAX_NB_CHANNELS ); +} + +void RegionIN865SetContinuousWave( ContinuousWaveParams_t* continuousWave ) +{ + int8_t txPowerLimited = LimitTxPower( continuousWave->TxPower, Bands[Channels[continuousWave->Channel].Band].TxMaxPower, continuousWave->Datarate, ChannelsMask ); + int8_t phyTxPower = 0; + uint32_t frequency = Channels[continuousWave->Channel].Frequency; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, continuousWave->MaxEirp, continuousWave->AntennaGain ); + + Radio.SetTxContinuousWave( frequency, phyTxPower, continuousWave->Timeout ); +} + +uint8_t RegionIN865ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +{ + // Apply offset formula + return MIN( DR_5, MAX( DR_0, dr - EffectiveRx1DrOffsetIN865[drOffset] ) ); +} + +void RegionIN865RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ) +{ + RegionCommonRxBeaconSetupParams_t regionCommonRxBeaconSetup; + + regionCommonRxBeaconSetup.Datarates = DataratesIN865; + regionCommonRxBeaconSetup.Frequency = rxBeaconSetup->Frequency; + regionCommonRxBeaconSetup.BeaconSize = IN865_BEACON_SIZE; + regionCommonRxBeaconSetup.BeaconDatarate = IN865_BEACON_CHANNEL_DR; + regionCommonRxBeaconSetup.BeaconChannelBW = IN865_BEACON_CHANNEL_BW; + regionCommonRxBeaconSetup.RxTime = rxBeaconSetup->RxTime; + regionCommonRxBeaconSetup.SymbolTimeout = rxBeaconSetup->SymbolTimeout; + + RegionCommonRxBeaconSetup( ®ionCommonRxBeaconSetup ); + + // Store downlink datarate + *outDr = IN865_BEACON_CHANNEL_DR; +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionIN865.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionIN865.h new file mode 100644 index 00000000..fae96f33 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionIN865.h @@ -0,0 +1,514 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file RegionIN865.h + * + * \brief Region definition for IN865 + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGIONIN865 Region IN865 + * Implementation according to LoRaWAN Specification v1.0.2. + * \{ + */ +#ifndef __REGION_IN865_H__ +#define __REGION_IN865_H__ + +#include "LoRaMac.h" + +/*! + * LoRaMac maximum number of channels + */ +#define IN865_MAX_NB_CHANNELS 16 + +/*! + * Number of default channels + */ +#define IN865_NUMB_DEFAULT_CHANNELS 3 + +/*! + * Number of channels to apply for the CF list + */ +#define IN865_NUMB_CHANNELS_CF_LIST 5 + +/*! + * Minimal datarate that can be used by the node + */ +#define IN865_TX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define IN865_TX_MAX_DATARATE DR_7 + +/*! + * Minimal datarate that can be used by the node + */ +#define IN865_RX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define IN865_RX_MAX_DATARATE DR_7 + +/*! + * Default datarate used by the node + */ +#define IN865_DEFAULT_DATARATE DR_0 + +/*! + * Minimal Rx1 receive datarate offset + */ +#define IN865_MIN_RX1_DR_OFFSET 0 + +/*! + * Maximal Rx1 receive datarate offset + */ +#define IN865_MAX_RX1_DR_OFFSET 7 + +/*! + * Default Rx1 receive datarate offset + */ +#define IN865_DEFAULT_RX1_DR_OFFSET 0 + +/*! + * Minimal Tx output power that can be used by the node + */ +#define IN865_MIN_TX_POWER TX_POWER_10 + +/*! + * Maximal Tx output power that can be used by the node + */ +#define IN865_MAX_TX_POWER TX_POWER_0 + +/*! + * Default Tx output power used by the node + */ +#define IN865_DEFAULT_TX_POWER TX_POWER_0 + +/*! + * Default Max EIRP + */ +#define IN865_DEFAULT_MAX_EIRP 30.0f + +/*! + * Default antenna gain + */ +#define IN865_DEFAULT_ANTENNA_GAIN 2.15f + +/*! + * ADR Ack limit + */ +#define IN865_ADR_ACK_LIMIT 64 + +/*! + * ADR Ack delay + */ +#define IN865_ADR_ACK_DELAY 32 + +/*! + * Enabled or disabled the duty cycle + */ +#define IN865_DUTY_CYCLE_ENABLED 1 + +/*! + * Maximum RX window duration + */ +#define IN865_MAX_RX_WINDOW 3000 + +/*! + * Receive delay 1 + */ +#define IN865_RECEIVE_DELAY1 1000 + +/*! + * Receive delay 2 + */ +#define IN865_RECEIVE_DELAY2 2000 + +/*! + * Join accept delay 1 + */ +#define IN865_JOIN_ACCEPT_DELAY1 5000 + +/*! + * Join accept delay 2 + */ +#define IN865_JOIN_ACCEPT_DELAY2 6000 + +/*! + * Maximum frame counter gap + */ +#define IN865_MAX_FCNT_GAP 16384 + +/*! + * Ack timeout + */ +#define IN865_ACKTIMEOUT 2000 + +/*! + * Random ack timeout limits + */ +#define IN865_ACK_TIMEOUT_RND 1000 + +#if ( IN865_DEFAULT_DATARATE > DR_5 ) +#error "A default DR higher than DR_5 may lead to connectivity loss." +#endif + +/*! + * Second reception window channel frequency definition. + */ +#define IN865_RX_WND_2_FREQ 866550000 + +/*! + * Second reception window channel datarate definition. + */ +#define IN865_RX_WND_2_DR DR_2 + +/* + * CLASS B + */ +/*! + * Beacon frequency + */ +#define IN865_BEACON_CHANNEL_FREQ 866550000 + +/*! + * Payload size of a beacon frame + */ +#define IN865_BEACON_SIZE 19 + +/*! + * Size of RFU 1 field + */ +#define IN865_RFU1_SIZE 1 + +/*! + * Size of RFU 2 field + */ +#define IN865_RFU2_SIZE 3 + +/*! + * Datarate of the beacon channel + */ +#define IN865_BEACON_CHANNEL_DR DR_4 + +/*! + * Bandwith of the beacon channel + */ +#define IN865_BEACON_CHANNEL_BW 0 + +/*! + * Maximum number of bands + */ +#define IN865_MAX_NB_BANDS 1 + +/*! + * Band 0 definition + * { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define IN865_BAND0 { 1 , IN865_MAX_TX_POWER, 0, 0 } // 100.0 % + +/*! + * LoRaMac default channel 1 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define IN865_LC1 { 865062500, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac default channel 2 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define IN865_LC2 { 865402500, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac default channel 3 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define IN865_LC3 { 865985000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac channels which are allowed for the join procedure + */ +#define IN865_JOIN_CHANNELS ( uint16_t )( LC( 1 ) | LC( 2 ) | LC( 3 ) ) + +/*! + * Data rates table definition + */ +static const uint8_t DataratesIN865[] = { 12, 11, 10, 9, 8, 7, 7, 50 }; + +/*! + * Bandwidths table definition in Hz + */ +static const uint32_t BandwidthsIN865[] = { 125000, 125000, 125000, 125000, 125000, 125000, 250000, 0 }; + +/*! + * Maximum payload with respect to the datarate index. Cannot operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateIN865[] = { 51, 51, 51, 115, 242, 242, 242, 242 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateRepeaterIN865[] = { 51, 51, 51, 115, 222, 222, 222, 222 }; + +/*! + * Effective datarate offsets for receive window 1. + */ +static const int8_t EffectiveRx1DrOffsetIN865[] = { 0, 1, 2, 3, 4, 5, -1, -2 }; + +/*! + * \brief The function gets a value of a specific phy attribute. + * + * \param [IN] getPhy Pointer to the function parameters. + * + * \retval Returns a structure containing the PHY parameter. + */ +PhyParam_t RegionIN865GetPhyParam( GetPhyParams_t* getPhy ); + +/*! + * \brief Updates the last TX done parameters of the current channel. + * + * \param [IN] txDone Pointer to the function parameters. + */ +void RegionIN865SetBandTxDone( SetBandTxDoneParams_t* txDone ); + +/*! + * \brief Initializes the channels masks and the channels. + * + * \param [IN] type Sets the initialization type. + */ +void RegionIN865InitDefaults( InitType_t type ); + +/*! + * \brief Verifies a parameter. + * + * \param [IN] verify Pointer to the function parameters. + * + * \param [IN] type Sets the initialization type. + * + * \retval Returns true, if the parameter is valid. + */ +bool RegionIN865Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ); + +/*! + * \brief The function parses the input buffer and sets up the channels of the + * CF list. + * + * \param [IN] applyCFList Pointer to the function parameters. + */ +void RegionIN865ApplyCFList( ApplyCFListParams_t* applyCFList ); + +/*! + * \brief Sets a channels mask. + * + * \param [IN] chanMaskSet Pointer to the function parameters. + * + * \retval Returns true, if the channels mask could be set. + */ +bool RegionIN865ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ); + +/*! + * \brief Calculates the next datarate to set, when ADR is on or off. + * + * \param [IN] adrNext Pointer to the function parameters. + * + * \param [OUT] drOut The calculated datarate for the next TX. + * + * \param [OUT] txPowOut The TX power for the next TX. + * + * \param [OUT] adrAckCounter The calculated ADR acknowledgement counter. + * + * \retval Returns true, if an ADR request should be performed. + */ +bool RegionIN865AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ); + +/*! + * Computes the Rx window timeout and offset. + * + * \param [IN] datarate Rx window datarate index to be used + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms + * interval around RxOffset + * + * \param [OUT]rxConfigParams Returns updated WindowTimeout and WindowOffset fields. + */ +void RegionIN865ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ); + +/*! + * \brief Configuration of the RX windows. + * + * \param [IN] rxConfig Pointer to the function parameters. + * + * \param [OUT] datarate The datarate index which was set. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionIN865RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ); + +/*! + * \brief TX configuration. + * + * \param [IN] txConfig Pointer to the function parameters. + * + * \param [OUT] txPower The tx power index which was set. + * + * \param [OUT] txTimeOnAir The time-on-air of the frame. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionIN865TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ); + +/*! + * \brief The function processes a Link ADR Request. + * + * \param [IN] linkAdrReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionIN865LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ); + +/*! + * \brief The function processes a RX Parameter Setup Request. + * + * \param [IN] rxParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionIN865RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ); + +/*! + * \brief The function processes a Channel Request. + * + * \param [IN] newChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionIN865NewChannelReq( NewChannelReqParams_t* newChannelReq ); + +/*! + * \brief The function processes a TX ParamSetup Request. + * + * \param [IN] txParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + * Returns -1, if the functionality is not implemented. In this case, the end node + * shall not process the command. + */ +int8_t RegionIN865TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ); + +/*! + * \brief The function processes a DlChannel Request. + * + * \param [IN] dlChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionIN865DlChannelReq( DlChannelReqParams_t* dlChannelReq ); + +/*! + * \brief Alternates the datarate of the channel for the join request. + * + * \param [IN] alternateDr Pointer to the function parameters. + * + * \retval Datarate to apply. + */ +int8_t RegionIN865AlternateDr( AlternateDrParams_t* alternateDr ); + +/*! + * \brief Calculates the back-off time. + * + * \param [IN] calcBackOff Pointer to the function parameters. + */ +void RegionIN865CalcBackOff( CalcBackOffParams_t* calcBackOff ); + +/*! + * \brief Searches and set the next random available channel + * + * \param [OUT] channel Next channel to use for TX. + * + * \param [OUT] time Time to wait for the next transmission according to the duty + * cycle. + * + * \param [OUT] aggregatedTimeOff Updates the aggregated time off. + * + * \retval Function status [1: OK, 0: Unable to find a channel on the current datarate] + */ +bool RegionIN865NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ); + +/*! + * \brief Adds a channel. + * + * \param [IN] channelAdd Pointer to the function parameters. + * + * \retval Status of the operation. + */ +LoRaMacStatus_t RegionIN865ChannelAdd( ChannelAddParams_t* channelAdd ); + +/*! + * \brief Removes a channel. + * + * \param [IN] channelRemove Pointer to the function parameters. + * + * \retval Returns true, if the channel was removed successfully. + */ +bool RegionIN865ChannelsRemove( ChannelRemoveParams_t* channelRemove ); + +/*! + * \brief Sets the radio into continuous wave mode. + * + * \param [IN] continuousWave Pointer to the function parameters. + */ +void RegionIN865SetContinuousWave( ContinuousWaveParams_t* continuousWave ); + +/*! + * \brief Computes new datarate according to the given offset + * + * \param [IN] downlinkDwellTime Downlink dwell time configuration. 0: No limit, 1: 400ms + * + * \param [IN] dr Current datarate + * + * \param [IN] drOffset Offset to be applied + * + * \retval newDr Computed datarate. + */ +uint8_t RegionIN865ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ); + +/*! + * \brief Sets the radio into beacon reception mode + * + * \param [IN] rxBeaconSetup Pointer to the function parameters + */ + void RegionIN865RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ); + +/*! \} defgroup REGIONIN865 */ + +#endif // __REGION_IN865_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionKR920.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionKR920.c new file mode 100644 index 00000000..a96e53de --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionKR920.c @@ -0,0 +1,1102 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC region KR920 implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include +#include + +#include "radio.h" +//#include "timer.h" +#include "timeServer.h" +#include "LoRaMac.h" + +#include "utilities.h" + +#include "Region.h" +#include "RegionCommon.h" +#include "RegionKR920.h" +#include "debug.h" + +// Definitions +#define CHANNELS_MASK_SIZE 1 + +// Global attributes +/*! + * LoRaMAC channels + */ +static ChannelParams_t Channels[KR920_MAX_NB_CHANNELS]; + +/*! + * LoRaMac bands + */ +static Band_t Bands[KR920_MAX_NB_BANDS] = +{ + KR920_BAND0 +}; + +/*! + * LoRaMac channels mask + */ +static uint16_t ChannelsMask[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels default mask + */ +static uint16_t ChannelsDefaultMask[CHANNELS_MASK_SIZE]; + +// Static functions +static int8_t GetNextLowerTxDr( int8_t dr, int8_t minDr ) +{ + uint8_t nextLowerDr = 0; + + if( dr == minDr ) + { + nextLowerDr = minDr; + } + else + { + nextLowerDr = dr - 1; + } + return nextLowerDr; +} + +static int8_t GetMaxEIRP( uint32_t freq ) +{ + if( freq >= 922100000 ) + {// Limit to 14dBm + return KR920_DEFAULT_MAX_EIRP_HIGH; + } + // Limit to 10dBm + return KR920_DEFAULT_MAX_EIRP_LOW; +} + +static uint32_t GetBandwidth( uint32_t drIndex ) +{ + switch( BandwidthsKR920[drIndex] ) + { + default: + case 125000: + return 0; + case 250000: + return 1; + case 500000: + return 2; + } +} + +static int8_t LimitTxPower( int8_t txPower, int8_t maxBandTxPower, int8_t datarate, uint16_t* channelsMask ) +{ + int8_t txPowerResult = txPower; + + // Limit tx power to the band max + txPowerResult = MAX( txPower, maxBandTxPower ); + + return txPowerResult; +} + +static bool VerifyTxFreq( uint32_t freq ) +{ + uint32_t tmpFreq = freq; + + // Check radio driver support + if( Radio.CheckRfFrequency( tmpFreq ) == false ) + { + return false; + } + + // Verify if the frequency is valid. The frequency must be in a specified + // range and can be set to specific values. + if( ( tmpFreq >= 920900000 ) && ( tmpFreq <=923300000 ) ) + { + // Range ok, check for specific value + tmpFreq -= 920900000; + if( ( tmpFreq % 200000 ) == 0 ) + { + return true; + } + } + return false; +} + +static uint8_t CountNbOfEnabledChannels( bool joined, uint8_t datarate, uint16_t* channelsMask, ChannelParams_t* channels, Band_t* bands, uint8_t* enabledChannels, uint8_t* delayTx ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTransmission = 0; + + for( uint8_t i = 0, k = 0; i < KR920_MAX_NB_CHANNELS; i += 16, k++ ) + { + for( uint8_t j = 0; j < 16; j++ ) + { + if( ( channelsMask[k] & ( 1 << j ) ) != 0 ) + { + if( channels[i + j].Frequency == 0 ) + { // Check if the channel is enabled + continue; + } + if( joined == false ) + { + if( ( KR920_JOIN_CHANNELS & ( 1 << j ) ) == 0 ) + { + continue; + } + } + if( RegionCommonValueInRange( datarate, channels[i + j].DrRange.Fields.Min, + channels[i + j].DrRange.Fields.Max ) == false ) + { // Check if the current channel selection supports the given datarate + continue; + } + if( bands[channels[i + j].Band].TimeOff > 0 ) + { // Check if the band is available for transmission + delayTransmission++; + continue; + } + enabledChannels[nbEnabledChannels++] = i + j; + } + } + } + + *delayTx = delayTransmission; + return nbEnabledChannels; +} + +PhyParam_t RegionKR920GetPhyParam( GetPhyParams_t* getPhy ) +{ + PhyParam_t phyParam = { 0 }; + + switch( getPhy->Attribute ) + { + case PHY_MIN_RX_DR: + { + phyParam.Value = KR920_RX_MIN_DATARATE; + break; + } + case PHY_MIN_TX_DR: + { + phyParam.Value = KR920_TX_MIN_DATARATE; + break; + } + case PHY_DEF_TX_DR: + { + phyParam.Value = KR920_DEFAULT_DATARATE; + break; + } + case PHY_NEXT_LOWER_TX_DR: + { + phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, KR920_TX_MIN_DATARATE ); + break; + } + case PHY_DEF_TX_POWER: + { + phyParam.Value = KR920_DEFAULT_TX_POWER; + break; + } + case PHY_MAX_PAYLOAD: + { + phyParam.Value = MaxPayloadOfDatarateKR920[getPhy->Datarate]; + break; + } + case PHY_MAX_PAYLOAD_REPEATER: + { + phyParam.Value = MaxPayloadOfDatarateRepeaterKR920[getPhy->Datarate]; + break; + } + case PHY_DUTY_CYCLE: + { + phyParam.Value = KR920_DUTY_CYCLE_ENABLED; + break; + } + case PHY_MAX_RX_WINDOW: + { + phyParam.Value = KR920_MAX_RX_WINDOW; + break; + } + case PHY_RECEIVE_DELAY1: + { + phyParam.Value = KR920_RECEIVE_DELAY1; + break; + } + case PHY_RECEIVE_DELAY2: + { + phyParam.Value = KR920_RECEIVE_DELAY2; + break; + } + case PHY_JOIN_ACCEPT_DELAY1: + { + phyParam.Value = KR920_JOIN_ACCEPT_DELAY1; + break; + } + case PHY_JOIN_ACCEPT_DELAY2: + { + phyParam.Value = KR920_JOIN_ACCEPT_DELAY2; + break; + } + case PHY_MAX_FCNT_GAP: + { + phyParam.Value = KR920_MAX_FCNT_GAP; + break; + } + case PHY_ACK_TIMEOUT: + { + phyParam.Value = ( KR920_ACKTIMEOUT + randr( -KR920_ACK_TIMEOUT_RND, KR920_ACK_TIMEOUT_RND ) ); + break; + } + case PHY_DEF_DR1_OFFSET: + { + phyParam.Value = KR920_DEFAULT_RX1_DR_OFFSET; + break; + } + case PHY_DEF_RX2_FREQUENCY: + { + phyParam.Value = KR920_RX_WND_2_FREQ; + break; + } + case PHY_DEF_RX2_DR: + { + phyParam.Value = KR920_RX_WND_2_DR; + break; + } + case PHY_CHANNELS_MASK: + { + phyParam.ChannelsMask = ChannelsMask; + break; + } + case PHY_CHANNELS_DEFAULT_MASK: + { + phyParam.ChannelsMask = ChannelsDefaultMask; + break; + } + case PHY_MAX_NB_CHANNELS: + { + phyParam.Value = KR920_MAX_NB_CHANNELS; + break; + } + case PHY_CHANNELS: + { + phyParam.Channels = Channels; + break; + } + case PHY_DEF_UPLINK_DWELL_TIME: + case PHY_DEF_DOWNLINK_DWELL_TIME: + { + phyParam.Value = 0; + break; + } + case PHY_DEF_MAX_EIRP: + { + // We set the higher maximum EIRP as default value. + // The reason for this is, that the frequency may + // change during a channel selection for the next uplink. + // The value has to be recalculated in the TX configuration. + phyParam.fValue = KR920_DEFAULT_MAX_EIRP_HIGH; + break; + } + case PHY_DEF_ANTENNA_GAIN: + { + phyParam.fValue = KR920_DEFAULT_ANTENNA_GAIN; + break; + } + case PHY_NB_JOIN_TRIALS: + case PHY_DEF_NB_JOIN_TRIALS: + { + phyParam.Value = 48; + break; + } + case PHY_BEACON_CHANNEL_FREQ: + { + phyParam.Value = KR920_BEACON_CHANNEL_FREQ; + break; + } + case PHY_BEACON_FORMAT: + { + phyParam.BeaconFormat.BeaconSize = KR920_BEACON_SIZE; + phyParam.BeaconFormat.Rfu1Size = KR920_RFU1_SIZE; + phyParam.BeaconFormat.Rfu2Size = KR920_RFU2_SIZE; + break; + } + case PHY_BEACON_CHANNEL_DR: + { + phyParam.Value = KR920_BEACON_CHANNEL_DR; + break; + } + default: + { + break; + } + } + + return phyParam; +} + +void RegionKR920SetBandTxDone( SetBandTxDoneParams_t* txDone ) +{ + RegionCommonSetBandTxDone( txDone->Joined, &Bands[Channels[txDone->Channel].Band], txDone->LastTxDoneTime ); +} + +void RegionKR920InitDefaults( InitType_t type ) +{ + switch( type ) + { + case INIT_TYPE_INIT: + { + // Channels + Channels[0] = ( ChannelParams_t ) KR920_LC1; + Channels[1] = ( ChannelParams_t ) KR920_LC2; + Channels[2] = ( ChannelParams_t ) KR920_LC3; + + // Initialize the channels default mask + ChannelsDefaultMask[0] = LC( 1 ) + LC( 2 ) + LC( 3 ); + // Update the channels mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 1 ); + break; + } + case INIT_TYPE_RESTORE: + { + // Restore channels default mask + ChannelsMask[0] |= ChannelsDefaultMask[0]; + break; + } + default: + { + break; + } + } +} + +bool RegionKR920Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ) +{ + switch( phyAttribute ) + { + case PHY_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, KR920_TX_MIN_DATARATE, KR920_TX_MAX_DATARATE ); + } + case PHY_DEF_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, DR_0, DR_5 ); + } + case PHY_RX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, KR920_RX_MIN_DATARATE, KR920_RX_MAX_DATARATE ); + } + case PHY_DEF_TX_POWER: + case PHY_TX_POWER: + { + // Remark: switched min and max! + return RegionCommonValueInRange( verify->TxPower, KR920_MAX_TX_POWER, KR920_MIN_TX_POWER ); + } + case PHY_DUTY_CYCLE: + { + return KR920_DUTY_CYCLE_ENABLED; + } + case PHY_NB_JOIN_TRIALS: + { + if( verify->NbJoinTrials < 48 ) + { + return false; + } + break; + } + default: + return false; + } + return true; +} + +void RegionKR920ApplyCFList( ApplyCFListParams_t* applyCFList ) +{ + ChannelParams_t newChannel; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + // Setup default datarate range + newChannel.DrRange.Value = ( DR_5 << 4 ) | DR_0; + + // Size of the optional CF list + if( applyCFList->Size != 16 ) + { + return; + } + + // Last byte is RFU, don't take it into account + for( uint8_t i = 0, chanIdx = KR920_NUMB_DEFAULT_CHANNELS; chanIdx < KR920_MAX_NB_CHANNELS; i+=3, chanIdx++ ) + { + if( chanIdx < ( KR920_NUMB_CHANNELS_CF_LIST + KR920_NUMB_DEFAULT_CHANNELS ) ) + { + // Channel frequency + newChannel.Frequency = (uint32_t) applyCFList->Payload[i]; + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 1] << 8 ); + newChannel.Frequency |= ( (uint32_t) applyCFList->Payload[i + 2] << 16 ); + newChannel.Frequency *= 100; + + // Initialize alternative frequency to 0 + newChannel.Rx1Frequency = 0; + } + else + { + newChannel.Frequency = 0; + newChannel.DrRange.Value = 0; + newChannel.Rx1Frequency = 0; + } + + if( newChannel.Frequency != 0 ) + { + channelAdd.NewChannel = &newChannel; + channelAdd.ChannelId = chanIdx; + + // Try to add all channels + RegionKR920ChannelAdd( &channelAdd ); + } + else + { + channelRemove.ChannelId = chanIdx; + + RegionKR920ChannelsRemove( &channelRemove ); + } + } +} + +bool RegionKR920ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ) +{ + switch( chanMaskSet->ChannelsMaskType ) + { + case CHANNELS_MASK: + { + RegionCommonChanMaskCopy( ChannelsMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + case CHANNELS_DEFAULT_MASK: + { + RegionCommonChanMaskCopy( ChannelsDefaultMask, chanMaskSet->ChannelsMaskIn, 1 ); + break; + } + default: + return false; + } + return true; +} + +bool RegionKR920AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ) +{ + bool adrAckReq = false; + int8_t datarate = adrNext->Datarate; + int8_t txPower = adrNext->TxPower; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + // Report back the adr ack counter + *adrAckCounter = adrNext->AdrAckCounter; + + if( adrNext->AdrEnabled == true ) + { + if( datarate == KR920_TX_MIN_DATARATE ) + { + *adrAckCounter = 0; + adrAckReq = false; + } + else + { + if( adrNext->AdrAckCounter >= KR920_ADR_ACK_LIMIT ) + { + adrAckReq = true; + txPower = KR920_MAX_TX_POWER; + } + else + { + adrAckReq = false; + } + if( adrNext->AdrAckCounter >= ( KR920_ADR_ACK_LIMIT + KR920_ADR_ACK_DELAY ) ) + { + if( ( adrNext->AdrAckCounter % KR920_ADR_ACK_DELAY ) == 1 ) + { + // Decrease the datarate + getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + getPhy.Datarate = datarate; + getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + phyParam = RegionKR920GetPhyParam( &getPhy ); + datarate = phyParam.Value; + + if( datarate == KR920_TX_MIN_DATARATE ) + { + // We must set adrAckReq to false as soon as we reach the lowest datarate + adrAckReq = false; + if( adrNext->UpdateChanMask == true ) + { + // Re-enable default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + } + } + } + } + } + } + + *drOut = datarate; + *txPowOut = txPower; + return adrAckReq; +} + +void RegionKR920ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ) +{ + double tSymbol = 0.0; + uint32_t radioWakeUpTime; + + rxConfigParams->Datarate = datarate; + rxConfigParams->Bandwidth = GetBandwidth( datarate ); + + if( datarate == DR_7 ) + { // FSK + tSymbol = RegionCommonComputeSymbolTimeFsk( DataratesKR920[datarate] ); + } + else + { // LoRa + tSymbol = RegionCommonComputeSymbolTimeLoRa( DataratesKR920[datarate], BandwidthsKR920[datarate] ); + } + + radioWakeUpTime = Radio.GetWakeupTime( ); + RegionCommonComputeRxWindowParameters( tSymbol, minRxSymbols, rxError, radioWakeUpTime, &rxConfigParams->WindowTimeout, &rxConfigParams->WindowOffset ); +} + +bool RegionKR920RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ) +{ + int8_t dr = rxConfig->Datarate; + uint8_t maxPayload = 0; + int8_t phyDr = 0; + uint32_t frequency = rxConfig->Frequency; + + if( Radio.GetStatus( ) != RF_IDLE ) + { + return false; + } + + if( rxConfig->RxSlot == RX_SLOT_WIN_1 ) + { + // Apply window 1 frequency + frequency = Channels[rxConfig->Channel].Frequency; + // Apply the alternative RX 1 window frequency, if it is available + if( Channels[rxConfig->Channel].Rx1Frequency != 0 ) + { + frequency = Channels[rxConfig->Channel].Rx1Frequency; + } + } + + // Read the physical datarate from the datarates table + phyDr = DataratesKR920[dr]; + + Radio.SetChannel( frequency ); + + // Radio configuration + Radio.SetRxConfig( MODEM_LORA, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, false, 0, false, 0, 0, true, rxConfig->RxContinuous ); + maxPayload = MaxPayloadOfDatarateKR920[dr]; + Radio.SetMaxPayloadLength( MODEM_LORA, maxPayload + LORA_MAC_FRMPAYLOAD_OVERHEAD ); + DBG_PRINTF("RX on freq %u Hz at DR %d\n\r", (unsigned int)frequency, dr); + + *datarate = (uint8_t) dr; + return true; +} + +bool RegionKR920TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) +{ + int8_t phyDr = DataratesKR920[txConfig->Datarate]; + int8_t txPowerLimited = LimitTxPower( txConfig->TxPower, Bands[Channels[txConfig->Channel].Band].TxMaxPower, txConfig->Datarate, ChannelsMask ); + uint32_t bandwidth = GetBandwidth( txConfig->Datarate ); + float maxEIRP = GetMaxEIRP( Channels[txConfig->Channel].Frequency ); + int8_t phyTxPower = 0; + + // Take the minimum between the maxEIRP and txConfig->MaxEirp. + // The value of txConfig->MaxEirp could have changed during runtime, e.g. due to a MAC command. + maxEIRP = MIN( txConfig->MaxEirp, maxEIRP ); + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, maxEIRP, txConfig->AntennaGain ); + + // Setup the radio frequency + Radio.SetChannel( Channels[txConfig->Channel].Frequency ); + + Radio.SetTxConfig( MODEM_LORA, phyTxPower, 0, bandwidth, phyDr, 1, 8, false, true, 0, 0, false, 4e3 ); + DBG_PRINTF("TX on freq %u Hz at DR %d\n\r", (unsigned int)Channels[txConfig->Channel].Frequency, txConfig->Datarate); + + // Setup maximum payload lenght of the radio driver + Radio.SetMaxPayloadLength( MODEM_LORA, txConfig->PktLen ); + // Get the time-on-air of the next tx frame + *txTimeOnAir = Radio.TimeOnAir( MODEM_LORA, txConfig->PktLen ); + + *txPower = txPowerLimited; + return true; +} + +uint8_t RegionKR920LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ) +{ + uint8_t status = 0x07; + LinkAdrParams_t linkAdrParams; + uint8_t nextIndex = 0; + uint8_t bytesProcessed = 0; + uint16_t chMask = 0; + + while( bytesProcessed < linkAdrReq->PayloadSize ) + { + // Get ADR request parameters + nextIndex = RegionCommonParseLinkAdrReq( &( linkAdrReq->Payload[bytesProcessed] ), &linkAdrParams ); + + if( nextIndex == 0 ) + break; // break loop, since no more request has been found + + // Update bytes processed + bytesProcessed += nextIndex; + + // Revert status, as we only check the last ADR request for the channel mask KO + status = 0x07; + + // Setup temporary channels mask + chMask = linkAdrParams.ChMask; + + // Verify channels mask + if( ( linkAdrParams.ChMaskCtrl == 0 ) && ( chMask == 0 ) ) + { + status &= 0xFE; // Channel mask KO + } + else if( ( ( linkAdrParams.ChMaskCtrl >= 1 ) && ( linkAdrParams.ChMaskCtrl <= 5 )) || + ( linkAdrParams.ChMaskCtrl >= 7 ) ) + { + // RFU + status &= 0xFE; // Channel mask KO + } + else + { + for( uint8_t i = 0; i < KR920_MAX_NB_CHANNELS; i++ ) + { + if( linkAdrParams.ChMaskCtrl == 6 ) + { + if( Channels[i].Frequency != 0 ) + { + chMask |= 1 << i; + } + } + else + { + if( ( ( chMask & ( 1 << i ) ) != 0 ) && + ( Channels[i].Frequency == 0 ) ) + {// Trying to enable an undefined channel + status &= 0xFE; // Channel mask KO + } + } + } + } + } + + // Verify datarate + if( RegionCommonChanVerifyDr( KR920_MAX_NB_CHANNELS, &chMask, linkAdrParams.Datarate, KR920_TX_MIN_DATARATE, KR920_TX_MAX_DATARATE, Channels ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify tx power + if( RegionCommonValueInRange( linkAdrParams.TxPower, KR920_MAX_TX_POWER, KR920_MIN_TX_POWER ) == 0 ) + { + // Verify if the maximum TX power is exceeded + if( KR920_MAX_TX_POWER > linkAdrParams.TxPower ) + { // Apply maximum TX power. Accept TX power. + linkAdrParams.TxPower = KR920_MAX_TX_POWER; + } + else + { + status &= 0xFB; // TxPower KO + } + } + + // Update channelsMask if everything is correct + if( status == 0x07 ) + { + if( linkAdrParams.NbRep == 0 ) + { // Value of 0 is not allowed, revert to default. + linkAdrParams.NbRep = 1; + } + + // Set the channels mask to a default value + memset( ChannelsMask, 0, sizeof( ChannelsMask ) ); + // Update the channels mask + ChannelsMask[0] = chMask; + } + + // Update status variables + *drOut = linkAdrParams.Datarate; + *txPowOut = linkAdrParams.TxPower; + *nbRepOut = linkAdrParams.NbRep; + *nbBytesParsed = bytesProcessed; + + return status; +} + +uint8_t RegionKR920RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ) +{ + uint8_t status = 0x07; + + // Verify radio frequency + if( Radio.CheckRfFrequency( rxParamSetupReq->Frequency ) == false ) + { + status &= 0xFE; // Channel frequency KO + } + + // Verify datarate + if( RegionCommonValueInRange( rxParamSetupReq->Datarate, KR920_RX_MIN_DATARATE, KR920_RX_MAX_DATARATE ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify datarate offset + if( RegionCommonValueInRange( rxParamSetupReq->DrOffset, KR920_MIN_RX1_DR_OFFSET, KR920_MAX_RX1_DR_OFFSET ) == false ) + { + status &= 0xFB; // Rx1DrOffset range KO + } + + return status; +} + +uint8_t RegionKR920NewChannelReq( NewChannelReqParams_t* newChannelReq ) +{ + uint8_t status = 0x03; + ChannelAddParams_t channelAdd; + ChannelRemoveParams_t channelRemove; + + if( newChannelReq->NewChannel->Frequency == 0 ) + { + channelRemove.ChannelId = newChannelReq->ChannelId; + + // Remove + if( RegionKR920ChannelsRemove( &channelRemove ) == false ) + { + status &= 0xFC; + } + } + else + { + channelAdd.NewChannel = newChannelReq->NewChannel; + channelAdd.ChannelId = newChannelReq->ChannelId; + + switch( RegionKR920ChannelAdd( &channelAdd ) ) + { + case LORAMAC_STATUS_OK: + { + break; + } + case LORAMAC_STATUS_FREQUENCY_INVALID: + { + status &= 0xFE; + break; + } + case LORAMAC_STATUS_DATARATE_INVALID: + { + status &= 0xFD; + break; + } + case LORAMAC_STATUS_FREQ_AND_DR_INVALID: + { + status &= 0xFC; + break; + } + default: + { + status &= 0xFC; + break; + } + } + } + + return status; +} + +int8_t RegionKR920TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ) +{ + return -1; +} + +uint8_t RegionKR920DlChannelReq( DlChannelReqParams_t* dlChannelReq ) +{ + uint8_t status = 0x03; + + // Verify if the frequency is supported + if( VerifyTxFreq( dlChannelReq->Rx1Frequency ) == false ) + { + status &= 0xFE; + } + + // Verify if an uplink frequency exists + if( Channels[dlChannelReq->ChannelId].Frequency == 0 ) + { + status &= 0xFD; + } + + // Apply Rx1 frequency, if the status is OK + if( status == 0x03 ) + { + Channels[dlChannelReq->ChannelId].Rx1Frequency = dlChannelReq->Rx1Frequency; + } + + return status; +} + +int8_t RegionKR920AlternateDr( AlternateDrParams_t* alternateDr ) +{ + int8_t datarate = 0; + + if( ( alternateDr->NbTrials % 48 ) == 0 ) + { + datarate = DR_0; + } + else if( ( alternateDr->NbTrials % 32 ) == 0 ) + { + datarate = DR_1; + } + else if( ( alternateDr->NbTrials % 24 ) == 0 ) + { + datarate = DR_2; + } + else if( ( alternateDr->NbTrials % 16 ) == 0 ) + { + datarate = DR_3; + } + else if( ( alternateDr->NbTrials % 8 ) == 0 ) + { + datarate = DR_4; + } + else + { + datarate = DR_5; + } + return datarate; +} + +void RegionKR920CalcBackOff( CalcBackOffParams_t* calcBackOff ) +{ + uint8_t channel = calcBackOff->Channel; + uint16_t dutyCycle = Bands[Channels[channel].Band].DCycle; + uint16_t joinDutyCycle = 0; + + // Reset time-off to initial value. + Bands[Channels[channel].Band].TimeOff = 0; + + if( calcBackOff->Joined == false ) + { + // Get the join duty cycle + joinDutyCycle = RegionCommonGetJoinDc( calcBackOff->ElapsedTime ); + // Apply the most restricting duty cycle + dutyCycle = MAX( dutyCycle, joinDutyCycle ); + // Apply band time-off. + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + else + { + if( calcBackOff->DutyCycleEnabled == true ) + { + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * dutyCycle - calcBackOff->TxTimeOnAir; + } + } +} + +bool RegionKR920NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ) +{ + uint8_t channelNext = 0; + uint8_t nbEnabledChannels = 0; + uint8_t delayTx = 0; + uint8_t enabledChannels[KR920_MAX_NB_CHANNELS] = { 0 }; + TimerTime_t nextTxDelay = 0; + + if( RegionCommonCountChannels( ChannelsMask, 0, 1 ) == 0 ) + { // Reactivate default channels + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + } + + if( nextChanParams->AggrTimeOff <= TimerGetElapsedTime( nextChanParams->LastAggrTx ) ) + { + // Reset Aggregated time off + *aggregatedTimeOff = 0; + + // Update bands Time OFF + nextTxDelay = RegionCommonUpdateBandTimeOff( nextChanParams->Joined, nextChanParams->DutyCycleEnabled, Bands, KR920_MAX_NB_BANDS ); + + // Search how many channels are enabled + nbEnabledChannels = CountNbOfEnabledChannels( nextChanParams->Joined, nextChanParams->Datarate, + ChannelsMask, Channels, + Bands, enabledChannels, &delayTx ); + } + else + { + delayTx++; + nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx ); + } + + if( nbEnabledChannels > 0 ) + { + for( uint8_t i = 0, j = randr( 0, nbEnabledChannels - 1 ); i < KR920_MAX_NB_CHANNELS; i++ ) + { + channelNext = enabledChannels[j]; + j = ( j + 1 ) % nbEnabledChannels; + + // Perform carrier sense for KR920_CARRIER_SENSE_TIME + // If the channel is free, we can stop the LBT mechanism + if( Radio.IsChannelFree( MODEM_LORA, Channels[channelNext].Frequency, KR920_RSSI_FREE_TH, KR920_CARRIER_SENSE_TIME ) == true ) + { + // Free channel found + *channel = channelNext; + *time = 0; + return true; + } + } + return false; + } + else + { + if( delayTx > 0 ) + { + // Delay transmission due to AggregatedTimeOff or to a band time off + *time = nextTxDelay; + return true; + } + // Datarate not supported by any channel, restore defaults + ChannelsMask[0] |= LC( 1 ) + LC( 2 ) + LC( 3 ); + *time = 0; + return false; + } +} + +LoRaMacStatus_t RegionKR920ChannelAdd( ChannelAddParams_t* channelAdd ) +{ + uint8_t band = 0; + bool drInvalid = false; + bool freqInvalid = false; + uint8_t id = channelAdd->ChannelId; + + if( id >= KR920_MAX_NB_CHANNELS ) + { + return LORAMAC_STATUS_PARAMETER_INVALID; + } + + // Validate the datarate range + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Min, KR920_TX_MIN_DATARATE, KR920_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( RegionCommonValueInRange( channelAdd->NewChannel->DrRange.Fields.Max, KR920_TX_MIN_DATARATE, KR920_TX_MAX_DATARATE ) == false ) + { + drInvalid = true; + } + if( channelAdd->NewChannel->DrRange.Fields.Min > channelAdd->NewChannel->DrRange.Fields.Max ) + { + drInvalid = true; + } + + // Default channels don't accept all values + if( id < KR920_NUMB_DEFAULT_CHANNELS ) + { + // All datarates are supported + // We are not allowed to change the frequency + if( channelAdd->NewChannel->Frequency != Channels[id].Frequency ) + { + freqInvalid = true; + } + } + + // Check frequency + if( freqInvalid == false ) + { + if( VerifyTxFreq( channelAdd->NewChannel->Frequency ) == false ) + { + freqInvalid = true; + } + } + + // Check status + if( ( drInvalid == true ) && ( freqInvalid == true ) ) + { + return LORAMAC_STATUS_FREQ_AND_DR_INVALID; + } + if( drInvalid == true ) + { + return LORAMAC_STATUS_DATARATE_INVALID; + } + if( freqInvalid == true ) + { + return LORAMAC_STATUS_FREQUENCY_INVALID; + } + + memcpy( &(Channels[id]), channelAdd->NewChannel, sizeof( Channels[id] ) ); + Channels[id].Band = band; + ChannelsMask[0] |= ( 1 << id ); + return LORAMAC_STATUS_OK; +} + +bool RegionKR920ChannelsRemove( ChannelRemoveParams_t* channelRemove ) +{ + uint8_t id = channelRemove->ChannelId; + + if( id < KR920_NUMB_DEFAULT_CHANNELS ) + { + return false; + } + + // Remove the channel from the list of channels + Channels[id] = ( ChannelParams_t ){ 0, 0, { 0 }, 0 }; + + return RegionCommonChanDisable( ChannelsMask, id, KR920_MAX_NB_CHANNELS ); +} + +void RegionKR920SetContinuousWave( ContinuousWaveParams_t* continuousWave ) +{ + int8_t txPowerLimited = LimitTxPower( continuousWave->TxPower, Bands[Channels[continuousWave->Channel].Band].TxMaxPower, continuousWave->Datarate, ChannelsMask ); + int8_t phyTxPower = 0; + uint32_t frequency = Channels[continuousWave->Channel].Frequency; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, continuousWave->MaxEirp, continuousWave->AntennaGain ); + + Radio.SetTxContinuousWave( frequency, phyTxPower, continuousWave->Timeout ); +} + +uint8_t RegionKR920ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +{ + int8_t datarate = dr - drOffset; + + if( datarate < 0 ) + { + datarate = DR_0; + } + return datarate; +} + +void RegionKR920RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ) +{ + RegionCommonRxBeaconSetupParams_t regionCommonRxBeaconSetup; + + regionCommonRxBeaconSetup.Datarates = DataratesKR920; + regionCommonRxBeaconSetup.Frequency = rxBeaconSetup->Frequency; + regionCommonRxBeaconSetup.BeaconSize = KR920_BEACON_SIZE; + regionCommonRxBeaconSetup.BeaconDatarate = KR920_BEACON_CHANNEL_DR; + regionCommonRxBeaconSetup.BeaconChannelBW = KR920_BEACON_CHANNEL_BW; + regionCommonRxBeaconSetup.RxTime = rxBeaconSetup->RxTime; + regionCommonRxBeaconSetup.SymbolTimeout = rxBeaconSetup->SymbolTimeout; + + RegionCommonRxBeaconSetup( ®ionCommonRxBeaconSetup ); + + // Store downlink datarate + *outDr = KR920_BEACON_CHANNEL_DR; +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionKR920.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionKR920.h new file mode 100644 index 00000000..d96bd7c7 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionKR920.h @@ -0,0 +1,524 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file RegionKR920.h + * + * \brief Region definition for KR920 + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGIONKR920 Region KR920 + * Implementation according to LoRaWAN Specification v1.0.2. + * \{ + */ +#ifndef __REGION_KR920_H__ +#define __REGION_KR920_H__ + +#include "LoRaMac.h" + +/*! + * LoRaMac maximum number of channels + */ +#define KR920_MAX_NB_CHANNELS 16 + +/*! + * Number of default channels + */ +#define KR920_NUMB_DEFAULT_CHANNELS 3 + +/*! + * Number of channels to apply for the CF list + */ +#define KR920_NUMB_CHANNELS_CF_LIST 5 + +/*! + * Minimal datarate that can be used by the node + */ +#define KR920_TX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define KR920_TX_MAX_DATARATE DR_5 + +/*! + * Minimal datarate that can be used by the node + */ +#define KR920_RX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define KR920_RX_MAX_DATARATE DR_5 + +/*! + * Default datarate used by the node + */ +#define KR920_DEFAULT_DATARATE DR_0 + +/*! + * Minimal Rx1 receive datarate offset + */ +#define KR920_MIN_RX1_DR_OFFSET 0 + +/*! + * Maximal Rx1 receive datarate offset + */ +#define KR920_MAX_RX1_DR_OFFSET 5 + +/*! + * Default Rx1 receive datarate offset + */ +#define KR920_DEFAULT_RX1_DR_OFFSET 0 + +/*! + * Minimal Tx output power that can be used by the node + */ +#define KR920_MIN_TX_POWER TX_POWER_7 + +/*! + * Maximal Tx output power that can be used by the node + */ +#define KR920_MAX_TX_POWER TX_POWER_0 + +/*! + * Default Tx output power used by the node + */ +#define KR920_DEFAULT_TX_POWER TX_POWER_0 + +/*! + * Default Max EIRP for frequency 920.9 MHz - 921.9 MHz + */ +#define KR920_DEFAULT_MAX_EIRP_LOW 10.0f + +/*! + * Default Max EIRP for frequency 922.1 MHz - 923.3 MHz + */ +#define KR920_DEFAULT_MAX_EIRP_HIGH 14.0f + +/*! + * Default antenna gain + */ +#define KR920_DEFAULT_ANTENNA_GAIN 2.15f + +/*! + * ADR Ack limit + */ +#define KR920_ADR_ACK_LIMIT 64 + +/*! + * ADR Ack delay + */ +#define KR920_ADR_ACK_DELAY 32 + +/*! + * Enabled or disabled the duty cycle + */ +#define KR920_DUTY_CYCLE_ENABLED 0 + +/*! + * Maximum RX window duration + */ +#define KR920_MAX_RX_WINDOW 4000 + +/*! + * Receive delay 1 + */ +#define KR920_RECEIVE_DELAY1 1000 + +/*! + * Receive delay 2 + */ +#define KR920_RECEIVE_DELAY2 2000 + +/*! + * Join accept delay 1 + */ +#define KR920_JOIN_ACCEPT_DELAY1 5000 + +/*! + * Join accept delay 2 + */ +#define KR920_JOIN_ACCEPT_DELAY2 6000 + +/*! + * Maximum frame counter gap + */ +#define KR920_MAX_FCNT_GAP 16384 + +/*! + * Ack timeout + */ +#define KR920_ACKTIMEOUT 2000 + +/*! + * Random ack timeout limits + */ +#define KR920_ACK_TIMEOUT_RND 1000 + +#if ( KR920_DEFAULT_DATARATE > DR_5 ) +#error "A default DR higher than DR_5 may lead to connectivity loss." +#endif + +/*! + * Second reception window channel frequency definition. + */ +#define KR920_RX_WND_2_FREQ 921900000 + +/*! + * Second reception window channel datarate definition. + */ +#define KR920_RX_WND_2_DR DR_0 + +/* + * CLASS B + */ +/*! + * Beacon frequency + */ +#define KR920_BEACON_CHANNEL_FREQ 923100000 + +/*! + * Payload size of a beacon frame + */ +#define KR920_BEACON_SIZE 17 + +/*! + * Size of RFU 1 field + */ +#define KR920_RFU1_SIZE 2 + +/*! + * Size of RFU 2 field + */ +#define KR920_RFU2_SIZE 0 + +/*! + * Datarate of the beacon channel + */ +#define KR920_BEACON_CHANNEL_DR DR_3 + +/*! + * Bandwith of the beacon channel + */ +#define KR920_BEACON_CHANNEL_BW 0 + +/*! + * Maximum number of bands + */ +#define KR920_MAX_NB_BANDS 1 + +/*! + * Band 0 definition + * { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define KR920_BAND0 { 1 , KR920_MAX_TX_POWER, 0, 0 } // 100.0 % + +/*! + * LoRaMac default channel 1 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define KR920_LC1 { 922100000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac default channel 2 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define KR920_LC2 { 922300000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac default channel 3 + * Channel = { Frequency [Hz], RX1 Frequency [Hz], { ( ( DrMax << 4 ) | DrMin ) }, Band } + */ +#define KR920_LC3 { 922500000, 0, { ( ( DR_5 << 4 ) | DR_0 ) }, 0 } + +/*! + * LoRaMac channels which are allowed for the join procedure + */ +#define KR920_JOIN_CHANNELS ( uint16_t )( LC( 1 ) | LC( 2 ) | LC( 3 ) ) + +/*! + * RSSI threshold for a free channel [dBm] + */ +#define KR920_RSSI_FREE_TH -65 + +/*! + * Specifies the time the node performs a carrier sense + */ +#define KR920_CARRIER_SENSE_TIME 6 + +/*! + * Data rates table definition + */ +static const uint8_t DataratesKR920[] = { 12, 11, 10, 9, 8, 7 }; + +/*! + * Bandwidths table definition in Hz + */ +static const uint32_t BandwidthsKR920[] = { 125000, 125000, 125000, 125000, 125000, 125000 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with and without a repeater. + */ +static const uint8_t MaxPayloadOfDatarateKR920[] = { 51, 51, 51, 115, 242, 242 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateRepeaterKR920[] = { 51, 51, 51, 115, 222, 222 }; + +/*! + * \brief The function gets a value of a specific phy attribute. + * + * \param [IN] getPhy Pointer to the function parameters. + * + * \retval Returns a structure containing the PHY parameter. + */ +PhyParam_t RegionKR920GetPhyParam( GetPhyParams_t* getPhy ); + +/*! + * \brief Updates the last TX done parameters of the current channel. + * + * \param [IN] txDone Pointer to the function parameters. + */ +void RegionKR920SetBandTxDone( SetBandTxDoneParams_t* txDone ); + +/*! + * \brief Initializes the channels masks and the channels. + * + * \param [IN] type Sets the initialization type. + */ +void RegionKR920InitDefaults( InitType_t type ); + +/*! + * \brief Verifies a parameter. + * + * \param [IN] verify Pointer to the function parameters. + * + * \param [IN] type Sets the initialization type. + * + * \retval Returns true, if the parameter is valid. + */ +bool RegionKR920Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ); + +/*! + * \brief The function parses the input buffer and sets up the channels of the + * CF list. + * + * \param [IN] applyCFList Pointer to the function parameters. + */ +void RegionKR920ApplyCFList( ApplyCFListParams_t* applyCFList ); + +/*! + * \brief Sets a channels mask. + * + * \param [IN] chanMaskSet Pointer to the function parameters. + * + * \retval Returns true, if the channels mask could be set. + */ +bool RegionKR920ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ); + +/*! + * \brief Calculates the next datarate to set, when ADR is on or off. + * + * \param [IN] adrNext Pointer to the function parameters. + * + * \param [OUT] drOut The calculated datarate for the next TX. + * + * \param [OUT] txPowOut The TX power for the next TX. + * + * \param [OUT] adrAckCounter The calculated ADR acknowledgement counter. + * + * \retval Returns true, if an ADR request should be performed. + */ +bool RegionKR920AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ); + +/*! + * Computes the Rx window timeout and offset. + * + * \param [IN] datarate Rx window datarate index to be used + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms + * interval around RxOffset + * + * \param [OUT]rxConfigParams Returns updated WindowTimeout and WindowOffset fields. + */ +void RegionKR920ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ); + +/*! + * \brief Configuration of the RX windows. + * + * \param [IN] rxConfig Pointer to the function parameters. + * + * \param [OUT] datarate The datarate index which was set. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionKR920RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ); + +/*! + * \brief TX configuration. + * + * \param [IN] txConfig Pointer to the function parameters. + * + * \param [OUT] txPower The tx power index which was set. + * + * \param [OUT] txTimeOnAir The time-on-air of the frame. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionKR920TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ); + +/*! + * \brief The function processes a Link ADR Request. + * + * \param [IN] linkAdrReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionKR920LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ); + +/*! + * \brief The function processes a RX Parameter Setup Request. + * + * \param [IN] rxParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionKR920RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ); + +/*! + * \brief The function processes a Channel Request. + * + * \param [IN] newChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionKR920NewChannelReq( NewChannelReqParams_t* newChannelReq ); + +/*! + * \brief The function processes a TX ParamSetup Request. + * + * \param [IN] txParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + * Returns -1, if the functionality is not implemented. In this case, the end node + * shall not process the command. + */ +int8_t RegionKR920TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ); + +/*! + * \brief The function processes a DlChannel Request. + * + * \param [IN] dlChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionKR920DlChannelReq( DlChannelReqParams_t* dlChannelReq ); + +/*! + * \brief Alternates the datarate of the channel for the join request. + * + * \param [IN] alternateDr Pointer to the function parameters. + * + * \retval Datarate to apply. + */ +int8_t RegionKR920AlternateDr( AlternateDrParams_t* alternateDr ); + +/*! + * \brief Calculates the back-off time. + * + * \param [IN] calcBackOff Pointer to the function parameters. + */ +void RegionKR920CalcBackOff( CalcBackOffParams_t* calcBackOff ); + +/*! + * \brief Searches and set the next random available channel + * + * \param [OUT] channel Next channel to use for TX. + * + * \param [OUT] time Time to wait for the next transmission according to the duty + * cycle. + * + * \param [OUT] aggregatedTimeOff Updates the aggregated time off. + * + * \retval Function status [1: OK, 0: Unable to find a channel on the current datarate] + */ +bool RegionKR920NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ); + +/*! + * \brief Adds a channel. + * + * \param [IN] channelAdd Pointer to the function parameters. + * + * \retval Status of the operation. + */ +LoRaMacStatus_t RegionKR920ChannelAdd( ChannelAddParams_t* channelAdd ); + +/*! + * \brief Removes a channel. + * + * \param [IN] channelRemove Pointer to the function parameters. + * + * \retval Returns true, if the channel was removed successfully. + */ +bool RegionKR920ChannelsRemove( ChannelRemoveParams_t* channelRemove ); + +/*! + * \brief Sets the radio into continuous wave mode. + * + * \param [IN] continuousWave Pointer to the function parameters. + */ +void RegionKR920SetContinuousWave( ContinuousWaveParams_t* continuousWave ); + +/*! + * \brief Computes new datarate according to the given offset + * + * \param [IN] downlinkDwellTime Downlink dwell time configuration. 0: No limit, 1: 400ms + * + * \param [IN] dr Current datarate + * + * \param [IN] drOffset Offset to be applied + * + * \retval newDr Computed datarate. + */ +uint8_t RegionKR920ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ); + +/*! + * \brief Sets the radio into beacon reception mode + * + * \param [IN] rxBeaconSetup Pointer to the function parameters + */ + void RegionKR920RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ); + +/*! \} defgroup REGIONKR920 */ + +#endif // __REGION_KR920_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915-Hybrid.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915-Hybrid.c new file mode 100644 index 00000000..d2238c99 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915-Hybrid.c @@ -0,0 +1,1017 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC region US915 Hybrid implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include +#include + +#include "radio.h" +//#include "timer.h" +#include "timeServer.h" +#include "LoRaMac.h" + +#include "utilities.h" + +#include "Region.h" +#include "RegionCommon.h" +#include "RegionUS915-Hybrid.h" +#include "debug.h" + +// Definitions +#define CHANNELS_MASK_SIZE 6 + +// Global attributes +/*! + * LoRaMAC channels + */ +static ChannelParams_t Channels[US915_HYBRID_MAX_NB_CHANNELS]; + +/*! + * LoRaMac bands + */ +static Band_t Bands[US915_HYBRID_MAX_NB_BANDS] = +{ + US915_HYBRID_BAND0 +}; + +/*! + * LoRaMac channels mask + */ +static uint16_t ChannelsMask[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels remaining + */ +static uint16_t ChannelsMaskRemaining[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels default mask + */ +static uint16_t ChannelsDefaultMask[CHANNELS_MASK_SIZE]; + +// Static functions +static int8_t GetNextLowerTxDr( int8_t dr, int8_t minDr ) +{ + uint8_t nextLowerDr = 0; + + if( dr == minDr ) + { + nextLowerDr = minDr; + } + else + { + nextLowerDr = dr - 1; + } + return nextLowerDr; +} + +static uint32_t GetBandwidth( uint32_t drIndex ) +{ + switch( BandwidthsUS915_HYBRID[drIndex] ) + { + default: + case 125000: + return 0; + case 250000: + return 1; + case 500000: + return 2; + } +} + +static void ReenableChannels( uint16_t mask, uint16_t* channelsMask ) +{ + uint16_t blockMask = mask; + + for( uint8_t i = 0, j = 0; i < 4; i++, j += 2 ) + { + channelsMask[i] = 0; + if( ( blockMask & ( 1 << j ) ) != 0 ) + { + channelsMask[i] |= 0x00FF; + } + if( ( blockMask & ( 1 << ( j + 1 ) ) ) != 0 ) + { + channelsMask[i] |= 0xFF00; + } + } + channelsMask[4] = blockMask; + channelsMask[5] = 0x0000; +} + +static uint8_t CountBits( uint16_t mask, uint8_t nbBits ) +{ + uint8_t nbActiveBits = 0; + + for( uint8_t j = 0; j < nbBits; j++ ) + { + if( ( mask & ( 1 << j ) ) == ( 1 << j ) ) + { + nbActiveBits++; + } + } + return nbActiveBits; +} + +static int8_t LimitTxPower( int8_t txPower, int8_t maxBandTxPower, int8_t datarate, uint16_t* channelsMask ) +{ + int8_t txPowerResult = txPower; + + // Limit tx power to the band max + txPowerResult = MAX( txPower, maxBandTxPower ); + + if( datarate == DR_4 ) + {// Limit tx power to max 26dBm + txPowerResult = MAX( txPower, TX_POWER_2 ); + } + else + { + if( RegionCommonCountChannels( channelsMask, 0, 4 ) < 50 ) + {// Limit tx power to max 21dBm + txPowerResult = MAX( txPower, TX_POWER_5 ); + } + } + return txPowerResult; +} + +static bool ValidateChannelsMask( uint16_t* channelsMask ) +{ + bool chanMaskState = false; + uint16_t block1 = 0; + uint16_t block2 = 0; + uint8_t index = 0; + uint16_t channelsMaskCpy[6]; + + // Copy channels mask to not change the input + for( uint8_t i = 0; i < 4; i++ ) + { + channelsMaskCpy[i] = channelsMask[i]; + } + + for( uint8_t i = 0; i < 4; i++ ) + { + block1 = channelsMaskCpy[i] & 0x00FF; + block2 = channelsMaskCpy[i] & 0xFF00; + + if( CountBits( block1, 16 ) > 5 ) + { + channelsMaskCpy[i] &= block1; + channelsMaskCpy[4] = 1 << ( i * 2 ); + chanMaskState = true; + index = i; + break; + } + else if( CountBits( block2, 16 ) > 5 ) + { + channelsMaskCpy[i] &= block2; + channelsMaskCpy[4] = 1 << ( i * 2 + 1 ); + chanMaskState = true; + index = i; + break; + } + } + + // Do only change the channel mask, if we have found a valid block. + if( chanMaskState == true ) + { + // Copy channels mask back again + for( uint8_t i = 0; i < 4; i++ ) + { + channelsMask[i] = channelsMaskCpy[i]; + + if( i != index ) + { + channelsMask[i] = 0; + } + } + channelsMask[4] = channelsMaskCpy[4]; + } + return chanMaskState; +} + +static uint8_t CountNbOfEnabledChannels( uint8_t datarate, uint16_t* channelsMask, ChannelParams_t* channels, Band_t* bands, uint8_t* enabledChannels, uint8_t* delayTx ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTransmission = 0; + + for( uint8_t i = 0, k = 0; i < US915_HYBRID_MAX_NB_CHANNELS; i += 16, k++ ) + { + for( uint8_t j = 0; j < 16; j++ ) + { + if( ( channelsMask[k] & ( 1 << j ) ) != 0 ) + { + if( channels[i + j].Frequency == 0 ) + { // Check if the channel is enabled + continue; + } + if( RegionCommonValueInRange( datarate, channels[i + j].DrRange.Fields.Min, + channels[i + j].DrRange.Fields.Max ) == false ) + { // Check if the current channel selection supports the given datarate + continue; + } + if( bands[channels[i + j].Band].TimeOff > 0 ) + { // Check if the band is available for transmission + delayTransmission++; + continue; + } + enabledChannels[nbEnabledChannels++] = i + j; + } + } + } + + *delayTx = delayTransmission; + return nbEnabledChannels; +} + +PhyParam_t RegionUS915HybridGetPhyParam( GetPhyParams_t* getPhy ) +{ + PhyParam_t phyParam = { 0 }; + + switch( getPhy->Attribute ) + { + case PHY_MIN_RX_DR: + { + phyParam.Value = US915_HYBRID_RX_MIN_DATARATE; + break; + } + case PHY_MIN_TX_DR: + { + phyParam.Value = US915_HYBRID_TX_MIN_DATARATE; + break; + } + case PHY_DEF_TX_DR: + { + phyParam.Value = US915_HYBRID_DEFAULT_DATARATE; + break; + } + case PHY_NEXT_LOWER_TX_DR: + { + phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, US915_HYBRID_TX_MIN_DATARATE ); + break; + } + case PHY_DEF_TX_POWER: + { + phyParam.Value = US915_HYBRID_DEFAULT_TX_POWER; + break; + } + case PHY_MAX_PAYLOAD: + { + phyParam.Value = MaxPayloadOfDatarateUS915_HYBRID[getPhy->Datarate]; + break; + } + case PHY_MAX_PAYLOAD_REPEATER: + { + phyParam.Value = MaxPayloadOfDatarateRepeaterUS915_HYBRID[getPhy->Datarate]; + break; + } + case PHY_DUTY_CYCLE: + { + phyParam.Value = US915_HYBRID_DUTY_CYCLE_ENABLED; + break; + } + case PHY_MAX_RX_WINDOW: + { + phyParam.Value = US915_HYBRID_MAX_RX_WINDOW; + break; + } + case PHY_RECEIVE_DELAY1: + { + phyParam.Value = US915_HYBRID_RECEIVE_DELAY1; + break; + } + case PHY_RECEIVE_DELAY2: + { + phyParam.Value = US915_HYBRID_RECEIVE_DELAY2; + break; + } + case PHY_JOIN_ACCEPT_DELAY1: + { + phyParam.Value = US915_HYBRID_JOIN_ACCEPT_DELAY1; + break; + } + case PHY_JOIN_ACCEPT_DELAY2: + { + phyParam.Value = US915_HYBRID_JOIN_ACCEPT_DELAY2; + break; + } + case PHY_MAX_FCNT_GAP: + { + phyParam.Value = US915_HYBRID_MAX_FCNT_GAP; + break; + } + case PHY_ACK_TIMEOUT: + { + phyParam.Value = ( US915_HYBRID_ACKTIMEOUT + randr( -US915_HYBRID_ACK_TIMEOUT_RND, US915_HYBRID_ACK_TIMEOUT_RND ) ); + break; + } + case PHY_DEF_DR1_OFFSET: + { + phyParam.Value = US915_HYBRID_DEFAULT_RX1_DR_OFFSET; + break; + } + case PHY_DEF_RX2_FREQUENCY: + { + phyParam.Value = US915_HYBRID_RX_WND_2_FREQ; + break; + } + case PHY_DEF_RX2_DR: + { + phyParam.Value = US915_HYBRID_RX_WND_2_DR; + break; + } + case PHY_CHANNELS_MASK: + { + phyParam.ChannelsMask = ChannelsMask; + break; + } + case PHY_CHANNELS_DEFAULT_MASK: + { + phyParam.ChannelsMask = ChannelsDefaultMask; + break; + } + case PHY_MAX_NB_CHANNELS: + { + phyParam.Value = US915_HYBRID_MAX_NB_CHANNELS; + break; + } + case PHY_CHANNELS: + { + phyParam.Channels = Channels; + break; + } + case PHY_DEF_UPLINK_DWELL_TIME: + case PHY_DEF_DOWNLINK_DWELL_TIME: + { + phyParam.Value = 0; + break; + } + case PHY_DEF_MAX_EIRP: + case PHY_DEF_ANTENNA_GAIN: + { + phyParam.fValue = 0; + break; + } + case PHY_NB_JOIN_TRIALS: + case PHY_DEF_NB_JOIN_TRIALS: + { + phyParam.Value = 2; + break; + } + case PHY_BEACON_CHANNEL_FREQ: + { + phyParam.Value = US915_HYBRID_BEACON_CHANNEL_FREQ; + break; + } + case PHY_BEACON_FORMAT: + { + phyParam.BeaconFormat.BeaconSize = US915_HYBRID_BEACON_SIZE; + phyParam.BeaconFormat.Rfu1Size = US915_HYBRID_RFU1_SIZE; + phyParam.BeaconFormat.Rfu2Size = US915_HYBRID_RFU2_SIZE; + break; + } + case PHY_BEACON_CHANNEL_DR: + { + phyParam.Value = US915_HYBRID_BEACON_CHANNEL_DR; + break; + } + case PHY_BEACON_CHANNEL_STEPWIDTH: + { + phyParam.Value = US915_HYBRID_BEACON_CHANNEL_STEPWIDTH; + break; + } + case PHY_BEACON_NB_CHANNELS: + { + phyParam.Value = US915_HYBRID_BEACON_NB_CHANNELS; + break; + } + default: + { + break; + } + } + + return phyParam; +} + +void RegionUS915HybridSetBandTxDone( SetBandTxDoneParams_t* txDone ) +{ + RegionCommonSetBandTxDone( txDone->Joined, &Bands[Channels[txDone->Channel].Band], txDone->LastTxDoneTime ); +} + +void RegionUS915HybridInitDefaults( InitType_t type ) +{ + switch( type ) + { + case INIT_TYPE_INIT: + { + // Channels + // 125 kHz channels + for( uint8_t i = 0; i < US915_HYBRID_MAX_NB_CHANNELS - 8; i++ ) + { + Channels[i].Frequency = 902300000 + i * 200000; + Channels[i].DrRange.Value = ( DR_3 << 4 ) | DR_0; + Channels[i].Band = 0; + } + // 500 kHz channels + for( uint8_t i = US915_HYBRID_MAX_NB_CHANNELS - 8; i < US915_HYBRID_MAX_NB_CHANNELS; i++ ) + { + Channels[i].Frequency = 903000000 + ( i - ( US915_HYBRID_MAX_NB_CHANNELS - 8 ) ) * 1600000; + Channels[i].DrRange.Value = ( DR_4 << 4 ) | DR_4; + Channels[i].Band = 0; + } + + // ChannelsMask + ChannelsDefaultMask[0] = 0x00FF; + ChannelsDefaultMask[1] = 0x0000; + ChannelsDefaultMask[2] = 0x0000; + ChannelsDefaultMask[3] = 0x0000; + ChannelsDefaultMask[4] = 0x0001; + ChannelsDefaultMask[5] = 0x0000; + + // Copy channels default mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 6 ); + + // Copy into channels mask remaining + RegionCommonChanMaskCopy( ChannelsMaskRemaining, ChannelsMask, 6 ); + break; + } + case INIT_TYPE_RESTORE: + { + ReenableChannels( ChannelsDefaultMask[4], ChannelsMask ); + + for( uint8_t i = 0; i < 6; i++ ) + { // Copy-And the channels mask + ChannelsMaskRemaining[i] &= ChannelsMask[i]; + } + } + default: + { + break; + } + } +} + +bool RegionUS915HybridVerify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ) +{ + switch( phyAttribute ) + { + case PHY_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, US915_HYBRID_TX_MIN_DATARATE, US915_HYBRID_TX_MAX_DATARATE ); + } + case PHY_DEF_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, DR_0, DR_5 ); + } + case PHY_RX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, US915_HYBRID_RX_MIN_DATARATE, US915_HYBRID_RX_MAX_DATARATE ); + } + case PHY_DEF_TX_POWER: + case PHY_TX_POWER: + { + // Remark: switched min and max! + return RegionCommonValueInRange( verify->TxPower, US915_HYBRID_MAX_TX_POWER, US915_HYBRID_MIN_TX_POWER ); + } + case PHY_DUTY_CYCLE: + { + return US915_HYBRID_DUTY_CYCLE_ENABLED; + } + case PHY_NB_JOIN_TRIALS: + { + if( verify->NbJoinTrials < 2 ) + { + return false; + } + break; + } + default: + return false; + } + return true; +} + +void RegionUS915HybridApplyCFList( ApplyCFListParams_t* applyCFList ) +{ + return; +} + +bool RegionUS915HybridChanMaskSet( ChanMaskSetParams_t* chanMaskSet ) +{ + uint8_t nbChannels = RegionCommonCountChannels( chanMaskSet->ChannelsMaskIn, 0, 4 ); + + // Check the number of active channels + if( ( nbChannels < 2 ) && + ( nbChannels > 0 ) ) + { + return false; + } + + // Validate the channels mask + if( ValidateChannelsMask( chanMaskSet->ChannelsMaskIn ) == false ) + { + return false; + } + + switch( chanMaskSet->ChannelsMaskType ) + { + case CHANNELS_MASK: + { + RegionCommonChanMaskCopy( ChannelsMask, chanMaskSet->ChannelsMaskIn, 6 ); + + for( uint8_t i = 0; i < 6; i++ ) + { // Copy-And the channels mask + ChannelsMaskRemaining[i] &= ChannelsMask[i]; + } + break; + } + case CHANNELS_DEFAULT_MASK: + { + RegionCommonChanMaskCopy( ChannelsDefaultMask, chanMaskSet->ChannelsMaskIn, 6 ); + break; + } + default: + return false; + } + return true; +} + +bool RegionUS915HybridAdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ) +{ + bool adrAckReq = false; + int8_t datarate = adrNext->Datarate; + int8_t txPower = adrNext->TxPower; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + // Report back the adr ack counter + *adrAckCounter = adrNext->AdrAckCounter; + + if( adrNext->AdrEnabled == true ) + { + if( datarate == US915_HYBRID_TX_MIN_DATARATE ) + { + *adrAckCounter = 0; + adrAckReq = false; + } + else + { + if( adrNext->AdrAckCounter >= US915_HYBRID_ADR_ACK_LIMIT ) + { + adrAckReq = true; + txPower = US915_HYBRID_MAX_TX_POWER; + } + else + { + adrAckReq = false; + } + if( adrNext->AdrAckCounter >= ( US915_HYBRID_ADR_ACK_LIMIT + US915_HYBRID_ADR_ACK_DELAY ) ) + { + if( ( adrNext->AdrAckCounter % US915_HYBRID_ADR_ACK_DELAY ) == 1 ) + { + // Decrease the datarate + getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + getPhy.Datarate = datarate; + getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + phyParam = RegionUS915HybridGetPhyParam( &getPhy ); + datarate = phyParam.Value; + + if( datarate == US915_HYBRID_TX_MIN_DATARATE ) + { + // We must set adrAckReq to false as soon as we reach the lowest datarate + adrAckReq = false; + if( adrNext->UpdateChanMask == true ) + { + // Re-enable default channels + ReenableChannels( ChannelsMask[4], ChannelsMask ); + } + } + } + } + } + } + + *drOut = datarate; + *txPowOut = txPower; + return adrAckReq; +} + +void RegionUS915HybridComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ) +{ + double tSymbol = 0.0; + uint32_t radioWakeUpTime; + + rxConfigParams->Datarate = datarate; + rxConfigParams->Bandwidth = GetBandwidth( datarate ); + + if( datarate == DR_7 ) + { // FSK + tSymbol = RegionCommonComputeSymbolTimeFsk( DataratesUS915_HYBRID[datarate] ); + } + else + { // LoRa + tSymbol = RegionCommonComputeSymbolTimeLoRa( DataratesUS915_HYBRID[datarate], BandwidthsUS915_HYBRID[datarate] ); + } + + radioWakeUpTime = Radio.GetWakeupTime( ); + RegionCommonComputeRxWindowParameters( tSymbol, minRxSymbols, rxError, radioWakeUpTime, &rxConfigParams->WindowTimeout, &rxConfigParams->WindowOffset ); +} + +bool RegionUS915HybridRxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ) +{ + int8_t dr = rxConfig->Datarate; + uint8_t maxPayload = 0; + int8_t phyDr = 0; + uint32_t frequency = rxConfig->Frequency; + + if( Radio.GetStatus( ) != RF_IDLE ) + { + return false; + } + + if( rxConfig->RxSlot == RX_SLOT_WIN_1 ) + { + // Apply window 1 frequency + frequency = US915_HYBRID_FIRST_RX1_CHANNEL + ( rxConfig->Channel % 8 ) * US915_HYBRID_STEPWIDTH_RX1_CHANNEL; + } + + // Read the physical datarate from the datarates table + phyDr = DataratesUS915_HYBRID[dr]; + + Radio.SetChannel( frequency ); + + // Radio configuration + Radio.SetRxConfig( MODEM_LORA, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, false, 0, false, 0, 0, true, rxConfig->RxContinuous ); + + if( rxConfig->RepeaterSupport == true ) + { + maxPayload = MaxPayloadOfDatarateRepeaterUS915_HYBRID[dr]; + } + else + { + maxPayload = MaxPayloadOfDatarateUS915_HYBRID[dr]; + } + Radio.SetMaxPayloadLength( MODEM_LORA, maxPayload + LORA_MAC_FRMPAYLOAD_OVERHEAD ); + DBG_PRINTF("RX on freq %u Hz at DR %d\n\r", (unsigned int)frequency, dr); + + *datarate = (uint8_t) dr; + return true; +} + +bool RegionUS915HybridTxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) +{ + int8_t phyDr = DataratesUS915_HYBRID[txConfig->Datarate]; + int8_t txPowerLimited = LimitTxPower( txConfig->TxPower, Bands[Channels[txConfig->Channel].Band].TxMaxPower, txConfig->Datarate, ChannelsMask ); + uint32_t bandwidth = GetBandwidth( txConfig->Datarate ); + int8_t phyTxPower = 0; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, US915_HYBRID_DEFAULT_MAX_ERP, 0 ); + + Radio.SetChannel( Channels[txConfig->Channel].Frequency ); + + Radio.SetMaxPayloadLength( MODEM_LORA, txConfig->PktLen ); + Radio.SetTxConfig( MODEM_LORA, phyTxPower, 0, bandwidth, phyDr, 1, 8, false, true, 0, 0, false, 3e3 ); + DBG_PRINTF("TX on freq %u Hz at DR %d\n\r", (unsigned int)Channels[txConfig->Channel].Frequency, txConfig->Datarate); + + *txTimeOnAir = Radio.TimeOnAir( MODEM_LORA, txConfig->PktLen ); + *txPower = txPowerLimited; + + return true; +} + +uint8_t RegionUS915HybridLinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ) +{ + uint8_t status = 0x07; + LinkAdrParams_t linkAdrParams; + uint8_t nextIndex = 0; + uint8_t bytesProcessed = 0; + uint16_t channelsMask[6] = { 0, 0, 0, 0, 0, 0 }; + + // Initialize local copy of channels mask + RegionCommonChanMaskCopy( channelsMask, ChannelsMask, 6 ); + + while( bytesProcessed < linkAdrReq->PayloadSize ) + { + nextIndex = RegionCommonParseLinkAdrReq( &( linkAdrReq->Payload[bytesProcessed] ), &linkAdrParams ); + + if( nextIndex == 0 ) + break; // break loop, since no more request has been found + + // Update bytes processed + bytesProcessed += nextIndex; + + // Revert status, as we only check the last ADR request for the channel mask KO + status = 0x07; + + if( linkAdrParams.ChMaskCtrl == 6 ) + { + // Enable all 125 kHz channels + channelsMask[0] = 0xFFFF; + channelsMask[1] = 0xFFFF; + channelsMask[2] = 0xFFFF; + channelsMask[3] = 0xFFFF; + // Apply chMask to channels 64 to 71 + channelsMask[4] = linkAdrParams.ChMask; + } + else if( linkAdrParams.ChMaskCtrl == 7 ) + { + // Disable all 125 kHz channels + channelsMask[0] = 0x0000; + channelsMask[1] = 0x0000; + channelsMask[2] = 0x0000; + channelsMask[3] = 0x0000; + // Apply chMask to channels 64 to 71 + channelsMask[4] = linkAdrParams.ChMask; + } + else if( linkAdrParams.ChMaskCtrl == 5 ) + { + // RFU + status &= 0xFE; // Channel mask KO + } + else + { + channelsMask[linkAdrParams.ChMaskCtrl] = linkAdrParams.ChMask; + } + } + + // FCC 15.247 paragraph F mandates to hop on at least 2 125 kHz channels + if( ( linkAdrParams.Datarate < DR_4 ) && ( RegionCommonCountChannels( channelsMask, 0, 4 ) < 2 ) ) + { + status &= 0xFE; // Channel mask KO + } + + if( ValidateChannelsMask( channelsMask ) == false ) + { + status &= 0xFE; // Channel mask KO + } + + // Verify datarate + if( RegionCommonChanVerifyDr( US915_HYBRID_MAX_NB_CHANNELS, channelsMask, linkAdrParams.Datarate, US915_HYBRID_TX_MIN_DATARATE, US915_HYBRID_TX_MAX_DATARATE, Channels ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify tx power + if( RegionCommonValueInRange( linkAdrParams.TxPower, US915_HYBRID_MAX_TX_POWER, US915_HYBRID_MIN_TX_POWER ) == 0 ) + { + // Verify if the maximum TX power is exceeded + if( US915_HYBRID_MAX_TX_POWER > linkAdrParams.TxPower ) + { // Apply maximum TX power. Accept TX power. + linkAdrParams.TxPower = US915_HYBRID_MAX_TX_POWER; + } + else + { + status &= 0xFB; // TxPower KO + } + } + + // Update channelsMask if everything is correct + if( status == 0x07 ) + { + if( linkAdrParams.NbRep == 0 ) + { // Value of 0 is not allowed, revert to default. + linkAdrParams.NbRep = 1; + } + + // Copy Mask + RegionCommonChanMaskCopy( ChannelsMask, channelsMask, 6 ); + + ChannelsMaskRemaining[0] &= ChannelsMask[0]; + ChannelsMaskRemaining[1] &= ChannelsMask[1]; + ChannelsMaskRemaining[2] &= ChannelsMask[2]; + ChannelsMaskRemaining[3] &= ChannelsMask[3]; + ChannelsMaskRemaining[4] = ChannelsMask[4]; + ChannelsMaskRemaining[5] = ChannelsMask[5]; + } + + // Update status variables + *drOut = linkAdrParams.Datarate; + *txPowOut = linkAdrParams.TxPower; + *nbRepOut = linkAdrParams.NbRep; + *nbBytesParsed = bytesProcessed; + + return status; +} + +uint8_t RegionUS915HybridRxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ) +{ + uint8_t status = 0x07; + uint32_t freq = rxParamSetupReq->Frequency; + + // Verify radio frequency + if( ( Radio.CheckRfFrequency( freq ) == false ) || + ( freq < US915_HYBRID_FIRST_RX1_CHANNEL ) || + ( freq > US915_HYBRID_LAST_RX1_CHANNEL ) || + ( ( ( freq - ( uint32_t ) US915_HYBRID_FIRST_RX1_CHANNEL ) % ( uint32_t ) US915_HYBRID_STEPWIDTH_RX1_CHANNEL ) != 0 ) ) + { + status &= 0xFE; // Channel frequency KO + } + + // Verify datarate + if( RegionCommonValueInRange( rxParamSetupReq->Datarate, US915_HYBRID_RX_MIN_DATARATE, US915_HYBRID_RX_MAX_DATARATE ) == false ) + { + status &= 0xFD; // Datarate KO + } + if( ( RegionCommonValueInRange( rxParamSetupReq->Datarate, DR_5, DR_7 ) == true ) || + ( rxParamSetupReq->Datarate > DR_13 ) ) + { + status &= 0xFD; // Datarate KO + } + + // Verify datarate offset + if( RegionCommonValueInRange( rxParamSetupReq->DrOffset, US915_HYBRID_MIN_RX1_DR_OFFSET, US915_HYBRID_MAX_RX1_DR_OFFSET ) == false ) + { + status &= 0xFB; // Rx1DrOffset range KO + } + + return status; +} + +uint8_t RegionUS915HybridNewChannelReq( NewChannelReqParams_t* newChannelReq ) +{ + // Datarate and frequency KO + return 0; +} + +int8_t RegionUS915HybridTxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ) +{ + return -1; +} + +uint8_t RegionUS915HybridDlChannelReq( DlChannelReqParams_t* dlChannelReq ) +{ + return 0; +} + +int8_t RegionUS915HybridAlternateDr( AlternateDrParams_t* alternateDr ) +{ + int8_t datarate = 0; + + // Re-enable 500 kHz default channels + ReenableChannels( ChannelsMask[4], ChannelsMask ); + + if( ( alternateDr->NbTrials & 0x01 ) == 0x01 ) + { + datarate = DR_4; + } + else + { + datarate = DR_0; + } + return datarate; +} + +void RegionUS915HybridCalcBackOff( CalcBackOffParams_t* calcBackOff ) +{ + uint8_t channel = calcBackOff->Channel; + uint16_t joinDutyCycle = 0; + + if( calcBackOff->Joined == false ) + { + // Get the join duty cycle + joinDutyCycle = RegionCommonGetJoinDc( calcBackOff->ElapsedTime ); + // Apply band time-off. + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * joinDutyCycle - calcBackOff->TxTimeOnAir; + } + else + { + Bands[Channels[channel].Band].TimeOff = 0; + } +} + +bool RegionUS915HybridNextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTx = 0; + uint8_t enabledChannels[US915_HYBRID_MAX_NB_CHANNELS] = { 0 }; + TimerTime_t nextTxDelay = 0; + + // Count 125kHz channels + if( RegionCommonCountChannels( ChannelsMaskRemaining, 0, 4 ) == 0 ) + { // Reactivate default channels + RegionCommonChanMaskCopy( ChannelsMaskRemaining, ChannelsMask, 4 ); + } + // Check other channels + if( nextChanParams->Datarate >= DR_4 ) + { + if( ( ChannelsMaskRemaining[4] & 0x00FF ) == 0 ) + { + ChannelsMaskRemaining[4] = ChannelsMask[4]; + } + } + + if( nextChanParams->AggrTimeOff <= TimerGetElapsedTime( nextChanParams->LastAggrTx ) ) + { + // Reset Aggregated time off + *aggregatedTimeOff = 0; + + // Update bands Time OFF + nextTxDelay = RegionCommonUpdateBandTimeOff( nextChanParams->Joined, nextChanParams->DutyCycleEnabled, Bands, US915_HYBRID_MAX_NB_BANDS ); + + // Search how many channels are enabled + nbEnabledChannels = CountNbOfEnabledChannels( nextChanParams->Datarate, + ChannelsMaskRemaining, Channels, + Bands, enabledChannels, &delayTx ); + } + else + { + delayTx++; + nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx ); + } + + if( nbEnabledChannels > 0 ) + { + // We found a valid channel + *channel = enabledChannels[randr( 0, nbEnabledChannels - 1 )]; + // Disable the channel in the mask + RegionCommonChanDisable( ChannelsMaskRemaining, *channel, US915_HYBRID_MAX_NB_CHANNELS - 8 ); + + *time = 0; + return true; + } + else + { + if( delayTx > 0 ) + { + // Delay transmission due to AggregatedTimeOff or to a band time off + *time = nextTxDelay; + return true; + } + // Datarate not supported by any channel + *time = 0; + return false; + } +} + +LoRaMacStatus_t RegionUS915HybridChannelAdd( ChannelAddParams_t* channelAdd ) +{ + return LORAMAC_STATUS_PARAMETER_INVALID; +} + +bool RegionUS915HybridChannelsRemove( ChannelRemoveParams_t* channelRemove ) +{ + return LORAMAC_STATUS_PARAMETER_INVALID; +} + +void RegionUS915HybridSetContinuousWave( ContinuousWaveParams_t* continuousWave ) +{ + int8_t txPowerLimited = LimitTxPower( continuousWave->TxPower, Bands[Channels[continuousWave->Channel].Band].TxMaxPower, continuousWave->Datarate, ChannelsMask ); + int8_t phyTxPower = 0; + uint32_t frequency = Channels[continuousWave->Channel].Frequency; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, US915_HYBRID_DEFAULT_MAX_ERP, 0 ); + + Radio.SetTxContinuousWave( frequency, phyTxPower, continuousWave->Timeout ); +} + +uint8_t RegionUS915HybridApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +{ + int8_t datarate = DatarateOffsetsUS915_HYBRID[dr][drOffset]; + + if( datarate < 0 ) + { + datarate = DR_0; + } + return datarate; +} + +void RegionUS915HybridRxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ) +{ + RegionCommonRxBeaconSetupParams_t regionCommonRxBeaconSetup; + + regionCommonRxBeaconSetup.Datarates = DataratesUS915_HYBRID; + regionCommonRxBeaconSetup.Frequency = rxBeaconSetup->Frequency; + regionCommonRxBeaconSetup.BeaconSize = US915_HYBRID_BEACON_SIZE; + regionCommonRxBeaconSetup.BeaconDatarate = US915_HYBRID_BEACON_CHANNEL_DR; + regionCommonRxBeaconSetup.BeaconChannelBW = US915_HYBRID_BEACON_CHANNEL_BW; + regionCommonRxBeaconSetup.RxTime = rxBeaconSetup->RxTime; + regionCommonRxBeaconSetup.SymbolTimeout = rxBeaconSetup->SymbolTimeout; + + RegionCommonRxBeaconSetup( ®ionCommonRxBeaconSetup ); + + // Store downlink datarate + *outDr = US915_HYBRID_BEACON_CHANNEL_DR; +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915-Hybrid.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915-Hybrid.h new file mode 100644 index 00000000..afa1144b --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915-Hybrid.h @@ -0,0 +1,504 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file RegionUS915Hybrid-Hybrid.h + * + * \brief Region definition for US915 + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGIONUS915HYB Region US915 in hybrid mode + * This is a hybrid implementation for US915, supporting 16 uplink channels only. + * \{ + */ +#ifndef __REGION_US915_HYBRID_H__ +#define __REGION_US915_HYBRID_H__ + +#include "LoRaMac.h" + +/*! + * LoRaMac maximum number of channels + */ +#define US915_HYBRID_MAX_NB_CHANNELS 72 + +/*! + * Minimal datarate that can be used by the node + */ +#define US915_HYBRID_TX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define US915_HYBRID_TX_MAX_DATARATE DR_4 + +/*! + * Minimal datarate that can be used by the node + */ +#define US915_HYBRID_RX_MIN_DATARATE DR_8 + +/*! + * Maximal datarate that can be used by the node + */ +#define US915_HYBRID_RX_MAX_DATARATE DR_13 + +/*! + * Default datarate used by the node + */ +#define US915_HYBRID_DEFAULT_DATARATE DR_0 + +/*! + * Minimal Rx1 receive datarate offset + */ +#define US915_HYBRID_MIN_RX1_DR_OFFSET 0 + +/*! + * Maximal Rx1 receive datarate offset + */ +#define US915_HYBRID_MAX_RX1_DR_OFFSET 3 + +/*! + * Default Rx1 receive datarate offset + */ +#define US915_HYBRID_DEFAULT_RX1_DR_OFFSET 0 + +/*! + * Minimal Tx output power that can be used by the node + */ +#define US915_HYBRID_MIN_TX_POWER TX_POWER_10 + +/*! + * Maximal Tx output power that can be used by the node + */ +#define US915_HYBRID_MAX_TX_POWER TX_POWER_0 + +/*! + * Default Tx output power used by the node + */ +#define US915_HYBRID_DEFAULT_TX_POWER TX_POWER_0 + +/*! + * Default Max ERP + */ +#define US915_HYBRID_DEFAULT_MAX_ERP 30.0f + +/*! + * ADR Ack limit + */ +#define US915_HYBRID_ADR_ACK_LIMIT 64 + +/*! + * ADR Ack delay + */ +#define US915_HYBRID_ADR_ACK_DELAY 32 + +/*! + * Enabled or disabled the duty cycle + */ +#define US915_HYBRID_DUTY_CYCLE_ENABLED 0 + +/*! + * Maximum RX window duration + */ +#define US915_HYBRID_MAX_RX_WINDOW 3000 + +/*! + * Receive delay 1 + */ +#define US915_HYBRID_RECEIVE_DELAY1 1000 + +/*! + * Receive delay 2 + */ +#define US915_HYBRID_RECEIVE_DELAY2 2000 + +/*! + * Join accept delay 1 + */ +#define US915_HYBRID_JOIN_ACCEPT_DELAY1 5000 + +/*! + * Join accept delay 2 + */ +#define US915_HYBRID_JOIN_ACCEPT_DELAY2 6000 + +/*! + * Maximum frame counter gap + */ +#define US915_HYBRID_MAX_FCNT_GAP 16384 + +/*! + * Ack timeout + */ +#define US915_HYBRID_ACKTIMEOUT 2000 + +/*! + * Random ack timeout limits + */ +#define US915_HYBRID_ACK_TIMEOUT_RND 1000 + +/*! + * Second reception window channel frequency definition. + */ +#define US915_HYBRID_RX_WND_2_FREQ 923300000 + +/*! + * Second reception window channel datarate definition. + */ +#define US915_HYBRID_RX_WND_2_DR DR_8 + +/* + * CLASS B + */ +/*! + * Beacon frequency + */ + #define US915_HYBRID_BEACON_CHANNEL_FREQ 923300000 + +/*! + * Beacon frequency channel stepwidth + */ + #define US915_HYBRID_BEACON_CHANNEL_STEPWIDTH 600000 + +/*! + * Number of possible beacon channels + */ + #define US915_HYBRID_BEACON_NB_CHANNELS 8 + +/*! + * Payload size of a beacon frame + */ + #define US915_HYBRID_BEACON_SIZE 23 + +/*! + * Size of RFU 1 field + */ +#define US915_HYBRID_RFU1_SIZE 5 + +/*! + * Size of RFU 2 field + */ +#define US915_HYBRID_RFU2_SIZE 3 + +/*! + * Datarate of the beacon channel + */ + #define US915_HYBRID_BEACON_CHANNEL_DR DR_8 + +/*! + * Bandwith of the beacon channel + */ + #define US915_HYBRID_BEACON_CHANNEL_BW 2 + +/*! + * LoRaMac maximum number of bands + */ +#define US915_HYBRID_MAX_NB_BANDS 1 + +/*! + * Band 0 definition + * { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define US915_HYBRID_BAND0 { 1, US915_HYBRID_MAX_TX_POWER, 0, 0 } // 100.0 % + +/*! + * Defines the first channel for RX window 1 for US band + */ +#define US915_HYBRID_FIRST_RX1_CHANNEL ( (uint32_t) 923300000 ) + +/*! + * Defines the last channel for RX window 1 for US band + */ +#define US915_HYBRID_LAST_RX1_CHANNEL ( (uint32_t) 927500000 ) + +/*! + * Defines the step width of the channels for RX window 1 + */ +#define US915_HYBRID_STEPWIDTH_RX1_CHANNEL ( (uint32_t) 600000 ) + +/*! + * Data rates table definition + */ +static const uint8_t DataratesUS915_HYBRID[] = { 10, 9, 8, 7, 8, 0, 0, 0, 12, 11, 10, 9, 8, 7, 0, 0 }; + +/*! + * Bandwidths table definition in Hz + */ +static const uint32_t BandwidthsUS915_HYBRID[] = { 125000, 125000, 125000, 125000, 500000, 0, 0, 0, 500000, 500000, 500000, 500000, 500000, 500000, 0, 0 }; + +/*! + * Up/Down link data rates offset definition + */ +static const int8_t DatarateOffsetsUS915_HYBRID[5][4] = +{ + { DR_10, DR_9 , DR_8 , DR_8 }, // DR_0 + { DR_11, DR_10, DR_9 , DR_8 }, // DR_1 + { DR_12, DR_11, DR_10, DR_9 }, // DR_2 + { DR_13, DR_12, DR_11, DR_10 }, // DR_3 + { DR_13, DR_13, DR_12, DR_11 }, // DR_4 +}; + +/*! + * Maximum payload with respect to the datarate index. Cannot operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateUS915_HYBRID[] = { 11, 53, 125, 242, 242, 0, 0, 0, 53, 129, 242, 242, 242, 242, 0, 0 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateRepeaterUS915_HYBRID[] = { 11, 53, 125, 242, 242, 0, 0, 0, 33, 109, 222, 222, 222, 222, 0, 0 }; + +/*! + * \brief The function gets a value of a specific phy attribute. + * + * \param [IN] getPhy Pointer to the function parameters. + * + * \retval Returns a structure containing the PHY parameter. + */ +PhyParam_t RegionUS915HybridGetPhyParam( GetPhyParams_t* getPhy ); + +/*! + * \brief Updates the last TX done parameters of the current channel. + * + * \param [IN] txDone Pointer to the function parameters. + */ +void RegionUS915HybridSetBandTxDone( SetBandTxDoneParams_t* txDone ); + +/*! + * \brief Initializes the channels masks and the channels. + * + * \param [IN] type Sets the initialization type. + */ +void RegionUS915HybridInitDefaults( InitType_t type ); + +/*! + * \brief Verifies a parameter. + * + * \param [IN] verify Pointer to the function parameters. + * + * \param [IN] type Sets the initialization type. + * + * \retval Returns true, if the parameter is valid. + */ +bool RegionUS915HybridVerify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ); + +/*! + * \brief The function parses the input buffer and sets up the channels of the + * CF list. + * + * \param [IN] applyCFList Pointer to the function parameters. + */ +void RegionUS915HybridApplyCFList( ApplyCFListParams_t* applyCFList ); + +/*! + * \brief Sets a channels mask. + * + * \param [IN] chanMaskSet Pointer to the function parameters. + * + * \retval Returns true, if the channels mask could be set. + */ +bool RegionUS915HybridChanMaskSet( ChanMaskSetParams_t* chanMaskSet ); + +/*! + * \brief Calculates the next datarate to set, when ADR is on or off. + * + * \param [IN] adrNext Pointer to the function parameters. + * + * \param [OUT] drOut The calculated datarate for the next TX. + * + * \param [OUT] txPowOut The TX power for the next TX. + * + * \param [OUT] adrAckCounter The calculated ADR acknowledgement counter. + * + * \retval Returns true, if an ADR request should be performed. + */ +bool RegionUS915HybridAdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ); + +/*! + * Computes the Rx window timeout and offset. + * + * \param [IN] datarate Rx window datarate index to be used + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms + * interval around RxOffset + * + * \param [OUT]rxConfigParams Returns updated WindowTimeout and WindowOffset fields. + */ +void RegionUS915HybridComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ); + +/*! + * \brief Configuration of the RX windows. + * + * \param [IN] rxConfig Pointer to the function parameters. + * + * \param [OUT] datarate The datarate index which was set. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionUS915HybridRxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ); + +/*! + * \brief TX configuration. + * + * \param [IN] txConfig Pointer to the function parameters. + * + * \param [OUT] txPower The tx power index which was set. + * + * \param [OUT] txTimeOnAir The time-on-air of the frame. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionUS915HybridTxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ); + +/*! + * \brief The function processes a Link ADR Request. + * + * \param [IN] linkAdrReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionUS915HybridLinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ); + +/*! + * \brief The function processes a RX Parameter Setup Request. + * + * \param [IN] rxParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionUS915HybridRxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ); + +/*! + * \brief The function processes a Channel Request. + * + * \param [IN] newChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionUS915HybridNewChannelReq( NewChannelReqParams_t* newChannelReq ); + +/*! + * \brief The function processes a TX ParamSetup Request. + * + * \param [IN] txParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + * Returns -1, if the functionality is not implemented. In this case, the end node + * shall not process the command. + */ +int8_t RegionUS915HybridTxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ); + +/*! + * \brief The function processes a DlChannel Request. + * + * \param [IN] dlChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionUS915HybridDlChannelReq( DlChannelReqParams_t* dlChannelReq ); + +/*! + * \brief Alternates the datarate of the channel for the join request. + * + * \param [IN] alternateDr Pointer to the function parameters. + * + * \retval Datarate to apply. + */ +int8_t RegionUS915HybridAlternateDr( AlternateDrParams_t* alternateDr ); + +/*! + * \brief Calculates the back-off time. + * + * \param [IN] calcBackOff Pointer to the function parameters. + */ +void RegionUS915HybridCalcBackOff( CalcBackOffParams_t* calcBackOff ); + +/*! + * \brief Searches and set the next random available channel + * + * \param [OUT] channel Next channel to use for TX. + * + * \param [OUT] time Time to wait for the next transmission according to the duty + * cycle. + * + * \param [OUT] aggregatedTimeOff Updates the aggregated time off. + * + * \retval Function status [1: OK, 0: Unable to find a channel on the current datarate] + */ +bool RegionUS915HybridNextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ); + +/*! + * \brief Adds a channel. + * + * \param [IN] channelAdd Pointer to the function parameters. + * + * \retval Status of the operation. + */ +LoRaMacStatus_t RegionUS915HybridChannelAdd( ChannelAddParams_t* channelAdd ); + +/*! + * \brief Removes a channel. + * + * \param [IN] channelRemove Pointer to the function parameters. + * + * \retval Returns true, if the channel was removed successfully. + */ +bool RegionUS915HybridChannelsRemove( ChannelRemoveParams_t* channelRemove ); + +/*! + * \brief Sets the radio into continuous wave mode. + * + * \param [IN] continuousWave Pointer to the function parameters. + */ +void RegionUS915HybridSetContinuousWave( ContinuousWaveParams_t* continuousWave ); + +/*! + * \brief Computes new datarate according to the given offset + * + * \param [IN] downlinkDwellTime Downlink dwell time configuration. 0: No limit, 1: 400ms + * + * \param [IN] dr Current datarate + * + * \param [IN] drOffset Offset to be applied + * + * \retval newDr Computed datarate. + */ +uint8_t RegionUS915HybridApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ); + +/*! + * \brief Sets the radio into beacon reception mode + * + * \param [IN] rxBeaconSetup Pointer to the function parameters + */ + void RegionUS915HybridRxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ); + +/*! \} defgroup REGIONUS915HYB */ + +#endif // __REGION_US915_HYBRID_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915.c b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915.c new file mode 100644 index 00000000..1ba7f6ea --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915.c @@ -0,0 +1,925 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + ___ _____ _ ___ _ _____ ___ ___ ___ ___ +/ __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| +\__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| +|___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| +embedded.connectivity.solutions=============== + +Description: LoRa MAC region US915 implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) +*/ +#include +#include +#include +#include + +#include "radio.h" +//#include "timer.h" +#include "timeServer.h" +#include "LoRaMac.h" + +#include "utilities.h" + +#include "Region.h" +#include "RegionCommon.h" +#include "RegionUS915.h" +#include "debug.h" + +// Definitions +#define CHANNELS_MASK_SIZE 6 + +// Global attributes +/*! + * LoRaMAC channels + */ +static ChannelParams_t Channels[US915_MAX_NB_CHANNELS]; + +/*! + * LoRaMac bands + */ +static Band_t Bands[US915_MAX_NB_BANDS] = +{ + US915_BAND0 +}; + +/*! + * LoRaMac channels mask + */ +static uint16_t ChannelsMask[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels remaining + */ +static uint16_t ChannelsMaskRemaining[CHANNELS_MASK_SIZE]; + +/*! + * LoRaMac channels default mask + */ +static uint16_t ChannelsDefaultMask[CHANNELS_MASK_SIZE]; + +// Static functions +static int8_t GetNextLowerTxDr( int8_t dr, int8_t minDr ) +{ + uint8_t nextLowerDr = 0; + + if( dr == minDr ) + { + nextLowerDr = minDr; + } + else + { + nextLowerDr = dr - 1; + } + return nextLowerDr; +} + +static uint32_t GetBandwidth( uint32_t drIndex ) +{ + switch( BandwidthsUS915[drIndex] ) + { + default: + case 125000: + return 0; + case 250000: + return 1; + case 500000: + return 2; + } +} + +static int8_t LimitTxPower( int8_t txPower, int8_t maxBandTxPower, int8_t datarate, uint16_t* channelsMask ) +{ + int8_t txPowerResult = txPower; + + // Limit tx power to the band max + txPowerResult = MAX( txPower, maxBandTxPower ); + + if( datarate == DR_4 ) + {// Limit tx power to max 26dBm + txPowerResult = MAX( txPower, TX_POWER_2 ); + } + else + { + if( RegionCommonCountChannels( channelsMask, 0, 4 ) < 50 ) + {// Limit tx power to max 21dBm + txPowerResult = MAX( txPower, TX_POWER_5 ); + } + } + return txPowerResult; +} + +static uint8_t CountNbOfEnabledChannels( uint8_t datarate, uint16_t* channelsMask, ChannelParams_t* channels, Band_t* bands, uint8_t* enabledChannels, uint8_t* delayTx ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTransmission = 0; + + for( uint8_t i = 0, k = 0; i < US915_MAX_NB_CHANNELS; i += 16, k++ ) + { + for( uint8_t j = 0; j < 16; j++ ) + { + if( ( channelsMask[k] & ( 1 << j ) ) != 0 ) + { + if( channels[i + j].Frequency == 0 ) + { // Check if the channel is enabled + continue; + } + if( RegionCommonValueInRange( datarate, channels[i + j].DrRange.Fields.Min, + channels[i + j].DrRange.Fields.Max ) == false ) + { // Check if the current channel selection supports the given datarate + continue; + } + if( bands[channels[i + j].Band].TimeOff > 0 ) + { // Check if the band is available for transmission + delayTransmission++; + continue; + } + enabledChannels[nbEnabledChannels++] = i + j; + } + } + } + + *delayTx = delayTransmission; + return nbEnabledChannels; +} + +PhyParam_t RegionUS915GetPhyParam( GetPhyParams_t* getPhy ) +{ + PhyParam_t phyParam = { 0 }; + + switch( getPhy->Attribute ) + { + case PHY_MIN_RX_DR: + { + phyParam.Value = US915_RX_MIN_DATARATE; + break; + } + case PHY_MIN_TX_DR: + { + phyParam.Value = US915_TX_MIN_DATARATE; + break; + } + case PHY_DEF_TX_DR: + { + phyParam.Value = US915_DEFAULT_DATARATE; + break; + } + case PHY_NEXT_LOWER_TX_DR: + { + phyParam.Value = GetNextLowerTxDr( getPhy->Datarate, US915_TX_MIN_DATARATE ); + break; + } + case PHY_DEF_TX_POWER: + { + phyParam.Value = US915_DEFAULT_TX_POWER; + break; + } + case PHY_MAX_PAYLOAD: + { + phyParam.Value = MaxPayloadOfDatarateUS915[getPhy->Datarate]; + break; + } + case PHY_MAX_PAYLOAD_REPEATER: + { + phyParam.Value = MaxPayloadOfDatarateRepeaterUS915[getPhy->Datarate]; + break; + } + case PHY_DUTY_CYCLE: + { + phyParam.Value = US915_DUTY_CYCLE_ENABLED; + break; + } + case PHY_MAX_RX_WINDOW: + { + phyParam.Value = US915_MAX_RX_WINDOW; + break; + } + case PHY_RECEIVE_DELAY1: + { + phyParam.Value = US915_RECEIVE_DELAY1; + break; + } + case PHY_RECEIVE_DELAY2: + { + phyParam.Value = US915_RECEIVE_DELAY2; + break; + } + case PHY_JOIN_ACCEPT_DELAY1: + { + phyParam.Value = US915_JOIN_ACCEPT_DELAY1; + break; + } + case PHY_JOIN_ACCEPT_DELAY2: + { + phyParam.Value = US915_JOIN_ACCEPT_DELAY2; + break; + } + case PHY_MAX_FCNT_GAP: + { + phyParam.Value = US915_MAX_FCNT_GAP; + break; + } + case PHY_ACK_TIMEOUT: + { + phyParam.Value = ( US915_ACKTIMEOUT + randr( -US915_ACK_TIMEOUT_RND, US915_ACK_TIMEOUT_RND ) ); + break; + } + case PHY_DEF_DR1_OFFSET: + { + phyParam.Value = US915_DEFAULT_RX1_DR_OFFSET; + break; + } + case PHY_DEF_RX2_FREQUENCY: + { + phyParam.Value = US915_RX_WND_2_FREQ; + break; + } + case PHY_DEF_RX2_DR: + { + phyParam.Value = US915_RX_WND_2_DR; + break; + } + case PHY_CHANNELS_MASK: + { + phyParam.ChannelsMask = ChannelsMask; + break; + } + case PHY_CHANNELS_DEFAULT_MASK: + { + phyParam.ChannelsMask = ChannelsDefaultMask; + break; + } + case PHY_MAX_NB_CHANNELS: + { + phyParam.Value = US915_MAX_NB_CHANNELS; + break; + } + case PHY_CHANNELS: + { + phyParam.Channels = Channels; + break; + } + case PHY_DEF_UPLINK_DWELL_TIME: + case PHY_DEF_DOWNLINK_DWELL_TIME: + { + phyParam.Value = 0; + break; + } + case PHY_DEF_MAX_EIRP: + case PHY_DEF_ANTENNA_GAIN: + { + phyParam.fValue = 0; + break; + } + case PHY_NB_JOIN_TRIALS: + case PHY_DEF_NB_JOIN_TRIALS: + { + phyParam.Value = 2; + break; + } + + case PHY_BEACON_CHANNEL_FREQ: + { + phyParam.Value = US915_BEACON_CHANNEL_FREQ; + break; + } + case PHY_BEACON_FORMAT: + { + phyParam.BeaconFormat.BeaconSize = US915_BEACON_SIZE; + phyParam.BeaconFormat.Rfu1Size = US915_RFU1_SIZE; + phyParam.BeaconFormat.Rfu2Size = US915_RFU2_SIZE; + break; + } + case PHY_BEACON_CHANNEL_DR: + { + phyParam.Value = US915_BEACON_CHANNEL_DR; + break; + } + case PHY_BEACON_CHANNEL_STEPWIDTH: + { + phyParam.Value = US915_BEACON_CHANNEL_STEPWIDTH; + break; + } + case PHY_BEACON_NB_CHANNELS: + { + phyParam.Value = US915_BEACON_NB_CHANNELS; + break; + } + default: + { + break; + } + } + + return phyParam; +} + +void RegionUS915SetBandTxDone( SetBandTxDoneParams_t* txDone ) +{ + RegionCommonSetBandTxDone( txDone->Joined, &Bands[Channels[txDone->Channel].Band], txDone->LastTxDoneTime ); +} + +void RegionUS915InitDefaults( InitType_t type ) +{ + switch( type ) + { + case INIT_TYPE_INIT: + { + // Channels + // 125 kHz channels + for( uint8_t i = 0; i < US915_MAX_NB_CHANNELS - 8; i++ ) + { + Channels[i].Frequency = 902300000 + i * 200000; + Channels[i].DrRange.Value = ( DR_3 << 4 ) | DR_0; + Channels[i].Band = 0; + } + // 500 kHz channels + for( uint8_t i = US915_MAX_NB_CHANNELS - 8; i < US915_MAX_NB_CHANNELS; i++ ) + { + Channels[i].Frequency = 903000000 + ( i - ( US915_MAX_NB_CHANNELS - 8 ) ) * 1600000; + Channels[i].DrRange.Value = ( DR_4 << 4 ) | DR_4; + Channels[i].Band = 0; + } + + // ChannelsMask + ChannelsDefaultMask[0] = 0xFFFF; + ChannelsDefaultMask[1] = 0xFFFF; + ChannelsDefaultMask[2] = 0xFFFF; + ChannelsDefaultMask[3] = 0xFFFF; + ChannelsDefaultMask[4] = 0x00FF; + ChannelsDefaultMask[5] = 0x0000; + + // Copy channels default mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 6 ); + + // Copy into channels mask remaining + RegionCommonChanMaskCopy( ChannelsMaskRemaining, ChannelsMask, 6 ); + break; + } + case INIT_TYPE_RESTORE: + { + // Copy channels default mask + RegionCommonChanMaskCopy( ChannelsMask, ChannelsDefaultMask, 6 ); + + for( uint8_t i = 0; i < 6; i++ ) + { // Copy-And the channels mask + ChannelsMaskRemaining[i] &= ChannelsMask[i]; + } + break; + } + default: + { + break; + } + } +} + +bool RegionUS915Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ) +{ + switch( phyAttribute ) + { + case PHY_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, US915_TX_MIN_DATARATE, US915_TX_MAX_DATARATE ); + } + case PHY_DEF_TX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, DR_0, DR_5 ); + } + case PHY_RX_DR: + { + return RegionCommonValueInRange( verify->DatarateParams.Datarate, US915_RX_MIN_DATARATE, US915_RX_MAX_DATARATE ); + } + case PHY_DEF_TX_POWER: + case PHY_TX_POWER: + { + // Remark: switched min and max! + return RegionCommonValueInRange( verify->TxPower, US915_MAX_TX_POWER, US915_MIN_TX_POWER ); + } + case PHY_DUTY_CYCLE: + { + return US915_DUTY_CYCLE_ENABLED; + } + case PHY_NB_JOIN_TRIALS: + { + if( verify->NbJoinTrials < 2 ) + { + return false; + } + break; + } + default: + return false; + } + return true; +} + +void RegionUS915ApplyCFList( ApplyCFListParams_t* applyCFList ) +{ + return; +} + +bool RegionUS915ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ) +{ + uint8_t nbChannels = RegionCommonCountChannels( chanMaskSet->ChannelsMaskIn, 0, 4 ); + + // Check the number of active channels + if( ( nbChannels < 2 ) && + ( nbChannels > 0 ) ) + { + return false; + } + + switch( chanMaskSet->ChannelsMaskType ) + { + case CHANNELS_MASK: + { + RegionCommonChanMaskCopy( ChannelsMask, chanMaskSet->ChannelsMaskIn, 6 ); + + for( uint8_t i = 0; i < 6; i++ ) + { // Copy-And the channels mask + ChannelsMaskRemaining[i] &= ChannelsMask[i]; + } + break; + } + case CHANNELS_DEFAULT_MASK: + { + RegionCommonChanMaskCopy( ChannelsDefaultMask, chanMaskSet->ChannelsMaskIn, 6 ); + break; + } + default: + return false; + } + return true; +} + +bool RegionUS915AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ) +{ + bool adrAckReq = false; + int8_t datarate = adrNext->Datarate; + int8_t txPower = adrNext->TxPower; + GetPhyParams_t getPhy; + PhyParam_t phyParam; + + // Report back the adr ack counter + *adrAckCounter = adrNext->AdrAckCounter; + + if( adrNext->AdrEnabled == true ) + { + if( datarate == US915_TX_MIN_DATARATE ) + { + *adrAckCounter = 0; + adrAckReq = false; + } + else + { + if( adrNext->AdrAckCounter >= US915_ADR_ACK_LIMIT ) + { + adrAckReq = true; + txPower = US915_MAX_TX_POWER; + } + else + { + adrAckReq = false; + } + if( adrNext->AdrAckCounter >= ( US915_ADR_ACK_LIMIT + US915_ADR_ACK_DELAY ) ) + { + if( ( adrNext->AdrAckCounter % US915_ADR_ACK_DELAY ) == 1 ) + { + // Decrease the datarate + getPhy.Attribute = PHY_NEXT_LOWER_TX_DR; + getPhy.Datarate = datarate; + getPhy.UplinkDwellTime = adrNext->UplinkDwellTime; + phyParam = RegionUS915GetPhyParam( &getPhy ); + datarate = phyParam.Value; + + if( datarate == US915_TX_MIN_DATARATE ) + { + // We must set adrAckReq to false as soon as we reach the lowest datarate + adrAckReq = false; + if( adrNext->UpdateChanMask == true ) + { + // Re-enable default channels + ChannelsMask[0] = 0xFFFF; + ChannelsMask[1] = 0xFFFF; + ChannelsMask[2] = 0xFFFF; + ChannelsMask[3] = 0xFFFF; + ChannelsMask[4] = 0x00FF; + ChannelsMask[5] = 0x0000; + } + } + } + } + } + } + + *drOut = datarate; + *txPowOut = txPower; + return adrAckReq; +} + +void RegionUS915ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ) +{ + double tSymbol = 0.0; + uint32_t radioWakeUpTime; + + rxConfigParams->Datarate = datarate; + rxConfigParams->Bandwidth = GetBandwidth( datarate ); + + if( datarate == DR_7 ) + { // FSK + tSymbol = RegionCommonComputeSymbolTimeFsk( DataratesUS915[datarate] ); + } + else + { // LoRa + tSymbol = RegionCommonComputeSymbolTimeLoRa( DataratesUS915[datarate], BandwidthsUS915[datarate] ); + } + + radioWakeUpTime = Radio.GetWakeupTime( ); + RegionCommonComputeRxWindowParameters( tSymbol, minRxSymbols, rxError, radioWakeUpTime, &rxConfigParams->WindowTimeout, &rxConfigParams->WindowOffset ); +} + +bool RegionUS915RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ) +{ + int8_t dr = rxConfig->Datarate; + uint8_t maxPayload = 0; + int8_t phyDr = 0; + uint32_t frequency = rxConfig->Frequency; + + if( Radio.GetStatus( ) != RF_IDLE ) + { + return false; + } + + if( rxConfig->RxSlot == RX_SLOT_WIN_1 ) + { + // Apply window 1 frequency + frequency = US915_FIRST_RX1_CHANNEL + ( rxConfig->Channel % 8 ) * US915_STEPWIDTH_RX1_CHANNEL; + } + + // Read the physical datarate from the datarates table + phyDr = DataratesUS915[dr]; + + Radio.SetChannel( frequency ); + + // Radio configuration + Radio.SetRxConfig( MODEM_LORA, rxConfig->Bandwidth, phyDr, 1, 0, 8, rxConfig->WindowTimeout, false, 0, false, 0, 0, true, rxConfig->RxContinuous ); + + if( rxConfig->RepeaterSupport == true ) + { + maxPayload = MaxPayloadOfDatarateRepeaterUS915[dr]; + } + else + { + maxPayload = MaxPayloadOfDatarateUS915[dr]; + } + Radio.SetMaxPayloadLength( MODEM_LORA, maxPayload + LORA_MAC_FRMPAYLOAD_OVERHEAD ); + DBG_PRINTF("RX on freq %u Hz at DR %d\n\r", (unsigned int)frequency, dr); + + *datarate = (uint8_t) dr; + return true; +} + +bool RegionUS915TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ) +{ + int8_t phyDr = DataratesUS915[txConfig->Datarate]; + int8_t txPowerLimited = LimitTxPower( txConfig->TxPower, Bands[Channels[txConfig->Channel].Band].TxMaxPower, txConfig->Datarate, ChannelsMask ); + uint32_t bandwidth = GetBandwidth( txConfig->Datarate ); + int8_t phyTxPower = 0; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, US915_DEFAULT_MAX_ERP, 0 ); + + Radio.SetChannel( Channels[txConfig->Channel].Frequency ); + + Radio.SetMaxPayloadLength( MODEM_LORA, txConfig->PktLen ); + Radio.SetTxConfig( MODEM_LORA, phyTxPower, 0, bandwidth, phyDr, 1, 8, false, true, 0, 0, false, 3e3 ); + DBG_PRINTF("TX on freq %u Hz at DR %d\n\r", (unsigned int)Channels[txConfig->Channel].Frequency, txConfig->Datarate); + + *txTimeOnAir = Radio.TimeOnAir( MODEM_LORA, txConfig->PktLen ); + *txPower = txPowerLimited; + + return true; +} + +uint8_t RegionUS915LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ) +{ + uint8_t status = 0x07; + LinkAdrParams_t linkAdrParams; + uint8_t nextIndex = 0; + uint8_t bytesProcessed = 0; + uint16_t channelsMask[6] = { 0, 0, 0, 0, 0, 0 }; + + // Initialize local copy of channels mask + RegionCommonChanMaskCopy( channelsMask, ChannelsMask, 6 ); + + while( bytesProcessed < linkAdrReq->PayloadSize ) + { + nextIndex = RegionCommonParseLinkAdrReq( &( linkAdrReq->Payload[bytesProcessed] ), &linkAdrParams ); + + if( nextIndex == 0 ) + break; // break loop, since no more request has been found + + // Update bytes processed + bytesProcessed += nextIndex; + + // Revert status, as we only check the last ADR request for the channel mask KO + status = 0x07; + + if( linkAdrParams.ChMaskCtrl == 6 ) + { + // Enable all 125 kHz channels + channelsMask[0] = 0xFFFF; + channelsMask[1] = 0xFFFF; + channelsMask[2] = 0xFFFF; + channelsMask[3] = 0xFFFF; + // Apply chMask to channels 64 to 71 + channelsMask[4] = linkAdrParams.ChMask; + } + else if( linkAdrParams.ChMaskCtrl == 7 ) + { + // Disable all 125 kHz channels + channelsMask[0] = 0x0000; + channelsMask[1] = 0x0000; + channelsMask[2] = 0x0000; + channelsMask[3] = 0x0000; + // Apply chMask to channels 64 to 71 + channelsMask[4] = linkAdrParams.ChMask; + } + else if( linkAdrParams.ChMaskCtrl == 5 ) + { + // RFU + status &= 0xFE; // Channel mask KO + } + else + { + channelsMask[linkAdrParams.ChMaskCtrl] = linkAdrParams.ChMask; + } + } + + // FCC 15.247 paragraph F mandates to hop on at least 2 125 kHz channels + if( ( linkAdrParams.Datarate < DR_4 ) && ( RegionCommonCountChannels( channelsMask, 0, 4 ) < 2 ) ) + { + status &= 0xFE; // Channel mask KO + } + + // Verify datarate + if( RegionCommonChanVerifyDr( US915_MAX_NB_CHANNELS, channelsMask, linkAdrParams.Datarate, US915_TX_MIN_DATARATE, US915_TX_MAX_DATARATE, Channels ) == false ) + { + status &= 0xFD; // Datarate KO + } + + // Verify tx power + if( RegionCommonValueInRange( linkAdrParams.TxPower, US915_MAX_TX_POWER, US915_MIN_TX_POWER ) == 0 ) + { + // Verify if the maximum TX power is exceeded + if( US915_MAX_TX_POWER > linkAdrParams.TxPower ) + { // Apply maximum TX power. Accept TX power. + linkAdrParams.TxPower = US915_MAX_TX_POWER; + } + else + { + status &= 0xFB; // TxPower KO + } + } + + // Update channelsMask if everything is correct + if( status == 0x07 ) + { + if( linkAdrParams.NbRep == 0 ) + { // Value of 0 is not allowed, revert to default. + linkAdrParams.NbRep = 1; + } + + // Copy Mask + RegionCommonChanMaskCopy( ChannelsMask, channelsMask, 6 ); + + ChannelsMaskRemaining[0] &= ChannelsMask[0]; + ChannelsMaskRemaining[1] &= ChannelsMask[1]; + ChannelsMaskRemaining[2] &= ChannelsMask[2]; + ChannelsMaskRemaining[3] &= ChannelsMask[3]; + ChannelsMaskRemaining[4] = ChannelsMask[4]; + ChannelsMaskRemaining[5] = ChannelsMask[5]; + } + + // Update status variables + *drOut = linkAdrParams.Datarate; + *txPowOut = linkAdrParams.TxPower; + *nbRepOut = linkAdrParams.NbRep; + *nbBytesParsed = bytesProcessed; + + return status; +} + +uint8_t RegionUS915RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ) +{ + uint8_t status = 0x07; + uint32_t freq = rxParamSetupReq->Frequency; + + // Verify radio frequency + if( ( Radio.CheckRfFrequency( freq ) == false ) || + ( freq < US915_FIRST_RX1_CHANNEL ) || + ( freq > US915_LAST_RX1_CHANNEL ) || + ( ( ( freq - ( uint32_t ) US915_FIRST_RX1_CHANNEL ) % ( uint32_t ) US915_STEPWIDTH_RX1_CHANNEL ) != 0 ) ) + { + status &= 0xFE; // Channel frequency KO + } + + // Verify datarate + if( RegionCommonValueInRange( rxParamSetupReq->Datarate, US915_RX_MIN_DATARATE, US915_RX_MAX_DATARATE ) == false ) + { + status &= 0xFD; // Datarate KO + } + if( ( RegionCommonValueInRange( rxParamSetupReq->Datarate, DR_5, DR_7 ) == true ) || + ( rxParamSetupReq->Datarate > DR_13 ) ) + { + status &= 0xFD; // Datarate KO + } + + // Verify datarate offset + if( RegionCommonValueInRange( rxParamSetupReq->DrOffset, US915_MIN_RX1_DR_OFFSET, US915_MAX_RX1_DR_OFFSET ) == false ) + { + status &= 0xFB; // Rx1DrOffset range KO + } + + return status; +} + +uint8_t RegionUS915NewChannelReq( NewChannelReqParams_t* newChannelReq ) +{ + // Datarate and frequency KO + return 0; +} + +int8_t RegionUS915TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ) +{ + return -1; +} + +uint8_t RegionUS915DlChannelReq( DlChannelReqParams_t* dlChannelReq ) +{ + return 0; +} + +int8_t RegionUS915AlternateDr( AlternateDrParams_t* alternateDr ) +{ + int8_t datarate = 0; + + // Re-enable 500 kHz default channels + ChannelsMask[4] = 0x00FF; + + if( ( alternateDr->NbTrials & 0x01 ) == 0x01 ) + { + datarate = DR_4; + } + else + { + datarate = DR_0; + } + return datarate; +} + +void RegionUS915CalcBackOff( CalcBackOffParams_t* calcBackOff ) +{ + uint8_t channel = calcBackOff->Channel; + uint16_t joinDutyCycle = 0; + + if( calcBackOff->Joined == false ) + { + // Get the join duty cycle + joinDutyCycle = RegionCommonGetJoinDc( calcBackOff->ElapsedTime ); + // Apply band time-off. + Bands[Channels[channel].Band].TimeOff = calcBackOff->TxTimeOnAir * joinDutyCycle - calcBackOff->TxTimeOnAir; + } + else + { + Bands[Channels[channel].Band].TimeOff = 0; + } +} + +bool RegionUS915NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ) +{ + uint8_t nbEnabledChannels = 0; + uint8_t delayTx = 0; + uint8_t enabledChannels[US915_MAX_NB_CHANNELS] = { 0 }; + TimerTime_t nextTxDelay = 0; + + // Count 125kHz channels + if( RegionCommonCountChannels( ChannelsMaskRemaining, 0, 4 ) == 0 ) + { // Reactivate default channels + RegionCommonChanMaskCopy( ChannelsMaskRemaining, ChannelsMask, 4 ); + } + // Check other channels + if( nextChanParams->Datarate >= DR_4 ) + { + if( ( ChannelsMaskRemaining[4] & 0x00FF ) == 0 ) + { + ChannelsMaskRemaining[4] = ChannelsMask[4]; + } + } + + if( nextChanParams->AggrTimeOff <= TimerGetElapsedTime( nextChanParams->LastAggrTx ) ) + { + // Reset Aggregated time off + *aggregatedTimeOff = 0; + + // Update bands Time OFF + nextTxDelay = RegionCommonUpdateBandTimeOff( nextChanParams->Joined, nextChanParams->DutyCycleEnabled, Bands, US915_MAX_NB_BANDS ); + + // Search how many channels are enabled + nbEnabledChannels = CountNbOfEnabledChannels( nextChanParams->Datarate, + ChannelsMaskRemaining, Channels, + Bands, enabledChannels, &delayTx ); + } + else + { + delayTx++; + nextTxDelay = nextChanParams->AggrTimeOff - TimerGetElapsedTime( nextChanParams->LastAggrTx ); + } + + if( nbEnabledChannels > 0 ) + { + // We found a valid channel + *channel = enabledChannels[randr( 0, nbEnabledChannels - 1 )]; + // Disable the channel in the mask + RegionCommonChanDisable( ChannelsMaskRemaining, *channel, US915_MAX_NB_CHANNELS - 8 ); + + *time = 0; + return true; + } + else + { + if( delayTx > 0 ) + { + // Delay transmission due to AggregatedTimeOff or to a band time off + *time = nextTxDelay; + return true; + } + // Datarate not supported by any channel + *time = 0; + return false; + } +} + +LoRaMacStatus_t RegionUS915ChannelAdd( ChannelAddParams_t* channelAdd ) +{ + return LORAMAC_STATUS_PARAMETER_INVALID; +} + +bool RegionUS915ChannelsRemove( ChannelRemoveParams_t* channelRemove ) +{ + return LORAMAC_STATUS_PARAMETER_INVALID; +} + +void RegionUS915SetContinuousWave( ContinuousWaveParams_t* continuousWave ) +{ + int8_t txPowerLimited = LimitTxPower( continuousWave->TxPower, Bands[Channels[continuousWave->Channel].Band].TxMaxPower, continuousWave->Datarate, ChannelsMask ); + int8_t phyTxPower = 0; + uint32_t frequency = Channels[continuousWave->Channel].Frequency; + + // Calculate physical TX power + phyTxPower = RegionCommonComputeTxPower( txPowerLimited, US915_DEFAULT_MAX_ERP, 0 ); + + Radio.SetTxContinuousWave( frequency, phyTxPower, continuousWave->Timeout ); +} + +uint8_t RegionUS915ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ) +{ + int8_t datarate = DatarateOffsetsUS915[dr][drOffset]; + + if( datarate < 0 ) + { + datarate = DR_0; + } + return datarate; +} + +void RegionUS915RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ) +{ + RegionCommonRxBeaconSetupParams_t regionCommonRxBeaconSetup; + + regionCommonRxBeaconSetup.Datarates = DataratesUS915; + regionCommonRxBeaconSetup.Frequency = rxBeaconSetup->Frequency; + regionCommonRxBeaconSetup.BeaconSize = US915_BEACON_SIZE; + regionCommonRxBeaconSetup.BeaconDatarate = US915_BEACON_CHANNEL_DR; + regionCommonRxBeaconSetup.BeaconChannelBW = US915_BEACON_CHANNEL_BW; + regionCommonRxBeaconSetup.RxTime = rxBeaconSetup->RxTime; + regionCommonRxBeaconSetup.SymbolTimeout = rxBeaconSetup->SymbolTimeout; + + RegionCommonRxBeaconSetup( ®ionCommonRxBeaconSetup ); + + // Store downlink datarate + *outDr = US915_BEACON_CHANNEL_DR; +} diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915.h b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915.h new file mode 100644 index 00000000..c22d30d5 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/mac/region/RegionUS915.h @@ -0,0 +1,504 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/*! + * \file RegionUS915.h + * + * \brief Region definition for US915 + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013 Semtech + * + * ___ _____ _ ___ _ _____ ___ ___ ___ ___ + * / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| + * \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| + * |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| + * embedded.connectivity.solutions=============== + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + * + * \author Daniel Jaeckle ( STACKFORCE ) + * + * \defgroup REGIONUS915 Region US915 + * Implementation according to LoRaWAN Specification v1.0.2. + * \{ + */ +#ifndef __REGION_US915_H__ +#define __REGION_US915_H__ + +#include "LoRaMac.h" + +/*! + * LoRaMac maximum number of channels + */ +#define US915_MAX_NB_CHANNELS 72 + +/*! + * Minimal datarate that can be used by the node + */ +#define US915_TX_MIN_DATARATE DR_0 + +/*! + * Maximal datarate that can be used by the node + */ +#define US915_TX_MAX_DATARATE DR_4 + +/*! + * Minimal datarate that can be used by the node + */ +#define US915_RX_MIN_DATARATE DR_8 + +/*! + * Maximal datarate that can be used by the node + */ +#define US915_RX_MAX_DATARATE DR_13 + +/*! + * Default datarate used by the node + */ +#define US915_DEFAULT_DATARATE DR_0 + +/*! + * Minimal Rx1 receive datarate offset + */ +#define US915_MIN_RX1_DR_OFFSET 0 + +/*! + * Maximal Rx1 receive datarate offset + */ +#define US915_MAX_RX1_DR_OFFSET 3 + +/*! + * Default Rx1 receive datarate offset + */ +#define US915_DEFAULT_RX1_DR_OFFSET 0 + +/*! + * Minimal Tx output power that can be used by the node + */ +#define US915_MIN_TX_POWER TX_POWER_10 + +/*! + * Maximal Tx output power that can be used by the node + */ +#define US915_MAX_TX_POWER TX_POWER_0 + +/*! + * Default Tx output power used by the node + */ +#define US915_DEFAULT_TX_POWER TX_POWER_0 + +/*! + * Default Max ERP + */ +#define US915_DEFAULT_MAX_ERP 30.0f + +/*! + * ADR Ack limit + */ +#define US915_ADR_ACK_LIMIT 64 + +/*! + * ADR Ack delay + */ +#define US915_ADR_ACK_DELAY 32 + +/*! + * Enabled or disabled the duty cycle + */ +#define US915_DUTY_CYCLE_ENABLED 0 + +/*! + * Maximum RX window duration + */ +#define US915_MAX_RX_WINDOW 3000 + +/*! + * Receive delay 1 + */ +#define US915_RECEIVE_DELAY1 1000 + +/*! + * Receive delay 2 + */ +#define US915_RECEIVE_DELAY2 2000 + +/*! + * Join accept delay 1 + */ +#define US915_JOIN_ACCEPT_DELAY1 5000 + +/*! + * Join accept delay 2 + */ +#define US915_JOIN_ACCEPT_DELAY2 6000 + +/*! + * Maximum frame counter gap + */ +#define US915_MAX_FCNT_GAP 16384 + +/*! + * Ack timeout + */ +#define US915_ACKTIMEOUT 2000 + +/*! + * Random ack timeout limits + */ +#define US915_ACK_TIMEOUT_RND 1000 + +/*! + * Second reception window channel frequency definition. + */ +#define US915_RX_WND_2_FREQ 923300000 + +/*! + * Second reception window channel datarate definition. + */ +#define US915_RX_WND_2_DR DR_8 + +/* + * CLASS B + */ +/*! + * Beacon frequency + */ +#define US915_BEACON_CHANNEL_FREQ 923300000 + +/*! + * Beacon frequency channel stepwidth + */ +#define US915_BEACON_CHANNEL_STEPWIDTH 600000 + +/*! + * Number of possible beacon channels + */ +#define US915_BEACON_NB_CHANNELS 8 + +/*! + * Payload size of a beacon frame + */ +#define US915_BEACON_SIZE 23 + +/*! + * Size of RFU 1 field + */ +#define US915_RFU1_SIZE 5 + +/*! + * Size of RFU 2 field + */ +#define US915_RFU2_SIZE 3 + +/*! + * Datarate of the beacon channel + */ +#define US915_BEACON_CHANNEL_DR DR_8 + +/*! + * Bandwith of the beacon channel + */ +#define US915_BEACON_CHANNEL_BW 2 + +/*! + * LoRaMac maximum number of bands + */ +#define US915_MAX_NB_BANDS 1 + +/*! + * Band 0 definition + * { DutyCycle, TxMaxPower, LastTxDoneTime, TimeOff } + */ +#define US915_BAND0 { 1, US915_MAX_TX_POWER, 0, 0 } // 100.0 % + +/*! + * Defines the first channel for RX window 1 for US band + */ +#define US915_FIRST_RX1_CHANNEL ( (uint32_t) 923300000 ) + +/*! + * Defines the last channel for RX window 1 for US band + */ +#define US915_LAST_RX1_CHANNEL ( (uint32_t) 927500000 ) + +/*! + * Defines the step width of the channels for RX window 1 + */ +#define US915_STEPWIDTH_RX1_CHANNEL ( (uint32_t) 600000 ) + +/*! + * Data rates table definition + */ +static const uint8_t DataratesUS915[] = { 10, 9, 8, 7, 8, 0, 0, 0, 12, 11, 10, 9, 8, 7, 0, 0 }; + +/*! + * Bandwidths table definition in Hz + */ +static const uint32_t BandwidthsUS915[] = { 125000, 125000, 125000, 125000, 500000, 0, 0, 0, 500000, 500000, 500000, 500000, 500000, 500000, 0, 0 }; + +/*! + * Up/Down link data rates offset definition + */ +static const int8_t DatarateOffsetsUS915[5][4] = +{ + { DR_10, DR_9 , DR_8 , DR_8 }, // DR_0 + { DR_11, DR_10, DR_9 , DR_8 }, // DR_1 + { DR_12, DR_11, DR_10, DR_9 }, // DR_2 + { DR_13, DR_12, DR_11, DR_10 }, // DR_3 + { DR_13, DR_13, DR_12, DR_11 }, // DR_4 +}; + +/*! + * Maximum payload with respect to the datarate index. Cannot operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateUS915[] = { 11, 53, 125, 242, 242, 0, 0, 0, 53, 129, 242, 242, 242, 242, 0, 0 }; + +/*! + * Maximum payload with respect to the datarate index. Can operate with repeater. + */ +static const uint8_t MaxPayloadOfDatarateRepeaterUS915[] = { 11, 53, 125, 242, 242, 0, 0, 0, 33, 109, 222, 222, 222, 222, 0, 0 }; + +/*! + * \brief The function gets a value of a specific phy attribute. + * + * \param [IN] getPhy Pointer to the function parameters. + * + * \retval Returns a structure containing the PHY parameter. + */ +PhyParam_t RegionUS915GetPhyParam( GetPhyParams_t* getPhy ); + +/*! + * \brief Updates the last TX done parameters of the current channel. + * + * \param [IN] txDone Pointer to the function parameters. + */ +void RegionUS915SetBandTxDone( SetBandTxDoneParams_t* txDone ); + +/*! + * \brief Initializes the channels masks and the channels. + * + * \param [IN] type Sets the initialization type. + */ +void RegionUS915InitDefaults( InitType_t type ); + +/*! + * \brief Verifies a parameter. + * + * \param [IN] verify Pointer to the function parameters. + * + * \param [IN] type Sets the initialization type. + * + * \retval Returns true, if the parameter is valid. + */ +bool RegionUS915Verify( VerifyParams_t* verify, PhyAttribute_t phyAttribute ); + +/*! + * \brief The function parses the input buffer and sets up the channels of the + * CF list. + * + * \param [IN] applyCFList Pointer to the function parameters. + */ +void RegionUS915ApplyCFList( ApplyCFListParams_t* applyCFList ); + +/*! + * \brief Sets a channels mask. + * + * \param [IN] chanMaskSet Pointer to the function parameters. + * + * \retval Returns true, if the channels mask could be set. + */ +bool RegionUS915ChanMaskSet( ChanMaskSetParams_t* chanMaskSet ); + +/*! + * \brief Calculates the next datarate to set, when ADR is on or off. + * + * \param [IN] adrNext Pointer to the function parameters. + * + * \param [OUT] drOut The calculated datarate for the next TX. + * + * \param [OUT] txPowOut The TX power for the next TX. + * + * \param [OUT] adrAckCounter The calculated ADR acknowledgement counter. + * + * \retval Returns true, if an ADR request should be performed. + */ +bool RegionUS915AdrNext( AdrNextParams_t* adrNext, int8_t* drOut, int8_t* txPowOut, uint32_t* adrAckCounter ); + +/*! + * Computes the Rx window timeout and offset. + * + * \param [IN] datarate Rx window datarate index to be used + * + * \param [IN] minRxSymbols Minimum required number of symbols to detect an Rx frame. + * + * \param [IN] rxError System maximum timing error of the receiver. In milliseconds + * The receiver will turn on in a [-rxError : +rxError] ms + * interval around RxOffset + * + * \param [OUT]rxConfigParams Returns updated WindowTimeout and WindowOffset fields. + */ +void RegionUS915ComputeRxWindowParameters( int8_t datarate, uint8_t minRxSymbols, uint32_t rxError, RxConfigParams_t *rxConfigParams ); + +/*! + * \brief Configuration of the RX windows. + * + * \param [IN] rxConfig Pointer to the function parameters. + * + * \param [OUT] datarate The datarate index which was set. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionUS915RxConfig( RxConfigParams_t* rxConfig, int8_t* datarate ); + +/*! + * \brief TX configuration. + * + * \param [IN] txConfig Pointer to the function parameters. + * + * \param [OUT] txPower The tx power index which was set. + * + * \param [OUT] txTimeOnAir The time-on-air of the frame. + * + * \retval Returns true, if the configuration was applied successfully. + */ +bool RegionUS915TxConfig( TxConfigParams_t* txConfig, int8_t* txPower, TimerTime_t* txTimeOnAir ); + +/*! + * \brief The function processes a Link ADR Request. + * + * \param [IN] linkAdrReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionUS915LinkAdrReq( LinkAdrReqParams_t* linkAdrReq, int8_t* drOut, int8_t* txPowOut, uint8_t* nbRepOut, uint8_t* nbBytesParsed ); + +/*! + * \brief The function processes a RX Parameter Setup Request. + * + * \param [IN] rxParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionUS915RxParamSetupReq( RxParamSetupReqParams_t* rxParamSetupReq ); + +/*! + * \brief The function processes a Channel Request. + * + * \param [IN] newChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionUS915NewChannelReq( NewChannelReqParams_t* newChannelReq ); + +/*! + * \brief The function processes a TX ParamSetup Request. + * + * \param [IN] txParamSetupReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + * Returns -1, if the functionality is not implemented. In this case, the end node + * shall not process the command. + */ +int8_t RegionUS915TxParamSetupReq( TxParamSetupReqParams_t* txParamSetupReq ); + +/*! + * \brief The function processes a DlChannel Request. + * + * \param [IN] dlChannelReq Pointer to the function parameters. + * + * \retval Returns the status of the operation, according to the LoRaMAC specification. + */ +uint8_t RegionUS915DlChannelReq( DlChannelReqParams_t* dlChannelReq ); + +/*! + * \brief Alternates the datarate of the channel for the join request. + * + * \param [IN] alternateDr Pointer to the function parameters. + * + * \retval Datarate to apply. + */ +int8_t RegionUS915AlternateDr( AlternateDrParams_t* alternateDr ); + +/*! + * \brief Calculates the back-off time. + * + * \param [IN] calcBackOff Pointer to the function parameters. + */ +void RegionUS915CalcBackOff( CalcBackOffParams_t* calcBackOff ); + +/*! + * \brief Searches and set the next random available channel + * + * \param [OUT] channel Next channel to use for TX. + * + * \param [OUT] time Time to wait for the next transmission according to the duty + * cycle. + * + * \param [OUT] aggregatedTimeOff Updates the aggregated time off. + * + * \retval Function status [1: OK, 0: Unable to find a channel on the current datarate] + */ +bool RegionUS915NextChannel( NextChanParams_t* nextChanParams, uint8_t* channel, TimerTime_t* time, TimerTime_t* aggregatedTimeOff ); + +/*! + * \brief Adds a channel. + * + * \param [IN] channelAdd Pointer to the function parameters. + * + * \retval Status of the operation. + */ +LoRaMacStatus_t RegionUS915ChannelAdd( ChannelAddParams_t* channelAdd ); + +/*! + * \brief Removes a channel. + * + * \param [IN] channelRemove Pointer to the function parameters. + * + * \retval Returns true, if the channel was removed successfully. + */ +bool RegionUS915ChannelsRemove( ChannelRemoveParams_t* channelRemove ); + +/*! + * \brief Sets the radio into continuous wave mode. + * + * \param [IN] continuousWave Pointer to the function parameters. + */ +void RegionUS915SetContinuousWave( ContinuousWaveParams_t* continuousWave ); + +/*! + * \brief Computes new datarate according to the given offset + * + * \param [IN] downlinkDwellTime Downlink dwell time configuration. 0: No limit, 1: 400ms + * + * \param [IN] dr Current datarate + * + * \param [IN] drOffset Offset to be applied + * + * \retval newDr Computed datarate. + */ +uint8_t RegionUS915ApplyDrOffset( uint8_t downlinkDwellTime, int8_t dr, int8_t drOffset ); + +/*! + * \brief Sets the radio into beacon reception mode + * + * \param [IN] rxBeaconSetup Pointer to the function parameters + */ + void RegionUS915RxBeaconSetup( RxBeaconSetup_t* rxBeaconSetup, uint8_t* outDr ); + +/*! \} defgroup REGIONUS915 */ + +#endif // __REGION_US915_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/radio/radio.h b/cores/asr650x/kernel/protocols/lorawan/lora/radio/radio.h new file mode 100644 index 00000000..730ccdce --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/radio/radio.h @@ -0,0 +1,359 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + +Description: Generic radio driver definition + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian +*/ +#ifndef __RADIO_H__ +#define __RADIO_H__ + +/*! + * Radio driver supported modems + */ +typedef enum +{ + MODEM_FSK = 0, + MODEM_LORA, +}RadioModems_t; + +/*! + * Radio driver internal state machine states definition + */ +typedef enum +{ + RF_IDLE = 0, //!< The radio is idle + RF_RX_RUNNING, //!< The radio is in reception state + RF_TX_RUNNING, //!< The radio is in transmission state + RF_CAD, //!< The radio is doing channel activity detection +}RadioState_t; + +/*! + * \brief Radio driver callback functions + */ +typedef struct +{ + /*! + * \brief Tx Done callback prototype. + */ + void ( *TxDone )( void ); + /*! + * \brief Tx Timeout callback prototype. + */ + void ( *TxTimeout )( void ); + /*! + * \brief Rx Done callback prototype. + * + * \param [IN] payload Received buffer pointer + * \param [IN] size Received buffer size + * \param [IN] rssi RSSI value computed while receiving the frame [dBm] + * \param [IN] snr Raw SNR value given by the radio hardware + * FSK : N/A ( set to 0 ) + * LoRa: SNR value in dB + */ + void ( *RxDone )( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ); + /*! + * \brief Rx Timeout callback prototype. + */ + void ( *RxTimeout )( void ); + /*! + * \brief Rx Error callback prototype. + */ + void ( *RxError )( void ); + /*! + * \brief FHSS Change Channel callback prototype. + * + * \param [IN] currentChannel Index number of the current channel + */ + void ( *FhssChangeChannel )( uint8_t currentChannel ); + + /*! + * \brief CAD Done callback prototype. + * + * \param [IN] channelDetected Channel Activity detected during the CAD + */ + void ( *CadDone ) ( bool channelActivityDetected ); +}RadioEvents_t; + +/*! + * \brief Radio driver definition + */ +struct Radio_s +{ + /*! + * \brief Initializes the radio + * + * \param [IN] events Structure containing the driver callback functions + */ + void ( *IoInit )( void ); + + /*! + * \brief Initializes the radio + * + * \param [IN] events Structure containing the driver callback functions + */ + void ( *IoDeInit )( void ); + /*! + * \brief Initializes the radio + * + * \param [IN] events Structure containing the driver callback functions + * \param [OUT] returns radioWakeUpTime + */ + uint32_t ( *Init )( RadioEvents_t *events ); + /*! + * Return current radio status + * + * \param status Radio status.[RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING] + */ + RadioState_t ( *GetStatus )( void ); + /*! + * \brief Configures the radio with the given modem + * + * \param [IN] modem Modem to be used [0: FSK, 1: LoRa] + */ + void ( *SetModem )( RadioModems_t modem ); + /*! + * \brief Sets the channel frequency + * + * \param [IN] freq Channel RF frequency + */ + void ( *SetChannel )( uint32_t freq ); + /*! + * \brief Sets the channels configuration + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] freq Channel RF frequency + * \param [IN] rssiThresh RSSI threshold + * \param [IN] maxCarrierSenseTime Max time while the RSSI is measured + * + * \retval isFree [true: Channel is free, false: Channel is not free] + */ + bool ( *IsChannelFree )( RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime ); + /*! + * \brief Generates a 32 bits random value based on the RSSI readings + * + * \remark This function sets the radio in LoRa modem mode and disables + * all interrupts. + * After calling this function either Radio.SetRxConfig or + * Radio.SetTxConfig functions must be called. + * + * \retval randomValue 32 bits random value + */ + uint32_t ( *Random )( void ); + /*! + * \brief Sets the reception parameters + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] bandwidth Sets the bandwidth + * FSK : >= 2600 and <= 250000 Hz + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [IN] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [IN] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [IN] bandwidthAfc Sets the AFC Bandwidth (FSK only) + * FSK : >= 2600 and <= 250000 Hz + * LoRa: N/A ( set to 0 ) + * \param [IN] preambleLen Sets the Preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [IN] symbTimeout Sets the RxSingle timeout value + * FSK : timeout in number of bytes + * LoRa: timeout in symbols + * \param [IN] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [IN] payloadLen Sets payload length when fixed length is used + * \param [IN] crcOn Enables/Disables the CRC [0: OFF, 1: ON] + * \param [IN] FreqHopOn Enables disables the intra-packet frequency hopping + * FSK : N/A ( set to 0 ) + * LoRa: [0: OFF, 1: ON] + * \param [IN] HopPeriod Number of symbols between each hop + * FSK : N/A ( set to 0 ) + * LoRa: Number of symbols + * \param [IN] iqInverted Inverts IQ signals (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [0: not inverted, 1: inverted] + * \param [IN] rxContinuous Sets the reception in continuous mode + * [false: single mode, true: continuous mode] + */ + void ( *SetRxConfig )( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint32_t bandwidthAfc, uint16_t preambleLen, + uint16_t symbTimeout, bool fixLen, + uint8_t payloadLen, + bool crcOn, bool FreqHopOn, uint8_t HopPeriod, + bool iqInverted, bool rxContinuous ); + /*! + * \brief Sets the transmission parameters + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] power Sets the output power [dBm] + * \param [IN] fdev Sets the frequency deviation (FSK only) + * FSK : [Hz] + * LoRa: 0 + * \param [IN] bandwidth Sets the bandwidth (LoRa only) + * FSK : 0 + * LoRa: [0: 125 kHz, 1: 250 kHz, + * 2: 500 kHz, 3: Reserved] + * \param [IN] datarate Sets the Datarate + * FSK : 600..300000 bits/s + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512, + * 10: 1024, 11: 2048, 12: 4096 chips] + * \param [IN] coderate Sets the coding rate (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8] + * \param [IN] preambleLen Sets the preamble length + * FSK : Number of bytes + * LoRa: Length in symbols (the hardware adds 4 more symbols) + * \param [IN] fixLen Fixed length packets [0: variable, 1: fixed] + * \param [IN] crcOn Enables disables the CRC [0: OFF, 1: ON] + * \param [IN] FreqHopOn Enables disables the intra-packet frequency hopping + * FSK : N/A ( set to 0 ) + * LoRa: [0: OFF, 1: ON] + * \param [IN] HopPeriod Number of symbols between each hop + * FSK : N/A ( set to 0 ) + * LoRa: Number of symbols + * \param [IN] iqInverted Inverts IQ signals (LoRa only) + * FSK : N/A ( set to 0 ) + * LoRa: [0: not inverted, 1: inverted] + * \param [IN] timeout Transmission timeout [ms] + */ + void ( *SetTxConfig )( RadioModems_t modem, int8_t power, uint32_t fdev, + uint32_t bandwidth, uint32_t datarate, + uint8_t coderate, uint16_t preambleLen, + bool fixLen, bool crcOn, bool FreqHopOn, + uint8_t HopPeriod, bool iqInverted, uint32_t timeout ); + /*! + * \brief Checks if the given RF frequency is supported by the hardware + * + * \param [IN] frequency RF frequency to be checked + * \retval isSupported [true: supported, false: unsupported] + */ + bool ( *CheckRfFrequency )( uint32_t frequency ); + /*! + * \brief Computes the packet time on air in ms for the given payload + * + * \Remark Can only be called once SetRxConfig or SetTxConfig have been called + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] pktLen Packet payload length + * + * \retval airTime Computed airTime (ms) for the given packet payload length + */ + uint32_t ( *TimeOnAir )( RadioModems_t modem, uint8_t pktLen ); + /*! + * \brief Sends the buffer of size. Prepares the packet to be sent and sets + * the radio in transmission + * + * \param [IN]: buffer Buffer pointer + * \param [IN]: size Buffer size + */ + void ( *Send )( uint8_t *buffer, uint8_t size ); + /*! + * \brief Sets the radio in sleep mode + */ + void ( *Sleep )( void ); + /*! + * \brief Sets the radio in standby mode + */ + void ( *Standby )( void ); + /*! + * \brief Sets the radio in reception mode for the given time + * \param [IN] timeout Reception timeout [ms] + * [0: continuous, others timeout] + */ + void ( *Rx )( uint32_t timeout ); + /*! + * \brief Start a Channel Activity Detection + */ + void ( *StartCad )( void ); + /*! + * \brief Sets the radio in continuous wave transmission mode + * + * \param [IN]: freq Channel RF frequency + * \param [IN]: power Sets the output power [dBm] + * \param [IN]: time Transmission mode timeout [s] + */ + void ( *SetTxContinuousWave )( uint32_t freq, int8_t power, uint16_t time ); + /*! + * \brief Reads the current RSSI value + * + * \retval rssiValue Current RSSI value in [dBm] + */ + int16_t ( *Rssi )( RadioModems_t modem ); + /*! + * \brief Writes the radio register at the specified address + * + * \param [IN]: addr Register address + * \param [IN]: data New register value + */ + void ( *Write )( uint8_t addr, uint8_t data ); + /*! + * \brief Reads the radio register at the specified address + * + * \param [IN]: addr Register address + * \retval data Register value + */ + uint8_t ( *Read )( uint8_t addr ); + /*! + * \brief Writes multiple radio registers starting at address + * + * \param [IN] addr First Radio register address + * \param [IN] buffer Buffer containing the new register's values + * \param [IN] size Number of registers to be written + */ + void ( *WriteBuffer )( uint8_t addr, uint8_t *buffer, uint8_t size ); + /*! + * \brief Reads multiple radio registers starting at address + * + * \param [IN] addr First Radio register address + * \param [OUT] buffer Buffer where to copy the registers data + * \param [IN] size Number of registers to be read + */ + void ( *ReadBuffer )( uint8_t addr, uint8_t *buffer, uint8_t size ); + /*! + * \brief Set synchro word in radio + * + * \param [IN] data THe syncword + */ + void ( *SetSyncWord )( uint8_t data ); + + /*! + * \brief Sets the maximum payload length. + * + * \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa] + * \param [IN] max Maximum payload length in bytes + */ + void ( *SetMaxPayloadLength )( RadioModems_t modem, uint8_t max ); + /*! + * \brief Service to get the radio wake-up time. + * + * \retval Value of the radio wake-up time. + */ + uint32_t ( *GetRadioWakeUpTime ) ( void ); + +}; + +/*! + * \brief Radio driver + * + * \remark This variable is defined and initialized in the specific radio + * board implementation + */ +extern const struct Radio_s Radio; + +#endif // __RADIO_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/readme.md b/cores/asr650x/kernel/protocols/lorawan/lora/readme.md new file mode 100644 index 00000000..c94f0188 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/readme.md @@ -0,0 +1,723 @@ + / _____) _ | | + ( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | + (______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + +LoRaWAN endpoint stack implementation and example projects. +===================================== + +1. Introduction +---------------- +The aim of this project is to show an example of the endpoint LoRaWAN stack implementation. + +This LoRaWAN stack is an EU868 and US915 bands Class A and Class C endpoint implementation +fully compatible with LoRaWAN 1.0.1 specification. +Each LoRaWAN application example includes the LoRaWAN certification protocol implementation. + +SX1272/76 radio drivers are also provided. +In case only point to point links are required a Ping-Pong application is provided as example. + +*The LoRaWAN stack API documentation can be found at: http://stackforce.github.io/LoRaMac-doc/* + +**Note 1:** + +*A port of this project can be found on [MBED Semtech Team page](http://developer.mbed.org/teams/Semtech/)* + +*The example projects are:* + +1. [LoRaWAN-demo-72](http://developer.mbed.org/teams/Semtech/code/LoRaWAN-demo-72/) +2. [LoRaWAN-demo-76](http://developer.mbed.org/teams/Semtech/code/LoRaWAN-demo-76/) + + +2. System schematic and definitions +------------------------------------ +The available supported hardware platforms schematics can be found in the Doc directory. + +3. Acknowledgments +------------------- +The mbed (https://mbed.org/) project was used at the beginning as source of +inspiration. + +This program uses the AES algorithm implementation (http://www.gladman.me.uk/) +by Brian Gladman. + +This program uses the CMAC algorithm implementation +(http://www.cse.chalmers.se/research/group/dcs/masters/contikisec/) by +Lander Casado, Philippas Tsigas. + +4. Dependencies +---------------- +This program depends on specific hardware platforms. Currently the supported +platforms are: + + - LoRaMote + MCU : STM32L151CB - 128K FLASH, 10K RAM, Timers, SPI, I2C, + USART, + USB 2.0 full-speed device/host/OTG controller, + DAC, ADC, DMA + RADIO : SX1272 + ANTENNA : Printed circuit antenna + BUTTONS : No + LEDS : 3 + SENSORS : Proximity, Magnetic, 3 axis Accelerometer, Pressure, + Temperature + GPS : Yes, UP501 module + EXTENSION HEADER : Yes, 20 pins + REMARK : The MCU and Radio are on an IMST iM880A module + + - MoteII + MCU : STM32L051C8 - 64K FLASH, 8K RAM, Timers, SPI, I2C, + USART, + USB 2.0 full-speed device/host/OTG controller (Not used), + DAC, ADC, DMA + RADIO : SX1272 + ANTENNA : Printed circuit antenna + BUTTONS : 3 + LEDS : 3 + SENSORS : Magnetic, 3 axis Accelerometer, Pressure, + Temperature + GPS : Yes, PAM7Q module + Display : OLED + ST-Link : Yes, MBED like + EXTENSION HEADER : Yes, 20 pins + REMARK : The MCU and Radio are on an IMST iM881A module + + - NAMote72 + MCU : STM32L152RC - 256K FLASH, 32K RAM, Timers, SPI, I2C, + USART, + USB 2.0 full-speed device/host/OTG controller (Not used), + DAC, ADC, DMA + RADIO : SX1272 + ANTENNA : Printed circuit antenna + BUTTONS : No + LEDS : 4 + SENSORS : Magnetic, 3 axis Accelerometer, Pressure, + Temperature + GPS : Yes, SIM39EA module + Display : OLED + ST-Link : Yes, MBED like + EXTENSION HEADER : Yes, Arduino connectors + REMARK : None + + - SensorNode + MCU : STM32L151CBU6 - 128K FLASH, 16K RAM, Timers, SPI, I2C, + USART, + USB 2.0 full-speed device/host/OTG controller, + DAC, ADC, DMA + RADIO : SX1276 + ANTENNA : Printed circuit antenna + BUTTONS : Power ON/OFF, General purpose button + LEDS : 3 + SENSORS : Proximity, Magnetic, 3 axis Accelerometer, Pressure, + Temperature + GPS : Yes, SIM39EA module + EXTENSION No + REMARK : The MCU and Radio are on an NYMTEK Cherry-LCC module + + - SK-iM880A ( IMST starter kit ) + MCU : STM32L151CB - 128K FLASH, 10K RAM, Timers, SPI, I2C, + USART, + USB 2.0 full-speed device/host/OTG controller, + DAC, ADC, DMA + RADIO : SX1272 + ANTENNA : Connector for external antenna + BUTTONS : 1 Reset, 3 buttons + 2 DIP-Switch + LEDS : 3 + SENSORS : Potentiometer + GPS : Possible through pin header GPS module connection + SDCARD : No + EXTENSION HEADER : Yes, all IMST iM880A module pins + REMARK : None + +5. Usage +--------- +Projects for CooCox-CoIDE and Keil Integrated Development Environments are available. + +One project is available per application and for each hardware platform in each +development environment. Different targets/configurations have been created in +the different projects in order to select different options such as the usage or +not of a bootloader and the radio frequency band to be used. + +6. Changelog +------------- +2017-04-19, V4.3.2 +* General (Last release based on LoRaWAN specification 1.0.1) + 1. This version has passed EU868 and US915 LoRa-Alliance compliance tests. + 2. GitHub reported issues corrections. + 3. Added an algorithm to automatically compute the Rx windows parameters. (Window symbolTimeout and Offset from downlink expected time) + 4. Added a workaround to reset the radio in case a TxTimeout occurs. + 5. Modified FSK modem handling to use the provided symbolTimeout (1 symbol equals 1 byte) when in RxSingle mode. + 6. Added newly defined TxCw(Tx Continuous Wave) certification protocol command. + 7. Added a fix for an overflow issue that could happen with NmeaStringSize variable. + 8. Improved GpioMcuInit function to first configure the output pin state before activating the pin. + +* LoRaWAN + 1. GitHub reported issues corrections. + 2. Changed the AdrAckCounter handling as expected by the test houses. + 3. Fix an issue where the node stopped transmitting. + 4. Removed useless LoRaMacPayload buffer. + 5. MAC layer indications handling simplification. + 6. Relocate parameter settings from ResetMacParameters to the initialization. + +2017-02-27, V4.3.1 +* General + 1. This version has passed EU868 and US915 LoRa-Alliance compliance tests. + 2. Update the MAC layer in order to be LoRaWAN version 1.0.1 compliant (Mainly US915 bug fixes) + 3. Removed api-v3 support from the project. + 4. GitHub reported issues corrections. + 5. Updated SensorNode projects according to the new MCU reference STM32L151CBU6. Bigger memories. + 6. Addition of MoteII platform based on the IMST module iM881A (STM32L051C8) + 7. Addition of NAMote72 platform + 8. Correct compliance test protocol command 0x06 behaviour + 9. Added TxCw (Tx continuous wave) LoRaWAN compliance protocol command. + 10. Added TxContinuousWave support to the radio drivers. + 11. Updated ST HAL drivers. + - STM32L1xx_HAL-Driver : V1.2.0 + - STM32L0xx_HAL_Driver : V1.7.0 + +* LoRaWAN + 1. US band corrections in order to pass the LoRaWAN certification. + 2. GitHub reported issues corrections. + 3. Add region CN470 support. + +2016-06-22, V4.3.0 +* General + 1. This version has passed all LoRa-Alliance compliance tests. + 2. Update the MAC layer in order to be LoRaWAN version 1.0.1 compliant + 3. Applied to all application files the certification protocol change for LoRaWAN 1.0.1 compliance tests. + + **REMARK**: api-v3 application files aren't updated. + + 4. Add radio RX_TIMEOUT irq clear into the irq handler. + 5. Removed the end less loop from HAL_UART_ErrorCallback. + 6. Update of the STM32L0 HAL to version 1.6.0 + 7. Consolidated the line endings across all project files. + Windows line endings has been choose for almost every file. + +* LoRaWAN + 1. Updated maximum payload size for US band. + 2. Update datarate offset table for US band. + 3. Make MAC commands sticky + 4. Add retransmission back-off + 5. Remove the TxPower limitation for US band on LoRaMacMibSetRequestConfirm function. The power will be limited anyway when the SendFrameOnChannel functions is called. + 6. Issue(#81): Bug fix in function LoRaMacMlmeRequest case MLME_JOIN. Function will return LORAMAC_STATUS_BUSY in case the MAC is in status MAC_TX_DELAYED. + 7. Add debug pin support to LoRaMote platform. + 8. Updated and improved MPL3115 device driver. + 9. Issue(#83): Bug fix in parameter validation + 10. Issue(#84): Fix issue of CalibrateTimer function. + 11. RTC driver major update + 12. Applied pull request #87. + 13. Add a function to verify the RX frequency of window 2 for US band. + 14. Issue(#88): Bug fix in function PrepareFrame where repeated MAC commands were not handled correctly. + 15. Bug fix in OnRadioRxDone. Node now drops frames on port 0 with fOpts > 0. + 16. Bug fix in OnRadioRxDone. Node now receives frames with fOpts > 0 when no payload is present. + +2016-05-13, V4.2.0 +* General + 1. This version has passed all LoRa-Alliance compliance tests. + 2. Update STM32L1xx_HAL_Driver version to 1.5. Update related drivers and implementations accordingly. + + **REMARK**: This change implies that the time base had to be changed from microseconds to milliseconds. + + 3. Corrected the frequency check condition for // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth + 4. Optimize radio drivers regarding FSK PER + 5. Resolve issue when calling SX127xInit function more than once + 6. Add a definition for the LoRaWAN device address. Add an IEEE_OUI for the LoRaWAN device EUI. + 7. Add a definition for the default datarate. + 8. Issue(#66) correction of functions SX1276SetOpMode and SX1272SetOpMode. + 9. Issue(#68): Fix for low level RF switch control. + 10. Increase RTC tick frequency for higher resolution. + 11. Update the radio wake up time. + +* LoRaWAN + 1. Issue(#56) correction + 2. Update channel mask handling for US915 hybrid mode to support any block in the channel mask. + 3. Issue(#63) correct the maximum payload length in RX mode. + 4. Fix Tx power setting loss for repeated join requests on US band. + 5. Introduce individual MIN and MAX datarates for RX and TX. + 6. Add the possibility to set and get the ChannelsDefaultDatarate. + 7. Optimization of the RX symbol timeout. + 8. Issue(#59): Add the possibility to set the uplink and downlink counter. + 9. Replace definition LORAMAC_DEFAULT_DATARATE by ChannelsDefaultDatarate in LoRaMacChannelAdd. + 10. Issue(#72): Fix of possible array overrun in LoRaMacChannelRemove. + 11. Introduce a new status MAC_RX_ABORT. Reset MAC_TX_RUNNING only in OnMacStateCheckTimerEvent. + 12. Accept MAC information of duplicated, confirmed downlinks. + 13. Issue(#74): Drop frames with a downlink counter difference greater or equal to MAX_FCNT_GAP. + +2016-03-10, V4.1.0 +* General + 1. This version has passed all mandatory LoRa-Alliance compliance tests. + + *One of the optional tests is unsuccessful (FSK downlinks PER on Rx1 and Rx2 windows) and is currently under investigation.* + 2. Removed support for Raisonance Ride7 IDE (Reduces the amount of work to be done at each new release) + 3. Removed the Bleeper-72 and Bleeper-76 platforms support as these are now deprecated. + 4. Application state machine. Relocate setting sleep state and update the duty cycle in compliance test mode. + 5. Bug fix in TimerIrqHandler. Now, it is possible to insert timers in callback. + 6. Changed TimerHwDelayMs function to be re-entrant. + 7. Corrected FSK modem packets bigger than 64 bytes handling (Issue #36) + +* LoRaWAN + 1. Rename attribute nbRetries to NbTrials in structure McpsReqConfirmed_t. (Issue #37) + 2. Updated implementation of SetNextChannel. Added enabling default channels in case of join request. (Issue #39) + 3. Add missing documentation about MIB_REPEATER_SUPPORT. (Issue #42). + 4. Add a new LoRaMacState to allow adding channels during TX procedure. (Issue #43) + 5. Relocate the activation of LoRaMacFlags.Bits.McpsInd in OnRadioRxDone. + 6. Add a new function PrepareRxDoneAbort to prepare a break-out of OnRadioRxDone in case of an error + 7. Activate default channels in case all others are disabled. (Issue #39) + 8. Bug fix in setting the default channel in case none is enabled. + 9. SRV_MAC_NEW_CHANNEL_REQ MAC command added a fix to the macIndex variable on US915 band. + 10. Start the MacStateCheckTimer in OnRxDone and related error cases with a short interval to handle events promptly. (Issue #44) + 11. Reset status of NodeAckRequested if we received an ACK or in case of timeout. + 12. Removed additional EU868 channels from the LoRaWAN implementation files. GitHub (Issue #49) + The creation of these additional channels has been moved to the application example. + 13. Improved and corrected AdrNextDr function. + +2015-12-18, V4.0.0 +* General + 1. STACKFORCE new API integration + 2. Reverse the EUIs arrays in the MAC layer. + 3. LoRaWAN certification protocol implementation + 4. All reported issues and Pull requests have been addressed. + +2015-10-06, V3.4.1 +* General + 1. Bug fixes + +* LoRaWAN + 1. Corrected downlink counter roll over management when several downlinks were missed. + 2. Corrected the Radio maximum payload length management. Radio was filtering received frames with a length bigger than the transmitted one. + 3. Applied Pull request #22 solution proposition. + +2015-10-30, V3.4.0 +* General + 1. Changed all applications in order to have preprocessing definitions on top of the files and added relevant comments + 2. Applications LED control is no more done into the timer callback functions but instead on the main while loop. + 3. Added TimerStop function calls to each timer event callback. + 4. Corrected timings comments. Timing values are most of the time us based. + 5. Changed types names for stdint.h names. Helps on code portability + 6. Renamed rand and srand to rand1 and srand1. Helps on code portability + 7. Added some missing variables casts. Helps on code portability + 8. Removed NULL definition from board.h + 9. Added const variable attribute when necessary to functions prototypes + 10. Moved ID1, ID2 and ID3 definition from board.h to board.c, usb-cdc-board.c and usb-dfu-board.c + 11. Removed the definition of RAND_SEED. It has been replaced by a function named BoardGetRandomSeed + 12. Renamed BoardMeasureBatterieLevel to BoardGetBatteryLevel + 13. Added SetMaxPayloadLength API function to SX1272 and SX1276 radio drivers + 14. Changed the name of Radio API Status function to GetStatus + 15. AES/CMAC Changed types names for stdint.h names. Helps on code portability (Issue #20) + 16. Moved __ffs function from utilities.h to spi-board.c. This function is only used there. + 17. Utilities.c removed fputc function redefinition. + 18. Replaced the usage of __IO attribute by volatile. + +* LoRaWAN + 1. Added support for the US915 band (Normal mode and hybrid mode. Hybrid mode is a temporary configuration up until servers support it automatically) (Issue #16) + 2. Corrected and simplified the downlink sequence counter management. + 3. Removed the usage of PACKED attribute for data structures. + 4. Renamed LoRaMacEvent_t into LoRaMacCallbacks_t and added a function pointer for getting battery level status + 5. Renamed LoRaMacSetDutyCycleOn into LoRaMacSetTestDutyCycleOn + 6. Renamed LoRaMacSetMicTest into LoRaMacTestSetMic + 7. Increased the PHY buffer size to 250 + 8. Removed IsChannelFree check on LoRaMacSetNextChannel function. LoRaWAN is an ALHOA protocol. (Pull request #8) + 9. LoRaMacEventInfo.TxDatarate now returns LoRaWAN datarate (DR0 -> DR7) instead of (SF12 -> DF7) + 10. Corrected channel mask management for EU868 band. + 11. Corrected LoRaMacPrepareFrame behavior function when no applicative payload is present. + 12. LoRaMac-board.h now implements the settings for the PHY layers specified by LoRaWAN 1.0 specification. ( EU433, CN780, EU868, US915 ) (Issue #19) + 13. Added LORAMAC_MIN_RX1_DR_OFFSET and LORAMAC_MAX_RX1_DR_OFFSET definitions to LoRaMac-board.h. Can be different upon used PHY layer + 14. Added the limitation of output power according to the number of enabled channels for US915 band. + 15. Added the limitation of the applicative payload length according to the datarate. Does not yet take in account the MAC commands buffer. (Issue #15) + 16. Corrected MacCommandBufferIndex management. (Issue #18) + +2015-08-07, v3.3.0 +* General + 1. Added the support for LoRaWAN Class C devices. + 2. Implemented the radios errata note workarounds. SX1276 errata 2.3 "Receiver Spurious Reception of a LoRa Signal" is not yet implemented. + 3. Increased FSK SyncWord timeout value in order to listen for longer time if a down link is available or not. Makes FSK downlink more reliable. + 4. Increased the UART USB FIFO buffer size in order to handle bigger chunks of data. + +* LoRaWAN + 1. Renamed data rates as per LoRaWAN specification. + 2. Added the support for LoRaWAN Class C devices. + 3. Handling of the MAC commands was done incorrectly the condition to verify the length of the buffer has changed from < to <=. + 4. Added the possibility to change the channel mask and number of repetitions trough SRV_MAC_LINK_ADR_REQ command when ADR is disabled. + 5. Corrected Rx1DrOffset management. In previous version DR1 was missing for all offsets. + 6. Changed confirmed messages function to use default datarate when ADR control is off. + 7. After a Join accept the node falls back to the default datarate. Enables the user to Join a network using a different datarate from its own default one. + 8. Corrected default FSK channel frequency. + 9. Solved a firmware freezing when one of the following situations arrived in OnRxDone callback: bad address, bad MIC, bad frame. (Pull request #10) + 10. Moved the MAC commands processing to the right places. FOpts field before the Payload and Port 0 just after the decryption. (Pull request #9) + 11. Weird conditions to check datarate on cmd mac SRV_MAC_NEW_CHANNEL_REQ (Pull request #7) + 12. Ignore join accept message if already joined (Pull request #6) + 13. Channel index verification should use OR on SRV_MAC_NEW_CHANNEL_REQ command (Pull request #5) + 14. Corrected the CFList management on JoinAccept. The for loop indexes were wrong. (Pull request #4) + 15. Correction of AES key size (Pull request #3) + +2015-04-30, v3.2.0 +* General + 1. Updated LoRaMac implementation according to LoRaWAN R1.0 specification + 2. General cosmetics corrections + 3. Added the support of packed structures when using IAR tool chain + 4. Timers: Added a function to get the time in us. + 5. Timers: Added a typedef for time variables (TimerTime_t) + 6. Radios: Changed the TimeOnAir radio function to return a uint32_t value instead of a double. The value is in us. + 7. Radios: Corrected the 250 kHz bandwidth choice for the FSK modem + 8. GPS: Added a function that returns if the GPS has a fix or not. + 9. GPS: Changed the GetPosition functions to return a latitude and longitude of 0 and altitude of 65535 when no GPS fix. + +* LoRaWAN + 1. Removed support for previous LoRaMac/LoRaWAN specifications + 2. Added missing MAC commands and updated others when necessary + * Corrected the Port 0 MAC commands decryption + * Changed the way the upper layer is notified. Now it is only notified + when all the operations are finished. + + When a ClassA Tx cycle starts a timer is launched to check every second if everything is finished. + + * Added a new parameter to LoRaMacEventFlags structure that indicates on which Rx window the data has been received. + * Added a new parameter to LoRaMacEventFlags structure that indicates if there is applicative data on the received payload. + * Corrected ADR MAC command behavior + * DutyCycle enforcement implementation (EU868 PHY only) + + **REMARK 1** *The regulatory duty cycle enforcement is enabled by default + which means that for lower data rates the node may not transmit a new + frame as quickly as requested. + The formula used to compute the node idle time is* + + *Toff = TimeOnAir / DutyCycle - TxTimeOnAir* + + *Example:* + *A device just transmitted a 0.5 s long frame on one default channel. + This channel is in a sub-band allowing 1% duty-cycle. Therefore this + whole sub-band (868 MHz - 868.6 MHz) will be unavailable for 49.5 s.* + + **REMARK 2** *The duty cycle enforcement can be disabled for test + purposes by calling the LoRaMacSetDutyCycleOn function with false + parameter.* + * Implemented aggregated duty cycle management + * Added a function to create new channels + * Implemented the missing features on the JoinAccept MAC command + * Updated LoRaMacJoinDecrypt function to handle the CFList field. + 3. Due to duty cycle management the applicative API has changed. + All applications must be updated accordingly. + 4. Added the possibility to chose to use either public or private networks + +2015-01-30, v3.1.0 +* General + 1. Started to add support for CooCox CoIDE Integrated Development Environment. + Currently only LoRaMote and SensorNode platform projects are available. + 2. Updated GCC compiler linker scripts. + 3. Added the support of different tool chains for the HardFault_Handler function. + + 4. Corrected Radio drivers I&Q signals inversion to be possible in Rx and in Tx. + Added some missing radio state machine initialization. + 5. Changed the RSSI values type from int8_t to int16_t. We can have RSSI values below -128 dBm. + 6. Corrected SNR computation on RxDone interrupt. + 7. Updated radio API to support FHSS and CAD handling. + 8. Corrected in SetRxConfig function the FSK modem preamble register name. + 9. Added an invalid bandwidth to the Bandwidths table in order to avoid an error + when selecting 250 kHz bandwidth when using FSK modem. + + 10. Corrected RTC alarm setup which could be set to an invalid date. + 11. Added another timer in order increment the tick counter without blocking the normal timer count. + 12. Added the possibility to switch between low power timers and normal timers on the fly. + 13. I2C driver corrected the 2 bytes internal address management. + Corrected buffer read function when more that 1 byte was to be read. + Added a function to wait for the I2C bus to become IDLE. + 14. Added an I2C EEPROM driver. + 15. Corrected and improved USB Virtual COM Port management files. + Corrected the USB CDC and USB UART drivers. + 16. Added the possibility to analyze a hard fault interrupt. + +* LoRaMac + 1. Corrected RxWindow2 Datarate management. + 2. SrvAckRequested variable was never reset. + 3. Corrected tstIndoor applications for LoRaMac R3.0 support. + 4. LoRaMac added the possibility to configure almost all the MAC parameters. + 5. Corrected the LoRaMacSetNextChannel function. + 6. Corrected the port 0 MAC command decoding. + 7. Changed all structures declarations to be packed. + 8. Corrected the Acknowledgment retries management when only 1 trial is needed. + Before the device was issuing at least 2 trials. + 9. Corrected server mac new channel req answer. + 10. Added the functions to read the Up and Down Link sequence counters. + 11. Corrected SRV_MAC_RX2_SETUP_REQ frequency handling. Added a 100 multiplication. + 12. Corrected SRV_MAC_NEW_CHANNEL_REQ. Removed the DutyCycle parameter decoding. + 13. Automatically activate the channel once it is created. + 14. Corrected NbRepTimeoutTimer initial value. RxWindow2Delay already contains RxWindow1Delay in it. + +2014-07-18, v3.0.0 +* General + 1. Added to Radio API the possibility to select the modem. + 2. Corrected RSSI reading formulas as well as changed the RSSI and SNR values from double to int8_t type. + 3. Changed radio callbacks events to timeout when it is a timeout event and error when it is a CRC error. + 4. Radio API updated. + 5. Updated ping-pong applications. + 6. Updated tx-cw applications. + 7. Updated LoRaMac applications in order to handle LoRaMac returned functions calls status. + 8. Updated LoRaMac applications to toggle LED2 each time there is an application payload down link. + 9. Updated tstIndoor application to handle correctly more than 6 channels. + 10. Changed the MPL3115 altitude variable from unsigned to signed value. + 11. Replaced the usage of pow(2, n) by defining POW2 functions. Saves ~2 KBytes of code. + 12. Corrected an issue potentially arriving when LOW_POWER_MODE_ENABLE wasn't defined. + A timer interrupt could be generated while the TimerList could already be emptied. + + +* LoRaMac + 1. Implemented LoRaMac specification R3.0 changes. + + 2. MAC commands implemented + * LinkCheckReq **YES** + * LinkCheckAns **YES** + * LinkADRReq **YES** + * LinkADRAns **YES** + * DutyCycleReq **YES** + * DutyCycleAns **YES** + * Rx2SetupReq **YES** + * Rx2SetupAns **YES** + * DevStatusReq **YES** + * DevStatusAns **YES** + * JoinReq **YES** + * JoinAccept **YES** + * NewChannelReq **YES** + * NewChannelAns **YES** + + 3. Features implemented + * Possibility to shut-down the device **YES** + + Possible by issuing DutyCycleReq MAC command. + * Duty cycle management enforcement **NO** + * Acknowledgments retries **YES** + * Unconfirmed messages retries **YES** + +2014-07-10, v2.3.RC2 +* General + 1. Corrected all radios antenna switch low power mode handling. + 2. SX1276: Corrected antenna switch control. + +2014-06-06, v2.3.RC1 +* General + 1. Added the support for SX1276 radio. + 2. Radio continuous reception mode correction. + 3. Radio driver RxDone callback function API has changed ( size parameter is no more a pointer). + Previous function prototype: + + void ( *RxDone )( uint8_t *payload, uint16_t *size, double rssi, double snr, uint8_t rawSnr ); + + New function prototype: + + void ( *RxDone )( uint8_t *payload, uint16_t size, double rssi, double snr, uint8_t rawSnr ); + + 4. Added Bleeper-76 and SensorNode platforms support. + 5. Added to the radio drivers a function that generates a random value from + RSSI readings. + 6. Added a project to transmit a continuous wave and a project to measure the + the radio sensitivity. + 7. Added a bootloader project for the LoRaMote and SensorNode platforms. + 8. The LoRaMac application for Bleeper platforms now sends the Selector and LED status plus the sensors values. + * The application payload for the Bleeper platforms is as follows: + + LoRaMac port 1: + + { 0xX0/0xX1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } + ---------- ---------- ---------- ---------- ---- + | | | | | + SELECTOR/LED PRESSURE TEMPERATURE ALTITUDE BATTERY + MSB nibble = SELECTOR (barometric) + LSB bit = LED + 9. Redefined rand() and srand() standard C functions. These functions are + redefined in order to get the same behavior across different compiler + tool chains implementations. + 10. GPS driver improvements. Made independent of the board platform. + 11. Simplified the RTC management. + 12. Added a function to the timer driver that checks if a timer is already in + the list or not. + 13. Added the UART Overrun bit exception handling to the UART driver. + 14. Removed dependency of spi-board files to the "__builtin_ffs" function. + This function is only available on GNU compiler tool suite. Removed --gnu + compiler option from Keil projects. Added own __ffs function + implementation to utilities.h file. + 15. Removed obsolete class1 devices support. + 16. Known bugs correction. + +* LoRaMac + 1. MAC commands implemented + * LinkCheckReq **YES** + * LinkCheckAns **YES** + * LinkADRReq **YES** + * LinkADRAns **YES** + * DutyCycleReq **YES** (LoRaMac specification R2.2.1) + * DutyCycleAns **YES** (LoRaMac specification R2.2.1) + * Rx2SetupReq **YES** (LoRaMac specification R2.2.1) + * Rx2SetupAns **YES** (LoRaMac specification R2.2.1) + * DevStatusReq **YES** + * DevStatusAns **YES** + * JoinReq **YES** + * JoinAccept **YES** (LoRaMac specification R2.2.1) + * NewChannelReq **YES** (LoRaMac specification R2.2.1) + * NewChannelAns **YES** (LoRaMac specification R2.2.1) + 2. Features implemented + * Possibility to shut-down the device **YES** + + Possible by issuing DutyCycleReq MAC command. + * Duty cycle management enforcement **NO** + * Acknowledgments retries **WORK IN PROGRESS** + + Not fully debugged. Disabled by default. + * Unconfirmed messages retries **WORK IN PROGRESS** (LoRaMac specification R2.2.1) + 3. Implemented LoRaMac specification R2.2.1 changes. + 4. Due to new specification the LoRaMacInitNwkIds LoRaMac API function had + to be modified. + + Previous function prototype: + + void LoRaMacInitNwkIds( uint32_t devAddr, uint8_t *nwkSKey, uint8_t *appSKey ); + + New function prototype: + + void LoRaMacInitNwkIds( uint32_t netID, uint32_t devAddr, uint8_t *nwkSKey, uint8_t *appSKey ); + 5. Changed the LoRaMac channels management. + 6. LoRaMac channels definition has been moved to LoRaMac-board.h file + located in each specific board directory. + +2014-04-07, v2.2.0 +* General + 1. Added IMST SK-iM880A starter kit board support to the project. + * The application payload for the SK-iM880A platform is as follows: + + LoRaMac port 3: + + { 0x00/0x01, 0x00, 0x00, 0x00 } + ---------- ----- ---------- + | | | + LED POTI VDD + 2. Ping-Pong applications have been split per supported board. + 3. Corrected the SX1272 output power management. + Added a variable to store the current Radio channel. + Added missing FSK bit definition. + 4. Made fifo functions coding style coherent with the project. + 5. UART driver is now independent of the used MCU + +2014-03-28, v2.1.0 +* General + 1. The timers and RTC management has been rewritten. + 2. Improved the UART and UP501 GPS drivers. + 3. Corrected GPIO pin names management. + 4. Corrected the antenna switch management in the SX1272 driver. + 5. Added to the radio driver the possibility to choose the preamble length + and rxSingle symbol timeout in reception. + 6. Added Hex coder selector driver for the Bleeper board. + 7. Changed copyright Unicode character to (C) in all source files. + +* LoRaMac + 1. MAC commands implemented + * LinkCheckReq **YES** + * LinkCheckAns **YES** + * LinkADRReq **YES** + * LinkADRAns **YES** + * DevStatusReq **YES** + * DevStatusAns **YES** + * JoinReq **YES** + * JoinAccept **YES** + 2. Added acknowledgments retries management. + Split the LoRaMacSendOnChannel function in LoRaMacPrepareFrame and + LoRaMacSendFrameOnChannel. LoRaMacSendOnChannel now calls the 2 newly + defined functions. + + **WARNING**: By default the acknowledgment retries specific code isn't + enabled. The current http://iot.semtech.com server version doesn't support + it. + + 3. Corrected issues on JoinRequest and JoinAccept MAC commands. + Added LORAMAC_EVENT_INFO_STATUS_MAC_ERROR event info status. + +2014-02-21, v2.0.0 + +* General + 1. The LoRaMac applications now sends the LED status plus the sensors values. + For the LoRaMote platform the application also sends the GPS coordinates. + * The application payload for the Bleeper platform is as follows: + + LoRaMac port 1: + + { 0x00/0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } + ---------- ---------- ---------- ---------- ---- + | | | | | + LED PRESSURE TEMPERATURE ALTITUDE BATTERY + (barometric) + * The application payload for the LoRaMote platform is as follows: + + LoRaMac port 2: + + { 0x00/0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } + ---------- ---------- ---------- ---------- ---- ---------------- ---------------- ---------- + | | | | | | | | + LED PRESSURE TEMPERATURE ALTITUDE BATTERY LATITUDE LONGITUDE ALTITUDE + (barometric) (gps) + 2. Adapted applications to the new MAC layer API. + 3. Added sensors drivers implementation. + 4. Corrected new or known issues. +* LoRaMac + 1. MAC commands implemented + * LinkCheckReq **YES** + * LinkCheckAns **YES** + * LinkADRReq **YES** + * LinkADRAns **YES** + * DevStatusReq **YES** + * DevStatusAns **YES** + * JoinReq **YES (Not tested)** + * JoinAccept **YES (Not tested)** + 2. New MAC layer application API implementation. +* Timers and RTC. + 1. Still some issues. They will be corrected on next revisions of the firmware. + +2014-01-24, v1.1.0 + +* LoRaMac + 1. MAC commands implemented + * LinkCheckReq **NO** + * LinkCheckAns **NO** + * LinkADRReq **YES** + * LinkADRAns **YES** + * DevStatusReq **YES** + * DevStatusAns **YES** + 2. Implemented an application LED control + If the server sends on port 1 an application payload of one byte with + the following contents: + + 0: LED off + 1: LED on + The node transmits periodically on port 1 the LED status on 1st byte and + the message "Hello World!!!!" the array looks like: + + { 0, 'H', 'e', 'l', 'l', 'o', ' ', 'W', 'o', 'r', 'l', 'd', '!', '!', '!', '!' } +* Timers and RTC. + 1. Corrected issues existing in the previous version + 2. Known bugs are: + * There is an issue when launching an asynchronous Timer. Will be solved + in a future version + +2014-01-20, v1.1.RC1 + +* Added Doc directory. The directory contains: + 1. LoRa MAC specification + 2. Bleeper board schematic +* LoRaMac has been updated according to Release1 of the specification. Main changes are: + 1. MAC API changed. + 2. Frame format. + 3. ClassA first ADR implementation. + 4. MAC commands implemented + * LinkCheckReq **NO** + * LinkCheckAns **NO** + * LinkADRReq **YES** + * LinkADRAns **NO** + * DevStatusReq **NO** + * DevStatusAns **NO** + +* Timers and RTC rewriting. Known bugs are: + 1. The Radio wakeup time is taken in account for all timings. + 2. When opening the second reception window the microcontroller sometimes doesn't enter in low power mode. + +2013-11-28, v1.0.0 + +* Initial version of the LoRa MAC node firmware implementation. diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/aes.c b/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/aes.c new file mode 100644 index 00000000..cb309e71 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/aes.c @@ -0,0 +1,936 @@ +/* + --------------------------------------------------------------------------- + Copyright (c) 1998-2008, Brian Gladman, Worcester, UK. All rights reserved. + + LICENSE TERMS + + The redistribution and use of this software (with or without changes) + is allowed without the payment of fees or royalties provided that: + + 1. source code distributions include the above copyright notice, this + list of conditions and the following disclaimer; + + 2. binary distributions include the above copyright notice, this list + of conditions and the following disclaimer in their documentation; + + 3. the name of the copyright holder is not used to endorse products + built using this software without specific written permission. + + DISCLAIMER + + This software is provided 'as is' with no explicit or implied warranties + in respect of its properties, including, but not limited to, correctness + and/or fitness for purpose. + --------------------------------------------------------------------------- + Issue 09/09/2006 + + This is an AES implementation that uses only 8-bit byte operations on the + cipher state (there are options to use 32-bit types if available). + + The combination of mix columns and byte substitution used here is based on + that developed by Karl Malbrain. His contribution is acknowledged. + */ + +/* define if you have a fast memcpy function on your system */ +#if 0 +# define HAVE_MEMCPY +# include +# if defined( _MSC_VER ) +# include +# pragma intrinsic( memcpy ) +# endif +#endif + + +#include +#include + +/* define if you have fast 32-bit types on your system */ +#if 0 +# define HAVE_UINT_32T +#endif + +/* define if you don't want any tables */ +#if 1 +# define USE_TABLES +#endif + +/* On Intel Core 2 duo VERSION_1 is faster */ + +/* alternative versions (test for performance on your system) */ +#if 1 +# define VERSION_1 +#endif + +#include "aes.h" + +//#if defined( HAVE_UINT_32T ) +// typedef unsigned long uint32_t; +//#endif + +/* functions for finite field multiplication in the AES Galois field */ + +#define WPOLY 0x011b +#define BPOLY 0x1b +#define DPOLY 0x008d + +#define f1(x) (x) +#define f2(x) ((x << 1) ^ (((x >> 7) & 1) * WPOLY)) +#define f4(x) ((x << 2) ^ (((x >> 6) & 1) * WPOLY) ^ (((x >> 6) & 2) * WPOLY)) +#define f8(x) ((x << 3) ^ (((x >> 5) & 1) * WPOLY) ^ (((x >> 5) & 2) * WPOLY) \ + ^ (((x >> 5) & 4) * WPOLY)) +#define d2(x) (((x) >> 1) ^ ((x) & 1 ? DPOLY : 0)) + +#define f3(x) (f2(x) ^ x) +#define f9(x) (f8(x) ^ x) +#define fb(x) (f8(x) ^ f2(x) ^ x) +#define fd(x) (f8(x) ^ f4(x) ^ x) +#define fe(x) (f8(x) ^ f4(x) ^ f2(x)) + +#if defined( USE_TABLES ) + +#define sb_data(w) { /* S Box data values */ \ + w(0x63), w(0x7c), w(0x77), w(0x7b), w(0xf2), w(0x6b), w(0x6f), w(0xc5),\ + w(0x30), w(0x01), w(0x67), w(0x2b), w(0xfe), w(0xd7), w(0xab), w(0x76),\ + w(0xca), w(0x82), w(0xc9), w(0x7d), w(0xfa), w(0x59), w(0x47), w(0xf0),\ + w(0xad), w(0xd4), w(0xa2), w(0xaf), w(0x9c), w(0xa4), w(0x72), w(0xc0),\ + w(0xb7), w(0xfd), w(0x93), w(0x26), w(0x36), w(0x3f), w(0xf7), w(0xcc),\ + w(0x34), w(0xa5), w(0xe5), w(0xf1), w(0x71), w(0xd8), w(0x31), w(0x15),\ + w(0x04), w(0xc7), w(0x23), w(0xc3), w(0x18), w(0x96), w(0x05), w(0x9a),\ + w(0x07), w(0x12), w(0x80), w(0xe2), w(0xeb), w(0x27), w(0xb2), w(0x75),\ + w(0x09), w(0x83), w(0x2c), w(0x1a), w(0x1b), w(0x6e), w(0x5a), w(0xa0),\ + w(0x52), w(0x3b), w(0xd6), w(0xb3), w(0x29), w(0xe3), w(0x2f), w(0x84),\ + w(0x53), w(0xd1), w(0x00), w(0xed), w(0x20), w(0xfc), w(0xb1), w(0x5b),\ + w(0x6a), w(0xcb), w(0xbe), w(0x39), w(0x4a), w(0x4c), w(0x58), w(0xcf),\ + w(0xd0), w(0xef), w(0xaa), w(0xfb), w(0x43), w(0x4d), w(0x33), w(0x85),\ + w(0x45), w(0xf9), w(0x02), w(0x7f), w(0x50), w(0x3c), w(0x9f), w(0xa8),\ + w(0x51), w(0xa3), w(0x40), w(0x8f), w(0x92), w(0x9d), w(0x38), w(0xf5),\ + w(0xbc), w(0xb6), w(0xda), w(0x21), w(0x10), w(0xff), w(0xf3), w(0xd2),\ + w(0xcd), w(0x0c), w(0x13), w(0xec), w(0x5f), w(0x97), w(0x44), w(0x17),\ + w(0xc4), w(0xa7), w(0x7e), w(0x3d), w(0x64), w(0x5d), w(0x19), w(0x73),\ + w(0x60), w(0x81), w(0x4f), w(0xdc), w(0x22), w(0x2a), w(0x90), w(0x88),\ + w(0x46), w(0xee), w(0xb8), w(0x14), w(0xde), w(0x5e), w(0x0b), w(0xdb),\ + w(0xe0), w(0x32), w(0x3a), w(0x0a), w(0x49), w(0x06), w(0x24), w(0x5c),\ + w(0xc2), w(0xd3), w(0xac), w(0x62), w(0x91), w(0x95), w(0xe4), w(0x79),\ + w(0xe7), w(0xc8), w(0x37), w(0x6d), w(0x8d), w(0xd5), w(0x4e), w(0xa9),\ + w(0x6c), w(0x56), w(0xf4), w(0xea), w(0x65), w(0x7a), w(0xae), w(0x08),\ + w(0xba), w(0x78), w(0x25), w(0x2e), w(0x1c), w(0xa6), w(0xb4), w(0xc6),\ + w(0xe8), w(0xdd), w(0x74), w(0x1f), w(0x4b), w(0xbd), w(0x8b), w(0x8a),\ + w(0x70), w(0x3e), w(0xb5), w(0x66), w(0x48), w(0x03), w(0xf6), w(0x0e),\ + w(0x61), w(0x35), w(0x57), w(0xb9), w(0x86), w(0xc1), w(0x1d), w(0x9e),\ + w(0xe1), w(0xf8), w(0x98), w(0x11), w(0x69), w(0xd9), w(0x8e), w(0x94),\ + w(0x9b), w(0x1e), w(0x87), w(0xe9), w(0xce), w(0x55), w(0x28), w(0xdf),\ + w(0x8c), w(0xa1), w(0x89), w(0x0d), w(0xbf), w(0xe6), w(0x42), w(0x68),\ + w(0x41), w(0x99), w(0x2d), w(0x0f), w(0xb0), w(0x54), w(0xbb), w(0x16) } + +#define isb_data(w) { /* inverse S Box data values */ \ + w(0x52), w(0x09), w(0x6a), w(0xd5), w(0x30), w(0x36), w(0xa5), w(0x38),\ + w(0xbf), w(0x40), w(0xa3), w(0x9e), w(0x81), w(0xf3), w(0xd7), w(0xfb),\ + w(0x7c), w(0xe3), w(0x39), w(0x82), w(0x9b), w(0x2f), w(0xff), w(0x87),\ + w(0x34), w(0x8e), w(0x43), w(0x44), w(0xc4), w(0xde), w(0xe9), w(0xcb),\ + w(0x54), w(0x7b), w(0x94), w(0x32), w(0xa6), w(0xc2), w(0x23), w(0x3d),\ + w(0xee), w(0x4c), w(0x95), w(0x0b), w(0x42), w(0xfa), w(0xc3), w(0x4e),\ + w(0x08), w(0x2e), w(0xa1), w(0x66), w(0x28), w(0xd9), w(0x24), w(0xb2),\ + w(0x76), w(0x5b), w(0xa2), w(0x49), w(0x6d), w(0x8b), w(0xd1), w(0x25),\ + w(0x72), w(0xf8), w(0xf6), w(0x64), w(0x86), w(0x68), w(0x98), w(0x16),\ + w(0xd4), w(0xa4), w(0x5c), w(0xcc), w(0x5d), w(0x65), w(0xb6), w(0x92),\ + w(0x6c), w(0x70), w(0x48), w(0x50), w(0xfd), w(0xed), w(0xb9), w(0xda),\ + w(0x5e), w(0x15), w(0x46), w(0x57), w(0xa7), w(0x8d), w(0x9d), w(0x84),\ + w(0x90), w(0xd8), w(0xab), w(0x00), w(0x8c), w(0xbc), w(0xd3), w(0x0a),\ + w(0xf7), w(0xe4), w(0x58), w(0x05), w(0xb8), w(0xb3), w(0x45), w(0x06),\ + w(0xd0), w(0x2c), w(0x1e), w(0x8f), w(0xca), w(0x3f), w(0x0f), w(0x02),\ + w(0xc1), w(0xaf), w(0xbd), w(0x03), w(0x01), w(0x13), w(0x8a), w(0x6b),\ + w(0x3a), w(0x91), w(0x11), w(0x41), w(0x4f), w(0x67), w(0xdc), w(0xea),\ + w(0x97), w(0xf2), w(0xcf), w(0xce), w(0xf0), w(0xb4), w(0xe6), w(0x73),\ + w(0x96), w(0xac), w(0x74), w(0x22), w(0xe7), w(0xad), w(0x35), w(0x85),\ + w(0xe2), w(0xf9), w(0x37), w(0xe8), w(0x1c), w(0x75), w(0xdf), w(0x6e),\ + w(0x47), w(0xf1), w(0x1a), w(0x71), w(0x1d), w(0x29), w(0xc5), w(0x89),\ + w(0x6f), w(0xb7), w(0x62), w(0x0e), w(0xaa), w(0x18), w(0xbe), w(0x1b),\ + w(0xfc), w(0x56), w(0x3e), w(0x4b), w(0xc6), w(0xd2), w(0x79), w(0x20),\ + w(0x9a), w(0xdb), w(0xc0), w(0xfe), w(0x78), w(0xcd), w(0x5a), w(0xf4),\ + w(0x1f), w(0xdd), w(0xa8), w(0x33), w(0x88), w(0x07), w(0xc7), w(0x31),\ + w(0xb1), w(0x12), w(0x10), w(0x59), w(0x27), w(0x80), w(0xec), w(0x5f),\ + w(0x60), w(0x51), w(0x7f), w(0xa9), w(0x19), w(0xb5), w(0x4a), w(0x0d),\ + w(0x2d), w(0xe5), w(0x7a), w(0x9f), w(0x93), w(0xc9), w(0x9c), w(0xef),\ + w(0xa0), w(0xe0), w(0x3b), w(0x4d), w(0xae), w(0x2a), w(0xf5), w(0xb0),\ + w(0xc8), w(0xeb), w(0xbb), w(0x3c), w(0x83), w(0x53), w(0x99), w(0x61),\ + w(0x17), w(0x2b), w(0x04), w(0x7e), w(0xba), w(0x77), w(0xd6), w(0x26),\ + w(0xe1), w(0x69), w(0x14), w(0x63), w(0x55), w(0x21), w(0x0c), w(0x7d) } + +#define mm_data(w) { /* basic data for forming finite field tables */ \ + w(0x00), w(0x01), w(0x02), w(0x03), w(0x04), w(0x05), w(0x06), w(0x07),\ + w(0x08), w(0x09), w(0x0a), w(0x0b), w(0x0c), w(0x0d), w(0x0e), w(0x0f),\ + w(0x10), w(0x11), w(0x12), w(0x13), w(0x14), w(0x15), w(0x16), w(0x17),\ + w(0x18), w(0x19), w(0x1a), w(0x1b), w(0x1c), w(0x1d), w(0x1e), w(0x1f),\ + w(0x20), w(0x21), w(0x22), w(0x23), w(0x24), w(0x25), w(0x26), w(0x27),\ + w(0x28), w(0x29), w(0x2a), w(0x2b), w(0x2c), w(0x2d), w(0x2e), w(0x2f),\ + w(0x30), w(0x31), w(0x32), w(0x33), w(0x34), w(0x35), w(0x36), w(0x37),\ + w(0x38), w(0x39), w(0x3a), w(0x3b), w(0x3c), w(0x3d), w(0x3e), w(0x3f),\ + w(0x40), w(0x41), w(0x42), w(0x43), w(0x44), w(0x45), w(0x46), w(0x47),\ + w(0x48), w(0x49), w(0x4a), w(0x4b), w(0x4c), w(0x4d), w(0x4e), w(0x4f),\ + w(0x50), w(0x51), w(0x52), w(0x53), w(0x54), w(0x55), w(0x56), w(0x57),\ + w(0x58), w(0x59), w(0x5a), w(0x5b), w(0x5c), w(0x5d), w(0x5e), w(0x5f),\ + w(0x60), w(0x61), w(0x62), w(0x63), w(0x64), w(0x65), w(0x66), w(0x67),\ + w(0x68), w(0x69), w(0x6a), w(0x6b), w(0x6c), w(0x6d), w(0x6e), w(0x6f),\ + w(0x70), w(0x71), w(0x72), w(0x73), w(0x74), w(0x75), w(0x76), w(0x77),\ + w(0x78), w(0x79), w(0x7a), w(0x7b), w(0x7c), w(0x7d), w(0x7e), w(0x7f),\ + w(0x80), w(0x81), w(0x82), w(0x83), w(0x84), w(0x85), w(0x86), w(0x87),\ + w(0x88), w(0x89), w(0x8a), w(0x8b), w(0x8c), w(0x8d), w(0x8e), w(0x8f),\ + w(0x90), w(0x91), w(0x92), w(0x93), w(0x94), w(0x95), w(0x96), w(0x97),\ + w(0x98), w(0x99), w(0x9a), w(0x9b), w(0x9c), w(0x9d), w(0x9e), w(0x9f),\ + w(0xa0), w(0xa1), w(0xa2), w(0xa3), w(0xa4), w(0xa5), w(0xa6), w(0xa7),\ + w(0xa8), w(0xa9), w(0xaa), w(0xab), w(0xac), w(0xad), w(0xae), w(0xaf),\ + w(0xb0), w(0xb1), w(0xb2), w(0xb3), w(0xb4), w(0xb5), w(0xb6), w(0xb7),\ + w(0xb8), w(0xb9), w(0xba), w(0xbb), w(0xbc), w(0xbd), w(0xbe), w(0xbf),\ + w(0xc0), w(0xc1), w(0xc2), w(0xc3), w(0xc4), w(0xc5), w(0xc6), w(0xc7),\ + w(0xc8), w(0xc9), w(0xca), w(0xcb), w(0xcc), w(0xcd), w(0xce), w(0xcf),\ + w(0xd0), w(0xd1), w(0xd2), w(0xd3), w(0xd4), w(0xd5), w(0xd6), w(0xd7),\ + w(0xd8), w(0xd9), w(0xda), w(0xdb), w(0xdc), w(0xdd), w(0xde), w(0xdf),\ + w(0xe0), w(0xe1), w(0xe2), w(0xe3), w(0xe4), w(0xe5), w(0xe6), w(0xe7),\ + w(0xe8), w(0xe9), w(0xea), w(0xeb), w(0xec), w(0xed), w(0xee), w(0xef),\ + w(0xf0), w(0xf1), w(0xf2), w(0xf3), w(0xf4), w(0xf5), w(0xf6), w(0xf7),\ + w(0xf8), w(0xf9), w(0xfa), w(0xfb), w(0xfc), w(0xfd), w(0xfe), w(0xff) } + +static const uint8_t sbox[256] = sb_data(f1); + +#if defined( AES_DEC_PREKEYED ) +static const uint8_t isbox[256] = isb_data(f1); +#endif + +static const uint8_t gfm2_sbox[256] = sb_data(f2); +static const uint8_t gfm3_sbox[256] = sb_data(f3); + +#if defined( AES_DEC_PREKEYED ) +static const uint8_t gfmul_9[256] = mm_data(f9); +static const uint8_t gfmul_b[256] = mm_data(fb); +static const uint8_t gfmul_d[256] = mm_data(fd); +static const uint8_t gfmul_e[256] = mm_data(fe); +#endif + +#define s_box(x) sbox[(x)] +#if defined( AES_DEC_PREKEYED ) +#define is_box(x) isbox[(x)] +#endif +#define gfm2_sb(x) gfm2_sbox[(x)] +#define gfm3_sb(x) gfm3_sbox[(x)] +#if defined( AES_DEC_PREKEYED ) +#define gfm_9(x) gfmul_9[(x)] +#define gfm_b(x) gfmul_b[(x)] +#define gfm_d(x) gfmul_d[(x)] +#define gfm_e(x) gfmul_e[(x)] +#endif +#else + +/* this is the high bit of x right shifted by 1 */ +/* position. Since the starting polynomial has */ +/* 9 bits (0x11b), this right shift keeps the */ +/* values of all top bits within a byte */ + +static uint8_t hibit(const uint8_t x) +{ uint8_t r = (uint8_t)((x >> 1) | (x >> 2)); + + r |= (r >> 2); + r |= (r >> 4); + return (r + 1) >> 1; +} + +/* return the inverse of the finite field element x */ + +static uint8_t gf_inv(const uint8_t x) +{ uint8_t p1 = x, p2 = BPOLY, n1 = hibit(x), n2 = 0x80, v1 = 1, v2 = 0; + + if(x < 2) + return x; + + for( ; ; ) + { + if(n1) + while(n2 >= n1) /* divide polynomial p2 by p1 */ + { + n2 /= n1; /* shift smaller polynomial left */ + p2 ^= (p1 * n2) & 0xff; /* and remove from larger one */ + v2 ^= (v1 * n2); /* shift accumulated value and */ + n2 = hibit(p2); /* add into result */ + } + else + return v1; + + if(n2) /* repeat with values swapped */ + while(n1 >= n2) + { + n1 /= n2; + p1 ^= p2 * n1; + v1 ^= v2 * n1; + n1 = hibit(p1); + } + else + return v2; + } +} + +/* The forward and inverse affine transformations used in the S-box */ +uint8_t fwd_affine(const uint8_t x) +{ +#if defined( HAVE_UINT_32T ) + uint32_t w = x; + w ^= (w << 1) ^ (w << 2) ^ (w << 3) ^ (w << 4); + return 0x63 ^ ((w ^ (w >> 8)) & 0xff); +#else + return 0x63 ^ x ^ (x << 1) ^ (x << 2) ^ (x << 3) ^ (x << 4) + ^ (x >> 7) ^ (x >> 6) ^ (x >> 5) ^ (x >> 4); +#endif +} + +uint8_t inv_affine(const uint8_t x) +{ +#if defined( HAVE_UINT_32T ) + uint32_t w = x; + w = (w << 1) ^ (w << 3) ^ (w << 6); + return 0x05 ^ ((w ^ (w >> 8)) & 0xff); +#else + return 0x05 ^ (x << 1) ^ (x << 3) ^ (x << 6) + ^ (x >> 7) ^ (x >> 5) ^ (x >> 2); +#endif +} + +#define s_box(x) fwd_affine(gf_inv(x)) +#define is_box(x) gf_inv(inv_affine(x)) +#define gfm2_sb(x) f2(s_box(x)) +#define gfm3_sb(x) f3(s_box(x)) +#define gfm_9(x) f9(x) +#define gfm_b(x) fb(x) +#define gfm_d(x) fd(x) +#define gfm_e(x) fe(x) + +#endif + +#if defined( HAVE_MEMCPY ) +# define block_copy_nn(d, s, l) memcpy(d, s, l) +# define block_copy(d, s) memcpy(d, s, N_BLOCK) +#else +# define block_copy_nn(d, s, l) copy_block_nn(d, s, l) +# define block_copy(d, s) copy_block(d, s) +#endif + +static void copy_block( void *d, const void *s ) +{ +#if defined( HAVE_UINT_32T ) + ((uint32_t*)d)[ 0] = ((uint32_t*)s)[ 0]; + ((uint32_t*)d)[ 1] = ((uint32_t*)s)[ 1]; + ((uint32_t*)d)[ 2] = ((uint32_t*)s)[ 2]; + ((uint32_t*)d)[ 3] = ((uint32_t*)s)[ 3]; +#else + ((uint8_t*)d)[ 0] = ((uint8_t*)s)[ 0]; + ((uint8_t*)d)[ 1] = ((uint8_t*)s)[ 1]; + ((uint8_t*)d)[ 2] = ((uint8_t*)s)[ 2]; + ((uint8_t*)d)[ 3] = ((uint8_t*)s)[ 3]; + ((uint8_t*)d)[ 4] = ((uint8_t*)s)[ 4]; + ((uint8_t*)d)[ 5] = ((uint8_t*)s)[ 5]; + ((uint8_t*)d)[ 6] = ((uint8_t*)s)[ 6]; + ((uint8_t*)d)[ 7] = ((uint8_t*)s)[ 7]; + ((uint8_t*)d)[ 8] = ((uint8_t*)s)[ 8]; + ((uint8_t*)d)[ 9] = ((uint8_t*)s)[ 9]; + ((uint8_t*)d)[10] = ((uint8_t*)s)[10]; + ((uint8_t*)d)[11] = ((uint8_t*)s)[11]; + ((uint8_t*)d)[12] = ((uint8_t*)s)[12]; + ((uint8_t*)d)[13] = ((uint8_t*)s)[13]; + ((uint8_t*)d)[14] = ((uint8_t*)s)[14]; + ((uint8_t*)d)[15] = ((uint8_t*)s)[15]; +#endif +} + +static void copy_block_nn( uint8_t * d, const uint8_t *s, uint8_t nn ) +{ + while( nn-- ) + //*((uint8_t*)d)++ = *((uint8_t*)s)++; + *d++ = *s++; +} + +static void xor_block( void *d, const void *s ) +{ +#if defined( HAVE_UINT_32T ) + ((uint32_t*)d)[ 0] ^= ((uint32_t*)s)[ 0]; + ((uint32_t*)d)[ 1] ^= ((uint32_t*)s)[ 1]; + ((uint32_t*)d)[ 2] ^= ((uint32_t*)s)[ 2]; + ((uint32_t*)d)[ 3] ^= ((uint32_t*)s)[ 3]; +#else + ((uint8_t*)d)[ 0] ^= ((uint8_t*)s)[ 0]; + ((uint8_t*)d)[ 1] ^= ((uint8_t*)s)[ 1]; + ((uint8_t*)d)[ 2] ^= ((uint8_t*)s)[ 2]; + ((uint8_t*)d)[ 3] ^= ((uint8_t*)s)[ 3]; + ((uint8_t*)d)[ 4] ^= ((uint8_t*)s)[ 4]; + ((uint8_t*)d)[ 5] ^= ((uint8_t*)s)[ 5]; + ((uint8_t*)d)[ 6] ^= ((uint8_t*)s)[ 6]; + ((uint8_t*)d)[ 7] ^= ((uint8_t*)s)[ 7]; + ((uint8_t*)d)[ 8] ^= ((uint8_t*)s)[ 8]; + ((uint8_t*)d)[ 9] ^= ((uint8_t*)s)[ 9]; + ((uint8_t*)d)[10] ^= ((uint8_t*)s)[10]; + ((uint8_t*)d)[11] ^= ((uint8_t*)s)[11]; + ((uint8_t*)d)[12] ^= ((uint8_t*)s)[12]; + ((uint8_t*)d)[13] ^= ((uint8_t*)s)[13]; + ((uint8_t*)d)[14] ^= ((uint8_t*)s)[14]; + ((uint8_t*)d)[15] ^= ((uint8_t*)s)[15]; +#endif +} + +static void copy_and_key( void *d, const void *s, const void *k ) +{ +#if defined( HAVE_UINT_32T ) + ((uint32_t*)d)[ 0] = ((uint32_t*)s)[ 0] ^ ((uint32_t*)k)[ 0]; + ((uint32_t*)d)[ 1] = ((uint32_t*)s)[ 1] ^ ((uint32_t*)k)[ 1]; + ((uint32_t*)d)[ 2] = ((uint32_t*)s)[ 2] ^ ((uint32_t*)k)[ 2]; + ((uint32_t*)d)[ 3] = ((uint32_t*)s)[ 3] ^ ((uint32_t*)k)[ 3]; +#elif 1 + ((uint8_t*)d)[ 0] = ((uint8_t*)s)[ 0] ^ ((uint8_t*)k)[ 0]; + ((uint8_t*)d)[ 1] = ((uint8_t*)s)[ 1] ^ ((uint8_t*)k)[ 1]; + ((uint8_t*)d)[ 2] = ((uint8_t*)s)[ 2] ^ ((uint8_t*)k)[ 2]; + ((uint8_t*)d)[ 3] = ((uint8_t*)s)[ 3] ^ ((uint8_t*)k)[ 3]; + ((uint8_t*)d)[ 4] = ((uint8_t*)s)[ 4] ^ ((uint8_t*)k)[ 4]; + ((uint8_t*)d)[ 5] = ((uint8_t*)s)[ 5] ^ ((uint8_t*)k)[ 5]; + ((uint8_t*)d)[ 6] = ((uint8_t*)s)[ 6] ^ ((uint8_t*)k)[ 6]; + ((uint8_t*)d)[ 7] = ((uint8_t*)s)[ 7] ^ ((uint8_t*)k)[ 7]; + ((uint8_t*)d)[ 8] = ((uint8_t*)s)[ 8] ^ ((uint8_t*)k)[ 8]; + ((uint8_t*)d)[ 9] = ((uint8_t*)s)[ 9] ^ ((uint8_t*)k)[ 9]; + ((uint8_t*)d)[10] = ((uint8_t*)s)[10] ^ ((uint8_t*)k)[10]; + ((uint8_t*)d)[11] = ((uint8_t*)s)[11] ^ ((uint8_t*)k)[11]; + ((uint8_t*)d)[12] = ((uint8_t*)s)[12] ^ ((uint8_t*)k)[12]; + ((uint8_t*)d)[13] = ((uint8_t*)s)[13] ^ ((uint8_t*)k)[13]; + ((uint8_t*)d)[14] = ((uint8_t*)s)[14] ^ ((uint8_t*)k)[14]; + ((uint8_t*)d)[15] = ((uint8_t*)s)[15] ^ ((uint8_t*)k)[15]; +#else + block_copy(d, s); + xor_block(d, k); +#endif +} + +static void add_round_key( uint8_t d[N_BLOCK], const uint8_t k[N_BLOCK] ) +{ + xor_block(d, k); +} + +static void shift_sub_rows( uint8_t st[N_BLOCK] ) +{ uint8_t tt; + + st[ 0] = s_box(st[ 0]); st[ 4] = s_box(st[ 4]); + st[ 8] = s_box(st[ 8]); st[12] = s_box(st[12]); + + tt = st[1]; st[ 1] = s_box(st[ 5]); st[ 5] = s_box(st[ 9]); + st[ 9] = s_box(st[13]); st[13] = s_box( tt ); + + tt = st[2]; st[ 2] = s_box(st[10]); st[10] = s_box( tt ); + tt = st[6]; st[ 6] = s_box(st[14]); st[14] = s_box( tt ); + + tt = st[15]; st[15] = s_box(st[11]); st[11] = s_box(st[ 7]); + st[ 7] = s_box(st[ 3]); st[ 3] = s_box( tt ); +} + +#if defined( AES_DEC_PREKEYED ) + +static void inv_shift_sub_rows( uint8_t st[N_BLOCK] ) +{ uint8_t tt; + + st[ 0] = is_box(st[ 0]); st[ 4] = is_box(st[ 4]); + st[ 8] = is_box(st[ 8]); st[12] = is_box(st[12]); + + tt = st[13]; st[13] = is_box(st[9]); st[ 9] = is_box(st[5]); + st[ 5] = is_box(st[1]); st[ 1] = is_box( tt ); + + tt = st[2]; st[ 2] = is_box(st[10]); st[10] = is_box( tt ); + tt = st[6]; st[ 6] = is_box(st[14]); st[14] = is_box( tt ); + + tt = st[3]; st[ 3] = is_box(st[ 7]); st[ 7] = is_box(st[11]); + st[11] = is_box(st[15]); st[15] = is_box( tt ); +} + +#endif + +#if defined( VERSION_1 ) + static void mix_sub_columns( uint8_t dt[N_BLOCK] ) + { uint8_t st[N_BLOCK]; + block_copy(st, dt); +#else + static void mix_sub_columns( uint8_t dt[N_BLOCK], uint8_t st[N_BLOCK] ) + { +#endif + dt[ 0] = gfm2_sb(st[0]) ^ gfm3_sb(st[5]) ^ s_box(st[10]) ^ s_box(st[15]); + dt[ 1] = s_box(st[0]) ^ gfm2_sb(st[5]) ^ gfm3_sb(st[10]) ^ s_box(st[15]); + dt[ 2] = s_box(st[0]) ^ s_box(st[5]) ^ gfm2_sb(st[10]) ^ gfm3_sb(st[15]); + dt[ 3] = gfm3_sb(st[0]) ^ s_box(st[5]) ^ s_box(st[10]) ^ gfm2_sb(st[15]); + + dt[ 4] = gfm2_sb(st[4]) ^ gfm3_sb(st[9]) ^ s_box(st[14]) ^ s_box(st[3]); + dt[ 5] = s_box(st[4]) ^ gfm2_sb(st[9]) ^ gfm3_sb(st[14]) ^ s_box(st[3]); + dt[ 6] = s_box(st[4]) ^ s_box(st[9]) ^ gfm2_sb(st[14]) ^ gfm3_sb(st[3]); + dt[ 7] = gfm3_sb(st[4]) ^ s_box(st[9]) ^ s_box(st[14]) ^ gfm2_sb(st[3]); + + dt[ 8] = gfm2_sb(st[8]) ^ gfm3_sb(st[13]) ^ s_box(st[2]) ^ s_box(st[7]); + dt[ 9] = s_box(st[8]) ^ gfm2_sb(st[13]) ^ gfm3_sb(st[2]) ^ s_box(st[7]); + dt[10] = s_box(st[8]) ^ s_box(st[13]) ^ gfm2_sb(st[2]) ^ gfm3_sb(st[7]); + dt[11] = gfm3_sb(st[8]) ^ s_box(st[13]) ^ s_box(st[2]) ^ gfm2_sb(st[7]); + + dt[12] = gfm2_sb(st[12]) ^ gfm3_sb(st[1]) ^ s_box(st[6]) ^ s_box(st[11]); + dt[13] = s_box(st[12]) ^ gfm2_sb(st[1]) ^ gfm3_sb(st[6]) ^ s_box(st[11]); + dt[14] = s_box(st[12]) ^ s_box(st[1]) ^ gfm2_sb(st[6]) ^ gfm3_sb(st[11]); + dt[15] = gfm3_sb(st[12]) ^ s_box(st[1]) ^ s_box(st[6]) ^ gfm2_sb(st[11]); + } + +#if defined( AES_DEC_PREKEYED ) + +#if defined( VERSION_1 ) + static void inv_mix_sub_columns( uint8_t dt[N_BLOCK] ) + { uint8_t st[N_BLOCK]; + block_copy(st, dt); +#else + static void inv_mix_sub_columns( uint8_t dt[N_BLOCK], uint8_t st[N_BLOCK] ) + { +#endif + dt[ 0] = is_box(gfm_e(st[ 0]) ^ gfm_b(st[ 1]) ^ gfm_d(st[ 2]) ^ gfm_9(st[ 3])); + dt[ 5] = is_box(gfm_9(st[ 0]) ^ gfm_e(st[ 1]) ^ gfm_b(st[ 2]) ^ gfm_d(st[ 3])); + dt[10] = is_box(gfm_d(st[ 0]) ^ gfm_9(st[ 1]) ^ gfm_e(st[ 2]) ^ gfm_b(st[ 3])); + dt[15] = is_box(gfm_b(st[ 0]) ^ gfm_d(st[ 1]) ^ gfm_9(st[ 2]) ^ gfm_e(st[ 3])); + + dt[ 4] = is_box(gfm_e(st[ 4]) ^ gfm_b(st[ 5]) ^ gfm_d(st[ 6]) ^ gfm_9(st[ 7])); + dt[ 9] = is_box(gfm_9(st[ 4]) ^ gfm_e(st[ 5]) ^ gfm_b(st[ 6]) ^ gfm_d(st[ 7])); + dt[14] = is_box(gfm_d(st[ 4]) ^ gfm_9(st[ 5]) ^ gfm_e(st[ 6]) ^ gfm_b(st[ 7])); + dt[ 3] = is_box(gfm_b(st[ 4]) ^ gfm_d(st[ 5]) ^ gfm_9(st[ 6]) ^ gfm_e(st[ 7])); + + dt[ 8] = is_box(gfm_e(st[ 8]) ^ gfm_b(st[ 9]) ^ gfm_d(st[10]) ^ gfm_9(st[11])); + dt[13] = is_box(gfm_9(st[ 8]) ^ gfm_e(st[ 9]) ^ gfm_b(st[10]) ^ gfm_d(st[11])); + dt[ 2] = is_box(gfm_d(st[ 8]) ^ gfm_9(st[ 9]) ^ gfm_e(st[10]) ^ gfm_b(st[11])); + dt[ 7] = is_box(gfm_b(st[ 8]) ^ gfm_d(st[ 9]) ^ gfm_9(st[10]) ^ gfm_e(st[11])); + + dt[12] = is_box(gfm_e(st[12]) ^ gfm_b(st[13]) ^ gfm_d(st[14]) ^ gfm_9(st[15])); + dt[ 1] = is_box(gfm_9(st[12]) ^ gfm_e(st[13]) ^ gfm_b(st[14]) ^ gfm_d(st[15])); + dt[ 6] = is_box(gfm_d(st[12]) ^ gfm_9(st[13]) ^ gfm_e(st[14]) ^ gfm_b(st[15])); + dt[11] = is_box(gfm_b(st[12]) ^ gfm_d(st[13]) ^ gfm_9(st[14]) ^ gfm_e(st[15])); + } + +#endif + +#if defined( AES_ENC_PREKEYED ) || defined( AES_DEC_PREKEYED ) + +/* Set the cipher key for the pre-keyed version */ + +return_type aes_set_key( const uint8_t key[], length_type keylen, aes_context ctx[1] ) +{ + uint8_t cc, rc, hi; + + switch( keylen ) + { + case 16: + case 24: + case 32: + break; + default: + ctx->rnd = 0; + return ( uint8_t )-1; + } + block_copy_nn(ctx->ksch, key, keylen); + hi = (keylen + 28) << 2; + ctx->rnd = (hi >> 4) - 1; + for( cc = keylen, rc = 1; cc < hi; cc += 4 ) + { uint8_t tt, t0, t1, t2, t3; + + t0 = ctx->ksch[cc - 4]; + t1 = ctx->ksch[cc - 3]; + t2 = ctx->ksch[cc - 2]; + t3 = ctx->ksch[cc - 1]; + if( cc % keylen == 0 ) + { + tt = t0; + t0 = s_box(t1) ^ rc; + t1 = s_box(t2); + t2 = s_box(t3); + t3 = s_box(tt); + rc = f2(rc); + } + else if( keylen > 24 && cc % keylen == 16 ) + { + t0 = s_box(t0); + t1 = s_box(t1); + t2 = s_box(t2); + t3 = s_box(t3); + } + tt = cc - keylen; + ctx->ksch[cc + 0] = ctx->ksch[tt + 0] ^ t0; + ctx->ksch[cc + 1] = ctx->ksch[tt + 1] ^ t1; + ctx->ksch[cc + 2] = ctx->ksch[tt + 2] ^ t2; + ctx->ksch[cc + 3] = ctx->ksch[tt + 3] ^ t3; + } + return 0; +} + +#endif + +#if defined( AES_ENC_PREKEYED ) + +/* Encrypt a single block of 16 bytes */ + +return_type aes_encrypt( const uint8_t in[N_BLOCK], uint8_t out[N_BLOCK], const aes_context ctx[1] ) +{ + if( ctx->rnd ) + { + uint8_t s1[N_BLOCK], r; + copy_and_key( s1, in, ctx->ksch ); + + for( r = 1 ; r < ctx->rnd ; ++r ) +#if defined( VERSION_1 ) + { + mix_sub_columns( s1 ); + add_round_key( s1, ctx->ksch + r * N_BLOCK); + } +#else + { uint8_t s2[N_BLOCK]; + mix_sub_columns( s2, s1 ); + copy_and_key( s1, s2, ctx->ksch + r * N_BLOCK); + } +#endif + shift_sub_rows( s1 ); + copy_and_key( out, s1, ctx->ksch + r * N_BLOCK ); + } + else + return ( uint8_t )-1; + return 0; +} + +/* CBC encrypt a number of blocks (input and return an IV) */ + +return_type aes_cbc_encrypt( const uint8_t *in, uint8_t *out, + int32_t n_block, uint8_t iv[N_BLOCK], const aes_context ctx[1] ) +{ + + while(n_block--) + { + xor_block(iv, in); + if(aes_encrypt(iv, iv, ctx) != EXIT_SUCCESS) + return EXIT_FAILURE; + //memcpy(out, iv, N_BLOCK); + block_copy(out, iv); + in += N_BLOCK; + out += N_BLOCK; + } + return EXIT_SUCCESS; +} + +#endif + +#if defined( AES_DEC_PREKEYED ) + +/* Decrypt a single block of 16 bytes */ + +return_type aes_decrypt( const uint8_t in[N_BLOCK], uint8_t out[N_BLOCK], const aes_context ctx[1] ) +{ + if( ctx->rnd ) + { + uint8_t s1[N_BLOCK], r; + copy_and_key( s1, in, ctx->ksch + ctx->rnd * N_BLOCK ); + inv_shift_sub_rows( s1 ); + + for( r = ctx->rnd ; --r ; ) +#if defined( VERSION_1 ) + { + add_round_key( s1, ctx->ksch + r * N_BLOCK ); + inv_mix_sub_columns( s1 ); + } +#else + { uint8_t s2[N_BLOCK]; + copy_and_key( s2, s1, ctx->ksch + r * N_BLOCK ); + inv_mix_sub_columns( s1, s2 ); + } +#endif + copy_and_key( out, s1, ctx->ksch ); + } + else + return -1; + return 0; +} + +/* CBC decrypt a number of blocks (input and return an IV) */ + +return_type aes_cbc_decrypt( const uint8_t *in, uint8_t *out, + int32_t n_block, uint8_t iv[N_BLOCK], const aes_context ctx[1] ) +{ + while(n_block--) + { uint8_t tmp[N_BLOCK]; + + //memcpy(tmp, in, N_BLOCK); + block_copy(tmp, in); + if(aes_decrypt(in, out, ctx) != EXIT_SUCCESS) + return EXIT_FAILURE; + xor_block(out, iv); + //memcpy(iv, tmp, N_BLOCK); + block_copy(iv, tmp); + in += N_BLOCK; + out += N_BLOCK; + } + return EXIT_SUCCESS; +} + +#endif + +#if defined( AES_ENC_128_OTFK ) + +/* The 'on the fly' encryption key update for for 128 bit keys */ + +static void update_encrypt_key_128( uint8_t k[N_BLOCK], uint8_t *rc ) +{ uint8_t cc; + + k[0] ^= s_box(k[13]) ^ *rc; + k[1] ^= s_box(k[14]); + k[2] ^= s_box(k[15]); + k[3] ^= s_box(k[12]); + *rc = f2( *rc ); + + for(cc = 4; cc < 16; cc += 4 ) + { + k[cc + 0] ^= k[cc - 4]; + k[cc + 1] ^= k[cc - 3]; + k[cc + 2] ^= k[cc - 2]; + k[cc + 3] ^= k[cc - 1]; + } +} + +/* Encrypt a single block of 16 bytes with 'on the fly' 128 bit keying */ + +void aes_encrypt_128( const uint8_t in[N_BLOCK], uint8_t out[N_BLOCK], + const uint8_t key[N_BLOCK], uint8_t o_key[N_BLOCK] ) +{ uint8_t s1[N_BLOCK], r, rc = 1; + + if(o_key != key) + block_copy( o_key, key ); + copy_and_key( s1, in, o_key ); + + for( r = 1 ; r < 10 ; ++r ) +#if defined( VERSION_1 ) + { + mix_sub_columns( s1 ); + update_encrypt_key_128( o_key, &rc ); + add_round_key( s1, o_key ); + } +#else + { uint8_t s2[N_BLOCK]; + mix_sub_columns( s2, s1 ); + update_encrypt_key_128( o_key, &rc ); + copy_and_key( s1, s2, o_key ); + } +#endif + + shift_sub_rows( s1 ); + update_encrypt_key_128( o_key, &rc ); + copy_and_key( out, s1, o_key ); +} + +#endif + +#if defined( AES_DEC_128_OTFK ) + +/* The 'on the fly' decryption key update for for 128 bit keys */ + +static void update_decrypt_key_128( uint8_t k[N_BLOCK], uint8_t *rc ) +{ uint8_t cc; + + for( cc = 12; cc > 0; cc -= 4 ) + { + k[cc + 0] ^= k[cc - 4]; + k[cc + 1] ^= k[cc - 3]; + k[cc + 2] ^= k[cc - 2]; + k[cc + 3] ^= k[cc - 1]; + } + *rc = d2(*rc); + k[0] ^= s_box(k[13]) ^ *rc; + k[1] ^= s_box(k[14]); + k[2] ^= s_box(k[15]); + k[3] ^= s_box(k[12]); +} + +/* Decrypt a single block of 16 bytes with 'on the fly' 128 bit keying */ + +void aes_decrypt_128( const uint8_t in[N_BLOCK], uint8_t out[N_BLOCK], + const uint8_t key[N_BLOCK], uint8_t o_key[N_BLOCK] ) +{ + uint8_t s1[N_BLOCK], r, rc = 0x6c; + if(o_key != key) + block_copy( o_key, key ); + + copy_and_key( s1, in, o_key ); + inv_shift_sub_rows( s1 ); + + for( r = 10 ; --r ; ) +#if defined( VERSION_1 ) + { + update_decrypt_key_128( o_key, &rc ); + add_round_key( s1, o_key ); + inv_mix_sub_columns( s1 ); + } +#else + { uint8_t s2[N_BLOCK]; + update_decrypt_key_128( o_key, &rc ); + copy_and_key( s2, s1, o_key ); + inv_mix_sub_columns( s1, s2 ); + } +#endif + update_decrypt_key_128( o_key, &rc ); + copy_and_key( out, s1, o_key ); +} + +#endif + +#if defined( AES_ENC_256_OTFK ) + +/* The 'on the fly' encryption key update for for 256 bit keys */ + +static void update_encrypt_key_256( uint8_t k[2 * N_BLOCK], uint8_t *rc ) +{ uint8_t cc; + + k[0] ^= s_box(k[29]) ^ *rc; + k[1] ^= s_box(k[30]); + k[2] ^= s_box(k[31]); + k[3] ^= s_box(k[28]); + *rc = f2( *rc ); + + for(cc = 4; cc < 16; cc += 4) + { + k[cc + 0] ^= k[cc - 4]; + k[cc + 1] ^= k[cc - 3]; + k[cc + 2] ^= k[cc - 2]; + k[cc + 3] ^= k[cc - 1]; + } + + k[16] ^= s_box(k[12]); + k[17] ^= s_box(k[13]); + k[18] ^= s_box(k[14]); + k[19] ^= s_box(k[15]); + + for( cc = 20; cc < 32; cc += 4 ) + { + k[cc + 0] ^= k[cc - 4]; + k[cc + 1] ^= k[cc - 3]; + k[cc + 2] ^= k[cc - 2]; + k[cc + 3] ^= k[cc - 1]; + } +} + +/* Encrypt a single block of 16 bytes with 'on the fly' 256 bit keying */ + +void aes_encrypt_256( const uint8_t in[N_BLOCK], uint8_t out[N_BLOCK], + const uint8_t key[2 * N_BLOCK], uint8_t o_key[2 * N_BLOCK] ) +{ + uint8_t s1[N_BLOCK], r, rc = 1; + if(o_key != key) + { + block_copy( o_key, key ); + block_copy( o_key + 16, key + 16 ); + } + copy_and_key( s1, in, o_key ); + + for( r = 1 ; r < 14 ; ++r ) +#if defined( VERSION_1 ) + { + mix_sub_columns(s1); + if( r & 1 ) + add_round_key( s1, o_key + 16 ); + else + { + update_encrypt_key_256( o_key, &rc ); + add_round_key( s1, o_key ); + } + } +#else + { uint8_t s2[N_BLOCK]; + mix_sub_columns( s2, s1 ); + if( r & 1 ) + copy_and_key( s1, s2, o_key + 16 ); + else + { + update_encrypt_key_256( o_key, &rc ); + copy_and_key( s1, s2, o_key ); + } + } +#endif + + shift_sub_rows( s1 ); + update_encrypt_key_256( o_key, &rc ); + copy_and_key( out, s1, o_key ); +} + +#endif + +#if defined( AES_DEC_256_OTFK ) + +/* The 'on the fly' encryption key update for for 256 bit keys */ + +static void update_decrypt_key_256( uint8_t k[2 * N_BLOCK], uint8_t *rc ) +{ uint8_t cc; + + for(cc = 28; cc > 16; cc -= 4) + { + k[cc + 0] ^= k[cc - 4]; + k[cc + 1] ^= k[cc - 3]; + k[cc + 2] ^= k[cc - 2]; + k[cc + 3] ^= k[cc - 1]; + } + + k[16] ^= s_box(k[12]); + k[17] ^= s_box(k[13]); + k[18] ^= s_box(k[14]); + k[19] ^= s_box(k[15]); + + for(cc = 12; cc > 0; cc -= 4) + { + k[cc + 0] ^= k[cc - 4]; + k[cc + 1] ^= k[cc - 3]; + k[cc + 2] ^= k[cc - 2]; + k[cc + 3] ^= k[cc - 1]; + } + + *rc = d2(*rc); + k[0] ^= s_box(k[29]) ^ *rc; + k[1] ^= s_box(k[30]); + k[2] ^= s_box(k[31]); + k[3] ^= s_box(k[28]); +} + +/* Decrypt a single block of 16 bytes with 'on the fly' + 256 bit keying +*/ +void aes_decrypt_256( const uint8_t in[N_BLOCK], uint8_t out[N_BLOCK], + const uint8_t key[2 * N_BLOCK], uint8_t o_key[2 * N_BLOCK] ) +{ + uint8_t s1[N_BLOCK], r, rc = 0x80; + + if(o_key != key) + { + block_copy( o_key, key ); + block_copy( o_key + 16, key + 16 ); + } + + copy_and_key( s1, in, o_key ); + inv_shift_sub_rows( s1 ); + + for( r = 14 ; --r ; ) +#if defined( VERSION_1 ) + { + if( ( r & 1 ) ) + { + update_decrypt_key_256( o_key, &rc ); + add_round_key( s1, o_key + 16 ); + } + else + add_round_key( s1, o_key ); + inv_mix_sub_columns( s1 ); + } +#else + { uint8_t s2[N_BLOCK]; + if( ( r & 1 ) ) + { + update_decrypt_key_256( o_key, &rc ); + copy_and_key( s2, s1, o_key + 16 ); + } + else + copy_and_key( s2, s1, o_key ); + inv_mix_sub_columns( s1, s2 ); + } +#endif + copy_and_key( out, s1, o_key ); +} + +#endif diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/aes.h b/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/aes.h new file mode 100644 index 00000000..7203db53 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/aes.h @@ -0,0 +1,160 @@ +/* + --------------------------------------------------------------------------- + Copyright (c) 1998-2008, Brian Gladman, Worcester, UK. All rights reserved. + + LICENSE TERMS + + The redistribution and use of this software (with or without changes) + is allowed without the payment of fees or royalties provided that: + + 1. source code distributions include the above copyright notice, this + list of conditions and the following disclaimer; + + 2. binary distributions include the above copyright notice, this list + of conditions and the following disclaimer in their documentation; + + 3. the name of the copyright holder is not used to endorse products + built using this software without specific written permission. + + DISCLAIMER + + This software is provided 'as is' with no explicit or implied warranties + in respect of its properties, including, but not limited to, correctness + and/or fitness for purpose. + --------------------------------------------------------------------------- + Issue 09/09/2006 + + This is an AES implementation that uses only 8-bit byte operations on the + cipher state. + */ + +#ifndef AES_H +#define AES_H + +#if 1 +# define AES_ENC_PREKEYED /* AES encryption with a precomputed key schedule */ +#endif +#if 0 +# define AES_DEC_PREKEYED /* AES decryption with a precomputed key schedule */ +#endif +#if 0 +# define AES_ENC_128_OTFK /* AES encryption with 'on the fly' 128 bit keying */ +#endif +#if 0 +# define AES_DEC_128_OTFK /* AES decryption with 'on the fly' 128 bit keying */ +#endif +#if 0 +# define AES_ENC_256_OTFK /* AES encryption with 'on the fly' 256 bit keying */ +#endif +#if 0 +# define AES_DEC_256_OTFK /* AES decryption with 'on the fly' 256 bit keying */ +#endif + +#define N_ROW 4 +#define N_COL 4 +#define N_BLOCK (N_ROW * N_COL) +#define N_MAX_ROUNDS 14 + +typedef uint8_t return_type; + +/* Warning: The key length for 256 bit keys overflows a byte + (see comment below) +*/ + +typedef uint8_t length_type; + +typedef struct +{ uint8_t ksch[(N_MAX_ROUNDS + 1) * N_BLOCK]; + uint8_t rnd; +} aes_context; + +/* The following calls are for a precomputed key schedule + + NOTE: If the length_type used for the key length is an + unsigned 8-bit character, a key length of 256 bits must + be entered as a length in bytes (valid inputs are hence + 128, 192, 16, 24 and 32). +*/ + +#if defined( AES_ENC_PREKEYED ) || defined( AES_DEC_PREKEYED ) + +return_type aes_set_key( const uint8_t key[], + length_type keylen, + aes_context ctx[1] ); +#endif + +#if defined( AES_ENC_PREKEYED ) + +return_type aes_encrypt( const uint8_t in[N_BLOCK], + uint8_t out[N_BLOCK], + const aes_context ctx[1] ); + +return_type aes_cbc_encrypt( const uint8_t *in, + uint8_t *out, + int32_t n_block, + uint8_t iv[N_BLOCK], + const aes_context ctx[1] ); +#endif + +#if defined( AES_DEC_PREKEYED ) + +return_type aes_decrypt( const uint8_t in[N_BLOCK], + uint8_t out[N_BLOCK], + const aes_context ctx[1] ); + +return_type aes_cbc_decrypt( const uint8_t *in, + uint8_t *out, + int32_t n_block, + uint8_t iv[N_BLOCK], + const aes_context ctx[1] ); +#endif + +/* The following calls are for 'on the fly' keying. In this case the + encryption and decryption keys are different. + + The encryption subroutines take a key in an array of bytes in + key[L] where L is 16, 24 or 32 bytes for key lengths of 128, + 192, and 256 bits respectively. They then encrypts the input + data, in[] with this key and put the reult in the output array + out[]. In addition, the second key array, o_key[L], is used + to output the key that is needed by the decryption subroutine + to reverse the encryption operation. The two key arrays can + be the same array but in this case the original key will be + overwritten. + + In the same way, the decryption subroutines output keys that + can be used to reverse their effect when used for encryption. + + Only 128 and 256 bit keys are supported in these 'on the fly' + modes. +*/ + +#if defined( AES_ENC_128_OTFK ) +void aes_encrypt_128( const uint8_t in[N_BLOCK], + uint8_t out[N_BLOCK], + const uint8_t key[N_BLOCK], + uint8_t o_key[N_BLOCK] ); +#endif + +#if defined( AES_DEC_128_OTFK ) +void aes_decrypt_128( const uint8_t in[N_BLOCK], + uint8_t out[N_BLOCK], + const uint8_t key[N_BLOCK], + uint8_t o_key[N_BLOCK] ); +#endif + +#if defined( AES_ENC_256_OTFK ) +void aes_encrypt_256( const uint8_t in[N_BLOCK], + uint8_t out[N_BLOCK], + const uint8_t key[2 * N_BLOCK], + uint8_t o_key[2 * N_BLOCK] ); +#endif + +#if defined( AES_DEC_256_OTFK ) +void aes_decrypt_256( const uint8_t in[N_BLOCK], + uint8_t out[N_BLOCK], + const uint8_t key[2 * N_BLOCK], + uint8_t o_key[2 * N_BLOCK] ); +#endif + +#endif diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/cmac.c b/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/cmac.c new file mode 100644 index 00000000..9ea1a42b --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/cmac.c @@ -0,0 +1,153 @@ +/************************************************************************** +Copyright (C) 2009 Lander Casado, Philippas Tsigas + +All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files +(the "Software"), to deal with the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +Redistributions of source code must retain the above copyright notice, +this list of conditions and the following disclaimers. Redistributions in +binary form must reproduce the above copyright notice, this list of +conditions and the following disclaimers in the documentation and/or +other materials provided with the distribution. + +In no event shall the authors or copyright holders be liable for any special, +incidental, indirect or consequential damages of any kind, or any damages +whatsoever resulting from loss of use, data or profits, whether or not +advised of the possibility of damage, and on any theory of liability, +arising out of or in connection with the use or performance of this software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS WITH THE SOFTWARE + +*****************************************************************************/ +//#include +//#include +#include +#include "aes.h" +#include "cmac.h" +#include "utilities.h" + +#define LSHIFT(v, r) do { \ + int32_t i; \ + for (i = 0; i < 15; i++) \ + (r)[i] = (v)[i] << 1 | (v)[i + 1] >> 7; \ + (r)[15] = (v)[15] << 1; \ + } while (0) + +#define XOR(v, r) do { \ + int32_t i; \ + for (i = 0; i < 16; i++) \ + { \ + (r)[i] = (r)[i] ^ (v)[i]; \ + } \ + } while (0) \ + + +void AES_CMAC_Init(AES_CMAC_CTX *ctx) +{ + memset1(ctx->X, 0, sizeof ctx->X); + ctx->M_n = 0; + memset1(ctx->rijndael.ksch, '\0', 240); +} + +void AES_CMAC_SetKey(AES_CMAC_CTX *ctx, const uint8_t key[AES_CMAC_KEY_LENGTH]) +{ + //rijndael_set_key_enc_only(&ctx->rijndael, key, 128); + aes_set_key( key, AES_CMAC_KEY_LENGTH, &ctx->rijndael); +} + +void AES_CMAC_Update(AES_CMAC_CTX *ctx, const uint8_t *data, uint32_t len) +{ + uint32_t mlen; + uint8_t in[16]; + + if (ctx->M_n > 0) { + mlen = MIN(16 - ctx->M_n, len); + memcpy1(ctx->M_last + ctx->M_n, data, mlen); + ctx->M_n += mlen; + if (ctx->M_n < 16 || len == mlen) + return; + XOR(ctx->M_last, ctx->X); + //rijndael_encrypt(&ctx->rijndael, ctx->X, ctx->X); + aes_encrypt( ctx->X, ctx->X, &ctx->rijndael); + data += mlen; + len -= mlen; + } + while (len > 16) { /* not last block */ + + XOR(data, ctx->X); + //rijndael_encrypt(&ctx->rijndael, ctx->X, ctx->X); + + memcpy1(in, &ctx->X[0], 16); //Bestela ez du ondo iten + aes_encrypt( in, in, &ctx->rijndael); + memcpy1(&ctx->X[0], in, 16); + + data += 16; + len -= 16; + } + /* potential last block, save it */ + memcpy1(ctx->M_last, data, len); + ctx->M_n = len; +} + +void AES_CMAC_Final(uint8_t digest[AES_CMAC_DIGEST_LENGTH], AES_CMAC_CTX *ctx) +{ + uint8_t K[16]; + uint8_t in[16]; + /* generate subkey K1 */ + memset1(K, '\0', 16); + + //rijndael_encrypt(&ctx->rijndael, K, K); + + aes_encrypt( K, K, &ctx->rijndael); + + if (K[0] & 0x80) { + LSHIFT(K, K); + K[15] ^= 0x87; + } else + LSHIFT(K, K); + + + if (ctx->M_n == 16) { + /* last block was a complete block */ + XOR(K, ctx->M_last); + + } else { + /* generate subkey K2 */ + if (K[0] & 0x80) { + LSHIFT(K, K); + K[15] ^= 0x87; + } else + LSHIFT(K, K); + + /* padding(M_last) */ + ctx->M_last[ctx->M_n] = 0x80; + while (++ctx->M_n < 16) + ctx->M_last[ctx->M_n] = 0; + + XOR(K, ctx->M_last); + + + } + XOR(ctx->M_last, ctx->X); + + //rijndael_encrypt(&ctx->rijndael, ctx->X, digest); + + memcpy1(in, &ctx->X[0], 16); //Bestela ez du ondo iten + aes_encrypt(in, digest, &ctx->rijndael); + memset1(K, 0, sizeof K); + +} + diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/cmac.h b/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/cmac.h new file mode 100644 index 00000000..5ad7c582 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/crypto/cmac.h @@ -0,0 +1,63 @@ +/************************************************************************** +Copyright (C) 2009 Lander Casado, Philippas Tsigas + +All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files +(the "Software"), to deal with the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +Redistributions of source code must retain the above copyright notice, +this list of conditions and the following disclaimers. Redistributions in +binary form must reproduce the above copyright notice, this list of +conditions and the following disclaimers in the documentation and/or +other materials provided with the distribution. + +In no event shall the authors or copyright holders be liable for any special, +incidental, indirect or consequential damages of any kind, or any damages +whatsoever resulting from loss of use, data or profits, whether or not +advised of the possibility of damage, and on any theory of liability, +arising out of or in connection with the use or performance of this software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS WITH THE SOFTWARE + +*****************************************************************************/ + +#ifndef _CMAC_H_ +#define _CMAC_H_ + +#include "aes.h" + +#define AES_CMAC_KEY_LENGTH 16 +#define AES_CMAC_DIGEST_LENGTH 16 + +typedef struct _AES_CMAC_CTX { + uint32_t M_n; + uint8_t X[16]; + uint8_t M_last[16]; + aes_context rijndael; + } AES_CMAC_CTX; + +//#include + +//__BEGIN_DECLS +void AES_CMAC_Init(AES_CMAC_CTX * ctx); +void AES_CMAC_SetKey(AES_CMAC_CTX * ctx, const uint8_t key[AES_CMAC_KEY_LENGTH]); +void AES_CMAC_Update(AES_CMAC_CTX * ctx, const uint8_t * data, uint32_t len); + // __attribute__((__bounded__(__string__,2,3))); +void AES_CMAC_Final(uint8_t digest[AES_CMAC_DIGEST_LENGTH], AES_CMAC_CTX * ctx); + // __attribute__((__bounded__(__minbytes__,1,AES_CMAC_DIGEST_LENGTH))); +//__END_DECLS + +#endif /* _CMAC_H_ */ + diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/delay.c b/cores/asr650x/kernel/protocols/lorawan/lora/system/delay.c new file mode 100644 index 00000000..7b48a092 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/delay.c @@ -0,0 +1,77 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + +Description: Delay functions implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian +*/ +/****************************************************************************** + * @file delay.c + * @author MCD Application Team + * @version V1.1.1 + * @date 01-June-2017 + * @brief Delay function + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics International N.V. + * All rights reserved.

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "hw.h" +#include "timeServer.h" +#include "lorawan_port.h" + +void DelayMs( uint32_t ms ) +{ + aos_lrwan_time_itf.delay_ms(ms); +} + +void Delay( float s ) +{ + DelayMs( (uint32_t) (s * 1000.0f) ); +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/delay.h b/cores/asr650x/kernel/protocols/lorawan/lora/system/delay.h new file mode 100644 index 00000000..2b266e28 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/delay.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + +Description: Delay functions implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian +*/ +#ifndef __DELAY_H__ +#define __DELAY_H__ + +/*! + * Blocking delay of "s" seconds + */ +void Delay( float s ); + +/*! + * Blocking delay of "ms" milliseconds + */ +void DelayMs( uint32_t ms ); + +#endif // __DELAY_H__ + diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/low_power.c b/cores/asr650x/kernel/protocols/lorawan/lora/system/low_power.c new file mode 100644 index 00000000..c3724c53 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/low_power.c @@ -0,0 +1,133 @@ + /******************************************************************************* + * @file low_power.c + * @author MCD Application Team + * @version V1.1.1 + * @date 01-June-2017 + * @brief driver for low power + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics International N.V. + * All rights reserved.

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "hw.h" +#include "low_power.h" +#include "lorawan_port.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** + * \brief Flag to indicate if MCU can go to low power mode + * When 0, MCU is authorized to go in low power mode + */ +static uint32_t LowPower_State = 0; + +/* Private function prototypes -----------------------------------------------*/ +extern bool WakeByUart; + + + +/* Exported functions ---------------------------------------------------------*/ + +/** + * \brief API to set flag allowing power mode + * + * \param [IN] enum e_LOW_POWER_State_Id_t + */ +void LowPower_Disable( e_LOW_POWER_State_Id_t state ) +{ + CPSR_ALLOC(); + RHINO_CPU_INTRPT_DISABLE(); + LowPower_State |= state; + RHINO_CPU_INTRPT_ENABLE(); +} + +/** + * \brief API to reset flag allowing power mode + * + * \param [IN] enum e_LOW_POWER_State_Id_t + */ +void LowPower_Enable( e_LOW_POWER_State_Id_t state ) +{ + CPSR_ALLOC(); + RHINO_CPU_INTRPT_DISABLE(); + LowPower_State &= ~state; + RHINO_CPU_INTRPT_ENABLE(); +} + +/** + * \brief API to get flag allowing power mode + * \note When flag is 0, low power mode is allowed + * \param [IN] state + * \retval flag state + */ +uint32_t LowPower_GetState( void ) +{ + return LowPower_State; +} + +/** + * @brief Handle Low Power + * @param None + * @retval None + */ +void LowPower_Handler( void ) +{ + CPSR_ALLOC(); + RHINO_CPU_INTRPT_DISABLE(); + if (LowPower_State == 0 && WakeByUart == false) { +// printf("s"); + DBG_PRINTF_CRITICAL("dz\n\r"); + aos_lrwan_chg_mode.enter_stop_mode(); + /* mcu dependent. to be implemented by user*/ + aos_lrwan_chg_mode.exit_stop_mode(); + aos_lrwan_time_itf.set_uc_wakeup_time(); + } else { + //printf("L"); + //DBG_PRINTF_CRITICAL("z\n\r"); + aos_lrwan_chg_mode.enter_sleep_mode(); + } + + RHINO_CPU_INTRPT_ENABLE(); +} +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/low_power.h b/cores/asr650x/kernel/protocols/lorawan/lora/system/low_power.h new file mode 100644 index 00000000..acd8ee7e --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/low_power.h @@ -0,0 +1,98 @@ + /****************************************************************************** + * @file low_power.h + * @author MCD Application Team + * @version V1.1.1 + * @date 01-June-2017 + * @brief Header for driver low_power.c module + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics International N.V. + * All rights reserved.

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LOW_POWER_H__ +#define __LOW_POWER_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* External variables --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/*! + * @brief API to set flag allowing power mode + * + * @param [IN] enum e_LOW_POWER_State_Id_t + */ +void LowPower_Disable( e_LOW_POWER_State_Id_t state ); + +/*! + * @brief API to reset flag allowing power mode + * + * @param [IN] enum e_LOW_POWER_State_Id_t + */ + +void LowPower_Enable( e_LOW_POWER_State_Id_t state ); + +/*! + * @brief API to get flag allowing power mode + * @note When flag is 0, low power mode is allowed + * @param [IN] non + * @retval flag state + */ +uint32_t LowPower_GetState( void ); + +/*! + * @brief Manages the entry into ARM cortex deep-sleep mode + * @param none + * @retval none + */ +void LowPower_Handler( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* __LOW_POWER_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/timeServer.h b/cores/asr650x/kernel/protocols/lorawan/lora/system/timeServer.h new file mode 100644 index 00000000..746dd5ba --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/timeServer.h @@ -0,0 +1,247 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + +Description: Timer objects and scheduling management + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian +*/ +/****************************************************************************** + * @file timeServer.h + * @author MCD Application Team + * @version V1.1.1 + * @date 01-June-2017 + * @brief is the timer server driver + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics International N.V. + * All rights reserved.

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIMESERVER_H__ +#define __TIMESERVER_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "utilities.h" + +/* Exported types ------------------------------------------------------------*/ + +/*! + * \brief Timer object description + */ +typedef struct TimerEvent_s +{ + uint32_t Timestamp; //! Expiring timer value in ticks from TimerContext + uint32_t ReloadValue; //! Reload Value when Timer is restarted + bool IsRunning; //! Is the timer currently running + void ( *Callback )( void ); //! Timer IRQ callback function + struct TimerEvent_s *Next; //! Pointer to the next Timer object. +} TimerEvent_t; + + +/* Exported constants --------------------------------------------------------*/ +/* External variables --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/*! + * \brief Number of seconds elapsed between Unix and GPS epoch + */ +#define UNIX_GPS_EPOCH_OFFSET 315964800 + +/*! + * \brief Structure holding the system time in seconds and miliseconds. + */ +typedef struct TimerSysTime_s +{ + uint32_t Seconds; + int16_t SubSeconds; +}TimerSysTime_t; + +/*! + * Adds 2 TimerSysTime_t values + * + * \param a Value + * \param b Value to added + * + * \retval result Addition result (TimerSysTime_t value) + */ +inline TimerSysTime_t TimerAddSysTime( TimerSysTime_t a, TimerSysTime_t b ) +{ + TimerSysTime_t c = { 0 }; + + c.Seconds = a.Seconds + b.Seconds; + c.SubSeconds = a.SubSeconds + b.SubSeconds; + if( c.SubSeconds >= 1000 ) + { + c.Seconds++; + c.SubSeconds -= 1000; + } + return c; +} + +/*! + * Subtracts 2 TimerSysTime_t values + * + * \param a Value + * \param b Value to be subtracted + * + * \retval result Subtraction result (TimerSysTime_t value) + */ +inline TimerSysTime_t TimerSubSysTime( TimerSysTime_t a, TimerSysTime_t b ) +{ + TimerSysTime_t c = { 0 }; + + c.Seconds = a.Seconds - b.Seconds; + c.SubSeconds = a.SubSeconds - b.SubSeconds; + if( c.SubSeconds < 0 ) + { + c.Seconds--; + c.SubSeconds += 1000; + } + return c; +} + +/*! + * \brief Sets the system time with the number of sconds elapsed since epoch + * + * \param [IN] sysTime Structure provideing the number of seconds and + * subseconds elapsed since epoch + */ +void TimerSetSysTime( TimerSysTime_t sysTime ); + +/*! + * \brief Gets the current system number of sconds elapsed since epoch + * + * \retval sysTime Structure provideing the number of seconds and + * subseconds elapsed since epoch + */ +TimerSysTime_t TimerGetSysTime( void ); + +/*! + * \brief Initializes the timer object + * + * \remark TimerSetValue function must be called before starting the timer. + * this function initializes timestamp and reload value at 0. + * + * \param [IN] obj Structure containing the timer object parameters + * \param [IN] callback Function callback called at the end of the timeout + */ +void TimerInit( TimerEvent_t *obj, void ( *callback )( void ) ); + +/*! + * \brief Timer IRQ event handler + * + * \note Head Timer Object is automaitcally removed from the List + * + * \note e.g. it is snot needded to stop it + */ +void TimerIrqHandler( void ); + +/*! + * \brief Starts and adds the timer object to the list of timer events + * + * \param [IN] obj Structure containing the timer object parameters + */ +void TimerStart( TimerEvent_t *obj ); + +/*! + * \brief Stops and removes the timer object from the list of timer events + * + * \param [IN] obj Structure containing the timer object parameters + */ +void TimerStop( TimerEvent_t *obj ); + +/*! + * \brief Resets the timer object + * + * \param [IN] obj Structure containing the timer object parameters + */ +void TimerReset( TimerEvent_t *obj ); + +/*! + * \brief Set timer new timeout value + * + * \param [IN] obj Structure containing the timer object parameters + * \param [IN] value New timer timeout value + */ +void TimerSetValue( TimerEvent_t *obj, uint32_t value ); + + +/*! + * \brief Read the current time + * + * \retval returns current time in ms + */ +TimerTime_t TimerGetCurrentTime( void ); + +/*! + * \brief Return the Time elapsed since a fix moment in Time + * + * \param [IN] savedTime fix moment in Time + * \retval time returns elapsed time in ms + */ +TimerTime_t TimerGetElapsedTime( TimerTime_t savedTime ); + +/*! + * \brief Computes the temperature compensation for a period of time on a + * specific temperature. + * + * \param [IN] period Time period to compensate + * \param [IN] temperature Current temperature + * + * \retval Compensated time period + */ +TimerTime_t TimerTempCompensation( TimerTime_t period, float temperature ); +#ifdef __cplusplus +} +#endif + +#endif /* __TIMESERVER_H__*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/timer.h b/cores/asr650x/kernel/protocols/lorawan/lora/system/timer.h new file mode 100644 index 00000000..393c08e1 --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/timer.h @@ -0,0 +1,86 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + +Description: Timer objects and scheduling management + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian +*/ +/****************************************************************************** + * @file timer.h + * @author MCD Application Team + * @version V1.1.1 + * @date 01-June-2017 + * @brief wrapper to timer server + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics International N.V. + * All rights reserved.

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "timeServer.h" + +/* Exported types ------------------------------------------------------------*/ + +/*! + * \brief Timer object description + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_H__*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/utilities.c b/cores/asr650x/kernel/protocols/lorawan/lora/system/utilities.c new file mode 100644 index 00000000..111fa7be --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/utilities.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + +Description: Helper functions implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian +*/ +#include +#include +#include +#include "utilities.h" + +/*! + * Redefinition of rand() and srand() standard C functions. + * These functions are redefined in order to get the same behavior across + * different compiler toolchains implementations. + */ +// Standard random functions redefinition start +#define RAND_LOCAL_MAX 2147483647L + +static uint32_t next = 1; + +int32_t rand1( void ) +{ + return ( ( next = next * 1103515245L + 12345L ) % RAND_LOCAL_MAX ); +} + +void srand1( uint32_t seed ) +{ + next = seed; +} +// Standard random functions redefinition end + +int32_t randr( int32_t min, int32_t max ) +{ + return ( int32_t )rand1( ) % ( max - min + 1 ) + min; +} + +void memcpy1( uint8_t *dst, const uint8_t *src, uint16_t size ) +{ + while( size-- ) + { + *dst++ = *src++; + } +} + +void memcpyr( uint8_t *dst, const uint8_t *src, uint16_t size ) +{ + dst = dst + ( size - 1 ); + while( size-- ) + { + *dst-- = *src++; + } +} + +void memset1( uint8_t *dst, uint8_t value, uint16_t size ) +{ + while( size-- ) + { + *dst++ = value; + } +} + +int8_t Nibble2HexChar( uint8_t a ) +{ + if( a < 10 ) + { + return '0' + a; + } + else if( a < 16 ) + { + return 'A' + ( a - 10 ); + } + else + { + return '?'; + } +} + + diff --git a/cores/asr650x/kernel/protocols/lorawan/lora/system/utilities.h b/cores/asr650x/kernel/protocols/lorawan/lora/system/utilities.h new file mode 100644 index 00000000..575bcfbb --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lora/system/utilities.h @@ -0,0 +1,161 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech + +Description: Helper functions implementation + +License: Revised BSD License, see LICENSE.TXT file include in the project + +Maintainer: Miguel Luis and Gregory Cristian +*/ +/****************************************************************************** + * @file utilities.h + * @author MCD Application Team + * @version V1.1.1 + * @date 01-June-2017 + * @brief Header for driver utilities.c module + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics International N.V. + * All rights reserved.

+ * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __UTILITIES_H__ +#define __UTILITIES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* prepocessor directive to align buffer*/ +#define ALIGN(n) __attribute__((aligned(n))) +#include +#include +typedef uint64_t TimerTime_t; + +/*! + * \brief Returns the minimum value between a and b + * + * \param [IN] a 1st value + * \param [IN] b 2nd value + * \retval minValue Minimum value + */ +#define MIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) + +/*! + * \brief Returns the maximum value between a and b + * + * \param [IN] a 1st value + * \param [IN] b 2nd value + * \retval maxValue Maximum value + */ +#define MAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) + +/*! + * \brief Returns 2 raised to the power of n + * + * \param [IN] n power value + * \retval result of raising 2 to the power n + */ +#define POW2( n ) ( 1 << n ) + +/*! + * \brief Initializes the pseudo random generator initial value + * + * \param [IN] seed Pseudo random generator initial value + */ +void srand1( uint32_t seed ); + +int32_t rand1( void ); +/*! + * \brief Computes a random number between min and max + * + * \param [IN] min range minimum value + * \param [IN] max range maximum value + * \retval random random value in range min..max + */ +int32_t randr( int32_t min, int32_t max ); + +/*! + * \brief Copies size elements of src array to dst array + * + * \remark STM32 Standard memcpy function only works on pointers that are aligned + * + * \param [OUT] dst Destination array + * \param [IN] src Source array + * \param [IN] size Number of bytes to be copied + */ +void memcpy1( uint8_t *dst, const uint8_t *src, uint16_t size ); + +/*! + * \brief Copies size elements of src array to dst array reversing the byte order + * + * \param [OUT] dst Destination array + * \param [IN] src Source array + * \param [IN] size Number of bytes to be copied + */ +void memcpyr( uint8_t *dst, const uint8_t *src, uint16_t size ); + +/*! + * \brief Set size elements of dst array with value + * + * \remark STM32 Standard memset function only works on pointers that are aligned + * + * \param [OUT] dst Destination array + * \param [IN] value Default value + * \param [IN] size Number of bytes to be copied + */ +void memset1( uint8_t *dst, uint8_t value, uint16_t size ); + +/*! + * \brief Converts a nibble to an hexadecimal character + * + * \param [IN] a Nibble to be converted + * \retval hexChar Converted hexadecimal character + */ +int8_t Nibble2HexChar( uint8_t a ); + +char * strtok_l (char *s, const char *delim); + +#ifdef __cplusplus +} +#endif + +#endif // __UTILITIES_H__ diff --git a/cores/asr650x/kernel/protocols/lorawan/lorawan.mk b/cores/asr650x/kernel/protocols/lorawan/lorawan.mk new file mode 100644 index 00000000..c613de4a --- /dev/null +++ b/cores/asr650x/kernel/protocols/lorawan/lorawan.mk @@ -0,0 +1,54 @@ + +NAME := lorawan + +$(NAME)_SOURCES := lora/system/crypto/aes.c \ + lora/system/crypto/cmac.c \ + lora/system/timeServer.c \ + lora/system/low_power.c \ + lora/system/utilities.c \ + lora/system/delay.c \ + lora/mac/region/Region.c \ + lora/mac/region/RegionCommon.c \ + lora/mac/LoRaMac.c \ + lora/mac/LoRaMacCrypto.c \ + ../../../device/lora/sx1276/sx1276.c + +GLOBAL_INCLUDES += . \ + ../../../device/lora/sx1276 \ + lora/system/crypto \ + lora/radio \ + lora/mac \ + lora/mac/region \ + lora/system + +linkwan?=0 +ifeq ($(linkwan), 1) +GLOBAL_DEFINES += CONFIG_LINKWAN +GLOBAL_DEFINES += CONFIG_DEBUG_LINKWAN +GLOBAL_DEFINES += CONFIG_AOS_DISABLE_TICK +GLOBAL_DEFINES += REGION_CN470A +$(NAME)_SOURCES += linkwan/region/RegionCN470A.c +$(NAME)_SOURCES += linkwan/linkwan.c + +GLOBAL_INCLUDES += linkwan/include +GLOBAL_INCLUDES += linkwan/region + +linkwanat ?= 0 +ifeq ($(linkwanat), 1) +GLOBAL_DEFINES += CONFIG_LINKWAN_AT +GLOBAL_DEFINES += LOW_POWER_DISABLE +$(NAME)_SOURCES += linkwan/linkwan_ica_at.c +#$(NAME)_SOURCES += linkwan/linkwan_at.c +endif +else +$(NAME)_SOURCES += lora/mac/region/RegionAS923.c \ + lora/mac/region/RegionAU915.c \ + lora/mac/region/RegionCN470.c \ + lora/mac/region/RegionCN779.c \ + lora/mac/region/RegionEU433.c \ + lora/mac/region/RegionEU868.c \ + lora/mac/region/RegionIN865.c \ + lora/mac/region/RegionKR920.c \ + lora/mac/region/RegionUS915.c \ + lora/mac/region/RegionUS915-Hybrid.c +endif diff --git a/cores/asr650x/main.cpp b/cores/asr650x/main.cpp new file mode 100644 index 00000000..0eff215c --- /dev/null +++ b/cores/asr650x/main.cpp @@ -0,0 +1,35 @@ +/* + Copyright (c) 2015 Arduino LLC. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#define ARDUINO_MAIN +#include "Arduino.h" + +/* + * \brief Main entry point of Arduino application + */ +int main( void ) +{ + setup(); + + for (;;) + { + loop(); + } + + return 0; +} diff --git a/cores/asr650x/port/aos_port.c b/cores/asr650x/port/aos_port.c new file mode 100644 index 00000000..80892b7b --- /dev/null +++ b/cores/asr650x/port/aos_port.c @@ -0,0 +1,78 @@ +#include +#include +#include "aos/aos.h" + +void *aos_malloc(unsigned int size) +{ + return malloc(size); +} + +void aos_free(void *mem) +{ + free(mem); +} + +int aos_task_new(const char *name, void (*fn)(void *), void *arg, int stack_size) +{ + (void)name; + (void)stack_size; + + fn(arg); + return 0; +} + +void aos_task_exit(int code) +{ + (void)code; +} + +int aos_mutex_new(aos_mutex_t *mutex) +{ + (void)mutex; + return 0; +} +void aos_mutex_free(aos_mutex_t *mutex) +{ + (void)mutex; +} +int aos_mutex_lock(aos_mutex_t *mutex, unsigned int timeout) +{ + (void)mutex; + (void)timeout; + return 0; +} +int aos_mutex_unlock(aos_mutex_t *mutex) +{ + (void)mutex; + return 0; +} + +int aos_sem_new(aos_sem_t *sem, int count) +{ + (void)sem; + (void)count; + return 0; +} +void aos_sem_free(aos_sem_t *sem) +{ + (void)sem; +} +int aos_sem_wait(aos_sem_t *sem, unsigned int timeout) +{ + (void)sem; + (void)timeout; + return 0; +} +void aos_sem_signal(aos_sem_t *sem) +{ + (void)sem; +} +int aos_sem_is_valid(aos_sem_t *sem) +{ + (void)sem; + return 1; +} +void aos_sem_signal_all(aos_sem_t *sem) +{ + (void)sem; +} \ No newline at end of file diff --git a/cores/asr650x/port/flash_port.c b/cores/asr650x/port/flash_port.c new file mode 100644 index 00000000..407bad31 --- /dev/null +++ b/cores/asr650x/port/flash_port.c @@ -0,0 +1,214 @@ +#include "hal/soc/soc.h" +#include +#include +#include +#include + +#define ROUND_DOWN(a,b) (((a) / (b)) * (b)) +#define MIN(a,b) (((a) < (b)) ? (a) : (b)) + +#define FLASH_PAGE_SIZE (CY_FLASH_SIZEOF_ROW) + +extern const hal_logic_partition_t hal_partitions[]; + +/** + * @brief Update a chunk of the FLASH memory. + * @note The FLASH chunk must no cross a FLASH bank boundary. + * @note The source and destination buffers have no specific alignment constraints. + * @param In: dst_addr Destination address in the FLASH memory. + * @param In: data Source address. + * @param In: size Number of bytes to update. + * @retval 0: Success. + * <0: Failure. + */ +int FLASH_update(uint32_t dst_addr, const void *data, uint32_t size) +{ + int remaining = size; + uint8_t * src_addr = (uint8_t *) data; + uint32 status; + + uint32_t * page_cache = NULL; + page_cache = (uint32_t *)aos_malloc(FLASH_PAGE_SIZE); + if (page_cache == NULL) + return -1; + memset(page_cache, 0, FLASH_PAGE_SIZE); + + do { + uint32_t fl_addr = ROUND_DOWN(dst_addr, FLASH_PAGE_SIZE); + int fl_offset = dst_addr - fl_addr; + int len = MIN(FLASH_PAGE_SIZE - fl_offset, size); + + /* Load from the flash into the cache */ + memcpy(page_cache, (void *) fl_addr, FLASH_PAGE_SIZE); + /* Update the cache from the source */ + memcpy((uint8_t *)page_cache + fl_offset, src_addr, len); + + status = CySysFlashWriteRow(fl_addr/FLASH_PAGE_SIZE, (uint8 *)page_cache); + if(status != CY_SYS_FLASH_SUCCESS) + { + printf("Error writing %u bytes at 0x%08x\n", FLASH_PAGE_SIZE, (unsigned int)fl_addr); + } + else + { + dst_addr += len; + src_addr += len; + remaining -= len; + } + } + while ((status == CY_SYS_FLASH_SUCCESS) && (remaining > 0)); + + aos_free(page_cache); + + return 0; +} + +/*****************************************************************/ +/** + * @brief Read from FLASH memory. + * @param In: address Destination address. + * @param In: pData Data to be programmed: Must be 8 byte aligned. + * @param In: len_bytes Number of bytes to be programmed. + * @retval 0: Success. + -1: Failure. + */ +int FLASH_read_at(uint32_t address, uint8_t *pData, uint32_t len_bytes) +{ + uint32 i; + int ret = -1; + uint8_t *src = (uint8_t *)(address); + uint8_t *dst = (uint8_t *)(pData); + + for (i = 0; i < len_bytes; i++) + { + *(dst++) = *(src++); + } + + ret = 0; + return ret; +} + +hal_logic_partition_t *hal_flash_get_info(hal_partition_t pno) +{ + hal_logic_partition_t *logic_partition; + + logic_partition = (hal_logic_partition_t *)&hal_partitions[ pno ]; + + return logic_partition; +} + +int32_t hal_flash_write(hal_partition_t pno, uint32_t* poff, const void* buf ,uint32_t buf_size) +{ + uint32_t start_addr; + hal_logic_partition_t *partition_info; + hal_partition_t real_pno; + +#ifdef CONFIG_AOS_KV_MULTIPTN_MODE + if (pno == CONFIG_AOS_KV_PTN) { + if ((*poff) >= CONFIG_AOS_KV_PTN_SIZE) { + pno = (hal_partition_t)CONFIG_AOS_KV_SECOND_PTN; + *poff = (*poff) - CONFIG_AOS_KV_PTN_SIZE; + } + } +#endif + real_pno = pno; + + partition_info = hal_flash_get_info( real_pno ); + start_addr = partition_info->partition_start_addr + *poff; + + if (0 != FLASH_update(start_addr, buf, buf_size)) { + printf("FLASH_update failed!\n"); + } + *poff += buf_size; + + return 0; +} + +int32_t hal_flash_read(hal_partition_t pno, uint32_t* poff, void* buf, uint32_t buf_size) +{ + uint32_t start_addr; + hal_logic_partition_t *partition_info; + hal_partition_t real_pno; + +#ifdef CONFIG_AOS_KV_MULTIPTN_MODE + if (pno == CONFIG_AOS_KV_PTN) { + if ((*poff) >= CONFIG_AOS_KV_PTN_SIZE) { + pno = (hal_partition_t)CONFIG_AOS_KV_SECOND_PTN; + *poff = (*poff) - CONFIG_AOS_KV_PTN_SIZE; + } + } +#endif + real_pno = pno; + + partition_info = hal_flash_get_info( real_pno ); + + if(poff == NULL || buf == NULL || *poff + buf_size > partition_info->partition_length) + return -1; + start_addr = partition_info->partition_start_addr + *poff; + FLASH_read_at(start_addr, buf, buf_size); + *poff += buf_size; + + return 0; +} + +int32_t hal_flash_erase(hal_partition_t pno, uint32_t off_set, + uint32_t size) +{ + uint32_t start_addr; + uint32 status; + hal_logic_partition_t *partition_info; + hal_partition_t real_pno; + uint32_t * page_cache = NULL; + + page_cache = (uint32_t *)aos_malloc(FLASH_PAGE_SIZE); + if (page_cache == NULL) + return -1; + memset(page_cache, 0xff, FLASH_PAGE_SIZE); + +#ifdef CONFIG_AOS_KV_MULTIPTN_MODE + if (pno == CONFIG_AOS_KV_PTN) { + if (off_set >= CONFIG_AOS_KV_PTN_SIZE) { + pno = (hal_partition_t)CONFIG_AOS_KV_SECOND_PTN; + off_set -= CONFIG_AOS_KV_PTN_SIZE; + } + } +#endif + real_pno = pno; + + partition_info = hal_flash_get_info( real_pno ); + if(size + off_set > partition_info->partition_length) + return -1; + + start_addr = ROUND_DOWN((partition_info->partition_start_addr + off_set), FLASH_PAGE_SIZE); + + for(uint32_t i=0; i +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define AOS_WAIT_FOREVER 0xffffffffu +#define AOS_NO_WAIT 0x0 +#define AOS_DEFAULT_APP_PRI 32 + +typedef struct { + void *hdl; +} aos_hdl_t; + +typedef aos_hdl_t aos_task_t; +typedef aos_hdl_t aos_mutex_t; +typedef aos_hdl_t aos_sem_t; +typedef aos_hdl_t aos_queue_t; +typedef aos_hdl_t aos_timer_t; +typedef aos_hdl_t aos_work_t; +typedef aos_hdl_t aos_event_t; + +//mm +void *aos_malloc(unsigned int size); +void aos_free(void *mem); + +//task +int aos_task_new(const char *name, void (*fn)(void *), void *arg, int stack_size); +void aos_task_exit(int code); + +//mutex +int aos_mutex_new(aos_mutex_t *mutex); +void aos_mutex_free(aos_mutex_t *mutex); +int aos_mutex_lock(aos_mutex_t *mutex, unsigned int timeout); +int aos_mutex_unlock(aos_mutex_t *mutex); + +//sem +int aos_sem_new(aos_sem_t *sem, int count); +void aos_sem_free(aos_sem_t *sem); +int aos_sem_wait(aos_sem_t *sem, unsigned int timeout); +void aos_sem_signal(aos_sem_t *sem); +int aos_sem_is_valid(aos_sem_t *sem); +void aos_sem_signal_all(aos_sem_t *sem); + +#ifdef __cplusplus +} +#endif + +#endif /* AOS_KERNEL_H */ + diff --git a/cores/asr650x/port/include/aos/kv.h b/cores/asr650x/port/include/aos/kv.h new file mode 100644 index 00000000..46927dfc --- /dev/null +++ b/cores/asr650x/port/include/aos/kv.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef AOS_KV_H +#define AOS_KV_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * Add a new KV pair. + * + * @param[in] key the key of the KV pair. + * @param[in] value the value of the KV pair. + * @param[in] len the length of the value. + * @param[in] sync save the KV pair to flash right now (should always be 1). + * + * @return 0 on success, negative error on failure. + */ +int aos_kv_set(const char *key, const void *value, int len, int sync); + +/** + * Get the KV pair's value stored in buffer by its key. + * + * @note: the buffer_len should be larger than the real length of the value, + * otherwise buffer would be NULL. + * + * @param[in] key the key of the KV pair to get. + * @param[out] buffer the memory to store the value. + * @param[in-out] buffer_len in: the length of the input buffer. + * out: the real length of the value. + * + * @return 0 on success, negative error on failure. + */ +int aos_kv_get(const char *key, void *buffer, int *buffer_len); + +/** + * Delete the KV pair by its key. + * + * @param[in] key the key of the KV pair to delete. + * + * @return 0 on success, negative error on failure. + */ +int aos_kv_del(const char *key); + +#ifdef __cplusplus +} +#endif + +#endif /* AOS_KV_H */ + diff --git a/cores/asr650x/port/include/aos/list.h b/cores/asr650x/port/include/aos/list.h new file mode 100644 index 00000000..50a047f3 --- /dev/null +++ b/cores/asr650x/port/include/aos/list.h @@ -0,0 +1,338 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef AOS_LIST_H +#define AOS_LIST_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Get offset of a member variable. + * + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the variable within the struct. + */ +#define aos_offsetof(type, member) ((size_t)&(((type *)0)->member)) + +/* + * Get the struct for this entry. + * + * @param[in] ptr the list head to take the element from. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the variable within the struct. + */ +#define aos_container_of(ptr, type, member) \ + ((type *) ((char *) (ptr) - aos_offsetof(type, member))) + +/* for double link list */ +typedef struct dlist_s { + struct dlist_s *prev; + struct dlist_s *next; +} dlist_t; + +static inline void __dlist_add(dlist_t *node, dlist_t *prev, dlist_t *next) +{ + node->next = next; + node->prev = prev; + + prev->next = node; + next->prev = node; +} + +/* + * Get the struct for this entry. + * + * @param[in] addr the list head to take the element from. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the dlist_t within the struct. + */ +#define dlist_entry(addr, type, member) \ + ((type *)((long)addr - aos_offsetof(type, member))) + + +static inline void dlist_add(dlist_t *node, dlist_t *queue) +{ + __dlist_add(node, queue, queue->next); +} + +static inline void dlist_add_tail(dlist_t *node, dlist_t *queue) +{ + __dlist_add(node, queue->prev, queue); +} + +static inline void dlist_del(dlist_t *node) +{ + dlist_t *prev = node->prev; + dlist_t *next = node->next; + + prev->next = next; + next->prev = prev; +} + +static inline void dlist_init(dlist_t *node) +{ + node->next = node->prev = node; +} + +static inline void INIT_AOS_DLIST_HEAD(dlist_t *list) +{ + list->next = list; + list->prev = list; +} + +static inline int dlist_empty(const dlist_t *head) +{ + return head->next == head; +} + +/* + * Initialise the list. + * + * @param[in] list the list to be inited. + */ +#define AOS_DLIST_INIT(list) {&(list), &(list)} + +/* + * Get the first element from a list + * + * @param[in] ptr the list head to take the element from. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the dlist_t within the struct. + */ +#define dlist_first_entry(ptr, type, member) \ + dlist_entry((ptr)->next, type, member) + +/* + * Iterate over a list. + * + * @param[in] pos the &struct dlist_t to use as a loop cursor. + * @param[in] head he head for your list. + */ +#define dlist_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/* + * Iterate over a list safe against removal of list entry. + * + * @param[in] pos the &struct dlist_t to use as a loop cursor. + * @param[in] n another &struct dlist_t to use as temporary storage. + * @param[in] head he head for your list. + */ +#define dlist_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/* + * Iterate over list of given type. + * + * @param[in] queue he head for your list. + * @param[in] node the &struct dlist_t to use as a loop cursor. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the dlist_t within the struct. + */ +#define dlist_for_each_entry(queue, node, type, member) \ + for (node = aos_container_of((queue)->next, type, member); \ + &node->member != (queue); \ + node = aos_container_of(node->member.next, type, member)) + +/* + * Iterate over list of given type safe against removal of list entry. + * + * @param[in] queue the head for your list. + * @param[in] n the type * to use as a temp. + * @param[in] node the type * to use as a loop cursor. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the dlist_t within the struct. + */ +#define dlist_for_each_entry_safe(queue, n, node, type, member) \ + for (node = aos_container_of((queue)->next, type, member), \ + n = (queue)->next ? (queue)->next->next : NULL; \ + &node->member != (queue); \ + node = aos_container_of(n, type, member), n = n ? n->next : NULL) + +/* + * Get the struct for this entry. + * @param[in] ptr the list head to take the element from. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the variable within the struct. + */ +#define list_entry(ptr, type, member) \ + aos_container_of(ptr, type, member) + + +/* + * Iterate backwards over list of given type. + * + * @param[in] pos the type * to use as a loop cursor. + * @param[in] head he head for your list. + * @param[in] member the name of the dlist_t within the struct. + * @param[in] type the type of the struct this is embedded in. + */ +#define dlist_for_each_entry_reverse(pos, head, member, type) \ + for (pos = list_entry((head)->prev, type, member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.prev, type, member)) + + +/* + * Get the list length. + * + * @param[in] queue the head for your list. + */ +static inline int dlist_entry_number(dlist_t *queue) +{ + int num; + dlist_t *cur = queue; + for (num=0;cur->next != queue;cur=cur->next, num++) + ; + + return num; +} + + + +/* + * Initialise the list. + * + * @param[in] name the list to be initialized. + */ +#define AOS_DLIST_HEAD_INIT(name) { &(name), &(name) } + +/* + * Initialise the list. + * + * @param[in] name the list to be initialized. + */ +#define AOS_DLIST_HEAD(name) \ + dlist_t name = AOS_DLIST_HEAD_INIT(name) + +/* for single link list */ +typedef struct slist_s { + struct slist_s *next; +} slist_t; + +static inline void slist_add(slist_t *node, slist_t *head) +{ + node->next = head->next; + head->next = node; +} + +static inline void slist_add_tail(slist_t *node, slist_t *head) +{ + while (head->next) { + head = head->next; + } + + slist_add(node, head); +} + +static inline void slist_del(slist_t *node, slist_t *head) +{ + while (head->next) { + if (head->next == node) { + head->next = node->next; + break; + } + + head = head->next; + } +} + +static inline int slist_empty(const slist_t *head) +{ + return !head->next; +} + +static inline void slist_init(slist_t *head) +{ + head->next = 0; +} + +/* +* Iterate over list of given type. +* +* @param[in] queue he head for your list. +* @param[in] node the type * to use as a loop cursor. +* @param[in] type the type of the struct this is embedded in. +* @param[in] member the name of the slist_t within the struct. +*/ +#define slist_for_each_entry(queue, node, type, member) \ + for (node = aos_container_of((queue)->next, type, member); \ + &node->member; \ + node = aos_container_of(node->member.next, type, member)) + +/* + * Iterate over list of given type safe against removal of list entry. + * + * @param[in] queue the head for your list. + * @param[in] tmp the type * to use as a temp. + * @param[in] node the type * to use as a loop cursor. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the slist_t within the struct. + */ +#define slist_for_each_entry_safe(queue, tmp, node, type, member) \ + for (node = aos_container_of((queue)->next, type, member), \ + tmp = (queue)->next ? (queue)->next->next : NULL; \ + &node->member; \ + node = aos_container_of(tmp, type, member), tmp = tmp ? tmp->next : tmp) + +/* + * Initialise the list. + * + * @param[in] name the list to be initialized. + */ +#define AOS_SLIST_HEAD_INIT(name) {0} + +/* + * Initialise the list. + * + * @param[in] name the list to be initialized. + */ +#define AOS_SLIST_HEAD(name) \ + slist_t name = AOS_SLIST_HEAD_INIT(name) + +/* + * Get the struct for this entry. + * @param[in] addr the list head to take the element from. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the slist_t within the struct. + */ +#define slist_entry(addr, type, member) ( \ + addr ? (type *)((long)addr - aos_offsetof(type, member)) : (type *)addr \ +) + +/* +* Get the first element from a list. +* +* @param[in] ptr the list head to take the element from. +* @param[in] type the type of the struct this is embedded in. +* @param[in] member the name of the slist_t within the struct. +*/ +#define slist_first_entry(ptr, type, member) \ + slist_entry((ptr)->next, type, member) + +/* + * Get the list length. + * + * @param[in] queue the head for your list. + */ +static inline int slist_entry_number(slist_t *queue) +{ + int num; + slist_t *cur = queue; + for (num=0;cur->next;cur=cur->next, num++) + ; + + return num; +} + + +#ifdef __cplusplus +} +#endif + +#endif /* AOS_LIST_H */ + diff --git a/cores/asr650x/port/include/hal/base.h b/cores/asr650x/port/include/hal/base.h new file mode 100644 index 00000000..bc8c3270 --- /dev/null +++ b/cores/asr650x/port/include/hal/base.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef HAL_BASE_H +#define HAL_BASE_H + +#include + +/* + * HAL common error code + */ +enum { + HAL_ERR_ARG = -4096, + HAL_ERR_CAP, +}; + +/* + * HAL Module define + */ +typedef struct { + dlist_t list; + int magic; + const char *name; + void *priv_dev; /* Driver may want to describe it */ +} hal_module_base_t; + +#endif /* HAL_BASE_H */ + diff --git a/cores/asr650x/port/include/hal/hal.h b/cores/asr650x/port/include/hal/hal.h new file mode 100644 index 00000000..0a210903 --- /dev/null +++ b/cores/asr650x/port/include/hal/hal.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef HAL_HAL_H_ +#define HAL_HAL_H_ + +#include +#include + +#include +//#include +//#include +//#include +//#include +//#include + +#include + +#endif /* HAL_HAL_H */ + diff --git a/cores/asr650x/port/include/hal/lorawan.h b/cores/asr650x/port/include/hal/lorawan.h new file mode 100644 index 00000000..d2143163 --- /dev/null +++ b/cores/asr650x/port/include/hal/lorawan.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef HAL_LRWAN_H +#define HAL_LRWAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*INCLUDES******************************************************************* + * SYSTEM HEADER FILES + *END***********************************************************************/ +#include +#include "base.h" +#include "timeServer.h" + +/*MACROS********************************************************************* + * DATATYPE DEFINITIONS + *END***********************************************************************/ +/* the struct is for changing the device working mode */ +typedef struct +{ + void (*enter_stop_mode)(void); + void (*exit_stop_mode)(void); + void (*enter_sleep_mode)(void); +} hal_lrwan_dev_chg_mode_t; + +/* LoRaWan time and timer interface */ +typedef struct +{ + void (*delay_ms)(uint32_t delay); + TimerTime_t (*set_timer_context)(void); + TimerTime_t (*get_timer_context)(void); + TimerTime_t (*get_timer_elapsed_time)(void); + void (*stop_alarm)(void); + void (*set_alarm)(uint32_t timeout); + void (*set_uc_wakeup_time)(void); + void (*set_timeout)(TimerEvent_t *obj); + TimerTime_t (*compute_elapsed_time)(TimerTime_t time); + TimerTime_t (*get_current_time)(void ); + void (*set_timer_val)(TimerEvent_t *obj, uint32_t value); + uint32_t (*get_sys_time)( uint16_t *subSeconds ); + void (*set_sys_time)( uint32_t seconds, uint16_t subSeconds ); +} hal_lrwan_time_itf_t; + +/* the struct is for control of radio */ +typedef struct +{ + void (*radio_reset)(void); + void (*radio_reset_cfg_input)(void); + void (*radio_rw_en)(void); + void (*radio_rw_dis)(void); + uint16_t (*radio_rw)(uint16_t tx_data); +} hal_lrwan_radio_ctrl_t; + +/* LoraWan manufactory interface*/ +typedef struct { + char *(*get_mft_id)(void); + char *(*get_mft_model)(void); + char *(*get_mft_rev)(void); + char * (*get_mft_sn)(void); + bool (*set_mft_baud)(uint32_t baud); + uint32_t (*get_mft_baud)(void); +} hal_manufactory_itf_t; +#ifdef __cplusplus +} +#endif + +#endif /* HAL_LRWAN_H */ + diff --git a/cores/asr650x/port/include/hal/soc/flash.h b/cores/asr650x/port/include/hal/soc/flash.h new file mode 100644 index 00000000..b975a166 --- /dev/null +++ b/cores/asr650x/port/include/hal/soc/flash.h @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef HAL_FLASH_H +#define HAL_FLASH_H + +#define PAR_OPT_READ_POS ( 0 ) +#define PAR_OPT_WRITE_POS ( 1 ) + +#define PAR_OPT_READ_MASK ( 0x1u << PAR_OPT_READ_POS ) +#define PAR_OPT_WRITE_MASK ( 0x1u << PAR_OPT_WRITE_POS ) + +#define PAR_OPT_READ_DIS ( 0x0u << PAR_OPT_READ_POS ) +#define PAR_OPT_READ_EN ( 0x1u << PAR_OPT_READ_POS ) +#define PAR_OPT_WRITE_DIS ( 0x0u << PAR_OPT_WRITE_POS ) +#define PAR_OPT_WRITE_EN ( 0x1u << PAR_OPT_WRITE_POS ) + +typedef enum { + HAL_PARTITION_ERROR = -1, + HAL_PARTITION_BOOTLOADER, + HAL_PARTITION_APPLICATION, + HAL_PARTITION_ATE, + HAL_PARTITION_OTA_TEMP, + HAL_PARTITION_RF_FIRMWARE, + HAL_PARTITION_PARAMETER_1, + HAL_PARTITION_PARAMETER_2, + HAL_PARTITION_PARAMETER_3, + HAL_PARTITION_PARAMETER_4, + HAL_PARTITION_BT_FIRMWARE, + HAL_PARTITION_SPIFFS, + HAL_PARTITION_MAX, + HAL_PARTITION_NONE, +} hal_partition_t; + +typedef enum { + HAL_FLASH_EMBEDDED, + HAL_FLASH_SPI, + HAL_FLASH_QSPI, + HAL_FLASH_MAX, + HAL_FLASH_NONE, +} hal_flash_t; + +typedef struct { + hal_flash_t partition_owner; + const char *partition_description; + uint32_t partition_start_addr; + uint32_t partition_length; + uint32_t partition_options; +} hal_logic_partition_t; + +/** + * Get the infomation of the specified flash area + * + * @param[in] in_partition The target flash logical partition + * + * @return HAL_logi_partition struct + */ +hal_logic_partition_t *hal_flash_get_info(hal_partition_t in_partition); + +/** + * Erase an area on a Flash logical partition + * + * @note Erase on an address will erase all data on a sector that the + * address is belonged to, this function does not save data that + * beyond the address area but in the affected sector, the data + * will be lost. + * + * @param[in] in_partition The target flash logical partition which should be erased + * @param[in] off_set Start address of the erased flash area + * @param[in] size Size of the erased flash area + * + * @return 0 : On success, EIO : If an error occurred with any step + */ +int32_t hal_flash_erase(hal_partition_t in_partition, uint32_t off_set, uint32_t size); + +/** + * Write data to an area on a flash logical partition without erase + * + * @param[in] in_partition The target flash logical partition which should be read which should be written + * @param[in] off_set Point to the start address that the data is written to, and + * point to the last unwritten address after this function is + * returned, so you can call this function serval times without + * update this start address. + * @param[in] inBuffer point to the data buffer that will be written to flash + * @param[in] inBufferLength The length of the buffer + * + * @return 0 : On success, EIO : If an error occurred with any step + */ +int32_t hal_flash_write(hal_partition_t in_partition, uint32_t *off_set, + const void *in_buf, uint32_t in_buf_len); + +/** + * Write data to an area on a flash logical partition with erase first + * + * @param[in] in_partition The target flash logical partition which should be read which should be written + * @param[in] off_set Point to the start address that the data is written to, and + * point to the last unwritten address after this function is + * returned, so you can call this function serval times without + * update this start address. + * @param[in] inBuffer point to the data buffer that will be written to flash + * @param[in] inBufferLength The length of the buffer + * + * @return 0 : On success, EIO : If an error occurred with any step + */ +int32_t hal_flash_erase_write(hal_partition_t in_partition, uint32_t *off_set, + const void *in_buf, uint32_t in_buf_len); + +/** + * Read data from an area on a Flash to data buffer in RAM + * + * @param[in] in_partition The target flash logical partition which should be read + * @param[in] off_set Point to the start address that the data is read, and + * point to the last unread address after this function is + * returned, so you can call this function serval times without + * update this start address. + * @param[in] outBuffer Point to the data buffer that stores the data read from flash + * @param[in] inBufferLength The length of the buffer + * + * @return 0 : On success, EIO : If an error occurred with any step + */ +int32_t hal_flash_read(hal_partition_t in_partition, uint32_t *off_set, + void *out_buf, uint32_t in_buf_len); + +/** + * Set security options on a logical partition + * + * @param[in] partition The target flash logical partition + * @param[in] offset Point to the start address that the data is read, and + * point to the last unread address after this function is + * returned, so you can call this function serval times without + * update this start address. + * @param[in] size Size of enabled flash area + * + * @return 0 : On success, EIO : If an error occurred with any step + */ +int32_t hal_flash_enable_secure(hal_partition_t partition, uint32_t off_set, uint32_t size); + +/** + * Disable security options on a logical partition + * + * @param[in] partition The target flash logical partition + * @param[in] offset Point to the start address that the data is read, and + * point to the last unread address after this function is + * returned, so you can call this function serval times without + * update this start address. + * @param[in] size Size of disabled flash area + * + * @return 0 : On success, EIO : If an error occurred with any step + */ +int32_t hal_flash_dis_secure(hal_partition_t partition, uint32_t off_set, uint32_t size); + +#endif /* HAL_FLASH_H */ + diff --git a/cores/asr650x/port/include/hal/soc/soc.h b/cores/asr650x/port/include/hal/soc/soc.h new file mode 100644 index 00000000..05bddfc3 --- /dev/null +++ b/cores/asr650x/port/include/hal/soc/soc.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef HAL_SOC_H +#define HAL_SOC_H + +#include +#include + + +#include +#include + +#define HAL_WAIT_FOREVER 0xFFFFFFFFU + +#endif /* HAL_SOC_H */ + diff --git a/cores/asr650x/port/include/hal/soc/uart.h b/cores/asr650x/port/include/hal/soc/uart.h new file mode 100644 index 00000000..7316ccc2 --- /dev/null +++ b/cores/asr650x/port/include/hal/soc/uart.h @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef HAL_UART_H +#define HAL_UART_H + +/* + * UART data width + */ +typedef enum { + DATA_WIDTH_5BIT, + DATA_WIDTH_6BIT, + DATA_WIDTH_7BIT, + DATA_WIDTH_8BIT, + DATA_WIDTH_9BIT +} hal_uart_data_width_t; + +/* + * UART stop bits + */ +typedef enum { + STOP_BITS_1, + STOP_BITS_2 +} hal_uart_stop_bits_t; + +/* + * UART flow control + */ +typedef enum { + FLOW_CONTROL_DISABLED, + FLOW_CONTROL_CTS, + FLOW_CONTROL_RTS, + FLOW_CONTROL_CTS_RTS +} hal_uart_flow_control_t; + +/* + * UART parity + */ +typedef enum { + NO_PARITY, + ODD_PARITY, + EVEN_PARITY +} hal_uart_parity_t; + +/* + * UART mode + */ +typedef enum { + MODE_TX, + MODE_RX, + MODE_TX_RX +} hal_uart_mode_t; + +/* + * UART configuration + */ +typedef struct { + uint32_t baud_rate; + hal_uart_data_width_t data_width; + hal_uart_parity_t parity; + hal_uart_stop_bits_t stop_bits; + hal_uart_flow_control_t flow_control; + hal_uart_mode_t mode; +} uart_config_t; + +typedef struct { + uint8_t port; /* uart port */ + uart_config_t config; /* uart config */ + void *priv; /* priv data */ +} uart_dev_t; + +/** + * Initialises a UART interface + * + * + * @param[in] uart the interface which should be initialised + * + * @return 0 : on success, EIO : if an error occurred with any step + */ +int32_t hal_uart_init(uart_dev_t *uart); + +/** + * Transmit data on a UART interface + * + * @param[in] uart the UART interface + * @param[in] data pointer to the start of data + * @param[in] size number of bytes to transmit + * + * @return 0 : on success, EIO : if an error occurred with any step + */ +int32_t hal_uart_send(uart_dev_t *uart, const void *data, uint32_t size, uint32_t timeout); + +/** + * Receive data on a UART interface + * + * @param[in] uart the UART interface + * @param[out] data pointer to the buffer which will store incoming data + * @param[in] expect_size number of bytes to receive + * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER + * if you want to wait forever + * + * @return 0 : on success, EIO : if an error occurred with any step + */ +int32_t hal_uart_recv(uart_dev_t *uart, void *data, uint32_t expect_size, uint32_t timeout); + +/** + * Receive data on a UART interface + * + * @param[in] uart the UART interface + * @param[out] data pointer to the buffer which will store incoming data + * @param[in] expect_size number of bytes to receive + * @param[out] recv_size number of bytes received + * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER + * if you want to wait forever + * + * @return 0 : on success, EIO : if an error occurred with any step + */ +int32_t hal_uart_recv_II(uart_dev_t *uart, void *data, uint32_t expect_size, + uint32_t *recv_size, uint32_t timeout); + +/** + * Deinitialises a UART interface + * + * @param[in] uart the interface which should be deinitialised + * + * @return 0 : on success, EIO : if an error occurred with any step + */ +int32_t hal_uart_finalize(uart_dev_t *uart); + +#endif /* HAL_UART_H */ + diff --git a/cores/asr650x/port/include/k_api.h b/cores/asr650x/port/include/k_api.h new file mode 100644 index 00000000..9d481722 --- /dev/null +++ b/cores/asr650x/port/include/k_api.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef K_API_H +#define K_API_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +} +#endif + +#endif /* K_API_H */ + diff --git a/cores/asr650x/port/include/k_types.h b/cores/asr650x/port/include/k_types.h new file mode 100644 index 00000000..c1733f5c --- /dev/null +++ b/cores/asr650x/port/include/k_types.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef TYPES_H +#define TYPES_H + +#define RHINO_TASK_STACK_OVF_MAGIC 0xdeadbeafu /* 32 bit or 64 bit stack overflow magic value */ +#define RHINO_INTRPT_STACK_OVF_MAGIC 0xdeaddeadu /* 32 bit or 64 bit stack overflow magic value */ +#define RHINO_MM_CORRUPT_DYE 0xFEFEFEFE +#define RHINO_MM_FREE_DYE 0xABABABAB +#define RHINO_INLINE static inline /* inline keyword, it may change under different compilers */ + +typedef char name_t; +typedef uint32_t sem_count_t; +typedef uint32_t cpu_stack_t; +typedef uint32_t hr_timer_t; +typedef uint32_t lr_timer_t; +typedef uint32_t mutex_nested_t; +typedef uint8_t suspend_nested_t; +typedef uint64_t ctx_switch_t; +typedef uint32_t cpu_cpsr_t; + +#endif /* TYPES_H */ + diff --git a/cores/asr650x/port/include/port.h b/cores/asr650x/port/include/port.h new file mode 100644 index 00000000..f303ddd3 --- /dev/null +++ b/cores/asr650x/port/include/port.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2015-2017 Alibaba Group Holding Limited + */ + +#ifndef PORT_H +#define PORT_H + +size_t cpu_intrpt_save(void); +void cpu_intrpt_restore(size_t cpsr); +void cpu_intrpt_switch(void); +void cpu_task_switch(void); +void cpu_first_task_start(void); +//void *cpu_task_stack_init(cpu_stack_t *base, size_t size, void *arg, task_entry_t entry); + +RHINO_INLINE uint8_t cpu_cur_get(void) +{ + return 0; +} + +#define CPSR_ALLOC() size_t cpsr + +#define RHINO_CPU_INTRPT_DISABLE() { cpsr = cpu_intrpt_save(); } +#define RHINO_CPU_INTRPT_ENABLE() { cpu_intrpt_restore(cpsr); } + +#endif /* PORT_H */ + diff --git a/cores/asr650x/port/include/uart_port.h b/cores/asr650x/port/include/uart_port.h new file mode 100644 index 00000000..c1720705 --- /dev/null +++ b/cores/asr650x/port/include/uart_port.h @@ -0,0 +1,94 @@ +#ifndef __UART_PORT_H +#define __UART_PORT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "board.h" +#include + +/* USER CONFIGURABLE: Instance name of the UART component */ +#if(STDIO_UART == 0) +#define CONSOLE_UART_INSTANCE UART_1 +#elif (STDIO_UART == 1) +#define CONSOLE_UART_INSTANCE SCB1 +#elif (STDIO_UART == 2) +#define CONSOLE_UART_INSTANCE SCB2 +#elif (STDIO_UART == 3) +#define CONSOLE_UART_INSTANCE SCB3 +#elif (STDIO_UART == 4) +#define CONSOLE_UART_INSTANCE SCB4 +#endif + +#define UART_API(fn) UART_API_IMPL(CONSOLE_UART_INSTANCE, fn) +#define UART_API_IMPL(a, b) UART_API_IMPL2(a, b) +#define UART_API_IMPL2(a, b) a ## b + +#define UART_FLAG(fg) UART_FLAG_IMPL(CONSOLE_UART_INSTANCE, fg) +#define UART_FLAG_IMPL(a, b) UART_FLAG_IMPL2(a, b) +#define UART_FLAG_IMPL2(a, b) a ## b + +#define UART_RX_QUEUE_SIZE 64 +typedef enum { + UART0 = 0, + UART1, + UART2, + UART3, + UART4, + UARTn +} uart_port; + +typedef enum { + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_Status; + +typedef struct { + aos_mutex_t uart_tx_mutex; + aos_mutex_t uart_rx_mutex; + aos_sem_t uart_tx_sem; + aos_sem_t uart_rx_sem; +} uart_os_t; + +int default_UART_Init(void); +void uart_put_char(int c); +int32_t aos_uart_recv(void *data, uint32_t expect_size, uint32_t *recv_size, uint32_t timeout); +int32_t aos_uart_send(void *data, uint32_t size, uint32_t timeout); +struct circ_buf { + char *buf; + int head; + int tail; +}; + +/* Return count in buffer. */ +#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1)) + +/* Return space available, 0..size-1. We always leave one free char + as a completely full buffer has head == tail, which is the same as + empty. */ +#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) + +/* Return count up to the end of the buffer. Carefully avoid + accessing head and tail more than once, so they can change + underneath us without returning inconsistent results. */ +#define CIRC_CNT_TO_END(head,tail,size) \ + ({int end = (size) - (tail); \ + int n = ((head) + end) & ((size)-1); \ + n < end ? n : end;}) + +/* Return space available up to the end of the buffer. */ +#define CIRC_SPACE_TO_END(head,tail,size) \ + ({int end = (size) - 1 - (head); \ + int n = (end + (tail)) & ((size)-1); \ + n <= end ? n : end+1;}) +//the size should be 2^ +#define UART_CONSOLE_SIZE 256 +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/cores/asr650x/port/port_s.S b/cores/asr650x/port/port_s.S new file mode 100644 index 00000000..f2346568 --- /dev/null +++ b/cores/asr650x/port/port_s.S @@ -0,0 +1,72 @@ +@****************************************************************************** +@ EXTERN PARAMETERS +@****************************************************************************** + +.extern g_active_task +.extern g_preferred_ready_task +.extern krhino_stack_ovf_check + +@****************************************************************************** +@ EXPORT FUNCTIONS +@****************************************************************************** + +.global cpu_intrpt_save +.global cpu_intrpt_restore +.global cpu_task_switch +.global cpu_intrpt_switch + +@****************************************************************************** +@ EQUATES +@****************************************************************************** + +.equ SCB_ICSR, 0xE000ED04 @ Interrupt Control and State Register. +.equ ICSR_PENDSVSET, 0x10000000 @ Value to trigger PendSV exception. + +.equ SHPR3_PRI_14_15, 0xE000ED20 @ System Handler Priority Register 3 (PendSV + SysTick). +.equ SHPR3_PRI_LVL, 0xC0C00000 @ PendSV + SysTick priority level (lowest). + +@****************************************************************************** +@ CODE GENERATION DIRECTIVES +@****************************************************************************** +.text +.align 2 +.thumb +.syntax unified + +@****************************************************************************** +@ Functions: +@ size_t cpu_intrpt_save(void); +@ void cpu_intrpt_restore(size_t cpsr); +@****************************************************************************** +.thumb_func +cpu_intrpt_save: + MRS R0, PRIMASK + CPSID I + BX LR + +.thumb_func +cpu_intrpt_restore: + MSR PRIMASK, R0 + BX LR + +@****************************************************************************** +@ Functions: +@ void cpu_intrpt_switch(void); +@ void cpu_task_switch(void); +@****************************************************************************** +.thumb_func +cpu_task_switch: + LDR R0, =SCB_ICSR + LDR R1, =ICSR_PENDSVSET + STR R1, [R0] + BX LR + +.thumb_func +cpu_intrpt_switch: + LDR R0, =SCB_ICSR + LDR R1, =ICSR_PENDSVSET + STR R1, [R0] + BX LR + +.end + diff --git a/cores/asr650x/port/printf.c b/cores/asr650x/port/printf.c new file mode 100644 index 00000000..d74138d4 --- /dev/null +++ b/cores/asr650x/port/printf.c @@ -0,0 +1,345 @@ + + +#include +#include +#include +#include + +static int tiny_print( char **out, const char *format, va_list args, unsigned int buflen ); + +static void printchar(char **str, int c, char *buflimit) +{ + + if (str) { + if( buflimit == ( char * ) 0 ) { + /* Limit of buffer not known, write charater to buffer. */ + **str = (char)c; + ++(*str); + } + else if( ( ( unsigned long ) *str ) < ( ( unsigned long ) buflimit ) ) { + /* Withing known limit of buffer, write character. */ + **str = (char)c; + ++(*str); + } + } + else + { + //(void)uart_put_char(c); + UART_1_UartPutChar(c); + } +} + +#define PAD_RIGHT 1 +#define PAD_ZERO 2 + +static int prints(char **out, const char *string, int width, int pad, char *buflimit) +{ + register int pc = 0, padchar = ' '; + + if (width > 0) { + register int len = 0; + register const char *ptr; + for (ptr = string; *ptr; ++ptr) ++len; + if (len >= width) width = 0; + else width -= len; + if (pad & PAD_ZERO) padchar = '0'; + } + if (!(pad & PAD_RIGHT)) { + for ( ; width > 0; --width) { + printchar (out, padchar, buflimit); + ++pc; + } + } + for ( ; *string ; ++string) { + printchar (out, *string, buflimit); + ++pc; + } + for ( ; width > 0; --width) { + printchar (out, padchar, buflimit); + ++pc; + } + + return pc; +} + +/* the following should be enough for 64 bit int */ +#define PRINT_BUF_LEN_ll 20 + +static int printi(char **out, long long i, int b, int sg, int width, int pad, int letbase,int isll, char *buflimit) +{ + char print_buf[PRINT_BUF_LEN_ll]; + register char *s; + register int t, neg = 0, pc = 0; + register unsigned long long u = (unsigned int)i; + if(isll) + u = (unsigned long long)i; + if (i == 0) { + print_buf[0] = '0'; + print_buf[1] = '\0'; + return prints (out, print_buf, width, pad, buflimit); + } + + if (sg && b == 10 && i < 0) { + neg = 1; + if(isll) + u = (unsigned long long)-i; + else + u = (unsigned int)-i; + } + + s = print_buf + PRINT_BUF_LEN_ll-1; + *s = '\0'; + + while (u) { + if(isll) + t = (unsigned long long)u % b; + else + t = (unsigned int)u % b; + if( t >= 10 ) + t += letbase - '0' - 10; + *--s = (char)(t + '0'); + u /= b; + } + + if (neg) { + if( width && (pad & PAD_ZERO) ) { + printchar (out, '-', buflimit); + ++pc; + --width; + } + else { + *--s = '-'; + } + } + + return pc + prints (out, s, width, pad, buflimit); +} + +static int tiny_print( char **out, const char *format, va_list args, unsigned int buflen ) +{ + register int width, pad; + register int pc = 0; + char scr[2], *buflimit; + + if( buflen == 0 ){ + buflimit = ( char * ) 0; + } + else { + /* Calculate the last valid buffer space, leaving space for the NULL + terminator. */ + buflimit = ( *out ) + ( buflen - 1 ); + } + + for (; *format != 0; ++format) { + if (*format == '%') { + ++format; + width = pad = 0; + if (*format == '\0') break; + if (*format == '%') goto out; + if (*format == '-') { + ++format; + pad = PAD_RIGHT; + } + while (*format == '0') { + ++format; + pad |= PAD_ZERO; + } + for ( ; *format >= '0' && *format <= '9'; ++format) { + width *= 10; + width += *format - '0'; + } + if( *format == 's' ) { + register char *s = (char *)va_arg( args, int ); + pc += prints (out, s?s:"(null)", width, pad, buflimit); + continue; + } + if( *format == 'l' && *(format+1) == 'l'){ + if(*(format+2) == 'd'){ + format +=2; + pc += printi (out, va_arg( args, long long ), 10, 1, width, pad, 'a',1,buflimit); + continue; + } + if(*(format+2) == 'u'){ + format +=2; + pc += printi (out, va_arg( args, unsigned long long ), 10, 0, width, pad, 'a',1,buflimit); + continue; + } + } + if( *format == 'd' || *format == 'i' ) { + pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a',0, buflimit); + continue; + } + if( *format == 'x' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a',0, buflimit); + continue; + } + if( *format == 'X' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A',0, buflimit); + continue; + } + if( *format == 'u' ) { + pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a',0, buflimit); + continue; + } + if( *format == 'c' ) { + /* char are converted to int then pushed on the stack */ + scr[0] = (char)va_arg( args, int ); + scr[1] = '\0'; + pc += prints (out, scr, width, pad, buflimit); + continue; + } + } + else { + out: + printchar (out, *format, buflimit); + ++pc; + } + } + if (out) **out = '\0'; + va_end( args ); + return pc; +} +#ifdef CONSOLE_LOG_BUFFER +char log_buf[UART_CONSOLE_SIZE]; +struct circ_buf log_cb = { + .buf = log_buf, + .head = 0, + .tail = 0, +}; +char logs[256]; +#endif +int __wrap_printf(const char *format, ...) +{ + va_list args; + + va_start( args, format ); + #ifndef CONSOLE_LOG_BUFFER + return tiny_print( 0, format, args, 0 ); + #else + uint16_t log_len, circ_space_len; + char *p = logs; + log_len = tiny_print(&p, format, args, 0); + circ_space_len = CIRC_SPACE_TO_END(log_cb.head, log_cb.tail, UART_CONSOLE_SIZE); + if (log_len < circ_space_len) { + circ_space_len = log_len; + } + memcpy(log_cb.buf + log_cb.head, logs, circ_space_len); + log_cb.head = (log_cb.head + circ_space_len) & (UART_CONSOLE_SIZE - 1); + return log_len; + #endif +} + +int __wrap_sprintf(char *out, const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return tiny_print( &out, format, args, 0 ); +} + + +int __wrap_snprintf( char *buf, unsigned int count, const char *format, ... ) +{ + va_list args; + + ( void ) count; + + va_start( args, format ); + return tiny_print( &buf, format, args, count ); +} +int csp_printf(const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return tiny_print( 0, format, args, 0 ); +} +int __wrap_fflush(FILE* fp) +{ + return 0; +} +#ifdef TEST_PRINTF +int main(void) +{ + char *ptr = "Hello world!"; + char *np = 0; + int i = 5; + unsigned int bs = sizeof(int)*8; + int mi; + char buf[80]={0}; + + mi = (1 << (bs-1)) + 1; + printf_std("%s\n", ptr); + printf_std("printf_std test\n"); + printf_std("%s is null pointer\n", np); + printf_std("%d = 5\n", i); + printf_std("%d = - max int\n", mi); + printf_std("char %c = 'a'\n", 'a'); + printf_std("hex %x = ff\n", 0xff); + printf_std("hex %02x = 00\n", 0); + printf_std("signed %d = unsigned %u = hex %x\n", -3, -3, -3); + printf_std("%d %s(s)%", 0, "message"); + printf_std("\n"); + printf_std("%d %s(s) with %%\n", 0, "message"); + sprintf_std(buf, "justif: \"%-10s\"\n", "left"); + printf_std("%s", buf); + sprintf_std(buf, "justif: \"%10s\"\n", "right"); + printf_std("%s", buf); + sprintf_std(buf, " 3: %04d zero padded\n", 3); + printf_std("%s", buf); + sprintf_std(buf, " 3: %-4d left justif.\n", 3); + printf_std("%s", buf); + sprintf_std(buf, " 3: %4d right justif.\n", 3); + printf_std("%s", buf); + sprintf_std(buf, "-3: %04d zero padded\n", -3); + printf_std("%s", buf); + sprintf_std(buf, "-3: %-4d left justif.\n", -3); + printf_std("%s", buf); + sprintf_std(buf, "-3: %4d right justif.\n", -3); + printf_std("%s", buf); + + return 0; +} + +/* + * if you compile this file with + * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c + * you will get a normal warning: + * printf.c:214: warning: spurious trailing `%' in format + * this line is testing an invalid % at the end of the format string. + * + * this should display (on 32bit int machine) : + * + * Hello world! + * printf test + * (null) is null pointer + * 5 = 5 + * -2147483647 = - max int + * char a = 'a' + * hex ff = ff + * hex 00 = 00 + * signed -3 = unsigned 4294967293 = hex fffffffd + * 0 message(s) + * 0 message(s) with % + * justif: "left " + * justif: " right" + * 3: 0003 zero padded + * 3: 3 left justif. + * 3: 3 right justif. + * -3: -003 zero padded + * -3: -3 left justif. + * -3: -3 right justif. + */ + +#endif + +#if 0 +/* To keep linker happy. */ +int write( int i, char* c, int n) +{ + (void)i; + (void)n; + (void)c; + return 0; +} +#endif diff --git a/cores/asr650x/port/uart_port.c b/cores/asr650x/port/uart_port.c new file mode 100644 index 00000000..ae523649 --- /dev/null +++ b/cores/asr650x/port/uart_port.c @@ -0,0 +1,164 @@ +#include "hal/soc/soc.h" +#include "board.h" +#include "uart_port.h" +#include + +#include +#include +uart_dev_t uart_0; + +extern uint32_t HW_Get_MFT_Baud(void); + +#define UART_1_UART_BITS_TO_WAIT (2u) +int default_UART_Init(void) +{ + uart_0.port = STDIO_UART; + uart_0.config.baud_rate = HW_Get_MFT_Baud(); + uart_0.config.data_width = DATA_WIDTH_8BIT; + uart_0.config.parity = NO_PARITY; + uart_0.config.stop_bits = STOP_BITS_1; + uart_0.config.flow_control = FLOW_CONTROL_DISABLED; + + return hal_uart_init(&uart_0); +} + +extern void wakeup_from_uart(char ch); +extern void linkwan_serial_input(uint8_t cmd); +void UART_API(_customISR)(void) +{ + while(0u != (UART_API(_GetRxInterruptSourceMasked()) & UART_FLAG(_INTR_RX_NOT_EMPTY))) + { + char ch=0; + ch=(char)UART_API(_UartGetChar()); + UART_API(_ClearRxInterruptSource)(UART_FLAG(_INTR_RX_NOT_EMPTY)); + +//#ifndef LOW_POWER_DISABLE + //wakeup_from_uart(ch); +//#endif + + if(isprint(ch) || ch == '\r' || ch == '\n') { + //linkwan_serial_input(ch); +#ifndef CONFIG_PRINT_ECHO_DISABLE + UART_API(_UartPutChar(ch)); +#endif + } + } + /* UART done */ + if(0u != (UART_API(_GetTxInterruptSourceMasked)() & UART_FLAG(_INTR_TX_UART_DONE))) + { + UART_API(_ClearTxInterruptSource)(UART_FLAG(_INTR_TX_UART_DONE)); + } +} + +int32_t hal_uart_init(uart_dev_t *uart) +{ + switch(uart->port) + { + case UART0: + UART_API(_SetCustomInterruptHandler)(&UART_API(_customISR)); + UART_API(_Start)(); + break; + + default: + break; + } + return 0; +} + +int32_t hal_uart_send(uart_dev_t *uart, const void *data, uint32_t size, uint32_t timeout) +{ + uint8 *pdata = (uint8 *)data; + + (void) timeout; + + if((uart == NULL) || (data == NULL)) + { + return -1; + } + + switch(uart->port) + { + case UART0: + UART_API(_SpiUartPutArray)(pdata, size); + break; + + default: + break; + } return 0; +} + +int32_t hal_uart_recv(uart_dev_t *uart, void *data, uint32_t expect_size, uint32_t timeout) +{ + uint32 *pdata = (uint32 *)data; + uint32 i = 0; + + (void)timeout; + + switch(uart->port) + { + case UART0: + for(i = 0; i < expect_size; i++) + { + *pdata = UART_API(_UartGetChar()); + } + break; + + default: + break; + } + + return 0; +} + +int32_t hal_uart_finalize(uart_dev_t *uart) +{ + (void)uart; + + switch(uart->port) + { + case UART0: + UART_API(_Stop()); + break; + + default: + break; + } + + return 0; +} + +void uart_put_char(int c) +{ + hal_uart_send(&uart_0,&c,1,3000); +} +uint8 uart_pre_deepsleep(void) +{ + uint32_t div = (UART_1_SCBCLK_DIV_REG >> 8) + 1; + uint32_t bitTime = div*UART_1_UART_OVS_FACTOR/(CYDEV_BCLK__HFCLK__HZ/1000000) + 1; + uint8 bitsToWait = UART_1_UART_BITS_TO_WAIT; + uint8 enterDeepSleep = 1u; + + UART_1_skipStart = bitTime<25?0:1; + + while (0 != (UART_1_SpiUartGetTxBufferSize() + UART_1_GET_TX_FIFO_SR_VALID)) { + ; + } + if (0 == UART_1_SpiUartGetRxBufferSize()) { + UART_1_Sleep(); + while (0 != bitsToWait) { + CyDelayUs(bitTime); + --bitsToWait; + if (0 != UART_1_GET_RX_FIFO_SR_VALID) { + enterDeepSleep = 0; + break; + } + } + if (0 != enterDeepSleep) { + return 1; + } else { + return 0; + } + } + + return 0; +} diff --git a/cores/asr650x/projects/CubeCellLib.a b/cores/asr650x/projects/CubeCellLib.a new file mode 100644 index 00000000..f36bb350 Binary files /dev/null and b/cores/asr650x/projects/CubeCellLib.a differ diff --git a/cores/asr650x/projects/PSoC4/Bootloadable_1.c b/cores/asr650x/projects/PSoC4/Bootloadable_1.c new file mode 100644 index 00000000..b212da69 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/Bootloadable_1.c @@ -0,0 +1,270 @@ +/****************************************************************************//** +* \file Bootloadable_1.c +* \version 1.60 +* +* \brief +* Provides an API for the Bootloadable application. +* +******************************************************************************** +* \copyright +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "Bootloadable_1.h" + +/** + \defgroup functions_group Functions + @{ +*/ + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) +static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \ + ; +#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + +/******************************************************************************* +* Function Name: Bootloadable_1_Load +****************************************************************************//** +* +* \brief +* Schedules the Bootloader/Launcher to be launched and then performs +* a software reset to launch it +* +* \return +* This method will never return. It will load a new application and reset +* the device. +* +*******************************************************************************/ +void Bootloadable_1_Load(void) +{ + /* Schedule Bootloader to start after reset */ + Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_SCHEDULE_BTLDR); + + CySoftwareReset(); +} + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) +/******************************************************************************* +* Function Name: Bootloadable_1_GetActiveApplication +****************************************************************************//** +* +* \brief +* Gets the application which will be loaded after a next reset event. +* NOTE Intended for the combination project type ONLY! +* +* \return +* A number of the current active application set in the metadata section. +* \n 0 - app#0 is set as active. +* \n 1 - app#1 is set as active. +* +* \note If neither of the applications is set active, then the API returns 0x02. +* +*******************************************************************************/ +uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \ + +{ + uint8 result = Bootloadable_1_MD_BTLDB_ACTIVE_NONE; + + if (0u != Bootloadable_1_GET_CODE_DATA( \ + Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_0))) + { + result = Bootloadable_1_MD_BTLDB_ACTIVE_0; + } + else if (0u != Bootloadable_1_GET_CODE_DATA( \ + Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_1))) + { + result = Bootloadable_1_MD_BTLDB_ACTIVE_1; + } + else + { + /*Do nothing, result is none*/ + } + + return (result); +} + +/******************************************************************************* +* Function Name: Bootloadable_1_SetActiveApplication +****************************************************************************//** +* +* \brief +* Sets the application which will be loaded after a next reset event. +* +* \details +* Theory: +* This API sets in the Flash (metadata section) the given active application +* number. +* +* NOTE The active application number is not set directly, but the boolean +* mark instead means that the application is active or not for the relative +* metadata. Both metadata sections are updated. For example, if the second +* application is to be set active, then in the metadata section for the first +* application there will be a "0" written, which means that it is not active, and +* for the second metadata section there will be a "1" written, which means that it is +* active. +* +* NOTE Intended for the combination project type ONLY! +* +* \param appId +* The active application number to be written to flash (metadata section) +* NOTE Possible values are: +* 0 - for the first application +* 1 - for the second application. +* Any other number is considered invalid. +* +* \return +* A status of writing to flash operation. +* \n CYRET_SUCCESS - Returned if appId was successfully changed. +* \n CYRET_BAD_PARAM - Returned if the parameter appID passed to the function has the +* same value as the active application ID. +* \note - The other non-zero value is considered as a failure during writing to flash. +* +* \note - This API does not update Bootloader_activeApp variable. +* +*******************************************************************************/ +cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \ + +{ + cystatus result = CYRET_SUCCESS; + + uint8 CYDATA idx; + + /* If invalid application number */ + if (appId > Bootloadable_1_MD_BTLDB_ACTIVE_1) + { + result = CYRET_BAD_PARAM; + } + else + { + /* If appID has same value as active application ID */ + if (1u == Bootloadable_1_GET_CODE_DATA(Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId))) + { + result = CYRET_BAD_PARAM; + } + else + { + /* Updating metadata section */ + for(idx = 0u; idx < Bootloadable_1_MAX_NUM_OF_BTLDB; idx++) + { + result |= Bootloadable_1_WriteFlashByte((uint32) Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(idx), \ + (uint8)(idx == appId)); + } + } + } + + return (result); +} + +/******************************************************************************* +* Function Name: Bootloadable_1_WriteFlashByte +****************************************************************************//** +* +* \brief +* This API writes to flash the specified data. +* +* \param address +* The address in flash. +* +* \param inputValue +* One-byte data. +* +* \return +* A status of the writing to flash procedure. +* +*******************************************************************************/ +static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \ + +{ + cystatus result = CYRET_SUCCESS; + uint32 flsAddr = address - CYDEV_FLASH_BASE; + uint8 rowData[CYDEV_FLS_ROW_SIZE]; + + #if !(CY_PSOC4) + uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); + #endif /* !(CY_PSOC4) */ + + #if (CY_PSOC4) + uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE); + #else + uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); + #endif /* (CY_PSOC4) */ + + uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); + uint16 idx; + + for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) + { + rowData[idx] = (uint8)Bootloadable_1_GET_CODE_DATA(baseAddr + idx); + } + + rowData[address % CYDEV_FLS_ROW_SIZE] = inputValue; + + #if(CY_PSOC4) + result = CySysFlashWriteRow((uint32) rowNum, rowData); + #else + result = CyWriteRowData(arrayId, rowNum, rowData); + #endif /* (CY_PSOC4) */ + + #if(CY_PSOC5) + /*************************************************************************** + * When writing to flash, data in the instruction cache can become stale. + * Therefore, the cache data does not correlate to the data just written to + * flash. A call to CyFlushCache() is required to invalidate the data in the + * cache and force fresh information to be loaded from flash. + ***************************************************************************/ + CyFlushCache(); + #endif /* (CY_PSOC5) */ + return (result); +} +#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ +/** @} functions_group */ + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +*******************************************************************************/ +void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) +{ + uint32 flsAddr = address - CYDEV_FLASH_BASE; + uint8 rowData[CYDEV_FLS_ROW_SIZE]; + + #if !(CY_PSOC4) + uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); + #endif /* !(CY_PSOC4) */ + + #if (CY_PSOC4) + uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE); + #else + uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); + #endif /* (CY_PSOC4) */ + + uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); + uint16 idx; + + + for (idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) + { + rowData[idx] = Bootloadable_1_GET_CODE_DATA(baseAddr + idx); + } + rowData[address % CYDEV_FLS_ROW_SIZE] = runType; + + #if(CY_PSOC4) + (void) CySysFlashWriteRow((uint32) rowNum, rowData); + #else + (void) CyWriteRowData(arrayId, rowNum, rowData); + #endif /* (CY_PSOC4) */ + + #if(CY_PSOC5) + /*************************************************************************** + * When writing to flash, data in the instruction cache can become obsolete. + * Therefore, the cache data does not correlate to the data just written to + * flash. A call to CyFlushCache() is required to invalidate the data in the + * cache and force fresh information to be loaded from flash. + ***************************************************************************/ + CyFlushCache(); + #endif /* (CY_PSOC5) */ +} + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/Bootloadable_1.h b/cores/asr650x/projects/PSoC4/Bootloadable_1.h new file mode 100644 index 00000000..acfe0c37 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/Bootloadable_1.h @@ -0,0 +1,200 @@ +/****************************************************************************//** +* \file Bootloadable_1.c +* \version 1.60 +* +* \brief +* Provides an API for the Bootloadable application. The API includes a +* single function for starting the Bootloader. +* +******************************************************************************** +* \copyright +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#ifndef CY_BOOTLOADABLE_Bootloadable_1_H +#define CY_BOOTLOADABLE_Bootloadable_1_H + +#include "cydevice_trm.h" +#include "CyFlash.h" + + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component Bootloadable_v1_60 requires cy_boot v3.0 or later +#endif /* !defined (CY_PSOC5LP) */ + + +#ifndef CYDEV_FLASH_BASE + #define CYDEV_FLASH_BASE CYDEV_FLS_BASE + #define CYDEV_FLASH_SIZE CYDEV_FLS_SIZE +#endif /* CYDEV_FLASH_BASE */ + +#if(CY_PSOC3) + #define Bootloadable_1_GET_CODE_DATA(idx) (*((uint8 CYCODE *) (idx))) +#else + #define Bootloadable_1_GET_CODE_DATA(idx) (*((uint8 *)(CYDEV_FLASH_BASE + (idx)))) +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* This variable is used by the Bootloader/Bootloadable components to schedule which +* application will be started after a software reset. +*******************************************************************************/ +#if (CY_PSOC4) + #if defined(__ARMCC_VERSION) + __attribute__ ((section(".bootloaderruntype"), zero_init)) + #elif defined (__GNUC__) + __attribute__ ((section(".bootloaderruntype"))) + #elif defined (__ICCARM__) + #pragma location=".bootloaderruntype" + #endif /* defined(__ARMCC_VERSION) */ + extern volatile uint32 cyBtldrRunType; +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Gets the reason for a device reset +*******************************************************************************/ +#if(CY_PSOC4) + #define Bootloadable_1_RES_CAUSE_RESET_SOFT (0x10u) + #define Bootloadable_1_GET_RUN_TYPE \ + (((CY_GET_REG32(CYREG_RES_CAUSE) & Bootloadable_1_RES_CAUSE_RESET_SOFT) > 0u) \ + ? (cyBtldrRunType) \ + : 0u) +#else + #define Bootloadable_1_GET_RUN_TYPE (CY_GET_REG8(CYREG_RESET_SR0) & \ + (Bootloadable_1_START_BTLDR | Bootloadable_1_START_APP)) +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Schedule the Bootloader/Bootloadable to be run after a software reset. +*******************************************************************************/ +#if(CY_PSOC4) + #define Bootloadable_1_SET_RUN_TYPE(x) (cyBtldrRunType = (x)) +#else + #define Bootloadable_1_SET_RUN_TYPE(x) CY_SET_REG8(CYREG_RESET_SR0, (x)) +#endif /* (CY_PSOC4) */ + + + +/*************************************** +* Function Prototypes +***************************************/ +extern void Bootloadable_1_Load(void) ; + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from version 1.10. +*******************************************************************************/ +#define CYBTDLR_SET_RUN_TYPE(x) Bootloadable_1_SET_RUN_TYPE(x) + +/******************************************************************************* +* Bootloadable's declarations for in-app bootloading. +*******************************************************************************/ +#define Bootloadable_1_MD_BTLDB_ACTIVE_0 (0x00u) + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + #define Bootloadable_1_MAX_NUM_OF_BTLDB (0x02u) + #define Bootloadable_1_MD_BTLDB_ACTIVE_1 (0x01u) + #define Bootloadable_1_MD_BTLDB_ACTIVE_NONE (0x02u) + #define Bootloadable_1_MD_SIZEOF (64u) + #define Bootloadable_1_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \ + Bootloadable_1_MD_SIZEOF)) + #define Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId) (Bootloadable_1_MD_BASE_ADDR(appId) + 16u) + +#else + #define Bootloadable_1_MAX_NUM_OF_BTLDB (0x01u) +#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + +/* Mask used to indicate starting application */ +#define Bootloadable_1_SCHEDULE_BTLDB (0x80u) +#define Bootloadable_1_SCHEDULE_BTLDR (0x40u) +#define Bootloadable_1_SCHEDULE_MASK (0xC0u) +/******************************************************************************* +* API prototypes +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \ + ; + cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \ + ; +#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from version 1.20 +*******************************************************************************/ +#define Bootloadable_1_START_APP (0x80u) +#define Bootloadable_1_START_BTLDR (0x40u) +#define Bootloadable_1_META_DATA_SIZE (64u) +#define Bootloadable_1_META_APP_CHECKSUM_OFFSET (0u) + +#if(CY_PSOC3) + + #define Bootloadable_1_APP_ADDRESS uint16 + #define Bootloadable_1_GET_CODE_WORD(idx) (*((uint32 CYCODE *) (idx))) + + /* Offset by 2 from 32 bit start because only 16 bits are needed */ + #define Bootloadable_1_META_APP_ADDR_OFFSET (3u) + #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET (7u) + #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET (11u) + #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET (15u) + +#else + + #define Bootloadable_1_APP_ADDRESS uint32 + #define Bootloadable_1_GET_CODE_WORD(idx) (*((uint32 *)(CYDEV_FLASH_BASE + (idx)))) + + #define Bootloadable_1_META_APP_ADDR_OFFSET (1u) + #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET (5u) + #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET (9u) + #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET (13u) + +#endif /* (CY_PSOC3) */ + +#define Bootloadable_1_META_APP_ACTIVE_OFFSET (16u) +#define Bootloadable_1_META_APP_VERIFIED_OFFSET (17u) + +#define Bootloadable_1_META_APP_BL_BUILD_VER_OFFSET (18u) +#define Bootloadable_1_META_APP_ID_OFFSET (20u) +#define Bootloadable_1_META_APP_VER_OFFSET (22u) +#define Bootloadable_1_META_APP_CUST_ID_OFFSET (24u) + +#define Bootloadable_1_SetFlashRunType(runType) \ + Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType)) + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions are intended for the application, use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* NOTE Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ; +#if(CY_PSOC4) + #define Bootloadable_1_SOFTWARE_RESET CySoftwareReset() +#else + #define Bootloadable_1_SOFTWARE_RESET CySoftwareReset() +#endif /* (CY_PSOC4) */ + +#if(CY_PSOC4) + extern uint8 appRunType; +#endif /* (CY_PSOC4) */ + + +#endif /* CY_BOOTLOADABLE_Bootloadable_1_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/Cm0plusIar.icf b/cores/asr650x/projects/PSoC4/Cm0plusIar.icf new file mode 100644 index 00000000..5a8c937c --- /dev/null +++ b/cores/asr650x/projects/PSoC4/Cm0plusIar.icf @@ -0,0 +1,226 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x0; +define symbol __ICFEDIT_region_ROM_end__ = 131072 - 1; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + 16384 - 1; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0800; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + + +/******** Definitions ********/ +define symbol CY_FLASH_SIZE = 131072; +define symbol CY_APPL_ORIGIN = 0; +define symbol CY_FLASH_ROW_SIZE = 256; +define symbol CY_APPL_LOADABLE = 1; +define symbol CY_APPL_LOADER = 0; +define symbol CY_APPL_NUM = 1; +define symbol CY_METADATA_SIZE = 64; +define symbol CY_APPL_MAX = 1; +define symbol CY_CHECKSUM_EXCLUDE_SIZE = 0; +define symbol CY_APPL_FOR_STACK_AND_COPIER = 0; +define symbol CY_FIRST_AVAILABLE_META_ROW = 1; + +define symbol CYDEV_IS_IMPORTING_CODE = 0; +define symbol CYDEV_IS_EXPORTING_CODE = 0; + + +include "cybootloader.icf"; +if (!CY_APPL_LOADABLE) { + define symbol CYDEV_BTLDR_SIZE = 0; + + /* The first 0x100 Flash bytes become unavailable right after remapping of the vector table to RAM. + * This space should be used for .romvectors section. + */ + define block ROMVEC with size = 0x100 {readonly section .romvectors}; + + define block APPL with fixed order {block ROMVEC, section .psocinit, readonly}; +} else { + define block APPL with fixed order {readonly section .romvectors, section .psocinit, readonly}; +} + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, last block CSTACK}; + +define block RAMVEC with fixed order {readwrite section .ramvectors, readwrite section .bootloaderruntype}; + +if (CY_APPL_LOADABLE) +{ + define block LOADER { readonly section .cybootloader }; +} + +/* The address of the Flash row next after the Bootloader image */ +define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE + + ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ? + (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0); + +/* The start address of Standard/Loader/Loadable#1 image */ +define symbol CY_APPL1_START = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END; + +/* The number of metadata records located at the end of Flash */ +define symbol CY_METADATA_CNT = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0); + +/* The application area size measured in rows */ +define symbol CY_APPL_ROW_CNT = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT; + +/* The start address of Loadable#2 image if any */ +define symbol CY_APPL2_START = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE; + +/* The current image (Standard/Loader/Loadable) start address */ +define symbol CY_APPL_START = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START; + +/* Define APPL region that will limit application size */ +define region APPL_region = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE]; + + +/****** Initializations ******/ +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { readwrite section .ramvectors, readwrite section .bootloaderruntype }; + +/******** Placements *********/ +if (CY_APPL_LOADABLE) +{ +".cybootloader" : place at start of ROM_region {block LOADER}; +} + +"APPL" : place at start of APPL_region {block APPL}; + +"RAMVEC" : place at start of RAM_region { block RAMVEC }; +"readwrite" : place in RAM_region { readwrite }; +"HSTACK" : place at end of RAM_region { block HSTACK}; + +keep { section .cybootloader, + section .cyloadermeta, + section .cyloadablemeta, + section .cy_checksum_exclude, + section .cyflashprotect, + section .cymeta, + section .cychipprotect }; + + +/******************************************************************************* +* Bootloader Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +if ((CY_APPL_LOADER)&&!(CY_APPL_LOADABLE)) +{ + ".cyloadermeta" : place at address mem : (CY_FLASH_SIZE - CY_METADATA_SIZE) { readonly section .cyloadermeta }; +} +else +{ + if ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + { + ".cyloadermeta" : place at address mem : (CY_FLASH_SIZE - CY_METADATA_SIZE) { readonly section .cyloadermeta }; + } + else + { + /* Must be part of the image, but beyond rom memory. */ + ".cyloadermeta" : place at address mem : 0x90700000 { readonly section .cyloadermeta }; + } +} + + + +/******************************************************************************* +* Bootloadable Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +if (CY_APPL_LOADABLE) +{ + /* General case */ + if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + { + define symbol CY_APPL_METADATA_SLOT_NUM = (CY_APPL_NUM - 1); + } + + /* Stack Project (SP) */ + if (CYDEV_IS_EXPORTING_CODE == 1) + { + define symbol CY_APPL_METADATA_SLOT_NUM = (0); + } + + /* App for SP+L */ + if ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + { + define symbol CY_APPL_METADATA_SLOT_NUM = (1); + } + + define symbol CYLOADABLEMETA_START_ADDR = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_METADATA_SLOT_NUM - CY_METADATA_SIZE); + + + ".cyloadablemeta" : place at address mem : CYLOADABLEMETA_START_ADDR { readonly section .cyloadablemeta }; +} + + +/******************************************************************************* +* Checksum Exclude Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +if (CY_APPL_LOADABLE) +{ + /* Align size to the flash row size */ + define symbol CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED = CY_CHECKSUM_EXCLUDE_SIZE + ((CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE)) : 0); + + if (CY_CHECKSUM_EXCLUDE_SIZE != 0) + { + + /* General case */ + if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + { + if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2)) + { + define symbol CY_CHECKSUM_EXCLUDE_START = CY_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + } + else + { + define symbol CY_CHECKSUM_EXCLUDE_START = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + } + + define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0); + + ".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude }; + } + + + if (CY_APPL_MAX == 1) + { + /* Stack Project (SP) */ + if (CYDEV_IS_EXPORTING_CODE == 1) + { + ".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude }; + } + + /* App for SP+L */ + if ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + { + define symbol CY_CHECKSUM_EXCLUDE_START = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * 2) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + + define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0); + + ".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude }; + } + } + + } /* (CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED != 0) */ +} +else +{ + ".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude }; +} + + +".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect }; +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; +".cychipprotect" : place at address mem : 0x90600000 { readonly section .cychipprotect }; + + +/* EOF */ diff --git a/cores/asr650x/projects/PSoC4/Cm0plusRealView.scat b/cores/asr650x/projects/PSoC4/Cm0plusRealView.scat new file mode 100644 index 00000000..0e42c37c --- /dev/null +++ b/cores/asr650x/projects/PSoC4/Cm0plusRealView.scat @@ -0,0 +1,245 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************** +;* \file Cm0RealView.scat +;* \version 5.70 +;* +;* \brief This Linker Descriptor file describes the memory layout of the PSOC4 +;* device family. The memory layout of the final binary and hex images as well +;* as the placement in the PSOC4 memory is described. +;* +;* romvectors: Cypress default Interrupt service routine vector table. +;* +;* This is the ISR vector table at bootup. Used only for the reset vector. +;* +;* +;* ramvectors: Cypress ram interrupt service routine vector table. +;* +;* This is the ISR vector table used by the application. +;* +;******************************************************************************** +;* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;********************************************************************************/ +#include "cyfitter.h" +#include "cycodeshareimport.scat" + +#define CY_FLASH_SIZE 131072 +#define CY_APPL_ORIGIN 0 +#define CY_FLASH_ROW_SIZE 256 +#define CY_METADATA_SIZE 64 + +#define CY_APPL_FOR_STACK_AND_COPIER 0 +#define CY_CHECKSUM_EXCLUDE_SIZE AlignExpr(0, CY_FLASH_ROW_SIZE) +#define CY_APPL_NUM 1 +#define CY_APPL_MAX 1 + + +; Define application base address +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + #if CY_APPL_ORIGIN + #define APPL1_START CY_APPL_ORIGIN + #else + #define APPL1_START AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE) + #endif + + #define APPL_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE)) + +#else + + #define APPL_START 0 + +#endif + + +; Place Bootloader at the beginning of Flash +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + CYBOOTLOADER 0 + { + .cybootloader +0 + { + * (.cybootloader) + } + } + + #if CY_APPL_ORIGIN + ScatterAssert(APPL_START >= LoadLimit(CYBOOTLOADER)) + #endif + +#endif + + +APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START) +{ + VECTORS +0 + { + * (.romvectors) + } + + RELOCATION +0 + { + * (.psocinit) + } + + CODE ((ImageLimit(RELOCATION) < 0x100) ? 0x100 : ImageLimit(RELOCATION)) FIXED + { + * (+RO) + } + + ISRVECTORS (0x20000000) UNINIT + { + * (.ramvectors, +FIRST) + } + + #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) + BTLDR_RUN +0 UNINIT + { + * (.bootloaderruntype) + } + #endif + + NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + DATA +1 + { + .ANY (+RW, +ZI) + } + + ARM_LIB_HEAP (0x20000000 + 16384 - 0x1000 - 0x0800) EMPTY 0x1000 + { + } + + ARM_LIB_STACK (0x20000000 + 16384) EMPTY -0x0800 + { + } +} + + +/******************************************************************************* +* Checksum Exclude Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + + #if (0 != 0) + + /* General case */ + #if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + #if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2)) + #define CY_CHECKSUM_APPL2_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ), CY_FLASH_ROW_SIZE)) + #define CY_CHECKSUM_EXCLUDE_START AlignExpr(CY_CHECKSUM_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #else + #define CY_CHECKSUM_EXCLUDE_START AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #endif + #endif + + #if (CY_APPL_MAX == 1) + + /* Stack Project (SP) */ + #if (CYDEV_IS_EXPORTING_CODE == 1) + #define CY_CHECKSUM_EXCLUDE_START (+0) + #endif + + /* App for SP+L */ + #if ((CYDEV_IS_IMPORTING_CODE == 1) && (1 == 2)) + #define CY_CHECKSUM_EXCLUDE_START AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * 2) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #endif + #endif + + CY_CHECKSUM_EXCLUDE (CY_CHECKSUM_EXCLUDE_START) + { + .cy_checksum_exclude +0 + { + * (.cy_checksum_exclude) + } + } + + #endif /* (0 != 0) */ + +#endif + + +/******************************************************************************* +* Bootloader Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LAUNCHER || \ + CY_APPL_FOR_STACK_AND_COPIER) + + CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE) + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#endif + + +/******************************************************************************* +* Bootloadable Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* General case */ + #if ((CYDEV_IS_EXPORTING_CODE == 0) && (CYDEV_IS_IMPORTING_CODE == 0)) + #define CY_APPL_METADATA_SLOT_NUM (CY_APPL_NUM - 1) + #endif + + /* Stack Project (SP) */ + #if (CYDEV_IS_EXPORTING_CODE == 1) + #define CY_APPL_METADATA_SLOT_NUM (0) + #endif + + /* App for SP+L */ + #if ((CYDEV_IS_IMPORTING_CODE == 1) && (1 == 2)) + #define CY_APPL_METADATA_SLOT_NUM (1) + #endif + + #define CYLOADABLEMETA_START_ADDR (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_METADATA_SLOT_NUM - CY_METADATA_SIZE) + + CYLOADABLEMETA (CYLOADABLEMETA_START_ADDR) + { + .cyloadablemeta +0 { * (.cyloadablemeta) } + } +#endif + +CYFLASHPROTECT 0x90400000 +{ + .cyflashprotect +0 { * (.cyflashprotect) } +} + +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +CYCHIPPROTECT 0x90600000 +{ + .cychipprotect +0 { * (.cychipprotect) } +} + + +/******************************************************************************* +* Bootloader Metadata Section. Must be part of the image, but beyond rom memory. +*******************************************************************************/ +#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) && \ + !(CY_APPL_FOR_STACK_AND_COPIER)) + + CYLOADERMETA +0 + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#endif + diff --git a/cores/asr650x/projects/PSoC4/Cm0plusStart.c b/cores/asr650x/projects/PSoC4/Cm0plusStart.c new file mode 100644 index 00000000..e3d97801 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/Cm0plusStart.c @@ -0,0 +1,545 @@ +/***************************************************************************//** +* \file Cm0Start.c +* \version 5.70 +* +* \brief Startup code for the ARM CM0. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "cydevice_trm.h" +#include "cytypes.h" +#include "cyfitter_cfg.h" +#include "CyLib.h" +#include "cyfitter.h" +#include "cyapicallbacks.h" + +#define CY_NUM_VECTORS (CY_INT_IRQ_BASE + CY_NUM_INTERRUPTS) + +#if (CY_IP_CPUSS_CM0) + #define CY_CPUSS_CONFIG_VECT_IN_RAM (( uint32 ) 0x01) +#endif /* (CY_IP_CPUSS_CM0) */ + + +#if (CY_IP_CPUSS_CM0) + /* CPUSS Configuration register */ + #define CY_CPUSS_CONFIG_REG (*(reg32 *) CYREG_CPUSS_CONFIG) + #define CY_CPUSS_CONFIG_PTR ( (reg32 *) CYREG_CPUSS_CONFIG) +#endif /* (CY_IP_CPUSS_CM0) */ + + +#if defined (__ICCARM__) + #define CY_NUM_ROM_VECTORS (CY_NUM_VECTORS) +#else + #define CY_NUM_ROM_VECTORS (4u) +#endif /* defined (__ICCARM__) */ + +/* Vector table address in SRAM */ +#define CY_CPUSS_CONFIG_VECT_ADDR_IN_RAM (0x20000000u) + +#ifndef CY_SYS_INITIAL_STACK_POINTER + + #if defined(__ARMCC_VERSION) + #define CY_SYS_INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit) + #elif defined (__GNUC__) + #define CY_SYS_INITIAL_STACK_POINTER (&__cy_stack) + #elif defined (__ICCARM__) + #pragma language=extended + #pragma segment="CSTACK" + #define CY_SYS_INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) } + + extern void __iar_program_start( void ); + extern void __iar_data_init3 (void); + #endif /* (__ARMCC_VERSION) */ + +#endif /* CY_SYS_INITIAL_STACK_POINTER */ + + +#if defined(__GNUC__) + #include + extern int end; +#endif /* defined(__GNUC__) */ + +/* Extern functions */ +extern void CyBtldr_CheckLaunch(void); + +/* Function prototypes */ +void initialize_psoc(void); + +/* Global variables */ +#if !defined (__ICCARM__) + CY_NOINIT static uint32 cySysNoInitDataValid; +#endif /* !defined (__ICCARM__) */ + + +#if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) + + /******************************************************************************* + This variable is used by the Bootloader/Bootloadable components to schedule + what application will be started after a software reset. + *******************************************************************************/ + #if (__ARMCC_VERSION) + __attribute__ ((section(".bootloaderruntype"), zero_init)) + #elif defined (__GNUC__) + __attribute__ ((section(".bootloaderruntype"))) + #elif defined (__ICCARM__) + #pragma location=".bootloaderruntype" + #endif /* (__ARMCC_VERSION) */ + volatile uint32 cyBtldrRunType; + +#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) */ + + +/******************************************************************************* +* Function Name: IntDefaultHandler +****************************************************************************//** +* +* This function is called for all interrupts, other than a reset that is called +* before the system is setup. +* +*******************************************************************************/ +CY_NORETURN +CY_ISR(IntDefaultHandler) +{ + /*************************************************************************** + * We must not get here. If we do, a serious problem occurs, so go into + * an infinite loop. + ***************************************************************************/ + + #if defined(__GNUC__) + if (errno == ENOMEM) + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK + CyBoot_IntDefaultHandler_Enomem_Exception_Callback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK */ + + while(1) + { + /* Out Of Heap Space + * This can be increased in the System tab of the Design Wide Resources. + */ + } + } + else + #endif + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK + CyBoot_IntDefaultHandler_Exception_EntryCallback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */ + + while(1) + { + + } + } +} + +#if defined(__ARMCC_VERSION) + +/* Local function for device reset. */ +extern void Reset(void); + +/* Application entry point. */ +extern void $Super$$main(void); + +/* Linker-generated Stack Base addresses, Two Region and One Region */ +extern unsigned long Image$$ARM_LIB_STACK$$ZI$$Limit; + +/* RealView C Library initialization. */ +extern int __main(void); + + +/******************************************************************************* +* Function Name: Reset +****************************************************************************//** +* +* This function handles the reset interrupt for the MDK toolchains. +* This is the first bit of code that is executed at startup. +* +*******************************************************************************/ +void Reset(void) +{ + #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + /* The bootloadable application image is started at Reset() handler + * as a result of a branch instruction execution from the bootloader. + * So, the stack pointer needs to be reset to be sure that + * there is no garbage in the stack. + */ + register uint32_t msp __asm("msp"); + msp = (uint32_t)&Image$$ARM_LIB_STACK$$ZI$$Limit; + #endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + + #if(CY_IP_SRSSLT) + CySysWdtDisable(); + #endif /* (CY_IP_SRSSLT) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + __main(); +} + +/******************************************************************************* +* Function Name: $Sub$$main +****************************************************************************//** +* +* This function is called immediately before the users main +* +*******************************************************************************/ +__attribute__ ((noreturn, __noinline__)) +void $Sub$$main(void) +{ + initialize_psoc(); + + /* Call original main */ + $Super$$main(); + + while (1) + { + /* If main returns it is undefined what we should do. */ + } +} + +#elif defined(__GNUC__) + +/* Stack Base address */ +extern void __cy_stack(void); + +/* Application entry point. */ +extern int main(void); + +/* The static objects constructors initializer */ +extern void __libc_init_array(void); + +typedef unsigned char __cy_byte_align8 __attribute ((aligned (8))); + +struct __cy_region +{ + __cy_byte_align8 *init; /* Initial contents of this region. */ + __cy_byte_align8 *data; /* Start address of region. */ + size_t init_size; /* Size of initial data. */ + size_t zero_size; /* Additional size to be zeroed. */ +}; + +extern const struct __cy_region __cy_regions[]; +extern const char __cy_region_num __attribute__((weak)); +#define __cy_region_num ((size_t)&__cy_region_num) + + +/******************************************************************************* +* System Calls of the Red Hat newlib C Library +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: _exit +****************************************************************************//** +* +* Exit a program without cleaning up files. If your system doesn't provide +* this, it is best to avoid linking with subroutines that require it (exit, +* system). +* +* \param status: Status caused program exit. +* +*******************************************************************************/ +__attribute__((weak)) +void _exit(int status) +{ + CyHalt((uint8) status); + + while(1) + { + + } +} + + +/******************************************************************************* +* Function Name: _sbrk +****************************************************************************//** +* +* Increase program data space. As malloc and related functions depend on this, +* it is useful to have a working implementation. The following suffices for a +* standalone system; it exploits the symbol end automatically defined by the +* GNU linker. +* +* \param nbytes: The number of bytes requested (if the parameter value is positive) +* from the heap or returned back to the heap (if the parameter value is +* negative). +* +*******************************************************************************/ +__attribute__((weak)) +void * _sbrk (int nbytes) +{ + extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */ + void * returnValue; + + /* The statically held previous end of the heap, with its initialization. */ + static uint8 *heapPointer = (uint8 *) &end; /* Previous end */ + + if (((heapPointer + nbytes) - (uint8 *) &end) <= CYDEV_HEAP_SIZE) + { + returnValue = (void *) heapPointer; + heapPointer += nbytes; + } + else + { + errno = ENOMEM; + returnValue = (void *) -1; + } + + return (returnValue); +} + + +/******************************************************************************* +* Function Name: Start_c +****************************************************************************//** +* +* This function handles initializing the .data and .bss sections in +* preparation for running the standard c code. Once initialization is complete +* it will call main(). This function will never return. +* +*******************************************************************************/ +void Start_c(void) __attribute__ ((noreturn, noinline)); +void Start_c(void) +{ + #ifdef CY_BOOT_START_C_CALLBACK + CyBoot_Start_c_Callback(); + #else + unsigned regions = __cy_region_num; + const struct __cy_region *rptr = __cy_regions; + + /* Initialize memory */ + for (regions = __cy_region_num; regions != 0u; regions--) + { + uint32 *src = (uint32 *)rptr->init; + uint32 *dst = (uint32 *)rptr->data; + unsigned limit = rptr->init_size; + unsigned count; + + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = *src; + dst++; + src++; + } + limit = rptr->zero_size; + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = 0u; + dst++; + } + + rptr++; + } + + /* Invoke static objects constructors */ + __libc_init_array(); + (void) main(); + + while (1) + { + /* If main returns, make sure we don't return. */ + } + + #endif /* CY_BOOT_START_C_CALLBACK */ +} + + +/******************************************************************************* +* Function Name: Reset +****************************************************************************//** +* +* This function handles the reset interrupt for the GCC toolchain. This is +* the first bit of code that is executed at startup. +* +*******************************************************************************/ +void Reset(void) +{ + #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* The bootloadable application image is started at Reset() handler + * as a result of a branch instruction execution from the bootloader. + * So, the stack pointer needs to be reset to be sure that + * there is no garbage in the stack. + */ + __asm volatile ("MSR msp, %0\n" : : "r" ((uint32)&__cy_stack) : "sp"); + #endif /* CYDEV_PROJ_TYPE_LOADABLE */ + + #if(CY_IP_SRSSLT) + CySysWdtDisable(); + #endif /* (CY_IP_SRSSLT) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + Start_c(); +} + +#elif defined (__ICCARM__) + + +/******************************************************************************* +* Function Name: __low_level_init +****************************************************************************//** +* +* This function performs early initializations for the IAR Embedded +* Workbench IDE. It is executed in the context of reset interrupt handler +* before the data sections are initialized. +* +* \return The value that determines whether or not data sections should be +* initialized by the system startup code: +* 0 - skip data sections initialization; +* 1 - initialize data sections; +* +*******************************************************************************/ +#pragma inline = never +int __low_level_init(void) +{ + #if(CY_IP_SRSSLT) + CySysWdtDisable(); + #endif /* (CY_IP_SRSSLT) */ + +#if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); +#endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + /* Initialize data sections */ + __iar_data_init3(); + + initialize_psoc(); + + return 0; +} + +#endif /* __GNUC__ */ + + +/******************************************************************************* +* Ram Interrupt Vector table storage area. Must be placed at 0x20000000. +*******************************************************************************/ + +#if defined (__ICCARM__) + #pragma location=".ramvectors" +#elif defined (__ARMCC_VERSION) + #ifndef CY_SYS_RAM_VECTOR_SECTION + #define CY_SYS_RAM_VECTOR_SECTION __attribute__((section(".ramvectors"), zero_init)) + #endif /* CY_SYS_RAM_VECTOR_SECTION */ + CY_SYS_RAM_VECTOR_SECTION +#else + #ifndef CY_SYS_RAM_VECTOR_SECTION + #define CY_SYS_RAM_VECTOR_SECTION CY_SECTION(".ramvectors") + #endif /* CY_SYS_RAM_VECTOR_SECTION */ + CY_SYS_RAM_VECTOR_SECTION +#endif /* defined (__ICCARM__) */ +cyisraddress CyRamVectors[CY_NUM_VECTORS]; + + +/******************************************************************************* +* Rom Interrupt Vector table storage area. Must be 256-byte aligned. +*******************************************************************************/ + +#if defined(__ARMCC_VERSION) + /* Suppress diagnostic message 1296-D: extended constant initialiser used */ + #pragma diag_suppress 1296 +#endif /* defined(__ARMCC_VERSION) */ + +#if defined (__ICCARM__) + #pragma location=".romvectors" + const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] = +#else + #ifndef CY_SYS_ROM_VECTOR_SECTION + #define CY_SYS_ROM_VECTOR_SECTION CY_SECTION(".romvectors") + #endif /* CY_SYS_ROM_VECTOR_SECTION */ + CY_SYS_ROM_VECTOR_SECTION + const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] = +#endif /* defined (__ICCARM__) */ +{ + CY_SYS_INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ + #if defined (__ICCARM__) /* The reset handler 1 */ + __iar_program_start, + #else + (cyisraddress)&Reset, + #endif /* defined (__ICCARM__) */ + &IntDefaultHandler, /* The NMI handler 2 */ + &IntDefaultHandler, /* The hard fault handler 3 */ +}; + +#if defined(__ARMCC_VERSION) + #pragma diag_default 1296 +#endif /* defined(__ARMCC_VERSION) */ + + +/******************************************************************************* +* Function Name: initialize_psoc +****************************************************************************//** +* +* This function is used to initialize the PSoC chip before calling main. +* +*******************************************************************************/ +#if(defined(__GNUC__) && !defined(__ARMCC_VERSION)) +__attribute__ ((constructor(101))) +#endif /* (defined(__GNUC__) && !defined(__ARMCC_VERSION)) */ +void initialize_psoc(void) +{ + uint32 indexInit; + + #if(CY_IP_CPUSSV2) + #if (CY_IP_CPUSS_CM0) + /*********************************************************************** + * Make sure that Vector Table is located at 0000_0000 in Flash, before + * accessing RomVectors or calling functions that may be placed in + * .psocinit (cyfitter_cfg and ClockSetup). Note The CY_CPUSS_CONFIG_REG + * register is retention for the specified device family. + ***********************************************************************/ + CY_CPUSS_CONFIG_REG &= (uint32) ~CY_CPUSS_CONFIG_VECT_IN_RAM; + #endif /* (CY_IP_CPUSS_CM0) */ + #endif /* (CY_IP_CPUSSV2) */ + + /* Set Ram interrupt vectors to default functions. */ + for (indexInit = 0u; indexInit < CY_NUM_VECTORS; indexInit++) + { + CyRamVectors[indexInit] = (indexInit < CY_NUM_ROM_VECTORS) ? + #if defined (__ICCARM__) + __vector_table[indexInit].__fun : &IntDefaultHandler; + #else + RomVectors[indexInit] : &IntDefaultHandler; + #endif /* defined (__ICCARM__) */ + } + + /* Initialize configuration registers. */ + cyfitter_cfg(); + + #if !defined (__ICCARM__) + /* Actually, no need to clean this variable, just to make compiler happy. */ + cySysNoInitDataValid = 0u; + #endif /* !defined (__ICCARM__) */ + + #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) + + /* Need to make sure that this variable will not be optimized out */ + if (0u == cyBtldrRunType) + { + cyBtldrRunType = 0u; + } + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_STANDARD) */ + + #if (CY_IP_CPUSS_CM0) + /* Vector Table is located at 0x2000:0000 in SRAM */ + CY_CPUSS_CONFIG_REG |= CY_CPUSS_CONFIG_VECT_IN_RAM; + #else + (*(uint32 *)CYREG_CM0P_VTOR) = CY_CPUSS_CONFIG_VECT_ADDR_IN_RAM; + #endif /* (CY_IP_CPUSS_CM0) */ +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/CyBootAsmGnu.S b/cores/asr650x/projects/PSoC4/CyBootAsmGnu.S new file mode 100644 index 00000000..b4dd1118 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/CyBootAsmGnu.S @@ -0,0 +1,140 @@ +/***************************************************************************//** +* \file CyBootAsmGnu.s +* \version 5.70 +* +* \brief Assembly routines for GNU as. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +.syntax unified +.text +.thumb +.include "cyfittergnu.inc" + + +/******************************************************************************* +* Function Name: CyDelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* \param uint32 cycles: number of cycles to delay. +* +* \return +* None +* +*******************************************************************************/ +/* void CyDelayCycles(uint32 cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global CyDelayCycles +.func CyDelayCycles, CyDelayCycles +.type CyDelayCycles, %function +.thumb_func +CyDelayCycles: /* cycles bytes */ + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ CyDelayCycles_done /* 2 2 Skip if 0 */ +.IFDEF CYIPBLOCK_m0s8cpuss_VERSION + NOP /* 1 2 Loop alignment padding */ +.ELSE + .IFDEF CYIPBLOCK_s8srsslt_VERSION + .IFDEF CYIPBLOCK_m0s8cpussv2_VERSION + .IFDEF CYIPBLOCK_mxusbpd_VERSION + /* Do nothing */ + .ELSE + .IFDEF CYIPBLOCK_m0s8usbpd_VERSION + /* Do nothing */ + .ELSE + NOP /* 1 2 Loop alignment padding */ + .ENDIF + .ENDIF + .ENDIF + .ENDIF + /* Leave loop unaligned */ +.ENDIF +CyDelayCycles_loop: +/* For CM0+ branch instruction takes 2 CPU cycles, for CM0 it takes 3 cycles */ +.IFDEF CYDEV_CM0P_BASE + ADDS r0, r0, #1 /* 1 2 Increment counter */ + SUBS r0, r0, #2 /* 1 2 Decrement counter by 2 */ + BNE CyDelayCycles_loop /* 2 2 2 CPU cycles (if branche is taken)*/ + NOP /* 1 2 Loop alignment padding */ +.ELSE + SUBS r0, r0, #1 /* 1 2 Decrement counter */ + BNE CyDelayCycles_loop /* 3 2 3 CPU cycles (if branche is taken)*/ + NOP /* 1 2 Loop alignment padding */ + NOP /* 1 2 Loop alignment padding */ +.ENDIF +CyDelayCycles_done: + NOP /* 1 2 Loop alignment padding */ + BX lr /* 3 2 */ +.endfunc + + +/******************************************************************************* +* Function Name: CyEnterCriticalSection +****************************************************************************//** +* +* CyEnterCriticalSection disables interrupts and returns a value indicating +* whether interrupts were previously enabled (the actual value depends on +* whether the device is PSoC 3 or PSoC 5). +* +* Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +* with interrupts still enabled. The test and set of the interrupt bits is not +* atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a +* corrupting processor state, it must be the policy that all interrupt routines +* restore the interrupt enable bits as they were found on entry. +* +* \return +* uint8 +* Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8 CyEnterCriticalSection(void) */ +.global CyEnterCriticalSection +.func CyEnterCriticalSection, CyEnterCriticalSection +.type CyEnterCriticalSection, %function +.thumb_func +CyEnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + CPSID I /* Disable interrupts */ + BX lr +.endfunc + + +/******************************************************************************* +* Function Name: CyExitCriticalSection +****************************************************************************//** +* +* CyExitCriticalSection re-enables interrupts if they were enabled before +* CyEnterCriticalSection was called. The argument should be the value returned +* from CyEnterCriticalSection. +* +* \param uint8 savedIntrStatus: +* Saved interrupt status returned by the CyEnterCriticalSection function. +* +* \return +* None +* +*******************************************************************************/ +/* void CyExitCriticalSection(uint8 savedIntrStatus) */ +.global CyExitCriticalSection +.func CyExitCriticalSection, CyExitCriticalSection +.type CyExitCriticalSection, %function +.thumb_func +CyExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr +.endfunc + +.end + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/CyBootAsmIar.s b/cores/asr650x/projects/PSoC4/CyBootAsmIar.s new file mode 100644 index 00000000..81aa2afa --- /dev/null +++ b/cores/asr650x/projects/PSoC4/CyBootAsmIar.s @@ -0,0 +1,132 @@ +;------------------------------------------------------------------------------- +; \file CyBootAsmIar.s +; \version 5.70 +; +; \brief Assembly routines for IAR Embedded Workbench IDE. +; +;------------------------------------------------------------------------------- +; Copyright 2013-2018, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + SECTION .text:CODE:ROOT(4) + PUBLIC CyDelayCycles + PUBLIC CyEnterCriticalSection + PUBLIC CyExitCriticalSection + THUMB + INCLUDE cyfitter.h + + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + +CyDelayCycles: + ADDS r0, r0, #2 + LSRS r0, r0, #2 + BEQ CyDelayCycles_done + #ifdef CYIPBLOCK_m0s8cpuss_VERSION + NOP ; 1 2 Loop alignment padding + #else + #ifdef CYIPBLOCK_s8srsslt_VERSION + #ifdef CYIPBLOCK_m0s8cpussv2_VERSION + #ifdef CYIPBLOCK_mxusbpd_VERSION + /* Do nothing */ + #else + #ifdef CYIPBLOCK_m0s8usbpd_VERSION + /* Do nothing */ + #else + NOP ; 1 2 Loop alignment padding + #endif + #endif + #endif + #endif + ;Leave loop unaligned + #endif +CyDelayCycles_loop: + #ifdef CYDEV_CM0P_BASE + ADDS r0, r0, #1 + SUBS r0, r0, #2 + BNE CyDelayCycles_loop + NOP + #else + SUBS r0, r0, #1 + BNE CyDelayCycles_loop + NOP + NOP + #endif +CyDelayCycles_done: + BX lr + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled. +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic. Therefore, to avoid corrupting processor state, it must be the policy +; that all interrupt routines restore the interrupt enable bits as they were +; found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) + +CyEnterCriticalSection: + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) + +CyExitCriticalSection: + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + + END + +;Undefine temporary defines +#undef CYIPBLOCK_m0s8cpussv2_VERSION +#undef CYIPBLOCK_m0s8srssv2_VERSION diff --git a/cores/asr650x/projects/PSoC4/CyBootAsmRv.s b/cores/asr650x/projects/PSoC4/CyBootAsmRv.s new file mode 100644 index 00000000..a1396f03 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/CyBootAsmRv.s @@ -0,0 +1,136 @@ +;------------------------------------------------------------------------------- +; \file CyBootAsmRv.s +; \version 5.70 +; +; \brief Assembly routines for RealView. +; +;------------------------------------------------------------------------------- +; Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + AREA |.text|,CODE,ALIGN=3 + THUMB + EXTERN Reset + INCLUDE cyfitterrv.inc + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + ALIGN 8 +CyDelayCycles FUNCTION + EXPORT CyDelayCycles + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + IF :DEF: CYIPBLOCK_m0s8cpuss_VERSION + NOP ; 1 2 Loop alignment padding + ELSE + IF :DEF: CYIPBLOCK_s8srsslt_VERSION + IF :DEF: CYIPBLOCK_m0s8cpussv2_VERSION + IF :DEF: CYIPBLOCK_mxusbpd_VERSION + ; Do nothing + ELSE + IF :DEF: CYIPBLOCK_m0s8usbpd_VERSION + ; Do nothing + ELSE + NOP ; 1 2 Loop alignment padding + ENDIF + ENDIF + ENDIF + ENDIF + ;Leave loop unaligned + ENDIF +CyDelayCycles_loop + ; For CM0+ branch instruction takes 2 CPU cycles, for CM0 it takes 3 cycles + IF :DEF: CYDEV_CM0P_BASE + ADDS r0, r0, #1 ; 1 2 Increment counter + SUBS r0, r0, #2 ; 1 2 Decrement counter by 2 + BNE CyDelayCycles_loop ; 2 2 2 CPU cycles (if branche is taken) + NOP ; 1 2 Loop alignment padding + ELSE + SUBS r0, r0, #1 ; 1 2 Decrement counter + BNE CyDelayCycles_loop ; 3 2 3 CPU cycles (if branche is taken) + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + ENDIF +CyDelayCycles_done + BX lr ; 3 2 + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled (the actual value depends on +; whether the device is PSoC 3 or PSoC 5). +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a +; corrupting processor state, it must be the policy that all interrupt routines +; restore the interrupt enable bits as they were found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) +CyEnterCriticalSection FUNCTION + EXPORT CyEnterCriticalSection + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) +CyExitCriticalSection FUNCTION + EXPORT CyExitCriticalSection + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + ENDFUNC + + END + +; [] END OF FILE diff --git a/cores/asr650x/projects/PSoC4/CyDMA.c b/cores/asr650x/projects/PSoC4/CyDMA.c new file mode 100644 index 00000000..af871593 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/CyDMA.c @@ -0,0 +1,1452 @@ +/******************************************************************************* +* File Name: CyDMA.c +* Version 1.10 +* +* Description: +* This file contains all of the global DMA API functions. +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyDMA.h" +#include "CyLib.h" + +/* Default callback function. It is invoked if the user callback function is +* undefined. +*/ +static void CyDmaDefaultInterruptCallback(void); + +/* Array of pointers to user defined callback functions to be called +* from DMA interrupt. +*/ +static cydma_callback_t CyDmaInterruptCallback[CYDMA_CH_NR] = { + &CyDmaDefaultInterruptCallback, &CyDmaDefaultInterruptCallback, + &CyDmaDefaultInterruptCallback, &CyDmaDefaultInterruptCallback, + &CyDmaDefaultInterruptCallback, &CyDmaDefaultInterruptCallback, + &CyDmaDefaultInterruptCallback, &CyDmaDefaultInterruptCallback +}; + +/* The live status of all DMA channels usage. Bit i is associated to channel i, +* with i = 0..CYDMA_CH_NR-1. '0' - channel is free. '1' - channel is in use. +* All the channels allocated for DMA instances placed on a schematic are in use +* by default and cannot be freed. +* DMA_CHANNELS_USED__MASK is generated during the build time and is a bit field +* corresponding to the DMA channels placed on a design schematic. +*/ +static uint32 CyDmaChannelUsedMask = DMA_CHANNELS_USED__MASK; + + +/******************************************************************************* +* Function Name: CyDmaEnable +******************************************************************************** +* +* Summary: +* Sets the default ISR to be called by the DMA interrupt and enables the DMA +* transfer engine. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side effect: +* Does not affect the channel enable status. Overrides the interrupt vector +* set prior the first time CyDmaEnable() is called. +* +*******************************************************************************/ +void CyDmaEnable(void) +{ + static uint8 initIntrVector = 0u; + + if(0u == initIntrVector) + { + CyDmaSetInterruptVector(&CyDmaInterrupt); + CyIntSetPriority(CYDMA_INTR_NUMBER, CYDMA_INTR_PRIO); + initIntrVector = 1u; + } + CYDMA_CTL_REG = CYDMA_ENABLED; +} + + +/******************************************************************************* +* Function Name: CyDmaDisable +******************************************************************************** +* +* Summary: +* Disables the DMA transfer engine. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side effect: +* Does not affect the channel enable status. +* +*******************************************************************************/ +void CyDmaDisable(void) +{ + CYDMA_CTL_REG = (uint32)~CYDMA_ENABLED; +} + + +/******************************************************************************* +* Function Name: CyDmaGetStatus +******************************************************************************** +* +* Summary: +* Returns the status of the DMA transfer engine. +* +* Parameters: +* None. +* +* Return: +* The contents of the DMA status register. Refer to the status register bit +* definitions in CyDMA_P4.h or the API description in the DMA channel +* datasheet. +* +* Side effect: +* The series of function calls CyDmaGetActiveSrcAddress(), +* CyDmaGetActiveDstAddress(), CyDmaGetStatus() are not atomic, the DMA +* engine may have advanced after one or more of these function calls. Meaning +* the returns from these three functions may not be related to each other. +* +*******************************************************************************/ +uint32 CyDmaGetStatus(void) +{ + return (CYDMA_STATUS_REG); +} + + +/******************************************************************************* +* Function Name: CyDmaGetActiveChannels +******************************************************************************** +* +* Summary: +* Returns a bit field of all the DMA channels that are either active or +* pending. +* +* Parameters: +* None. +* +* Return: +* Bit field of active and pending channels. +* +*******************************************************************************/ +uint32 CyDmaGetActiveChannels(void) +{ + return (CYDMA_STATUS_CH_ACT_REG); +} + + +/******************************************************************************* +* Function Name: CyDmaGetActiveSrcAddress +******************************************************************************** +* +* Summary: +* Returns the source address currently being used by the DMA transfer engine. +* This function can be used to debug the DMA, or observe where it is at in a +* transfer. It will not be used in normal DMA operation. +* +* Parameters: +* None. +* +* Return: +* Source address currently being used by the DMA transfer engine. +* +* Side effect: +* The series of function calls CyDmaGetActiveSrcAddress(), +* CyDmaGetActiveDstAddress(), CyDmaGetStatus() are not atomic, the DMA +* engine may have advanced after one or more of these function calls. Meaning +* the returns from these three functions may not be related to each other. +* +*******************************************************************************/ +void * CyDmaGetActiveSrcAddress(void) +{ + return ((void *)CYDMA_STATUS_SRC_ADDR_REG); +} + + +/******************************************************************************* +* Function Name: CyDmaGetActiveDstAddress +******************************************************************************** +* +* Summary: +* Returns the destination address currently being used by the DMA transfer +* engine. This function can be used to debug the DMA, or observe where it is at +* in a transfer. It will not be used in normal DMA operation. +* +* Parameters: +* None. +* +* Return: +* Destination address currently being used by the DMA transfer engine. +* +* Side effect: +* The series of function calls CyDmaGetActiveSrcAddress(), +* CyDmaGetActiveDstAddress(), CyDmaGetStatus() are not atomic, the DMA +* engine may have advanced after one or more of these function calls. Meaning +* the returns from these three functions may not be related to each other. +* +*******************************************************************************/ +void * CyDmaGetActiveDstAddress(void) +{ + return ((void *)CYDMA_STATUS_DST_ADDR_REG); +} + + +/******************************************************************************* +* Function Name: CyDmaSetInterruptVector +******************************************************************************** +* +* Summary: +* Sets the function that will be called by the DMA interrupt. Note, calling +* CyDmaEnable() for the first time overrides any effect this API could have. +* Call CyDmaSetInterruptVector() after calling CyDmaEnable() to change +* the default ISR. +* +* Parameters: +* interruptVector: Address of the function that will be called by the DMA +* interrupt. +* Return: +* None. +* +* Side effect: +* Other components that use DMA may register their callback functions to be +* called from the default DMA ISR. Therefore, changing the DMA ISR to a user +* defined ISR using this API may prevent these other components from +* functioning correctly. +* +*******************************************************************************/ +void CyDmaSetInterruptVector(cyisraddress interruptVector) +{ + (void)CyIntSetVector(CYDMA_INTR_NUMBER, interruptVector); +} + + +/******************************************************************************* +* Function Name: CyDmaGetInterruptSource +******************************************************************************** +* +* Summary: +* Returns the bit field of which channels generated an interrupt request. +* +* Parameters: +* None. +* +* Return: +* Bit filed of which channels generated an interrupt request. +* +*******************************************************************************/ +uint32 CyDmaGetInterruptSource(void) +{ + return (CYDMA_INTR_REG); +} + + +/******************************************************************************* +* Function Name: CyDmaClearInterruptSource +******************************************************************************** +* +* Summary: +* Clears the pending interrupts. +* +* Parameters: +* interruptMask: Bit field of interrupts to clear. +* +* Return: +* None. +* +*******************************************************************************/ +void CyDmaClearInterruptSource(uint32 interruptMask) +{ + CYDMA_INTR_REG = interruptMask; +} + + +/******************************************************************************* +* Function Name: CyDmaSetInterruptSourceMask +******************************************************************************** +* +* Summary: +* Sets mask for interrupt source. +* +* Parameters: +* interruptmask: Mask corresponding to interrupt bit field. +* +* Return: +* None. +* +*******************************************************************************/ +void CyDmaSetInterruptSourceMask(uint32 interruptMask) +{ + CYDMA_INTR_MASK_REG = interruptMask; +} + + +/******************************************************************************* +* Function Name: CyDmaGetInterruptSourceMask +******************************************************************************** +* +* Summary: +* Returns mask for interrupt source. +* +* Parameters: +* None. +* +* Return: +* Mask corresponding to interrupt bit field. +* +*******************************************************************************/ +uint32 CyDmaGetInterruptSourceMask(void) +{ + return (CYDMA_INTR_MASK_REG); +} + + +/******************************************************************************* +* Function Name: CyDmaGetInterruptSourceMasked +******************************************************************************** +* +* Summary: +* Returns the bitwise AND of the interrupt source and the interrupt mask. +* +* Parameters: +* None. +* +* Return: +* Bitwise AND of the interrupt source and the interrupt mask. +* +*******************************************************************************/ +uint32 CyDmaGetInterruptSourceMasked(void) +{ + return (CYDMA_INTR_MASKED_REG); +} + + +/******************************************************************************* +* Function Name: CyDmaSetInterruptCallback +******************************************************************************** +* +* Summary: +* Sets a user defined callback function to be called by the DMA interrupt. The +* function should contain code to process the interrupt request for the +* associated DMA channel. +* +* Parameters: +* channel: Channel used by this function. +* callback: Pointer to the user defined callback function. +* +* Return: +* Pointer to the function previously set for the specified channel. +* +*******************************************************************************/ +cydma_callback_t CyDmaSetInterruptCallback(int32 channel, cydma_callback_t callback) +{ + cydma_callback_t prevCallback; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + + prevCallback = CyDmaInterruptCallback[channel]; + CyDmaInterruptCallback[channel] = callback; + return (prevCallback); +} + + +/******************************************************************************* +* Function Name: CyDmaGetInterruptCallback +******************************************************************************** +* +* Summary: +* Returns the pointer to the interrupt callback function for the specified DMA +* channel. +* +* Parameters: +* channel: Channel used by this function. +* +* Return: +* Callback function pointer for the specified channel. +* +*******************************************************************************/ +cydma_callback_t CyDmaGetInterruptCallback(int32 channel) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + + return (CyDmaInterruptCallback[channel]); +} + + +/******************************************************************************* +* Function Name: CyDmaInterrupt +******************************************************************************** +* +* Summary: +* The default ISR for DMA interrupts. The handler checks which DMA channel has +* triggered the interrupt and calls the user defined callback function. +* The callback function is set using CyDmaSetInteruptCallback() API. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* This function clears the pending interrupts. +* +*******************************************************************************/ +CY_ISR(CyDmaInterrupt) +{ + uint32 intr; + uint32 cbIdx = 0u; + + /* Get interrupt source. */ + intr = CYDMA_INTR_MASKED_REG; + + /* Clear pending interrupts. */ + CYDMA_INTR_REG = intr; + + /* Call user defined callback functions for triggered interrupt sources. */ + while(0u != intr) + { + if(0u != (intr & 0x1u)) + { + CyDmaInterruptCallback[cbIdx](); + } + intr >>= 1; + ++cbIdx; + } +} + + +/******************************************************************************* +* Function Name: CyDmaDefaultInterruptCallback +******************************************************************************** +* +* Summary: +* This function is invoked when the user defined callback function is undefined +* for the interrupt source. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +static void CyDmaDefaultInterruptCallback(void) +{ + /* Halt CPU in debug mode. We get here because there is no user defined + * callback function for the interrupt source. You should either set a + * callback function or disable generating an interrupt from this + * interrupt source. + * To set a callback, use the CyDmaSetInterruptCallback() API function. + * To disable interrupt generation, write '0' to the corresponding bit + * in the interrupt mask by calling CyDmaSetInterruptSourceMask(). + */ + CYASSERT(0 != 0); +} + + +/******************************************************************************* +* Function Name: CyDmaChAlloc +******************************************************************************** +* +* Summary: +* Allocates a channel number to use with later DMA functions. +* +* Parameters: +* None. +* +* Return: +* The allocated channel number. Zero is a valid channel number. +* CYDMA_INVALID_CHANNEL is returned if there are no channels available. +* +*******************************************************************************/ +int32 CyDmaChAlloc(void) +{ + int32 channel = CYDMA_CH_NR-1; + uint32 channelMask = (uint32)(1UL << (CYDMA_CH_NR-1)); + + while (channel >= 0) + { + if(0u == (CyDmaChannelUsedMask & channelMask)) + { + /* Mark channel as used and exit loop. */ + CyDmaChannelUsedMask |= channelMask; + break; + } + channelMask >>= 1; + --channel; + } + return (channel); +} + + +/******************************************************************************* +* Function Name: CyDmaChFree +******************************************************************************** +* +* Summary: +* Frees a channel handle allocated by CyDmaChAlloc(). Channels allocated for +* DMA instances placed on a schematic cannot be freed. +* +* Parameters: +* channel: The handle previously returned by CyDmaChAlloc(). +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if channel is invalid. +* +*******************************************************************************/ +cystatus CyDmaChFree(int32 channel) +{ + uint32 channelMask; + cystatus result = CYRET_BAD_PARAM; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + + channelMask = (uint32)(1UL << channel); + + /* Check against attempt to free channel allocated for DMA instance + * placed on schematic. + */ + if(0u == (channelMask & DMA_CHANNELS_USED__MASK)) + { + CyDmaChannelUsedMask &= (uint32)~channelMask; + result = CYRET_SUCCESS; + } + + return (result); +} + + +/******************************************************************************* +* Function Name: CyDmaChEnable +******************************************************************************** +* +* Summary: +* Enables the DMA channel. +* +* Parameters: +* channel: Channel used by this function. +* +* Return: +* None. +* +* Side effect: +* If this function is called before CyDmaSetConfiguration(), and +* CyDmaSetSrcAddress() and CyDmaSetDstAddress(), the operation of +* the DMA is undefined and could result in system data corruption. +* +*******************************************************************************/ +void CyDmaChEnable(int32 channel) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + + CYDMA_CH_CTL_BASE.ctl[channel] |= CYDMA_ENABLED; +} + + +/******************************************************************************* +* Function Name: CyDmaChDisable +******************************************************************************** +* +* Summary: +* Disables the DMA channel. +* +* Parameters: +* channel: Channel used by this function. +* +* Return: +* None. +* +* Side effect: +* If this function is called during a DMA transfer the transfer is aborted. +* +*******************************************************************************/ +void CyDmaChDisable(int32 channel) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + + CYDMA_CH_CTL_BASE.ctl[channel] &= (uint32)~CYDMA_ENABLED; +} + + +/******************************************************************************* +* Function Name: CyDmaTrigger +******************************************************************************** +* +* Summary: +* Triggers the DMA channel, this is useful only for software triggers. This is +* not needed when hardware triggers are used. +* +* Parameters: +* channel: Channel used by this function. +* +* Return: +* None. +* +*******************************************************************************/ +void CyDmaTrigger(int32 channel) +{ + /* The LUT is device-dependent, thus it is generated during the build process. */ + static const uint32 trCtlLut[] = {0xC0020000U}; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + + CYDMA_TR_CTL_REG = trCtlLut[(uint32)channel >> CYDMA_TR_GROUP_SHR] | ((uint32)channel & CYDMA_TR_SEL_MASK); +} + + +/******************************************************************************* +* Function Name: CyDmaSetPriority +******************************************************************************** +* +* Summary: +* Sets the priority for the channel. +* +* Parameters: +* channel: Channel used by this function +* priority: Priority for channel. Priority can be 0,1,2, or 3. +* 0 is the highest priority. +* +* Return: +* None. +* +* Side effect: +* This function should not be called while the channel is enabled. +* +*******************************************************************************/ +void CyDmaSetPriority(int32 channel, int32 priority) +{ + uint32 regValue; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((priority >= 0) && (priority <= CY_DMA_MAX_PRIO)); + + regValue = CYDMA_CH_CTL_BASE.ctl[channel] & (uint32)~CYDMA_PRIO; + CYDMA_CH_CTL_BASE.ctl[channel] = regValue | (uint32)((uint32)priority << CYDMA_PRIO_POS); +} + + +/******************************************************************************* +* Function Name: CyDmaGetPriority +******************************************************************************** +* +* Summary: +* Gets the priority for the channel. +* +* Parameters: +* channel: Channel used by this function. +* +* Return: +* Priority for channel. Priority can be 0,1,2, or 3. 0 is the highest priority. +* +*******************************************************************************/ +int32 CyDmaGetPriority(int32 channel) +{ + uint32 priority; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + + priority = (CYDMA_CH_CTL_BASE.ctl[channel] & CYDMA_PRIO) >> CYDMA_PRIO_POS; + return ((int32)priority); +} + + +/******************************************************************************* +* Function Name: CyDmaSetNextDescriptor +******************************************************************************** +* +* Summary: +* Sets the descriptor that should be run the next time the channel is +* triggered. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Next Descriptor to run (0 or 1). +* +* Return: +* None. +* +* Side effect: +* This function should not be called while the channel is enabled. +* +*******************************************************************************/ +void CyDmaSetNextDescriptor(int32 channel, int32 descriptor) +{ + uint32 regValue; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + regValue = CYDMA_CH_CTL_BASE.ctl[channel] & (uint32)~CYDMA_DESCRIPTOR; + CYDMA_CH_CTL_BASE.ctl[channel] = regValue | (uint32)((uint32)descriptor << CYDMA_DESCRIPTOR_POS); +} + + +/******************************************************************************* +* Function Name: CyDmaGetNextDescriptor +******************************************************************************** +* +* Summary: +* Returns the next descriptor that should be run, as set by +* CyDmaSetNextDescriptor(). +* +* Parameters: +* channel: channel used by this function. +* +* Return: +* Next Descriptor to run (0 or 1). +* +*******************************************************************************/ +int32 CyDmaGetNextDescriptor(int32 channel) +{ + uint32 nextDescriptor; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + + nextDescriptor = (CYDMA_CH_CTL_BASE.ctl[channel] & CYDMA_DESCRIPTOR) >> CYDMA_DESCRIPTOR_POS; + return ((int32)nextDescriptor); +} + + +/******************************************************************************* +* Function Name: CyDmaSetConfiguration +******************************************************************************** +* +* Summary: +* Sets configuration information for the specified descriptor. +* +* Parameters: +* channel: DMA channel modified by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* config: Pointer to a configuration structure. Refer to cydma_init_struct +* structure definition in CyDMA_P4.h and/or DMA channel datasheet +* for more information. +* +* Return: +* None. +* +* Side effect: +* The status register associated with the specified descriptor is reset to +* zero after this function call. This function also validates the descriptor. +* This function should not be called while the descriptor is active. +* This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaSetConfiguration(int32 channel, int32 descriptor, const cydma_init_struct * config) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + CYASSERT(0u == (config->dataElementSize & (uint32)~CYDMA_DATA_SIZE)); + CYASSERT((config->numDataElements > 0) && (config->numDataElements <= CYDMA_MAX_DATA_NR)); + CYASSERT(0u == (config->srcDstTransferWidth & (uint32)~CYDMA_TRANSFER_WIDTH)); + CYASSERT(0u == (config->addressIncrement & (uint32)~CYDMA_ADDR_INCR)); + CYASSERT(0u == (config->triggerType & (uint32)~CYDMA_TRIGGER_TYPE)); + CYASSERT(0u == (config->transferMode & (uint32)~CYDMA_TRANSFER_MODE)); + CYASSERT(0u == (config->preemptable & (uint32)~CYDMA_PREEMPTABLE)); + CYASSERT(0u == (config->actions & (uint32)~CYDMA_POST_COMPLETE_ACTIONS)); + + CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl = config->dataElementSize | + ((uint32)config->numDataElements-1u) | + config->srcDstTransferWidth | + config->addressIncrement | + config->triggerType | + config->transferMode | + config->preemptable | + config->actions; + + CYDMA_DESCR_BASE.descriptor[channel][descriptor].status = CYDMA_VALID; +} + + +/******************************************************************************* +* Function Name: CyDmaValidateDescriptor +******************************************************************************** +* +* Summary: +* Validates the specified descriptor after it has been invalidated. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* +* Return: +* None. +* +* Side effect: +* The status register associated with the specified descriptor is reset to +* zero after this function call. +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaValidateDescriptor(int32 channel, int32 descriptor) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + CYDMA_DESCR_BASE.descriptor[channel][descriptor].status = CYDMA_VALID; +} + + +/******************************************************************************* +* Function Name: CyDmaGetDescriptorStatus +******************************************************************************** +* +* Summary: +* Returns the status of the specified descriptor. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* +* Return: +* Returns the contents of the specified descriptors status register. Refer to +* descriptor status register bit definitions in CyDMA_P4.h or the API +* description in the DMA channel datasheet for more information. +* +*******************************************************************************/ +uint32 CyDmaGetDescriptorStatus(int32 channel, int32 descriptor) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + return (CYDMA_DESCR_BASE.descriptor[channel][descriptor].status); +} + + +/******************************************************************************* +* Function Name: CyDmaSetSrcAddress +******************************************************************************** +* +* Summary: +* Configures the source address for the specified descriptor. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* srcAddress: Address of DMA transfer source. +* +* Return: +* None. +* +* Side effect: +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaSetSrcAddress(int32 channel, int32 descriptor, void * srcAddress) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + CYDMA_DESCR_BASE.descriptor[channel][descriptor].src = srcAddress; +} + + +/******************************************************************************* +* Function Name: CyDmaGetSrcAddress +******************************************************************************** +* +* Summary: +* Returns the source address for the specified descriptor, set by +* CyDmaSetSrcAddress(). +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Specifies descriptor (0 or 1) used by this function. +* +* Return: +* Source address written to specified descriptor. +* +*******************************************************************************/ +void * CyDmaGetSrcAddress(int32 channel, int32 descriptor) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + return (CYDMA_DESCR_BASE.descriptor[channel][descriptor].src); +} + + +/******************************************************************************* +* Function Name: CyDmaSetDstAddress +******************************************************************************** +* +* Summary: +* Configures the destination address for the specified descriptor. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* dstAddress: Address of DMA transfer destination. +* +* Return: +* None. +* +* Side effect: +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaSetDstAddress(int32 channel, int32 descriptor, void * dstAddress) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + CYDMA_DESCR_BASE.descriptor[channel][descriptor].dst = dstAddress; +} + + +/******************************************************************************* +* Function Name: CyDmaGetDstAddress +******************************************************************************** +* +* Summary: +* Returns the destination address for the specified descriptor, set by +* CyDmaSetDstAddress(). +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Specifies descriptor (0 or 1) used by this function. +* +* Return: +* Destination address written to specified descriptor. +* +*******************************************************************************/ +void * CyDmaGetDstAddress(int32 channel, int32 descriptor) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + return (CYDMA_DESCR_BASE.descriptor[channel][descriptor].dst); +} + +/******************************************************************************* +* Function Name: CyDmaSetDataElementSize +******************************************************************************** +* +* Summary: +* Sets the data element size for the specified descriptor. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* dataElementSize: Specifies the size of the data element. The DMA transfer +* engine transfers one data element at a time. How these +* transfers occur is controlled by the transfer mode. +* Refer to the API bit field definitions in CyDMA_P4.h +* or API description in the DMA channel datasheet for the +* parameter options. +* +* Return: +* None. +* +* Side effect: +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaSetDataElementSize(int32 channel, int32 descriptor, uint32 dataElementSize) +{ + uint32 regValue; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + CYASSERT(0u == (dataElementSize & (uint32)~CYDMA_DATA_SIZE)); + + regValue = CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & (uint32)~CYDMA_DATA_SIZE; + CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl = regValue | dataElementSize; +} + + +/******************************************************************************* +* Function Name: CyDmaGetDataElementSize +******************************************************************************** +* +* Summary: +* Returns the data element size configured for the specified descriptor, set by +* CyDmaSetDataElementSize() or CyDmaSetConfiguration. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* +* Return: +* The size of the data element. The DMA transfer engine transfers one data +* element at a time. How these transfers occur is controlled by the transfer +* mode. Refer to the API bit field definitions in CyDMA_P4.h or the API +* description in the DMA channel datasheet for more information. +* +* Note: +* The size of the source and destination can be configured to use the +* data element size, or a Word, this is set in CyDmaSetSrcDstTransferWidth(). +* +*******************************************************************************/ +uint32 CyDmaGetDataElementSize(int32 channel, int32 descriptor) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + return (CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & CYDMA_DATA_SIZE); +} + + +/******************************************************************************* +* Function Name: CyDmaSetNumDataElements +******************************************************************************** +* +* Summary: +* Sets the number of data elements to transfer for specified descriptor. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* numDataElements: Total number of data elements this descriptor transfers. +* Valid ranges are 1 to 65536. +* +* Return: +* None. +* +* Side effect: +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaSetNumDataElements(int32 channel, int32 descriptor, int32 numDataElements) +{ + uint32 regValue; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + CYASSERT((numDataElements > 0) && (numDataElements <= CYDMA_MAX_DATA_NR)); + + --numDataElements; + regValue = CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & (uint32)~CYDMA_DATA_NR; + CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl = regValue | (uint32)numDataElements; +} + + +/******************************************************************************* +* Function Name: CyDmaGetNumDataElements +******************************************************************************** +* +* Summary: +* Returns the number of data elements to be transferred. Only reflects the +* value written by CyDmaSetNumDataElements() or CyDmaSetConfiguration(). This +* does not reflect how many elements have been transferred. For that +* information use the CyDmaGetDescriptorStatus() function. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* +* Return: +* Number of data elements to transfer. +* +*******************************************************************************/ +int32 CyDmaGetNumDataElements(int32 channel, int32 descriptor) +{ + uint32 numElements; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + numElements = (CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & CYDMA_DATA_NR) + 1u; + return ((int32)numElements); +} + + +/******************************************************************************* +* Function Name: CyDmaSetSrcDstTransferWidth +******************************************************************************** +* +* Summary: +* Sets the width of the source and destination. The DMA can either read and +* write data from the source and destination at the size specified by +* CyDmaSetDataElementSize() or by a word (4bytes). This also determines how +* many bytes the addresses are incremented if increment source and destination +* address are turned on. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* transferWidth: Specifies the source and destination widths. Refer to +* the API bit field definitions in CyDMA_P4.h or the API +* description in the DMA channel datasheet for the parameter +* options. +* +* Return: +* None. +* +* Side effect: +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaSetSrcDstTransferWidth(int32 channel, int32 descriptor, uint32 transferWidth) +{ + uint32 regValue; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + CYASSERT(0u == (transferWidth & (uint32)~CYDMA_TRANSFER_WIDTH)); + + regValue = CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & (uint32)~CYDMA_TRANSFER_WIDTH; + CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl = regValue | transferWidth; +} + + +/******************************************************************************* +* Function Name: CyDmaGetSrcDstTransferWidth +******************************************************************************** +* +* Summary: +* Returns the width of the source and destination, as set by +* CyDmaSetSrcDstTransferWidth() or CyDmaSetConfiguration(). +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* +* Return: +* Width of source and destination. Refer to the API bit field definitions in +* CyDMA_P4.h or the API description in the DMA channel datasheet for more +* information. +* +*******************************************************************************/ +uint32 CyDmaGetSrcDstTransferWidth(int32 channel, int32 descriptor) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + return (CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & CYDMA_TRANSFER_WIDTH); +} + + +/******************************************************************************* +* Function Name: CyDmaSetAddressIncrement +******************************************************************************** +* +* Summary: +* Sets whether the source or destination addresses are incremented after the +* transfer of each data element. The amount that the source and destination +* address are incremented is determined by the CyDmaSetSrcDstTransferWidth() +* function. The addresses will either be incremented by the data element size +* or by a word (4 bytes). +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* addressIncrement: Address increment settings. Refer to the API bit fields +* definition in CyDMA_P4.h or the API description in the DMA +* channel datasheet for the parameter options. +* +* Return: +* None. +* +* Side effect: +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaSetAddressIncrement(int32 channel, int32 descriptor, uint32 addressIncrement) +{ + uint32 regValue; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + CYASSERT(0u == (addressIncrement & (uint32)~CYDMA_ADDR_INCR)); + + regValue = CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & (uint32)~CYDMA_ADDR_INCR; + CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl = regValue | addressIncrement; +} + + +/******************************************************************************* +* Function Name: CyDmaGetAddressIncrement +******************************************************************************** +* +* Summary: +* Returns address increment settings as set by CyDmaSetAddressIncrement() or +* CyDmaSetConfiguration(). +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* +* Return: +* Address increment settings. Refer to the API bit field definitions in +* CyDMA_P4.h or the API description in the DMA channel datasheet for more +* information. +* +*******************************************************************************/ +uint32 CyDmaGetAddressIncrement(int32 channel, int32 descriptor) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + return (CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & CYDMA_ADDR_INCR); +} + + +/******************************************************************************* +* Function Name: CyDmaSetTriggerType +******************************************************************************** +* +* Summary: +* Sets the type of input trigger for the DMA For level sensitive triggers sets +* how long the DMA waits for the trigger to go low (deactivate) before +* triggering the channel again. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* triggerType: Type of DMA trigger. Refer to the API bit field definitions +* in CyDMA_P4.h or the API description in the DMA channel +* datasheet for the parameter options. +* +* Return: +* None. +* +* Side effect: +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaSetTriggerType(int32 channel, int32 descriptor, uint32 triggerType) +{ + uint32 regValue; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + CYASSERT(0u == (triggerType & (uint32)~CYDMA_TRIGGER_TYPE)); + + regValue = CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & (uint32)~CYDMA_TRIGGER_TYPE; + CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl = regValue | triggerType; +} + + +/******************************************************************************* +* Function Name: CyDmaGetTriggerType +******************************************************************************** +* +* Summary: +* Returns the trigger deactivation settings as set by CyDmaSetTriggerType() or +* CyDmaSetConfiguration(). +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* +* Return: +* Trigger deactivation settings. Refer to the API bit field definitions in +* CyDMA_P4.h or the API description in the DMA channel datasheet for more +* information. +* +*******************************************************************************/ +uint32 CyDmaGetTriggerType(int32 channel, int32 descriptor) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + return (CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & CYDMA_TRIGGER_TYPE); +} + + +/******************************************************************************* +* Function Name: CyDmaSetTransferMode +******************************************************************************** +* +* Summary: +* Sets the DMA transfer mode. This determines how the DMA reacts to each trigger +* event. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* transferMode: Specifies the DMA transfer mode settings. Refer to the API bit +* field definitions in CyDMA_P4.h or the API description in the +* DMA channel datasheet for the parameter options. +* +* Return: +* None. +* +* Side effect: +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaSetTransferMode(int32 channel, int32 descriptor, uint32 transferMode) +{ + uint32 regValue; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + CYASSERT(0u == (transferMode & (uint32)~CYDMA_TRANSFER_MODE)); + + regValue = CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & (uint32)~CYDMA_TRANSFER_MODE; + CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl = regValue | transferMode; +} + + +/******************************************************************************* +* Function Name: CyDmaGetTransferMode +******************************************************************************** +* +* Summary: +* Returns the transfer mode for the specified descriptor as set by +* CyDmaSetTransferMode() or CyDmaSetConfiguration. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* +* Return: +* DMA transfer mode settings. Refer to the API bit field definitions in +* CyDMA_P4.h or the API description in the DMA channel datasheet for more +* information. +* +*******************************************************************************/ +uint32 CyDmaGetTransferMode(int32 channel, int32 descriptor) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + return (CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & CYDMA_TRANSFER_MODE); +} + + +/******************************************************************************* +* Function Name: CyDmaSetPreemptable +******************************************************************************** +* +* Summary: +* Determines if the descriptor is preemptable. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* preemptable: Descriptor preemption settings. Refer to the API bit fields +* definition in CyDMA_P4.h or the API description in the DMA +* channel datasheet for the parameter options. +* +* Return: +* None. +* +* Side effect: +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaSetPreemptable(int32 channel, int32 descriptor, uint32 preemptable) +{ + uint32 regValue; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + CYASSERT(0u == (preemptable & (uint32)~CYDMA_PREEMPTABLE)); + + regValue = CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & (uint32)~CYDMA_PREEMPTABLE; + CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl = regValue | preemptable; +} + + +/******************************************************************************* +* Function Name: CyDmaGetPreemptable +******************************************************************************** +* +* Summary: +* Returns whether or not the descriptor is preemptable. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* +* Return: +* Descriptor preemption setting. Refer to the API bit field definitions in +* CyDMA_P4.h or the API description in the DMA channel datasheet for more +* information. +* +*******************************************************************************/ +uint32 CyDmaGetPreemptable(int32 channel, int32 descriptor) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + return (CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & CYDMA_PREEMPTABLE); +} + + +/******************************************************************************* +* Function Name: CyDmaSetPostCompletionActions +******************************************************************************** +* +* Summary: +* Determines what occurs after a descriptor completes. +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* actions: Specifies descriptor post completion actions. Refer to the API +* bit field definitions in CyDMA_P4.h or the API description +* in the DMA channel datasheet for the parameter options. +* +* Return: +* None. +* +* Side effect: +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +void CyDmaSetPostCompletionActions(int32 channel, int32 descriptor, uint32 actions) +{ + uint32 regValue; + + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + CYASSERT(0u == (actions & (uint32)~CYDMA_POST_COMPLETE_ACTIONS)); + + regValue = CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & (uint32)~CYDMA_POST_COMPLETE_ACTIONS; + CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl = regValue | actions; +} + + +/******************************************************************************* +* Function Name: CyDmaGetPostCompletionActions +******************************************************************************** +* +* Summary: +* Returns the post descriptor action settings as set by +* CyDmaSetPostCompletionActions() or CyDmaSetConfiguration(). +* +* Parameters: +* channel: Channel used by this function. +* descriptor: Descriptor (0 or 1) modified by this function. +* +* Return: +* Post descriptor actions. Refer to the API bit field definitions in +* CyDMA_P4.h or the API description in the DMA channel datasheet for more +* information. +* +*******************************************************************************/ +uint32 CyDmaGetPostCompletionActions(int32 channel, int32 descriptor) +{ + CYASSERT((channel >= 0) && (channel < CYDMA_CH_NR)); + CYASSERT((descriptor >= 0) && (descriptor < CYDMA_DESCR_NR)); + + return (CYDMA_DESCR_BASE.descriptor[channel][descriptor].ctl & CYDMA_POST_COMPLETE_ACTIONS); +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/CyDMA.h b/cores/asr650x/projects/PSoC4/CyDMA.h new file mode 100644 index 00000000..4f4c6cd2 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/CyDMA.h @@ -0,0 +1,386 @@ +/******************************************************************************* +* File Name: CyDMA.h +* Version 1.10 +* +* Description: +* This file provides global DMA defines and API function definitions. +* +* Note: +* All the API function in this file are documented in the DMA Channel +* component datasheet. +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef CY_DMA_GLOBAL_P4_H +#define CY_DMA_GLOBAL_P4_H + +#include "cytypes.h" + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +#define CYDMA_CH_NR (CYDEV_DMA_CHANNELS_AVAILABLE) +#define CYDMA_DESCR_NR (2) + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Channel control registers. Each channel has a dedicated control register. */ +typedef struct +{ + uint32 ctl[CYDMA_CH_NR]; +} cydma_channel_ctl_struct; + +/* Descriptor structure specifies transfer settings. */ +typedef struct +{ + void * src; /* Source address */ + void * dst; /* Destination address */ + uint32 ctl; /* Control word */ + uint32 status; /* Status word */ +} cydma_descriptor_struct; + +/* Each channel has two descriptor structures for double buffering purposes. +* The two descriptor structures are identical. All descriptors are placed +* sequentially in the DMAC MMIO register space. +*/ +typedef struct +{ + cydma_descriptor_struct descriptor[CYDMA_CH_NR][CYDMA_DESCR_NR]; +} cydma_descriptor_ram_struct; + +/* Configuration structure used by CyDmaSetConfiguration() API. */ +typedef struct +{ + /* Specifies the size of the data element. The DMA transfer engine transfers + * one data element at a time. How these transfers occur is controlled by the + * transferMode parameter. + */ + uint32 dataElementSize; + + /* Specifies the total number of data elements this descriptor transfers. + * Valid ranges are 1 to 65536. + */ + int32 numDataElements; + + /* Specifies the source and destination widths. */ + uint32 srcDstTransferWidth; + + /* Specifies whether the source and/or destination address will be + * incremented after the transfer of each single data element. + */ + uint32 addressIncrement; + + /* Specifies the type of DMA trigger. */ + uint32 triggerType; + + /* Specifies how the DMA reacts to each trigger event. */ + uint32 transferMode; + + /* Specifies whether the descriptor is preemptable. */ + uint32 preemptable; + + /* Specifies what occurs after a descriptor completes. */ + uint32 actions; + +} cydma_init_struct; + + +/*************************************** +* Function Prototypes +***************************************/ + +/* Callback function pointer type */ +typedef void (*cydma_callback_t)(void); + +/* Default interrupt service routine */ +CY_ISR_PROTO(CyDmaInterrupt); + +/* DMA controller specific functions */ +void CyDmaEnable(void); +void CyDmaDisable(void); + +uint32 CyDmaGetStatus(void); +uint32 CyDmaGetActiveChannels(void); +void * CyDmaGetActiveSrcAddress(void); +void * CyDmaGetActiveDstAddress(void); + +void CyDmaSetInterruptVector(cyisraddress interruptVector); +uint32 CyDmaGetInterruptSource(void); +void CyDmaClearInterruptSource(uint32 interruptMask); +uint32 CyDmaGetInterruptSourceMasked(void); +void CyDmaSetInterruptSourceMask(uint32 interruptMask); +uint32 CyDmaGetInterruptSourceMask(void); +cydma_callback_t CyDmaSetInterruptCallback(int32 channel, cydma_callback_t callback); +cydma_callback_t CyDmaGetInterruptCallback(int32 channel); + +/* Channel specific functions */ +int32 CyDmaChAlloc(void); +cystatus CyDmaChFree(int32 channel); + +void CyDmaChEnable(int32 channel); +void CyDmaChDisable(int32 channel); +void CyDmaTrigger(int32 channel); + +void CyDmaSetPriority(int32 channel, int32 priority); +int32 CyDmaGetPriority(int32 channel); + +void CyDmaSetNextDescriptor(int32 channel, int32 descriptor); +int32 CyDmaGetNextDescriptor(int32 channel); + +/* Descriptor specific functions */ +void CyDmaSetConfiguration(int32 channel, int32 descriptor, const cydma_init_struct * config); + +void CyDmaValidateDescriptor(int32 channel, int32 descriptor); + +uint32 CyDmaGetDescriptorStatus(int32 channel, int32 descriptor); + +void CyDmaSetSrcAddress(int32 channel, int32 descriptor, void * srcAddress); +void * CyDmaGetSrcAddress(int32 channel, int32 descriptor); + +void CyDmaSetDstAddress(int32 channel, int32 descriptor, void * dstAddress); +void * CyDmaGetDstAddress(int32 channel, int32 descriptor); + +void CyDmaSetDataElementSize(int32 channel, int32 descriptor, uint32 dataElementSize); +uint32 CyDmaGetDataElementSize(int32 channel, int32 descriptor); + +void CyDmaSetNumDataElements(int32 channel, int32 descriptor, int32 numDataElements); +int32 CyDmaGetNumDataElements(int32 channel, int32 descriptor); + +void CyDmaSetSrcDstTransferWidth(int32 channel, int32 descriptor, uint32 transferWidth); +uint32 CyDmaGetSrcDstTransferWidth(int32 channel, int32 descriptor); + +void CyDmaSetAddressIncrement(int32 channel, int32 descriptor, uint32 addressIncrement); +uint32 CyDmaGetAddressIncrement(int32 channel, int32 descriptor); + +void CyDmaSetTriggerType(int32 channel, int32 descriptor, uint32 triggerType); +uint32 CyDmaGetTriggerType(int32 channel, int32 descriptor); + +void CyDmaSetTransferMode(int32 channel, int32 descriptor, uint32 transferMode); +uint32 CyDmaGetTransferMode(int32 channel, int32 descriptor); + +void CyDmaSetPreemptable(int32 channel, int32 descriptor, uint32 preemptable); +uint32 CyDmaGetPreemptable(int32 channel, int32 descriptor); + +void CyDmaSetPostCompletionActions(int32 channel, int32 descriptor, uint32 actions); +uint32 CyDmaGetPostCompletionActions(int32 channel, int32 descriptor); + + +/*************************************** +* API Constants +***************************************/ + +#define CYDMA_INTR_NUMBER (CYDEV_INTR_NUMBER_DMA) +#define CYDMA_INTR_PRIO (3u) + +#define CYDMA_INVALID_CHANNEL (-1) + +#define CYDMA_TRIGGER_MASK (0xC0020000U) +#define CYDMA_TR_SEL_MASK (0x00000007U) +#define CYDMA_TR_GROUP_SHR (3) + +#define CYDMA_MAX_DATA_NR (65536) + +#define CY_DMA_MAX_PRIO (3) + + +/******************************************************************************* +* Bit fields for CyDmaSetDataElementSize()/CyDmaGetDataElementSize(). +*******************************************************************************/ + +/* Specifies the size of the data element that is transferred at a time. */ +#define CYDMA_BYTE (0x00000000U) /* 1 byte */ +#define CYDMA_HALFWORD (0x00010000U) /* 2 bytes */ +#define CYDMA_WORD (0x00020000U) /* 4 bytes */ + + +/******************************************************************************* +* Bit fields for CyDmaSetSrcDstTransferWidth()/CyDmaGetSrcDstTransferWidth(). +*******************************************************************************/ + +/* Source and Destination widths are set by the data element size. */ +#define CYDMA_ELEMENT_ELEMENT (0x00000000U) + +/* Source width is set by data element size. Destination width is a +* word (4bytes). If the source width is smaller than the destination +* width, the upper bytes of the destination are written with zeros. +*/ +#define CYDMA_ELEMENT_WORD (0x00100000U) + +/* Source width is a word (4 bytes). Destination width is set by data +* element size. If the source width is larger than the destination width, +* the upper bytes of the source are ignored during the transaction. +*/ +#define CYDMA_WORD_ELEMENT (0x00400000U) + +/* Both source and destination widths are words. However, the data element +* size still has an effect in this mode. For example, if the data element +* size is set to a byte, then the upper three bytes of destination is +* padded with zeros, and the upper three bytes of the source is ignored +* during the transaction. +*/ +#define CYDMA_WORD_WORD (0x00500000U) + + +/******************************************************************************* +* Bit fields for CyDmaSetAddressIncrement()/CyDmaGetAddressIncrement(). +*******************************************************************************/ + +/* Specifies whether the source and/or destination address is incremented +* after the transfer of each single data element. The defines can be OR'd +* together. +*/ +#define CYDMA_INC_SRC_ADDR (0x00800000U) +#define CYDMA_INC_DST_ADDR (0x00200000U) +#define CYDMA_INC_NONE (0x00000000U) + + +/******************************************************************************* +* Bit fields for CyDmaSetTriggerType()/CyDmaGetTriggerType(). +*******************************************************************************/ + +/* Specifies the type of DMA trigger */ +#define CYDMA_PULSE (0x00000000U) +#define CYDMA_LEVEL_FOUR (0x01000000U) +#define CYDMA_LEVEL_EIGHT (0x02000000U) +#define CYDMA_PULSE_UNKNOWN (0x03000000U) + + +/******************************************************************************* +* Bit fields for CyDmaSetTransferMode()/CyDmaGetTransferMode(). +*******************************************************************************/ + +/* Each trigger causes the DMA to transfer a single data element. */ +#define CYDMA_SINGLE_DATA_ELEMENT (0x00000000U) + +/* Each trigger automatically transfers all data elements associated with +* the current descriptor, one data element at a time. +*/ +#define CYDMA_ENTIRE_DESCRIPTOR (0x40000000U) + +/* Each trigger automatically transfers all data elements associated with +* the current descriptor, one data element at a time. Upon completion the +* next descriptor is automatically triggered. +*/ +#define CYDMA_ENTIRE_DESCRIPTOR_CHAIN (0x80000000U) + + +/******************************************************************************* +* Bit fields for CyDmaSetPreemptable()/CyDmaGetPreemptable(). +*******************************************************************************/ + +/* Specifies whether the descriptor is preemptable. */ +#define CYDMA_PREEMPTABLE (0x10000000U) +#define CYDMA_NON_PREEMPTABLE (0x00000000U) + + +/******************************************************************************* +* Bit fields for CyDmaSetPostCompletionActions()/CyDmaGetPostCompletionActions() +*******************************************************************************/ + +/* Specifies what occurs after a descriptor completes. The defines that can be +* OR'd together. +* +* On completion of descriptor chain to the next descriptor. */ +#define CYDMA_CHAIN (0x20000000U) + +/* Invalidate the descriptor when it completes. */ +#define CYDMA_INVALIDATE (0x04000000U) + +/* On completion of descriptor generate an interrupt request. */ +#define CYDMA_GENERATE_IRQ (0x08000000U) + +/* No actions after the descriptor completes. */ +#define CYDMA_NONE (0x00000000U) + + +/******************************************************************************* +* Bit fields for CyDmaGetStatus(). +*******************************************************************************/ + +/* Bit fields to access the status register bits of the DMA transfer engine. */ +#define CYDMA_TRANSFER_INDEX (0x0000FFFFU) +#define CYDMA_CH_NUM (0x001F0000U) +#define CYDMA_STATE (0x07000000U) +#define CYDMA_PRIO (0x30000000U) +#define CYDMA_DESCRIPTOR (0x40000000U) +#define CYDMA_ACTIVE (0x80000000U) + +/* Defines for STATE: Only one define can be active at a time. */ +#define CYDMA_IDLE (0x00000000U) +#define CYDMA_LOAD_DESCR (0x01000000U) +#define CYDMA_LOAD_SRC (0x02000000U) +#define CYDMA_STORE_DST (0x03000000U) +#define CYDMA_STORE_DESCR (0x04000000U) +#define CYDMA_WAIT_TRIG_DEACT (0x05000000U) +#define CYDMA_STORE_ERROR (0x06000000U) + + +/******************************************************************************* +* Bit fields for CyDmaGetDescriptorStatus(). +*******************************************************************************/ + +/* Bit fields to access the status register bits of the descriptor. */ +#define CYDMA_TRANSFER_INDEX (0x0000FFFFU) +#define CYDMA_RESPONSE (0x00070000U) +#define CYDMA_VALID (0x80000000U) + +/* Response code meaning */ +#define CYDMA_NO_ERROR (0x00000000U) +#define CYDMA_DONE (0x00010000U) +#define CYDMA_SRC_BUS_ERROR (0x00020000U) +#define CYDMA_DST_BUS_ERROR (0x00030000U) +#define CYDMA_SRC_MISAL (0x00040000U) +#define CYDMA_DST_MISAL (0x00050000U) +#define CYDMA_INVALID_DESCR (0x00060000U) + + +/*************************************** +* Registers +***************************************/ + +#define CYDMA_CTL_REG (*(reg32 *) CYREG_DMAC_CTL) +#define CYDMA_STATUS_REG (*(reg32 *) CYREG_DMAC_STATUS) +#define CYDMA_STATUS_SRC_ADDR_REG (*(reg32 *) CYREG_DMAC_STATUS_SRC_ADDR) +#define CYDMA_STATUS_DST_ADDR_REG (*(reg32 *) CYREG_DMAC_STATUS_DST_ADDR) +#define CYDMA_STATUS_CH_ACT_REG (*(reg32 *) CYREG_DMAC_STATUS_CH_ACT) +#define CYDMA_INTR_REG (*(reg32 *) CYREG_DMAC_INTR) +#define CYDMA_INTR_SET_REG (*(reg32 *) CYREG_DMAC_INTR_SET) +#define CYDMA_INTR_MASK_REG (*(reg32 *) CYREG_DMAC_INTR_MASK) +#define CYDMA_INTR_MASKED_REG (*(reg32 *) CYREG_DMAC_INTR_MASKED) +#define CYDMA_CH_CTL_BASE (*(volatile cydma_channel_ctl_struct *) CYREG_DMAC_CH_CTL0) +#define CYDMA_DESCR_BASE (*(volatile cydma_descriptor_ram_struct *) CYDEV_DMAC_DESCR0_BASE) + +#define CYDMA_TR_CTL_REG (*(reg32 *) CYREG_PERI_TR_CTL) + + +/*************************************** +* Register Constants +***************************************/ + +#define CYDMA_ENABLED (0x80000000U) +#define CYDMA_PRIO_POS (28) +#define CYDMA_DESCRIPTOR_POS (30) + +/* Descriptor control register */ +#define CYDMA_DATA_SIZE (0x00030000U) +#define CYDMA_DATA_NR (0x0000FFFFUL) +#define CYDMA_TRANSFER_WIDTH (0x00500000U) +#define CYDMA_ADDR_INCR (0x00A00000U) +#define CYDMA_TRANSFER_MODE (0xC0000000U) +#define CYDMA_TRIGGER_TYPE (0x03000000U) +#define CYDMA_POST_COMPLETE_ACTIONS (0x2C000000U) + +#endif /* CY_DMA_GLOBAL_P4_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/CyFlash.c b/cores/asr650x/projects/PSoC4/CyFlash.c new file mode 100644 index 00000000..2a1f2ada --- /dev/null +++ b/cores/asr650x/projects/PSoC4/CyFlash.c @@ -0,0 +1,803 @@ +/***************************************************************************//** +* \file CyFlash.c +* \version 5.70 +* +* \brief Provides an API for the FLASH. +* +* \note This code is endian agnostic. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyFlash.h" + + +/******************************************************************************* +* Cypress identified a defect with the Flash write functionality of the +* PSoC 4000, PSoC 4000U, PSoC 4100, and PSoC 4200 devices. The +* CySysFlashWriteRow() function now checks the data to be written and, if +* necessary, modifies it to have a non-zero checksum. After writing to Flash, +* the modified data is replaced (Flash program) with +* the correct (original) data. +*******************************************************************************/ +#define CY_FLASH_CHECKSUM_WORKAROUND (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + +#if (CY_IP_FM || ((!CY_PSOC4_4000) && CY_IP_SPCIF_SYNCHRONOUS) || (!CY_IP_FM) && CY_PSOC4_4000) + static CY_SYS_FLASH_CLOCK_BACKUP_STRUCT cySysFlashBackup; +#endif /* (CY_IP_FM || ((!CY_PSOC4_4000) && CY_IP_SPCIF_SYNCHRONOUS) || (!CY_IP_FM) && CY_PSOC4_4000) */ + +static cystatus CySysFlashClockBackup(void); +static cystatus CySysFlashClockRestore(void); +#if(CY_IP_SPCIF_SYNCHRONOUS) + static cystatus CySysFlashClockConfig(void); +#endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + +/******************************************************************************* +* Function Name: CySysFlashWriteRow +****************************************************************************//** +* +* Erases a row of Flash and programs it with the new data. +* +* The IMO must be enabled before calling this function. The operation of the +* flash writing hardware is dependent on the IMO. +* +* For PSoC 4000, PSoC 4100 BLE and PSoC 4200 BLE devices (PSoC 4100 BLE and +* PSoC 4200 BLE devices with 256K of Flash memory are not affected), this API +* will automatically modify the clock settings for the device. Writing to +* flash requires that changes be made to the IMO and HFCLK settings. The +* configuration is restored before returning. This will impact the operation +* of most of the hardware in the device. +* +* For PSoC 4000 devices this API will automatically modify the clock settings +* for the device. Writing to flash requires that changes be made to the IMO +* and HFCLK settings. The configuration is restored before returning. HFCLK +* will have several frequency changes during the operation of this API between +* a minimum frequency of the current IMO frequency divided by 8 and a maximum +* frequency of 12 MHz. This will impact the operation of most of the hardware +* in the device. +* +* \param rowNum The flash row number. The number of the flash rows is defined by +* the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. Refer to the +* device datasheet for the details. +* \note The target flash array is calculated based on the specified flash row. +* +* \param rowData Array of bytes to write. The size of the array must be equal to +* the flash row size. The flash row size for the selected device is defined by +* the \ref CY_FLASH_SIZEOF_ROW macro. Refer to the device datasheet for the +* details. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashWriteRow(uint32 rowNum, const uint8 rowData[]) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 clkCnfRetValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 parameters[(CY_FLASH_SIZEOF_ROW + CY_FLASH_SRAM_ROM_DATA) / sizeof(uint32)]; + uint8 interruptState; + + #if (CY_FLASH_CHECKSUM_WORKAROUND) + uint32 needChecksumWorkaround = 0u; + uint32 savedIndex = 0u; + uint32 savedValue = 0u; + uint32 checksum = 0u; + uint32 bits = 0u; + uint32 i; + #endif /* (CY_FLASH_CHECKSUM_WORKAROUND) */ + + if ((rowNum < CY_FLASH_NUMBER_ROWS) && (rowData != 0u)) + { + /* Copy data to be written into internal variable */ + (void)memcpy((void *)¶meters[2u], rowData, CY_FLASH_SIZEOF_ROW); + + #if (CY_FLASH_CHECKSUM_WORKAROUND) + + for (i = 2u; i < ((CY_FLASH_SIZEOF_ROW / sizeof(uint32)) + 2u); i++) + { + uint32 tmp = parameters[i]; + if (tmp != 0u) + { + checksum += tmp; + bits |= tmp; + savedIndex = i; + } + } + + needChecksumWorkaround = ((checksum == 0u) && (bits != 0u)) ? 1u : 0u; + if (needChecksumWorkaround != 0u) + { + savedValue = parameters[savedIndex]; + parameters[savedIndex] = 0u; + } + #endif /* (CY_FLASH_CHECKSUM_WORKAROUND) */ + + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /*************************************************************** + * Mask all the exceptions to guarantee that Flash write will + * occur in the atomic way. It will not affect system call + * execution (flash row write) since it is executed in the NMI + * context. + ***************************************************************/ + interruptState = CyEnterCriticalSection(); + + clkCnfRetValue = CySysFlashClockBackup(); + + #if(CY_IP_SPCIF_SYNCHRONOUS) + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + retValue = CySysFlashClockConfig(); + } + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Write Row */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_WRITE_ROW) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[0u] |= (uint32)(rowNum << 16u); + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_WRITE_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + + #if (CY_FLASH_CHECKSUM_WORKAROUND) + + if ((retValue == CYRET_SUCCESS) && (needChecksumWorkaround != 0u)) + { + (void)memset((void *)¶meters[2u], 0, CY_FLASH_SIZEOF_ROW); + parameters[savedIndex] = savedValue; + + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Program Row */ + parameters[0u] = + (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_PROGRAM_ROW) << + CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[0u] |= (uint32)(rowNum << 16u); + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_PROGRAM_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + } + #endif /* (CY_FLASH_CHECKSUM_WORKAROUND) */ + + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + clkCnfRetValue = CySysFlashClockRestore(); + + if(clkCnfRetValue != CY_SYS_FLASH_SUCCESS) + { + retValue = clkCnfRetValue; + } + } + + CyExitCriticalSection(interruptState); + } + } + else + { + retValue = CY_SYS_FLASH_INVALID_ADDR; + } + + return (retValue); +} + + + +#if (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) +/******************************************************************************* +* Function Name: CySysFlashStartWriteRow +****************************************************************************//** +* +* Initiates a write to a row of Flash. A call to this API is non-blocking. +* Use CySysFlashResumeWriteRow() to resume flash writes and +* CySysFlashGetWriteRowStatus() to ascertain status of the write operation. +* +* The devices require HFCLK to be sourced by 48 MHz IMO during flash write. +* This API will modify IMO configuration; it can be later restored to original +* configuration by calling \ref CySysFlashGetWriteRowStatus(). +* +* \note The non-blocking operation does not return success status +* CY_SYS_FLASH_SUCCESS until the last \ref CySysFlashResumeWriteRow API +* is complete. The CPUSS_SYSARG register will be reflecting the SRAM address +* during an ongoing non-blocking operation. +* +* \param rowNum The flash row number. The number of the flash rows is defined by +* the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. Refer to the +* device datasheet for the details. +* \note The target flash array is calculated based on the specified flash row. +* +* \param rowData Array of bytes to write. The size of the array must be equal to +* the flash row size. The flash row size for the selected device is defined by +* the \ref CY_FLASH_SIZEOF_ROW macro. Refer to the device datasheet for the +* details. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashStartWriteRow(uint32 rowNum, const uint8 rowData[]) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 parameters[(CY_FLASH_SIZEOF_ROW + CY_FLASH_SRAM_ROM_DATA) / sizeof(uint32)]; + uint8 interruptState; + +#if(CY_IP_SPCIF_SYNCHRONOUS) + volatile uint32 clkCnfRetValue = CY_SYS_FLASH_SUCCESS; +#endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if ((rowNum < CY_FLASH_NUMBER_ROWS) && (rowData != 0u)) + { + /* Copy data to be written into internal variable */ + (void)memcpy((void *)¶meters[2u], rowData, CY_FLASH_SIZEOF_ROW); + + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /*************************************************************** + * Mask all the exceptions to guarantee that Flash write will + * occur in the atomic way. It will not affect system call + * execution (flash row write) since it is executed in the NMI + * context. + ***************************************************************/ + interruptState = CyEnterCriticalSection(); + + #if(CY_IP_SPCIF_SYNCHRONOUS) + clkCnfRetValue = CySysFlashClockBackup(); + + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + retValue = CySysFlashClockConfig(); + } + #else + (void)CySysFlashClockBackup(); + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Non-blocking Write Row */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_NON_BLOCKING_WRITE_ROW) << + CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[0u] |= (uint32)(rowNum << 16u); + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_NON_BLOCKING_WRITE_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + + CyExitCriticalSection(interruptState); + } + } + else + { + retValue = CY_SYS_FLASH_INVALID_ADDR; + } + + return (retValue); +} + + +/******************************************************************************* +* Function Name: CySysFlashGetWriteRowStatus +****************************************************************************//** +* +* Returns the current status of the flash write operation. +* +** \note The non-blocking operation does not return success status +* CY_SYS_FLASH_SUCCESS until the last \ref CySysFlashResumeWriteRow API +* is complete. The CPUSS_SYSARG register will be reflecting the SRAM address +* during an ongoing non-blocking operation. +* Calling this API before starting a non-blocking write row operation +* using the \ref CySysFlashStartWriteRow() API will cause improper operation. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashGetWriteRowStatus(void) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + (void) CySysFlashClockRestore(); + + return (retValue); +} + + +/******************************************************************************* +* Function Name: CySysFlashResumeWriteRow +****************************************************************************//** +* +* This API must be called, once the SPC interrupt is triggered to complete the +* non-blocking operation. It is advised not to prolong calling this API for +* more than 25 ms. +* +* The non-blocking write row API \ref CySysFlashStartWriteRow() requires that +* this API be called 3 times to complete the write. This can be done by +* configuring SPCIF interrupt and placing a call to this API. +* +* For CM0 based device, a non-blocking call to program a row of macro 0 +* requires the user to set the CPUSS_CONFIG.VECS_IN_RAM bit so that the +* interrupt vector for the SPC is fetched from the SRAM rather than the FLASH. +* +* For CM0+ based device, if the user wants to keep the vector table in flash +* when performing non-blocking flash write then they need to make sure the +* vector table is placed in the flash macro which is not getting programmed by +* configuring the VTOR register. +* +* \note The non-blocking operation does not return success status +* CY_SYS_FLASH_SUCCESS until the last Resume API is complete. +* The CPUSS_SYSARG register will be reflecting the SRAM address during an +* ongoing non-blocking operation. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysFlashResumeWriteRow(void) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + static volatile uint32 parameters[1u]; + + /* Resume */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_RESUME_NON_BLOCKING) << + CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_RESUME_NON_BLOCKING; + + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + return (retValue); +} + +#endif /* (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) */ + + +/******************************************************************************* +* Function Name: CySysFlashSetWaitCycles +****************************************************************************//** +* +* Sets the number of clock cycles the cache will wait before it samples data +* coming back from Flash. This function must be called before increasing the +* SYSCLK clock frequency. It can optionally be called after lowering SYSCLK +* clock frequency in order to improve the CPU performance. +* +* \param freq The System clock frequency in MHz. +* +* \note Invalid frequency will be ignored in Release mode and the CPU will be +* halted if project is compiled in Debug mode. +* +*******************************************************************************/ +void CySysFlashSetWaitCycles(uint32 freq) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_CPUSS) + + if ( freq <= CY_FLASH_SYSCLK_BOUNDARY_MHZ ) + { + CY_SYS_CLK_SELECT_REG &= (uint32)(~CY_FLASH_WAIT_STATE_EN); + } + else + { + CY_SYS_CLK_SELECT_REG |= CY_FLASH_WAIT_STATE_EN; + } + #else + #if (CY_IP_CPUSS_FLASHC_PRESENT) + /* CY_IP_FM and CY_IP_FS */ + if (freq <= CY_FLASH_CTL_WS_0_FREQ_MAX) + { + CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS_0_VALUE; + } else + if (freq <= CY_FLASH_CTL_WS_1_FREQ_MAX) + { + CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS_1_VALUE; + } else + #if (CY_IP_FMLT || CY_IP_FSLT) + if (freq <= CY_FLASH_CTL_WS_2_FREQ_MAX) + { + CY_FLASH_CTL_REG = (CY_FLASH_CTL_REG & ~CY_FLASH_CTL_WS_MASK) | CY_FLASH_CTL_WS_2_VALUE; + } + else + #endif /* (CY_IP_FMLT || CY_IP_FSLT) */ + #endif /* (CY_IP_CPUSS_FLASHC_PRESENT) */ + { + /* Halt CPU in debug mode if frequency is invalid */ + CYASSERT(0u != 0u); + } + + #endif /* (CY_IP_CPUSS) */ + + CyExitCriticalSection(interruptState); +} + + +#if (CY_SFLASH_XTRA_ROWS) +/******************************************************************************* +* Function Name: CySysSFlashWriteUserRow +****************************************************************************//** +* +* Writes data to a row of SFlash user configurable area. +* +* This API is applicable for PSoC 4100 BLE, PSoC 4200 BLE, PSoC 4100M, +* PSoC 4200M, and PSoC 4200L family of devices. +* +* \param rowNum The flash row number. The flash row number. The number of the +* flash rows is defined by the CY_SFLASH_NUMBER_USERROWS macro for the selected +* device. Valid range is 0-3. Refer to the device TRM for details. +* +* \param rowData Array of bytes to write. The size of the array must be equal to +* the flash row size. The flash row size for the selected device is defined by +* the \ref CY_SFLASH_SIZEOF_USERROW macro. Refer to the device TRM for the +* details. +* +* \return \ref group_flash_status_codes +* +*******************************************************************************/ +uint32 CySysSFlashWriteUserRow(uint32 rowNum, const uint8 rowData[]) +{ + volatile uint32 retValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 clkCnfRetValue = CY_SYS_FLASH_SUCCESS; + volatile uint32 parameters[(CY_FLASH_SIZEOF_ROW + CY_FLASH_SRAM_ROM_DATA)/4u]; + uint8 interruptState; + + + if ((rowNum < CY_SFLASH_NUMBER_USERROWS) && (rowData != 0u)) + { + /* Load Flash Bytes */ + parameters[0u] = (uint32) (CY_FLASH_GET_MACRO_FROM_ROW(rowNum) << CY_FLASH_PARAM_MACRO_SEL_OFFSET) | + (uint32) (CY_FLASH_PAGE_LATCH_START_ADDR << CY_FLASH_PARAM_ADDR_OFFSET ) | + (uint32) (CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_LOAD) << CY_FLASH_PARAM_KEY_TWO_OFFSET ) | + CY_FLASH_KEY_ONE; + parameters[1u] = CY_FLASH_SIZEOF_ROW - 1u; + + (void)memcpy((void *)¶meters[2u], rowData, CY_FLASH_SIZEOF_ROW); + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_LOAD; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /*************************************************************** + * Mask all the exceptions to guarantee that Flash write will + * occur in the atomic way. It will not affect system call + * execution (flash row write) since it is executed in the NMI + * context. + ***************************************************************/ + interruptState = CyEnterCriticalSection(); + + clkCnfRetValue = CySysFlashClockBackup(); + + #if(CY_IP_SPCIF_SYNCHRONOUS) + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + retValue = CySysFlashClockConfig(); + } + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + if(retValue == CY_SYS_FLASH_SUCCESS) + { + /* Write User Sflash Row */ + parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_WRITE_SFLASH_ROW) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) rowNum; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_WRITE_SFLASH_ROW; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + } + + if(clkCnfRetValue == CY_SYS_FLASH_SUCCESS) + { + clkCnfRetValue = CySysFlashClockRestore(); + } + CyExitCriticalSection(interruptState); + } + } + else + { + retValue = CY_SYS_FLASH_INVALID_ADDR; + } + + return (retValue); +} +#endif /* (CY_SFLASH_XTRA_ROWS) */ + + +/******************************************************************************* +* Function Name: CySysFlashClockBackup +****************************************************************************//** +* +* Backups the device clock configuration. +* +* \return The same as \ref CySysFlashWriteRow(). +* +*******************************************************************************/ +static cystatus CySysFlashClockBackup(void) +{ + cystatus retValue = CY_SYS_FLASH_SUCCESS; +#if(!CY_IP_FM) + #if !(CY_PSOC4_4000) + #if (CY_IP_SPCIF_SYNCHRONOUS) + volatile uint32 parameters[2u]; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + #endif /* !(CY_PSOC4_4000) */ +#endif /* (!CY_IP_FM) */ + +#if(CY_IP_FM) + + /*************************************************************** + * Preserve IMO configuration that could be changed during + * system call execution (Cypress ID #150448). + ***************************************************************/ + cySysFlashBackup.imoConfigReg = CY_SYS_CLK_IMO_CONFIG_REG; + +#else /* (CY_IP_FMLT) */ + + #if (CY_PSOC4_4000) + + /*************************************************************************** + * Perform firmware clock settings backup for the PSOC4 4000 devices (the + * corresponding system call is not available). + ***************************************************************************/ + + /*************************************************************************** + * The registers listed below are modified by CySysFlashClockConfig(). + * + * The registers to be saved: + * - CY_SYS_CLK_IMO_CONFIG_REG - IMO enable state. + * - CY_SYS_CLK_SELECT_REG - HFCLK source, divider, pump source. Save + * entire register as it can be directly + * written on restore (no special + * requirements). + * - CY_SYS_CLK_IMO_SELECT_REG - Save IMO frequency. + * + * The registers not to be saved: + * - CY_SYS_CLK_IMO_TRIM1_REG - No need to save. Function of frequency. + * Restored by CySysClkWriteImoFreq(). + * - CY_SYS_CLK_IMO_TRIM3_REG - No need to save. Function of frequency. + * Restored by CySysClkWriteImoFreq(). + * - REG_CPUSS_FLASH_CTL - Flash wait cycles. Unmodified due to system + * clock 16 MHz limit. + ***************************************************************************/ + + cySysFlashBackup.clkSelectReg = CY_SYS_CLK_SELECT_REG; + cySysFlashBackup.clkImoEna = CY_SYS_CLK_IMO_CONFIG_REG & CY_SYS_CLK_IMO_CONFIG_ENABLE; + cySysFlashBackup.clkImoFreq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ + (CY_SYS_CLK_IMO_SELECT_REG << 2u); + + #else + + #if (CY_IP_SPCIF_SYNCHRONOUS) + /* FM-Lite Clock Backup System Call */ + parameters[0u] = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_BACKUP) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) &cySysFlashBackup.clockSettings[0u]; + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_BACKUP; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + #endif /* (CY_PSOC4_4000) */ + +#endif /* (CY_IP_FM) */ + + return (retValue); +} + + +#if(CY_IP_SPCIF_SYNCHRONOUS) +/******************************************************************************* +* Function Name: CySysFlashClockConfig +****************************************************************************//** +* +* Configures the device clocks for the flash writing. +* +* \return The same as \ref CySysFlashWriteRow(). +* +*******************************************************************************/ +static cystatus CySysFlashClockConfig(void) +{ + cystatus retValue = CY_SYS_FLASH_SUCCESS; + + /*************************************************************************** + * The FM-Lite IP uses the IMO at 48MHz for the pump clock and SPC timer + * clock. The PUMP_SEL and HF clock must be set to IMO before calling Flash + * write or erase operation. + ***************************************************************************/ +#if (CY_PSOC4_4000) + + /*************************************************************************** + * Perform firmware clock settings setup for the PSOC4 4000 devices (the + * corresponding system call is not reliable): + * - The IMO frequency should be 48 MHz + * - The IMO should be source for the HFCLK + * - The IMO should be the source for the charge pump clock + * + * Note The structure members used below are initialized by + * the CySysFlashClockBackup() function. + ***************************************************************************/ + if ((cySysFlashBackup.clkImoFreq != 48u) || + ((cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) != CY_SYS_CLK_HFCLK_IMO) || + (((cySysFlashBackup.clkSelectReg >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & CY_SYS_CLK_SELECT_PUMP_SEL_MASK) != + CY_SYS_CLK_SELECT_PUMP_SEL_IMO)) + { + /*********************************************************************** + Set HFCLK divider to divide-by-4 to ensure that System clock frequency + * is within the valid limit (16 MHz for the PSoC4 4000). + ***********************************************************************/ + CySysClkWriteHfclkDiv(CY_SYS_CLK_HFCLK_DIV_4); + + /* The IMO frequency should be 48 MHz */ + if (cySysFlashBackup.clkImoFreq != 48u) + { + CySysClkWriteImoFreq(48u); + } + CySysClkImoStart(); + + /* The IMO should be source for the HFCLK */ + CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_IMO); + + /* The IMO should be the source for the charge pump clock */ + CY_SYS_CLK_SELECT_REG = (CY_SYS_CLK_SELECT_REG & + ((uint32)~(uint32)(CY_SYS_CLK_SELECT_PUMP_SEL_MASK << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT))) | + ((uint32)((uint32)1u << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT)); + } + +#else + + /* FM-Lite Clock Configuration */ + CY_FLASH_CPUSS_SYSARG_REG = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_CONFIG) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_CONFIG; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + +#endif /* (CY_PSOC4_4000) */ + + return (retValue); +} +#endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + +/******************************************************************************* +* Function Name: CySysFlashClockRestore +****************************************************************************//** +* +* Restores the device clock configuration. +* +* \return The same as \ref CySysFlashWriteRow(). +* +*******************************************************************************/ +static cystatus CySysFlashClockRestore(void) +{ + cystatus retValue = CY_SYS_FLASH_SUCCESS; +#if(!CY_IP_FM) + #if !(CY_PSOC4_4000) + #if (CY_IP_SPCIF_SYNCHRONOUS) + volatile uint32 parameters[2u]; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + #endif /* !(CY_PSOC4_4000) */ +#endif /* (!CY_IP_FM) */ + +#if(CY_IP_FM) + + /*************************************************************** + * Restore IMO configuration that could be changed during + * system call execution (Cypress ID #150448). + ***************************************************************/ + CY_SYS_CLK_IMO_CONFIG_REG = cySysFlashBackup.imoConfigReg; + +#else + + #if (CY_PSOC4_4000) + + /*************************************************************************** + * Perform firmware clock settings restore for the PSOC4 4000 devices (the + * corresponding system call is not available). + ***************************************************************************/ + + /* Restore clock settings */ + if ((cySysFlashBackup.clkImoFreq != 48u) || + ((cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) != CY_SYS_CLK_HFCLK_IMO) || + (((cySysFlashBackup.clkSelectReg >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & CY_SYS_CLK_SELECT_PUMP_SEL_MASK) != + CY_SYS_CLK_SELECT_PUMP_SEL_IMO)) + { + /* Restore IMO frequency if needed */ + if (cySysFlashBackup.clkImoFreq != 48u) + { + CySysClkWriteImoFreq(cySysFlashBackup.clkImoFreq); + } + + /* Restore HFCLK clock source */ + CySysClkWriteHfclkDirect(cySysFlashBackup.clkSelectReg & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + + /* Restore HFCLK divider and source for pump */ + CY_SYS_CLK_SELECT_REG = cySysFlashBackup.clkSelectReg; + + /* Stop IMO if needed */ + if (0u == cySysFlashBackup.clkImoEna) + { + CySysClkImoStop(); + } + } + + #else + + #if (CY_IP_SPCIF_SYNCHRONOUS) + /* FM-Lite Clock Restore */ + parameters[0u] = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_RESTORE) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) &cySysFlashBackup.clockSettings[0u]; + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_RESTORE; + CY_NOP; + retValue = CY_FLASH_API_RETURN; + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + #endif /* (CY_PSOC4_4000) */ + +#endif /* (CY_IP_FM) */ + + return (retValue); +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/CyFlash.h b/cores/asr650x/projects/PSoC4/CyFlash.h new file mode 100644 index 00000000..0ea8ecf1 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/CyFlash.h @@ -0,0 +1,293 @@ +/***************************************************************************//** +* \file CyFlash.h +* \version 5.70 +* +* \brief Provides the function definitions for the FLASH. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYFLASH_H) +#define CY_BOOT_CYFLASH_H + +#include "CyLib.h" + +/** +* \addtogroup group_flash + +\brief Flash memory in PSoC devices provides nonvolatile storage for user +firmware, user configuration data, and bulk data storage. See the device +datasheet and TRM for more information on Flash architecture. + +\section section_flash_protection Flash Protection +PSoC devices include a flexible flash-protection model that prevents access +and visibility to on-chip flash memory. The device offers the ability to +assign one of two protection levels to each row of flash: unprotected and +full protection. The required protection level can be selected using the Flash +Security tab of the PSoC Creator DWR file. Flash protection levels can only be +changed by performing a complete flash erase. The Flash programming APIs will +fail to write a row with Full Protection level. For more information on +protection model, refer to the Flash Security Editor section in the PSoC +Creator Help. + +\section section_flash_working_with Working with Flash +Flash programming operations are implemented as system calls. System calls are +executed out of SROM in the privileged mode of operation. Users have no access +to read or modify the SROM code. The CPU requests the system call by writing +the function opcode and parameters to the System Performance Controller (SPC) +input registers, and then requesting the SROM to execute the function. Based +on the function opcode, the SPC executes the corresponding system call from +SROM and updates the SPC status register. The CPU should read this status +register for the pass/fail result of the function execution. As part of +function execution, the code in SROM interacts with the SPC interface to do +the actual flash programming operations. + +It can take as many as 20 milliseconds to write to flash. During this time, +the device should not be reset, or unexpected changes may be made to portions +of the flash. Reset sources include XRES pin, software reset, and watchdog. +Make sure that these are not inadvertently activated. Also, the low voltage +detect circuits should be configured to generate an interrupt instead of a +reset. + +The flash can be read either by the cache controller or the SPC. Flash write +can be performed only by the SPC. Both the SPC and cache cannot simultaneously +access flash memory. If the cache controller tries to access flash at the same +time as the SPC, then it must wait until the SPC completes its flash access +operation. The CPU, which accesses the flash memory through the cache +controller, is therefore also stalled in this circumstance. If a CPU code +fetch has to be done from flash memory due to a cache miss condition, then the +cache would have to wait until the SPC completes the flash write operation. +Thus the CPU code execution will also be halted till the flash write is +complete. Flash is directly mapped into memory space and can be read directly. + +\note Flash write operations on PSoC 4000 devices modify the clock settings of +the device during the period of the write operation. +Refer to the \ref CySysFlashWriteRow() API documentation for details. + +* @{ +*/ + +uint32 CySysFlashWriteRow (uint32 rowNum, const uint8 rowData[]); +#if (CY_SFLASH_XTRA_ROWS) + uint32 CySysSFlashWriteUserRow (uint32 rowNum, const uint8 rowData[]); +#endif /* (CY_SFLASH_XTRA_ROWS) */ +void CySysFlashSetWaitCycles (uint32 freq); + +#if (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) + uint32 CySysFlashStartWriteRow(uint32 rowNum, const uint8 rowData[]); + uint32 CySysFlashGetWriteRowStatus(void); + uint32 CySysFlashResumeWriteRow(void); +#endif /* (CY_IP_FLASH_PARALLEL_PGM_EN && (CY_IP_FLASH_MACROS > 1u)) */ + +/** @} group_flash */ + + +#define CY_FLASH_BASE (CYDEV_FLASH_BASE) /**< The base pointer of the Flash memory.*/ +#define CY_FLASH_SIZE (CYDEV_FLASH_SIZE) /**< The size of the Flash memory. */ +#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE) /**< The size of Flash array. */ +#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE) /**< The size of the Flash row. */ +#define CY_FLASH_NUMBER_ROWS (CYDEV_FLASH_SIZE / CYDEV_FLS_ROW_SIZE) /**< The number of Flash row. */ +#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE) /**< The number of Flash arrays. */ + +#if (CY_SFLASH_XTRA_ROWS) + #define CY_SFLASH_USERBASE (CYREG_SFLASH_MACRO_0_FREE_SFLASH0) /**< The base pointer of the user SFlash memory. */ + #define CY_SFLASH_SIZE (CYDEV_SFLASH_SIZE) /**< The size of the SFlash memory. */ + #define CY_SFLASH_SIZEOF_USERROW (CYDEV_FLS_ROW_SIZE) /**< The size of the SFlash row. */ + #define CY_SFLASH_NUMBER_USERROWS (4u) /**< The number of SFlash row. */ +#endif /* (CY_SFLASH_XTRA_ROWS) */ + + +/** +* \addtogroup group_flash_status_codes Flash API status codes +* \ingroup group_flash +* @{ +*/ + +/** Completed successfully. */ +#define CY_SYS_FLASH_SUCCESS (0x00u) +/** Specified flash row address is invalid. The row id or byte address provided is outside of the available memory. */ +#define CY_SYS_FLASH_INVALID_ADDR (0x04u) +/** Specified flash row is protected. */ +#define CY_SYS_FLASH_PROTECTED (0x05u) +/** Resume Completed. All non-blocking calls have completed. The resume/abort function cannot be called until the +next non-blocking. */ +#define CY_SYS_FLASH_RESUME_COMPLETED (0x07u) +/** \brief Pending Resume. A non-blocking was initiated and must be completed by calling the resume API, before any other +function may be called. */ +#define CY_SYS_FLASH_PENDING_RESUME (0x08u) +/** System Call Still In Progress. A resume or non-blocking is still in progress. The SPC ISR must fire before +attempting the next resume. */ +#define CY_SYS_FLASH_CALL_IN_PROGRESS (0x09u) +/** Invalid Flash Clock. Products using CY_IP_SRSSLT must set the IMO to 48MHz and the HF clock source to the IMO clock +before Write/Erase operations. */ +#define CY_SYS_FLASH_INVALID_CLOCK (0x12u) +/** @} group_flash_status_codes */ + +#define CY_SYS_SFLASH_SUCCESS (CY_SYS_FLASH_SUCCESS) +#define CY_SYS_SFLASH_INVALID_ADDR (CY_SYS_FLASH_INVALID_ADDR) +#define CY_SYS_SFLASH_PROTECTED (CY_SYS_FLASH_PROTECTED) + +/* CySysFlashSetWaitCycles() - implementation definitions */ +#define CY_FLASH_WAIT_STATE_EN (( uint32 )(( uint32 )0x01u << 18u)) +#define CY_FLASH_SYSCLK_BOUNDARY_MHZ (24u) +#if (CY_IP_CPUSS_FLASHC_PRESENT) + /* CySysFlashSetWaitCycles() */ + #if(CY_IP_FM || CY_IP_FS) + #define CY_FLASH_CTL_WS_0_FREQ_MIN (0u) + #define CY_FLASH_CTL_WS_0_FREQ_MAX (24u) + + #define CY_FLASH_CTL_WS_1_FREQ_MIN (24u) + #define CY_FLASH_CTL_WS_1_FREQ_MAX (48u) + #else /* (CY_IP_FMLT || CY_IP_FSLT) */ + #define CY_FLASH_CTL_WS_0_FREQ_MIN (0u) + #define CY_FLASH_CTL_WS_0_FREQ_MAX (16u) + + #define CY_FLASH_CTL_WS_1_FREQ_MIN (16u) + #define CY_FLASH_CTL_WS_1_FREQ_MAX (32u) + + #define CY_FLASH_CTL_WS_2_FREQ_MIN (32u) + #define CY_FLASH_CTL_WS_2_FREQ_MAX (48u) + #endif /* (CY_IP_FM || CY_IP_FS) */ + + #define CY_FLASH_CTL_WS_MASK ((uint32) 0x03u) + #define CY_FLASH_CTL_WS_0_VALUE (0x00u) + #define CY_FLASH_CTL_WS_1_VALUE (0x01u) + #if(CY_IP_FMLT || CY_IP_FSLT) + #define CY_FLASH_CTL_WS_2_VALUE (0x02u) + #endif /* (CY_IP_FMLT || CY_IP_FSLT) */ +#endif /* (CY_IP_CPUSS_FLASHC_PRESENT) */ + + +#define CY_FLASH_KEY_ONE (0xB6u) +#define CY_FLASH_KEY_TWO(x) ((uint32) (((uint16) 0xD3u) + ((uint16) (x)))) + +#define CY_FLASH_PAGE_LATCH_START_ADDR ((uint32) (0x00u)) +#define CY_FLASH_ROW_NUM_MASK (0x100u) +#define CY_FLASH_CPUSS_REQ_START (( uint32 )(( uint32 )0x1u << 31u)) + +/* Opcodes */ +#define CY_FLASH_API_OPCODE_LOAD (0x04u) +#define CY_FLASH_API_OPCODE_WRITE_ROW (0x05u) +#define CY_FLASH_API_OPCODE_NON_BLOCKING_WRITE_ROW (0x07u) +#define CY_FLASH_API_OPCODE_RESUME_NON_BLOCKING (0x09u) + +#define CY_FLASH_API_OPCODE_PROGRAM_ROW (0x06u) +#define CY_FLASH_API_OPCODE_WRITE_SFLASH_ROW (0x18u) + +#define CY_FLASH_API_OPCODE_CLK_CONFIG (0x15u) +#define CY_FLASH_API_OPCODE_CLK_BACKUP (0x16u) +#define CY_FLASH_API_OPCODE_CLK_RESTORE (0x17u) + +/* SROM API parameters offsets */ +#define CY_FLASH_PARAM_KEY_TWO_OFFSET (8u) +#define CY_FLASH_PARAM_ADDR_OFFSET (16u) +#define CY_FLASH_PARAM_MACRO_SEL_OFFSET (24u) + +#if (CY_IP_FLASH_MACROS == 2u) + /* Macro #0: rows 0x00-0x1ff, Macro #1: rows 0x200-0x3ff */ + #define CY_FLASH_GET_MACRO_FROM_ROW(row) ((uint32)(((row) > 0x1ffu) ? 1u : 0u)) +#else + /* Only macro # 0 is available */ + #define CY_FLASH_GET_MACRO_FROM_ROW(row) ((uint32)(((row) != 0u) ? 0u : 0u)) +#endif /* (CY_IP_FLASH_MACROS == 2u) */ + +#if(CY_IP_FMLT) + /* SROM size greater than 4k */ + #define CY_FLASH_IS_BACKUP_RESTORE (CYDEV_SROM_SIZE > 0x00001000u) +#endif /* (CY_IP_FMLT) */ + + +#if(CY_IP_SRSSV2) + #define CY_FLASH_CLOCK_BACKUP_SIZE (4u) +#else /* CY_IP_SRSSLT */ + #define CY_FLASH_CLOCK_BACKUP_SIZE (6u) +#endif /* (CY_IP_SRSSV2) */ + + +typedef struct cySysFlashClockBackupStruct +{ +#if(CY_IP_FM) + uint32 imoConfigReg; +#else /* (CY_IP_FMLT) */ + #if (CY_PSOC4_4000) + uint32 clkSelectReg; + uint32 clkImoEna; + uint32 clkImoFreq; + #else + + #if(CY_IP_SRSSV2) + uint32 clkImoPump; + #endif /* (CY_IP_SRSSV2) */ + + #if (CY_IP_SPCIF_SYNCHRONOUS) + uint32 clockSettings[CY_FLASH_CLOCK_BACKUP_SIZE]; /* FM-Lite Clock Backup */ + #endif /* (CY_IP_SPCIF_SYNCHRONOUS) */ + + #endif /* (CY_PSOC4_4000) */ + +#endif /* (CY_IP_FM) */ +} CY_SYS_FLASH_CLOCK_BACKUP_STRUCT; + + +/* SYSARG control register */ +#define CY_FLASH_CPUSS_SYSARG_REG (*(reg32 *) CYREG_CPUSS_SYSARG) +#define CY_FLASH_CPUSS_SYSARG_PTR ( (reg32 *) CYREG_CPUSS_SYSARG) + +/* SYSCALL control register */ +#define CY_FLASH_CPUSS_SYSREQ_REG (*(reg32 *) CYREG_CPUSS_SYSREQ) +#define CY_FLASH_CPUSS_SYSREQ_PTR ( (reg32 *) CYREG_CPUSS_SYSREQ) + +#if (CY_IP_CPUSS_FLASHC_PRESENT) + /* SYSARG control register */ + #define CY_FLASH_CTL_REG (*(reg32 *) CYREG_CPUSS_FLASH_CTL) + #define CY_FLASH_CTL_PTR ( (reg32 *) CYREG_CPUSS_FLASH_CTL) +#endif /* (CY_IP_CPUSS_FLASHC_PRESENT) */ + + +#define CY_FLASH_API_RETURN (((CY_FLASH_CPUSS_SYSARG_REG & 0xF0000000u) == 0xF0000000u) ? \ + (CY_FLASH_CPUSS_SYSARG_REG & 0x000000FFu) : \ + (((CY_FLASH_CPUSS_SYSARG_REG & 0xF0000000u) == 0xA0000000u) ? \ + CYRET_SUCCESS : (CY_FLASH_CPUSS_SYSARG_REG & 0x000000FFu))) + + +/******************************************************************************* +* Thne following code is OBSOLETE and must not be used starting with cy_boot +* 4.20. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CY_FLASH_SRAM_ROM_KEY1 (( uint32 )0x00u) +#define CY_FLASH_SRAM_ROM_PARAM2 (CY_FLASH_SRAM_ROM_KEY1 + 0x04u) +#define CY_FLASH_SRAM_ROM_DATA (CY_FLASH_SRAM_ROM_KEY1 + 0x08u) + +#define CY_FLASH_SROM_CMD_RETURN_MASK (0xF0000000u) +#define CY_FLASH_SROM_CMD_RETURN_SUCC (0xA0000000u) +#define CY_FLASH_SROM_KEY1 (( uint32 )0xB6u) +#define CY_FLASH_SROM_KEY2_LOAD (( uint32 )0xD7u) +#define CY_FLASH_SROM_KEY2_WRITE (( uint32 )0xD8u) +#define CY_FLASH_SROM_LOAD_CMD ((CY_FLASH_SROM_KEY2_LOAD << 8u) | CY_FLASH_SROM_KEY1) +#define CY_FLASH_LOAD_BYTE_OPCODE (( uint32 )0x04u) +#define CY_FLASH_WRITE_ROW_OPCODE (( uint32 )0x05u) + + +#endif /* (CY_BOOT_CYFLASH_H) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/CyLFClk.c b/cores/asr650x/projects/PSoC4/CyLFClk.c new file mode 100644 index 00000000..86a9f3fc --- /dev/null +++ b/cores/asr650x/projects/PSoC4/CyLFClk.c @@ -0,0 +1,3232 @@ +/***************************************************************************//** +* \file .c +* \version 1.20 +* +* \brief +* This file provides the source code for configuring watchdog timers WDTs, +* low frequency clocks (LFCLK) and the Real-time Clock (RTC) component in +* PSoC Creator for the PSoC 4 families. +* +******************************************************************************** +* \copyright +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include "CyLFClk.h" +#include "CyLib.h" + + + +#if (CY_IP_WCO && CY_IP_SRSSV2) + static uint32 CySysClkGetLfclkSource(void); +#endif /* (CY_IP_WCO && CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + /* Default Ilo Trim Register value for ILO trimming*/ + static volatile uint16 defaultIloTrimRegValue = CY_SYS_CLK_ILO_TRIM_DEFAULT_VALUE; +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + +#if(CY_IP_SRSSV2) + /* CySysClkLfclkPosedgeCatch() / CySysClkLfclkPosedgeRestore() */ + static uint32 lfclkPosedgeWdtCounter0Enabled = 0u; + static uint32 lfclkPosedgeWdtCounter0Mode = CY_SYS_WDT_MODE_NONE; + + static volatile uint32 disableServicedIsr = 0uL; + static volatile uint32 wdtIsrMask = CY_SYS_WDT_COUNTER0_INT |\ + CY_SYS_WDT_COUNTER1_INT |\ + CY_SYS_WDT_COUNTER2_INT; + + static const uint32 counterIntMaskTbl[CY_WDT_NUM_OF_WDT] = {CY_SYS_WDT_COUNTER0_INT, + CY_SYS_WDT_COUNTER1_INT, + CY_SYS_WDT_COUNTER2_INT}; + + static void CySysClkLfclkPosedgeCatch(void); + static void CySysClkLfclkPosedgeRestore(void); + + static uint32 CySysWdtLocked(void); + static uint32 CySysClkIloEnabled(void); +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + static uint32 CySysClkGetTimerSource(void); + static volatile uint32 disableTimerServicedIsr = 0uL; + static volatile uint32 timerIsrMask = CY_SYS_TIMER0_INT |\ + CY_SYS_TIMER1_INT |\ + CY_SYS_TIMER2_INT; + + static const uint32 counterTimerIntMaskTbl[CY_SYS_NUM_OF_TIMERS] = {CY_SYS_TIMER0_INT, + CY_SYS_TIMER1_INT, + CY_SYS_TIMER2_INT}; + + static cyTimerCallback cySysTimerCallback[CY_SYS_NUM_OF_TIMERS] = {(void *)0, (void *)0, (void *)0}; +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_DWT_EN) */ + +#if(CY_IP_SRSSV2) + static cyWdtCallback cySysWdtCallback[CY_WDT_NUM_OF_WDT] = {(void *)0, (void *)0, (void *)0}; +#else + static cyWdtCallback cySysWdtCallback = (void *)0; +#endif /* (CY_IP_SRSSV2) */ + + +/******************************************************************************* +* Function Name: CySysClkIloStart +****************************************************************************//** +* \brief +* Enables ILO. +* +* Refer to the device datasheet for the ILO startup time. +* +*******************************************************************************/ +void CySysClkIloStart(void) +{ + CY_SYS_CLK_ILO_CONFIG_REG |= CY_SYS_CLK_ILO_CONFIG_ENABLE; +} + + +/******************************************************************************* +* Function Name: CySysClkIloStop +****************************************************************************//** +* \brief +* Disables the ILO. +* +* This function has no effect if WDT is locked (CySysWdtLock() is +* called). Call CySysWdtUnlock() to unlock WDT and stop ILO. +* +* PSoC 4100 / PSoC 4200: Note that ILO is required for WDT's operation. +* +* PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4200L / PSoC 4100M / +* PSoC 4200M: +* Stopping ILO affects the peripheral clocked by LFCLK, if +* LFCLK is configured to be sourced by ILO. +* +* If the ILO is disabled, all blocks run by ILO will stop functioning. +* +*******************************************************************************/ +void CySysClkIloStop(void) +{ + #if(CY_IP_SRSSV2) + uint8 interruptState; + + /* Do nothing if WDT is locked or ILO is disabled */ + if (0u == CySysWdtLocked()) + { + if (0u != CySysClkIloEnabled()) + { + + #if (CY_IP_WCO) + if (CY_SYS_CLK_LFCLK_SRC_ILO == CySysClkGetLfclkSource()) + { + #endif /* (CY_IP_WCO) */ + + interruptState = CyEnterCriticalSection(); + CySysClkLfclkPosedgeCatch(); + CY_SYS_CLK_ILO_CONFIG_REG &= (uint32) ( ~(uint32)CY_SYS_CLK_ILO_CONFIG_ENABLE); + CySysClkLfclkPosedgeRestore(); + CyExitCriticalSection(interruptState); + + #if (CY_IP_WCO) + } + else /* Safe to disable - shortened pulse does not impact peripheral */ + { + CY_SYS_CLK_ILO_CONFIG_REG &= (uint32) ( ~(uint32)CY_SYS_CLK_ILO_CONFIG_ENABLE); + } + #endif /* (CY_IP_WCO) */ + + } + } + #else + CY_SYS_CLK_ILO_CONFIG_REG &= ( uint32 ) ( ~( uint32 )CY_SYS_CLK_ILO_CONFIG_ENABLE); + #endif /* (CY_IP_SRSSV2) */ +} + + +/****************************************************************************** +* Function Name: CySysClkIloStartMeasurement +***************************************************************************//** +* \brief +* Starts the ILO accuracy measurement. +* +* This function is non-blocking and needs to be called before using the +* CySysClkIloTrim() and CySysClkIloCompensate() API. +* +* This API configures measurement counters to be sourced by SysClk (Counter 1) +* and ILO (Counter 2). +* +* \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and +* CySysClkIloCompensate() API can give incorrect results. +* +* In addition, this API stores the factory ILO trim settings on the first call +* after reset. This stored factory setting is used by the +* CySysClkIloRestoreFactoryTrim() API to restore the ILO factory trim. +* Hence, it is important to call this API before restoring the ILO +* factory trim settings. +* +******************************************************************************/ +void CySysClkIloStartMeasurement(void) +{ +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + static uint8 iloTrimTrig = 0u; + + /* Write default ILO trim value while ILO starting ( Cypress ID 225244 )*/ + if (0u == iloTrimTrig) + { + defaultIloTrimRegValue = ((uint8)(CY_SYS_CLK_ILO_TRIM_REG & CY_SYS_CLK_ILO_TRIM_MASK)); + iloTrimTrig = 1u; + } +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + + /* Configure measurement counters to source by SysClk (Counter 1) and ILO (Counter 2)*/ + CY_SYS_CLK_DFT_REG = (CY_SYS_CLK_DFT_REG & (uint32) ~CY_SYS_CLK_DFT_SELECT_DEFAULT_MASK) | + CY_SYS_CLK_SEL_ILO_DFT_SOURCE; + + CY_SYS_TST_DDFT_CTRL_REG = (CY_SYS_TST_DDFT_CTRL_REG & (uint32) ~ CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK) | + CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1; +} + + +/****************************************************************************** +* Function Name: CySysClkIloStopMeasurement +***************************************************************************//** +* \brief +* Stops the ILO accuracy measurement. +* +* Calling this function immediately stops the the ILO frequency measurement. +* This function should be called before placing the device to deepsleep, if +* CySysClkIloStartMeasurement() API was called before. +* +******************************************************************************/ +void CySysClkIloStopMeasurement(void) +{ + /* Set default configurations in 11...8 DFT register bits to zero */ + CY_SYS_CLK_DFT_REG &= ~CY_SYS_CLK_DFT_SELECT_DEFAULT_MASK; + #if(CY_IP_SRSSLT) + CY_SYS_TST_DDFT_CTRL_REG &= ((uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + #endif /* (CY_IP_SRSSLT) */ +} + + +/****************************************************************************** +* Function Name: CySysClkIloCompensate +***************************************************************************//** +* \brief +* This API measures the current ILO accuracy. +* +* Basing on the measured frequency the required number of ILO cycles for a +* given delay (in microseconds) is obtained. The desired delay that needs to +* be compensated is passed through the desiredDelay parameter. The compensated +* cycle count is returned through the compesatedCycles pointer. +* The compensated ILO cycles can then be used to define the WDT period value, +* effectively compensating for the ILO inaccuracy and allowing a more +* accurate WDT interrupt generation. +* +* CySysClkIloStartMeasurement() API should be called prior to calling this API. +* +* \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and +* CySysClkIloCompensate() API can give incorrect results. +* +* \note If the System clock frequency is changed in runtime, the CyDelayFreq() +* with the appropriate parameter (Frequency of bus clock in Hertz) should be +* called before calling a next CySysClkIloCompensate(). +* +* \warning Do not enter deep sleep mode until the function returns CYRET_SUCCESS. +* +* \param desiredDelay Required delay in microseconds. +* +* \param *compensatedCycles The pointer to the variable in which the required +* number of ILO cycles for the given delay will be returned. +* +* \details +* The value returned in *compensatedCycles pointer is not valid until the +* function returns CYRET_SUCCESS. +* +* The desiredDelay parameter value should be in next range:
From 100 to +* 2 000 000 microseconds for PSoC 4000 / PSoC 4000S / PSoC 4100S / PSoC Analog +* Coprocessor devices.
From 100 to 4 000 000 000 microseconds for +* PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / +* PSoC 4200L / PSoC 4100M /PSoC 4200M devices. +* +* \return CYRET_SUCCESS - The compensation process is complete and the +* compensated cycles value is returned in the compensatedCycles pointer. +* +* \return CYRET_STARTED - Indicates measurement is in progress. It is +* strongly recommended to do not make pauses between API calling. The +* function should be called repeatedly until the API returns CYRET_SUCCESS. +* +* \return CYRET_INVALID_STATE - Indicates that measurement not started. +* The user should call CySysClkIloStartMeasurement() API before calling +* this API. +* +* \note For a correct WDT or DeepSleep Timers functioning with ILO compensating +* the CySysClkIloCompensate() should be called before WDT or DeepSleep Timers +* enabling. +* +*******************************************************************************/ +cystatus CySysClkIloCompensate(uint32 desiredDelay , uint32* compensatedCycles) +{ + uint32 iloCompensatedCycles; + uint32 desiredDelayInCounts; + static uint32 compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + uint32 checkStatus; + cystatus returnStatus; + + checkStatus = (uint32) (CY_SYS_CLK_DFT_REG & (uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + + /* Check if CySysStartMeasurement was called before */ + if((checkStatus == CY_SYS_CLK_SEL_ILO_DFT_SOURCE) && + (CY_SYS_TST_DDFT_CTRL_REG == CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1) && + (CY_SYS_CLK_MAX_DELAY_US >= desiredDelay) && + (CY_SYS_CLK_MIN_DELAY_US <= desiredDelay) && + (compensatedCycles != NULL)) + { + if(CY_SYS_CLK_TRIM_OR_COMP_FINISHED != compensateRunningStatus) + { + /* Wait until counter 1 stopped counting and after it calculate compensated cycles */ + if(0u != (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + { + if (0u != CY_SYS_CNT_REG2_REG) + { + /* Calculate required number of ILO cycles for given delay */ + #if(CY_IP_SRSSV2) + if (CY_SYS_CLK_DELAY_COUNTS_LIMIT < desiredDelay) + { + desiredDelayInCounts = (desiredDelay / CY_SYS_CLK_ILO_PERIOD); + iloCompensatedCycles = + (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) >> + CY_SYS_CLK_ILO_FREQ_2MSB) * (desiredDelayInCounts / CY_SYS_CLK_ILO_FREQ_3LSB); + } + else + { + desiredDelayInCounts = ((desiredDelay * CY_SYS_CLK_COEF_PHUNDRED) + + CY_SYS_CLK_HALF_OF_CLOCK) / CY_SYS_CLK_ILO_PERIOD_PPH; + + iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / + (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) * + desiredDelayInCounts) / CY_SYS_CLK_ILO_DESIRED_FREQ_HZ; + } + #else /* (CY_IP_SRSSLT) */ + desiredDelayInCounts = ((desiredDelay * CY_SYS_CLK_COEF_PHUNDRED) + CY_SYS_CLK_HALF_OF_CLOCK) / + CY_SYS_CLK_ILO_PERIOD_PPH; + if(CY_SYS_CLK_MAX_LITE_NUMBER < desiredDelayInCounts) + { + iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydelayFreqHz >> + CY_SYS_CLK_SYS_CLK_DEVIDER)) / CY_SYS_CLK_ILO_FREQ_2MSB) * + (desiredDelayInCounts / CY_SYS_CLK_ILO_FREQ_3LSB); + } + else + { + iloCompensatedCycles = (((CY_SYS_CNT_REG2_REG * cydelayFreqHz) / + (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER)) * + desiredDelayInCounts) / CY_SYS_CLK_ILO_DESIRED_FREQ_HZ; + } + #endif /* (CY_IP_SRSSV2) */ + + *compensatedCycles = iloCompensatedCycles; + compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + returnStatus = CYRET_SUCCESS; + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + } + else + { + returnStatus = CYRET_STARTED; + } + } + else + { + /* Reload CNTR 1 count value for next measurement cycle*/ + CY_SYS_CNT_REG1_REG = (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER); + compensateRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_STARTED; + returnStatus = CYRET_STARTED; + } + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + + return (returnStatus); +} + + +#if(CY_IP_SRSSV2) + /******************************************************************************* + * Function Name: CySysClkIloEnabled + ****************************************************************************//** + * + * \internal + * Reports the ILO enable state. + * + * \return + * 1 if ILO is enabled, and 0 if ILO is disabled. + * + * \endinternal + ********************************************************************************/ + static uint32 CySysClkIloEnabled(void) + { + /* Prohibits writing to WDT registers and ILO/WCO registers when not equal to 0 */ + return ((0u != (CY_SYS_CLK_ILO_CONFIG_REG & (uint32)(CY_SYS_CLK_ILO_CONFIG_ENABLE))) ? + (uint32) 1u : + (uint32) 0u); + } +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) +/******************************************************************************** +* Function Name: CySysClkIloTrim +*****************************************************************************//** +* \brief +* The API trims the ILO frequency to +/- 10% accuracy range using accurate +* SysClk. +* +* The API can be blocking or non-blocking depending on the value of the mode +* parameter passed. The accuracy of ILO after trimming in parts per thousand +* is returned through the iloAccuracyInPPT pointer. A positive number indicates +* that the ILO is running fast and a negative number indicates that the ILO is +* running slowly. This error is relative to the error in the reference clock +* (SysClk), so the absolute error will be higher and depends on the accuracy +* of the reference. +* +* The CySysClkIloStartMeasurement() API should be called prior to calling this +* API. Otherwise it will return CYRET_INVALID_STATE as the measurement was not +* started. +* +* \note SysClk should be sourced by IMO. Otherwise CySysClkIloTrim() and +* CySysClkIloCompensate() API can give incorrect results. +* +* \note If System clock frequency is changed in runtime, the CyDelayFreq() +* with the appropriate parameter (Frequency of bus clock in Hertz) should be +* called before next CySysClkIloCompensate() usage. +* +* \warning Do not enter deep sleep mode until the function returns CYRET_SUCCESS +* or CYRET_TIMEOUT. +* +* Available for all PSoC 4 devices with ILO trim capability. This excludes +* PSoC 4000 / PSoC 4100 / PSoC 4200 / PSoC 4000S / PSoC 4100S / PSoC +* Analog Coprocessor devices. +* +* \param mode +* CY_SYS_CLK_BLOCKING - The function does not return until the ILO is +* within +/-10% accuracy range or time out has occurred.
+* CY_SYS_CLK_NON_BLOCKING - The function returns immediately after +* performing a single iteration of the trim process. The function should be +* called repeatedly until the trimming is completed successfully. +* +* \param *iloAccuracyInPPT Pointer to an integer in which the trimmed ILO +* accuracy will be returned. +* +* \details The value returned in *iloAccuracyInPPT pointer is not valid +* until the function returns CYRET_SUCCESS. ILO accuracy in PPT is given by: +* +* IloAccuracyInPPT = ((MeasuredIloFreq - DesiredIloFreq) * +* CY_SYS_CLK_PERTHOUSAND) / DesiredIloFreq); +* +* DesiredIloFreq = 32000, CY_SYS_CLK_PERTHOUSAND = 1000; +* +* \return CYRET_SUCCESS - Indicates trimming is complete. This value indicates +* trimming is successful and iloAccuracyInPPT is within +/- 10%. +* +* \return CYRET_STARTED - Indicates measurement is in progress. This is applicable +* only for non-blocking mode. +* +* \return CYRET_INVALID_STATE - Indicates trimming was unsuccessful. You should +* call CySysClkIloStartMeasurement() before calling this API. +* +* \return CYRET_TIMEOUT - Indicates trimming was unsuccessful. This is applicable +* only for blocking mode. Timeout means the trimming was tried 5 times without +* success (i.e. ILO accuracy > +/- 10%). The user can call the API again for +* another try or wait for some time before calling it again (to let the system +* to settle to another operating point change in temperature etc.) and continue +* using the previous trim value till the next call. +* +**********************************************************************************/ +cystatus CySysClkIloTrim(uint32 mode, int32* iloAccuracyInPPT) +{ + uint32 timeOutClocks = CY_SYS_CLK_TIMEOUT; + uint32 waitUntilCntr1Stops; + static uint32 trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + uint32 checkStatus; + cystatus returnStatus; + + checkStatus = (uint32) (CY_SYS_CLK_DFT_REG & (uint32) CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK); + + /* Check if DFT and CTRL registers were configures in CySysStartMeasurement*/ + if((checkStatus == CY_SYS_CLK_SEL_ILO_DFT_SOURCE) && + (CY_SYS_TST_DDFT_CTRL_REG == CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1) && + (iloAccuracyInPPT != NULL)) + { + if(CY_SYS_CLK_BLOCKING == mode) + { + waitUntilCntr1Stops = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + do + { + /* Reload CNTR 1 count value for measuring cycle*/ + CY_SYS_CNT_REG1_REG = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + + /* Wait until counter CNTR 1 will finish down-counting */ + while (0u == (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + { + waitUntilCntr1Stops--; + if (0u == waitUntilCntr1Stops) + { + break; + } + } + trimRunningStatus = CySysClkIloUpdateTrimReg(iloAccuracyInPPT); + timeOutClocks--; + + /* Untill ILO accuracy will be in range less than +/- 10% or timeout occurs*/ + } while((CYRET_SUCCESS != trimRunningStatus) && + (CYRET_INVALID_STATE != trimRunningStatus) && + (0u != timeOutClocks)); + + if (CYRET_SUCCESS == trimRunningStatus) + { + returnStatus = CYRET_SUCCESS; + } + else + { + if(0u == timeOutClocks) + { + trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + returnStatus = CYRET_TIMEOUT; + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + } + } + /* Non - blocking mode */ + else + { + if (CY_SYS_CLK_TRIM_OR_COMP_FINISHED != trimRunningStatus) + { + /* Checking if the counter CNTR 1 finished down-counting */ + if(0u != (CY_SYS_CNT_REG1_REG & CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK)) + { + returnStatus = CySysClkIloUpdateTrimReg(iloAccuracyInPPT); + trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_FINISHED; + } + else + { + returnStatus = CYRET_STARTED; + } + } + else + { + /* Reload CNTR 1 count value for next measuring */ + CY_SYS_CNT_REG1_REG = cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER; + trimRunningStatus = CY_SYS_CLK_TRIM_OR_COMP_STARTED; + returnStatus = CYRET_STARTED; + } + } + } + else + { + returnStatus = CYRET_INVALID_STATE; + } + + return (returnStatus); +} + + +/******************************************************************************** +* Function Name: CySysClkIloUpdateTrimReg +********************************************************************************* +* +* \internal +* Function calculates ILO accuracy and check is error range is higher than +* +/- 10%. If Measured frequency is higher than +/- 10% function updates +* ILO Trim register. +* +* \param +* iloAccuracyInPPT Pointer to an integer in which the trimmed ILO +* accuracy will be returned. The value returned in this pointer is not valid +* until the function returns CYRET_SUCCESS. If ILO frequency error is lower +* than +/- 10% then the value returned in this pointer will be updated. +* +* \return CYRET_SUCCESS - Indicates that ILO frequency error is lower than +* +/- 10% and no actions are required. +* +* \return CYRET_STARTED - Indicates that ILO frequency error is higher than +* +/- 10% and ILO Trim register was updated. +* +* \return CYRET_INVALID_STATE - Indicates trimming was unsuccessful. +* +* Post #1 - To obtain 10% ILO accuracy the calculated accuracy should be equal +* CY_SYS_CLK_ERROR_RANGE = 5.6%. Error value should take to account IMO error of +* +/-2% (+/-0.64kHz), trim step of 2.36kHz (+/-1.18kHz) and error while ILO +* frequency measuring. +* +* \endinternal +* +**********************************************************************************/ +cystatus CySysClkIloUpdateTrimReg(int32* iloAccuracyInPPT) +{ + uint32 measuredIloFreq; + uint32 currentIloTrimValue; + int32 iloAccuracyValue; + int32 trimStep; + cystatus errorRangeStatus; + + if(0u != CY_SYS_CNT_REG2_REG) + { + measuredIloFreq = (CY_SYS_CNT_REG2_REG * cydelayFreqHz) / (cydelayFreqHz >> CY_SYS_CLK_SYS_CLK_DEVIDER); + + /* Calculate value of error in PPT according to formula - + * ((measuredIlofrequency - iloDesired frequency) * 1000 / iloDesired frequency) */ + iloAccuracyValue = (((int32) measuredIloFreq - (int32) CY_SYS_CLK_ILO_DESIRED_FREQ_HZ) * \ + ((int32) CY_SYS_CLK_PERTHOUSAND)) / ((int32) CY_SYS_CLK_ILO_DESIRED_FREQ_HZ); + + /* Check if ILO accuracy is more than +/- CY_SYS_CLK_ERROR_RANGE. See post #1 of API description.*/ + if(CY_SYS_CLK_ERROR_RANGE < (uint32) (CY_SYS_CLK_ABS_MACRO(iloAccuracyValue))) + { + if (0 < iloAccuracyValue) + { + trimStep = (int32) (((iloAccuracyValue * (int32) CY_SYS_CLK_ERROR_COEF) + + CY_SYS_CLK_HALF_OF_STEP) / CY_SYS_CLK_ERROR_STEP); + } + else + { + trimStep = (int32) (((iloAccuracyValue * (int32) CY_SYS_CLK_ERROR_COEF) - + CY_SYS_CLK_HALF_OF_STEP) / CY_SYS_CLK_ERROR_STEP); + } + currentIloTrimValue = (CY_SYS_CLK_ILO_TRIM_REG & CY_SYS_CLK_ILO_TRIM_MASK); + trimStep = (int32) currentIloTrimValue - trimStep; + + if(trimStep > CY_SYS_CLK_FOURBITS_MAX) + { + trimStep = CY_SYS_CLK_FOURBITS_MAX; + } + if(trimStep < 0) + { + trimStep = 0; + } + CY_SYS_CLK_ILO_TRIM_REG = (CY_SYS_CLK_ILO_TRIM_REG & (uint32)(~CY_SYS_CLK_ILO_TRIM_MASK)) | + ((uint32) trimStep); + errorRangeStatus = CYRET_STARTED; + } /* Else return success because error is in +/- 10% range*/ + else + { + /* Write trimmed ILO accuracy through pointer. */ + *iloAccuracyInPPT = iloAccuracyValue; + errorRangeStatus = CYRET_SUCCESS; + } + } + else + { + errorRangeStatus = CYRET_INVALID_STATE; + } +return (errorRangeStatus); +} + + +/******************************************************************************* +* Function Name: CySysClkIloRestoreFactoryTrim +****************************************************************************//** +* \brief +* Restores the ILO Trim Register to factory value. +* +* The CySysClkIloStartMeasurement() API should be called prior to +* calling this API. Otherwise CYRET_UNKNOWN will be returned. +* +* Available for all PSoC 4 devices except for PSoC 4000 / PSoC 4100 / PSoC 4200 +* / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. +* +* \return CYRET_SUCCESS - Operation was successful. +* \return CYRET_UNKNOWN - CySysClkIloStartMeasurement() was not called +* before this API. Hence the trim value cannot be updated. +* +******************************************************************************/ +cystatus CySysClkIloRestoreFactoryTrim(void) +{ + cystatus returnStatus = CYRET_SUCCESS; + + /* Check was defaultIloTrimRegValue modified in CySysClkIloStartMeasurement */ + if(CY_SYS_CLK_ILO_TRIM_DEFAULT_VALUE != defaultIloTrimRegValue) + { + CY_SYS_CLK_ILO_TRIM_REG = ((CY_SYS_CLK_ILO_TRIM_REG & (uint32)(~CY_SYS_CLK_ILO_TRIM_MASK)) | + (defaultIloTrimRegValue & CY_SYS_CLK_ILO_TRIM_MASK)); + } + else + { + returnStatus = CYRET_UNKNOWN; + } + + return (returnStatus); +} +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + + +#if (CY_IP_WCO && CY_IP_SRSSV2) + /******************************************************************************* + * Function Name: CySysClkGetLfclkSource + ******************************************************************************** + * + * \internal + * Gets the clock source for the LFCLK clock. + * The function is applicable only for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L. + * + * \return The LFCLK source: + * CY_SYS_CLK_LFCLK_SRC_ILO Internal Low Frequency (32 kHz) Oscillator (ILO) + * CY_SYS_CLK_LFCLK_SRC_WCO Low Frequency Watch Crystal Oscillator (WCO) + * + * \endinternal + * + *******************************************************************************/ + static uint32 CySysClkGetLfclkSource(void) + { + uint32 lfclkSource; + lfclkSource = CY_SYS_WDT_CONFIG_REG & CY_SYS_CLK_LFCLK_SEL_MASK; + return (lfclkSource); + } + + + /******************************************************************************* + * Function Name: CySysClkSetLfclkSource + ****************************************************************************//** + * \brief + * Sets the clock source for the LFCLK clock. + * + * The switch between LFCLK sources must be done between the positive edges of + * LFCLK, because the glitch risk is around the LFCLK positive edge. To ensure + * that the switch can be done safely, the WDT counter value is read until it + * changes. + * + * That means that the positive edge just finished and the switch is performed. + * The enabled WDT counter is used for that purpose. If no counters are enabled, + * counter 0 is enabled. And after the LFCLK source is switched, counter 0 + * configuration is restored. + * + * The function is applicable only for devices with more than one source for + * LFCLK - PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L. + * + * \note For PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices LFCLK can + * only be sourced from ILO even though WCO is available. + * + * \param + * source + * CY_SYS_CLK_LFCLK_SRC_ILO - Internal Low Frequency (32 kHz) + * Oscillator (ILO).
+ * CY_SYS_CLK_LFCLK_SRC_WCO - Low Frequency Watch Crystal Oscillator (WCO). + * + * \details + * This function has no effect if WDT is locked (CySysWdtLock() is called). + * Call CySysWdtUnlock() to unlock WDT. + * + * Both the current source and the new source must be running and stable before + * calling this function. + * + * Changing the LFCLK clock source may change the LFCLK clock frequency and + * affect the functionality that uses this clock. For example, watchdog timer + * "uses this clock" or "this clock uses" (WDT) is clocked by LFCLK. + * + *******************************************************************************/ + void CySysClkSetLfclkSource(uint32 source) + { + uint8 interruptState; + + if (CySysClkGetLfclkSource() != source) + { + interruptState = CyEnterCriticalSection(); + CySysClkLfclkPosedgeCatch(); + CY_SYS_WDT_CONFIG_REG = (CY_SYS_WDT_CONFIG_REG & (uint32)(~CY_SYS_CLK_LFCLK_SEL_MASK)) | + (source & CY_SYS_CLK_LFCLK_SEL_MASK); + CySysClkLfclkPosedgeRestore(); + CyExitCriticalSection(interruptState); + } + } +#endif /* (CY_IP_WCO && CY_IP_SRSSV2) */ + + +#if (CY_IP_WCO) + /******************************************************************************* + * Function Name: CySysClkWcoStart + ****************************************************************************//** + * \brief + * Enables Watch Crystal Oscillator (WCO). + * + * This API enables WCO which is used as a source for LFCLK. Similar to ILO, + * WCO is also available in all modes except Hibernate and Stop modes. + * \note In PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices + * WCO cannot be a source for the LFCLK. + * + * WCO is always enabled in High Power Mode (HPM). Refer to the device + * datasheet for the WCO startup time. Once WCO becomes stable it can be + * switched to Low Power Mode (LPM). Note that oscillator can be unstable + * during a switch and hence its output should not be used at that moment. + * + * The CySysClkWcoSetPowerMode() function configures the WCO power mode. + * + *******************************************************************************/ + void CySysClkWcoStart(void) + { + CySysClkWcoSetHighPowerMode(); + CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + } + + + /******************************************************************************* + * Function Name: CySysClkWcoStop + ****************************************************************************//** + * \brief + * Disables the 32 KHz Crystal Oscillator. + * + * API switch of WCO. + * \note PSoC 4100S / PSoC Analog Coprocessor: WCO is required for DeepSleep + * Timer's operation. + * + *******************************************************************************/ + void CySysClkWcoStop(void) + { + #if (CY_IP_SRSSV2) + uint8 interruptState; + #endif /* (CY_IP_SRSSV2) */ + + if (0u != CySysClkWcoEnabled()) + { + #if (CY_IP_SRSSV2) + if (CY_SYS_CLK_LFCLK_SRC_WCO == CySysClkGetLfclkSource()) + { + interruptState = CyEnterCriticalSection(); + CySysClkLfclkPosedgeCatch(); + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + CySysClkLfclkPosedgeRestore(); + CyExitCriticalSection(interruptState); + } + else /* Safe to disable - shortened pulse does not impact peripheral */ + #endif /* (CY_IP_SRSSV2) */ + { + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE; + } + } /* Otherwise do nothing. WCO configuration cannot be changed. */ + } + + + /******************************************************************************* + * Function Name: CySysClkWcoEnabled + ****************************************************************************//** + * \internal Reports the WCO enable state. + * + * \return 1 if WCO is enabled + * \return 0 if WCO is disabled. + * \endinternal + *******************************************************************************/ + uint32 CySysClkWcoEnabled(void) + { + return ((0u != (CY_SYS_CLK_WCO_CONFIG_REG & (uint32)(CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE))) ? + (uint32) 1u : + (uint32) 0u); + } + + + /******************************************************************************* + * Function Name: CySysClkWcoSetPowerMode + ****************************************************************************//** + * \brief + * Sets the power mode for the 32 KHz WCO. + * + * By default (if this function is not called), the WCO is in High power mode + * during Active and device's low power modes + * + * \param mode + * CY_SYS_CLK_WCO_HPM - The High Power mode.
+ * CY_SYS_CLK_WCO_LPM - The Low Power mode. + * + * \return A previous power mode. The same as the parameters. + * + * \note + * The WCO Low Power mode is applicable for PSoC 4100 BLE / PSoC 4200 BLE devices. + * + *******************************************************************************/ + uint32 CySysClkWcoSetPowerMode(uint32 mode) + { + uint32 powerModeStatus; + + powerModeStatus = CY_SYS_CLK_WCO_CONFIG_REG & CY_SYS_CLK_WCO_CONFIG_LPM_EN; + + switch(mode) + { + case CY_SYS_CLK_WCO_HPM: + CySysClkWcoSetHighPowerMode(); + break; + + #if(CY_IP_BLESS) + case CY_SYS_CLK_WCO_LPM: + CySysClkWcoSetLowPowerMode(); + break; + #endif /* (CY_IP_BLESS) */ + + default: + CYASSERT(0u != 0u); + break; + } + + return (powerModeStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkWcoClockOutSelect + ****************************************************************************//** + * \brief + * Selects the WCO block output source. + * + * In addition to generating 32.768 kHz clock from external crystals, WCO + * can be sourced by external clock source using wco_out pin. The API help to + * lets you select between the sources: External crystal or external pin. + * + * If you want to use external pin to drive WCO the next procedure is required: + *
1) Disable the WCO. + *
2) Drive the wco_out pin to an external signal source. + *
3) Call CySysClkWcoClockOutSelect(CY_SYS_CLK_WCO_SEL_PIN). + *
4) Enable the WCO and wait for 15 us before clocking the XO pad at the high + * potential. Let's assume you are using the 1.6v clock amplitude, then the + * sequence would start at 1.6v, then 0v, then 1.6v etc at a chosen frequency. + * + * If you want to use WCO after using an external pin source: + *
1) Disable the WCO. + *
2) Drive off wco_out pin with external signal source. + *
3) Call CySysClkWcoClockOutSelect(CY_SYS_CLK_WCO_SEL_CRYSTAL). + *
4) Enable the WCO. + * + * \warning + * Do not use the oscillator output clock prior to a 15uS delay in your system. + * There are no limitations on the external clock frequency. + * \warning + * When external clock source was selected to drive WCO block the IMO can be + * trimmed only when external clock source period is equal to WCO external + * crystal period. Also external clock source accuracy should be higher + * or equal to WCO external crystal accuracy. + * + * \param clockSel + * CY_SYS_CLK_WCO_SEL_CRYSTAL - Selects External crystal as clock + * source of WCO.
+ * CY_SYS_CLK_WCO_SEL_PIN - Selects External clock input on wco_in pin as + * clock source of WCO. + * + *******************************************************************************/ + void CySysClkWcoClockOutSelect(uint32 clockSel) + { + if (0u != CySysClkWcoEnabled()) + { + if (1u >= clockSel) + { + CY_SYS_CLK_WCO_CONFIG_REG = (CY_SYS_CLK_WCO_CONFIG_REG & (uint32)(~CY_SYS_CLK_WCO_SELECT_PIN_MASK)) | + (clockSel << CY_SYS_CLK_WCO_SELECT_PIN_OFFSET); + } + else + { + CYASSERT(0u != 0u); + } + } + } +#endif /* (CY_IP_WCO) */ + + +#if(CY_IP_SRSSV2) + /******************************************************************************* + * Function Name: CySysWdtLock + ****************************************************************************//** + * \brief + * Locks out configuration changes to the Watchdog timer registers and ILO + * configuration register. + * + * After this function is called, ILO clock can't be disabled until + * CySysWdtUnlock() is called. + * + *******************************************************************************/ + void CySysWdtLock(void) + { + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_SELECT_REG = (CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) | + CY_SYS_WDT_CLK_LOCK_BITS_MASK; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysWdtLocked + ****************************************************************************//** + * \internal + * Reports the WDT lock state. + * + * \return 1 - WDT is locked, and 0 - WDT is unlocked. + * \endinternal + *******************************************************************************/ + static uint32 CySysWdtLocked(void) + { + /* Prohibits writing to WDT registers and ILO/WCO registers when not equal 0 */ + return ((0u != (CY_SYS_CLK_SELECT_REG & (uint32)(CY_SYS_WDT_CLK_LOCK_BITS_MASK))) ? (uint32) 1u : (uint32) 0u); + } + + + /******************************************************************************* + * Function Name: CySysWdtUnlock + ****************************************************************************//** + * \brief + * Unlocks the Watchdog Timer configuration register. + * + *******************************************************************************/ + void CySysWdtUnlock(void) + { + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + + /* Removing WDT lock requires two writes */ + CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) | + CY_SYS_WDT_CLK_LOCK_BIT0); + + CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & (uint32)(~CY_SYS_WDT_CLK_LOCK_BITS_MASK)) | + CY_SYS_WDT_CLK_LOCK_BIT1); + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetEnabledStatus + ****************************************************************************//** + * \brief + * Reads the enabled status of one of the three WDT counters. + * + * \param counterNum: Valid range [0-2]. The number of the WDT counter. + * + * \return The status of the WDT counter: + * \return 0 - If the counter is disabled. + * \return 1 - If the counter is enabled. + * + * \details + * This function returns an actual WDT counter status from the status register. It may + * take up to 3 LFCLK cycles for the WDT status register to contain actual data + * after the WDT counter is enabled. + * + *******************************************************************************/ + uint32 CySysWdtGetEnabledStatus(uint32 counterNum) + { + CYASSERT(counterNum < CY_SYS_WDT_COUNTERS_MAX); + return ((CY_SYS_WDT_CONTROL_REG >> ((CY_SYS_WDT_CNT_SHIFT * counterNum) + CY_SYS_WDT_CNT_STTS_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetMode + ****************************************************************************//** + * \brief + * Writes the mode of one of the three WDT counters. + * + * \param counterNum: Valid range [0-2]. The number of the WDT counter. + * + * \param mode + * CY_SYS_WDT_MODE_NONE - Free running.
+ * CY_SYS_WDT_MODE_INT - The interrupt generated on match for counter 0 + * and 1, and on bit toggle for counter 2.
+ * CY_SYS_WDT_MODE_RESET - Reset on match (valid for counter 0 and 1 only).
+ * CY_SYS_WDT_MODE_INT_RESET - Generate an interrupt. Generate a reset on + * the 3rd non-handled interrupt (valid for counter 0 and counter 1 only). + * + * \details + * WDT counter counterNum should be disabled to set a mode. Otherwise, this + * function call has no effect. If the specified counter is enabled, + * call the CySysWdtDisable() function with the corresponding parameter to + * disable the specified counter and wait for it to stop. + * + *******************************************************************************/ + void CySysWdtSetMode(uint32 counterNum, uint32 mode) + { + uint32 configRegValue; + + CYASSERT(counterNum < CY_SYS_WDT_COUNTERS_MAX); + + if(0u == CySysWdtGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WDT_CONFIG_REG & + (uint32)~((uint32)(CY_SYS_WDT_MODE_MASK << (counterNum * CY_SYS_WDT_CNT_SHIFT))); + configRegValue |= (uint32)((mode & CY_SYS_WDT_MODE_MASK) << (counterNum * CY_SYS_WDT_CNT_SHIFT)); + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetMode + ****************************************************************************//** + * + * \brief Reads the mode of one of the three WDT counters. + * + * \param counterNum Valid range [0-2]. The number of the WDT counter. + * + * \return The mode of the counter. The same enumerated values as the mode + * parameter used in CySysWdtSetMode(). + * + *******************************************************************************/ + uint32 CySysWdtGetMode(uint32 counterNum) + { + return ((CY_SYS_WDT_CONFIG_REG >> (counterNum * CY_SYS_WDT_CNT_SHIFT)) & CY_SYS_WDT_MODE_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetClearOnMatch + ****************************************************************************//** + * + * \brief Configures the WDT counter "clear on match" setting. + * + * If configured to "clear on match", the counter counts from 0 to MatchValue + * giving it a period of (MatchValue + 1). + * + * \param counterNum + * Valid range [0-1]. The number of the WDT counter. The match values are not + * supported by counter 2. + * + * \param enable 0 to disable appropriate counter
+ * 1 to enable appropriate counter + * + * \details + * WDT counter counterNum should be disabled. Otherwise this function call + * has no effect. If the specified counter is enabled, call the CySysWdtDisable() + * function with the corresponding parameter to disable the specified counter and + * wait for it to stop. This may take up to three LFCLK cycles. + * + *******************************************************************************/ + void CySysWdtSetClearOnMatch(uint32 counterNum, uint32 enable) + { + uint32 configRegValue; + + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + if(0u == CySysWdtGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WDT_CONFIG_REG & (uint32)~((uint32)((uint32)1u << + ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CLR_SHIFT))); + + configRegValue + |= (uint32)(enable << ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CLR_SHIFT)); + + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetClearOnMatch + ****************************************************************************//** + * \brief + * Reads the "clear on match" setting for the specified counter. + * + * \param + * counterNum Valid range [0-1]. The number of the WDT counter. The match values + * are not supported by counter 2. + * + * \return The "clear on match" status:
1 if enabled
0 if disabled + * + *******************************************************************************/ + uint32 CySysWdtGetClearOnMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + return (uint32)((CY_SYS_WDT_CONFIG_REG >> + ((counterNum * CY_SYS_WDT_CNT_SHIFT) + CY_SYS_WDT_CNT_MATCH_CLR_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysWdtEnable + ****************************************************************************//** + * + * \brief Enables the specified WDT counters. + * + * All the counters specified in the mask are enabled. + * + * \param counterMask + * CY_SYS_WDT_COUNTER0_MASK - The mask for counter 0 to enable.
+ * CY_SYS_WDT_COUNTER1_MASK - The mask for counter 1 to enable.
+ * CY_SYS_WDT_COUNTER2_MASK - The mask for counter 2 to enable. + * + * \details + * Enabling or disabling WDT requires 3 LFCLK cycles to come into effect. + * Therefore, the WDT enable state must not be changed more than once in + * that period. + * + * After WDT is enabled, it is illegal to write WDT configuration (WDT_CONFIG) + * and control (WDT_CONTROL) registers. This means that all WDT functions that + * contain 'write' in the name (with the exception of CySysWdtSetMatch() + * function) are illegal to call if WDT is enabled. + * + * PSoC 4100 / PSoC 4200: This function enables ILO. + * + * PSoC 4100 BLE / PSoC 4200 BLE / PSoC4200L / PSoC 4100M + * / PSoC 4200M: + * LFLCK should be configured before calling this function. The desired + * source should be enabled and configured to be the source for LFCLK. + * + *******************************************************************************/ + void CySysWdtEnable(uint32 counterMask) + { + #if (!CY_IP_WCO) + CySysClkIloStart(); + #endif /* (!CY_IP_WCO) */ + + CY_SYS_WDT_CONTROL_REG |= counterMask; + + if(0u != (counterMask & CY_SYS_WDT_COUNTER0_MASK)) + { + while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER1_MASK)) + { + while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER2_MASK)) + { + while (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + /* Wait for changes to come into effect */ + } + } + } + + + /******************************************************************************* + * Function Name: CySysWdtDisable + ****************************************************************************//** + * + * \brief Disables the specified WDT counters. + * All the counters specified in the mask are disabled. The function waits for + * the changes to come into effect. + * + * \param counterMask + * CY_SYS_WDT_COUNTER0_MASK - The mask for counter 0 to disable.
+ * CY_SYS_WDT_COUNTER1_MASK - The mask for counter 1 to disable.
+ * CY_SYS_WDT_COUNTER2_MASK - The mask for counter 2 to disable. + * + *******************************************************************************/ + void CySysWdtDisable(uint32 counterMask) + { + if (0uL == CySysWdtLocked()) + { + CY_SYS_WDT_CONTROL_REG &= ~counterMask; + + if(0u != (counterMask & CY_SYS_WDT_COUNTER0_MASK)) + { + while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER1_MASK)) + { + while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_WDT_COUNTER2_MASK)) + { + while (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + /* Wait for changes to come into effect */ + } + } + } + } + + + /******************************************************************************* + * Function Name: CySysWdtSetCascade + ****************************************************************************//** + * \brief + * Writes the two WDT cascade values based on the combination of mask values + * specified. + * + * \param cascadeMask The mask value used to set or clear the cascade values: + * CY_SYS_WDT_CASCADE_NONE - Neither
+ * CY_SYS_WDT_CASCADE_01 - Cascade 01
+ * CY_SYS_WDT_CASCADE_12 - Cascade 12 + * + * If only one cascade mask is specified, the second cascade is disabled. + * To set both cascade modes, two defines should be ORed: + * (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12). + * \note If CySysWdtSetCascade() was called with ORed defines it is necessary + * to call CySysWdtSetClearOnMatch(1,1). It is needed to make sure that + * Counter 2 will be updated in the expected way. + * + * WDT counters that are part of the specified cascade should be disabled. + * Otherwise this function call has no effect. If the specified + * counter is enabled, call CySysWdtDisable() function with the corresponding + * parameter to disable the specified counter and wait for it to stop. This may + * take up to 3 LFCLK cycles. + * + *******************************************************************************/ + void CySysWdtSetCascade(uint32 cascadeMask) + { + uint32 configRegValue; + uint32 countersEnableStatus; + + countersEnableStatus = CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0) | + CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1) | + CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2); + + if (0u == countersEnableStatus) + { + configRegValue = CY_SYS_WDT_CONFIG_REG; + configRegValue &= ((uint32)(~(CY_SYS_WDT_CASCADE_01|CY_SYS_WDT_CASCADE_12))); + configRegValue |= cascadeMask; + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetCascade + ****************************************************************************//** + * + * \brief Reads the two WDT cascade values returning a mask of the bits set. + * + * \return The mask of the cascade values set. + * \return CY_SYS_WDT_CASCADE_NONE - Neither + * \return CY_SYS_WDT_CASCADE_01 - Cascade 01 + * \return CY_SYS_WDT_CASCADE_12 - Cascade 12 + * + *******************************************************************************/ + uint32 CySysWdtGetCascade(void) + { + return (CY_SYS_WDT_CONFIG_REG & (CY_SYS_WDT_CASCADE_01 | CY_SYS_WDT_CASCADE_12)); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetMatch + ****************************************************************************//** + * + * \brief Configures the WDT counter match comparison value. + * + * \param counterNum + * Valid range [0-1]. The number of the WDT counter. The match values are not + * supported by counter 2. + * + * \param match + * Valid range [0-65535]. The value to be used to match against the counter. + * + *******************************************************************************/ + void CySysWdtSetMatch(uint32 counterNum, uint32 match) + { + uint32 regValue; + + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + /* Wait for previous changes to come into effect */ + CyDelayUs(CY_SYS_WDT_3LFCLK_DELAY_US); + + regValue = CY_SYS_WDT_MATCH_REG; + regValue &= (uint32)~((uint32)(CY_SYS_WDT_LOWER_16BITS_MASK << (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT))); + CY_SYS_WDT_MATCH_REG = (regValue | (match << (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT))); + + /* Make sure match synchronization has started */ + CyDelayUs(CY_SYS_WDT_1LFCLK_DELAY_US); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetToggleBit + ****************************************************************************//** + * \brief + * Configures which bit in WDT counter 2 to monitor for a toggle. + * + * When that bit toggles, an interrupt is generated if the mode for counter 2 has + * enabled interrupts. + * + * \param bits Valid range [0-31]. Counter 2 bit to monitor for a toggle. + * + * \details + * WDT Counter 2 should be disabled. Otherwise this function call has no + * effect. + * + * If the specified counter is enabled, call the CySysWdtDisable() function with + * the corresponding parameter to disable the specified counter and wait for it to + * stop. This may take up to 3 LFCLK cycles. + * + *******************************************************************************/ + void CySysWdtSetToggleBit(uint32 bits) + { + uint32 configRegValue; + + if (0u == CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + configRegValue = CY_SYS_WDT_CONFIG_REG; + configRegValue &= (uint32)(~((uint32)(CY_SYS_WDT_CONFIG_BITS2_MASK << CY_SYS_WDT_CONFIG_BITS2_POS))); + configRegValue |= ((bits & CY_SYS_WDT_CONFIG_BITS2_MASK) << CY_SYS_WDT_CONFIG_BITS2_POS); + CY_SYS_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysWdtGetToggleBit + ****************************************************************************//** + * \brief + * Reads which bit in WDT counter 2 is monitored for a toggle. + * + * \return The bit that is monitored (range of 0 to 31) + * + *******************************************************************************/ + uint32 CySysWdtGetToggleBit(void) + { + return ((CY_SYS_WDT_CONFIG_REG >> CY_SYS_WDT_CONFIG_BITS2_POS) & CY_SYS_WDT_CONFIG_BITS2_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetMatch + ****************************************************************************//** + * + * \brief Reads the WDT counter match comparison value. + * + * \param counterNum Valid range [0-1]. The number of the WDT counter. The match + * values are not supported by counter 2. + * + * \return A 16-bit match value. + * + *******************************************************************************/ + uint32 CySysWdtGetMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_WDT_COUNTER0) || + (counterNum == CY_SYS_WDT_COUNTER1)); + + return ((uint32)(CY_SYS_WDT_MATCH_REG >> + (counterNum * CY_SYS_WDT_CNT_MATCH_SHIFT)) & CY_SYS_WDT_LOWER_16BITS_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetCount + ****************************************************************************//** + * + * \brief Reads the current WDT counter value. + * + * \param counterNum: Valid range [0-2]. The number of the WDT counter. + * + * \return A live counter value. Counter 0 and Counter 1 are 16 bit counters + * and counter 2 is a 32 bit counter. + * + *******************************************************************************/ + uint32 CySysWdtGetCount(uint32 counterNum) + { + uint32 regValue = 0u; + + switch(counterNum) + { + /* WDT Counter 0 */ + case 0u: + regValue = CY_SYS_WDT_CTRLOW_REG & CY_SYS_WDT_LOWER_16BITS_MASK; + break; + + /* WDT Counter 1 */ + case 1u: + regValue = (CY_SYS_WDT_CTRLOW_REG >> CY_SYS_WDT_CNT_MATCH_SHIFT) & CY_SYS_WDT_LOWER_16BITS_MASK; + break; + + /* WDT Counter 2 */ + case 2u: + regValue = CY_SYS_WDT_CTRHIGH_REG; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + return (regValue); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetInterruptSource + ****************************************************************************//** + * \brief + * Reads a mask containing all the WDT counters interrupts that are currently + * set by the hardware, if a corresponding mode is selected. + * + * \return The mask of interrupts set + * \return CY_SYS_WDT_COUNTER0_INT - Counter 0 + * \return CY_SYS_WDT_COUNTER1_INT - Counter 1 + * \return CY_SYS_WDT_COUNTER2_INT - Counter 2 + * + *******************************************************************************/ + uint32 CySysWdtGetInterruptSource(void) + { + return (CY_SYS_WDT_CONTROL_REG & (CY_SYS_WDT_COUNTER0_INT | CY_SYS_WDT_COUNTER1_INT | CY_SYS_WDT_COUNTER2_INT)); + } + + + /******************************************************************************* + * Function Name: CySysWdtClearInterrupt + ****************************************************************************//** + * \brief + * Clears all the WDT counter interrupts set in the mask. + * + * Calling this function also prevents from Reset when the counter mode is set + * to generate 3 interrupts and then the device resets. + * + * All the WDT interrupts are to be cleared by the firmware, otherwise + * interrupts are generated continuously. + * + * \param counterMask + * CY_SYS_WDT_COUNTER0_INT - Clears counter 0 interrupts
+ * CY_SYS_WDT_COUNTER1_INT - Clears counter 1 interrupts
+ * CY_SYS_WDT_COUNTER2_INT - Clears counter 2 interrupts + * + * \details + * This function temporary removes the watchdog lock, if it was set, and + * restores the lock state after cleaning the WDT interrupts that are set in + * a mask. + * + *******************************************************************************/ + void CySysWdtClearInterrupt(uint32 counterMask) + { + uint8 interruptState; + uint32 wdtLockState; + + interruptState = CyEnterCriticalSection(); + + if (0u != CySysWdtLocked()) + { + wdtLockState = 1u; + CySysWdtUnlock(); + } + else + { + wdtLockState = 0u; + } + + /* Set new WDT control register value */ + counterMask &= (CY_SYS_WDT_COUNTER0_INT | + CY_SYS_WDT_COUNTER1_INT | + CY_SYS_WDT_COUNTER2_INT); + + CY_SYS_WDT_CONTROL_REG = counterMask | (CY_SYS_WDT_CONTROL_REG & ~(CY_SYS_WDT_COUNTER0_INT | + CY_SYS_WDT_COUNTER1_INT | + CY_SYS_WDT_COUNTER2_INT)); + + /* Read the CY_SYS_WDT_CONTROL_REG to clear the interrupt request. + * Cypress ID #207093, #206231 + */ + (void)CY_SYS_WDT_CONTROL_REG; + + if (1u == wdtLockState) + { + CySysWdtLock(); + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysWdtResetCounters + ****************************************************************************//** + * \brief + * Resets all the WDT counters set in the mask. + * + * \param countersMask + * CY_SYS_WDT_COUNTER0_RESET - Reset counter 0
+ * CY_SYS_WDT_COUNTER1_RESET - Reset counter 1
+ * CY_SYS_WDT_COUNTER2_RESET - Reset counter 2 + * + * \details + * This function does not reset counter values if the Watchdog is locked. + * This function waits while corresponding counters will be reset. This may + * take up to 3 LFCLK cycles. + * The LFCLK source must be enabled. Otherwise, the function will never exit. + * + *******************************************************************************/ + void CySysWdtResetCounters(uint32 countersMask) + { + /* Set new WDT reset value */ + CY_SYS_WDT_CONTROL_REG |= (countersMask & CY_SYS_WDT_COUNTERS_RESET); + + while (0uL != (CY_SYS_WDT_CONTROL_REG & CY_SYS_WDT_COUNTERS_RESET)) + { + /* Wait for reset to come into effect */ + } + } + + + /******************************************************************************* + * Function Name: CySysWdtSetInterruptCallback + ****************************************************************************//** + * \brief + * Sets the ISR callback function for the particular WDT counter. + * These functions are called on the WDT interrupt. + * + * \param counterNum The number of the WDT counter. + * \param function The pointer to the callback function. + * + * \return The pointer to the previous callback function. + * \return NULL is returned if the specified address is not set. + * + *******************************************************************************/ + cyWdtCallback CySysWdtSetInterruptCallback(uint32 counterNum, cyWdtCallback function) + { + cyWdtCallback prevCallback = (void *)0; + + if(counterNum < CY_WDT_NUM_OF_WDT) + { + prevCallback = cySysWdtCallback[counterNum]; + cySysWdtCallback[counterNum] = function; + } + else + { + CYASSERT(0u != 0u); + } + + return((cyWdtCallback)prevCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetInterruptCallback + ****************************************************************************//** + * \brief + * Gets the ISR callback function for the particular WDT counter. + * + * \param counterNum The number of the WDT counter. + * + * \return The pointer to the callback function registered for a particular WDT by + * a particular address that are passed through arguments. + * + *******************************************************************************/ + cyWdtCallback CySysWdtGetInterruptCallback(uint32 counterNum) + { + cyWdtCallback retCallback = (void *)0; + + if(counterNum < CY_WDT_NUM_OF_WDT) + { + retCallback = (cyWdtCallback)cySysWdtCallback[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + + return(retCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtEnableCounterIsr + ****************************************************************************//** + * \brief + * Enables the ISR callback servicing for the particular WDT counter + * + * \param counterNum Valid range [0-2]. The number of the WDT counter. + * + * Value corresponds to appropriate WDT counter. For example value 1 + * corresponds to second WDT counter. + * + *******************************************************************************/ + void CySysWdtEnableCounterIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_WDT_COUNTER2) + { + disableServicedIsr &= ~counterIntMaskTbl[counterNum]; + wdtIsrMask |= counterIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysWdtDisableCounterIsr + ****************************************************************************//** + * \brief + * Disables the ISR callback servicing for the particular WDT counter + * + * \param counterNum Valid range [0-2]. The number of the WDT counter. + * + *******************************************************************************/ + void CySysWdtDisableCounterIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_WDT_COUNTER2) + { + wdtIsrMask &= ~counterIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysWdtIsr + ****************************************************************************//** + * \brief + * This is the handler of the WDT interrupt in CPU NVIC. + * + * The handler checks which WDT triggered in the interrupt and calls the + * respective callback functions configured by the user by using + * CySysWdtSetIsrCallback() API. + * + * The order of the callback execution is incremental. Callback-0 is + * run as the first one and callback-2 is called as the last one. + * + * \details + * This function clears the WDT interrupt every time when it is called. + * Reset after the 3rd interrupt does not happen if this function is registered + * as the interrupt handler even if the "Watchdog with Interrupt" mode is + * selected on the "Low Frequency Clocks" tab. + * + *******************************************************************************/ + void CySysWdtIsr(void) + { + if(0u != (CY_SYS_WDT_COUNTER0_INT & CY_SYS_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_WDT_COUNTER0_INT & wdtIsrMask)) + { + wdtIsrMask &= ~(disableServicedIsr & CY_SYS_WDT_COUNTER0_INT); + disableServicedIsr &= ~CY_SYS_WDT_COUNTER0_INT; + if(cySysWdtCallback[CY_SYS_WDT_COUNTER0] != (void *) 0) + { + (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER0])(); + } + } + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + } + + if(0u != (CY_SYS_WDT_COUNTER1_INT & CY_SYS_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_WDT_COUNTER1_INT & wdtIsrMask)) + { + wdtIsrMask &= ~(disableServicedIsr & CY_SYS_WDT_COUNTER1_INT); + disableServicedIsr &= ~CY_SYS_WDT_COUNTER1_INT; + if(cySysWdtCallback[CY_SYS_WDT_COUNTER1] != (void *) 0) + { + (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER1])(); + } + } + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); + } + + if(0u != (CY_SYS_WDT_COUNTER2_INT & CY_SYS_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_WDT_COUNTER2_INT & wdtIsrMask)) + { + if(cySysWdtCallback[CY_SYS_WDT_COUNTER2] != (void *) 0) + { + (void)(cySysWdtCallback[CY_SYS_WDT_COUNTER2])(); + } + } + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER2_INT); + } + } + + + /******************************************************************************* + * Function Name: CySysWatchdogFeed + ****************************************************************************//** + * \brief + * Feeds the corresponded Watchdog Counter before it causes the device reset. + * + * Supported only for first WDT0 and second WDT1 counters in the "Watchdog" or + * "Watchdog w/ Interrupts" modes. + * + * \param counterNum + * CY_SYS_WDT_COUNTER0 - Feeds the Counter 0
+ * CY_SYS_WDT_COUNTER1 - Feeds the Counter 1 + * + * Value of counterNum corresponds to appropriate counter. For example value 1 + * corresponds to second WDT1 Counter. + * + * \details + * Clears the WDT counter in the "Watchdog" mode or clears the WDT interrupt in + * "Watchdog w/ Interrupts" mode. Does nothing in other modes. + * + *******************************************************************************/ + void CySysWatchdogFeed(uint32 counterNum) + { + if(counterNum == CY_SYS_WDT_COUNTER0) + { + if(CY_SYS_WDT_MODE_INT_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + } + else if(CY_SYS_WDT_MODE_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtResetCounters(CY_SYS_WDT_COUNTER0_RESET); + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT); + } + else + { + /* Do nothing. */ + } + } + else if(counterNum == CY_SYS_WDT_COUNTER1) + { + if(CY_SYS_WDT_MODE_INT_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); + } + else if(CY_SYS_WDT_MODE_RESET == CySysWdtGetMode(counterNum)) + { + CySysWdtResetCounters(CY_SYS_WDT_COUNTER1_RESET); + CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT); + } + else + { + /* Do nothing. */ + } + } + else + { + /* Do nothing. */ + } + } + + + /******************************************************************************* + * Function Name: CySysClkLfclkPosedgeCatch + ****************************************************************************//** + * \internal + * Returns once the LFCLK positive edge occurred. + * + * CySysClkLfclkPosedgeRestore() should be called after this function + * to restore the WDT configuration. + * + * A pair of the CySysClkLfclkPosedgeCatch() and CySysClkLfclkPosedgeRestore() + * functions is expected to be called inside a critical section. + * + * To ensure that the WDT counter value is read until it changes, the enabled + * WDT counter is used. If no counter is enabled, counter 0 is enabled. + * And after the LFCLK source is switched, the counter 0 configuration + * is restored. + * + * Not applicable for the PSoC 4000 / PSoC 4000S / PSoC 4100S / PSoC Analog + * Coprocessor devices. + * + * \details + * This function has no effect if WDT is locked (CySysWdtLock() is + * called). Call CySysWdtUnlock() to unlock WDT. + * \endinternal + *******************************************************************************/ + static void CySysClkLfclkPosedgeCatch(void) + { + uint32 firstCount; + static uint32 lfclkPosedgeEnabledWdtCounter = 0u; + + if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER0)) + { + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER0; + } + else if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER1)) + { + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER1; + } + else if (0u != CySysWdtGetEnabledStatus(CY_SYS_WDT_COUNTER2)) + { + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER2; + } + else /* All WDT counters are disabled */ + { + /* Configure WDT counter # 0 */ + lfclkPosedgeWdtCounter0Enabled = 1u; + lfclkPosedgeEnabledWdtCounter = CY_SYS_WDT_COUNTER0; + + lfclkPosedgeWdtCounter0Mode = CySysWdtGetMode(CY_SYS_WDT_COUNTER0); + CySysWdtSetMode(CY_SYS_WDT_COUNTER0, CY_SYS_WDT_MODE_NONE); + CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK); + } + + firstCount = CySysWdtGetCount(lfclkPosedgeEnabledWdtCounter); + while (CySysWdtGetCount(lfclkPosedgeEnabledWdtCounter) == firstCount) + { + /* Wait for counter to increment */ + } + } + + + /******************************************************************************* + * Function Name: CySysClkLfclkPosedgeRestore + ****************************************************************************//** + * \internal + * Restores the WDT configuration after a CySysClkLfclkPosedgeCatch() call. + * + * A pair of the CySysClkLfclkPosedgeCatch() and CySysClkLfclkPosedgeRestore() + * functions is expected to be called inside a critical section. + * + * Not applicable for the PSoC 4000/PSoC 4000S / PSoC 4100S / PSoC Analog + * Coprocessor devices. + * + * \details + * This function has no effect if WDT is locked (CySysWdtLock() is + * called). Call CySysWdtUnlock() to unlock WDT. + * + * \endinternal + *******************************************************************************/ + static void CySysClkLfclkPosedgeRestore(void) + { + if (lfclkPosedgeWdtCounter0Enabled != 0u) + { + /* Restore counter # 0 configuration and force its shutdown */ + CY_SYS_WDT_CONTROL_REG &= (uint32)(~CY_SYS_WDT_COUNTER0_MASK); + CySysWdtSetMode(CY_SYS_WDT_COUNTER0, lfclkPosedgeWdtCounter0Mode); + lfclkPosedgeWdtCounter0Enabled = 0u; + } + } + +#else + + /******************************************************************************* + * Function Name: CySysWdtGetEnabledStatus + ****************************************************************************//** + * + * \brief Reads the enabled status of the WDT counter. + * + * \return The status of the WDT counter: + * \return 0 - Counter is disabled + * \return 1 - Counter is enabled + * + *******************************************************************************/ + uint32 CySysWdtGetEnabledStatus(void) + { + return ((CY_SYS_WDT_DISABLE_KEY_REG == CY_SYS_WDT_KEY) ? (uint32) 0u : (uint32) 1u); + } + + + /******************************************************************************* + * Function Name: CySysWdtEnable + ****************************************************************************//** + * + * \brief + * Enables watchdog timer reset generation. + * + * CySysWdtClearInterrupt() feeds the watchdog. Two unserviced interrupts lead + * to a system reset (i.e. at the third match). + * + * ILO is enabled by the hardware once WDT is started. + * + *******************************************************************************/ + void CySysWdtEnable(void) + { + CY_SYS_WDT_DISABLE_KEY_REG = 0u; + } + + + /******************************************************************************* + * Function Name: CySysWdtDisable + ****************************************************************************//** + * + * \brief Disables the WDT reset generation. + * + * This function unlocks the ENABLE bit in the CLK_ILO_CONFIG registers and + * enables the user to disable ILO. + * + *******************************************************************************/ + void CySysWdtDisable(void) + { + CY_SYS_WDT_DISABLE_KEY_REG = CY_SYS_WDT_KEY; + } + + + /******************************************************************************* + * Function Name: CySysWdtSetMatch + ****************************************************************************//** + * + * \brief Configures the WDT counter match comparison value. + * + * \param match Valid range [0-65535]. The value to be used to match against + * the counter. + * + *******************************************************************************/ + void CySysWdtSetMatch(uint32 match) + { + match &= CY_SYS_WDT_MATCH_MASK; + CY_SYS_WDT_MATCH_REG = (CY_SYS_WDT_MATCH_REG & (uint32)(~CY_SYS_WDT_MATCH_MASK)) | match; + } + + + /******************************************************************************* + * Function Name: CySysWdtGetMatch + ****************************************************************************//** + * + * \brief Reads the WDT counter match comparison value. + * + * \return The counter match value. + * + *******************************************************************************/ + uint32 CySysWdtGetMatch(void) + { + return (CY_SYS_WDT_MATCH_REG & CY_SYS_WDT_MATCH_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetCount + ****************************************************************************//** + * + * \brief Reads the current WDT counter value. + * + * \return A live counter value. + * + *******************************************************************************/ + uint32 CySysWdtGetCount(void) + { + return ((uint32)CY_SYS_WDT_COUNTER_REG); + } + + + /******************************************************************************* + * Function Name: CySysWdtSetIgnoreBits + ****************************************************************************//** + * + * \brief + * Configures the number of the MSB bits of the watchdog timer that are not + * checked against the match. + * + * \param bitsNum Valid range [0-15]. The number of the MSB bits. + * + * \details The value of bitsNum controls the time-to-reset of the watchdog + * (which happens after 3 successive matches). + * + *******************************************************************************/ + void CySysWdtSetIgnoreBits(uint32 bitsNum) + { + bitsNum = ((uint32)(bitsNum << CY_SYS_WDT_IGNORE_BITS_SHIFT) & CY_SYS_WDT_IGNORE_BITS_MASK); + CY_SYS_WDT_MATCH_REG = (CY_SYS_WDT_MATCH_REG & (uint32)(~CY_SYS_WDT_IGNORE_BITS_MASK)) | bitsNum; + } + + + /******************************************************************************* + * Function Name: CySysWdtGetIgnoreBits + ****************************************************************************//** + * + * \brief + * Reads the number of the MSB bits of the watchdog timer that are not + * checked against the match. + * + * \return The number of the MSB bits. + * + *******************************************************************************/ + uint32 CySysWdtGetIgnoreBits(void) + { + return((uint32)((CY_SYS_WDT_MATCH_REG & CY_SYS_WDT_IGNORE_BITS_MASK) >> CY_SYS_WDT_IGNORE_BITS_SHIFT)); + } + + + /******************************************************************************* + * Function Name: CySysWdtClearInterrupt + ****************************************************************************//** + * + * \brief + * Feeds the watchdog. + * Cleans the WDT match flag which is set every time the WDT counter reaches a + * WDT match value. Two unserviced interrupts lead to a system reset + * (i.e. at the third match). + * + *******************************************************************************/ + void CySysWdtClearInterrupt(void) + { + CY_SYS_SRSS_INTR_REG |= CY_SYS_WDT_LOWER_BIT_MASK; + } + + + /******************************************************************************* + * Function Name: CySysWdtMaskInterrupt + ****************************************************************************//** + * + * \brief + * After masking interrupts from WDT, they are not passed to CPU. + * This function does not disable WDT reset generation. + * + *******************************************************************************/ + void CySysWdtMaskInterrupt(void) + { + CY_SYS_SRSS_INTR_MASK_REG &= (uint32)(~ (uint32)CY_SYS_WDT_LOWER_BIT_MASK); + } + + + /******************************************************************************* + * Function Name: CySysWdtUnmaskInterrupt + ****************************************************************************//** + * + * \brief + * After unmasking interrupts from WDT, they are passed to CPU. + * This function does not impact the reset generation. + * + *******************************************************************************/ + void CySysWdtUnmaskInterrupt(void) + { + CY_SYS_SRSS_INTR_MASK_REG |= CY_SYS_WDT_LOWER_BIT_MASK; + } + + + /******************************************************************************* + * Function Name: CySysWdtSetIsrCallback + ****************************************************************************//** + * + * \brief + * Sets the ISR callback function for the WDT counter + * + * \param function The pointer to the callback function. + * + * \return The pointer to a previous callback function. + * + *******************************************************************************/ + cyWdtCallback CySysWdtSetInterruptCallback(cyWdtCallback function) + { + cyWdtCallback prevCallback = (void *)0; + + prevCallback = cySysWdtCallback; + cySysWdtCallback = function; + + return(prevCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtGetIsrCallback + ****************************************************************************//** + * + * \brief + * Gets the ISR callback function for the WDT counter + * + * \return The pointer to the callback function registered for WDT. + * + *******************************************************************************/ + cyWdtCallback CySysWdtGetInterruptCallback(void) + { + return(cySysWdtCallback); + } + + + /******************************************************************************* + * Function Name: CySysWdtIsr + ****************************************************************************//** + * + * \brief + * This is the handler of the WDT interrupt in CPU NVIC. + * + * The handler calls the respective callback functions configured by the user + * by using CySysWdtSetIsrCallback() API. + * + * + * \details + * This function clears the WDT interrupt every time when it is called. + * Reset after the 3rd interrupt does not happen if this function is registered + * as the interrupt handler even if the "Watchdog with Interrupt" mode is + * selected on the "Low Frequency Clocks" tab. + * + *******************************************************************************/ + void CySysWdtIsr(void) + { + if(cySysWdtCallback != (void *) 0) + { + (void)(cySysWdtCallback)(); + } + + CySysWdtClearInterrupt(); + } + +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + +/******************************************************************************* +* Function Name: CySysClkGetTimerSource +******************************************************************************** +* +* \brief Gets the clock source for the DeepSleep Timers. +* +* The function is applicable only for PSoC 4100S / PSoC Analog Coprocessor. +* +* \return The DeepSleep Timer source +* CY_SYS_CLK_TIMER_SRC_ILO Internal Low Frequency (32 kHz) Oscillator (ILO) +* CY_SYS_CLK_TIMER_SRC_WCO Low Frequency Watch Crystal Oscillator (WCO) +* +*******************************************************************************/ + static uint32 CySysClkGetTimerSource(void) + { + uint32 timerSource; + timerSource = CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK; + return (timerSource); + } + + +/******************************************************************************* +* Function Name: CySysClkSetTimerSource +****************************************************************************//** +* +* \brief Sets the clock source for the DeepSleep Timers. +* +* The function is applicable only for PSoC 4100S / PSoC Analog Coprocessor +* devices. +* +* \param source +* CY_SYS_CLK_TIMER_SRC_ILO - Internal Low Frequency (32 kHz) Oscillator +* (ILO).
+* CY_SYS_CLK_TIMER_SRC_WCO - Low Frequency Watch Crystal Oscillator +* (WCO). +* +* \details Both the current source and the new source must be running and stable +* before calling this function. +* +* \warning DeepSleep Timer reset is required if Timer source was switched while +* DeepSleep Timers were running. Call CySysTimerResetCounters() API after +* Timer source switching. +* It is highly recommended to disable DeepSleep Timers before Timer source +* switching. Changing the Timer source may change the functionality that uses +* this Timers as clock source. +*******************************************************************************/ + void CySysClkSetTimerSource(uint32 source) + { + uint8 interruptState; + + if (CySysClkGetTimerSource() != source) + { + + /* Reset both _EN bits in WCO_WDT_CLKEN register */ + CY_SYS_WCO_WDT_CLKEN_REG &= ~CY_SYS_WCO_WDT_CLKEN_RESET_MASK; + + /* Wait 4 new clock source-cycles for change to come into effect */ + CyDelayUs(CY_SYS_4TIMER_DELAY_US); + + interruptState = CyEnterCriticalSection(); + CY_SYS_WCO_WDT_CONFIG_REG = (CY_SYS_WCO_WDT_CONFIG_REG & (uint32)(~CY_SYS_CLK_TIMER_SEL_MASK)) | + (source & CY_SYS_CLK_TIMER_SEL_MASK); + CyExitCriticalSection(interruptState); + } + + CY_SYS_WCO_WDT_CLKEN_REG = (CY_SYS_WCO_WDT_CLKEN_REG & (uint32)(~CY_SYS_WCO_WDT_CLKEN_RESET_MASK)) | + CY_SYS_SET_CURRENT_TIMER_SOURCE_BIT; + } + + + /******************************************************************************* + * Function Name: CySysTimerGetEnabledStatus + ****************************************************************************//** + * + * \brief Reads the enabled status of one of the three DeepSleep Timer + * counters. + * + * \param counterNum: Valid range [0-2]. The number of the DeepSleep Timer + * counter. + * + * \return The status of the Timers counter: + * \return 0 - If the Counter is disabled. + * \return 1 - If the Counter is enabled. + * + * \details + * This function returns an actual DeepSleep Timer counter status from the + * status register. It may take up to 3 LFCLK cycles for the Timer status + * register to contain actual data after the Timer counter is enabled. + * + *******************************************************************************/ + uint32 CySysTimerGetEnabledStatus(uint32 counterNum) + { + CYASSERT(counterNum < CY_SYS_TIMER_COUNTERS_MAX); + return ((CY_SYS_WCO_WDT_CONTROL_REG >> ((CY_SYS_TIMER_CNT_SHIFT * counterNum) + + CY_SYS_TIMER_CNT_STTS_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetMode + ****************************************************************************//** + * + * \brief Writes the mode of one of the three DeepSleep Timer counters. + * + * \param counterNum: Valid range [0-2]. The number of the DeepSleep Timer + * counter. + * + * \param mode + * CY_SYS_TIMER_MODE_NONE - Free running.
+ * CY_SYS_TIMER_MODE_INT - The interrupt generated on match for counter 0 + * and 1, and on bit toggle for counter 2. + * + * \details + * DeepSleep Timer counter counterNum should be disabled to set a mode. + * Otherwise, this function call has no effect. If the specified counter is + * enabled, call the CySysTimerDisable() function with the corresponding + * parameter to disable the specified counter and wait for it to stop. + * + *******************************************************************************/ + void CySysTimerSetMode(uint32 counterNum, uint32 mode) + { + uint32 configRegValue; + + CYASSERT(counterNum < CY_SYS_TIMER_COUNTERS_MAX); + + CYASSERT(mode <= CY_SYS_TIMER_MODE_MASK); + + if(0u == CySysTimerGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG & + (uint32)~((uint32)(CY_SYS_TIMER_MODE_MASK << (counterNum * CY_SYS_TIMER_CNT_SHIFT))); + configRegValue |= (uint32)((mode & CY_SYS_TIMER_MODE_MASK) << (counterNum * CY_SYS_TIMER_CNT_SHIFT)); + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetMode + ****************************************************************************//** + * + * \brief Reads the mode of one of the three DeepSleep Timer counters. + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + * \return The mode of the counter. The same enumerated values as the mode + * parameter used in CySysTimerSetMode(). + * + *******************************************************************************/ + uint32 CySysTimerGetMode(uint32 counterNum) + { + return ((CY_SYS_WCO_WDT_CONFIG_REG >> (counterNum * CY_SYS_TIMER_CNT_SHIFT)) & CY_SYS_TIMER_MODE_MASK); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetClearOnMatch + ****************************************************************************//** + * + * \brief Configures the DeepSleep Timer counter "clear on match" setting. + * + * If configured to "clear on match", the counter counts from 0 to MatchValue + * giving it a period of (MatchValue + 1). + * + * \param counterNum + * Valid range [0-1]. The number of the Timer counter. The match values are not + * supported by counter 2. + * \param enable 0 to disable appropriate counter
+ * 1 to enable appropriate counter + * + * \details + * Timer counter counterNum should be disabled. Otherwise this function call + * has no effect. If the specified counter is enabled, call the CySysTimerDisable() + * function with the corresponding parameter to disable the specified counter and + * wait for it to stop. This may take up to three Timer source-cycles. + * + *******************************************************************************/ + void CySysTimerSetClearOnMatch(uint32 counterNum, uint32 enable) + { + uint32 configRegValue; + + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + if(0u == CySysTimerGetEnabledStatus(counterNum)) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG & (uint32)~((uint32)((uint32)1u << + ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT))); + + configRegValue + |= (uint32)(enable << ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT)); + + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetClearOnMatch + ****************************************************************************//** + * + * \brief Reads the "clear on match" setting for the specified DeepSleep Timer + * counter. + * + * \param counterNum Valid range [0-1]. The number of the Timer counter. The + * match values are not supported by counter 2. + * + * \return The "clear on match" status:
1 if enabled
0 if disabled + * + *******************************************************************************/ + uint32 CySysTimerGetClearOnMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + return (uint32)((CY_SYS_WCO_WDT_CONFIG_REG >> + ((counterNum * CY_SYS_TIMER_CNT_SHIFT) + CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT)) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysTimerEnable + ****************************************************************************//** + * + * \brief Enables the specified DeepSleep Timer counters. All the counters + * specified in the mask are enabled. + * + * \param counterMask CY_SYS_TIMER0_MASK - The mask for counter 0 to enable.
+ * CY_SYS_TIMER1_MASK - The mask for counter 1 to enable.
+ * CY_SYS_TIMER2_MASK - The mask for counter 2 to enable. + * + * \details + * Enabling or disabling Timer requires 3 Timer source-cycles to come into effect. + * Therefore, the Timer enable state must not be changed more than once in + * that period. + * + * After Timer is enabled, it is illegal to write Timer configuration + * (WCO_WDT_CONFIG) and control (WCO_WDT_CONTROL) registers. This means that all + * Timer functions that contain 'write' in the name (with the exception of + * CySysTimerSetMatch() function) are illegal to call once Timer enabled. + * + * Timer current source must be running and stable before calling this + * function. + * + *******************************************************************************/ + void CySysTimerEnable(uint32 counterMask) + { + CY_SYS_WCO_WDT_CONTROL_REG |= counterMask; + + if(0u != (counterMask & CY_SYS_TIMER0_MASK)) + { + while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER1_MASK)) + { + while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER2_MASK)) + { + while (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) + { + /* Wait for changes to come into effect */ + } + } + } + + + /******************************************************************************* + * Function Name: CySysTimerDisable + ****************************************************************************//** + * + * \brief Disables the specified DeepSleep Timer counters. + * + * All the counters specified in the mask are disabled. The function waits for + * the changes to come into effect. + * + * \param counterMask + * CY_SYS_TIMER0_MASK - The mask for Counter 0 to disable.
+ * CY_SYS_TIMER1_MASK - The mask for Counter 1 to disable.
+ * CY_SYS_TIMER2_MASK - The mask for Counter 2 to disable. + * + *******************************************************************************/ + void CySysTimerDisable(uint32 counterMask) + { + + CY_SYS_WCO_WDT_CONTROL_REG &= ~counterMask; + + if(0u != (counterMask & CY_SYS_TIMER0_MASK)) + { + while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER0)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER1_MASK)) + { + while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER1)) + { + /* Wait for changes to come into effect */ + } + } + + if(0u != (counterMask & CY_SYS_TIMER2_MASK)) + { + while (0u != CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) + { + /* Wait for changes to come into effect */ + } + } + + } + + + /******************************************************************************* + * Function Name: CySysTimerSetCascade + ****************************************************************************//** + * + * \brief + * Writes the two DeepSleep Timers cascade values based on the combination of + * mask values specified. + * + * \param cascadeMask The mask value used to set or clear the cascade values: + * CY_SYS_TIMER_CASCADE_NONE - Neither
+ * CY_SYS_TIMER_CASCADE_01 - Cascade 01
+ * CY_SYS_TIMER_CASCADE_12 - Cascade 12 + * + * If only one cascade mask is specified, the second cascade is disabled. + * To set both cascade modes, two defines should be ORed: + * (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12). + * \note If CySysTimerSetCascade() was called with ORed defines it is necessary + * to call CySysTimeSetClearOnMatch(1,1). It is needed to make sure that + * Counter 2 will be updated in the expected way. + * + * Timer counters that are part of the specified cascade should be disabled. + * Otherwise this function call has no effect. If the specified + * counter is enabled, call CySysTimerDisable() function with the corresponding + * parameter to disable the specified counter and wait for it to stop. This may + * take up to 3 Timers source-cycles. + * + *******************************************************************************/ + void CySysTimerSetCascade(uint32 cascadeMask) + { + uint32 configRegValue; + uint32 countersEnableStatus; + + countersEnableStatus = CySysTimerGetEnabledStatus(CY_SYS_TIMER0) | + CySysTimerGetEnabledStatus(CY_SYS_TIMER1) | + CySysTimerGetEnabledStatus(CY_SYS_TIMER2); + + if (0u == countersEnableStatus) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG; + configRegValue &= ((uint32)(~(CY_SYS_TIMER_CASCADE_01|CY_SYS_TIMER_CASCADE_12))); + configRegValue |= cascadeMask; + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetCascade + ****************************************************************************//** + * + * \brief Reads the two DeepSleep Timer cascade values returning a mask of the + * bits set. + * + * \return The mask of the cascade values set. + * \return CY_SYS_TIMER_CASCADE_NONE - Neither + * \return CY_SYS_TIMER_CASCADE_01 - Cascade 01 + * \return CY_SYS_TIMER_CASCADE_12 - Cascade 12 + * + *******************************************************************************/ + uint32 CySysTimerGetCascade(void) + { + return (CY_SYS_WCO_WDT_CONFIG_REG & (CY_SYS_TIMER_CASCADE_01 | CY_SYS_TIMER_CASCADE_12)); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetMatch + ****************************************************************************//** + * + * \brief Configures the Timer counter match comparison value. + * + * \param counterNum Valid range [0-1]. The number of the Timer counter. The + * match values are not supported by counter 2. + * + * \param match Valid range [0-65535]. The value to be used to match against + * the counter. + * + *******************************************************************************/ + void CySysTimerSetMatch(uint32 counterNum, uint32 match) + { + uint32 regValue; + + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + /* Wait for previous changes to come into effect */ + CyDelayUs(CY_SYS_3TIMER_DELAY_US); + + regValue = CY_SYS_WCO_WDT_MATCH_REG; + regValue &= (uint32)~((uint32)(CY_SYS_TIMER_LOWER_16BITS_MASK << (counterNum * CY_SYS_TIMER_CNT_MATCH_SHIFT))); + CY_SYS_WCO_WDT_MATCH_REG = (regValue | (match << (counterNum * CY_SYS_TIMER_CNT_MATCH_SHIFT))); + + /* Make sure match synchronization has started */ + CyDelayUs(CY_SYS_1TIMER_DELAY_US); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetToggleBit + ****************************************************************************//** + * + * \brief Configures which bit in Timer counter 2 to monitor for a toggle. + * + * When that bit toggles, an interrupt is generated if mode for counter 2 has + * enabled interrupts. + * + * \param bits Valid range [0-31]. Counter 2 bit to monitor for a toggle. + * + * \details Timer counter 2 should be disabled. Otherwise this function call has + * no effect. + * + * If the specified counter is enabled, call the CySysTimerDisable() function with + * the corresponding parameter to disable the specified counter and wait for it to + * stop. This may take up to three Timer source-cycles. + * + *******************************************************************************/ + void CySysTimerSetToggleBit(uint32 bits) + { + uint32 configRegValue; + + if (0u == CySysTimerGetEnabledStatus(CY_SYS_TIMER2)) + { + configRegValue = CY_SYS_WCO_WDT_CONFIG_REG; + configRegValue &= (uint32)(~((uint32)(CY_SYS_TIMER_CONFIG_BITS2_MASK << CY_SYS_TIMER_CONFIG_BITS2_POS))); + configRegValue |= ((bits & CY_SYS_TIMER_CONFIG_BITS2_MASK) << CY_SYS_TIMER_CONFIG_BITS2_POS); + CY_SYS_WCO_WDT_CONFIG_REG = configRegValue; + } + } + + + /******************************************************************************* + * Function Name: CySysTimerGetToggleBit + ****************************************************************************//** + * + * \brief Reads which bit in Timer counter 2 is monitored for a toggle. + * + * \return The bit that is monitored (range of 0 to 31) + * + *******************************************************************************/ + uint32 CySysTimerGetToggleBit(void) + { + return ((CY_SYS_WCO_WDT_CONFIG_REG >> CY_SYS_TIMER_CONFIG_BITS2_POS) & CY_SYS_TIMER_CONFIG_BITS2_MASK); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetMatch + ****************************************************************************//** + * + * \brief Reads the Timer counter match comparison value. + * + * \param counterNum Valid range [0-1]. The number of the DeepSleep Timer + * counter. The match values are not supported by counter 2. + * + * \return A 16-bit match value. + * + *******************************************************************************/ + uint32 CySysTimerGetMatch(uint32 counterNum) + { + CYASSERT((counterNum == CY_SYS_TIMER0) || + (counterNum == CY_SYS_TIMER1)); + + return ((uint32)(CY_SYS_WCO_WDT_MATCH_REG >> (counterNum * CY_SYS_TIMER_CNT_MATCH_SHIFT)) & + CY_SYS_TIMER_LOWER_16BITS_MASK); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetCount + ****************************************************************************//** + * + * \brief Reads the current DeepSleep Timer counter value. + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + * \return A live counter value. Counter 0 and Counter 1 are 16 bit counters + * and counter 2 is a 32 bit counter. + * + *******************************************************************************/ + uint32 CySysTimerGetCount(uint32 counterNum) + { + uint32 regValue = 0u; + + switch(counterNum) + { + /* Timer Counter 0 */ + case 0u: + regValue = CY_SYS_WCO_WDT_CTRLOW_REG & CY_SYS_TIMER_LOWER_16BITS_MASK; + break; + + /* Timer Counter 1 */ + case 1u: + regValue = (CY_SYS_WCO_WDT_CTRLOW_REG >> CY_SYS_TIMER_CNT_MATCH_SHIFT) & CY_SYS_TIMER_LOWER_16BITS_MASK; + break; + + /* Timer Counter 2 */ + case 2u: + regValue = CY_SYS_WCO_WDT_CTRHIGH_REG; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + return (regValue); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetInterruptSource + ****************************************************************************//** + * + * \brief + * Reads a mask containing all the DeepSleep Timer counters interrupts that are + * currently set by the hardware, if a corresponding mode is selected. + * + * \return The mask of interrupts set + * \return CY_SYS_TIMER0_INT - Set interrupt for Counter 0 + * \return CY_SYS_TIMER1_INT - Set interrupt for Counter 1 + * \return CY_SYS_TIMER2_INT - Set interrupt for Counter 2 + * + *******************************************************************************/ + uint32 CySysTimerGetInterruptSource(void) + { + return (CY_SYS_WCO_WDT_CONTROL_REG & (CY_SYS_TIMER0_INT | CY_SYS_TIMER1_INT | CY_SYS_TIMER2_INT)); + } + + + /******************************************************************************* + * Function Name: CySysTimerClearInterrupt + ****************************************************************************//** + * + * \brief Clears all the DeepSleep Timer counter interrupts set in the mask. + * + * All the Timer interrupts are to be cleared by the firmware, otherwise + * interrupts are generated continuously. + * + * \param counterMask + * CY_SYS_TIMER0_INT - Clear counter 0
+ * CY_SYS_TIMER1_INT - Clear counter 1
+ * CY_SYS_TIMER2_INT - Clear counter 2 + * + *******************************************************************************/ + void CySysTimerClearInterrupt(uint32 counterMask) + { + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + + /* Set new WCO_TIMER control register value */ + counterMask &= (CY_SYS_TIMER0_INT | + CY_SYS_TIMER1_INT | + CY_SYS_TIMER2_INT); + + CY_SYS_WCO_WDT_CONTROL_REG = counterMask | (CY_SYS_WCO_WDT_CONTROL_REG & ~(CY_SYS_TIMER0_INT | + CY_SYS_TIMER1_INT | + CY_SYS_TIMER2_INT)); + + /* Read the CY_SYS_WDT_CONTROL_REG to clear the interrupt request. + * Cypress ID #207093, #206231 + */ + (void)CY_SYS_WCO_WDT_CONTROL_REG; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysTimerSetInterruptCallback + ****************************************************************************//** + * + * \brief + * Sets the ISR callback function for the particular DeepSleep Timer counter. + * + * These functions are called on the Timer interrupt. + * + * \param counterNum The number of the Timer counter. + * \param function The pointer to the callback function. + * + * \return The pointer to the previous callback function. + * \return NULL is returned if the specified address is not set. + * + *******************************************************************************/ + cyTimerCallback CySysTimerSetInterruptCallback(uint32 counterNum, cyTimerCallback function) + { + cyTimerCallback prevCallback = (void *)0; + + if(counterNum < CY_SYS_NUM_OF_TIMERS) + { + prevCallback = cySysTimerCallback[counterNum]; + cySysTimerCallback[counterNum] = function; + } + else + { + CYASSERT(0u != 0u); + } + + return((cyTimerCallback)prevCallback); + } + + + /******************************************************************************* + * Function Name: CySysTimerGetInterruptCallback + ****************************************************************************//** + * + * \brief Gets the ISR callback function for the particular DeepSleep Timer + * counter. + * + * \param counterNum The number of the Timer counter. + * + * \return + * The pointer to the callback function registered for a particular Timer by + * a particular address that are passed through arguments. + * + *******************************************************************************/ + cyTimerCallback CySysTimerGetInterruptCallback(uint32 counterNum) + { + cyTimerCallback retCallback = (void *)0; + + if(counterNum < CY_SYS_NUM_OF_TIMERS) + { + retCallback = (cyTimerCallback)cySysTimerCallback[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + + return(retCallback); + } + + + /******************************************************************************* + * Function Name: CySysTimerEnableIsr + ****************************************************************************//** + * + * \brief Enables the ISR callback servicing for the particular Timer counter + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + * Value corresponds to appropriate Timer counter. For example value 1 + * corresponds to second Timer counter. + * + *******************************************************************************/ + void CySysTimerEnableIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_TIMER2) + { + disableTimerServicedIsr &= ~counterTimerIntMaskTbl[counterNum]; + timerIsrMask |= counterTimerIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysTimerDisableIsr + ****************************************************************************//** + * + * \brief Disables the ISR callback servicing for the particular Timer counter + * + * \param counterNum Valid range [0-2]. The number of the Timer counter. + * + *******************************************************************************/ + void CySysTimerDisableIsr(uint32 counterNum) + { + if(counterNum <= CY_SYS_TIMER2) + { + timerIsrMask &= ~counterTimerIntMaskTbl[counterNum]; + } + else + { + CYASSERT(0u != 0u); + } + } + + + /******************************************************************************* + * Function Name: CySysTimerIsr + ****************************************************************************//** + * + * \brief This is the handler of the DeepSleep Timer interrupt in CPU NVIC. + * + * The handler checks which Timer triggered in the interrupt and calls the + * respective callback functions configured by the user by using + * CySysTimerSetIsrCallback() API. + * + * The order of the callback execution is incremental. Callback-0 is + * run as the first one and callback-2 is called as the last one. + * + * \details This function clears the DeepSleep Timer interrupt every time when + * it is called. + * + *******************************************************************************/ + void CySysTimerIsr(void) + { + if(0u != (CY_SYS_TIMER0_INT & CY_SYS_WCO_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_TIMER0_INT & timerIsrMask)) + { + timerIsrMask &= ~(disableTimerServicedIsr & CY_SYS_TIMER0_INT); + disableTimerServicedIsr &= ~CY_SYS_TIMER0_INT; + if(cySysTimerCallback[CY_SYS_TIMER0] != (void *) 0) + { + (void)(cySysTimerCallback[CY_SYS_TIMER0])(); + } + } + CySysTimerClearInterrupt(CY_SYS_TIMER0_INT); + } + + if(0u != (CY_SYS_TIMER1_INT & CY_SYS_WCO_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_TIMER1_INT & timerIsrMask)) + { + timerIsrMask &= ~(disableTimerServicedIsr & CY_SYS_TIMER1_INT); + disableTimerServicedIsr &= ~CY_SYS_TIMER1_INT; + if(cySysTimerCallback[CY_SYS_TIMER1] != (void *) 0) + { + (void)(cySysTimerCallback[CY_SYS_TIMER1])(); + } + } + CySysTimerClearInterrupt(CY_SYS_TIMER1_INT); + } + + if(0u != (CY_SYS_TIMER2_INT & CY_SYS_WCO_WDT_CONTROL_REG)) + { + if(0u != (CY_SYS_TIMER2_INT & timerIsrMask)) + { + if(cySysTimerCallback[CY_SYS_TIMER2] != (void *) 0) + { + (void)(cySysTimerCallback[CY_SYS_TIMER2])(); + } + } + CySysTimerClearInterrupt(CY_SYS_TIMER2_INT); + } + } + + + /******************************************************************************* + * Function Name: CySysTimerResetCounters + ****************************************************************************//** + * + * \brief Resets all the Timer counters set in the mask. + * + * \param countersMask + * CY_SYS_TIMER0_RESET - Reset the Counter 0
+ * CY_SYS_TIMER1_RESET - Reset the Counter 1
+ * CY_SYS_TIMER2_RESET - Reset the Counter 2 + * + * \details + * This function waits while corresponding counters will be reset. This may + * take up to 3 DeepSleep Timer source-cycles. DeepSleep Timer source must be + * enabled. Otherwise, the function will never exit. + * + *******************************************************************************/ + void CySysTimerResetCounters(uint32 countersMask) + { + /* Set new Timer reset value */ + CY_SYS_WCO_WDT_CONTROL_REG |= (countersMask & CY_SYS_TIMER_RESET); + + while (0uL != (CY_SYS_WCO_WDT_CONTROL_REG & CY_SYS_TIMER_RESET)) + { + /* Wait for reset to come into effect */ + } + } +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + + +#if(CY_IP_SRSSV2 || (CY_IP_WCO_WDT_EN && CY_IP_SRSSLT)) + /******************************************************************************* + * Function Name: CySysTimerDelay + ****************************************************************************//** + * + * \brief + * The function implements the delay specified in the LFCLK clock ticks. + * + * This API is applicable for PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / + * PSoC 4200 BLE / PRoC BLE / PSoC 4200L / PSoC 4100M / PSoC 4200M devices to + * use WDT. Also this API is available to use for PSoC4100S and / PSoC Analog + * Coprocessor devices to use DeepSleep Timers. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M / PSoC 4200M devices: + * The specified WDT counter should be configured as described below and started. + * + * For PSoC 4100S / PSoC Analog Coprocessor devices: + * The specified DeepSleep Timer counter should be configured as described below + * and started. + * + * This function can operate in two modes: the "WAIT" and "INTERRUPT" modes. In + * the "WAIT" mode, the function waits for the specified number of ticks. In the + * "INTERRUPT" mode, the interrupt is generated after the specified number of + * ticks. + * + * For the correct function operation, the "Clear On Match" option should be + * disabled for the specified WDT or DeepSleep Timer counter. Use + * CySysWdtSetClearOnMatch() for WDT or CySysTimerSetClearOnMatch() for DeepSleep + * Timer function with the "enable" parameter equal to zero for the used WDT + * counter or DeepSleep Timer counter. + * + * The corresponding WDT counter should be configured to match the selected + * mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" / "Watchdog (w/Interrupt)" for the "INTERRUPT" mode. + * + * Or the corresponding DeepSleep Timer counter should be configured to match the + * selected mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" for the "INTERRUPT" mode. + * + * This can be configured in two ways: + * - Through the DWR page. Open the "Clocks" tab, click the "Edit Clocks..." + * button, in the "Configure System Clocks" window click on the + * "Low Frequency Clocks" tab and choose the appropriate option for the used + * WDT or DeepSleep Timer counter. + * + * - Through the CySysWdtSetMode() for WDT or CySysTimerSetMode() for DeepSleep + * Timer function. Call it with the appropriate "mode" parameter for the + * used WDT or DeepSleep Timer counter. + * + * For the "INTERRUPT" mode, the recommended sequence is the following: + * - Call the CySysWdtDisableCounterIsr() for WDT or + * CySysTimerDisableIsr() for DeepSleep Timer function to disable servicing + * interrupts of the specified WDT or DeepSleep Timer counter. + * + * - Call the CySysWdtSetInterruptCallback() for WDT or + * CySysTimerSetIsrCallback() for DeepSleep Timer function to register + * the callback function for the corresponding WDT or DeepSleep Timer counter. + * + * - Call the CySysTimerDelay() function. + * + * \param counterNum Valid range [0-1]. The number of the counter + * (Timer0 or Timer1). + * \param delayType + * CY_SYS_TIMER_WAIT - "WAIT" mode.
+ * CY_SYS_TIMER_INTERRUPT - "INTERRUPT" mode. + * \param delay The delay value in the LFCLK ticks + * (allowable range - 16-bit value). + * + * \details + * In the "INTERRUPT" mode, this function enables ISR callback servicing + * from the corresponding WDT or DeepSleep Timer counter. Servicing of this ISR + * callback will be disabled after the expiration of the delay time. + * + *******************************************************************************/ + void CySysTimerDelay(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 delay) + { + uint32 regValue; + uint32 matchValue; + + #if(CY_IP_SRSSV2) + if((counterNum < CY_SYS_WDT_COUNTER2) && (0uL == CySysWdtGetClearOnMatch(counterNum)) && + (delay <= CY_SYS_UINT16_MAX_VAL)) + { + regValue = CySysWdtGetCount(counterNum); + matchValue = (regValue + delay) & (uint32)CY_SYS_UINT16_MAX_VAL; + + CySysTimerDelayUntilMatch(counterNum, delayType, matchValue); + } + else + { + CYASSERT(0u != 0u); + } + #endif /* (CY_IP_SRSSV2) */ + + #if(CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) + if((counterNum < CY_SYS_TIMER2) && (0uL == CySysTimerGetClearOnMatch(counterNum)) && + (delay <= CY_SYS_UINT16_MAX_VAL)) + { + regValue = CySysTimerGetCount(counterNum); + matchValue = (regValue + delay) & (uint32)CY_SYS_UINT16_MAX_VAL; + + CySysTimerDelayUntilMatch(counterNum, delayType, matchValue); + } + else + { + CYASSERT(0u != 0u); + } + #endif /* (CY_IP_WCO_WDT_EN) */ + } + + + /******************************************************************************* + * Function Name: CySysTimerDelayUntilMatch + ****************************************************************************//** + * + * \brief + * The function implements the delay specified as the number of WDT or DeepSleep + * Timer clock source ticks between WDT or DeepSleep Timer current value and + * match" value. + * + * This API is applicable for PSoC 4100 / PSoC 4200 / PRoC BLE / PSoC 4100 BLE / + * PSoC 4200 BLE / PSoC 4200L / PSoC 4100M / PSoC 4200M devices to use WDT. + * Also this API is available to use for PSoC4100S / Analog Coprocessor devices + * to use DeepSleep Timers. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M / PSoC 4200M devices: + * The function implements the delay specified as the number of LFCLK ticks + * between the specified WDT counter's current value and the "match" + * passed as the parameter to this function. The current WDT counter value can + * be obtained using the CySysWdtGetCount() function. + * + * For PSoC4100 S and Analog Coprocessor devices: + * The function implements the delay specified as the number of DeepSleep Timer + * input clock ticks for Timer0/Timer1 counter's current value and the "match" + * passed as the parameter to this function. The current DeepSleep Timer counter + * value can be obtained using the CySysWdtGetCount() function. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M / PSoC 4200M devices: + * The specified WDT counter should be configured as described below and started. + * + * For PSoC PSoC 4100S / PSoC Analog Coprocessor devices: + * The specified DeepSleep Timer counter should be configured as described below + * and started. + * + * This function can operate in two modes: the "WAIT" and "INTERRUPT" modes. In + * the "WAIT" mode, the function waits for the specified number of ticks. In the + * "INTERRUPT" mode, the interrupt is generated after the specified number of + * ticks. + * + * For the correct function operation, the "Clear On Match" option should be + * disabled for the specified WDT or DeepSleep Timer counter. Use + * CySysWdtSetClearOnMatch() for WDT or CySysTimerSetClearOnMatch() for DeepSleep + * Timer function with the "enable" parameter equal to zero for the used WDT + * or DeepSleep Timer counter. + * + * For PSoC 4100 / PSoC 4200 / PSoC 4100 BLE / PSoC 4200 BLE / PRoC BLE / PSoC + * 4200L / PSoC 4100M/PSoC 4200M devices: + * The corresponding WDT counter should be configured to match the selected + * mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" / "Watchdog (w/Interrupt)" for the "INTERRUPT" mode. + * + * For PSoC 4100S / PSoC Analog Coprocessor devices: + * Corresponding DeepSleep Timer counter should be configured to match the + * selected mode: "Free running Timer" for the "WAIT" mode, and + * "Periodic Timer" for the "INTERRUPT" mode. + * + * This can be configured in two ways: + * - Through the DWR page. Open the "Clocks" tab, click the "Edit Clocks..." + * button, in the "Configure System Clocks" window click on the + * "Low Frequency Clocks" tab and choose the appropriate option for the used + * WDT or DeepSleep Timer counter. + * + * - Through the CySysWdtSetMode() for WDT or CySysTimerSetMode() for DeepSleep + * Timer function. Call it with the appropriate "mode" parameter for the + * used WDT or DeepSleep Timer counter. + * + * For the "INTERRUPT" mode, the recommended sequence is the following: + * - Call the CySysWdtDisableCounterIsr() for WDT or + * CySysTimerDisableIsr() for DeepSleep Timer function to disable servicing + * interrupts of the specified WDT or DeepSleep Timer counter. + * + * - Call the CySysWdtSetInterruptCallback() for WDT or + * CySysTimerSetInterruptCallback() for DeepSleep Timer function to register + * the callback function for the corresponding WDT or DeepSleep Timer counter. + * + * - Call the CySysTimerDelay() function. + * + * \param counterNum Valid range [0-1]. The number of the WDT or DeepSleep + * Timer. + * counter (Timer0 or Timer1). + * \param delayType CY_SYS_TIMER_WAIT - "WAIT" mode.
+ * CY_SYS_TIMER_INTERRUPT - "INTERRUPT" mode. + * \param delay The delay value in the LFCLK ticks + * (allowable range - 16-bit value). + * + * \details + * In the "INTERRUPT" mode, this function enables ISR callback servicing + * from the corresponding WDT counter. Servicing of this ISR callback will be + * disabled after the expiration of the delay time. + * + *******************************************************************************/ + void CySysTimerDelayUntilMatch(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 match) + { + uint32 tmpValue; + + #if(CY_IP_SRSSV2) + if((counterNum < CY_SYS_WDT_COUNTER2) && (0uL == CySysWdtGetClearOnMatch(counterNum)) && + (match <= CY_SYS_UINT16_MAX_VAL)) + { + if(delayType == CY_SYS_TIMER_WAIT) + { + do + { + tmpValue = CySysWdtGetCount(counterNum); + }while(tmpValue > match); + + do + { + tmpValue = CySysWdtGetCount(counterNum); + }while(tmpValue < match); + } + else + { + tmpValue = counterIntMaskTbl[counterNum]; + CySysWdtSetMatch(counterNum, match); + + disableServicedIsr |= tmpValue; + wdtIsrMask |= tmpValue; + } + } + else + { + CYASSERT(0u != 0u); + } + + #endif /* (CY_IP_SRSSV2) */ + + #if(CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) + if((counterNum < CY_SYS_TIMER2) && (0uL == CySysTimerGetClearOnMatch(counterNum)) && + (match <= CY_SYS_UINT16_MAX_VAL)) + { + if(delayType == CY_SYS_TIMER_WAIT) + { + do + { + tmpValue = CySysTimerGetCount(counterNum); + }while(tmpValue > match); + + do + { + tmpValue = CySysTimerGetCount(counterNum); + }while(tmpValue < match); + } + else + { + tmpValue = counterTimerIntMaskTbl[counterNum]; + CySysTimerSetMatch(counterNum, match); + + disableTimerServicedIsr |= tmpValue; + timerIsrMask |= tmpValue; + } + } + else + { + CYASSERT(0u != 0u); + } + #endif /* (CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) */ + } + +#endif /* (CY_IP_SRSSV2 || (CY_IP_WCO_WDT_EN && CY_IP_SRSSLT) */ + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/CyLFClk.h b/cores/asr650x/projects/PSoC4/CyLFClk.h new file mode 100644 index 00000000..142f4a64 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/CyLFClk.h @@ -0,0 +1,724 @@ +/***************************************************************************//** +* \file .h +* \version 1.20 +* +* \brief +* This file provides the source code to API for the lfclk and wdt. +* +******************************************************************************** +* \copyright +* Copyright 2008-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_LFCLK_CYLIB_H) +#define CY_LFCLK_CYLIB_H + +#include "cytypes.h" +#include "cydevice_trm.h" + +#define CY_IP_WCO_WDT_EN (1 == 1) + +typedef enum +{ + CY_SYS_TIMER_WAIT = 0u, + CY_SYS_TIMER_INTERRUPT = 1u +} cy_sys_timer_delaytype_enum; + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +/* Clocks API */ +void CySysClkIloStart(void); +void CySysClkIloStop(void); +/** @} general */ + +/** +* \addtogroup group_compensate +* @{ +*/ +cystatus CySysClkIloCompensate(uint32 desiredDelay, uint32 *compensatedCycles); +void CySysClkIloStartMeasurement(void); +void CySysClkIloStopMeasurement(void); +/** @} compensate */ + +#if(CY_IP_SRSSV2 && (!CY_IP_CPUSS)) + /** + * \addtogroup group_compensate + * @{ + */ + cystatus CySysClkIloTrim(uint32 mode, int32 *iloAccuracyInPPT); + cystatus CySysClkIloRestoreFactoryTrim(void); + /** @} compensate */ + cystatus CySysClkIloUpdateTrimReg(int32* iloAccuracyInPPT); +#endif /* (CY_IP_SRSSV2 && (!CY_IP_CPUSS)) */ + +#if(CY_IP_SRSSV2 && CY_IP_WCO) + /** + * \addtogroup group_general + * @{ + */ + void CySysClkSetLfclkSource(uint32 source); + /** @} group_general */ +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO) */ + +#if (CY_IP_WCO) + /** + * \addtogroup group_wco + * @{ + */ + void CySysClkWcoStart(void); + void CySysClkWcoStop(void); + uint32 CySysClkWcoSetPowerMode(uint32 mode); + void CySysClkWcoClockOutSelect(uint32 clockSel); + /** @} wco */ + + uint32 CySysClkWcoEnabled(void); + +#endif /* (CY_IP_WCO) */ + +typedef void (*cyWdtCallback)(void); + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + + typedef void (*cyTimerCallback)(void); +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +#if(CY_IP_SRSSV2) + /** + * \addtogroup group_wdtsrssv2 + * @{ + */ + /* WDT API */ + void CySysWdtLock(void); + void CySysWdtUnlock(void); + void CySysWdtSetMode(uint32 counterNum, uint32 mode); + uint32 CySysWdtGetMode(uint32 counterNum); + uint32 CySysWdtGetEnabledStatus(uint32 counterNum); + void CySysWdtSetClearOnMatch(uint32 counterNum, uint32 enable); + uint32 CySysWdtGetClearOnMatch(uint32 counterNum); + void CySysWdtEnable(uint32 counterMask); + void CySysWdtDisable(uint32 counterMask); + void CySysWdtSetCascade(uint32 cascadeMask); + uint32 CySysWdtGetCascade(void); + void CySysWdtSetMatch(uint32 counterNum, uint32 match); + void CySysWdtSetToggleBit(uint32 bits); + uint32 CySysWdtGetToggleBit(void); + uint32 CySysWdtGetMatch(uint32 counterNum); + uint32 CySysWdtGetCount(uint32 counterNum); + uint32 CySysWdtGetInterruptSource(void); + void CySysWdtClearInterrupt(uint32 counterMask); + void CySysWdtResetCounters(uint32 countersMask); + cyWdtCallback CySysWdtSetInterruptCallback(uint32 counterNum, cyWdtCallback function); + cyWdtCallback CySysWdtGetInterruptCallback(uint32 counterNum); + void CySysTimerDelay(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 delay); + void CySysTimerDelayUntilMatch(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 match); + void CySysWatchdogFeed(uint32 counterNum); + void CySysWdtEnableCounterIsr(uint32 counterNum); + void CySysWdtDisableCounterIsr(uint32 counterNum); + void CySysWdtIsr(void); + /** @} wdtsrssv2 */ +#else + /** + * \addtogroup group_wdtsrsslite + * @{ + */ + /* WDT API */ + uint32 CySysWdtGetEnabledStatus(void); + void CySysWdtEnable(void); + void CySysWdtDisable(void); + void CySysWdtSetMatch(uint32 match); + uint32 CySysWdtGetMatch(void); + uint32 CySysWdtGetCount(void); + void CySysWdtSetIgnoreBits(uint32 bitsNum); + uint32 CySysWdtGetIgnoreBits(void); + void CySysWdtClearInterrupt(void); + void CySysWdtMaskInterrupt(void); + void CySysWdtUnmaskInterrupt(void); + cyWdtCallback CySysWdtSetInterruptCallback(cyWdtCallback function); + cyWdtCallback CySysWdtGetInterruptCallback(void); + void CySysWdtIsr(void); + /** @} wdtsrsslite*/ +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + /** + * \addtogroup group_deepsleepwdt + * @{ + */ + /* WCO WDT APIs */ + void CySysClkSetTimerSource(uint32 source); + void CySysTimerSetMode(uint32 counterNum, uint32 mode); + uint32 CySysTimerGetMode(uint32 counterNum); + uint32 CySysTimerGetEnabledStatus(uint32 counterNum); + void CySysTimerSetClearOnMatch(uint32 counterNum, uint32 enable); + uint32 CySysTimerGetClearOnMatch(uint32 counterNum); + void CySysTimerEnable(uint32 counterMask); + void CySysTimerDisable(uint32 counterMask); + void CySysTimerSetCascade(uint32 cascadeMask); + uint32 CySysTimerGetCascade(void); + void CySysTimerSetMatch(uint32 counterNum, uint32 match); + void CySysTimerSetToggleBit(uint32 bits); + uint32 CySysTimerGetToggleBit(void); + uint32 CySysTimerGetMatch(uint32 counterNum); + uint32 CySysTimerGetCount(uint32 counterNum); + uint32 CySysTimerGetInterruptSource(void); + void CySysTimerClearInterrupt(uint32 counterMask); + cyTimerCallback CySysTimerSetInterruptCallback(uint32 counterNum, cyTimerCallback function); + cyTimerCallback CySysTimerGetInterruptCallback(uint32 counterNum); + void CySysTimerDelay(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 delay); + void CySysTimerDelayUntilMatch(uint32 counterNum, cy_sys_timer_delaytype_enum delayType, uint32 match); + void CySysTimerResetCounters(uint32 countersMask); + void CySysTimerEnableIsr(uint32 counterNum); + void CySysTimerDisableIsr(uint32 counterNum); + void CySysTimerIsr(void); + /** @} deepsleepwdt */ +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + + +/******************************************************************************* +* API Constants +*******************************************************************************/ +#define CY_SYS_UINT16_MAX_VAL (0xFFFFu) + + +/******************************************************************************* +* Clock API Constants +*******************************************************************************/ + +/* CySysClkIloStart()/CySysClkIloStop() - implementation definitions */ +#define CY_SYS_CLK_ILO_CONFIG_ENABLE ((uint32)(( uint32 )0x01u << 31u)) +#define CY_SYS_CLK_DFT_SELECT_DEFAULT_MASK ((uint32)(( uint32 )0x0fu << 8u )) + +/* CySysClkIloCompensate() - one ILO clock in uS multiplied on thousand */ +#if (CY_IP_SRSSV2) + #define CY_SYS_CLK_ILO_PERIOD_PPH ((uint32) (0x0C35u)) +#else + #define CY_SYS_CLK_ILO_PERIOD_PPH ((uint32) (0x09C4u)) +#endif /* (CY_IP_SRSSV2) */ + +/* CySysClkIloCompensate() - implementation definitions */ +#define CY_SYS_CLK_ILO_CALIBR_COMPLETE_MASK ((uint32)(( uint32 )0x01u << 31u)) +#define CY_SYS_CLK_ILO_DFT_LSB_MASK ((uint32)(0x00000FFFu)) +#define CY_SYS_CLK_TRIM_OR_COMP_STARTED (1u) +#define CY_SYS_CLK_TRIM_OR_COMP_FINISHED (0u) +#define CY_SYS_CLK_COEF_PHUNDRED ((uint32) (0x64u)) +#define CY_SYS_CLK_HALF_OF_CLOCK ((uint32) ((uint32) CY_SYS_CLK_ILO_PERIOD_PPH >> 2u)) + +/* CySysClkIloCompensate() - maximum value of desiredDelay argument */ +#if (CY_IP_SRSSV2) + #define CY_SYS_CLK_MAX_DELAY_US ((uint32) (0xEE6B2800u)) + #define CY_SYS_CLK_ILO_PERIOD ((uint32) (0x1Fu)) + #define CY_SYS_CLK_ILO_FREQ_2MSB ((uint32) 5u) +#else + #define CY_SYS_CLK_MAX_DELAY_US ((uint32) (0x1E8480u)) + #define CY_SYS_CLK_ILO_FREQ_2MSB ((uint32) (0x28u )) + + /********************************************************************************** + * CySysClkIloCompensate() - value to walk over oversamling in calculations with + * srsslite. The oversample can be obtained when ilo frequency in equal 80 KHz and + * desired clocks are 80 000 clocks. + **********************************************************************************/ + #define CY_SYS_CLK_MAX_LITE_NUMBER ((uint32) 53600u) +#endif /* (CY_IP_SRSSV2) */ + +#define CY_SYS_CLK_ILO_FREQ_3LSB ((uint32) (0x3E8u)) +#define CY_SYS_CLK_DELAY_COUNTS_LIMIT ((uint32) (0xD160u)) +#define CY_SYS_CLK_MIN_DELAY_US ((uint32) (0x64u)) + +/* CySysClkSetLfclkSource() - parameter definitions */ +#if (CY_IP_SRSSV2 && CY_IP_WCO) + + /** Internal Low Frequency (32 kHz) Oscillator (ILO) */ + #define CY_SYS_CLK_LFCLK_SRC_ILO (0u) + + /** Low Frequency Watch Crystal Oscillator (WCO) */ + #define CY_SYS_CLK_LFCLK_SRC_WCO ((uint32)(( uint32 )0x01u << 30u)) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO) */ + + +#if (CY_IP_WCO) + + /* CySysClkSetLfclkSource() - implementation definitions */ + #define CY_SYS_CLK_LFCLK_SEL_MASK ((uint32)(( uint32 )0x03u << 30u)) +#endif /* (CY_IP_WCO) */ + +/* CySysClkSetTimerSource() - implementation definitions */ +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + #define CY_SYS_CLK_TIMER_SEL_MASK ((uint32)(( uint32 )0x03u << 30u)) +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +/* CySysClkSetTimerSource() - parameter definitions */ +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + + /** Internal Low Frequency (32 kHz) Oscillator (ILO) */ + #define CY_SYS_CLK_TIMER_SRC_ILO (0u) + + /** Low Frequency Watch Crystal Oscillator (WCO) */ + #define CY_SYS_CLK_TIMER_SRC_WCO ((uint32)(( uint32 )0x01u << 30u)) +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +/* CySysClkWcoClockOutSelect() - parameter definitions */ +#if (CY_IP_WCO) + + /** Selects External crystal as WCO鈥檚 clock source */ + #define CY_SYS_CLK_WCO_SEL_CRYSTAL (1u) + + /** Selects External clock input on wco_in pin as WCO鈥檚 clock source */ + #define CY_SYS_CLK_WCO_SEL_PIN (0u) +#endif /* (CY_IP_WCO) */ + +/* CySysClkWcoClockOutSelect() - implementation definitions */ +#if (CY_IP_WCO) + #define CY_SYS_CLK_WCO_SELECT_PIN_MASK ((uint32)(( uint32 )0x01u << 2u)) + #define CY_SYS_CLK_WCO_SELECT_PIN_OFFSET ((uint32) 0x02u) +#endif /* (CY_IP_WCO) */ + +/* CySysClkIloRestoreFactoryTrim() - implementation definitions */ +#if (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) + #define CY_SYS_CLK_ILO_TRIM_DEFAULT_VALUE ((uint8 )(0xF0u)) + #define CY_SYS_CLK_ILO_TRIM_DEFAULT_MASK ((uint32)((uint32)0x01u << 3u)) + #define CY_SYS_CLK_ILO_TRIM_MASK ((uint32)(0x0Fu)) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) */ + +/* CySysIloTrim() - parameter definitions and macros*/ +#if (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) + #define CY_SYS_CLK_BLOCKING (0u) + #define CY_SYS_CLK_NON_BLOCKING (1u) + #define CY_SYS_CLK_PERTHOUSAND ((uint32) 0x000003E8u ) + #define CY_SYS_CLK_ABS_MACRO(x) ((0 > (x)) ? (-(x)) : (x)) + #define CY_SYS_CLK_ERROR_RANGE ((uint32) 0x38u) + #define CY_SYS_CLK_TIMEOUT ((uint8 ) 0x05u) + + /* ILO error step is 7,37 % error range */ + #define CY_SYS_CLK_ERROR_STEP (( int32) 0x02E1u) + #define CY_SYS_CLK_ERROR_COEF ((uint32) 0x0Au) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO && (!CY_IP_CPUSS)) */ + +#if (CY_IP_WCO) + + /* WCO Configuration Register */ + #define CY_SYS_CLK_WCO_CONFIG_LPM_EN (( uint32 )(( uint32 )0x01u << 0u)) + #define CY_SYS_CLK_WCO_CONFIG_LPM_AUTO (( uint32 )(( uint32 )0x01u << 1u)) + #define CY_SYS_CLK_WCO_CONFIG_LPM_ENABLE (( uint32 )(( uint32 )0x01u << 31u)) + + /* WCO Status Register */ + #define CY_SYS_CLK_WCO_STATUS_OUT_BLNK_A (( uint32 )(( uint32 )0x01u << 0u)) + + /* WCO Trim Register */ + #define CY_SYS_CLK_WCO_TRIM_XGM_MASK (( uint32 ) 0x07u) + #define CY_SYS_CLK_WCO_TRIM_XGM_SHIFT (( uint32 ) 0x00u) + + #define CY_SYS_CLK_WCO_TRIM_XGM_3370NA (( uint32 ) 0x00u) + #define CY_SYS_CLK_WCO_TRIM_XGM_2620NA (( uint32 ) 0x01u) + #define CY_SYS_CLK_WCO_TRIM_XGM_2250NA (( uint32 ) 0x02u) + #define CY_SYS_CLK_WCO_TRIM_XGM_1500NA (( uint32 ) 0x03u) + #define CY_SYS_CLK_WCO_TRIM_XGM_1870NA (( uint32 ) 0x04u) + #define CY_SYS_CLK_WCO_TRIM_XGM_1120NA (( uint32 ) 0x05u) + #define CY_SYS_CLK_WCO_TRIM_XGM_750NA (( uint32 ) 0x06u) + #define CY_SYS_CLK_WCO_TRIM_XGM_0NA (( uint32 ) 0x07u) + + #define CY_SYS_CLK_WCO_TRIM_GM_MASK (( uint32 )(( uint32 )0x03u << 4u)) + #define CY_SYS_CLK_WCO_TRIM_GM_SHIFT (( uint32 ) 0x04u) + #define CY_SYS_CLK_WCO_TRIM_GM_HPM (( uint32 ) 0x01u) + #define CY_SYS_CLK_WCO_TRIM_GM_LPM (( uint32 ) 0x02u) +#endif /* (CY_IP_WCO) */ + + +/******************************************************************************* +* WDT API Constants +*******************************************************************************/ +#if(CY_IP_SRSSV2) + + #define CY_SYS_WDT_MODE_NONE (0u) + #define CY_SYS_WDT_MODE_INT (1u) + #define CY_SYS_WDT_MODE_RESET (2u) + #define CY_SYS_WDT_MODE_INT_RESET (3u) + + #define CY_SYS_WDT_COUNTER0_MASK ((uint32)((uint32)0x01u)) /**< Counter 0 */ + #define CY_SYS_WDT_COUNTER1_MASK ((uint32)((uint32)0x01u << 8u)) /**< Counter 1 */ + #define CY_SYS_WDT_COUNTER2_MASK ((uint32)((uint32)0x01u << 16u)) /**< Counter 2 */ + + #define CY_SYS_WDT_CASCADE_NONE ((uint32)0x00u) /**< Neither */ + #define CY_SYS_WDT_CASCADE_01 ((uint32)0x01u << 3u) /**< Cascade 01 */ + #define CY_SYS_WDT_CASCADE_12 ((uint32)0x01u << 11u) /**< Cascade 12 */ + + #define CY_SYS_WDT_COUNTER0_INT ((uint32)0x01u << 2u) + #define CY_SYS_WDT_COUNTER1_INT ((uint32)0x01u << 10u) + #define CY_SYS_WDT_COUNTER2_INT ((uint32)0x01u << 18u) + + #define CY_SYS_WDT_COUNTER0_RESET ((uint32)0x01u << 3u) /**< Counter 0 */ + #define CY_SYS_WDT_COUNTER1_RESET ((uint32)0x01u << 11u) /**< Counter 1 */ + #define CY_SYS_WDT_COUNTER2_RESET ((uint32)0x01u << 19u) /**< Counter 2 */ + + #define CY_SYS_WDT_COUNTERS_RESET (CY_SYS_WDT_COUNTER0_RESET |\ + CY_SYS_WDT_COUNTER1_RESET |\ + CY_SYS_WDT_COUNTER2_RESET) + + #define CY_SYS_WDT_COUNTER0 (0x00u) + #define CY_SYS_WDT_COUNTER1 (0x01u) + #define CY_SYS_WDT_COUNTER2 (0x02u) + + #define CY_SYS_WDT_COUNTER0_OFFSET (0x00u) + #define CY_SYS_WDT_COUNTER1_OFFSET (0x02u) + #define CY_SYS_WDT_COUNTER2_OFFSET (0x04u) + + #define CY_SYS_WDT_MODE_MASK ((uint32)(0x03u)) + + #define CY_SYS_WDT_CONFIG_BITS2_MASK (uint32)(0x1Fu) + #define CY_SYS_WDT_CONFIG_BITS2_POS (uint32)(24u) + #define CY_SYS_WDT_LOWER_16BITS_MASK (uint32)(0x0000FFFFu) + #define CY_SYS_WDT_HIGHER_16BITS_MASK (uint32)(0xFFFF0000u) + #define CY_SYS_WDT_COUNTERS_MAX (0x03u) + #define CY_SYS_WDT_CNT_SHIFT (0x08u) + #define CY_SYS_WDT_CNT_MATCH_CLR_SHIFT (0x02u) + #define CY_SYS_WDT_CNT_STTS_SHIFT (0x01u) + #define CY_SYS_WDT_CNT_MATCH_SHIFT (0x10u) + + #define CY_SYS_WDT_CLK_LOCK_BITS_MASK ((uint32)0x03u << 14u) + #define CY_SYS_WDT_CLK_LOCK_BIT0 ((uint32)0x01u << 14u) + #define CY_SYS_WDT_CLK_LOCK_BIT1 ((uint32)0x01u << 15u) + + #define CY_WDT_NUM_OF_WDT (3u) + #define CY_WDT_NUM_OF_CALLBACKS (3u) + + #else + #define CY_WDT_NUM_OF_WDT (1u) + #define CY_WDT_NUM_OF_CALLBACKS (3u) + #define CY_SYS_WDT_KEY ((uint32)(0xACED8865u)) + #define CY_SYS_WDT_MATCH_MASK ((uint32)(0x0000FFFFu)) + #define CY_SYS_WDT_IGNORE_BITS_MASK ((uint32)(0x000F0000u)) + #define CY_SYS_WDT_IGNORE_BITS_SHIFT ((uint32)(16u)) + #define CY_SYS_WDT_LOWER_BIT_MASK ((uint32)(0x00000001u)) + + #define CY_SYS_WDT_COUNTER0 (0x00u) + +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_SRSSV2 && CY_IP_WCO) + #define CY_SYS_WDT_1LFCLK_ILO_DELAY_US ((uint16)( 67u)) + #define CY_SYS_WDT_3LFCLK_ILO_DELAY_US ((uint16)(201u)) + #define CY_SYS_WDT_1LFCLK_WCO_DELAY_US ((uint16)( 31u)) + #define CY_SYS_WDT_3LFCLK_WCO_DELAY_US ((uint16)( 93u)) + + #define CY_SYS_WDT_1LFCLK_DELAY_US \ + ((CY_SYS_CLK_LFCLK_SRC_ILO == (CY_SYS_WDT_CONFIG_REG & CY_SYS_CLK_LFCLK_SEL_MASK)) ? \ + (CY_SYS_WDT_1LFCLK_ILO_DELAY_US) : \ + (CY_SYS_WDT_1LFCLK_WCO_DELAY_US)) + + #define CY_SYS_WDT_3LFCLK_DELAY_US \ + ((CY_SYS_CLK_LFCLK_SRC_ILO == (CY_SYS_WDT_CONFIG_REG & CY_SYS_CLK_LFCLK_SEL_MASK)) ? \ + (CY_SYS_WDT_3LFCLK_ILO_DELAY_US) : \ + (CY_SYS_WDT_3LFCLK_WCO_DELAY_US)) + #else + #define CY_SYS_WDT_1LFCLK_DELAY_US ((uint16) (67u)) + #define CY_SYS_WDT_3LFCLK_DELAY_US ((uint16) (201u)) +#endif /* (CY_IP_SRSSV2 && CY_IP_WCO) */ + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + + #define CY_SYS_TIMER_MODE_NONE (0u) + #define CY_SYS_TIMER_MODE_INT (1u) + + #define CY_SYS_TIMER0_MASK ((uint32)((uint32)0x01u)) /**< Counter 0 */ + #define CY_SYS_TIMER1_MASK ((uint32)((uint32)0x01u << 8u)) /**< Counter 1 */ + #define CY_SYS_TIMER2_MASK ((uint32)((uint32)0x01u << 16u)) /**< Counter 2 */ + + #define CY_SYS_TIMER0_RESET ((uint32)0x01u << 3u) /**< Counter 0 */ + #define CY_SYS_TIMER1_RESET ((uint32)0x01u << 11u) /**< Counter 1 */ + #define CY_SYS_TIMER2_RESET ((uint32)0x01u << 19u) /**< Counter 2 */ + + #define CY_SYS_TIMER_RESET (CY_SYS_TIMER0_RESET |\ + CY_SYS_TIMER1_RESET |\ + CY_SYS_TIMER2_RESET) + + #define CY_SYS_TIMER_CASCADE_NONE ((uint32)0x00u) /**< Neither */ + #define CY_SYS_TIMER_CASCADE_01 ((uint32)0x01u << 3u) /**< Cascade 01 */ + #define CY_SYS_TIMER_CASCADE_12 ((uint32)0x01u << 11u) /**< Cascade 12 */ + + #define CY_SYS_TIMER0_INT ((uint32)0x01u << 2u) + #define CY_SYS_TIMER1_INT ((uint32)0x01u << 10u) + #define CY_SYS_TIMER2_INT ((uint32)0x01u << 18u) + + #define CY_SYS_TIMER0 (0x00u) + #define CY_SYS_TIMER1 (0x01u) + #define CY_SYS_TIMER2 (0x02u) + + #define CY_SYS_TIMER_MODE_MASK ((uint32)(0x01u)) + + #define CY_SYS_TIMER_CONFIG_BITS2_MASK (uint32)(0x1Fu) + #define CY_SYS_TIMER_CONFIG_BITS2_POS (uint32)(24u) + #define CY_SYS_TIMER_LOWER_16BITS_MASK (uint32)(0x0000FFFFu) + #define CY_SYS_TIMER_HIGHER_16BITS_MASK (uint32)(0xFFFF0000u) + #define CY_SYS_TIMER_COUNTERS_MAX (0x03u) + #define CY_SYS_TIMER_CNT_SHIFT (0x08u) + #define CY_SYS_TIMER_CNT_MATCH_CLR_SHIFT (0x02u) + #define CY_SYS_TIMER_CNT_STTS_SHIFT (0x01u) + #define CY_SYS_TIMER_CNT_MATCH_SHIFT (0x10u) + + #define CY_SYS_NUM_OF_TIMERS (3u) + + #define CY_SYS_SET_NEW_TIMER_SOURCE_ILO ((uint16)(0x02u)) + #define CY_SYS_SET_NEW_TIMER_SOURCE_WCO ((uint16)(0x01u)) + #define CY_SYS_WCO_WDT_CLKEN_RESET_MASK ((uint32)(0x03u)) + + #define CY_SYS_TIMER_1ILO_DELAY_US ((uint16)( 67u)) + #define CY_SYS_TIMER_4ILO_DELAY_US ((uint16)(268u)) + #define CY_SYS_TIMER_3ILO_DELAY_US ((uint16)(201u)) + + #define CY_SYS_TIMER_1WCO_DELAY_US ((uint16)( 31u)) + #define CY_SYS_TIMER_4WCO_DELAY_US ((uint16)(124u)) + #define CY_SYS_TIMER_3WCO_DELAY_US ((uint16)( 93u)) + + #define CY_SYS_1TIMER_DELAY_US \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_TIMER_1ILO_DELAY_US) : \ + (CY_SYS_TIMER_1WCO_DELAY_US)) + + #define CY_SYS_4TIMER_DELAY_US \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_TIMER_4WCO_DELAY_US) : \ + (CY_SYS_TIMER_4ILO_DELAY_US)) + + #define CY_SYS_3TIMER_DELAY_US \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_TIMER_3ILO_DELAY_US) : \ + (CY_SYS_TIMER_3WCO_DELAY_US)) + + #define CY_SYS_SET_CURRENT_TIMER_SOURCE_BIT \ + ((CY_SYS_CLK_TIMER_SRC_ILO == (CY_SYS_WCO_WDT_CONFIG_REG & CY_SYS_CLK_TIMER_SEL_MASK)) ? \ + (CY_SYS_SET_NEW_TIMER_SOURCE_ILO) : \ + (CY_SYS_SET_NEW_TIMER_SOURCE_WCO)) + +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +/* CySysClkWcoSetPowerMode() */ +#define CY_SYS_CLK_WCO_HPM (0x0u) /**< WCO High power mode */ + +#if(CY_IP_BLESS) + #define CY_SYS_CLK_WCO_LPM (0x1u) /**< WCO Low power mode */ +#endif /* (CY_IP_BLESS) */ + + +/******************************************************************************* +* Trim Registers Constants +********************************************************************************/ +#define CY_SYS_CLK_SYS_CLK_DEVIDER ((uint32)0x0Au) +#define CY_SYS_CLK_SEL_ILO_DFT_SOURCE ((uint32)0x00000100u) +#define CY_SYS_CLK_FOURBITS_MAX (( int32)0x0f) +#define CY_SYS_CLK_HALF_OF_STEP (( int32)((uint32) CY_SYS_CLK_ERROR_STEP >> 1u)) + +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_ILO_DESIRED_FREQ_HZ (32000u) + #define CY_SYS_CLK_DFT_SELSIZE ((uint32) 0x3F) +#else + #define CY_SYS_CLK_ILO_DESIRED_FREQ_HZ (40000u) + #define CY_SYS_CLK_DFT_SELSIZE ((uint32) 0x0F) +#endif /* (CY_IP_SRSSV2) */ + +#define CY_SYS_TST_DDFT_CTRL_REG_DEFAULT_MASK ((uint32)((CY_SYS_CLK_DFT_SELSIZE << 8u) | (CY_SYS_CLK_DFT_SELSIZE ))) +#define CY_SYS_TST_DDFT_SELECT_CLK1 ((uint32) ((uint32) CYDEV_DFT_SELECT_CLK1 << 8u)) +#define CY_SYS_TST_DDFT_CTRL_REG_SEL2_CLK1 ((uint32) (CY_SYS_TST_DDFT_SELECT_CLK1 | CYDEV_DFT_SELECT_CLK0)) + + +/******************************************************************************* +* Trim Registers +********************************************************************************/ +/* DFT TST Control Register*/ +#define CY_SYS_TST_DDFT_CTRL_REG (*(reg32*) CYREG_TST_DDFT_CTRL) +#define CY_SYS_CNT_CTRL_PTR ( (reg32*) CYREG_TST_DDFT_CTRL) + +/* DFT TST Counter 1 Register*/ +#define CY_SYS_CNT_REG1_REG (*(reg32*) CYREG_TST_TRIM_CNTR1) +#define CY_SYS_CNT_REG1_PTR ( (reg32*) CYREG_TST_TRIM_CNTR1) + +/* DFT TST Counter 2 Register*/ +#define CY_SYS_CNT_REG2_REG (*(reg32*) CYREG_TST_TRIM_CNTR2) +#define CY_SYS_CNT_REG2_PTR ( (reg32*) CYREG_TST_TRIM_CNTR2) + +/* DFT Muxes Configuration Register*/ +#define CY_SYS_CLK_DFT_REG (*(reg32*) CYREG_CLK_DFT_SELECT) +#define CY_SYS_CLK_DFT_PTR ( (reg32*) CYREG_CLK_DFT_SELECT) + +/* ILO Configuration Register*/ +#define CY_SYS_CLK_ILO_CONFIG_REG (*(reg32 *) CYREG_CLK_ILO_CONFIG) +#define CY_SYS_CLK_ILO_CONFIG_PTR ( (reg32 *) CYREG_CLK_ILO_CONFIG) + +/* ILO Trim Register*/ +#if(CY_IP_SRSSV2 && CY_IP_WCO) + #define CY_SYS_CLK_ILO_TRIM_REG (*(reg32 *) CYREG_CLK_ILO_TRIM) + #define CY_SYS_CLK_ILO_TRIM_PTR ( (reg32 *) CYREG_CLK_ILO_TRIM) +#endif /* (CY_IP_SRSSV2) && CY_IP_WCO*/ + +#if (CY_IP_WCO) + #if (CY_IP_BLESS) + + /* WCO Status Register */ + #define CY_SYS_CLK_WCO_STATUS_REG (*(reg32 *) CYREG_BLE_BLESS_WCO_STATUS) + #define CY_SYS_CLK_WCO_STATUS_PTR ( (reg32 *) CYREG_BLE_BLESS_WCO_STATUS) + + /* WCO Configuration Register */ + #define CY_SYS_CLK_WCO_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_WCO_CONFIG) + #define CY_SYS_CLK_WCO_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_WCO_CONFIG) + + /* WCO Trim Register */ + #define CY_SYS_CLK_WCO_TRIM_REG (*(reg32 *) CYREG_BLE_BLESS_WCO_TRIM) + #define CY_SYS_CLK_WCO_TRIM_PTR ( (reg32 *) CYREG_BLE_BLESS_WCO_TRIM) + #else + + /* WCO Status Register */ + #define CY_SYS_CLK_WCO_STATUS_REG (*(reg32 *) CYREG_WCO_STATUS) + #define CY_SYS_CLK_WCO_STATUS_PTR ( (reg32 *) CYREG_WCO_STATUS) + + /* WCO Configuration Register */ + #define CY_SYS_CLK_WCO_CONFIG_REG (*(reg32 *) CYREG_WCO_CONFIG) + #define CY_SYS_CLK_WCO_CONFIG_PTR ( (reg32 *) CYREG_WCO_CONFIG) + + /* WCO Trim Register */ + #define CY_SYS_CLK_WCO_TRIM_REG (*(reg32 *) CYREG_WCO_TRIM) + #define CY_SYS_CLK_WCO_TRIM_PTR ( (reg32 *) CYREG_WCO_TRIM) + #endif /* (CY_IP_BLESS) */ +#endif /* (CY_IP_WCO) */ + + +/******************************************************************************* +* WDT API Registers +*******************************************************************************/ +#if(CY_IP_SRSSV2) + #define CY_SYS_WDT_CTRLOW_REG (*(reg32 *) CYREG_WDT_CTRLOW) + #define CY_SYS_WDT_CTRLOW_PTR ( (reg32 *) CYREG_WDT_CTRLOW) + + #define CY_SYS_WDT_CTRHIGH_REG (*(reg32 *) CYREG_WDT_CTRHIGH) + #define CY_SYS_WDT_CTRHIGH_PTR ( (reg32 *) CYREG_WDT_CTRHIGH) + + #define CY_SYS_WDT_MATCH_REG (*(reg32 *) CYREG_WDT_MATCH) + #define CY_SYS_WDT_MATCH_PTR ( (reg32 *) CYREG_WDT_MATCH) + + #define CY_SYS_WDT_CONFIG_REG (*(reg32 *) CYREG_WDT_CONFIG) + #define CY_SYS_WDT_CONFIG_PTR ( (reg32 *) CYREG_WDT_CONFIG) + + #define CY_SYS_WDT_CONTROL_REG (*(reg32 *) CYREG_WDT_CONTROL) + #define CY_SYS_WDT_CONTROL_PTR ( (reg32 *) CYREG_WDT_CONTROL) +#else + #define CY_SYS_WDT_DISABLE_KEY_REG (*(reg32 *) CYREG_WDT_DISABLE_KEY) + #define CY_SYS_WDT_DISABLE_KEY_PTR ( (reg32 *) CYREG_WDT_DISABLE_KEY) + + #define CY_SYS_WDT_MATCH_REG (*(reg32 *) CYREG_WDT_MATCH) + #define CY_SYS_WDT_MATCH_PTR ( (reg32 *) CYREG_WDT_MATCH) + + #define CY_SYS_WDT_COUNTER_REG (*(reg32 *) CYREG_WDT_COUNTER) + #define CY_SYS_WDT_COUNTER_PTR ( (reg32 *) CYREG_WDT_COUNTER) + + #define CY_SYS_SRSS_INTR_REG (*(reg32 *) CYREG_SRSS_INTR) + #define CY_SYS_SRSS_INTR_PTR ( (reg32 *) CYREG_SRSS_INTR) + + #define CY_SYS_SRSS_INTR_MASK_REG (*(reg32 *) CYREG_SRSS_INTR_MASK) + #define CY_SYS_SRSS_INTR_MASK_PTR ( (reg32 *) CYREG_SRSS_INTR_MASK) +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) + #define CY_SYS_WCO_WDT_CTRLOW_REG (*(reg32 *) CYREG_WCO_WDT_CTRLOW) + #define CY_SYS_WCO_WDT_CTRLOW_PTR ( (reg32 *) CYREG_WCO_WDT_CTRLOW) + + #define CY_SYS_WCO_WDT_CTRHIGH_REG (*(reg32 *) CYREG_WCO_WDT_CTRHIGH) + #define CY_SYS_WCO_WDT_CTRHIGH_PTR ( (reg32 *) CYREG_WCO_WDT_CTRHIGH) + + #define CY_SYS_WCO_WDT_MATCH_REG (*(reg32 *) CYREG_WCO_WDT_MATCH) + #define CY_SYS_WCO_WDT_MATCH_PTR ( (reg32 *) CYREG_WCO_WDT_MATCH) + + #define CY_SYS_WCO_WDT_CONFIG_REG (*(reg32 *) CYREG_WCO_WDT_CONFIG) + #define CY_SYS_WCO_WDT_CONFIG_PTR ( (reg32 *) CYREG_WCO_WDT_CONFIG) + + #define CY_SYS_WCO_WDT_CONTROL_REG (*(reg32 *) CYREG_WCO_WDT_CONTROL) + #define CY_SYS_WCO_WDT_CONTROL_PTR ( (reg32 *) CYREG_WCO_WDT_CONTROL) + + #define CY_SYS_WCO_WDT_CLKEN_REG (*(reg32 *) CYREG_WCO_WDT_CLKEN) + #define CY_SYS_WCO_WDT_CLKEN_PTR ( (reg32 *) CYREG_WCO_WDT_CLKEN) +#endif /* (CY_IP_SRSSLT && CY_IP_WCO && CY_IP_WCO_WDT_EN) */ + +#if (CY_IP_WCO) + + /******************************************************************************* + * Function Name: CySysClkWcoSetHighPowerMode + ******************************************************************************** + * + * Summary: + * Sets the high power mode for the 32 KHz WCO. + * + *******************************************************************************/ + static CY_INLINE void CySysClkWcoSetHighPowerMode(void) + { + /* Switch off low power mode for WCO */ + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_LPM_EN; + + /* Switch off auto low power mode in WCO */ + CY_SYS_CLK_WCO_CONFIG_REG &= ((uint32)~CY_SYS_CLK_WCO_CONFIG_LPM_AUTO); + + /* Restore WCO trim register HPM settings */ + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_GM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_GM_HPM << CY_SYS_CLK_WCO_TRIM_GM_SHIFT); + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_XGM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_XGM_2620NA << CY_SYS_CLK_WCO_TRIM_XGM_SHIFT); + } + + #if(CY_IP_BLESS) + /******************************************************************************* + * Function Name: CySysClkWcoSetLowPowerMode + ******************************************************************************** + * + * Summary: + * Sets the low power mode for the 32 KHz WCO. + * + * Note LPM available only for PSoC 4100 BLE / PSoC4 4200 BLE + *******************************************************************************/ + static CY_INLINE void CySysClkWcoSetLowPowerMode(void) + { + /* Switch off auto low power mode in WCO */ + CY_SYS_CLK_WCO_CONFIG_REG &= ((uint32)~CY_SYS_CLK_WCO_CONFIG_LPM_AUTO); + + /* Change WCO trim register settings to LPM */ + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_XGM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_XGM_2250NA << CY_SYS_CLK_WCO_TRIM_XGM_SHIFT); + CY_SYS_CLK_WCO_TRIM_REG = (CY_SYS_CLK_WCO_TRIM_REG & (uint32)(~CY_SYS_CLK_WCO_TRIM_GM_MASK)) \ + | (uint32)(CY_SYS_CLK_WCO_TRIM_GM_LPM << CY_SYS_CLK_WCO_TRIM_GM_SHIFT); + + /* Switch on low power mode for WCO */ + CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_LPM_EN; + } + #endif /* (CY_IP_BLESS) */ + +#endif /* (CY_IP_WCO) */ + + +/* These defines are intended to maintain the backward compatibility for + * projects which use cy_boot_v4_20 or earlier. +*/ +#define CySysWdtWriteMode CySysWdtSetMode +#define CySysWdtReadMode CySysWdtGetMode +#define CySysWdtWriteClearOnMatch CySysWdtSetClearOnMatch +#define CySysWdtReadClearOnMatch CySysWdtGetClearOnMatch +#define CySysWdtReadEnabledStatus CySysWdtGetEnabledStatus +#define CySysWdtWriteCascade CySysWdtSetCascade +#define CySysWdtReadCascade CySysWdtGetCascade +#define CySysWdtWriteMatch CySysWdtSetMatch +#define CySysWdtWriteToggleBit CySysWdtSetToggleBit +#define CySysWdtReadToggleBit CySysWdtGetToggleBit +#define CySysWdtReadMatch CySysWdtGetMatch +#define CySysWdtReadCount CySysWdtGetCount +#define CySysWdtWriteIgnoreBits CySysWdtSetIgnoreBits +#define CySysWdtReadIgnoreBits CySysWdtGetIgnoreBits +#define CySysWdtSetIsrCallback CySysWdtSetInterruptCallback +#define CySysWdtGetIsrCallback CySysWdtGetInterruptCallback + +#endif /* (CY_LFCLK_CYLIB_H) */ + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/CyLib.c b/cores/asr650x/projects/PSoC4/CyLib.c new file mode 100644 index 00000000..75d52926 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/CyLib.c @@ -0,0 +1,3504 @@ +/***************************************************************************//** +* \file CyLib.c +* \version 5.70 +* +* \brief Provides a system API for the Clocking, Interrupts, SysTick, and +* Voltage Detect. +* +* \note Documentation of the API's in this file is located in the PSoC 4 System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2010-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyLib.h" + +/* CySysClkWriteImoFreq() || CySysClkImoEnableWcoLock() */ +#if ((CY_IP_SRSSV2 && CY_IP_FMLT) || CY_IP_IMO_TRIMMABLE_BY_WCO) + #include "CyFlash.h" +#endif /* (CY_IP_SRSSV2 && CY_IP_FMLT) */ + +/* Do not use these definitions directly in your application */ +uint32 cydelayFreqHz = CYDEV_BCLK__SYSCLK__HZ; +uint32 cydelayFreqKhz = (CYDEV_BCLK__SYSCLK__HZ + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; +uint8 cydelayFreqMhz = (uint8)((CYDEV_BCLK__SYSCLK__HZ + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); +uint32 cydelay32kMs = CY_DELAY_MS_OVERFLOW * ((CYDEV_BCLK__SYSCLK__HZ + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD); + + +static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS]; +static void CySysTickServiceCallbacks(void); + +#if (CY_IP_PLL) + static uint32 CySysClkPllGetBypassMode(uint32 pll); + static cystatus CySysClkPllConfigChangeAllowed(uint32 pll); +#endif /* (CY_IP_PLL) */ + + +/***************************************************************************//** +* Indicates whether or not the SysTick has been initialized. The variable is +* initialized to 0 and set to 1 the first time CySysTickStart() is called. +* +* This allows the component to restart without reinitialization after the first +* call to the CySysTickStart() routine. +* +* If reinitialization of the SysTick is required, call CySysTickInit() before +* calling CySysTickStart(). Alternatively, the SysTick can be reinitialized by +* calling the CySysTickInit() and CySysTickEnable() functions. +*******************************************************************************/ +uint32 CySysTickInitVar = 0u; + + +#if(CY_IP_SRSSV2) + /* Conversion between CySysClkWriteImoFreq() parameter and register's value */ + const uint8 cyImoFreqMhz2Reg[CY_SYS_CLK_IMO_FREQ_TABLE_SIZE] = { + /* 3 MHz */ 0x03u, /* 4 MHz */ 0x04u, /* 5 MHz */ 0x05u, /* 6 MHz */ 0x06u, + /* 7 MHz */ 0x07u, /* 8 MHz */ 0x08u, /* 9 MHz */ 0x09u, /* 10 MHz */ 0x0Au, + /* 11 MHz */ 0x0Bu, /* 12 MHz */ 0x0Cu, /* 13 MHz */ 0x0Eu, /* 14 MHz */ 0x0Fu, + /* 15 MHz */ 0x10u, /* 16 MHz */ 0x11u, /* 17 MHz */ 0x12u, /* 18 MHz */ 0x13u, + /* 19 MHz */ 0x14u, /* 20 MHz */ 0x15u, /* 21 MHz */ 0x16u, /* 22 MHz */ 0x17u, + /* 23 MHz */ 0x18u, /* 24 MHz */ 0x19u, /* 25 MHz */ 0x1Bu, /* 26 MHz */ 0x1Cu, + /* 27 MHz */ 0x1Du, /* 28 MHz */ 0x1Eu, /* 29 MHz */ 0x1Fu, /* 30 MHz */ 0x20u, + /* 31 MHz */ 0x21u, /* 32 MHz */ 0x22u, /* 33 MHz */ 0x23u, /* 34 MHz */ 0x25u, + /* 35 MHz */ 0x26u, /* 36 MHz */ 0x27u, /* 37 MHz */ 0x28u, /* 38 MHz */ 0x29u, + /* 39 MHz */ 0x2Au, /* 40 MHz */ 0x2Bu, /* 41 MHz */ 0x2Eu, /* 42 MHz */ 0x2Fu, + /* 43 MHz */ 0x30u, /* 44 MHz */ 0x31u, /* 45 MHz */ 0x32u, /* 46 MHz */ 0x33u, + /* 47 MHz */ 0x34u, /* 48 MHz */ 0x35u }; +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + /* Conversion between IMO frequency and WCO DPLL max offset steps */ + const uint8 cyImoFreqMhz2DpllOffset[CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_SIZE] = { + /* 26 MHz */ 238u, /* 27 MHz */ 219u, /* 28 MHz */ 201u, /* 29 MHz */ 185u, + /* 30 MHz */ 170u, /* 31 MHz */ 155u, /* 32 MHz */ 142u, /* 33 MHz */ 130u, + /* 34 MHz */ 118u, /* 35 MHz */ 107u, /* 36 MHz */ 96u, /* 37 MHz */ 86u, + /* 38 MHz */ 77u, /* 39 MHz */ 68u, /* 40 MHz */ 59u, /* 41 MHz */ 51u, + /* 42 MHz */ 44u, /* 43 MHz */ 36u, /* 44 MHz */ 29u, /* 45 MHz */ 23u, + /* 46 MHz */ 16u, /* 47 MHz */ 10u, /* 48 MHz */ 4u }; +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + +/* Stored CY_SYS_CLK_IMO_TRIM4_REG when modified for USB lock */ +#if (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSV2) + uint32 CySysClkImoTrim4 = 0u; + uint32 CySysClkImoTrim5 = 0u; +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSV2) */ + +/* Stored PUMP_SEL configuration during disable (IMO output by default) */ +uint32 CySysClkPumpConfig = CY_SYS_CLK_PUMP_ENABLE; + +/******************************************************************************* +* Function Name: CySysClkImoStart +****************************************************************************//** +* +* Enables the IMO. +* +* For PSoC 4100M / PSoC 4200M / PSoC 4000S / PSoC 4100S / PSoC Analog +* Coprocessor devices, this function will also enable WCO lock if selected in +* the Design Wide Resources tab. +* +* For PSoC 4200L devices, this function will also enable USB lock if selected +* in the Design Wide Resources tab. +* +*******************************************************************************/ +void CySysClkImoStart(void) +{ + CY_SYS_CLK_IMO_CONFIG_REG |= CY_SYS_CLK_IMO_CONFIG_ENABLE; + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + #if (CYDEV_IMO_TRIMMED_BY_WCO == 1u) + CySysClkImoEnableWcoLock(); + #endif /* (CYDEV_IMO_TRIMMED_BY_WCO == 1u) */ + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + #if (CYDEV_IMO_TRIMMED_BY_USB == 1u) + CySysClkImoEnableUsbLock(); + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 1u) */ + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +} + + +/******************************************************************************* +* Function Name: CySysClkImoStop +****************************************************************************//** +* +* Disables the IMO. +* +* For PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / +* PSoC Analog Coprocessor devices, this function will also disable WCO lock. +* +* For PSoC PSoC 4200L devices, this function will also disable USB lock. +* +*******************************************************************************/ +void CySysClkImoStop(void) +{ + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + CySysClkImoDisableWcoLock(); + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + CySysClkImoDisableUsbLock(); + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + CY_SYS_CLK_IMO_CONFIG_REG &= ( uint32 ) ( ~( uint32 )CY_SYS_CLK_IMO_CONFIG_ENABLE); +} + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + + /******************************************************************************* + * Function Name: CySysClkImoEnableWcoLock + ****************************************************************************//** + * + * Enables the IMO to WCO lock feature. This function works only if the WCO is + * already enabled. If the WCO is not enabled then this function returns + * without enabling the lock feature. + * + * It takes up to 20 ms for the IMO to stabilize. The delay is implemented with + * CyDelay() function. The delay interval is measured based on the system + * frequency defined by PSoC Creator at build time. If System clock frequency + * is changed in runtime, the CyDelayFreq() with the appropriate parameter + * should be called. + * + * For PSoC 4200L devices, note that the IMO can lock to either WCO or USB + * but not both. + * + * This function is applicable for PSoC 4100M / PSoC 4200M / PSoC 4000S / + * PSoC 4100S / PSoC Analog Coprocessor / PSoC 4200L. + * + *******************************************************************************/ + void CySysClkImoEnableWcoLock(void) + { + #if(CY_IP_SRSSV2) + uint32 i; + #endif /* (CY_IP_SRSSV2) */ + + uint32 freq; + uint8 interruptState; + uint32 regTmp; + uint32 lfLimit = 0u; + volatile uint32 flashCtlReg; + + if (0u != CySysClkWcoEnabled()) + { + interruptState = CyEnterCriticalSection(); + + /* Set oscillator interface control port to WCO */ + #if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + CY_SYS_CLK_OSCINTF_CTL_REG = + (CY_SYS_CLK_OSCINTF_CTL_REG & (uint32) ~CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_MASK) | + CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_WCO; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + /* Get current IMO frequency based on the register value */ + #if(CY_IP_SRSSV2) + freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ; + for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + { + if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreqMhz2Reg[i]) + { + freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + break; + } + } + #else + /* Calculate frequency by shifting register field value and adding constant. */ + #if(CY_IP_SRSSLT) + freq = (((uint32) ((CY_SYS_CLK_IMO_SELECT_REG & ((uint32) CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) << + CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT) + CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> + ((CY_SYS_CLK_SELECT_REG >> CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT) & + (uint32) CY_SYS_CLK_SELECT_HFCLK_DIV_MASK)); + #else + freq = ((uint32) ((CY_SYS_CLK_IMO_SELECT_REG & ((uint32) CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) << + CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT) + CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + #endif /* (CY_IP_SRSSLT) */ + + #endif /* (CY_IP_SRSSV2) */ + + /* For the WCO locking mode, the IMO gain needs to be CY_SYS_CLK_IMO_TRIM4_GAIN */ + #if(CY_IP_SRSSV2) + if ((CY_SYS_CLK_IMO_TRIM4_REG & CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) == 0u) + { + CY_SYS_CLK_IMO_TRIM4_REG = (CY_SYS_CLK_IMO_TRIM4_REG & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + CY_SYS_CLK_IMO_TRIM4_WCO_GAIN; + } + #endif /* (CY_IP_SRSSV2) */ + + regTmp = CY_SYS_CLK_WCO_DPLL_REG & ~(CY_SYS_CLK_WCO_DPLL_MULT_MASK | + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_MASK | + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_MASK | + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MASK); + + /* Set multiplier to determine IMO frequency in multiples of the WCO frequency */ + regTmp |= (CY_SYS_CLK_WCO_DPLL_MULT_VALUE(freq) & CY_SYS_CLK_WCO_DPLL_MULT_MASK); + + /* Set DPLL Loop Filter Integral and Proportional Gains Setting */ + regTmp |= (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN | CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN); + + /* Set maximum allowed IMO offset */ + if (freq < CY_SYS_CLK_IMO_FREQ_WCO_DPLL_SAFE_POINT) + { + regTmp |= (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT); + } + else + { + lfLimit = (uint32) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) + + cyImoFreqMhz2DpllOffset[freq - CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_OFFSET]; + + lfLimit = (lfLimit > CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX) ? + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX : lfLimit; + + regTmp |= (lfLimit << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT); + } + + CY_SYS_CLK_WCO_DPLL_REG = regTmp; + + flashCtlReg = CY_FLASH_CTL_REG; + CySysFlashSetWaitCycles(CY_SYS_CLK_IMO_MAX_FREQ_MHZ); + CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE; + CyDelay(CY_SYS_CLK_WCO_IMO_TIMEOUT_MS); + CY_FLASH_CTL_REG = flashCtlReg; + + CyExitCriticalSection(interruptState); + } + } + + + /******************************************************************************* + * Function Name: CySysClkImoDisableWcoLock + ****************************************************************************//** + * + * Disables the IMO to WCO lock feature. + * + * For PSoC 4200L devices, note that the IMO can lock to either WCO or USB + * but not both. + * + * This function is applicable for PSoC 4100M / PSoC 4200M / PSoC 4000S / + * PSoC 4100S / PSoC Analog Coprocessor / PSoC 4200L. + * + *******************************************************************************/ + void CySysClkImoDisableWcoLock(void) + { + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE; + } + + + /******************************************************************************* + * Function Name: CySysClkImoGetWcoLock + ****************************************************************************//** + * + * Reports the IMO to WCO lock enable state. + * + * This function is applicable for PSoC 4100M / PSoC 4200M / PSoC 4000S / + * PSoC 4100S / PSoC Analog Coprocessor / PSoC 4200L. + * + * \return 1 if IMO to WCO lock is enabled. + * \return 0 if IMO to WCO lock is disabled. + * + *******************************************************************************/ + uint32 CySysClkImoGetWcoLock(void) + { + return ((0u != (CY_SYS_CLK_WCO_CONFIG_REG & CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE)) ? + (uint32) 1u : + (uint32) 0u); + } + +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + +#if (CY_IP_IMO_TRIMMABLE_BY_USB) + + /******************************************************************************* + * Function Name: CySysClkImoEnableUsbLock + ****************************************************************************//** + * + * Enables the IMO to USB lock feature. + * + * This function must be called before CySysClkWriteImoFreq(). + * + * This function is called from CySysClkImoStart() function if USB lock + * selected in the Design Wide Resources tab. + * + * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + * devices, the IMO can lock to either WCO or USB, but not both. + * + *******************************************************************************/ + void CySysClkImoEnableUsbLock(void) + { + #if(CY_IP_SRSSV2) + uint32 i; + + /* Check for new trim algorithm */ + uint32 CySysClkUsbCuSortTrim = ((CY_SFLASH_S1_TESTPGM_OLD_REV < (CY_SFLASH_S1_TESTPGM_REV_REG & + CY_SFLASH_S1_TESTPGM_REV_MASK)) ? 1u : 0u); + + /* Get current IMO frequency based on the register value */ + uint32 freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ; + + for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + { + if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreqMhz2Reg[i]) + { + freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + break; + } + } + #endif /* (CY_IP_SRSSV2) */ + + /* Set oscillator interface control port to USB */ + #if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + CY_SYS_CLK_OSCINTF_CTL_REG = (CY_SYS_CLK_OSCINTF_CTL_REG & (uint32) ~CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_MASK) | + CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_USB; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + #if(CY_IP_SRSSV2) + + /* Save CY_SYS_CLK_IMO_TRIM4_REG and set IMO gain for USB lock */ + CySysClkImoTrim4 = CY_SYS_CLK_IMO_TRIM4_REG; + + if(0u != CySysClkUsbCuSortTrim) + { + CySysClkImoTrim5 = CY_PWR_BG_TRIM5_REG; + + CY_SYS_CLK_IMO_TRIM4_REG = (CySysClkImoTrim4 & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + CY_SFLASH_USBMODE_IMO_GAIN_TRIM_REG; + CY_PWR_BG_TRIM5_REG = CY_SFLASH_USBMODE_IMO_TEMPCO_REG; + + } + else + { + CY_SYS_CLK_IMO_TRIM4_REG = (CySysClkImoTrim4 & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + CY_SYS_CLK_IMO_TRIM4_USB_GAIN; + + } + + if (48u == freq) + { + CY_SYS_CLK_IMO_TRIM1_REG = (0u != CySysClkUsbCuSortTrim) ? + (uint32)CY_SFLASH_CU_IMO_TRIM_USBMODE_48_REG : + (uint32)CY_SFLASH_IMO_TRIM_USBMODE_48_REG; + } + else if (24u == freq) + { + CY_SYS_CLK_IMO_TRIM1_REG = (0u != CySysClkUsbCuSortTrim) ? + (uint32)CY_SFLASH_CU_IMO_TRIM_USBMODE_24_REG : + (uint32)CY_SFLASH_IMO_TRIM_USBMODE_24_REG; + } + else + { + /* Do nothing */ + } + + #endif /* (CY_IP_SRSSV2) */ + + CY_SYS_CLK_USBDEVv2_CR1_REG |= CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK; + } + + + /******************************************************************************* + * Function Name: CySysClkImoDisableUsbLock + ****************************************************************************//** + * + * Disables the IMO to USB lock feature. + * + * This function is called from CySysClkImoStop() function if USB lock selected + * in the Design Wide Resources tab. + * + * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + * devices, the IMO can lock to either WCO or USB, but not both. + * + *******************************************************************************/ + void CySysClkImoDisableUsbLock(void) + { + #if(CY_IP_SRSSV2) + uint32 i; + + /* Check for new trim algorithm */ + uint32 CySysClkUsbCuSortTrim = ((CY_SFLASH_S1_TESTPGM_OLD_REV < (CY_SFLASH_S1_TESTPGM_REV_REG & + CY_SFLASH_S1_TESTPGM_REV_MASK)) ? 1u : 0u); + + /* Get current IMO frequency based on the register value */ + uint32 freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ;; + + for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + { + if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreqMhz2Reg[i]) + { + freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + break; + } + } + #endif /* (CY_IP_SRSSV2) */ + + CY_SYS_CLK_USBDEVv2_CR1_REG &= (uint32) ~CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK; + + #if(CY_IP_SRSSV2) + /* Restore CY_SYS_CLK_IMO_TRIM4_REG */ + CY_SYS_CLK_IMO_TRIM4_REG = ((CY_SYS_CLK_IMO_TRIM4_REG & (uint32) ~CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) | + (CySysClkImoTrim4 & CY_SYS_CLK_IMO_TRIM4_GAIN_MASK)); + + if(0u != CySysClkUsbCuSortTrim) + { + CY_PWR_BG_TRIM5_REG = CySysClkImoTrim5; + } + + CY_SYS_CLK_IMO_TRIM1_REG = CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET); + + #endif /* (CY_IP_SRSSV2) */ + } + + + /******************************************************************************* + * Function Name: CySysClkImoGetUsbLock + ****************************************************************************//** + * + * Reports the IMO to USB lock enable state. + * + * This is applicable for PSoC 4200L family of devices only. For PSoC 4200L + * devices, the IMO can lock to either WCO or USB, but not both. + * + * \return 1 if IMO to USB lock is enabled. + * \return 0 if IMO to USB lock is disabled. + * + *******************************************************************************/ + uint32 CySysClkImoGetUsbLock(void) + { + return ((0u != (CY_SYS_CLK_USBDEVv2_CR1_REG & CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK)) ? + (uint32) 1u : + (uint32) 0u); + } +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + + +/******************************************************************************* +* Function Name: CySysClkWriteHfclkDirect +****************************************************************************//** +* +* Selects the direct source for the HFCLK. +* +* The new source must be running and stable before calling this function. +* +* PSoC 4000: +* The SYSCLK has a maximum speed of 16 MHz, so HFCLK and SYSCLK dividers should +* be selected in a way to not to exceed 16 MHz for the System clock. +* +* If the SYSCLK clock frequency increases during device operation, call +* CySysFlashSetWaitCycles() with the appropriate parameter to adjust the number +* of clock cycles the cache will wait before sampling data comes back from +* Flash. If the SYSCLK clock frequency decreases, you can call +* CySysFlashSetWaitCycles() to improve the CPU performance. See +* CySysFlashSetWaitCycles() description for more information. +* +* Do not select PLL as the source for HFCLK if PLL output frequency exceeds +* maximum permissible value for HFCLK. +* +* \param clkSelect One of the available HFCLK direct sources. +* CY_SYS_CLK_HFCLK_IMO IMO. +* CY_SYS_CLK_HFCLK_EXTCLK External clock pin. +* CY_SYS_CLK_HFCLK_ECO External crystal oscillator. Applicable for +* PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4200L / +* 4100S with ECO. +* CY_SYS_CLK_HFCLK_PLL0 PLL#0. Applicable for PSoC 4200L / +* 4100S with PLL. +* CY_SYS_CLK_HFCLK_PLL1 PLL#1. Applicable for PSoC 4200L. +* +*******************************************************************************/ +void CySysClkWriteHfclkDirect(uint32 clkSelect) +{ + uint8 interruptState; + uint32 tmpReg; + + #if (CY_IP_SRSSLT && CY_IP_PLL) + uint8 i = 0u; + #endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + + interruptState = CyEnterCriticalSection(); + +#if (CY_IP_SRSSLT && CY_IP_PLL) + if ((CY_SYS_CLK_HFCLK_PLL0 == clkSelect) || (CY_SYS_CLK_HFCLK_ECO == clkSelect)) + { + tmpReg = CY_SYS_CLK_SELECT_REG & ~CY_SYS_CLK_SELECT_DIRECT_SEL_MASK; + tmpReg |= CY_SYS_CLK_HFCLK_IMO; + CY_SYS_CLK_SELECT_REG = tmpReg; + + /* SRSSLT block does not have registers to select PLL. It is part of EXCO */ + tmpReg = CY_SYS_ECO_CLK_SELECT_REG & ~CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK; + tmpReg |= ((clkSelect & CY_SYS_CLK_SELECT_HFCLK_SEL_PLL_MASK) >> CY_SYS_CLK_SELECT_HFCLK_PLL_SHIFT); + CY_SYS_ECO_CLK_SELECT_REG = tmpReg; + + /* Generate clock sequence to change clock source in CY_SYS_ECO_CLK_SELECT_REG */ + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + + for(i = 0u; i < CY_SYS_EXCO_PGM_CLK_SEQ_GENERATOR; i++) + { + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + } + + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + } +#endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + + tmpReg = CY_SYS_CLK_SELECT_REG & ~(CY_SYS_CLK_SELECT_DIRECT_SEL_MASK | + CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + +#if (CY_IP_SRSSV2 && CY_IP_PLL) + if ((CY_SYS_CLK_HFCLK_PLL0 == clkSelect) || (CY_SYS_CLK_HFCLK_PLL1 == clkSelect)) + { + tmpReg |= (clkSelect & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + } + else +#endif /* (CY_IP_SRSSV2 && CY_IP_PLL) */ + { + tmpReg |= (clkSelect & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + } + + CY_SYS_CLK_SELECT_REG = tmpReg; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySysEnablePumpClock +****************************************************************************//** +* +* Enables / disables the pump clock. +* +* \param enable +* CY_SYS_CLK_PUMP_DISABLE - Disables the pump clock +* CY_SYS_CLK_PUMP_ENABLE - Enables and restores the operating source of +* the pump clock. +* +* \sideeffect +* Enabling/disabling the pump clock does not guarantee glitch free operation +* when changing the IMO parameters or clock divider settings. +* +*******************************************************************************/ +void CySysEnablePumpClock(uint32 enable) +{ + #if(CY_IP_SRSSV2) + if (0u != (CY_SYS_CLK_PUMP_ENABLE & enable)) + { + CY_SYS_CLK_IMO_CONFIG_REG |= (CySysClkPumpConfig << CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT); + } + else + { + CySysClkPumpConfig = (CY_SYS_CLK_IMO_CONFIG_REG >> CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT) & + CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK; + CY_SYS_CLK_IMO_CONFIG_REG &= ~(CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK << CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT); + } + #else /* CY_IP_SRSSLT */ + if (0u != (CY_SYS_CLK_PUMP_ENABLE & enable)) + { + CY_SYS_CLK_SELECT_REG |= (CySysClkPumpConfig << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT); + } + else + { + CySysClkPumpConfig = (CY_SYS_CLK_SELECT_REG >> CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT) & + CY_SYS_CLK_SELECT_PUMP_SEL_MASK; + CY_SYS_CLK_SELECT_REG &= ~(CY_SYS_CLK_SELECT_PUMP_SEL_MASK << CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT); + } + #endif /* (CY_IP_SRSSV2) */ +} + + +/******************************************************************************* +* Function Name: CySysClkGetSysclkSource +****************************************************************************//** +* +* Returns the source of the System clock. +* +* \return The same as \ref CySysClkWriteHfclkDirect() function parameters. +* +*******************************************************************************/ +uint32 CySysClkGetSysclkSource(void) +{ + uint8 interruptState; + uint32 sysclkSource; + + interruptState = CyEnterCriticalSection(); + +#if (CY_IP_SRSSV2 && CY_IP_PLL) + if ((CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK) != 0u) + { + sysclkSource = (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_HFCLK_SEL_MASK); + } + else +#endif /* (CY_IP_SRSSV2 && CY_IP_PLL) */ + { + sysclkSource = (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + + #if (CY_IP_SRSSLT && CY_IP_PLL) + sysclkSource |= (((uint32)(CY_SYS_ECO_CLK_SELECT_REG & CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK)) << + CY_SYS_CLK_SELECT_HFCLK_PLL_SHIFT); + #endif /* (CY_IP_SRSSLT && CY_IP_PLL) */ + + } + + CyExitCriticalSection(interruptState); + + return (sysclkSource); +} + + +/******************************************************************************* +* Function Name: CySysClkWriteSysclkDiv +****************************************************************************//** +* +* Selects the prescaler divide amount for SYSCLK from HFCLK. +* +* PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers +* should be selected in a way, not to exceed 16 MHz for SYSCLK. +* +* PSoC 4100 \ PSoC 4100 BLE \ PSoC 4100M: The SYSCLK has the speed of 24 MHz, +* so HFCLK and SYSCLK dividers should be selected in a way, not to exceed 24 MHz +* for SYSCLK. +* +* If the SYSCLK clock frequency increases during the device operation, call +* \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the +* number of clock cycles the cache will wait before sampling data comes back +* from Flash. If the SYSCLK clock frequency decreases, you can call +* \ref CySysFlashSetWaitCycles() to improve the CPU performance. See +* \ref CySysFlashSetWaitCycles() description for more information. +* +* \param divider Power of 2 prescaler selection +* CY_SYS_CLK_SYSCLK_DIV1 SYSCLK = HFCLK / 1 +* CY_SYS_CLK_SYSCLK_DIV2 SYSCLK = HFCLK / 2 +* CY_SYS_CLK_SYSCLK_DIV4 SYSCLK = HFCLK / 4 +* CY_SYS_CLK_SYSCLK_DIV8 SYSCLK = HFCLK / 8 +* CY_SYS_CLK_SYSCLK_DIV16 SYSCLK = HFCLK / 16 (N/A for 4000 Family) +* CY_SYS_CLK_SYSCLK_DIV32 SYSCLK = HFCLK / 32 (N/A for 4000 Family) +* CY_SYS_CLK_SYSCLK_DIV64 SYSCLK = HFCLK / 64 (N/A for 4000 Family) +* CY_SYS_CLK_SYSCLK_DIV128 SYSCLK = HFCLK / 128 (N/A for 4000 Family) +* +*******************************************************************************/ +void CySysClkWriteSysclkDiv(uint32 divider) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_SELECT_REG = ((uint32)(((uint32)divider & CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK) << + CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT)) | + (CY_SYS_CLK_SELECT_REG & ((uint32)(~(uint32)(CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK << + CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT)))); + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySysClkWriteImoFreq +****************************************************************************//** +* +* Sets the frequency of the IMO. +* +* PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers +* should be selected in a way, not to exceed 16 MHz for SYSCLK. +* +* PSoC 4100 \ PSoC 4100 BLE \ PSoC 4100M: The SYSCLK has the speed of 24 MHz, +* so HFCLK and SYSCLK dividers should be selected in a way, not to exceed 24 MHz +* for SYSCLK. +* +* For PSoC 4200M and PSoC 4200L device families, if WCO lock feature is enabled +* then this API will disable the lock, write the new IMO frequency and then +* re-enable the lock. +* +* For PSoC 4200L device families, this function enables the USB lock when 24 or +* 48 MHz passed as a parameter if the USB lock option is enabled in Design Wide +* Resources tab or CySysClkImoEnableUsbLock() was called before. Note the USB +* lock is disabled during IMO frequency change. +* +* The CPU is halted if new frequency is invalid and project is compiled +* in debug mode. +* +* If the SYSCLK clock frequency increases during the device operation, call +* \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the +* number of clock cycles the cache will wait before sampling data comes back +* from Flash. If the SYSCLK clock frequency decreases, you can call +* \ref CySysFlashSetWaitCycles() to improve the CPU performance. See +* \ref CySysFlashSetWaitCycles() description for more information. +* +* PSoC 4000: The System Clock (SYSCLK) has maximum speed of 16 MHz, so HFCLK +* and SYSCLK dividers should be selected in a way, to not to exceed 16 MHz for +* the System clock. +* +* \param freq All PSoC 4 families excluding the following: Valid range [3-48] +* with step size equals 1. PSoC 4000: Valid values are 24, 32, and 48. +* PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor: Valid range [24-48] with +* step size equals 4. +* +*******************************************************************************/ +#if(CY_IP_SRSSV2) + void CySysClkWriteImoFreq(uint32 freq) + { + #if (CY_IP_FMLT) + volatile uint32 parameters[2u]; + volatile uint32 regValues[4u]; + #else + uint8 bgTrim4; + uint8 bgTrim5; + uint8 newImoTrim2Value; + uint8 currentImoTrim2Value; + #endif /* (CY_IP_FM) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + uint32 wcoLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + uint32 usbLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + uint8 interruptState; + + + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if(0u != CySysClkImoGetWcoLock()) + { + wcoLock = 1u; + CySysClkImoDisableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + if(0u != CySysClkImoGetUsbLock()) + { + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + if ((24u == freq) || (48u == freq)) + { + usbLock = 1u; + CySysClkImoDisableUsbLock(); + } + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + } + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + + #if (CY_IP_FMLT) + + /* FM-Lite Clock Restore */ + regValues[0u] = CY_SYS_CLK_IMO_CONFIG_REG; + regValues[1u] = CY_SYS_CLK_SELECT_REG; + regValues[2u] = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + regValues[3u] = CY_FLASH_CTL_REG; + + parameters[0u] = + (uint32) ((CY_FLASH_KEY_TWO(CY_FLASH_API_OPCODE_CLK_RESTORE) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | + CY_FLASH_KEY_ONE); + parameters[1u] = (uint32) ®Values[0u]; + + CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u]; + CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | CY_FLASH_API_OPCODE_CLK_RESTORE; + (void) CY_FLASH_CPUSS_SYSARG_REG; + + #else /* (CY_IP_FM) */ + + if ((freq >= CY_SYS_CLK_IMO_MIN_FREQ_MHZ) && (freq <= CY_SYS_CLK_IMO_MAX_FREQ_MHZ)) + { + if(freq <= CY_SFLASH_IMO_MAXF0_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS0_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO0_REG; + } + else if(freq <= CY_SFLASH_IMO_MAXF1_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS1_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO1_REG; + } + else if(freq <= CY_SFLASH_IMO_MAXF2_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS2_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO2_REG; + } + else if(freq <= CY_SFLASH_IMO_MAXF3_REG) + { + bgTrim4 = CY_SFLASH_IMO_ABS3_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO3_REG; + } + else + { + bgTrim4 = CY_SFLASH_IMO_ABS4_REG; + bgTrim5 = CY_SFLASH_IMO_TMPCO4_REG; + } + + /* Get IMO_TRIM2 value for the new frequency */ + newImoTrim2Value = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + + + /**************************************************************************** + * The IMO can have a different trim per frequency. To avoid possible corner + * cases where a trim change can exceed the maximum frequency, the trim must + * be applied at a frequency that is low enough. + * + * Comparing IMO_TRIM2 values for the current and new frequencies, since + * IMO_TRIM2 value as a function of IMO frequency is a strictly increasing + * function and is time-invariant. + ***************************************************************************/ + if ((newImoTrim2Value >= CY_SYS_CLK_IMO_BOUNDARY_FREQ_TRIM2) && (freq >= CY_SYS_CLK_IMO_BOUNDARY_FREQ_MHZ)) + { + /* Set boundary IMO frequency: safe for IMO above 48 MHZ trimming */ + CY_SYS_CLK_IMO_TRIM2_REG = (uint32) cyImoFreqMhz2Reg[CY_SYS_CLK_IMO_TEMP_FREQ_MHZ - + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + + CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + + currentImoTrim2Value = CY_SYS_CLK_IMO_TEMP_FREQ_TRIM2; + } + else + { + currentImoTrim2Value = (uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK); + } + + + /*************************************************************************** + * A trim change needs to be allowed to settle (within 5us) before the Freq + * can be changed to a new frequency. + * + * Comparing IMO_TRIM2 values for the current and new frequencies, since + * IMO_TRIM2 value as a function of IMO frequency is a strictly increasing + * function and is time-invariant. + ***************************************************************************/ + if (newImoTrim2Value < currentImoTrim2Value) + { + /* Set new IMO frequency */ + CY_SYS_CLK_IMO_TRIM2_REG = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + } + + /* Set trims for the new IMO frequency */ + CY_SYS_CLK_IMO_TRIM1_REG = (uint32) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET); + CY_PWR_BG_TRIM4_REG = bgTrim4; + CY_PWR_BG_TRIM5_REG = bgTrim5; + CyDelayUs(CY_SYS_CLK_IMO_TRIM_TIMEOUT_US); + + if (newImoTrim2Value > currentImoTrim2Value) + { + /* Set new IMO frequency */ + CY_SYS_CLK_IMO_TRIM2_REG = cyImoFreqMhz2Reg[freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET]; + CyDelayCycles(CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES); + } + } + else + { + /* Halt CPU in debug mode if new frequency is invalid */ + CYASSERT(0u != 0u); + } + + #endif /* (CY_IP_FMLT) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if (1u == wcoLock) + { + CySysClkImoEnableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + if (1u == usbLock) + { + CySysClkImoEnableUsbLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + CyExitCriticalSection(interruptState); + } + +#else + + void CySysClkWriteImoFreq(uint32 freq) + { + uint8 interruptState; + uint8 imoTrim1Value; + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + uint32 wcoLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + uint32 usbLock = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + #if (CY_PSOC4_4000) + if ((freq == 24u) || (freq == 32u) || (freq == 48u)) + #elif (CY_CCG3) + if ((freq == 24u) || (freq == 36u) || (freq == 48u)) + #else + if ((freq == 24u) || (freq == 28u) || (freq == 32u) || + (freq == 36u) || (freq == 40u) || (freq == 44u) || + (freq == 48u)) + #endif /* (CY_PSOC4_4000) */ + { + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if(0u != CySysClkImoGetWcoLock()) + { + wcoLock = 1u; + CySysClkImoDisableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + if(0u != CySysClkImoGetUsbLock()) + { + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + if (48u == freq) + { + usbLock = 1u; + CySysClkImoDisableUsbLock(); + } + + #if (CYDEV_IMO_TRIMMED_BY_USB == 0u) + } + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + #endif /* (CYDEV_IMO_TRIMMED_BY_USB == 0u) */ + + + /* Set IMO to 24 MHz - CLK_IMO_SELECT.FREQ = 0 */ + CY_SYS_CLK_IMO_SELECT_REG &= ((uint32) ~CY_SYS_CLK_IMO_SELECT_FREQ_MASK); + + + /* Apply coarse trim */ + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + if ((1u == usbLock) && (48u == freq)) + { + imoTrim1Value = CY_SFLASH_IMO_TRIM_USBMODE_48_REG; + } + else if ((1u == usbLock) && (24u == freq)) + { + imoTrim1Value = CY_SFLASH_IMO_TRIM_USBMODE_24_REG; + } + else + { + imoTrim1Value = (uint8) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + } + #else + imoTrim1Value = (uint8) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + CY_SYS_CLK_IMO_TRIM1_REG = (uint32) imoTrim1Value; + + /* Zero out fine trim */ + CY_SYS_CLK_IMO_TRIM2_REG = CY_SYS_CLK_IMO_TRIM2_REG & ((uint32) ~CY_SYS_CLK_IMO_TRIM2_FSOFFSET_MASK); + + /* Apply TC trim */ + CY_SYS_CLK_IMO_TRIM3_REG = (CY_SYS_CLK_IMO_TRIM3_REG & ((uint32) ~CY_SYS_CLK_IMO_TRIM3_VALUES_MASK)) | + (CY_SFLASH_IMO_TCTRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) & CY_SYS_CLK_IMO_TRIM3_VALUES_MASK); + + CyDelayCycles(CY_SYS_CLK_IMO_TRIM_DELAY_CYCLES); + + if (freq > CY_SYS_CLK_IMO_MIN_FREQ_MHZ) + { + /* Select nearby intermediate frequency */ + CY_SYS_CLK_IMO_SELECT_REG = (CY_SYS_CLK_IMO_SELECT_REG & ((uint32) ~CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) | + (((freq - 4u - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> 2u) & CY_SYS_CLK_IMO_SELECT_FREQ_MASK); + + CyDelayCycles(CY_SYS_CLK_IMO_TRIM_DELAY_CYCLES); + + /* Make small step to final frequency */ + /* Select nearby intermediate frequency */ + CY_SYS_CLK_IMO_SELECT_REG = (CY_SYS_CLK_IMO_SELECT_REG & ((uint32) ~CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) | + (((freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> 2u) & CY_SYS_CLK_IMO_SELECT_FREQ_MASK); + } + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if (1u == wcoLock) + { + CySysClkImoEnableWcoLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + if (1u == usbLock) + { + CySysClkImoEnableUsbLock(); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + CyExitCriticalSection(interruptState); + } + else + { + /* Halt CPU in debug mode if new frequency is invalid */ + CYASSERT(0u != 0u); + } + } + +#endif /* (CY_IP_SRSSV2) */ + + +#if(CY_IP_SRSSLT) + /******************************************************************************* + * Function Name: CySysClkWriteHfclkDiv + ****************************************************************************//** + * + * Selects the pre-scaler divider value for HFCLK from IMO. + * + * The HFCLK predivider allows the device to divide the HFCLK selection mux + * input before use as HFCLK. The predivider is capable of dividing the HFCLK by + * powers of 2 between 1 and 8. + * + * PSoC 4000: The SYSCLK has the speed of 16 MHz, so HFCLK and SYSCLK dividers + * should be selected in a way, not to exceed 16 MHz for SYSCLK. + * + * If the SYSCLK clock frequency increases during the device operation, call + * \ref CySysFlashSetWaitCycles() with the appropriate parameter to adjust the + * number of clock cycles the cache will wait before sampling data comes back + * from Flash. If the SYSCLK clock frequency decreases, you can call + * \ref CySysFlashSetWaitCycles() to improve the CPU performance. See + * \ref CySysFlashSetWaitCycles() description for more information. + * + * \param \ref CY_SYS_CLK_HFCLK_DIV_NODIV Transparent mode (w/o dividing) + * \param \ref CY_SYS_CLK_HFCLK_DIV_2 Divide selected clock source by 2 + * \param \ref CY_SYS_CLK_HFCLK_DIV_4 Divide selected clock source by 4 + * \param \ref CY_SYS_CLK_HFCLK_DIV_8 Divide selected clock source by 8 + * + *******************************************************************************/ + void CySysClkWriteHfclkDiv(uint32 divider) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_SELECT_REG = ((CY_SYS_CLK_SELECT_REG & ((uint32) (~(CY_SYS_CLK_SELECT_HFCLK_DIV_MASK << + CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT)))) | + ((uint32)((divider & CY_SYS_CLK_SELECT_HFCLK_DIV_MASK) << CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT))); + + CyExitCriticalSection(interruptState); + } +#endif /* (CY_IP_SRSSLT) */ + + +#if (CY_IP_ECO) + + /******************************************************************************* + * Function Name: CySysClkEcoStart + ****************************************************************************//** + * + * Starts the External Crystal Oscillator (ECO). Refer to the device datasheet + * for the ECO startup time. + * + * The timeout interval is measured based on the system frequency defined by + * PSoC Creator at build time. If System clock frequency is changed in + * runtime, the \ref CyDelayFreq() with the appropriate parameter should be + * called. + * + * PSoC 4100 BLE / PSoC 4200 BLE: The WCO must be enabled prior to enabling ECO. + * + * \param timeoutUs Timeout in microseconds. + * + * If zero is specified, the function does not wait for timeout and returns + * CYRET_SUCCESS. If non-zero is specified, the function waits for the timeout. + * + * \return \ref CYRET_SUCCESS Completed successfully. The ECO is oscillating and + * amplitude reached 60% and it does not mean 24 MHz crystal is within 50 ppm. + * + * \return \ref CYRET_TIMEOUT Timeout occurred. If the crystal is not oscillating + * or amplitude didn't reach 60% after specified amount of time, CYRET_TIMEOUT + * is returned. + * + * \return \ref CYRET_BAD_PARAM One or more invalid parameters. + * + *******************************************************************************/ + cystatus CySysClkEcoStart(uint32 timeoutUs) + { + cystatus returnStatus = CYRET_SUCCESS; + + #if (CY_IP_ECO_BLESS) + /* Enable the RF oscillator band gap */ + CY_SYS_XTAL_BLESS_RF_CONFIG_REG |= CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE; + + /* Update trimming register */ + CY_SYS_XTAL_BLERD_BB_XO_REG = CY_SYS_XTAL_BLERD_BB_XO_TRIM; + + /* Enable the Crystal */ + CY_SYS_XTAL_BLERD_DBUS_REG |= CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE; + + #elif (CY_IP_ECO_BLESSV3) + uint32 regConfig; + uint32 intrRegMaskStore = 0u; + + if (0u != (CY_SYS_BLESS_MT_CFG_REG & (CY_SYS_BLESS_MT_CFG_ENABLE_BLERD << CYFLD_BLE_BLESS_ENABLE_BLERD__OFFSET))) + { + CY_SYS_BLESS_MT_CFG_REG |= (CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON << CYFLD_BLE_BLESS_DPSLP_ECO_ON__OFFSET); + } + else + { + /* Init BLE core */ + CY_SYS_BLESS_MT_DELAY_CFG_REG = CY_SYS_BLESS_MT_DELAY_CFG_INIT; + CY_SYS_BLESS_MT_DELAY_CFG2_REG = CY_SYS_BLESS_MT_DELAY_CFG2_INIT; + CY_SYS_BLESS_MT_DELAY_CFG3_REG = CY_SYS_BLESS_MT_DELAY_CFG3_INIT; + + /* RCB init */ + regConfig = CY_SYS_RCB_CTRL_REG; + regConfig &= CY_SYS_RCB_CTRL_CLEAR; + regConfig |= CY_SYS_RCB_CTRL_INIT; + CY_SYS_RCB_CTRL_REG = regConfig; + + intrRegMaskStore = CY_SYS_BLESS_INTR_MASK_REG; + if(0u != (CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG &= ~CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK; + } + + /* Enable BLE core */ + regConfig = CY_SYS_BLESS_MT_CFG_REG; + regConfig &= CY_SYS_BLESS_MT_CFG_CLEAR; + regConfig |= CY_SYS_BLESS_MT_CFG_INIT; + CY_SYS_BLESS_MT_CFG_REG = regConfig; + + while(0u == ((CY_SYS_BLESS_BLERD_ACTIVE_INTR_STAT & CY_SYS_BLESS_INTR_STAT_REG))) + { + /* Wait until BLERD55 moves to active state */ + } + + if(0u != (CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG |= CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK; + } + + /* Send write commands to RBUS */ + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_NRST_SET; + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_DIG_CLK_SET; + + #if (CY_SYS_BLE_CLK_ECO_FREQ_32MHZ == CYDEV_ECO_CLK_MHZ) + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_XTAL_DIV_SET; + CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET | CY_SYS_RCB_RBUS_IB_VAL); + #else + CY_SYS_RCB_TX_FIFO_WR_REG = CY_SYS_RCB_RBUS_FREQ_XTAL_NODIV_SET; + #endif + + intrRegMaskStore = CY_SYS_BLESS_INTR_MASK_REG; + if(0u != (CY_SYS_RCB_INTR_RCB_DONE & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG &= ~(CY_SYS_RCB_INTR_RCB_DONE | CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY); + } + + /* Send read commands to RBUS */ + CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RD_CMD | + (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET & ~CY_SYS_RCB_RBUS_VAL_MASK)); + + while (0u == (CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY & CY_SYS_RCB_INTR_REG)) + { + /* Wait until RX_FIFO_NOT_EMPTY state */ + } + + CY_SYS_RCB_INTR_REG |= CY_SYS_RCB_INTR_RCB_DONE; + + regConfig = CY_SYS_RCB_RX_FIFO_RD_REG & CY_SYS_RCB_RBUS_TRIM_MASK; + + /* Send write commands to RBUS */ + CY_SYS_RCB_TX_FIFO_WR_REG = (CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET | regConfig | CY_SYS_RCB_RBUS_TRIM_VAL); + + while (0u == (CY_SYS_RCB_INTR_RCB_DONE & CY_SYS_RCB_INTR_REG)) + { + /* Wait until RCB_DONE state */ + } + + /* Clear Interrupt */ + CY_SYS_RCB_INTR_REG = CY_SYS_RCB_INTR_CLEAR; + + if(0u != ((CY_SYS_RCB_INTR_RCB_DONE | CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY) & intrRegMaskStore)) + { + CY_SYS_BLESS_INTR_MASK_REG |= intrRegMaskStore; + } + + } + #else /* CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT */ + CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_ENABLE; + CyDelayUs(CY_SYS_CLK_ECO_CONFIG_CLK_EN_TIMEOUT_US); + CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_CLK_EN; + #endif /* (CY_IP_ECO_BLESS) */ + + if(timeoutUs > 0u) + { + returnStatus = CYRET_TIMEOUT; + + for( ; timeoutUs > 0u; timeoutUs--) + { + CyDelayUs(1u); + + if(0u != CySysClkEcoReadStatus()) + { + returnStatus = CYRET_SUCCESS; + break; + } + } + + } + + return(returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkEcoStop + ****************************************************************************//** + * + * Stops the megahertz crystal. + * + * If ECO is disabled when it is sourcing HFCLK, the CPU will halt. In addition, + * for PSoC 4100 BLE / PSoC 4200 BLE devices, the BLE sub-system will stop + * functioning. + * + *******************************************************************************/ + void CySysClkEcoStop(void) + { + #if (CY_IP_WCO_BLESS) + /* Disable the RF oscillator band gap */ + CY_SYS_XTAL_BLESS_RF_CONFIG_REG &= (uint32) ~CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE; + + /* Disable the Crystal */ + CY_SYS_XTAL_BLERD_DBUS_REG &= (uint32) ~CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE; + #elif (CY_IP_ECO_BLESSV3) + CY_SYS_BLESS_MT_CFG_REG &= ~(CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON << CYFLD_BLE_BLESS_DPSLP_ECO_ON__OFFSET); + #else + CY_SYS_CLK_ECO_CONFIG_REG &= (uint32) ~(CY_SYS_CLK_ECO_CONFIG_ENABLE | CY_SYS_CLK_ECO_CONFIG_CLK_EN); + #endif /* (CY_IP_WCO_BLESS) */ + } + + + /******************************************************************************* + * Function Name: CySysClkEcoReadStatus + ****************************************************************************//** + * + * Reads the status bit for the megahertz crystal. + * + * For PSoC 4100 BLE / PSoC 4200 BLE devices, the status bit is the + * XO_AMP_DETECT bit in FSM register. + * + * For PSoC 4200L / 4100S with ECO devices, the error status bit is the + * WATCHDOG_ERROR bit in ECO_STATUS register. + * + * \return PSoC 4100 BLE/PSoC 4200 BLE: Non-zero indicates that ECO output + * reached 50 ppm and is oscillating in valid range. + * + * \return PSoC 4200L / 4100S with ECO: Non-zero indicates that ECO is running. + * + *******************************************************************************/ + uint32 CySysClkEcoReadStatus(void) + { + uint32 returnValue; + + #if (CY_IP_WCO_BLESS) + returnValue = CY_SYS_XTAL_BLERD_FSM_REG & CY_SYS_XTAL_BLERD_FSM_XO_AMP_DETECT; + #elif (CY_IP_ECO_BLESSV3) + returnValue = (CY_SYS_BLESS_MT_STATUS_REG & CY_SYS_BLESS_MT_STATUS_CURR_STATE_MASK) >> CYFLD_BLE_BLESS_MT_CURR_STATE__OFFSET; + + returnValue = ((CY_SYS_BLESS_MT_STATUS_BLERD_IDLE == returnValue) || + (CY_SYS_BLESS_MT_STATUS_SWITCH_EN == returnValue) || + (CY_SYS_BLESS_MT_STATUS_ACTIVE == returnValue) || + (CY_SYS_BLESS_MT_STATUS_ISOLATE == returnValue)); + #else + returnValue = (0u != (CY_SYS_CLK_ECO_STATUS_REG & CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR)) ? 0u : 1u; + #endif /* (CY_IP_WCO_BLESS) */ + + return (returnValue); + } + + #if (CY_IP_ECO_BLESS || CY_IP_ECO_BLESSV3) + /******************************************************************************* + * Function Name: CySysClkWriteEcoDiv + ****************************************************************************//** + * + * Selects value for the ECO divider. + * + * The ECO must not be the HFCLK clock source when this function is called. + * The HFCLK source can be changed to the other clock source by call to the + * CySysClkWriteHfclkDirect() function. If the ECO sources the HFCLK this + * function will not have any effect if compiler in release mode, and halt the + * CPU when compiler in debug mode. + * + * If the SYSCLK clock frequency increases during the device operation, call + * CySysFlashSetWaitCycles() with the appropriate parameter to adjust the number + * of clock cycles the cache will wait before sampling data comes back from + * Flash. If the SYSCLK clock frequency decreases, you can call + * CySysFlashSetWaitCycles() to improve the CPU performance. See + * CySysFlashSetWaitCycles() description for more information. + * + * \param divider Power of 2 divider selection. + * - \ref CY_SYS_CLK_ECO_DIV1 + * - \ref CY_SYS_CLK_ECO_DIV2 + * - \ref CY_SYS_CLK_ECO_DIV4 + * - \ref CY_SYS_CLK_ECO_DIV8 + * + *******************************************************************************/ + void CySysClkWriteEcoDiv(uint32 divider) + { + uint8 interruptState; + + if (CY_SYS_CLK_HFCLK_ECO != (CY_SYS_CLK_SELECT_REG & CY_SYS_CLK_SELECT_DIRECT_SEL_MASK)) + { + interruptState = CyEnterCriticalSection(); + + CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG = (divider & CY_SYS_CLK_XTAL_CLK_DIV_MASK) | + (CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG & ((uint32) ~CY_SYS_CLK_XTAL_CLK_DIV_MASK)); + + CyExitCriticalSection(interruptState); + } + else + { + /* Halt CPU in debug mode if ECO sources HFCLK */ + CYASSERT(0u != 0u); + } + } + + #else + + /******************************************************************************* + * Function Name: CySysClkConfigureEcoTrim + ****************************************************************************//** + * + * Selects trim setting values for ECO. This API is available only for PSoC + * 4200L / 4100S with ECO devices only. + * + * The following parameters can be trimmed for ECO. The affected registers are + * ECO_TRIM0 and ECO_TRIM1. + * + * Watchdog trim - This bit field sets the error threshold below the steady + * state amplitude level. + * + * Amplitude trim - This bit field is to set the crystal drive level when + * ECO_CONFIG.AGC_EN = 1. WARNING: use care when setting this field because + * driving a crystal beyond its rated limit can permanently damage the crystal. + * + * Filter frequency trim - This bit field sets LPF frequency trim and affects + * the 3rd harmonic content. + * + * Feedback resistor trim - This bit field sets the feedback resistor trim and + * impacts the oscillation amplitude. + * + * Amplifier gain trim - This bit field sets the amplifier gain trim and affects + * the startup time of the crystal. + * + * Use care when setting the amplitude trim field because driving a crystal + * beyond its rated limit can permanently damage the crystal. + * + * \param wDTrim: Watchdog trim + * - \ref CY_SYS_CLK_ECO_WDTRIM0 Error threshold is 0.05 V + * - \ref CY_SYS_CLK_ECO_WDTRIM1 Error threshold is 0.10 V + * - \ref CY_SYS_CLK_ECO_WDTRIM2 Error threshold is 0.15 V + * - \ref CY_SYS_CLK_ECO_WDTRIM3 Error threshold is 0.20 V + * + * \param aTrim: Amplitude trim + * - \ref CY_SYS_CLK_ECO_ATRIM0 Amplitude is 0.3 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM1 Amplitude is 0.4 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM2 Amplitude is 0.5 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM3 Amplitude is 0.6 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM4 Amplitude is 0.7 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM5 Amplitude is 0.8 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM6 Amplitude is 0.9 Vpp + * - \ref CY_SYS_CLK_ECO_ATRIM7 Amplitude is 1.0 Vpp + * + * \param fTrim: Filter frequency trim + * - \ref CY_SYS_CLK_ECO_FTRIM0 Crystal frequency > 30 MHz + * - \ref CY_SYS_CLK_ECO_FTRIM1 24 MHz < Crystal frequency <= 30 MHz + * - \ref CY_SYS_CLK_ECO_FTRIM2 17 MHz < Crystal frequency <= 24 MHz + * - \ref CY_SYS_CLK_ECO_FTRIM3 Crystal frequency <= 17 MHz + * + * \param rTrim: Feedback resistor trim + * - \ref CY_SYS_CLK_ECO_RTRIM0 Crystal frequency > 30 MHz + * - \ref CY_SYS_CLK_ECO_RTRIM1 24 MHz < Crystal frequency <= 30 MHz + * - \ref CY_SYS_CLK_ECO_RTRIM2 17 MHz < Crystal frequency <= 24 MHz + * - \ref CY_SYS_CLK_ECO_RTRIM3 Crystal frequency <= 17 MHz + * + * \param gTrim: Amplifier gain trim. Calculate the minimum required gm + * (trans-conductance value). Divide the calculated gm value by 4.5 to + * obtain an integer value 'result'. For more information please refer + * to the device TRM. + * - \ref CY_SYS_CLK_ECO_GTRIM0 If result = 1 + * - \ref CY_SYS_CLK_ECO_GTRIM1 If result = 0 + * - \ref CY_SYS_CLK_ECO_GTRIM2 If result = 2 + * - \ref CY_SYS_CLK_ECO_GTRIM2 If result = 3 + * + *******************************************************************************/ + void CySysClkConfigureEcoTrim(uint32 wDTrim, uint32 aTrim, uint32 fTrim, uint32 rTrim, uint32 gTrim) + { + uint8 interruptState; + uint32 regTmp; + + interruptState = CyEnterCriticalSection(); + + regTmp = CY_SYS_CLK_ECO_TRIM0_REG & ~(CY_SYS_CLK_ECO_TRIM0_WDTRIM_MASK | CY_SYS_CLK_ECO_TRIM0_ATRIM_MASK); + regTmp |= ((uint32) (wDTrim << CY_SYS_CLK_ECO_TRIM0_WDTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM0_WDTRIM_MASK); + regTmp |= ((uint32) (aTrim << CY_SYS_CLK_ECO_TRIM0_ATRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM0_ATRIM_MASK); + CY_SYS_CLK_ECO_TRIM0_REG = regTmp; + + regTmp = CY_SYS_CLK_ECO_TRIM1_REG & ~(CY_SYS_CLK_ECO_TRIM1_FTRIM_MASK | + CY_SYS_CLK_ECO_TRIM1_RTRIM_MASK | + CY_SYS_CLK_ECO_TRIM1_GTRIM_MASK); + regTmp |= ((uint32) (fTrim << CY_SYS_CLK_ECO_TRIM1_FTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_FTRIM_MASK); + regTmp |= ((uint32) (rTrim << CY_SYS_CLK_ECO_TRIM1_RTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_RTRIM_MASK); + regTmp |= ((uint32) (gTrim << CY_SYS_CLK_ECO_TRIM1_GTRIM_SHIFT) & CY_SYS_CLK_ECO_TRIM1_GTRIM_MASK); + + CY_SYS_CLK_ECO_TRIM1_REG = regTmp; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysClkConfigureEcoDrive + ****************************************************************************//** + * + * Selects trim setting values for ECO based on crystal parameters. Use care + * when setting the driveLevel parameter because driving a crystal beyond its + * rated limit can permanently damage the crystal. + * + * This API is available only for PSoC 4200L / 4100S with ECO devices only. + * + * \param freq Frequency of the crystal in kHz. + * \param cLoad Crystal load capacitance in pF. + * \param esr Equivalent series resistance of the crystal in ohm. + * maxAmplitude: maximum amplitude level in mV. Calculate as + * ((sqrt(driveLevel in uW / 2 / esr))/(3.14 * freq * cLoad)) * 10^9. + * + * The Automatic Gain Control (AGC) is disabled when the specified maximum + * amplitude level equals or above 2. In this case the amplitude is not + * explicitly controlled and will grow until it saturates to the supply rail + * (1.8V nom). WARNING: use care when disabling AGC because driving a crystal + * beyond its rated limit can permanently damage the crystal. + * + * \return \ref CYRET_SUCCESS ECO configuration completed successfully. + * \return \ref CYRET_BAD_PARAM One or more invalid parameters. + * + *******************************************************************************/ + cystatus CySysClkConfigureEcoDrive(uint32 freq, uint32 cLoad, uint32 esr, uint32 maxAmplitude) + { + cystatus returnStatus = CYRET_SUCCESS; + + uint32 wDTrim; + uint32 aTrim; + uint32 fTrim; + uint32 rTrim; + uint32 gTrim; + + uint32 gmMin; + + + if ((maxAmplitude < CY_SYS_CLK_ECO_MAX_AMPL_MIN_mV) || + (freq < CY_SYS_CLK_ECO_FREQ_KHZ_MIN) || (freq > CY_SYS_CLK_ECO_FREQ_KHZ_MAX)) + { + returnStatus = CYRET_BAD_PARAM; + } + else + { + /* Calculate amplitude trim */ + aTrim = (maxAmplitude < CY_SYS_CLK_ECO_TRIM_BOUNDARY) ? ((maxAmplitude/100u) - 4u) : 7u; + + if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM0) + { + aTrim = CY_SYS_CLK_ECO_ATRIM0; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM1) + { + aTrim = CY_SYS_CLK_ECO_ATRIM1; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM2) + { + aTrim = CY_SYS_CLK_ECO_ATRIM2; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM3) + { + aTrim = CY_SYS_CLK_ECO_ATRIM3; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM4) + { + aTrim = CY_SYS_CLK_ECO_ATRIM4; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM5) + { + aTrim = CY_SYS_CLK_ECO_ATRIM5; + } + else if (maxAmplitude < CY_SYS_CLK_ECO_AMPL_FOR_ATRIM6) + { + aTrim = CY_SYS_CLK_ECO_ATRIM6; + } + else + { + aTrim = CY_SYS_CLK_ECO_ATRIM7; + } + + /* Calculate Watchdog trim. */ + wDTrim = (maxAmplitude < CY_SYS_CLK_ECO_TRIM_BOUNDARY) ? ((maxAmplitude/200u) - 2u) : 3u; + + /* Calculate amplifier gain trim. */ + gmMin = (uint32) (((((CY_SYS_CLK_ECO_GMMIN_COEFFICIENT * freq * cLoad) / 1000) * ((freq * cLoad * esr) / 1000)) / 100u) / 4500000u); + if (gmMin > 3u) + { + returnStatus = CYRET_BAD_PARAM; + gTrim = 0u; + } + else if (gmMin > 1u) + { + gTrim = gmMin; + } + else + { + gTrim = (gmMin == 1u) ? 0u : 1u; + } + + /* Calculate feedback resistor trim */ + if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM0) + { + rTrim = CY_SYS_CLK_ECO_FTRIM0; + } + else if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM1) + { + rTrim = CY_SYS_CLK_ECO_FTRIM1; + } + else if (freq > CY_SYS_CLK_ECO_FREQ_FOR_FTRIM2) + { + rTrim = CY_SYS_CLK_ECO_FTRIM2; + } + else + { + rTrim = CY_SYS_CLK_ECO_FTRIM3; + } + + /* Calculate filter frequency trim */ + fTrim = rTrim; + + CySysClkConfigureEcoTrim(wDTrim, aTrim, fTrim, rTrim, gTrim); + + /* Automatic Gain Control (AGC) enable */ + if (maxAmplitude < 2u) + { + /* The oscillation amplitude is controlled to the level selected by amplitude trim */ + CY_SYS_CLK_ECO_CONFIG_REG |= CY_SYS_CLK_ECO_CONFIG_AGC_EN; + } + else + { + /* The amplitude is not explicitly controlled and will grow until it saturates to the + * supply rail (1.8V nom). + */ + CY_SYS_CLK_ECO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_ECO_CONFIG_AGC_EN; + } + } + + return (returnStatus); + } + + #endif /* CY_IP_ECO_BLESS */ + +#endif /* (CY_IP_ECO) */ + + +#if (CY_IP_PLL) + /******************************************************************************* + * Function Name: CySysClkPllStart + ****************************************************************************//** + * + * Enables the PLL. Optionally waits for it to become stable. Waits at least + * 250 us or until it is detected that the PLL is stable. + * + * Clears the unlock occurred status bit by calling CySysClkPllGetUnlockStatus(), + * once the PLL is locked if the wait parameter is 1). + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param wait: + * 0 - Return immediately after configuration. + * 1 - Wait for PLL lock or timeout. This API shall use the CyDelayUs() to + * implement the timeout feature. + * + * \return CYRET_SUCCESS Completed successfully. + * \return CYRET_TIMEOUT The timeout occurred without detecting a stable clock. + * If the input source of the clock is jittery, then the lock indication may + * not occur. However, after the timeout has expired, the generated PLL clock can + * still be used. + * \return CYRET_BAD_PARAM - Either the PLL or wait parameter is invalid. + * + *******************************************************************************/ + cystatus CySysClkPllStart(uint32 pll, uint32 wait) + { + uint32 counts = CY_SYS_CLK_PLL_MAX_STARTUP_US; + uint8 interruptState; + cystatus returnStatus = CYRET_SUCCESS; + + if((pll < CY_IP_PLL_NR) && (wait <= 1u)) + { + interruptState = CyEnterCriticalSection(); + + /* Isolate PLL outputs */ + CY_SYS_CLK_PLL_BASE.pll[pll].config &= (uint32) ~CY_SYS_CLK_PLL_CONFIG_ISOLATE; + + /* Enable PLL */ + CY_SYS_CLK_PLL_BASE.pll[pll].config |= CY_SYS_CLK_PLL_CONFIG_ENABLE; + + CyExitCriticalSection(interruptState); + + /* De-isolate >= CY_SYS_CLK_PLL_MIN_STARTUP_US after PLL enabled */ + CyDelayUs(CY_SYS_CLK_PLL_MIN_STARTUP_US); + interruptState = CyEnterCriticalSection(); + CY_SYS_CLK_PLL_BASE.pll[pll].config |= CY_SYS_CLK_PLL_CONFIG_ISOLATE; + CyExitCriticalSection(interruptState); + + if(wait != 0u) + { + returnStatus = CYRET_TIMEOUT; + + while(0u != counts) + { + + if(0u != CySysClkPllGetLockStatus(pll)) + { + returnStatus = CYRET_SUCCESS; + (void) CySysClkPllGetUnlockStatus(pll); + break; + } + + CyDelayUs(1u); + counts--; + } + } + } + else + { + returnStatus = CYRET_BAD_PARAM; + } + + return (returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkPllGetLockStatus + ****************************************************************************//** + * + * Returns non-zero if the output of the specified PLL output is locked. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \return A non-zero value when the specified PLL is locked. + * + *******************************************************************************/ + uint32 CySysClkPllGetLockStatus(uint32 pll) + { + uint8 interruptState; + uint32 returnStatus; + + CYASSERT(pll < CY_IP_PLL_NR); + + interruptState = CyEnterCriticalSection(); + + /* PLL is locked if reported so for two consecutive read. */ + returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].status & CY_SYS_CLK_PLL_STATUS_LOCKED; + if(0u != returnStatus) + { + returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].status & CY_SYS_CLK_PLL_STATUS_LOCKED; + } + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } + + /******************************************************************************* + * Function Name: CySysClkPllStop + ****************************************************************************//** + * + * Disables the PLL. + * + * Ensures that either PLL is not the source of HFCLK before it is disabled, + * otherwise, the CPU will halt. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + *******************************************************************************/ + void CySysClkPllStop(uint32 pll) + { + uint8 interruptState; + + if (pll < CY_IP_PLL_NR) + { + interruptState = CyEnterCriticalSection(); + CY_SYS_CLK_PLL_BASE.pll[pll].config &= (uint32) ~(CY_SYS_CLK_PLL_CONFIG_ISOLATE | CY_SYS_CLK_PLL_CONFIG_ENABLE); + CyExitCriticalSection(interruptState); + } + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetPQ + ****************************************************************************//** + * + * Sets feedback (P) and reference the (Q) divider value. This API also sets the + * programmable charge pump current value. Note that the PLL has to be disabled + * before calling this API. If this function is called while any PLL is sourcing, + * the SYSCLK will return an error. + * + * The PLL must not be the system clock source when calling this function. The + * PLL output will glitch during this function call. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param feedback The P divider. Range 4 - 259. Control bits for the feedback + * divider. + * + * \param reference The Q divider. Range 1 - 64. Divide by the reference. + * + * \param current Charge the pump current in uA. The 2 uA for output frequencies + * of 67 MHz or less, and 3 uA for higher output frequencies. The default + * value is 2 uA. + * + * \return CYRET_SUCCESS Completed successfully. + * \return CYRET_BAD_PARAM The parameters are out of range or the specified PLL + * sources the system clock. + * + *******************************************************************************/ + cystatus CySysClkPllSetPQ(uint32 pll, uint32 feedback, uint32 reference, uint32 current) + { + uint32 regTmp; + cystatus tmp; + uint8 interruptState; + cystatus returnStatus = CYRET_BAD_PARAM; + + interruptState = CyEnterCriticalSection(); + + tmp = CySysClkPllConfigChangeAllowed(pll); + + if ((pll < CY_IP_PLL_NR) && + (feedback >= CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MIN) && (feedback <= CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MAX) && + (reference >= CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MIN) && (reference <= CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MAX) && + (current >= CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MIN ) && (current <= CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MAX) && + (CYRET_SUCCESS == tmp)) + { + /* Set new feedback, reference and current values */ + regTmp = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~(CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MASK | + CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MASK | + CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MASK); + + regTmp |= ((feedback << CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_SHIFT) & CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MASK); + regTmp |= (((reference - 1u) << CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_SHIFT) & CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MASK); + regTmp |= ((current << CY_SYS_CLK_PLL_CONFIG_ICP_SEL_SHIFT) & CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MASK); + + CY_SYS_CLK_PLL_BASE.pll[pll].config = regTmp; + + returnStatus = CYRET_SUCCESS; + } + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetBypassMode + ****************************************************************************//** + * + * Sets the bypass mode for the specified PLL. + * + * The PLL must not be the system clock source when calling this function. + * The PLL output will glitch during this function call. + * + * When the PLL's reference input is higher than HFCLK frequency the device may + * lock due to incorrect flash wait cycle configuration and bypass switches from + * PLL output to the reference input. See description of + * CySysFlashSetWaitCycles() for more information. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param bypass: The bypass mode. + * CY_SYS_PLL_BYPASS_AUTO - Automatic usage of the lock indicator. When unlocked, + * automatically selects PLL the reference input (bypass mode). When locked, + * automatically selects the PLL output. + * + * CY_SYS_PLL_BYPASS_PLL_REF - Selects the PLL reference input (bypass mode). + * Ignores the lock indicator. + * + * CY_SYS_PLL_BYPASS_PLL_OUT - Selects the PLL output. Ignores the lock indicator. + * + *******************************************************************************/ + void CySysClkPllSetBypassMode(uint32 pll, uint32 bypass) + { + uint32 regTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + if ((pll < CY_IP_PLL_NR) && (bypass <= CY_SYS_PLL_BYPASS_PLL_OUT)) + { + regTmp = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_MASK; + regTmp |= (uint32)(bypass << CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT); + CY_SYS_CLK_PLL_BASE.pll[pll].config = regTmp; + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysClkPllGetBypassMode + ****************************************************************************//** + * + * Gets the bypass mode for the specified PLL. + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param bypass: Bypass mode. + * The same as the parameter of the CySysClkPllSetBypassMode(). + * + *******************************************************************************/ + static uint32 CySysClkPllGetBypassMode(uint32 pll) + { + uint32 returnValue; + uint8 interruptState; + + CYASSERT(pll < CY_IP_PLL_NR); + + interruptState = CyEnterCriticalSection(); + + returnValue = CY_SYS_CLK_PLL_BASE.pll[pll].config & CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_MASK; + returnValue = returnValue >> CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT; + + CyExitCriticalSection(interruptState); + + return (returnValue); + } + + + /******************************************************************************* + * Function Name: CySysClkPllConfigChangeAllowed + ****************************************************************************//** + * + * The function returns non-zero value if the specified PLL sources the System + * clock and the PLL is not in the bypass mode. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \return Non-zero value when the specified PLL sources the System clock and + * the PLL is not in the bypass mode. + * + *******************************************************************************/ + static cystatus CySysClkPllConfigChangeAllowed(uint32 pll) + { + uint32 pllBypassMode; + uint32 sysclkSource; + cystatus returnValue = CYRET_INVALID_STATE; + + sysclkSource = CySysClkGetSysclkSource(); + pllBypassMode = CySysClkPllGetBypassMode(pll); + + if ((CY_SYS_PLL_BYPASS_PLL_REF == pllBypassMode) || + ((CY_SYS_CLK_HFCLK_PLL0 != sysclkSource) && (0u == pll)) + #if (CY_IP_SRSSV2) + || ((CY_SYS_CLK_HFCLK_PLL1 != sysclkSource) && (1u == pll)) + #endif /* (CY_IP_SRSSV2) */ + ) + { + returnValue = CYRET_SUCCESS; + } + + return (returnValue); + } + + + /******************************************************************************* + * Function Name: CySysClkPllGetUnlockStatus + ****************************************************************************//** + * + * Returns a non-zero value if the specified PLL output was unlocked. + * The unlock status is an indicator that the PLL has lost a lock at least once + * during its operation. The unlock status is cleared once it is read using + * this API. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \return Non-zero value when the specified PLL was unlocked. + * + *******************************************************************************/ + uint32 CySysClkPllGetUnlockStatus(uint32 pll) + { + uint32 returnStatus = 0u; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + returnStatus = CY_SYS_CLK_PLL_BASE.pll[pll].test & CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_MASK; + CY_SYS_CLK_PLL_BASE.pll[pll].test |= CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_MASK; + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetFrequency + ****************************************************************************//** + * + * Configures either PLL#0 or PLL#1 for the requested input/output frequencies. + * The input frequency is the frequency of the source to the PLL. The source is + * set using the CySysClkPllSetSource() function. + * + * The PLL must not be the system clock source when calling this function. The + * PLL output will glitch during this function call. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param pll: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param inputFreq The reference frequency in KHz. The valid range is from 1000 to 49152 KHz. + * + * \param pllFreq The target frequency in KHz. The valid range is from 22500 to 49152 KHz. + * + * \param divider The output clock divider for the PLL: + * CY_SYS_PLL_OUTPUT_DIVPASS Pass Through + * CY_SYS_PLL_OUTPUT_DIV2 Divide by 2 + * CY_SYS_PLL_OUTPUT_DIV4 Divide by 4 + * CY_SYS_PLL_OUTPUT_DIV8 Divide by 8 + * + * \param freqTol The tolerance in ppm, 10 ppm is equal to 0.001%. + * + * \return CYRET_SUCCESS The PLL was successfully configured for the requested + * frequency. + * + * \return CYRET_BAD_PARAM The PLL was not able to successfully configure for the + * requested frequency. + * + *******************************************************************************/ + cystatus CySysClkPllSetFrequency(uint32 pll, uint32 inputFreq, uint32 pllFreq, uint32 divider, uint32 freqTol) + { + uint32 qMin; + uint32 qMax; + + uint32 qVal = CY_SYS_CLK_PLL_INVALID; + uint32 pVal = CY_SYS_CLK_PLL_INVALID; + + uint32 q; + uint32 p; + + uint32 fvco; + int32 ferr; + + cystatus tmp; + cystatus returnStatus = CYRET_BAD_PARAM; + + + tmp = CySysClkPllConfigChangeAllowed(pll); + + if ((pll < CY_IP_PLL_NR) && + (inputFreq >= CY_SYS_CLK_PLL_INPUT_FREQ_MIN ) && (inputFreq <= CY_SYS_CLK_PLL_INPUT_FREQ_MAX) && + (pllFreq >= CY_SYS_CLK_PLL_OUTPUT_FREQ_MIN ) && (pllFreq <= CY_SYS_CLK_PLL_OUTPUT_FREQ_MAX) && + (divider <= CY_SYS_PLL_OUTPUT_DIV8) && + (CYRET_SUCCESS == tmp)) + { + + /* Minimum feed forward loop divisor */ + qMin = (inputFreq + (CY_SYS_CLK_PLL_FPFDMAX - 1u)) / CY_SYS_CLK_PLL_FPFDMAX; + qMin = (qMin < CY_SYS_CLK_PLL_QMINIP) ? CY_SYS_CLK_PLL_QMINIP : qMin; + + /* Maximum feed forward loop divisor */ + qMax = inputFreq / CY_SYS_CLK_PLL_FPFDMIN; + qMax = (qMax > CY_SYS_CLK_PLL_QMAXIP) ? CY_SYS_CLK_PLL_QMAXIP : qMax; + + if (qMin <= qMax) + { + for(q = qMin; q <= qMax; q++) + { + /* Solve for the feedback divisor value */ + + /* INT((pllFreq * q ) / inputFreq), where INT is normal rounding */ + p = ((pllFreq * q) + (inputFreq / 2u)) / inputFreq; + + /* Calculate the actual VCO frequency (FVCO) */ + fvco = ((inputFreq * p) / q); + + /* Calculate the frequency error (FERR) */ + ferr = ((1000000 * ((int32) fvco - (int32) pllFreq))/ (int32) pllFreq); + + /* Bound check the frequency error and decide next action */ + if ((( -1 * (int32) freqTol) <= ferr) && (ferr <= (int32) freqTol)) + { + qVal = q; + pVal = p; + break; + } + } + + + if ((pVal != CY_SYS_CLK_PLL_INVALID) && (qVal != CY_SYS_CLK_PLL_INVALID)) + { + if (CySysClkPllSetPQ(pll, pVal, qVal, CY_SYS_CLK_PLL_CURRENT_DEFAULT) == CYRET_SUCCESS) + { + returnStatus = CySysClkPllSetOutputDivider(pll, divider); + } + } + } + + } + + return (returnStatus); + } + + /******************************************************************************* + * Function Name: CySysClkPllSetSource + ****************************************************************************//** + * + * Sets the input clock source to the PLL. The PLL must be disabled before + * calling this function. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param source: + * CY_SYS_PLL_SOURCE_IMO IMO + * CY_SYS_PLL_SOURCE_EXTCLK External Clock (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_ECO ECO + * CY_SYS_PLL_SOURCE_DSI0 DSI_OUT[0] (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_DSI1 DSI_OUT[1] (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_DSI2 DSI_OUT[2] (available only for PSoC 4200L) + * CY_SYS_PLL_SOURCE_DSI3 DSI_OUT[3] (available only for PSoC 4200L) + * + *******************************************************************************/ + void CySysClkPllSetSource(uint32 pll, uint32 source) + { + uint32 regTmp; + uint8 interruptState; + + #if (CY_IP_SRSSLT) + uint8 i = 0u; + #endif /* (CY_IP_SRSSLT) */ + + interruptState = CyEnterCriticalSection(); + + if (pll < CY_IP_PLL_NR) + { + #if(CY_IP_SRSSV2) + regTmp = CY_SYS_CLK_SELECT_REG & (uint32) ~CY_SYS_CLK_SELECT_PLL_MASK(pll); + regTmp |= ((source << CY_SYS_CLK_SELECT_PLL_SHIFT(pll)) & CY_SYS_CLK_SELECT_PLL_MASK(pll)); + CY_SYS_CLK_SELECT_REG = regTmp; + #else + regTmp = CY_SYS_ECO_CLK_SELECT_REG & (uint32) ~CY_SYS_ECO_CLK_SELECT_PLL0_MASK; + regTmp |= ((source << CY_SYS_ECO_CLK_SELECT_PLL0_SHIFT) & CY_SYS_ECO_CLK_SELECT_PLL0_MASK); + CY_SYS_ECO_CLK_SELECT_REG = regTmp; + + /* Generate clock sequence to change clock source in CY_SYS_ECO_CLK_SELECT_REG */ + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + + for(i = 0u; i < CY_SYS_EXCO_PGM_CLK_SEQ_GENERATOR; i++) + { + CY_SYS_EXCO_PGM_CLK_REG |= CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK; + } + + CY_SYS_EXCO_PGM_CLK_REG &= ~CY_SYS_EXCO_PGM_CLK_ENABLE_MASK; + + #endif /* (CY_IP_SRSSV2) */ + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysClkPllSetOutputDivider + ****************************************************************************//** + * + * Sets the output clock divider for the PLL. + * + * The PLL must not be the System Clock source when calling this function. The + * PLL output will glitch during this function call. + * + * This API is available only for PSoC 4200L / 4100S with PLL devices. + * + * \param PLL: + * 0 PLL#0 + * 1 PLL#1 (available only for PSoC 4200L) + * + * \param divider: + * CY_SYS_PLL_OUTPUT_DIVPASS Pass through + * CY_SYS_PLL_OUTPUT_DIV2 Divide by 2 + * CY_SYS_PLL_OUTPUT_DIV4 Divide by 4 + * CY_SYS_PLL_OUTPUT_DIV8 Divide by 8 + * + * \return \ref CYRET_SUCCESS Completed successfully. + * \return \ref CYRET_BAD_PARAM The parameters are out of range or the + * specified PLL sources the System clock. + * + *******************************************************************************/ + cystatus CySysClkPllSetOutputDivider(uint32 pll, uint32 divider) + { + uint32 tmpReg; + uint8 interruptState; + cystatus returnStatus = CYRET_BAD_PARAM; + cystatus tmp; + + + interruptState = CyEnterCriticalSection(); + + tmp = CySysClkPllConfigChangeAllowed(pll); + + if ((pll < CY_IP_PLL_NR) && (CYRET_SUCCESS == tmp) && (divider <= CY_SYS_PLL_OUTPUT_DIV8)) + { + tmpReg = CY_SYS_CLK_PLL_BASE.pll[pll].config & (uint32) ~(CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_MASK); + tmpReg |= ((divider << CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_SHIFT) & CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_MASK); + + CY_SYS_CLK_PLL_BASE.pll[pll].config = tmpReg; + + returnStatus = CYRET_SUCCESS; + } + + CyExitCriticalSection(interruptState); + + return (returnStatus); + } +#endif /* (CY_IP_PLL) */ + + +#if(CY_IP_SRSSV2) + + /******************************************************************************* + * Function Name: CySysLvdEnable + ****************************************************************************//** + * + * Enables the output of the low-voltage monitor when Vddd is at or below the + * trip point, configures the device to generate an interrupt, and sets the + * voltage trip level. + * + * \param threshold: Threshold selection for Low Voltage Detect circuit. + * Threshold variation is +/- 2.5% from these typical voltage choices. + * Define Voltage threshold + * CY_LVD_THRESHOLD_1_75_V 1.7500 V + * CY_LVD_THRESHOLD_1_80_V 1.8000 V + * CY_LVD_THRESHOLD_1_90_V 1.9000 V + * CY_LVD_THRESHOLD_2_00_V 2.0000 V + * CY_LVD_THRESHOLD_2_10_V 2.1000 V + * CY_LVD_THRESHOLD_2_20_V 2.2000 V + * CY_LVD_THRESHOLD_2_30_V 2.3000 V + * CY_LVD_THRESHOLD_2_40_V 2.4000 V + * CY_LVD_THRESHOLD_2_50_V 2.5000 V + * CY_LVD_THRESHOLD_2_60_V 2.6000 V + * CY_LVD_THRESHOLD_2_70_V 2.7000 V + * CY_LVD_THRESHOLD_2_80_V 2.8000 V + * CY_LVD_THRESHOLD_2_90_V 2.9000 V + * CY_LVD_THRESHOLD_3_00_V 3.0000 V + * CY_LVD_THRESHOLD_3_20_V 3.2000 V + * CY_LVD_THRESHOLD_4_50_V 4.5000 V + * + *******************************************************************************/ + void CySysLvdEnable(uint32 threshold) + { + /* Prevent propagating a false interrupt */ + CY_LVD_PWR_INTR_MASK_REG &= (uint32) ~CY_LVD_PROPAGATE_INT_TO_CPU; + + /* Set specified threshold */ + CY_LVD_PWR_VMON_CONFIG_REG = (CY_LVD_PWR_VMON_CONFIG_REG & ~CY_LVD_PWR_VMON_CONFIG_LVD_SEL_MASK) | + ((threshold << CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT) & CY_LVD_PWR_VMON_CONFIG_LVD_SEL_MASK); + + /* Enable the LVD. This may cause a false LVD event. */ + CY_LVD_PWR_VMON_CONFIG_REG |= CY_LVD_PWR_VMON_CONFIG_LVD_EN; + + /* Wait for the circuit to stabilize */ + CyDelayUs(CY_LVD_STABILIZE_TIMEOUT_US); + + /* Clear the false event */ + CySysLvdClearInterrupt(); + + /* Unmask the interrupt */ + CY_LVD_PWR_INTR_MASK_REG |= CY_LVD_PROPAGATE_INT_TO_CPU; + } + + + /******************************************************************************* + * Function Name: CySysLvdDisable + ****************************************************************************//** + * + * Disables the low voltage detection. A low voltage interrupt is disabled. + * + *******************************************************************************/ + void CySysLvdDisable(void) + { + CY_LVD_PWR_INTR_MASK_REG &= ~CY_LVD_PROPAGATE_INT_TO_CPU; + CY_LVD_PWR_VMON_CONFIG_REG &= ~CY_LVD_PWR_VMON_CONFIG_LVD_EN; + } + + + /******************************************************************************* + * Function Name: CySysLvdGetInterruptSource + ****************************************************************************//** + * + * Gets the low voltage detection interrupt status (without clearing). + * + * \return + * Interrupt request value: + * CY_SYS_LVD_INT - Indicates an Low Voltage Detect interrupt + * + *******************************************************************************/ + uint32 CySysLvdGetInterruptSource(void) + { + return (CY_LVD_PWR_INTR_REG & CY_SYS_LVD_INT); + } + + + /******************************************************************************* + * Function Name: CySysLvdClearInterrupt + ****************************************************************************//** + * + * Clears the low voltage detection interrupt status. + * + * \return + * None + * + *******************************************************************************/ + void CySysLvdClearInterrupt(void) + { + CY_LVD_PWR_INTR_REG = CY_SYS_LVD_INT; + } + +#endif /* (CY_IP_SRSSV2) */ + + +/******************************************************************************* +* Function Name: CySysGetResetReason +****************************************************************************//** +* +* Reports the cause for the latest reset(s) that occurred in the system. All +* the bits in the RES_CAUSE register assert when the corresponding reset cause +* occurs and must be cleared by the firmware. These bits are cleared by the +* hardware only during XRES, POR, or a detected brown-out. +* +* \param reason: bits in the RES_CAUSE register to clear. +* CY_SYS_RESET_WDT - WDT caused a reset +* CY_SYS_RESET_PROTFAULT - Occured protection violation that requires reset +* CY_SYS_RESET_SW - Cortex-M0 requested a system reset. +* +* \return +* Status. Same enumerated bit values as used for the reason parameter. +* +*******************************************************************************/ +uint32 CySysGetResetReason(uint32 reason) +{ + uint32 returnStatus; + + reason &= (CY_SYS_RESET_WDT | CY_SYS_RESET_PROTFAULT | CY_SYS_RESET_SW); + returnStatus = CY_SYS_RES_CAUSE_REG & + (CY_SYS_RESET_WDT | CY_SYS_RESET_PROTFAULT | CY_SYS_RESET_SW); + CY_SYS_RES_CAUSE_REG = reason; + + return (returnStatus); +} + + +/******************************************************************************* +* Function Name: CyDisableInts +****************************************************************************//** +* +* Disables all interrupts. +* +* \return +* 32 bit mask of previously enabled interrupts. +* +*******************************************************************************/ +uint32 CyDisableInts(void) +{ + uint32 intState; + + /* Get current interrupt state. */ + intState = CY_INT_CLEAR_REG; + + /* Disable all interrupts. */ + CY_INT_CLEAR_REG = CY_INT_CLEAR_DISABLE_ALL; + + return (intState); +} + + +/******************************************************************************* +* Function Name: CyEnableInts +****************************************************************************//** +* +* Enables interrupts to a given state. +* +* \param mask The 32 bit mask of interrupts to enable. +* +*******************************************************************************/ +void CyEnableInts(uint32 mask) +{ + CY_INT_ENABLE_REG = mask; +} + + +/******************************************************************************* +* Function Name: CyIntSetSysVector +****************************************************************************//** +* +* Sets the interrupt vector of the specified system interrupt number. These +* interrupts are for SysTick, PendSV and others. +* +* \param number: System interrupt number: +* CY_INT_NMI_IRQN - Non Maskable Interrupt +* CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt +* CY_INT_SVCALL_IRQN - SV Call Interrupt +* CY_INT_PEND_SV_IRQN - Pend SV Interrupt +* CY_INT_SYSTICK_IRQN - System Tick Interrupt +* +* \param address Pointer to an interrupt service routine. +* +* \return The old ISR vector at this location. +* +*******************************************************************************/ +cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) +{ + cyisraddress oldIsr; + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_INT_IRQ_BASE); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[number]; + + /* Set new Interrupt service routine. */ + ramVectorTable[number] = address; + + return(oldIsr); +} + + +/******************************************************************************* +* Function Name: CyIntGetSysVector +****************************************************************************//** +* +* Gets the interrupt vector of the specified system interrupt number. These +* interrupts are for SysTick, PendSV and others. +* +* \param number: System interrupt number: +* CY_INT_NMI_IRQN - Non Maskable Interrupt +* CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt +* CY_INT_SVCALL_IRQN - SV Call Interrupt +* CY_INT_PEND_SV_IRQN - Pend SV Interrupt +* CY_INT_SYSTICK_IRQN - System Tick Interrupt +* +* \return Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress CyIntGetSysVector(uint8 number) +{ + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_INT_IRQ_BASE); + + return(ramVectorTable[number]); +} + + +/******************************************************************************* +* Function Name: CyIntSetVector +****************************************************************************//** +* +* Sets the interrupt vector of the specified interrupt number. +* +* \param number Valid range [0-31]. Interrupt number +* \param address Pointer to an interrupt service routine +* +* \return Previous interrupt vector value. +* +*******************************************************************************/ +cyisraddress CyIntSetVector(uint8 number, cyisraddress address) +{ + cyisraddress oldIsr; + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_NUM_INTERRUPTS); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[CY_INT_IRQ_BASE + number]; + + /* Set new Interrupt service routine. */ + ramVectorTable[CY_INT_IRQ_BASE + number] = address; + + return(oldIsr); +} + + +/******************************************************************************* +* Function Name: CyIntGetVector +****************************************************************************//** +* +* Gets the interrupt vector of the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number +* +* \return Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress CyIntGetVector(uint8 number) +{ + cyisraddress *ramVectorTable = (cyisraddress *) CY_INT_VECT_TABLE; + + CYASSERT(number < CY_NUM_INTERRUPTS); + + return (ramVectorTable[CY_INT_IRQ_BASE + number]); +} + +/******************************************************************************* +* Function Name: CyIntSetPriority +****************************************************************************//** +* +* Sets the priority of the interrupt. +* +* \param priority: Priority of the interrupt. 0 - 3, 0 being the highest. +* \param number: The number of the interrupt, 0 - 31. +* +*******************************************************************************/ +void CyIntSetPriority(uint8 number, uint8 priority) +{ + uint8 interruptState; + uint32 shift; + uint32 value; + + CYASSERT(priority <= CY_MIN_PRIORITY); + CYASSERT(number < CY_NUM_INTERRUPTS); + + shift = CY_INT_PRIORITY_SHIFT(number); + + interruptState = CyEnterCriticalSection(); + + value = CY_INT_PRIORITY_REG(number); + value &= (uint32)(~((uint32)(CY_INT_PRIORITY_MASK << shift))); + value |= ((uint32)priority << shift); + CY_INT_PRIORITY_REG(number) = value; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyIntGetPriority +****************************************************************************//** +* +* Gets the priority of the interrupt. +* +* \param number: The number of the interrupt, 0 - 31. +* +* \return +* Priority of the interrupt. 0 - 3, 0 being the highest. +* +*******************************************************************************/ +uint8 CyIntGetPriority(uint8 number) +{ + uint8 priority; + + CYASSERT(number < CY_NUM_INTERRUPTS); + + priority = (uint8) (CY_INT_PRIORITY_REG(number) >> CY_INT_PRIORITY_SHIFT(number)); + + return (priority & (uint8) CY_INT_PRIORITY_MASK); +} + + +/******************************************************************************* +* Function Name: CyIntEnable +****************************************************************************//** +* +* Enables the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number +* +*******************************************************************************/ +void CyIntEnable(uint8 number) +{ + CY_INT_ENABLE_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + + +/******************************************************************************* +* Function Name: CyIntGetState +****************************************************************************//** +* +* Gets the enable state of the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number. +* +* \return +* Enable status: 1 if enabled, 0 if disabled +* +*******************************************************************************/ +uint8 CyIntGetState(uint8 number) +{ + /* Get state of interrupt. */ + return ((0u != (CY_INT_ENABLE_REG & ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)))) ? 1u : 0u); +} + + +/******************************************************************************* +* Function Name: CyIntDisable +****************************************************************************//** +* +* Disables the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number. +* +*******************************************************************************/ +void CyIntDisable(uint8 number) +{ + CY_INT_CLEAR_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + +/******************************************************************************* +* Function Name: CyIntSetPending +****************************************************************************//** +* +* Forces the specified interrupt number to be pending. +* +* \param number: Valid range [0-31]. Interrupt number. +* +*******************************************************************************/ +void CyIntSetPending(uint8 number) +{ + CY_INT_SET_PEND_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + + +/******************************************************************************* +* Function Name: CyIntClearPending +****************************************************************************//** +* +* Clears any pending interrupt for the specified interrupt number. +* +* \param number: Valid range [0-31]. Interrupt number. +* +*******************************************************************************/ +void CyIntClearPending(uint8 number) +{ + CY_INT_CLR_PEND_REG = ((uint32) 0x01u << (CY_INT_ENABLE_RANGE_MASK & number)); +} + + +/******************************************************************************* +* Function Name: CyHalt +****************************************************************************//** +* +* Halts the CPU. +* +* \param reason: Value to be used during debugging. +* +*******************************************************************************/ +void CyHalt(uint8 reason) +{ + if(0u != reason) + { + /* To remove unreferenced local variable warning */ + } + + #if defined (__ARMCC_VERSION) + __breakpoint(0x0); + #elif defined(__GNUC__) || defined (__ICCARM__) + __asm(" bkpt 1"); + #elif defined(__C51__) + CYDEV_HALT_CPU; + #endif /* (__ARMCC_VERSION) */ +} + + +/******************************************************************************* +* Function Name: CySoftwareReset +****************************************************************************//** +* +* Forces a software reset of the device. +* +*******************************************************************************/ +void CySoftwareReset(void) +{ + /*************************************************************************** + * Setting the system reset request bit. The vector key value must be written + * to the register, otherwise the register write is unpredictable. + ***************************************************************************/ + CY_SYS_AIRCR_REG = (CY_SYS_AIRCR_REG & (uint32)(~CY_SYS_AIRCR_VECTKEY_MASK)) | + CY_SYS_AIRCR_VECTKEY | CY_SYS_AIRCR_SYSRESETREQ; +} + + +/******************************************************************************* +* Function Name: CyDelay +****************************************************************************//** +* +* Blocks for milliseconds. +* +* \param milliseconds: number of milliseconds to delay. +* +*******************************************************************************/ +void CyDelay(uint32 milliseconds) +{ + while (milliseconds > CY_DELAY_MS_OVERFLOW) + { + /* This loop prevents overflow. + * At 100MHz, milliseconds * cydelayFreqKhz overflows at about 42 seconds + */ + CyDelayCycles(cydelay32kMs); + milliseconds -= CY_DELAY_MS_OVERFLOW; + } + + CyDelayCycles(milliseconds * cydelayFreqKhz); +} + + +/******************************************************************************* +* Function Name: CyDelayUs +****************************************************************************//** +* Blocks for microseconds. +* +* \param microseconds: number of microseconds to delay. +* +*******************************************************************************/ +void CyDelayUs(uint16 microseconds) +{ + CyDelayCycles((uint32)microseconds * cydelayFreqMhz); +} + + +/******************************************************************************* +* Function Name: CyDelayFreq +****************************************************************************//** +* Sets clock frequency for CyDelay. +* +* \param freq: Frequency of bus clock in Hertz. +* +*******************************************************************************/ +void CyDelayFreq(uint32 freq) +{ + if (freq != 0u) + { + cydelayFreqHz = freq; + } + else + { + cydelayFreqHz = CYDEV_BCLK__SYSCLK__HZ; + } + + cydelayFreqMhz = (uint8)((cydelayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cydelayFreqKhz = (cydelayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cydelay32kMs = CY_DELAY_MS_OVERFLOW * cydelayFreqKhz; +} + + +/******************************************************************************* +* Function Name: CySysTick_Start +****************************************************************************//** +* +* Starts the system timer (SysTick): configures SysTick to generate interrupt +* every 1 ms and enables the interrupt. +* +* There are components (LIN, CapSense Gesture) that relies on the default +* interval (1 ms). And that changing the interval will negatively impact +* their functionality. +* +* \sideeffect +* Clears SysTick count flag if it was set. +* +*******************************************************************************/ +void CySysTickStart(void) +{ + if (0u == CySysTickInitVar) + { + CySysTickInit(); + CySysTickInitVar = 1u; + } + + CySysTickEnable(); +} + + +/******************************************************************************* +* Function Name: CySysTickInit +****************************************************************************//** +* +* Initializes the callback addresses with pointers to NULL, associates the +* SysTick system vector with the function that is responsible for calling +* registered callback functions, configures SysTick timer to generate interrupt +* every 1 ms. +* +* The 1 ms interrupt interval is configured based on the frequency determined +* by PSoC Creator at build time. If System clock frequency is changed in +* runtime, the CyDelayFreq() with the appropriate parameter should be called. +* +* \sideeffect +* Clears SysTick count flag if it was set. +* +*******************************************************************************/ +void CySysTickInit(void) +{ + uint32 i; + + for (i = 0u; i> CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT) & CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ); + } + +#endif /* (CY_SYSTICK_LFCLK_SOURCE) */ + + +/******************************************************************************* +* Function Name: CySysTickGetCountFlag +****************************************************************************//** +* +* The count flag is set once SysTick counter reaches zero. +* The flag cleared on read. +* +* \return + * Returns non-zero value if flag is set, otherwise zero is returned. +* +* +* \sideeffect +* Clears SysTick count flag if it was set. +* +*******************************************************************************/ +uint32 CySysTickGetCountFlag(void) +{ + return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u); +} + + +/******************************************************************************* +* Function Name: CySysTickClear +****************************************************************************//** +* +* Clears the SysTick counter for well-defined startup. +* +*******************************************************************************/ +void CySysTickClear(void) +{ + CY_SYS_SYST_CVR_REG = 0u; +} + + +/******************************************************************************* +* Function Name: CySysTickSetCallback +****************************************************************************//** +* +* This function allows up to five user-defined interrupt service routine +* functions to be associated with the SysTick interrupt. These are specified +* through the use of pointers to the function. +* +* To set a custom callback function without the overhead of the system provided +* one, use CyIntSetSysVector(CY_INT_SYSTICK_IRQN, cyisraddress
), +* where
is address of the custom defined interrupt service routine. +* Note: a custom callback function overrides the system defined callback +* functions. +* +* \param number: The number of the callback function addresses to be set. The valid +* range is from 0 to 4. +* +* void(*CallbackFunction(void): A pointer to the function that will be +* associated with the SysTick ISR for the +* specified number. +* +* \return +* Returns the address of the previous callback function. +* The NULL is returned if the specified address in not set. +* +* \sideeffect +* The registered callback functions will be executed in the interrupt. +* +*******************************************************************************/ +cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function) +{ + cySysTickCallback retVal; + + retVal = CySysTickCallbacks[number]; + CySysTickCallbacks[number] = function; + return (retVal); +} + + +/******************************************************************************* +* Function Name: CySysTickGetCallback +****************************************************************************//** +* +* The function get the specified callback pointer. +* +* \param number: The number of callback function address to get. The valid +* range is from 0 to 4. +* +* \return +* Returns the address of the specified callback function. +* The NULL is returned if the specified address in not initialized. +* +*******************************************************************************/ +cySysTickCallback CySysTickGetCallback(uint32 number) +{ + return ((cySysTickCallback) CySysTickCallbacks[number]); +} + + +/******************************************************************************* +* Function Name: CySysTickServiceCallbacks +****************************************************************************//** +* +* System Tick timer interrupt routine +* +*******************************************************************************/ +static void CySysTickServiceCallbacks(void) +{ + uint32 i; + + /* Verify that tick timer flag was set */ + if (1u == CySysTickGetCountFlag()) + { + for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++) + { + if (CySysTickCallbacks[i] != (void *) 0) + { + (void)(CySysTickCallbacks[i])(); + } + } + } +} + + +/******************************************************************************* +* Function Name: CyGetUniqueId +****************************************************************************//** +* +* Returns the 64-bit unique ID of the device. The uniqueness of the number is +* guaranteed for 10 years due to the die lot number having a cycle life of 10 +* years and even after 10 years, the probability of getting two identical +* numbers is very small. +* +* \param uniqueId: The pointer to a two element 32-bit unsigned integer array. Returns +* the 64-bit unique ID of the device by loading them into the integer array +* pointed to by uniqueId. +* +*******************************************************************************/ +void CyGetUniqueId(uint32* uniqueId) +{ +#if(CY_PSOC4) + uniqueId[0u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT0 ); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT1 ) << 8u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT2 ) << 16u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_WAFER ) << 24u); + + uniqueId[1u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_X ); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_Y ) << 8u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_SORT ) << 16u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_MINOR ) << 24u); +#else + uniqueId[0u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_LSB )); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_MSB )) << 8u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_MLOGIC_REV_ID )) << 16u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WAFER_NUM )) << 24u); + + uniqueId[1u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_X_LOC )); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_Y_LOC )) << 8u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WRK_WK )) << 16u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_FAB_YR )) << 24u); +#endif /* (CY_PSOC4) */ +} + + +#if (CY_IP_DMAC_PRESENT) + /******************************************************************************* + * Function Name: CySysSetRamAccessArbPriority + ****************************************************************************//** + * + * Sets RAM access priority between CPU and DMA. The RAM_CTL register is + * configured to set the priority. Please refer to the device TRM for more + * details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetRamAccessArbPriority(uint32 source) + { + uint32 regTmp; + + regTmp = CY_SYS_CPUSS_RAM_CTL_REG & ~CY_SYS_CPUSS_RAM_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_RAM_CTL_ARB_SHIFT) & CY_SYS_CPUSS_RAM_CTL_ARB_MASK); + CY_SYS_CPUSS_RAM_CTL_REG = regTmp; + } + + + /******************************************************************************* + * Function Name: CySysSetFlashAccessArbPriority + ****************************************************************************//** + * + * Sets flash access priority between CPU and DMA. The FLASH_CTL register is + * configured to set the priority. Please refer to the device TRM for more + * details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetFlashAccessArbPriority(uint32 source) + { + uint32 regTmp; + + regTmp = CY_SYS_CPUSS_FLASH_CTL_REG & ~CY_SYS_CPUSS_FLASH_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_FLASH_CTL_ARB_SHIFT) & CY_SYS_CPUSS_FLASH_CTL_ARB_MASK); + CY_SYS_CPUSS_FLASH_CTL_REG = regTmp; + } + + + /******************************************************************************* + * Function Name: CySysSetDmacAccessArbPriority + ****************************************************************************//** + * + * Sets DMAC slave interface access priority between CPU and DMA. The DMAC_CTL + * register is configured to set the priority. Please refer to the device TRM + * for more details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetDmacAccessArbPriority(uint32 source) + { + uint32 regTmp; + + regTmp = CY_SYS_CPUSS_DMAC_CTL_REG & ~CY_SYS_CPUSS_DMAC_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_DMAC_CTL_ARB_SHIFT) & CY_SYS_CPUSS_DMAC_CTL_ARB_MASK); + CY_SYS_CPUSS_DMAC_CTL_REG = regTmp; + } + + + /******************************************************************************* + * Function Name: CySysSetPeripheralAccessArbPriority + ****************************************************************************//** + * + * Sets slave peripheral interface access priority between CPU and DMA. + * The SL_CTL register is configured to set the priority. Please refer to the + * device TRM for more details. + * + * This API is applicable for PSoC 4200M / PSoC 4200L / 4100S with + * DMA devices only. + * + * \param interfaceNumber: the slave interface number. Please refer to the + * device TRM for more details. + * \param source: + * CY_SYS_ARB_PRIORITY_CPU CPU has priority (Default) + * CY_SYS_ARB_PRIORITY_DMA DMA has priority + * CY_SYS_ARB_PRIORITY_ROUND Round robin + * CY_SYS_ARB_PRIORITY_ROUND_STICKY Round robin sticky + * + *******************************************************************************/ + void CySysSetPeripheralAccessArbPriority(uint32 interfaceNumber, uint32 source) + { + uint32 regTmp; + + if (interfaceNumber == 0u) + { + regTmp = CY_SYS_CPUSS_SL_CTL0_REG & ~CY_SYS_CPUSS_SL_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT) & CY_SYS_CPUSS_SL_CTL_ARB_MASK); + CY_SYS_CPUSS_SL_CTL0_REG = regTmp; + } else + #if (CY_IP_SL_NR >= 2) + if (interfaceNumber == 1u) + { + regTmp = CY_SYS_CPUSS_SL_CTL1_REG & ~CY_SYS_CPUSS_SL_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT) & CY_SYS_CPUSS_SL_CTL_ARB_MASK); + CY_SYS_CPUSS_SL_CTL1_REG = regTmp; + } else + #endif /* (CY_IP_SL_NR >= 1) */ + #if (CY_IP_SL_NR >= 3) + if (interfaceNumber == 2u) + { + regTmp = CY_SYS_CPUSS_SL_CTL2_REG & ~CY_SYS_CPUSS_SL_CTL_ARB_MASK; + regTmp |= ((uint32) (source << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT) & CY_SYS_CPUSS_SL_CTL_ARB_MASK); + CY_SYS_CPUSS_SL_CTL2_REG = regTmp; + } else + #endif /* (CY_IP_SL_NR >= 1) */ + { + /* Halt CPU in debug mode if interface is invalid */ + CYASSERT(0u != 0u); + } + } + +#endif /* (CY_IP_DMAC_PRESENT) */ + + +#if (CY_IP_PASS) + /******************************************************************************* + * Function Name: CySysPrbSetGlobalVrefSource + ****************************************************************************//** + * + * Selects the source of the global voltage reference. + * + * \note The global voltage reference uses one of the available programmable + * voltage reference lines. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + * This API affects the voltage values available in + * \ref CySysPrbSetGlobalVrefVoltage(). + * + * This API is applicable for PSoC 4200M, PSoC 4200L and PSoC Analog + * Coprocessor devices only. + * + * \param source: + * CY_SYS_VREF_SOURCE_BG Sets bandgap as the source of the global voltage + * reference. + * CY_SYS_VREF_SOURCE_VDDA Sets VDDA as the source of the global voltage + * reference. + * + *******************************************************************************/ + #ifdef CyDesignWideVoltageReference_PRB_REF + void CySysPrbSetGlobalVrefSource(uint32 source) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_REF, CYFLD_PASS_VREF_SUP_SEL, source); + } + #endif + + /******************************************************************************* + * Function Name: CySysPrbSetBgGain + ****************************************************************************//** + * + * Selects the gain of bandgap reference buffer. Note that this API is effective + * only when the bandgap is set as the source of global voltage reference. + * + * \note This API affects the voltage values available in \ref + * CySysPrbSetGlobalVrefVoltage() API. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + * \param gain: + * CY_SYS_VREF_BG_GAINx1 Gain is 1. + * CY_SYS_VREF_BG_GAINx2 Gain is 2. + * + *******************************************************************************/ + void CySysPrbSetBgGain(uint32 gain) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_VBGR_BUF_GAIN, gain); + } + + + /******************************************************************************* + * Function Name: CySysPrbSetGlobalVrefVoltage + ****************************************************************************//** + * + * Selects the value of global voltage reference. Set the source of the global + * voltage reference and bandgap buffer gain (if applicable) before calling this + * API. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + * \param voltageTap The range is from 1 to 16 that corresponds to: + * Source is bandgap (x1): 0.08 V to 1.20 V in steps of 0.07 V approximately. + * Source is bandgap (x2): 0.16 V to 2.40 V in steps of 0.14 V approximately. + * Source is Vdda: 0.21 V to 3.30 in steps of 0.21 V approximately. The Vdda + * is equal to 3.3 V. Voltage value will change according to value of Vdda. + * + * voltageTap | If bandgap (x1), V| If bandgap (x2), V| If Vdda + * ------------|-------------------|-------------------|------------------- + * 1 | 0.08 | 0.16 | 0.21 + * 2 | 0.15 | 0.30 | 0.41 + * 3 | 0.23 | 0.46 | 0.62 + * 4 | 0.30 | 0.60 | 0.83 + * 5 | 0.38 | 0.76 | 1.03 + * 6 | 0.45 | 0.90 | 1.24 + * 7 | 0.53 | 1.06 | 1.44 + * 8 | 0.60 | 1.20 | 1.65 + * 9 | 0.68 | 1.36 | 1.86 + * 10 | 0.75 | 1.50 | 2.06 + * 11 | 0.83 | 1.66 | 2.27 + * 12 | 0.90 | 1.80 | 2.48 + * 13 | 0.98 | 1.96 | 2.68 + * 14 | 1.05 | 2.10 | 2.89 + * 15 | 1.13 | 2.26 | 3.09 + * 16 | 1.20 | 2.40 | 3.30 + * + *******************************************************************************/ + #ifdef CyDesignWideVoltageReference_PRB_REF + void CySysPrbSetGlobalVrefVoltage(uint32 voltageTap) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_REF, CYFLD_PASS_VREF_SEL, voltageTap); + } + #endif + + + /******************************************************************************* + * Function Name: CySysPrbEnableDeepsleepVddaRef + ****************************************************************************//** + * + * Enables the Vdda reference in deep sleep mode. The Vdda reference is by + * default disabled when entering deep sleep mode. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbEnableDeepsleepVddaRef(void) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_DEEPSLEEP_ON, 1u); + } + + + /******************************************************************************* + * Function Name: CySysPrbDisableDeepsleepVddaRef + ****************************************************************************//** + * + * Disables the Vdda reference in deep sleep mode. The Vdda reference is by + * default disabled when entering deep sleep mode. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbDisableDeepsleepVddaRef(void) + { + CY_CLEAR_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_DEEPSLEEP_ON); + } + + + /******************************************************************************* + * Function Name: CySysPrbEnableVddaRef + ****************************************************************************//** + * + * Enables the Vdda reference. The Vdda reference is by default not enabled. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbEnableVddaRef(void) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_VDDA_ENABLE, 1u); + } + + + /******************************************************************************* + * Function Name: CySysPrbDisableVddaRef + ****************************************************************************//** + * + * Disables the Vdda reference. The Vdda reference is by default not enabled. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbDisableVddaRef(void) + { + CY_CLEAR_REG32_FIELD(CYREG_PASS_PRB_CTRL, CYFLD_PASS_VDDA_ENABLE); + } + + + /******************************************************************************* + * Function Name: CySysPrbSetBgBufferTrim + ****************************************************************************//** + * + * Sets the trim for the bandgap reference buffer. + * + * \note Affects all bandgap sourced references. + * + * \param bgTrim The trim value from -32 to 31. Step size is approximately 1 mV. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + void CySysPrbSetBgBufferTrim(int32 bgTrim) + { + uint8 tmp = 0u; + + if (bgTrim >= 0) + { + CY_SET_REG32_FIELD(CYREG_PASS_PRB_TRIM, CYFLD_PASS_VBGR_BUF_TRIM, (uint32) bgTrim); + } + else + { + tmp = (uint8)((int32) bgTrim * (int8) (-1)); /* Make positive */ + tmp = (uint8) ~tmp + 1u; /* Two's complement */ + tmp |= (uint8) CY_SYS_VREF_BG_BUFFER_TRIM_SIGN_BIT; + + CY_SET_REG32_FIELD(CYREG_PASS_PRB_TRIM, CYFLD_PASS_VBGR_BUF_TRIM, tmp); + } + } + + + /******************************************************************************* + * Function Name: CySysPrbGetBgBufferTrim + ****************************************************************************//** + * + * Returns the current trim of the bandgap reference buffer. + * + * This API is applicable for PSoC 4 devices that support the programmable + * reference block. Please refer to the device TRM for more details. + * + *******************************************************************************/ + int32 CySysPrbGetBgBufferTrim(void) + { + uint8 tmp; + int32 returnValue; + + tmp = (uint8) CY_GET_REG32_FIELD(CYREG_PASS_PRB_TRIM, CYFLD_PASS_VBGR_BUF_TRIM); + if ((tmp & CY_SYS_VREF_BG_BUFFER_TRIM_SIGN_BIT) != 0u) + { + tmp = ((uint8) ~tmp) + 1u; /* Make positive */ + returnValue = (int32) tmp * (-1); /* Make negative */ + } + else + { + returnValue = (int32) tmp; + } + + return (returnValue); + } + + +#endif /* (CY_IP_PASS) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/CyLib.h b/cores/asr650x/projects/PSoC4/CyLib.h new file mode 100644 index 00000000..0b90e97d --- /dev/null +++ b/cores/asr650x/projects/PSoC4/CyLib.h @@ -0,0 +1,1586 @@ +/***************************************************************************//** +* \file CyLib.h +* \version 5.70 +* +* \brief Provides a system API for the clocking, and interrupts. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifdef __cplusplus + extern "C" { +#endif + + + +#if !defined(CY_BOOT_CYLIB_H) +#define CY_BOOT_CYLIB_H + +#include "cytypes.h" +#include "cydevice_trm.h" +#include "CyLFClk.h" + +#include +#include +#include + + +/** +* \addtogroup group_clocking + +PSoC devices supported by PSoC Creator have flexible clocking capabilities. These clocking capabilities are +controlled in PSoC Creator by selections within the Design-Wide Resources settings, connectivity of clocking signals on +the design schematic, and API calls that can modify the clocking at runtime. The clocking API is provided in the CyLib.c +and CyLib.h files. + +This section describes how PSoC Creator maps clocks onto the device and provides guidance on clocking methodologies that +are optimized for the PSoC architecture. + + +\section section_clocking_modes Power Modes +The IMO is available in Active and Sleep modes. It is automatically disabled/enabled for the proper Deep Sleep and +Hibernate mode entry/exit. The IMO is disabled during Deep Sleep and Hibernate modes. + +The EXTCLK is available in Active and Sleep modes. The system will enter/exit Deep Sleep and Hibernate using external +clock. The device will re-enable the IMO if it was enabled before entering Deep Sleep or Hibernate, but it does not wait +for the IMO before starting the CPU. After entering Active mode, the IMO may take an additional 2 us to begin toggling. +The IMO will startup cleanly without glitches, but any dependency should account for this extra startup time. If +desired, firmware may increase wakeup hold-off using \ref CySysPmSetWakeupHoldoff() function to include this 2 us and +ensure the IMO is toggling by the time Active mode is reached. + +The ILO is available in all modes except Hibernate and Stop. + + + +\section section_clocking_connectivity Clock Connectivity +The PSoC architecture includes flexible clock generation logic. Refer to the Technical Reference Manual for a detailed +description of all the clocking sources available in a particular device. The usage of these various clocking sources +can be categorized by how those clocks are connected to elements of a design. + +\section section_clocking_runtime_changing Changing Clocks in Run-time + +\subsection section_clocking_runtime_changing_impact Impact on Components Operation +The components with internal clocks are directly impacted by the change of the system clock frequencies or sources. The +components clock frequencies obtained using design-time dividers. The run-time change of components clock source will +correspondingly change the internal component clock. Refer to the component datasheet for the details. + +\subsection section_clocking_runtime_adjust CyDelay APIs +The CyDelay APIs implement simple software-based delay loops. The loops compensate for system clock frequency. The +\ref CyDelayFreq() function must be called in order to adjust \ref CyDelay(), \ref CyDelayUs() and \ref CyDelayCycles() +functions to the new system clock value. + +\subsection section_clocking_runtime_cache Cache Configuration +If the CPU clock frequency increases during device operation, the number of clock cycles cache will wait before sampling +data coming back from Flash should be adjusted. If the CPU clock frequency decreases, the number of clock cycles can be +also adjusted to improve CPU performance. See 鈥淐ySysFlashSetWaitCycles()鈥?for PSoC 4 for more information. + +*/ + + +/** +* \addtogroup group_clocking_hfclk High-Frequency Clocking API +* \ingroup group_clocking +* @{ +*/ +void CySysClkImoStart(void); +void CySysClkImoStop(void); +void CySysClkWriteHfclkDirect(uint32 clkSelect); + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + void CySysClkImoEnableWcoLock(void); + void CySysClkImoDisableWcoLock(void); + uint32 CySysClkImoGetWcoLock(void); +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + +#if (CY_IP_IMO_TRIMMABLE_BY_USB) + void CySysClkImoEnableUsbLock(void); + void CySysClkImoDisableUsbLock(void); + uint32 CySysClkImoGetUsbLock(void); +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#if (CY_IP_SRSSLT) + void CySysClkWriteHfclkDiv(uint32 divider); +#endif /* (CY_IP_SRSSLT) */ + +void CySysClkWriteSysclkDiv(uint32 divider); +void CySysClkWriteImoFreq(uint32 freq); +uint32 CySysClkGetSysclkSource(void); +void CySysEnablePumpClock(uint32 enable); + +/** @} group_clocking_hfclk */ + + +/** +* \addtogroup group_clocking_lfclk Low-Frequency Clocking API +* \ingroup group_clocking +* \detailed For PSoC 4 devices, the CyLFClk (low-frequency clock) APIs are located in separate files +* (CyLFClk.h/CyLFClk.c). See the CyLFClk Component Datasheet available from the System Reference Guides item of the +* PSoC Creator Help menu. +* @{ +*/ +/** @} group_clocking_lfclk */ + + +/** +* \addtogroup group_clocking_eco External Crystal Oscillator (ECO) API +* \ingroup group_clocking +* @{ +*/ +#if (CY_IP_ECO) + cystatus CySysClkEcoStart(uint32 timeoutUs); + void CySysClkEcoStop(void); + uint32 CySysClkEcoReadStatus(void); + + #if (CY_IP_ECO_BLESS || CY_IP_ECO_BLESSV3) + void CySysClkWriteEcoDiv(uint32 divider); + #endif /* (CY_IP_ECO_BLESS || CY_IP_ECO_BLESSV3) */ + + #if (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) + void CySysClkConfigureEcoTrim(uint32 wDTrim, uint32 aTrim, uint32 fTrim, uint32 rTrim, uint32 gTrim); + cystatus CySysClkConfigureEcoDrive(uint32 freq, uint32 cLoad, uint32 esr, uint32 maxAmplitude); + #endif /* (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) */ +#endif /* (CY_IP_ECO) */ +/** @} group_clocking_eco */ + + +/** +* \addtogroup group_clocking_pll Phase-Locked Loop (PLL) API +* \ingroup group_clocking +* @{ +*/ +#if (CY_IP_PLL) + cystatus CySysClkPllStart(uint32 pll, uint32 wait); + void CySysClkPllStop(uint32 pll); + cystatus CySysClkPllSetPQ(uint32 pll, uint32 feedback, uint32 reference, uint32 current); + cystatus CySysClkPllSetFrequency(uint32 pll, uint32 inputFreq, uint32 pllFreq, uint32 divider, uint32 freqTol); + void CySysClkPllSetSource(uint32 pll, uint32 source); + cystatus CySysClkPllSetOutputDivider(uint32 pll, uint32 divider); + void CySysClkPllSetBypassMode(uint32 pll, uint32 bypass); + uint32 CySysClkPllGetUnlockStatus(uint32 pll); + uint32 CySysClkPllGetLockStatus(uint32 pll); +#endif /* (CY_IP_PLL) */ +/** @} group_clocking_pll */ + + +/** +* \addtogroup group_api_lvd_functions Low Voltage Detection API +* @{ +*/ +#if(CY_IP_SRSSV2) + void CySysLvdEnable(uint32 threshold); + void CySysLvdDisable(void); + uint32 CySysLvdGetInterruptSource(void); + void CySysLvdClearInterrupt(void); +#endif /* (CY_IP_SRSSV2) */ +/** @} group_api_lvd_functions */ + + +/** +* \addtogroup group_interrupts Interrupt API +* \brief The APIs in this chapter apply to all architectures except as noted. The Interrupts API is provided in the +* CyLib.c and CyLib.h files. Refer also to the Interrupt component datasheet for more information about interrupts. +* @{ +*/ +cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address); +cyisraddress CyIntGetSysVector(uint8 number); + +cyisraddress CyIntSetVector(uint8 number, cyisraddress address); +cyisraddress CyIntGetVector(uint8 number); + +void CyIntSetPriority(uint8 number, uint8 priority); +uint8 CyIntGetPriority(uint8 number); + +void CyIntEnable(uint8 number); +uint8 CyIntGetState(uint8 number); +void CyIntDisable(uint8 number); + +void CyIntSetPending(uint8 number); +void CyIntClearPending(uint8 number); + +uint32 CyDisableInts(void); +void CyEnableInts(uint32 mask); +/** @} group_interrupts */ + + +/** +* \addtogroup group_api_delay_functions Delay API +* @{ +*/ +/* Do not use these definitions directly in your application */ +extern uint32 cydelayFreqHz; +extern uint32 cydelayFreqKhz; +extern uint8 cydelayFreqMhz; +extern uint32 cydelay32kMs; + +void CyDelay(uint32 milliseconds); +void CyDelayUs(uint16 microseconds); +void CyDelayFreq(uint32 freq); +void CyDelayCycles(uint32 cycles); +/** @} group_api_delay_functions */ + + +/** +* \addtogroup group_api_system_functions System API +* @{ +*/ +void CySoftwareReset(void); +uint8 CyEnterCriticalSection(void); +void CyExitCriticalSection(uint8 savedIntrStatus); +void CyHalt(uint8 reason); +uint32 CySysGetResetReason(uint32 reason); +void CyGetUniqueId(uint32* uniqueId); + +/* Default interrupt handler */ +CY_ISR_PROTO(IntDefaultHandler); +/** @} group_api_system_functions */ + + +/** +* \addtogroup group_api_systick_functions System Timer (SysTick) API +* @{ +*/ + +typedef void (*cySysTickCallback)(void); + +void CySysTickStart(void); +void CySysTickInit(void); +void CySysTickEnable(void); +void CySysTickStop(void); +void CySysTickEnableInterrupt(void); +void CySysTickDisableInterrupt(void); +void CySysTickSetReload(uint32 value); +uint32 CySysTickGetReload(void); +uint32 CySysTickGetValue(void); +cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function); +cySysTickCallback CySysTickGetCallback(uint32 number); + +#if(CY_SYSTICK_LFCLK_SOURCE) + void CySysTickSetClockSource(uint32 clockSource); + uint32 CySysTickGetClockSource(void); +#endif /* (CY_SYSTICK_LFCLK_SOURCE) */ + +uint32 CySysTickGetCountFlag(void); +void CySysTickClear(void); +extern uint32 CySysTickInitVar; +/** @} group_api_systick_functions */ + + +#if (CY_IP_DMAC_PRESENT) + void CySysSetRamAccessArbPriority(uint32 source); + void CySysSetFlashAccessArbPriority(uint32 source); + void CySysSetDmacAccessArbPriority(uint32 source); + void CySysSetPeripheralAccessArbPriority(uint32 interfaceNumber, uint32 source); +#endif /* (CY_IP_DMAC_PRESENT) */ + + +/** +* \addtogroup group_api_pvb_functions Programmable Voltage Block (PVB) API +* @{ +*/ +#if (CY_IP_PASS) + void CySysPrbSetGlobalVrefSource(uint32 source); + void CySysPrbSetBgGain(uint32 gain); + void CySysPrbSetGlobalVrefVoltage(uint32 voltageTap); + void CySysPrbEnableDeepsleepVddaRef(void); + void CySysPrbDisableDeepsleepVddaRef(void); + void CySysPrbEnableVddaRef(void); + void CySysPrbDisableVddaRef(void); + void CySysPrbSetBgBufferTrim(int32 bgTrim); + int32 CySysPrbGetBgBufferTrim(void); +#endif /* (CY_IP_PASS) */ +/** @} group_api_pvb_functions */ + + +/*************************************** +* API Constants +***************************************/ + + +/******************************************************************************* +* Clock API Constants +*******************************************************************************/ + +/* CySysClkWriteHfclkDirect() - implementation definitions */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_MASK (( uint32 ) 0x07u) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_PARAM_MASK (( uint32 ) 0x07u) + + #define CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT (( uint32 ) 16u) + + #if (CY_IP_PLL) + #define CY_SYS_CLK_SELECT_HFCLK_SEL_MASK (( uint32 ) 3u << CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT) + #else + #define CY_SYS_CLK_SELECT_HFCLK_SEL_MASK (( uint32 ) 0u ) + #endif /* (CY_IP_PLL) */ + +#else + #if (CY_IP_PLL && CY_IP_SRSSLT) + #define CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK (( uint32 ) 0x01u ) + #define CY_SYS_CLK_SELECT_HFCLK_SEL_PLL_MASK (( uint32 ) 0x04u ) + #define CY_SYS_CLK_SELECT_HFCLK_PLL_SHIFT (( uint32 ) 2u) + + #define CY_SYS_EXCO_PGM_CLK_ENABLE_MASK (( uint32 ) 0x80000000u) + #define CY_SYS_EXCO_PGM_CLK_CLK_ECO_MASK (( uint32 ) 0x2u) + #define CY_SYS_EXCO_PGM_CLK_SEQ_GENERATOR (( uint8 ) 0x5u) + #endif /* (CY_IP_PLL && CY_IP_SRSSLT) */ + + #define CY_SYS_CLK_SELECT_HFCLK_SEL_MASK (( uint32 ) 0u ) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_MASK (( uint32 ) 0x03u) + #define CY_SYS_CLK_SELECT_DIRECT_SEL_PARAM_MASK (CY_SYS_CLK_SELECT_DIRECT_SEL_MASK) +#endif /* (CY_IP_SRSSV2) */ + +/* CySysClkWriteHfclkDirect() - parameter definitions */ +#define CY_SYS_CLK_HFCLK_IMO (0u) +#define CY_SYS_CLK_HFCLK_EXTCLK (1u) +#if (CY_IP_ECO) + #define CY_SYS_CLK_HFCLK_ECO (2u) +#endif /* (CY_IP_ECO) */ + +#if (CY_IP_PLL) + #if (CY_IP_SRSSV2) + #define CY_SYS_CLK_HFCLK_PLL0 ((uint32) ((uint32) 2u << CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT)) + #define CY_SYS_CLK_HFCLK_PLL1 ((uint32) ((uint32) 1u << CY_SYS_CLK_SELECT_HFCLK_SEL_SHIFT)) + #else + #define CY_SYS_CLK_HFCLK_PLL0 (6u) + #endif /* (CY_IP_SRSSV2) */ +#endif /* (CY_IP_PLL) */ + +/* CySysClkWriteSysclkDiv() - parameter definitions */ +#define CY_SYS_CLK_SYSCLK_DIV1 (0u) +#define CY_SYS_CLK_SYSCLK_DIV2 (1u) +#define CY_SYS_CLK_SYSCLK_DIV4 (2u) +#define CY_SYS_CLK_SYSCLK_DIV8 (3u) +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SYSCLK_DIV16 (4u) + #define CY_SYS_CLK_SYSCLK_DIV32 (5u) + #define CY_SYS_CLK_SYSCLK_DIV64 (6u) + #define CY_SYS_CLK_SYSCLK_DIV128 (7u) +#endif /* (CY_IP_SRSSV2) */ + + +/* CySysClkWriteSysclkDiv() - implementation definitions */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT (19u) + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK (( uint32 )0x07u) +#else + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_SHIFT (6u) + #define CY_SYS_CLK_SELECT_SYSCLK_DIV_MASK (( uint32 )0x03u) +#endif /* (CY_IP_SRSSV2) */ + + +/* CySysClkPllSetSource() - implementation definitions */ +#if (CY_IP_PLL) + #if(CY_IP_SRSSV2) + #define CY_SYS_CLK_SELECT_PLL_SHIFT(x) (3u + (3u * (x))) + #define CY_SYS_CLK_SELECT_PLL_MASK(x) ((uint32) ((uint32) 0x07u << CY_SYS_CLK_SELECT_PLL_SHIFT((x)))) + #else + #define CY_SYS_ECO_CLK_SELECT_PLL0_SHIFT (1u) + #define CY_SYS_ECO_CLK_SELECT_PLL0_MASK ((uint32) ((uint32) 0x01u << CY_SYS_ECO_CLK_SELECT_PLL0_SHIFT)) + #endif /* (CY_IP_SRSSV2) */ +#endif /* (CY_IP_PLL) */ + +/* CySysClkPllSetSource() - parameter definitions */ +#if (CY_IP_PLL) + #if(CY_IP_SRSSV2) + #define CY_SYS_PLL_SOURCE_IMO (0u) + #define CY_SYS_PLL_SOURCE_EXTCLK (1u) + #define CY_SYS_PLL_SOURCE_ECO (2u) + #define CY_SYS_PLL_SOURCE_DSI0 (4u) + #define CY_SYS_PLL_SOURCE_DSI1 (5u) + #define CY_SYS_PLL_SOURCE_DSI2 (6u) + #define CY_SYS_PLL_SOURCE_DSI3 (7u) + #else + #define CY_SYS_PLL_SOURCE_ECO (0u) + #define CY_SYS_PLL_SOURCE_IMO (1u) + #endif /* (CY_IP_SRSSV2) */ +#endif /* (CY_IP_PLL) */ + +/* CySysClkPllSetBypassMode() - parameter definitions */ +#if(CY_IP_SRSSV2 || CY_IP_SRSSLT) + #if (CY_IP_PLL) + #define CY_SYS_PLL_BYPASS_AUTO (0u) + #define CY_SYS_PLL_BYPASS_PLL_REF (2u) + #define CY_SYS_PLL_BYPASS_PLL_OUT (3u) + #endif /* (CY_IP_PLL) */ +#endif /* (CY_IP_SRSSV2 || CY_IP_SRSSLT)) */ + +/* CySysClkPllSetOutputDivider()/CySysClkPllSetFrequency() - parameters */ +#if(CY_IP_SRSSV2 || CY_IP_SRSSLT) + #if (CY_IP_PLL) + #define CY_SYS_PLL_OUTPUT_DIVPASS (0u) + #define CY_SYS_PLL_OUTPUT_DIV2 (1u) + #define CY_SYS_PLL_OUTPUT_DIV4 (2u) + #define CY_SYS_PLL_OUTPUT_DIV8 (3u) + #endif /* (CY_IP_PLL) */ +#endif /* (CY_IP_SRSSV2 || CY_IP_SRSSLT) */ + +/* CySysPumpClock() */ +#define CY_SYS_CLK_PUMP_DISABLE ((uint32) 0u) +#define CY_SYS_CLK_PUMP_ENABLE ((uint32) 1u) + +#if (CY_IP_PLL) + + /* Set of the PLL registers */ + typedef struct + { + uint32 config; + uint32 status; + uint32 test; + } cy_sys_clk_pll_regs_struct; + + /* Array of the PLL registers */ + typedef struct + { + cy_sys_clk_pll_regs_struct pll[2u]; + } cy_sys_clk_pll_struct; + + + /* CySysClkPllSetPQ() - implementation definitions */ + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_SHIFT (0u) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_SHIFT (8u) + #define CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_SHIFT (14u) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_SHIFT (16u) + #define CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT (20u) + + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MASK ((uint32) ((uint32) 0xFFu << CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MASK ((uint32) ((uint32) 0x3Fu << CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_MASK ((uint32) ((uint32) 0x03u << CY_SYS_CLK_PLL_CONFIG_OUTPUT_DIV_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MASK ((uint32) ((uint32) 0x07u << CY_SYS_CLK_PLL_CONFIG_ICP_SEL_SHIFT)) + #define CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_MASK ((uint32) ((uint32) 0x03u << CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT)) + + #define CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_PLL_REF ((uint32) ((uint32) 2u << CY_SYS_CLK_PLL_CONFIG_BYPASS_SEL_SHIFT)) + + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MIN (4u) + #define CY_SYS_CLK_PLL_CONFIG_FEEDBACK_DIV_MAX (259u) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MIN (2u) + #define CY_SYS_CLK_PLL_CONFIG_ICP_SEL_MAX (3u) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MIN (1u) + #define CY_SYS_CLK_PLL_CONFIG_REFERENCE_DIV_MAX (64u) + + /* CySysClkPllGetUnlockStatus() - implementation definitions */ + #define CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_SHIFT (4u) + #define CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_MASK (( uint32 )(( uint32 )0x01u << CY_SYS_CLK_PLL_TEST_UNLOCK_OCCURRED_SHIFT)) + + /* CySysClkPllSetFrequency() - implementation definitions */ + #define CY_SYS_CLK_PLL_QMINIP (1u) + #define CY_SYS_CLK_PLL_FPFDMAX (3000u) + + #define CY_SYS_CLK_PLL_QMAXIP (64u) + #define CY_SYS_CLK_PLL_FPFDMIN (1000u) + + #define CY_SYS_CLK_PLL_INVALID (0u) + #define CY_SYS_CLK_PLL_CURRENT_DEFAULT (2u) + + #define CY_SYS_CLK_PLL_INPUT_FREQ_MIN (1000u) + #define CY_SYS_CLK_PLL_INPUT_FREQ_MAX (49152u) + + #define CY_SYS_CLK_PLL_OUTPUT_FREQ_MIN (22500u) + #define CY_SYS_CLK_PLL_OUTPUT_FREQ_MAX (49152u) + + /* CySysClkPllStart() / CySysClkPllStop() - implementation definitions */ + #define CY_SYS_CLK_PLL_STATUS_LOCKED (1u) + #define CY_SYS_CLK_PLL_MIN_STARTUP_US (5u) + #define CY_SYS_CLK_PLL_MAX_STARTUP_US (255u) + + #define CY_SYS_CLK_PLL_CONFIG_ENABLE ((uint32) ((uint32) 1u << 31u)) + #define CY_SYS_CLK_PLL_CONFIG_ISOLATE ((uint32) ((uint32) 1u << 30u)) + +#endif /* (CY_IP_PLL) */ + +/* CySysClkWriteImoFreq() - implementation definitions */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_IMO_MAX_FREQ_MHZ (48u) + #define CY_SYS_CLK_IMO_MIN_FREQ_MHZ (3u) + + #define CY_SYS_CLK_IMO_TEMP_FREQ_MHZ (24u) + #define CY_SYS_CLK_IMO_TEMP_FREQ_TRIM2 (0x19u) /* Corresponds to 24 MHz */ + + #define CY_SYS_CLK_IMO_BOUNDARY_FREQ_MHZ (43u) + #define CY_SYS_CLK_IMO_BOUNDARY_FREQ_TRIM2 (0x30u) /* Corresponds to 43 MHz */ + + #define CY_SYS_CLK_IMO_FREQ_TIMEOUT_CYCLES (5u) + #define CY_SYS_CLK_IMO_TRIM_TIMEOUT_US (5u) + #define CY_SYS_CLK_IMO_FREQ_TABLE_SIZE (46u) + #define CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET (3u) + #define CY_SYS_CLK_IMO_FREQ_BITS_MASK (( uint32 )0x3Fu) + #define CY_SYS_CLK_IMO_FREQ_CLEAR (( uint32 )(CY_SYS_CLK_IMO_FREQ_BITS_MASK << 8u)) + #define CY_SYS_CLK_IMO_TRIM4_GAIN_MASK (( uint32 )0x1Fu) + #define CY_SYS_CLK_IMO_TRIM4_WCO_GAIN (( uint32 ) 12u) + #define CY_SYS_CLK_IMO_TRIM4_USB_GAIN (( uint32 ) 8u) + + #if(CY_IP_IMO_TRIMMABLE_BY_USB) + #define CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK (( uint32 )0x02u) + #define CY_SFLASH_S1_TESTPGM_REV_MASK (( uint32 )0x3Fu) + #define CY_SFLASH_S1_TESTPGM_OLD_REV (( uint32 )4u) + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#else + #define CY_SYS_CLK_IMO_MIN_FREQ_MHZ (24u) + #define CY_SYS_CLK_IMO_MAX_FREQ_MHZ (48u) + #define CY_SYS_CLK_IMO_STEP_SIZE_MASK (0x03u) + #define CY_SYS_CLK_IMO_TRIM1_OFFSET_MASK (( uint32 )(0xFFu)) + #define CY_SYS_CLK_IMO_TRIM2_FSOFFSET_MASK (( uint32 )(0x07u)) + #define CY_SYS_CLK_IMO_TRIM3_VALUES_MASK (( uint32 )(0x7Fu)) + #define CY_SYS_CLK_IMO_SELECT_FREQ_MASK (( uint32 )(0x07u)) + #define CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT (( uint32 )(0x02u)) + #define CY_SYS_CLK_IMO_SELECT_24MHZ (( uint32 )(0x00u)) + + #define CY_SYS_CLK_IMO_TRIM_DELAY_US (( uint32 )(50u)) + #define CY_SYS_CLK_IMO_TRIM_DELAY_CYCLES (( uint32 )(50u)) +#endif /* (CY_IP_SRSSV2) */ + +/* CySysClkImoEnableUsbLock(void) - - implementation definitions */ +#if(CY_IP_IMO_TRIMMABLE_BY_USB) + #define CY_SYS_CLK_USBDEVv2_CR1_ENABLE_LOCK (( uint32 )0x02u) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + #define CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_MASK (( uint32 )0x01u) + #define CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_USB (( uint32 )0x00u) + #define CY_SYS_CLK_OSCINTF_CTL_PORT_SEL_WCO (( uint32 )0x01u) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + +#if(CY_IP_SRSSV2) + /* Conversion between CySysClkWriteImoFreq() parameter and register's value */ + extern const uint8 cyImoFreqMhz2Reg[CY_SYS_CLK_IMO_FREQ_TABLE_SIZE]; +#endif /* (CY_IP_SRSSV2) */ + + +/* CySysClkImoStart()/CySysClkImoStop() - implementation definitions */ +#define CY_SYS_CLK_IMO_CONFIG_ENABLE (( uint32 )(( uint32 )0x01u << 31u)) + + +#if(CY_IP_SRSSLT) + /* CySysClkWriteHfclkDiv() - parameter definitions */ + #define CY_SYS_CLK_HFCLK_DIV_NODIV (0u) + #define CY_SYS_CLK_HFCLK_DIV_2 (1u) + #define CY_SYS_CLK_HFCLK_DIV_4 (2u) + #define CY_SYS_CLK_HFCLK_DIV_8 (3u) + + /* CySysClkWriteHfclkDiv() - implementation definitions */ + #define CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT (2u) + #define CY_SYS_CLK_SELECT_HFCLK_DIV_MASK (( uint32 )0x03u) +#endif /* (CY_IP_SRSSLT) */ + + +/* Operating source for Pump clock */ +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_SHIFT (25u) + #define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_MASK ((uint32) 0x07u) + #define CY_SYS_CLK_IMO_CONFIG_PUMP_SEL_IMO (1u) + + #define CY_SYS_CLK_IMO_CONFIG_PUMP_OSC (( uint32 )(( uint32 )0x01u << 22u)) +#else /* CY_IP_SRSSLT */ + #define CY_SYS_CLK_SELECT_PUMP_SEL_SHIFT (4u) + #define CY_SYS_CLK_SELECT_PUMP_SEL_MASK ((uint32) 0x03u) + #define CY_SYS_CLK_SELECT_PUMP_SEL_IMO (1u) +#endif /* (CY_IP_SRSSLT) */ + + +#if (CY_IP_ECO_BLESS) + /* Radio configuration register */ + #define CY_SYS_XTAL_BLESS_RF_CONFIG_RF_ENABLE (( uint32 )0x01u) + + /* RFCTRL mode transition control */ + #define CY_SYS_XTAL_BLERD_DBUS_XTAL_ENABLE (( uint32 )(( uint32 )0x01u << 15u)) + + /* XO is oscillating status */ + #define CY_SYS_XTAL_BLERD_FSM_XO_AMP_DETECT (( uint32 )0x01u) + + /* BB bump configuration 2 */ + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X1_MASK (( uint32 )(( uint32 )0x7Fu << 8u)) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X2_MASK (( uint32 )(( uint32 )0x7Fu << 0u)) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X1_ADD_CAP (( uint32 )(( uint32 )0x01u << 15u)) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_X2_ADD_CAP (( uint32 )(( uint32 )0x01u << 7u)) + + /* BB bump configuration 1 */ + #define CY_SYS_XTAL_BLERD_BB_XO_TRIM ((uint32) 0x2002u) + + + /** + * \addtogroup group_api_eco + * @{ + */ + #define CY_SYS_CLK_ECO_DIV1 ((uint32) 0x00) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 1 */ + #define CY_SYS_CLK_ECO_DIV2 ((uint32) 0x01) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 2 */ + #define CY_SYS_CLK_ECO_DIV4 ((uint32) 0x02) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 4 */ + #define CY_SYS_CLK_ECO_DIV8 ((uint32) 0x03) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 8 */ + /** @} group_api_eco */ + + /* CySysClkWriteEcoDiv() - implementation definitions */ + #define CY_SYS_CLK_XTAL_CLK_DIV_MASK ((uint32) 0x03) +#endif /* (CY_IP_ECO_BLESS) */ + +#if (CY_IP_ECO_BLESSV3) + #define CY_SYS_CLK_ECO_DIV1 ((uint32) 0x00) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 1 */ + #define CY_SYS_CLK_ECO_DIV2 ((uint32) 0x01) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 2 */ + #define CY_SYS_CLK_ECO_DIV4 ((uint32) 0x02) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 4 */ + #define CY_SYS_CLK_ECO_DIV8 ((uint32) 0x03) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 8 */ + /** @} group_api_eco */ + + #define CY_SYS_BLESS_HVLDO_STARTUP_DELAY ((uint32) 2u) + #define CY_SYS_BLESS_ISOLATE_DEASSERT_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_ACT_TO_SWITCH_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_HVLDO_DISABLE_DELAY ((uint32) 1u) + + #define CY_SYS_BLESS_OSC_STARTUP_DELAY_LF ((uint32) 80u) + #define CY_SYS_BLESS_DSM_OFFSET_TO_WAKEUP_INST_LF ((uint32) 4u) + #define CY_SYS_BLESS_ACT_STARTUP_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_DIG_LDO_STARTUP_DELAY ((uint32) 1u) + + #define CY_SYS_BLESS_XTAL_DISABLE_DELAY ((uint32) 1u) + #define CY_SYS_BLESS_DIG_LDO_DISABLE_DELAY ((uint32) 1u) + + #define CY_SYS_BLESS_MT_CFG_ACT_LDO ((uint32) 1u) + #define CY_SYS_BLESS_MT_CFG_ENABLE_BLERD ((uint32) 1u) + #define CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON ((uint32) 1u) + + #define CY_SYS_BLESS_MT_STATUS_BLERD_IDLE ((uint32) 4u) + #define CY_SYS_BLESS_MT_STATUS_SWITCH_EN ((uint32) 5u) + #define CY_SYS_BLESS_MT_STATUS_ACTIVE ((uint32) 6u) + #define CY_SYS_BLESS_MT_STATUS_ISOLATE ((uint32) 7u) + + #define CY_SYS_BLESS_BLERD_ACTIVE_INTR_MASK ((uint32) 0x20u) + #define CY_SYS_BLESS_BLERD_ACTIVE_INTR_STAT ((uint32) 0x8u) + + #define CY_SYS_BLESS_MT_STATUS_CURR_STATE_MASK ((uint32) 0x1Eu) + + #define CY_SYS_RCB_CTRL_ENABLED ((uint32) 1u) + #define CY_SYS_RCB_CTRL_DIV_ENABLED ((uint32) 1u) + #define CY_SYS_RCB_CTRL_DIV ((uint32) 2u) + #define CY_SYS_RCB_CTRL_LEAD ((uint32) 3u) + #define CY_SYS_RCB_CTRL_LAG ((uint32) 3u) + + #define CY_SYS_RCB_INTR_RCB_DONE ((uint32) 1u) + #define CY_SYS_RCB_INTR_RCB_RX_FIFO_NOT_EMPTY ((uint32) ((uint32)0x1u << 17u)) + #define CY_SYS_RCB_INTR_CLEAR ((uint32) 0xFFFFFFFFu) + #define CY_SYS_RCB_RBUS_RD_CMD ((uint32) ((uint32)0x1u << 31u)) + #define CY_SYS_RCB_RBUS_DIG_CLK_SET ((uint32) 0x1e030400u) + #define CY_SYS_RCB_RBUS_FREQ_NRST_SET ((uint32) 0x1e021800u) + #define CY_SYS_RCB_RBUS_FREQ_XTAL_DIV_SET ((uint32) 0x1e090040u) + #define CY_SYS_RCB_RBUS_FREQ_XTAL_NODIV_SET ((uint32) 0x1e090000u) + #define CY_SYS_RCB_RBUS_RF_DCXO_CFG_SET ((uint32) 0x1e080000u) + #define CY_SYS_RCB_RBUS_IB_VAL ((uint32) ((uint32)0x1u << 9u)) + #define CY_SYS_RCB_RBUS_IB_MASK ((uint32) ((uint32)0x3u << 9u)) + #define CY_SYS_RCB_RBUS_TRIM_VAL ((uint32) (CYDEV_RCB_RBUS_RF_DCXO_CAP_TRIM << 1u)) + #define CY_SYS_RCB_RBUS_TRIM_MASK ((uint32) ((uint32)0xFFu << 1u)) + #define CY_SYS_RCB_RBUS_VAL_MASK ((uint32) 0xFFFFu) + + #define CY_SYS_RCBLL_CPU_ACCESS ((uint32) 0u) + #define CY_SYS_RCBLL_BLELL_ACCESS ((uint32) 1u) + + #define CY_SYS_BLELL_CMD_ENTER_DSM ((uint32) 0x50u) + + #define CY_SYS_BLESS_MT_DELAY_CFG_INIT \ + ((CY_SYS_BLESS_HVLDO_STARTUP_DELAY << CYFLD_BLE_BLESS_HVLDO_STARTUP_DELAY__OFFSET) | \ + (CY_SYS_BLESS_ISOLATE_DEASSERT_DELAY << CYFLD_BLE_BLESS_ISOLATE_DEASSERT_DELAY__OFFSET) | \ + (CY_SYS_BLESS_ACT_TO_SWITCH_DELAY << CYFLD_BLE_BLESS_ACT_TO_SWITCH_DELAY__OFFSET) | \ + (CY_SYS_BLESS_HVLDO_DISABLE_DELAY << CYFLD_BLE_BLESS_HVLDO_DISABLE_DELAY__OFFSET)) + + #define CY_SYS_BLESS_MT_DELAY_CFG2_INIT \ + ((CY_SYS_BLESS_OSC_STARTUP_DELAY_LF << CYFLD_BLE_BLESS_OSC_STARTUP_DELAY_LF__OFFSET) | \ + (CY_SYS_BLESS_DSM_OFFSET_TO_WAKEUP_INST_LF << CYFLD_BLE_BLESS_DSM_OFFSET_TO_WAKEUP_INSTANT_LF__OFFSET) | \ + (CY_SYS_BLESS_ACT_STARTUP_DELAY << CYFLD_BLE_BLESS_ACT_STARTUP_DELAY__OFFSET) | \ + (CY_SYS_BLESS_DIG_LDO_STARTUP_DELAY << CYFLD_BLE_BLESS_DIG_LDO_STARTUP_DELAY__OFFSET)) + + #define CY_SYS_BLESS_MT_DELAY_CFG3_INIT \ + ((CY_SYS_BLESS_XTAL_DISABLE_DELAY << CYFLD_BLE_BLESS_XTAL_DISABLE_DELAY__OFFSET) | \ + (CY_SYS_BLESS_DIG_LDO_DISABLE_DELAY << CYFLD_BLE_BLESS_DIG_LDO_DISABLE_DELAY__OFFSET)) + + #define CY_SYS_BLESS_MT_CFG_CLEAR \ + ~(CY_GET_FIELD_MASK(32, CYFLD_BLE_BLESS_ENABLE_BLERD) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_BLESS_DPSLP_ECO_ON) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_BLESS_ACT_LDO_NOT_BUCK)) + + #define CY_SYS_BLESS_MT_CFG_INIT \ + ((CY_SYS_BLESS_MT_CFG_ENABLE_BLERD << CYFLD_BLE_BLESS_ENABLE_BLERD__OFFSET) | \ + (CY_SYS_BLESS_MT_CFG_DPSLP_ECO_ON << CYFLD_BLE_BLESS_DPSLP_ECO_ON__OFFSET) | \ + (CY_SYS_BLESS_MT_CFG_ACT_LDO << CYFLD_BLE_BLESS_ACT_LDO_NOT_BUCK__OFFSET)) + + #define CY_SYS_RCB_CTRL_CLEAR \ + ~(CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_ENABLED) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_DIV_ENABLED) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_DIV) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_LEAD) | \ + CY_GET_FIELD_MASK(32, CYFLD_BLE_RCB_LAG)) + + #define CY_SYS_RCB_CTRL_INIT \ + ((CY_SYS_RCB_CTRL_ENABLED << CYFLD_BLE_RCB_ENABLED__OFFSET) | \ + (CY_SYS_RCB_CTRL_DIV_ENABLED << CYFLD_BLE_RCB_DIV_ENABLED__OFFSET) | \ + (CY_SYS_RCB_CTRL_DIV << CYFLD_BLE_RCB_DIV__OFFSET) | \ + (CY_SYS_RCB_CTRL_LEAD << CYFLD_BLE_RCB_LEAD__OFFSET) | \ + (CY_SYS_RCB_CTRL_LAG << CYFLD_BLE_RCB_LAG__OFFSET)) + + /* CySysClkWriteEcoDiv() - implementation definitions */ + #define CY_SYS_CLK_XTAL_CLK_DIV_MASK ((uint32) 0x03) + + #define CY_SYS_BLE_CLK_ECO_FREQ_32MHZ (32) + +#endif /* (CY_IP_ECO_BLESSV3) */ + + +/* CySysClkImoEnableWcoLock() / CySysClkImoDisableWcoLock() constants */ +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + /* Fimo = DPLL_MULT * Fwco */ + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE (( uint32 )(( uint32 )0x01u << 30u)) + + /* Rounding integer division: DPLL_MULT = (Fimo_in_khz + Fwco_in_khz / 2) / Fwco_in_khz */ + #define CY_SYS_CLK_WCO_DPLL_MULT_VALUE(frequencyMhz) ((uint32) (((((frequencyMhz) * 1000000u) + 16384u) / 32768u) - 1u)) + #define CY_SYS_CLK_WCO_DPLL_MULT_MASK ((uint32) 0x7FFu) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT (16u) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT (19u) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT (22u) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_MASK (( uint32 )(( uint32 )0x07u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT)) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_MASK (( uint32 )(( uint32 )0x07u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT)) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MASK (( uint32 )(( uint32 )0xFFu << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT)) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN (( uint32 )(( uint32 ) 4u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN_SHIFT)) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN (( uint32 )(( uint32 ) 2u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT)) + + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX ((uint32) 0xFFu) + #define CY_SYS_CLK_WCO_IMO_TIMEOUT_MS ((uint32) 20u) + + #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_SAFE_POINT (26u) + #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_SIZE (23u) + #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_OFFSET (26u) + +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + +/******************************************************************************* +* System API Constants +*******************************************************************************/ + +/* CySysGetResetReason() */ +#define CY_SYS_RESET_WDT_SHIFT (0u) +#define CY_SYS_RESET_PROTFAULT_SHIFT (3u) +#define CY_SYS_RESET_SW_SHIFT (4u) + +#define CY_SYS_RESET_WDT ((uint32)1u << CY_SYS_RESET_WDT_SHIFT ) +#define CY_SYS_RESET_PROTFAULT ((uint32)1u << CY_SYS_RESET_PROTFAULT_SHIFT) +#define CY_SYS_RESET_SW ((uint32)1u << CY_SYS_RESET_SW_SHIFT ) + + +/* CySoftwareReset() - implementation definitions */ + +/* Vector Key */ +#define CY_SYS_AIRCR_VECTKEY_SHIFT (16u) +#define CY_SYS_AIRCR_VECTKEY ((uint32)((uint32)0x05FAu << CY_SYS_AIRCR_VECTKEY_SHIFT)) +#define CY_SYS_AIRCR_VECTKEY_MASK ((uint32)((uint32)0xFFFFu << CY_SYS_AIRCR_VECTKEY_SHIFT)) + +/* System Reset Request */ +#define CY_SYS_AIRCR_SYSRESETREQ_SHIFT (2u) +#define CY_SYS_AIRCR_SYSRESETREQ ((uint32)((uint32)1u << CY_SYS_AIRCR_SYSRESETREQ_SHIFT)) + + +#if defined(__ARMCC_VERSION) + + #define CyGlobalIntEnable do \ + { \ + __enable_irq(); \ + } while ( 0 ) + + #define CyGlobalIntDisable do \ + { \ + __disable_irq(); \ + } while ( 0 ) + +#elif defined(__GNUC__) || defined (__ICCARM__) + + #define CyGlobalIntEnable do \ + { \ + __asm("CPSIE i"); \ + } while ( 0 ) + + #define CyGlobalIntDisable do \ + { \ + __asm("CPSID i"); \ + } while ( 0 ) + +#else + #error No compiler toolchain defined + #define CyGlobalIntEnable + #define CyGlobalIntDisable +#endif /* (__ARMCC_VERSION) */ + +/* System tick timer */ +#define CY_SYS_SYST_CSR_ENABLE ((uint32) (0x01u)) +#define CY_SYS_SYST_CSR_ENABLE_INT ((uint32) (0x02u)) +#define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT (0x02u) +#define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT (16u) +#define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u)) +#define CY_SYS_SYST_CSR_CLK_SRC_LFCLK (0u) +#define CY_SYS_SYST_RVR_CNT_MASK (0x00FFFFFFu) +#define CY_SYS_SYST_CVR_CNT_MASK (0x00FFFFFFu) +#define CY_SYS_SYST_NUM_OF_CALLBACKS (5u) + + +/******************************************************************************* +* Macro Name: CyAssert +******************************************************************************** +* Summary: +* Macro that evaluates the expression and, if it is false (evaluates to 0), +* the processor is halted. +* +* This macro is evaluated unless NDEBUG is defined. +* If NDEBUG is defined, then no code is generated for this macro. +* NDEBUG is defined by default for a Release build setting and not defined for +* a Debug build setting. +* +* Parameters: +* expr: Logical expression. Asserts if false. +* +* Return: +* None +* +*******************************************************************************/ +#if !defined(NDEBUG) + #define CYASSERT(x) do \ + { \ + if(0u == (uint32)(x)) \ + { \ + CyHalt((uint8) 0u); \ + } \ + } while ( 0u ) +#else + #define CYASSERT(x) +#endif /* !defined(NDEBUG) */ + + +/******************************************************************************* +* Interrupt API Constants +*******************************************************************************/ +#define CY_NUM_INTERRUPTS (CY_IP_INT_NR) + +#define CY_MIN_PRIORITY (3u) + +#define CY_INT_IRQ_BASE (16u) +#define CY_INT_CLEAR_DISABLE_ALL (0xFFFFFFFFu) +#define CY_INT_ENABLE_RANGE_MASK (0x1Fu) + +/* Register n contains priorities for interrupts N=4n .. 4n+3 */ +#define CY_INT_PRIORITY_SHIFT(number) (( uint32 )6u + (8u * (( uint32 )(number) % 4u))) + +/* Mask to get valid range of system priority 0-3 */ +#define CY_INT_PRIORITY_MASK (( uint32 ) 0x03u) + +/* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */ +#define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */ +#define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */ +#define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */ +#define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */ +#define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */ + + +#if(CY_IP_SRSSV2) + + + /******************************************************************************* + * Low Voltage Detection API Constants + *******************************************************************************/ + + /* CySysLvdEnable() - parameter definitions */ + #define CY_LVD_THRESHOLD_1_75_V (( uint32 ) 0u) + #define CY_LVD_THRESHOLD_1_80_V (( uint32 ) 1u) + #define CY_LVD_THRESHOLD_1_90_V (( uint32 ) 2u) + #define CY_LVD_THRESHOLD_2_00_V (( uint32 ) 3u) + #define CY_LVD_THRESHOLD_2_10_V (( uint32 ) 4u) + #define CY_LVD_THRESHOLD_2_20_V (( uint32 ) 5u) + #define CY_LVD_THRESHOLD_2_30_V (( uint32 ) 6u) + #define CY_LVD_THRESHOLD_2_40_V (( uint32 ) 7u) + #define CY_LVD_THRESHOLD_2_50_V (( uint32 ) 8u) + #define CY_LVD_THRESHOLD_2_60_V (( uint32 ) 9u) + #define CY_LVD_THRESHOLD_2_70_V (( uint32 ) 10u) + #define CY_LVD_THRESHOLD_2_80_V (( uint32 ) 11u) + #define CY_LVD_THRESHOLD_2_90_V (( uint32 ) 12u) + #define CY_LVD_THRESHOLD_3_00_V (( uint32 ) 13u) + #define CY_LVD_THRESHOLD_3_20_V (( uint32 ) 14u) + #define CY_LVD_THRESHOLD_4_50_V (( uint32 ) 15u) + + /* CySysLvdEnable() - implementation definitions */ + #define CY_LVD_PWR_VMON_CONFIG_LVD_EN (( uint32 ) 0x01u) + #define CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT (1u) + #define CY_LVD_PWR_VMON_CONFIG_LVD_SEL_MASK (( uint32 ) (0x0F << CY_LVD_PWR_VMON_CONFIG_LVD_SEL_SHIFT)) + #define CY_LVD_PROPAGATE_INT_TO_CPU (( uint32 ) 0x02u) + #define CY_LVD_STABILIZE_TIMEOUT_US (1000u) + + /* CySysLvdGetInterruptSource()/ CySysLvdClearInterrupt() - parameter definitions */ + #define CY_SYS_LVD_INT (( uint32 ) 0x02u) +#endif /* (CY_IP_SRSSV2) */ + +/* CyDelay()/CyDelayFreq() - implementation definitions */ +#define CY_DELAY_MS_OVERFLOW (0x8000u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (999999u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (999u) + + +/******************************************************************************* +* ECO +*******************************************************************************/ +#if (CY_IP_ECO) + #if (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) + + /* CySysClkEcoStart() - implementation definitions */ + #define CY_SYS_CLK_ECO_CONFIG_CLK_EN_SHIFT (0u) + #define CY_SYS_CLK_ECO_CONFIG_CLK_EN ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_CONFIG_CLK_EN_SHIFT)) + #define CY_SYS_CLK_ECO_CONFIG_CLK_EN_TIMEOUT_US (10u) + + #define CY_SYS_CLK_ECO_CONFIG_ENABLE_SHIFT (31u) + #define CY_SYS_CLK_ECO_CONFIG_ENABLE ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_CONFIG_ENABLE_SHIFT)) + + #define CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR_SHIFT (0u) + #define CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_STATUS_WATCHDOG_ERROR_SHIFT)) + + #define CY_SYS_CLK_ECO_CONFIG_AGC_EN_SHIFT (1u) + #define CY_SYS_CLK_ECO_CONFIG_AGC_EN ((uint32) ((uint32) 1u << CY_SYS_CLK_ECO_CONFIG_AGC_EN_SHIFT)) + + + /** + * \addtogroup group_api_eco + * @{ + */ + #define CY_SYS_CLK_ECO_WDTRIM0 (0u) /**< CySysClkWriteEcoDiv(): HFCLK = ECO / 1 */ + #define CY_SYS_CLK_ECO_WDTRIM1 (1u) + #define CY_SYS_CLK_ECO_WDTRIM2 (2u) + #define CY_SYS_CLK_ECO_WDTRIM3 (3u) + + #define CY_SYS_CLK_ECO_ATRIM0 (0u) + #define CY_SYS_CLK_ECO_ATRIM1 (1u) + #define CY_SYS_CLK_ECO_ATRIM2 (2u) + #define CY_SYS_CLK_ECO_ATRIM3 (3u) + #define CY_SYS_CLK_ECO_ATRIM4 (4u) + #define CY_SYS_CLK_ECO_ATRIM5 (5u) + #define CY_SYS_CLK_ECO_ATRIM6 (6u) + #define CY_SYS_CLK_ECO_ATRIM7 (7u) + + #define CY_SYS_CLK_ECO_FTRIM0 (0u) + #define CY_SYS_CLK_ECO_FTRIM1 (1u) + #define CY_SYS_CLK_ECO_FTRIM2 (2u) + #define CY_SYS_CLK_ECO_FTRIM3 (3u) + + #define CY_SYS_CLK_ECO_RTRIM0 (0u) + #define CY_SYS_CLK_ECO_RTRIM1 (1u) + #define CY_SYS_CLK_ECO_RTRIM2 (2u) + #define CY_SYS_CLK_ECO_RTRIM3 (3u) + + #define CY_SYS_CLK_ECO_GTRIM0 (0u) + #define CY_SYS_CLK_ECO_GTRIM1 (1u) + #define CY_SYS_CLK_ECO_GTRIM2 (2u) + #define CY_SYS_CLK_ECO_GTRIM3 (3u) + /** @} group_api_eco */ + + + /* CySysClkConfigureEcoTrim() - implementation definitions */ + #define CY_SYS_CLK_ECO_TRIM0_WDTRIM_SHIFT (0u) + #define CY_SYS_CLK_ECO_TRIM0_WDTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM0_WDTRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM0_ATRIM_SHIFT (2u) + #define CY_SYS_CLK_ECO_TRIM0_ATRIM_MASK ((uint32) ((uint32) 7u << CY_SYS_CLK_ECO_TRIM0_ATRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM1_FTRIM_SHIFT (0u) + #define CY_SYS_CLK_ECO_TRIM1_FTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM1_FTRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM1_RTRIM_SHIFT (2u) + #define CY_SYS_CLK_ECO_TRIM1_RTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM1_RTRIM_SHIFT)) + + #define CY_SYS_CLK_ECO_TRIM1_GTRIM_SHIFT (4u) + #define CY_SYS_CLK_ECO_TRIM1_GTRIM_MASK ((uint32) ((uint32) 3u << CY_SYS_CLK_ECO_TRIM1_GTRIM_SHIFT)) + + + /* CySysClkConfigureEcoDrive() - implementation definitions */ + #define CY_SYS_CLK_ECO_FREQ_KHZ_MIN (4000u) + #define CY_SYS_CLK_ECO_FREQ_KHZ_MAX (33333u) + + #define CY_SYS_CLK_ECO_MAX_AMPL_MIN_mV (500u) + #define CY_SYS_CLK_ECO_TRIM_BOUNDARY (1200u) + + /* Constant coefficient: 5u * 4u * CY_M_PI * CY_M_PI * 4 / 10 */ + #define CY_SYS_CLK_ECO_GMMIN_COEFFICIENT (79u) + + #define CY_SYS_CLK_ECO_FREQ_FOR_FTRIM0 (30000u) + #define CY_SYS_CLK_ECO_FREQ_FOR_FTRIM1 (24000u) + #define CY_SYS_CLK_ECO_FREQ_FOR_FTRIM2 (17000u) + + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM0 (600u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM1 (700u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM2 (800u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM3 (900u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM4 (1025u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM5 (1150u) + #define CY_SYS_CLK_ECO_AMPL_FOR_ATRIM6 (1275u) + + #endif /* (CY_IP_ECO_SRSSV2 || CY_IP_ECO_SRSSLT) */ +#endif /* (CY_IP_ECO) */ + + +/******************************************************************************* +* Access Arbitration API Constants +*******************************************************************************/ +#if (CY_IP_DMAC_PRESENT) + #define CY_SYS_CPUSS_RAM_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_RAM_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_RAM_CTL_ARB_SHIFT)) + + #define CY_SYS_CPUSS_FLASH_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_FLASH_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_FLASH_CTL_ARB_SHIFT)) + + #define CY_SYS_CPUSS_DMAC_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_DMAC_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_DMAC_CTL_ARB_SHIFT)) + + #define CY_SYS_CPUSS_SL_CTL_ARB_SHIFT (17u) + #define CY_SYS_CPUSS_SL_CTL_ARB_MASK ((uint32) ((uint32) 3u << CY_SYS_CPUSS_SL_CTL_ARB_SHIFT)) + +#endif /* (CY_IP_DMAC_PRESENT) */ + + +#if (CY_IP_DMAC_PRESENT) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_CPU (0u) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_DMA (1u) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_ROUND (2u) + #define CY_SYS_RAM_ACCESS_ARB_PRIORITY_ROUND_STICKY (3u) +#endif /* (CY_IP_DMAC_PRESENT) */ + + +/******************************************************************************* +* Programmable Voltage Reference API +*******************************************************************************/ +#if (CY_IP_PASS) + + #define CYFLD_PASS_VREF_ENABLE__OFFSET (CYFLD_PASS_VREF0_ENABLE__OFFSET ) + #define CYFLD_PASS_VREF_ENABLE__SIZE (CYFLD_PASS_VREF0_ENABLE__SIZE ) + #define CYFLD_PASS_VREF_SUP_SEL__OFFSET (CYFLD_PASS_VREF0_SUP_SEL__OFFSET) + #define CYFLD_PASS_VREF_SUP_SEL__SIZE (CYFLD_PASS_VREF0_SUP_SEL__SIZE ) + #define CYFLD_PASS_VREF_SEL__OFFSET (CYFLD_PASS_VREF0_SEL__OFFSET ) + #define CYFLD_PASS_VREF_SEL__SIZE (CYFLD_PASS_VREF0_SEL__SIZE ) + + /* CySysSetGlobalVrefSource() */ + #define CY_SYS_VREF_SOURCE_BG (0u) + #define CY_SYS_VREF_SOURCE_VDDA (1u) + + /* CySysSetGlobalVrefBgGain() */ + #define CY_SYS_VREF_BG_GAINx1 (1u) + #define CY_SYS_VREF_BG_GAINx2 (2u) + + #ifdef CyDesignWideVoltageReference_PRB_REF + #define CYREG_PASS_PRB_REF (CyDesignWideVoltageReference_PRB_REF) + #endif + + #define CY_SYS_VREF_BG_BUFFER_TRIM_SIGN_BIT (0x20u) + +#endif /* (CY_IP_PASS) */ + + +/*************************************** +* Registers +***************************************/ + + +/******************************************************************************* +* Clocks API Registers +*******************************************************************************/ +#define CY_SYS_CLK_IMO_TRIM1_REG (*(reg32 *) CYREG_CLK_IMO_TRIM1) +#define CY_SYS_CLK_IMO_TRIM1_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM1) + +#define CY_SYS_CLK_IMO_TRIM2_REG (*(reg32 *) CYREG_CLK_IMO_TRIM2) +#define CY_SYS_CLK_IMO_TRIM2_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM2) + +#define CY_SYS_CLK_IMO_TRIM3_REG (*(reg32 *) CYREG_CLK_IMO_TRIM3) +#define CY_SYS_CLK_IMO_TRIM3_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM3) + +#if(CY_IP_SRSSV2) + #define CY_SYS_CLK_IMO_TRIM4_REG (*(reg32 *) CYREG_CLK_IMO_TRIM4) + #define CY_SYS_CLK_IMO_TRIM4_PTR ( (reg32 *) CYREG_CLK_IMO_TRIM4) +#endif /* (CY_IP_SRSSV2) */ + +#define CY_SYS_CLK_IMO_CONFIG_REG (*(reg32 *) CYREG_CLK_IMO_CONFIG) +#define CY_SYS_CLK_IMO_CONFIG_PTR ( (reg32 *) CYREG_CLK_IMO_CONFIG) + + +#define CY_SYS_CLK_SELECT_REG (*(reg32 *) CYREG_CLK_SELECT) +#define CY_SYS_CLK_SELECT_PTR ( (reg32 *) CYREG_CLK_SELECT) + +#if(CY_IP_SRSSV2) + + #if(CY_IP_HOBTO_DEVICE) + #define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM0)[number]) + #define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM0)[number]) + #else + #define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM00)[number]) + #define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM00)[number]) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_SFLASH_USBMODE_IMO_GAIN_TRIM_REG (*(reg8 *) CYREG_SFLASH_USBMODE_IMO_GAIN_TRIM) + #define CY_SFLASH_USBMODE_IMO_GAIN_TRIM_PTR ( (reg8 *) CYREG_SFLASH_USBMODE_IMO_GAIN_TRIM) + + #define CY_SFLASH_USBMODE_IMO_TEMPCO_REG (*(reg8 *) CYREG_SFLASH_USBMODE_IMO_TEMPCO) + #define CY_SFLASH_USBMODE_IMO_TEMPCO_PTR ( (reg8 *) CYREG_SFLASH_USBMODE_IMO_TEMPCO) + + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_24_REG (*(reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_24) + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_24_PTR ( (reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_24) + + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_48_REG (*(reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_48) + #define CY_SFLASH_CU_IMO_TRIM_USBMODE_48_PTR ( (reg8 *) CYREG_SFLASH_CU_IMO_TRIM_USBMODE_48) + + #define CY_SFLASH_S1_TESTPGM_REV_REG (*(reg8 *) CYSFLASH_S1_testpgm_rev) + #define CY_SFLASH_S1_TESTPGM_REV_PTR ( (reg8 *) CYSFLASH_S1_testpgm_rev) + + #define CY_SFLASH_IMO_MAXF0_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF0) + #define CY_SFLASH_IMO_MAXF0_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF0) + + #define CY_SFLASH_IMO_ABS0_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS0) + #define CY_SFLASH_IMO_ABS0_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS0) + + #define CY_SFLASH_IMO_TMPCO0_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO0) + #define CY_SFLASH_IMO_TMPCO0_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO0) + + #define CY_SFLASH_IMO_MAXF1_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF1) + #define CY_SFLASH_IMO_MAXF1_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF1) + + #define CY_SFLASH_IMO_ABS1_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS1) + #define CY_SFLASH_IMO_ABS1_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS1) + + #define CY_SFLASH_IMO_TMPCO1_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO1) + #define CY_SFLASH_IMO_TMPCO1_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO1) + + #define CY_SFLASH_IMO_MAXF2_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF2) + #define CY_SFLASH_IMO_MAXF2_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF2) + + #define CY_SFLASH_IMO_ABS2_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS2) + #define CY_SFLASH_IMO_ABS2_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS2) + + #define CY_SFLASH_IMO_TMPCO2_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO2) + #define CY_SFLASH_IMO_TMPCO2_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO2) + + #define CY_SFLASH_IMO_MAXF3_REG (*(reg8 *) CYREG_SFLASH_IMO_MAXF3) + #define CY_SFLASH_IMO_MAXF3_PTR ( (reg8 *) CYREG_SFLASH_IMO_MAXF3) + + #define CY_SFLASH_IMO_ABS3_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS3) + #define CY_SFLASH_IMO_ABS3_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS3) + + #define CY_SFLASH_IMO_TMPCO3_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO3) + #define CY_SFLASH_IMO_TMPCO3_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO3) + + #define CY_SFLASH_IMO_ABS4_REG (*(reg8 *) CYREG_SFLASH_IMO_ABS4) + #define CY_SFLASH_IMO_ABS4_PTR ( (reg8 *) CYREG_SFLASH_IMO_ABS4) + + #define CY_SFLASH_IMO_TMPCO4_REG (*(reg8 *) CYREG_SFLASH_IMO_TMPCO4) + #define CY_SFLASH_IMO_TMPCO4_PTR ( (reg8 *) CYREG_SFLASH_IMO_TMPCO4) + + #define CY_PWR_BG_TRIM4_REG (*(reg32 *) CYREG_PWR_BG_TRIM4) + #define CY_PWR_BG_TRIM4_PTR ( (reg32 *) CYREG_PWR_BG_TRIM4) + + #define CY_PWR_BG_TRIM5_REG (*(reg32 *) CYREG_PWR_BG_TRIM5) + #define CY_PWR_BG_TRIM5_PTR ( (reg32 *) CYREG_PWR_BG_TRIM5) + + #if (CY_IP_IMO_TRIMMABLE_BY_USB) + + #define CY_SFLASH_IMO_TRIM_USBMODE_24_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + #define CY_SFLASH_IMO_TRIM_USBMODE_24_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + + #define CY_SFLASH_IMO_TRIM_USBMODE_48_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + #define CY_SFLASH_IMO_TRIM_USBMODE_48_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + +#else + + #define CY_SYS_CLK_IMO_SELECT_REG (*(reg32 *) CYREG_CLK_IMO_SELECT) + #define CY_SYS_CLK_IMO_SELECT_PTR ( (reg32 *) CYREG_CLK_IMO_SELECT) + + #define CY_SFLASH_IMO_TCTRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TCTRIM_LT0)[number]) + #define CY_SFLASH_IMO_TCTRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TCTRIM_LT0)[number]) + + #define CY_SFLASH_IMO_TRIM_REG(number) ( ((reg8 *) CYREG_SFLASH_IMO_TRIM_LT0)[number]) + #define CY_SFLASH_IMO_TRIM_PTR(number) (&((reg8 *) CYREG_SFLASH_IMO_TRIM_LT0)[number]) + + #if (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSLT) + + #define CY_SFLASH_IMO_TRIM_USBMODE_24_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + #define CY_SFLASH_IMO_TRIM_USBMODE_24_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_24) + + #define CY_SFLASH_IMO_TRIM_USBMODE_48_REG (*(reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + #define CY_SFLASH_IMO_TRIM_USBMODE_48_PTR ( (reg8 *) CYREG_SFLASH_IMO_TRIM_USBMODE_48) + + #endif /* (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSLT) */ + +#endif /* (CY_IP_SRSSV2) */ + +#if(CY_IP_IMO_TRIMMABLE_BY_USB) + /* USB control 0 Register */ + #define CY_SYS_CLK_USBDEVv2_CR1_REG (*(reg32 *) CYREG_USBDEVv2_CR1) + #define CY_SYS_CLK_USBDEVv2_CR1_PTR ( (reg32 *) CYREG_USBDEVv2_CR1) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_USB) */ + + +/******************************************************************************* +* ECO +*******************************************************************************/ +#if (CY_IP_ECO) + #if (CY_IP_ECO_BLESS) + + /* Radio configuration register */ + #define CY_SYS_XTAL_BLESS_RF_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_RF_CONFIG) + #define CY_SYS_XTAL_BLESS_RF_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_RF_CONFIG) + + /* RFCTRL mode transition control */ + #define CY_SYS_XTAL_BLERD_DBUS_REG (*(reg32 *) CYREG_BLE_BLERD_DBUS) + #define CY_SYS_XTAL_BLERD_DBUS_PTR ( (reg32 *) CYREG_BLE_BLERD_DBUS) + + /* RFCTRL state information */ + #define CY_SYS_XTAL_BLERD_FSM_REG (*(reg32 *) CYREG_BLE_BLERD_FSM) + #define CY_SYS_XTAL_BLERD_FSM_PTR ( (reg32 *) CYREG_BLE_BLERD_FSM) + + /* BB bump configuration 1 */ + #define CY_SYS_XTAL_BLERD_BB_XO_REG (*(reg32 *) CYREG_BLE_BLERD_BB_XO) + #define CY_SYS_XTAL_BLERD_BB_XO_PTR ( (reg32 *) CYREG_BLE_BLERD_BB_XO) + + /* BB bump configuration 2 */ + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG (*(reg32 *) CYREG_BLE_BLERD_BB_XO_CAPTRIM) + #define CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_PTR ( (reg32 *) CYREG_BLE_BLERD_BB_XO_CAPTRIM) + + /* Crystal clock divider configuration register */ + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + + #elif (CY_IP_ECO_BLESSV3) + /* Crystal clock divider configuration register */ + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_REG (*(reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + #define CY_SYS_CLK_XTAL_CLK_DIV_CONFIG_PTR ( (reg32 *) CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG) + + /* RCB registers */ + #define CY_SYS_RCB_CTRL_REG (*(reg32 *) CYREG_BLE_RCB_CTRL) + #define CY_SYS_RCB_CTRL_PTR ( (reg32 *) CYREG_BLE_RCB_CTRL) + #define CY_SYS_RCB_TX_FIFO_WR_REG (*(reg32 *) CYREG_BLE_RCB_TX_FIFO_WR) + #define CY_SYS_RCB_TX_FIFO_WR_PTR ( (reg32 *) CYREG_BLE_RCB_TX_FIFO_WR) + #define CY_SYS_RCB_RX_FIFO_RD_REG (*(reg32 *) CYREG_BLE_RCB_RX_FIFO_RD) + #define CY_SYS_RCB_RX_FIFO_RD_PTR ( (reg32 *) CYREG_BLE_RCB_RX_FIFO_RD) + #define CY_SYS_RCB_INTR_REG (*(reg32 *) CYREG_BLE_RCB_INTR) + #define CY_SYS_RCB_INTR_PTR ( (reg32 *) CYREG_BLE_RCB_INTR) + #define CY_SYS_RCB_INTR_MASK_REG (*(reg32 *) CYREG_BLE_RCB_INTR_MASK) + #define CY_SYS_RCB_INTR_MASK_PTR ( (reg32 *) CYREG_BLE_RCB_INTR_MASK) + + + /* BLESS registers */ + #define CY_SYS_BLESS_MT_CFG_REG (*(reg32 *) CYREG_BLE_BLESS_MT_CFG) + #define CY_SYS_BLESS_MT_CFG_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_CFG) + #define CY_SYS_BLESS_MT_STATUS_REG (*(reg32 *) CYREG_BLE_BLESS_MT_STATUS) + #define CY_SYS_BLESS_MT_STATUS_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_STATUS) + #define CY_SYS_BLESS_INTR_STAT_REG (*(reg32 *) CYREG_BLE_BLESS_INTR_STAT) + #define CY_SYS_BLESS_INTR_STAT_PTR ( (reg32 *) CYREG_BLE_BLESS_INTR_STAT) + #define CY_SYS_BLESS_INTR_MASK_REG (*(reg32 *) CYREG_BLE_BLESS_INTR_MASK) + #define CY_SYS_BLESS_INTR_MASK_PTR ( (reg32 *) CYREG_BLE_BLESS_INTR_MASK) + #define CY_SYS_BLESS_MT_DELAY_CFG_REG (*(reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG) + #define CY_SYS_BLESS_MT_DELAY_CFG_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG) + #define CY_SYS_BLESS_MT_DELAY_CFG2_REG (*(reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG2) + #define CY_SYS_BLESS_MT_DELAY_CFG2_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG2) + #define CY_SYS_BLESS_MT_DELAY_CFG3_REG (*(reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG3) + #define CY_SYS_BLESS_MT_DELAY_CFG3_PTR ( (reg32 *) CYREG_BLE_BLESS_MT_DELAY_CFG3) + + /* BLELL registers */ + #define CY_SYS_BLELL_COMMAND_REG (*(reg32 *) CYREG_BLE_BLELL_COMMAND_REGISTER) + #define CY_SYS_BLELL_COMMAND_PTR ( (reg32 *) CYREG_BLE_BLELL_COMMAND_REGISTER) + + #elif (CY_IP_ECO_SRSSLT) + + /* ECO Clock Select Register */ + #define CY_SYS_ECO_CLK_SELECT_REG (*(reg32 *) CYREG_EXCO_CLK_SELECT) + #define CY_SYS_ECO_CLK_SELECT_PTR ( (reg32 *) CYREG_EXCO_CLK_SELECT) + + /* ECO Configuration Register */ + #define CY_SYS_CLK_ECO_CONFIG_REG (*(reg32 *) CYREG_EXCO_ECO_CONFIG) + #define CY_SYS_CLK_ECO_CONFIG_PTR ( (reg32 *) CYREG_EXCO_ECO_CONFIG) + + /* ECO Status Register */ + #define CY_SYS_CLK_ECO_STATUS_REG (*(reg32 *) CYREG_EXCO_ECO_STATUS) + #define CY_SYS_CLK_ECO_STATUS_PTR ( (reg32 *) CYREG_EXCO_ECO_STATUS) + + /* PLL Configuration Register */ + #define CY_SYS_CLK_PLL0_CONFIG_REG (*(reg32 *) CYREG_EXCO_PLL_CONFIG) + #define CY_SYS_CLK_PLL0_CONFIG_PTR ( (reg32 *) CYREG_EXCO_PLL_CONFIG) + + /* PLL Status Register */ + #define CY_SYS_CLK_PLL_STATUS_REG (*(reg32 *) CYREG_EXCO_PLL_STATUS) + #define CY_SYS_CLK_PLL_STATUS_PTR ( (reg32 *) CYREG_EXCO_PLL_STATUS) + + #define CY_SYS_CLK_PLL_BASE (*(volatile cy_sys_clk_pll_struct *) CYREG_EXCO_PLL_CONFIG) + + /* ECO Trim0 Register */ + #define CY_SYS_CLK_ECO_TRIM0_REG (*(reg32 *) CYREG_EXCO_ECO_TRIM0) + #define CY_SYS_CLK_ECO_TRIM0_PTR ( (reg32 *) CYREG_EXCO_ECO_TRIM0) + + /* ECO Trim1 Register */ + #define CY_SYS_CLK_ECO_TRIM1_REG (*(reg32 *) CYREG_EXCO_ECO_TRIM1) + #define CY_SYS_CLK_ECO_TRIM1_PTR ( (reg32 *) CYREG_EXCO_ECO_TRIM1) + + /* PLL Trim Register */ + #define CY_SYS_CLK_PLL_TRIM_REG (*(reg32 *) CYREG_EXCO_PLL_TRIM) + #define CY_SYS_CLK_PLL_TRIM_PTR ( (reg32 *) CYREG_EXCO_PLL_TRIM) + + #define CY_SYS_EXCO_PGM_CLK_REG (*(reg32 *) CYREG_EXCO_EXCO_PGM_CLK) + #define CY_SYS_EXCO_PGM_CLK_PTR ( (reg32 *) CYREG_EXCO_EXCO_PGM_CLK) + + #else + /* ECO Configuration Register */ + #define CY_SYS_CLK_ECO_CONFIG_REG (*(reg32 *) CYREG_CLK_ECO_CONFIG) + #define CY_SYS_CLK_ECO_CONFIG_PTR ( (reg32 *) CYREG_CLK_ECO_CONFIG) + + /* ECO Status Register */ + #define CY_SYS_CLK_ECO_STATUS_REG (*(reg32 *) CYREG_CLK_ECO_STATUS) + #define CY_SYS_CLK_ECO_STATUS_PTR ( (reg32 *) CYREG_CLK_ECO_STATUS) + + /* ECO Trim0 Register */ + #define CY_SYS_CLK_ECO_TRIM0_REG (*(reg32 *) CYREG_CLK_ECO_TRIM0) + #define CY_SYS_CLK_ECO_TRIM0_PTR ( (reg32 *) CYREG_CLK_ECO_TRIM0) + + /* ECO Trim1 Register */ + #define CY_SYS_CLK_ECO_TRIM1_REG (*(reg32 *) CYREG_CLK_ECO_TRIM1) + #define CY_SYS_CLK_ECO_TRIM1_PTR ( (reg32 *) CYREG_CLK_ECO_TRIM1) + #endif /* (CY_IP_ECO_BLESS) */ +#endif /* (CY_IP_ECO) */ + + +/* CySysClkImoEnableWcoLock() / CySysClkImoDisableWcoLock() registers */ +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + /* WCO DPLL Register */ + #define CY_SYS_CLK_WCO_DPLL_REG (*(reg32 *) CYREG_WCO_DPLL) + #define CY_SYS_CLK_WCO_DPLL_PTR ( (reg32 *) CYREG_WCO_DPLL) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + + +#if (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) + /* Oscillator Interface Control */ + #define CY_SYS_CLK_OSCINTF_CTL_REG (*(reg32 *) CYREG_CLK_OSCINTF_CTL) + #define CY_SYS_CLK_OSCINTF_CTL_PTR ( (reg32 *) CYREG_CLK_OSCINTF_CTL) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO && CY_IP_IMO_TRIMMABLE_BY_USB) */ + + +/******************************************************************************* +* PLL +*******************************************************************************/ +#if (CY_IP_SRSSV2 && CY_IP_PLL) + + /* PLL #0 Configuration Register */ + #define CY_SYS_CLK_PLL0_CONFIG_REG (*(reg32 *) CYREG_CLK_PLL0_CONFIG) + #define CY_SYS_CLK_PLL0_CONFIG_PTR ( (reg32 *) CYREG_CLK_PLL0_CONFIG) + + /* PLL #0 Status Register */ + #define CY_SYS_CLK_PLL0_STATUS_REG (*(reg32 *) CYREG_CLK_PLL0_STATUS) + #define CY_SYS_CLK_PLL0_STATUS_PTR ( (reg32 *) CYREG_CLK_PLL0_STATUS) + + + /* PLL #1 Configuration Register */ + #define CY_SYS_CLK_PLL1_CONFIG_REG (*(reg32 *) CYREG_CLK_PLL1_CONFIG) + #define CY_SYS_CLK_PLL1_CONFIG_PTR ( (reg32 *) CYREG_CLK_PLL1_CONFIG) + + /* PLL #1 Status Register */ + #define CY_SYS_CLK_PLL1_STATUS_REG (*(reg32 *) CYREG_CLK_PLL1_STATUS) + #define CY_SYS_CLK_PLL1_STATUS_PTR ( (reg32 *) CYREG_CLK_PLL1_STATUS) + + #define CY_SYS_CLK_PLL_BASE (*(volatile cy_sys_clk_pll_struct *) CYREG_CLK_PLL0_CONFIG) + +#endif /* (CY_IP_SRSSV2 && CY_IP_PLL) */ + + +/******************************************************************************* +* System API Registers +*******************************************************************************/ +#if (CY_IP_CPUSS_CM0) + #define CY_SYS_AIRCR_REG (*(reg32 *) CYREG_CM0_AIRCR) + #define CY_SYS_AIRCR_PTR ( (reg32 *) CYREG_CM0_AIRCR) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_SYS_AIRCR_REG (*(reg32 *) CYREG_CM0P_AIRCR) + #define CY_SYS_AIRCR_PTR ( (reg32 *) CYREG_CM0P_AIRCR) +#endif /* (CY_IP_CPUSS_CM0) */ + +/* Reset Cause Observation Register */ +#define CY_SYS_RES_CAUSE_REG (*(reg32 *) CYREG_RES_CAUSE) +#define CY_SYS_RES_CAUSE_PTR ( (reg32 *) CYREG_RES_CAUSE) + +#if(CY_IP_SRSSV2) + + /******************************************************************************* + * Low Voltage Detection + *******************************************************************************/ + + /* Voltage Monitoring Trim and Configuration */ + #define CY_LVD_PWR_VMON_CONFIG_REG (*(reg32 *) CYREG_PWR_VMON_CONFIG) + #define CY_LVD_PWR_VMON_CONFIG_PTR ( (reg32 *) CYREG_PWR_VMON_CONFIG) + + /* Power System Interrupt Mask Register */ + #define CY_LVD_PWR_INTR_MASK_REG (*(reg32 *) CYREG_PWR_INTR_MASK) + #define CY_LVD_PWR_INTR_MASK_PTR ( (reg32 *) CYREG_PWR_INTR_MASK) + + /* Power System Interrupt Register */ + #define CY_LVD_PWR_INTR_REG (*(reg32 *) CYREG_PWR_INTR) + #define CY_LVD_PWR_INTR_PTR ( (reg32 *) CYREG_PWR_INTR) + +#endif /* (CY_IP_SRSSV2) */ + + +/******************************************************************************* +* Interrupt API Registers +*******************************************************************************/ +#define CY_INT_VECT_TABLE ( (cyisraddress **) CYDEV_SRAM_BASE) + +#if (CY_IP_CPUSS_CM0) + #define CY_INT_PRIORITY_REG(number) ( ((reg32 *) CYREG_CM0_IPR0)[(number)/4u]) + #define CY_INT_PRIORITY_PTR(number) (&((reg32 *) CYREG_CM0_IPR0)[(number)/4u]) + + #define CY_INT_ENABLE_REG (*(reg32 *) CYREG_CM0_ISER) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_CM0_ISER) + + #define CY_INT_CLEAR_REG (*(reg32 *) CYREG_CM0_ICER) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_CM0_ICER) + + #define CY_INT_SET_PEND_REG (*(reg32 *) CYREG_CM0_ISPR) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_CM0_ISPR) + + #define CY_INT_CLR_PEND_REG (*(reg32 *) CYREG_CM0_ICPR) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_CM0_ICPR) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_INT_PRIORITY_REG(number) ( ((reg32 *) CYREG_CM0P_IPR0)[(number)/4u]) + #define CY_INT_PRIORITY_PTR(number) (&((reg32 *) CYREG_CM0P_IPR0)[(number)/4u]) + + #define CY_INT_ENABLE_REG (*(reg32 *) CYREG_CM0P_ISER) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_CM0P_ISER) + + #define CY_INT_CLEAR_REG (*(reg32 *) CYREG_CM0P_ICER) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_CM0P_ICER) + + #define CY_INT_SET_PEND_REG (*(reg32 *) CYREG_CM0P_ISPR) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_CM0P_ISPR) + + #define CY_INT_CLR_PEND_REG (*(reg32 *) CYREG_CM0P_ICPR) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_CM0P_ICPR) +#endif /* (CY_IP_CPUSS_CM0) */ + +/******************************************************************************* +* System tick API Registers +*******************************************************************************/ +#if (CY_IP_CPUSS_CM0) + #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_CM0_SYST_CSR) + #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_CM0_SYST_CSR) + + #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_CM0_SYST_RVR) + #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_CM0_SYST_RVR) + + #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_CM0_SYST_CVR) + #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_CM0_SYST_CVR) + + #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_CM0_SYST_CALIB) + #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_CM0_SYST_CALIB) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_CM0P_SYST_CSR) + #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_CM0P_SYST_CSR) + + #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_CM0P_SYST_RVR) + #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_CM0P_SYST_RVR) + + #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_CM0P_SYST_CVR) + #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_CM0P_SYST_CVR) + + #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_CM0P_SYST_CALIB) + #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_CM0P_SYST_CALIB) +#endif /* (CY_IP_CPUSS_CM0) */ + + +/******************************************************************************* +* Access Arbitration API Registers +*******************************************************************************/ +#if (CY_IP_DMAC_PRESENT) + /* RAM control register */ + #define CY_SYS_CPUSS_RAM_CTL_REG (*(reg32 *) CYREG_CPUSS_RAM_CTL) + #define CY_SYS_CPUSS_RAM_CTL_PTR ( (reg32 *) CYREG_CPUSS_RAM_CTL) + + /* FLASH control register */ + #define CY_SYS_CPUSS_FLASH_CTL_REG (*(reg32 *) CYREG_CPUSS_FLASH_CTL) + #define CY_SYS_CPUSS_FLASH_CTL_PTR ( (reg32 *) CYREG_CPUSS_FLASH_CTL) + + /* DMAC control register */ + #define CY_SYS_CPUSS_DMAC_CTL_REG (*(reg32 *) CYREG_CPUSS_DMAC_CTL) + #define CY_SYS_CPUSS_DMAC_CTL_PTR ( (reg32 *) CYREG_CPUSS_DMAC_CTL) + + #if (CY_IP_SL_NR >= 1) + /* Slave control register # 0 */ + #if (CY_IP_SL_NR == 1) + #define CY_SYS_CPUSS_SL_CTL0_REG (*(reg32 *) CYREG_CPUSS_SL_CTL) + #define CY_SYS_CPUSS_SL_CTL0_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL) + #else + #define CY_SYS_CPUSS_SL_CTL0_REG (*(reg32 *) CYREG_CPUSS_SL_CTL0) + #define CY_SYS_CPUSS_SL_CTL0_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL0) + #endif /* (CY_IP_SL_NR == 1) */ + #endif /* (CY_IP_SL_NR > 0) */ + + #if (CY_IP_SL_NR >= 2) + /* Slave control register # 1 */ + #define CY_SYS_CPUSS_SL_CTL1_REG (*(reg32 *) CYREG_CPUSS_SL_CTL1) + #define CY_SYS_CPUSS_SL_CTL1_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL1) + #endif /* (CY_IP_SL_NR >= 1) */ + + #if (CY_IP_SL_NR >= 3) + /* Slave control register # 2 */ + #define CY_SYS_CPUSS_SL_CTL2_REG (*(reg32 *) CYREG_CPUSS_SL_CTL2) + #define CY_SYS_CPUSS_SL_CTL2_PTR ( (reg32 *) CYREG_CPUSS_SL_CTL2) + #endif /* (CY_IP_SL_NR >= 2) */ + +#endif /* (CY_IP_DMAC_PRESENT) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions are intended for use in the application, +* use the following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) +#define CY_SYS_CLK_IMO_TRIM4_GAIN (CY_SYS_CLK_IMO_TRIM4_USB_GAIN) + +/* SFLASH0 block has been renamed to SFLASH */ +#if (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + #if !defined(CYREG_SFLASH_IMO_TRIM21) + #define CYREG_SFLASH_IMO_TRIM21 (CYREG_SFLASH0_IMO_TRIM21) + #endif /* !defined(CYREG_SFLASH_IMO_TRIM21) */ +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) */ + +#if (CY_IP_CPUSS_CM0) + + #define CY_SYS_CM0_AIRCR_REG (CY_SYS_AIRCR_REG) + #define CY_SYS_CM0_AIRCR_PTR (CY_SYS_AIRCR_PTR) + + #define CY_SYS_CM0_AIRCR_VECTKEY_SHIFT (CY_SYS_AIRCR_VECTKEY_SHIFT ) + #define CY_SYS_CM0_AIRCR_VECTKEY (CY_SYS_AIRCR_VECTKEY ) + #define CY_SYS_CM0_AIRCR_VECTKEY_MASK (CY_SYS_AIRCR_VECTKEY_MASK ) + #define CY_SYS_CM0_AIRCR_SYSRESETREQ_SHIFT (CY_SYS_AIRCR_SYSRESETREQ_SHIFT) + #define CY_SYS_CM0_AIRCR_SYSRESETREQ (CY_SYS_AIRCR_SYSRESETREQ ) + +#endif /* (CY_IP_CPUSS_CM0) */ + +#endif /* CY_BOOT_CYLIB_H */ + +#ifdef __cplusplus +} +#endif + + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/RTC.c b/cores/asr650x/projects/PSoC4/RTC.c new file mode 100644 index 00000000..b148d721 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/RTC.c @@ -0,0 +1,1444 @@ +/***************************************************************************//** +* \file Name: RTC.c +* \version 1.30 +* +* This file provides the source code to the API for the RTC_P4 Component. +* +******************************************************************************** +* \copyright +* Copyright 2015-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "RTC.h" + +uint8 RTC_initVar; + +volatile uint64 RTC_unixTime; +RTC_DATE_TIME RTC_currentTimeDate; + +static uint32 RTC_updateTimePeriod; +static uint32 RTC_tickRefOneSec; + +uint8 RTC_dstStatus; +static uint32 RTC_dstTimeOffset; +#if(0u != RTC_INITIAL_DST_STATUS) + static volatile uint64 RTC_unixTimeDstStart; + static volatile uint64 RTC_unixTimeDstStop; + RTC_DST_TIME RTC_dstStartTime; + RTC_DST_TIME RTC_dstStopTime; +#endif /* (0u != RTC_INITIAL_DST_STATUS) */ + +uint32 RTC_alarmCurStatus; +#if(0u != RTC_INITIAL_ALARM_STATUS) + uint32 RTC_alarmCfgMask = 0xFFu; + static volatile uint64 RTC_unixTimeAlarm; + RTC_DATE_TIME RTC_alarmCfgTimeDate; + void (*RTC_alarmCallbackPtr)(void) = (void *)0; +#endif /* (0u != RTC_INITIAL_ALARM_STATUS) */ + +const uint16 RTC_daysBeforeMonthTbl[RTC_MONTHS_PER_YEAR] = { + (0u), /* JANUARY */ + (0u + 31u), /* FEBRUARY */ + (0u + 31u + 28u), /* MARCH */ + (0u + 31u + 28u + 31u), /* APRIL */ + (0u + 31u + 28u + 31u + 30u), /* MAY */ + (0u + 31u + 28u + 31u + 30u + 31u), /* JUNE */ + (0u + 31u + 28u + 31u + 30u + 31u + 30u), /* JULY */ + (0u + 31u + 28u + 31u + 30u + 31u + 30u + 31u), /* AUGUST */ + (0u + 31u + 28u + 31u + 30u + 31u + 30u + 31u + 31u), /* SEPTEMBER */ + (0u + 31u + 28u + 31u + 30u + 31u + 30u + 31u + 31u + 30u), /* OCTOBER */ + (0u + 31u + 28u + 31u + 30u + 31u + 30u + 31u + 31u + 30u + 31u), /* NOVEMBER */ + (0u + 31u + 28u + 31u + 30u + 31u + 30u + 31u + 31u + 30u + 31u + 30u)}; /* DECEMBER */ + +const uint8 RTC_daysInMonthTbl[RTC_MONTHS_PER_YEAR] = {RTC_DAYS_IN_JANUARY, + RTC_DAYS_IN_FEBRUARY, + RTC_DAYS_IN_MARCH, + RTC_DAYS_IN_APRIL, + RTC_DAYS_IN_MAY, + RTC_DAYS_IN_JUNE, + RTC_DAYS_IN_JULY, + RTC_DAYS_IN_AUGUST, + RTC_DAYS_IN_SEPTEMBER, + RTC_DAYS_IN_OCTOBER, + RTC_DAYS_IN_NOVEMBER, + RTC_DAYS_IN_DECEMBER}; + + +/******************************************************************************* +* Function Name: RTC_Start +****************************************************************************//** +* +* Performs all the required calculations for the time and date registers and +* initializes the component along with the date and time selected in the +* customizer. +* +* If "Implement RTC update manually" is disabled in the customizer +* and if WDT or DeepSleep timer is selected as a source in the clocks +* configuration window (low frequency clocks tab), attaches RTC_Update API to a +* corresponding ISR callback of WDT or DeepSleep Timer. +* +* \note "Implement RTC update manually" checkbox is available for PSoC 4200L / +* PSoC 4100M / PSoC 4200M / PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4000S / PSoC +* 4100S and Analog Coprocessor. +* +*******************************************************************************/ +void RTC_Start(void) +{ + if(0u == RTC_initVar) + { + RTC_Init(); + } + + #if defined(CYDEV_RTC_SOURCE_WDT) + #if((0u != CYDEV_WDT_GENERATE_ISR) && (0u == RTC_INITIAL_UPDATE_MODE)) + RTC_CySysRtcSetCallback(CYDEV_RTC_SOURCE_WDT); + #endif /* ((0u != CYDEV_WDT_GENERATE_ISR) && (0u == RTC_INITIAL_UPDATE_MODE)) */ + #endif /* (CYDEV_RTC_SOURCE_WDT) */ +} + + +/******************************************************************************* +* Function Name: RTC_Stop +****************************************************************************//** +* +* Stops the time and date updates. +* +*******************************************************************************/ +void RTC_Stop(void) +{ + #if defined(CYDEV_RTC_SOURCE_WDT) + #if((0u != CYDEV_WDT_GENERATE_ISR) && (0u == RTC_INITIAL_UPDATE_MODE)) + RTC_CySysRtcResetCallback(CYDEV_RTC_SOURCE_WDT); + #endif /* ((0u != CYDEV_WDT_GENERATE_ISR) && (0u == RTC_INITIAL_UPDATE_MODE)) */ + #endif /* (CYDEV_RTC_SOURCE_WDT) */ +} + + +/******************************************************************************* +* Function Name: RTC_Init +****************************************************************************//** +* +* Initializes or restores the component according to the customizer Configure +* dialogue settings. +* +* It is not necessary to call RTC_Init() because RTC_Start() API calls this +* function and is the preferred method to begin component operation. +* +* All registers are set to values according to the customizer Configure +* dialogue. The default date value, if not set by the user before this function +* call, is 12:00:00 AM January 1, 2000. +* +*******************************************************************************/ +void RTC_Init(void) +{ + uint32 tmpDate; + uint32 tmpTime; + + #if(0u != RTC_INITIAL_DST_STATUS) + RTC_DST_TIME dstTimeTmp; + #endif /* (0u != RTC_INITIAL_DST_STATUS) */ + + RTC_initVar = 1u; + RTC_dstTimeOffset = 0uL; + RTC_currentTimeDate.status = 0uL; + + RTC_dstStatus = RTC_INITIAL_DST_STATUS; + RTC_alarmCurStatus = RTC_INITIAL_ALARM_STATUS; + + tmpDate = RTC_ConstructDate(RTC_INITIAL_MONTH, + RTC_INITIAL_DAY, + RTC_INITIAL_YEAR); + + tmpTime = RTC_ConstructTime(RTC_INITIAL_TIME_FORMAT, + 0u, + RTC_INITIAL_HOUR, + RTC_INITIAL_MINUTE, + RTC_INITIAL_SECOND); + + #if(0u != RTC_INITIAL_DST_STATUS) + RTC_dstStatus = 0u; + RTC_currentTimeDate.status = (1uL << RTC_STATUS_DST_OFFSET); + + dstTimeTmp.timeFormat = RTC_INITIAL_DST_DATE_TYPE; + dstTimeTmp.hour = RTC_INITIAL_DST_START_HRS; + dstTimeTmp.dayOfWeek = RTC_INITIAL_DST_START_DOW; + dstTimeTmp.weekOfMonth = RTC_INITIAL_DST_START_WOM; + dstTimeTmp.dayOfMonth = RTC_INITIAL_DST_START_DOM; + dstTimeTmp.month = RTC_INITIAL_DST_START_MONTH; + RTC_SetDSTStartTime(&dstTimeTmp, + (RTC_DST_DATETYPE_ENUM)RTC_INITIAL_DST_DATE_TYPE); + + dstTimeTmp.timeFormat = RTC_INITIAL_DST_DATE_TYPE; + dstTimeTmp.hour = RTC_INITIAL_DST_STOP_HRS; + dstTimeTmp.dayOfWeek = RTC_INITIAL_DST_STOP_DOW; + dstTimeTmp.weekOfMonth = RTC_INITIAL_DST_STOP_WOM; + dstTimeTmp.dayOfMonth = RTC_INITIAL_DST_STOP_DOM; + dstTimeTmp.month = RTC_INITIAL_DST_STOP_MONTH; + RTC_SetDSTStopTime(&dstTimeTmp, + (RTC_DST_DATETYPE_ENUM)RTC_INITIAL_DST_DATE_TYPE); + + RTC_unixTimeDstStart = RTC_GetDstUnixTime(&RTC_dstStartTime); + RTC_unixTimeDstStop = RTC_GetDstUnixTime(&RTC_dstStopTime); + + if((RTC_unixTime >= RTC_unixTimeDstStart) && + (RTC_unixTime <= RTC_unixTimeDstStop)) + { + RTC_dstStatus = 1u; + RTC_dstTimeOffset = RTC_SECONDS_PER_HOUR; + } + #endif /* (0u != RTC_INITIAL_DST_STATUS) */ + + RTC_SetDateAndTime(tmpTime, tmpDate); +} + + +/******************************************************************************* +* Function Name: RTC_SetDateAndTime +****************************************************************************//** +* +* Sets the time and date values as the current time and date. +* +* \param inputTime +* The time value in the HH:MM:SS format.
+* "HH"- The 2nd 8-bit MSB that denotes the hour value. +* (0-23 for the 24-hour format and 1-12 for the 12-hour format. The MSB bit of +* the value denotes AM/PM for the 12-hour format (0-AM and 1-PM).
+* "MM" - The 3nd 8-bit MSB denotes the minutes value, the valid +* entries -> 0-59.
+* "SS" - The 8-bit LSB denotes the seconds value, the valid entries -> 0-59. +* Each byte is in the BCD format. Invalid time entries retain the +* previously set values. +* +* \param inputDate +* The date value in the format selected in the customizer. +* For the MM/DD/YYYY format:
+* "MM" - The 8-bit MSB denotes the month value in BCD, the valid +* entries -> 1-12
+* "DD" - The 2nd 8-bit MSB denotes a day of the month value in BCD, the valid +* entries -> 1-31.
+* "YYYY" - The 16-bit LSB denotes a year in BCD, the valid entries -> 1900-2200. +* Each byte is in the BCD format. Invalid date entries retain the +* previously set values. +* +*******************************************************************************/ +void RTC_SetDateAndTime(uint32 inputTime, uint32 inputDate) +{ + uint32 tmpDay; + uint32 tmpMonth; + uint32 tmpYear; + + tmpDay = RTC_GetDay(inputDate); + tmpMonth = RTC_GetMonth(inputDate); + tmpYear = RTC_GetYear(inputDate); + + RTC_unixTime = RTC_DateTimeToUnix(inputDate, inputTime); + RTC_currentTimeDate.date = inputDate; + RTC_currentTimeDate.time = inputTime; + RTC_currentTimeDate.dayOfWeek = RTC_GetDayOfWeek(tmpDay, tmpMonth, tmpYear); + + #if(0u != RTC_INITIAL_DST_STATUS) + RTC_unixTimeDstStart = RTC_GetDstUnixTime(&RTC_dstStartTime); + RTC_unixTimeDstStop = RTC_GetDstUnixTime(&RTC_dstStopTime); + + if((RTC_unixTime >= RTC_unixTimeDstStart) && + (RTC_unixTime <= RTC_unixTimeDstStop)) + { + RTC_dstStatus = 1u; + RTC_dstTimeOffset = RTC_SECONDS_PER_HOUR; + RTC_unixTime -= RTC_dstTimeOffset; + } + else + { + RTC_dstStatus = 0u; + RTC_dstTimeOffset = 0uL; + } + #endif /* (0u != RTC_INITIAL_DST_STATUS) */ + + #if(0u != RTC_INITIAL_ALARM_STATUS) + RTC_unixTimeAlarm = RTC_ConstructUnixAlarmTime(&RTC_alarmCfgTimeDate, + (uint8)RTC_alarmCfgMask); + #endif /* (0u != RTC_INITIAL_ALARM_STATUS) */ +} + + +/******************************************************************************* +* Function Name: RTC_SetUnixTime +****************************************************************************//** +* +* Sets the time in the Unix/Epoch time format - the number of seconds elapsed +* from January 1, 1970 UTC 00:00 hrs. +* +* \param unixTime +* The time value in the Unix time/Epoch time format. +* +*******************************************************************************/ +void RTC_SetUnixTime(uint64 unixTime) +{ + RTC_DATE_TIME tmpDateTime; + + RTC_unixTime = unixTime; + RTC_UnixToDateTime(&tmpDateTime, unixTime, (uint32)RTC_24_HOURS_FORMAT); + + #if(0u != RTC_INITIAL_DST_STATUS) + RTC_unixTimeDstStart = RTC_GetDstUnixTime(&RTC_dstStartTime); + RTC_unixTimeDstStop = RTC_GetDstUnixTime(&RTC_dstStopTime); + + if((RTC_unixTime >= RTC_unixTimeDstStart) && + (RTC_unixTime <= RTC_unixTimeDstStop)) + { + RTC_dstStatus = 1u; + RTC_dstTimeOffset = RTC_SECONDS_PER_HOUR; + } + else + { + RTC_dstStatus = 0u; + RTC_dstTimeOffset = 0uL; + } + #endif /* (0u != RTC_INITIAL_DST_STATUS) */ +} + + +/******************************************************************************* +* Function Name: RTC_GetUnixTime +****************************************************************************//** +* +* Returns the time in the Unix/Epoch time format - the number of seconds +* elapsed from January 1, 1970 UTC 00:00 hrs. +* +* \return +* Time The time value in the Unix time/Epoch time format. +* +*******************************************************************************/ +uint64 RTC_GetUnixTime(void) +{ + return (RTC_unixTime); +} + + +/******************************************************************************* +* Function Name: RTC_SetPeriod +****************************************************************************//** +* +* Sets the RTC time update API period. +* +* The user needs to pass the period as +* a number of ticks and also a reference number of ticks taken by the same +* clock source for one second. For instance, for a 32 kHz clock source and RTC +* period of 100 ms, the "ticks" value is 3200 and the "refOneSecTicks" value +* is 32000. This value is used to increment the time every time +* RTC_Update() API is called. +* +* \param ticks +* The clock period taken as a number of ticks. +* +* \param refOneSecTicks +* The reference number of ticks taken by the same clock source +* for one second (the input clock frequency in Hz). +* +*******************************************************************************/ +void RTC_SetPeriod(uint32 ticks, uint32 refOneSecTicks) +{ + RTC_updateTimePeriod = ticks; + RTC_tickRefOneSec = refOneSecTicks; +} + + +/******************************************************************************* +* Function Name: RTC_SetPeriod +****************************************************************************//** +* +* Gets the RTC time update API period. +* +* \return +* Period The clock period taken as a number of ticks. +* +*******************************************************************************/ +uint32 RTC_GetPeriod(void) +{ + return(RTC_updateTimePeriod); +} + + +/******************************************************************************* +* Function Name: RTC_GetRefOneSec +****************************************************************************//** +* +* Gets the RTC time update API period. +* +* \return +* Period The reference number of ticks taken by the RTC clock source for one +* second. +* +*******************************************************************************/ +uint32 RTC_GetRefOneSec(void) +{ + return(RTC_tickRefOneSec); +} + + +/******************************************************************************* +* Function Name: RTC_GetDateAndTime +****************************************************************************//** +* +* Reads the current time and date. +* +* \param dateTime +* The pointer to the RTC_date_time structure to which time and date is returned. +* +*******************************************************************************/ +void RTC_GetDateAndTime(RTC_DATE_TIME* dateTime) +{ + RTC_UnixToDateTime(dateTime, (RTC_unixTime + RTC_dstTimeOffset), + RTC_INITIAL_TIME_FORMAT); +} + + +/******************************************************************************* +* Function Name: RTC_GetTime +****************************************************************************//** +* +* Reads the current time. +* +* \return +* time The time value in the format selected by the user (12/24 hr); +* The time value is available in the BCD format. +* +* \warning +* Using RTC_GetTime and RTC_GetDate API separately might result +* in errors when the time wraps around the end of the day. To avoid this, +* use RTC_GetDateAndTime API. +* +*******************************************************************************/ +uint32 RTC_GetTime(void) +{ + RTC_UnixToDateTime(&RTC_currentTimeDate, + (RTC_unixTime + RTC_dstTimeOffset), + RTC_INITIAL_TIME_FORMAT); + + return(RTC_currentTimeDate.time); +} + + +/******************************************************************************* +* Function Name: RTC_GetDate +****************************************************************************//** +* +* Reads the current date. +* +* \return +* date The value of date in the user selected format. The date value is +* available in the BCD format. +* +* \note +* Using RTC_GetTime and RTC_GetDate API separately +* might result in errors when the time wraps around the end of the day. To +* avoid this, use RTC_GetDateAndTime API. +* +*******************************************************************************/ +uint32 RTC_GetDate(void) +{ + RTC_UnixToDateTime(&RTC_currentTimeDate, + (RTC_unixTime + RTC_dstTimeOffset), + RTC_INITIAL_TIME_FORMAT); + + return(RTC_currentTimeDate.date); +} + + +#if(0u != RTC_INITIAL_ALARM_STATUS) + /******************************************************************************* + * Function Name: RTC_SetAlarmDateAndTime + ****************************************************************************//** + * + * Writes the time and date values as the current alarm time and date. + * + * \param alarmTime + * The pointer to the RTC_date_time global structure + * where new values of the alarm time and date are stored, + * see \ref RTC_DATE_TIME. + * + * \note + * Invalid time entries are written with "00:00:00:00" for the 24-hour format + * and "AM 12:00:00:00" for the 12-hour format. Invalid date entries are + * written with a date equivalent to 01-JAN-2000. + * + *******************************************************************************/ + void RTC_SetAlarmDateAndTime(const RTC_DATE_TIME* alarmTime) + { + RTC_alarmCfgTimeDate = *alarmTime; + RTC_unixTimeAlarm = + RTC_ConstructUnixAlarmTime(alarmTime, (uint8)RTC_alarmCfgMask); + } + + + /******************************************************************************* + * Function Name: RTC_GetAlarmDateAndTime + ****************************************************************************//** + * + * Reads the current alarm time and date. + * + * \param alarmTimeDate + * The pointer to the RTC_date_time structure to which the alarm + * date and time are returned, see \ref RTC_DATE_TIME. + * + *******************************************************************************/ + void RTC_GetAlarmDateAndTime(RTC_DATE_TIME* alarmTimeDate) + { + *alarmTimeDate = RTC_alarmCfgTimeDate; + } + + + /******************************************************************************* + * Function Name: RTC_SetAlarmMask + ****************************************************************************//** + * + * Writes the Alarm Mask software register with one bit per time/date entry. + * The alarm is true when all masked time/date values match the Alarm values. + * Generated only if the alarm functionality is enabled. + * + * \param mask + * The Alarm Mask software register value. The values shown below can be + * OR'ed and passed as an argument as well, see \ref group_rtc_alarm_mask. + * + *******************************************************************************/ + void RTC_SetAlarmMask(uint32 mask) + { + RTC_alarmCfgMask = (uint8)mask; + RTC_unixTimeAlarm = + RTC_ConstructUnixAlarmTime(&RTC_alarmCfgTimeDate, (uint8)mask); + } + + + /******************************************************************************* + * Function Name: RTC_GetAlarmMask + ****************************************************************************//** + * + * Reads the Alarm Mask software register. Generated only if the alarm + * functionality is enabled, see \ref group_rtc_alarm_mask. + * + *******************************************************************************/ + uint32 RTC_GetAlarmMask(void) + { + return((uint32)RTC_alarmCfgMask); + } + + + /******************************************************************************* + * Function Name: RTC_GetAlarmStatus + ****************************************************************************//** + * + * Returns the alarm status of RTC. + * + * \return + * The Alarm active status. This bit is high when the current time and date + * match the alarm time and date.
+ * 0 - The Alarm status is not active
+ * 1 - The Alarm status is active. + * + *******************************************************************************/ + uint32 RTC_GetAlarmStatus(void) + { + return((0uL != (RTC_currentTimeDate.status & (1uL << RTC_STATUS_ALARM_OFFSET))) ? + 1uL : + 0uL); + } + + + /******************************************************************************* + * Function Name: RTC_ClearAlarmStatus + ****************************************************************************//** + * + * Clears the alarm status of RTC. + * + * \note + * The Alarm active (AA) flag clears after read. This bit will be set in the next + * alarm match event only. If Alarm is set on only minutes and the alarm + * minutes is 20 minutes - the alarm triggers once every 20th minute of + * every hour. + * + *******************************************************************************/ + void RTC_ClearAlarmStatus(void) + { + RTC_currentTimeDate.status &= (~(1uL << RTC_STATUS_ALARM_OFFSET)); + RTC_alarmCurStatus = 0u; + } + + + /******************************************************************************* + * Function Name: RTC_SetAlarmHandler + ****************************************************************************//** + * + * This API sets the function to be called when the alarm goes off / triggers. + * This API is generated only if the alarm functionality is enabled in the + * customizer. + * + * \param CallbackFunction + * The callback function address. + * + * \return + * A previous callback function address. + * + *******************************************************************************/ + void* RTC_SetAlarmHandler(void (*CallbackFunction)(void)) + { + void (*tmpCallbackPtr)(void); + + tmpCallbackPtr = RTC_alarmCallbackPtr; + RTC_alarmCallbackPtr = CallbackFunction; + + return((void*)tmpCallbackPtr); + } + + + /******************************************************************************* + * Function Name: RTC_GetNexAlarmTime + ****************************************************************************//** + * + * This is an internal function that calculates the time of the next alarm + * in the UNIX format taking into account the current "Alarm Config Mask". + * + * \param curUnixTime + * The current time value in the UNIX format. + * + * \param alarmCfgMask + * The current Alarm Config Mask. + * + * \return + * Returns time of the next alarm in the UNIX format. + * + *******************************************************************************/ + uint64 RTC_GetNexAlarmTime(uint64 curUnixTime, uint8 alarmCfgMask) + { + uint32 prevVal; + uint32 nextVal; + uint32 carryFlag; + uint32 daysInMonth; + RTC_DATE_TIME curDateTime; + + carryFlag = 1u; + RTC_UnixToDateTime(&curDateTime, curUnixTime, (uint32)RTC_24_HOURS_FORMAT); + + /* Calculates Second value of next alarm time based on current time and Alarm Config Mask */ + if(0uL != ((~((uint32)alarmCfgMask)) & RTC_ALARM_SEC_MASK)) + { + prevVal = RTC_GetSecond(curDateTime.time); + nextVal = RTC_GetNextMinSec(prevVal); + curDateTime.time = RTC_SetSecond(curDateTime.time, nextVal); + carryFlag = (nextVal < prevVal) ? 1u : 0u; + } + + /* Calculates Minute value of next alarm time based on current time and Alarm Config Mask */ + if((0uL != carryFlag) && (0uL != ((~((uint32)alarmCfgMask)) & RTC_ALARM_MIN_MASK))) + { + prevVal = RTC_GetMinutes(curDateTime.time); + nextVal = RTC_GetNextMinSec(prevVal); + curDateTime.time = RTC_SetMinutes(curDateTime.time, nextVal); + carryFlag = (nextVal < prevVal) ? 1u : 0u; + } + + /* Calculates Hour value of next alarm time based on current time and Alarm Config Mask */ + if((0uL != carryFlag) && (0uL != ((~((uint32)alarmCfgMask)) & RTC_ALARM_HOUR_MASK))) + { + prevVal = RTC_GetHours(curDateTime.time); + nextVal = RTC_GetNextHour(prevVal); + curDateTime.time = RTC_SetHours(curDateTime.time, nextVal); + carryFlag = (nextVal < prevVal) ? 1u : 0u; + } + + /* Calculates Day value of next alarm time based on current time and Alarm Config Mask */ + if((0uL != carryFlag) && (0uL != ((~((uint32)alarmCfgMask)) & RTC_ALARM_DAYOFMONTH_MASK))) + { + prevVal = RTC_GetDay(curDateTime.date); + if(0u != (alarmCfgMask & RTC_ALARM_DAYOFWEEK_MASK)) + { + daysInMonth = RTC_DaysInMonth(RTC_GetMonth(curDateTime.date), + RTC_GetYear(curDateTime.date)); + nextVal = prevVal + RTC_DAYS_PER_WEEK; + nextVal = (nextVal > daysInMonth) ? (nextVal - daysInMonth) : nextVal; + } + else + { + nextVal = RTC_GetNextDay(RTC_GetYear(curDateTime.date), + RTC_GetMonth(curDateTime.date), + RTC_GetDay(curDateTime.date), + (~((uint32)alarmCfgMask))); + } + curDateTime.date = RTC_SetDay(curDateTime.date, nextVal); + carryFlag = (nextVal < prevVal) ? 1u : 0u; + } + + /* Calculates Month value of next alarm time based on current time and Alarm Config Mask */ + if((0uL != carryFlag) && (0uL != ((~((uint32)alarmCfgMask)) & RTC_ALARM_MONTH_MASK))) + { + prevVal = RTC_GetMonth(curDateTime.date); + nextVal = RTC_GetNextMonth(prevVal); + curDateTime.date = RTC_SetMonth(curDateTime.date, nextVal); + carryFlag = (nextVal < prevVal) ? 1u : 0u; + } + + /* Calculates Year value of next alarm time based on current time and Alarm Config Mask */ + if((0uL != carryFlag) && (0uL != ((~((uint32)alarmCfgMask)) & RTC_ALARM_YEAR_MASK))) + { + prevVal = RTC_GetYear(curDateTime.date); + nextVal = RTC_GetNextYear(prevVal); + curDateTime.date = RTC_SetYear(curDateTime.date, nextVal); + } + + return(RTC_DateTimeToUnix(curDateTime.date, curDateTime.time)); + } + + + /******************************************************************************* + * Function Name: RTC_ConstructUnixAlarmTime + ****************************************************************************//** + * + * This is an internal function that calculates the time of the first alarm + * in the UNIX format taking into account the current "Alarm Config Mask". + * + * \param alarmTime + * Desired alarm time in the regular time format, + * see \ref RTC_DATE_TIME + * + * \param alarmCfgMask + * The current Alarm Config Mask. + * + * \return + * time of the first alarm in the UNIX format. + * + *******************************************************************************/ + uint64 RTC_ConstructUnixAlarmTime(const RTC_DATE_TIME* alarmTime, uint8 alarmCfgMask) + { + uint32 tmpCurVal; + uint32 tmpNextVal; + uint32 carryFlag; + uint32 tmpAlarmDate; + uint32 tmpAlarmTime; + uint32 daysInMonth; + RTC_DATE_TIME curDateTime; + + tmpAlarmDate = 0u; + tmpAlarmTime = 0u; + RTC_UnixToDateTime(&curDateTime, RTC_unixTime, + (uint32)RTC_24_HOURS_FORMAT); + + /* Calculates Seconds value of first Alarm based on current time and Alarm Config Mask */ + tmpCurVal = RTC_GetSecond(curDateTime.time); + tmpNextVal = RTC_GetSecond(alarmTime->time); + carryFlag = (tmpCurVal > tmpNextVal) ? 1u : 0u; + if(0u != ((~((uint32)alarmCfgMask)) & RTC_ALARM_SEC_MASK)) + { + tmpNextVal = (0u != carryFlag) ? 0u : tmpCurVal; + } + tmpAlarmTime = RTC_SetSecond(tmpAlarmTime, tmpNextVal); + + /* Calculates Minutes value of first Alarm based on current time and Alarm Config Mask */ + tmpCurVal = RTC_GetMinutes(curDateTime.time); + if(0u != ((~((uint32)alarmCfgMask)) & RTC_ALARM_MIN_MASK)) + { + tmpNextVal = (0u != carryFlag) ? RTC_GetNextMinSec(tmpCurVal) : tmpCurVal; + } + else + { + tmpNextVal = RTC_GetMinutes(alarmTime->time); + } + carryFlag = (tmpNextVal < tmpCurVal) ? 1u : 0u; + tmpAlarmTime = RTC_SetMinutes(tmpAlarmTime, tmpNextVal); + + /* Calculates Hours value of first Alarm based on current time and Alarm Config Mask */ + tmpCurVal = RTC_GetHours(curDateTime.time); + if(0u != ((~((uint32)alarmCfgMask)) & RTC_ALARM_HOUR_MASK)) + { + tmpNextVal = (0u != carryFlag) ? RTC_GetNextHour(tmpCurVal) : tmpCurVal; + } + else + { + tmpNextVal = RTC_GetHours(alarmTime->time); + if((uint32)RTC_24_HOURS_FORMAT != RTC_GetTimeFormat(alarmTime->time)) + { + if((uint32)RTC_AM != RTC_GetAmPm(alarmTime->time)) + { + tmpNextVal += RTC_HOURS_PER_HALF_DAY; + } + } + } + carryFlag = (tmpNextVal < tmpCurVal) ? 1u : 0u; + tmpAlarmTime = RTC_SetHours(tmpAlarmTime, tmpNextVal); + + /* Calculates Day value of first Alarm based on current time and Alarm Config Mask */ + tmpCurVal = RTC_GetDay(curDateTime.date); + tmpNextVal = RTC_GetDay(alarmTime->date); + if(0u != ((~((uint32)alarmCfgMask)) & RTC_ALARM_DAYOFMONTH_MASK)) + { + if(0u != (alarmCfgMask & RTC_ALARM_DAYOFWEEK_MASK)) + { + daysInMonth = RTC_DaysInMonth(RTC_GetMonth(curDateTime.date), + RTC_GetYear(curDateTime.date)); + tmpNextVal = + (curDateTime.dayOfWeek <= alarmTime->dayOfWeek) ? (alarmTime->dayOfWeek - curDateTime.dayOfWeek) : + ((RTC_DAYS_PER_WEEK - curDateTime.dayOfWeek) + alarmTime->dayOfWeek); + tmpNextVal = tmpCurVal + tmpNextVal; + tmpNextVal = (tmpNextVal > daysInMonth) ? (tmpNextVal - daysInMonth) : tmpNextVal; + } + else + { + tmpNextVal = + (0u == carryFlag) ? tmpCurVal : RTC_GetNextDay(RTC_GetYear(curDateTime.date), + RTC_GetMonth(curDateTime.date), + tmpCurVal, + RTC_ALARM_DAYOFMONTH_MASK); + } + } + carryFlag = (tmpNextVal < tmpCurVal) ? 1u : 0u; + tmpAlarmDate = RTC_SetDay(tmpAlarmDate, tmpNextVal); + + /* Calculates Month value of first Alarm based on current time and Alarm Config Mask */ + tmpCurVal = RTC_GetMonth(curDateTime.date); + if(0u != ((~((uint32)alarmCfgMask)) & RTC_ALARM_MONTH_MASK)) + { + tmpNextVal = (0u != carryFlag) ? RTC_GetNextMonth(tmpCurVal) : tmpCurVal; + } + else + { + tmpNextVal = RTC_GetMonth(alarmTime->date); + } + carryFlag = (tmpNextVal < tmpCurVal) ? 1u : 0u; + tmpAlarmDate = RTC_SetMonth(tmpAlarmDate, tmpNextVal); + + /* Calculates Year value of first Alarm based on current time and Alarm Config Mask */ + tmpCurVal = RTC_GetYear(curDateTime.date); + if(0u != ((~((uint32)alarmCfgMask)) & RTC_ALARM_MONTH_MASK)) + { + tmpNextVal = (0u != carryFlag) ? RTC_GetNextYear(tmpCurVal) : tmpCurVal; + } + else + { + tmpNextVal = RTC_GetYear(alarmTime->date); + } + tmpAlarmDate = RTC_SetYear(tmpAlarmDate, tmpNextVal); + + return(RTC_DateTimeToUnix(tmpAlarmDate, tmpAlarmTime)); + } +#endif/* (0u != RTC_INITIAL_ALARM_STATUS) */ + + +/******************************************************************************* +* Function Name: RTC_ReadStatus +****************************************************************************//** +* +* Reads the Status software register, which has flags for DST (DST), +* Leap Year (LY), AM/PM (AM_PM). +* +* \return +* The values shown below are OR'ed and returned if more than one status +* bits are set, see \ref group_rtc_status. +* +* \note +* Reading the status without sync with the date and time read may cause an +* error due to a roll-over at AM/PM, the end of a year, the end of a day; +* RTC_GetDateAndTime() API is used to obtain the status and +* the status member of the returned structure can be checked with the masks. +* +*******************************************************************************/ +uint32 RTC_ReadStatus(void) +{ + uint32 tmpYear; + RTC_DATE_TIME tmpTimeDate; + + RTC_GetDateAndTime(&tmpTimeDate); + tmpYear = RTC_GetYear(tmpTimeDate.date); + + if(0uL != RTC_LeapYear(tmpYear)) + { + RTC_currentTimeDate.status |= (1uL << RTC_STATUS_LY_OFFSET); + } + else + { + RTC_currentTimeDate.status &= ~(1uL << RTC_STATUS_LY_OFFSET); + } + + + if(0uL != RTC_GetAmPm(tmpTimeDate.time)) + { + RTC_currentTimeDate.status |= (1uL << RTC_STATUS_AM_PM_OFFSET); + } + else + { + RTC_currentTimeDate.status &= ~(1uL << RTC_STATUS_AM_PM_OFFSET); + } + + return(RTC_currentTimeDate.status); +} + + +#if(0u != RTC_INITIAL_DST_STATUS) + /******************************************************************************* + * Function Name: RTC_SetDSTStartTime + ****************************************************************************//** + * + * Stores the DST Start time. + * + * Only generated if DST is enabled. The date passed can be relative or fixed. + * For a relative date, the user needs to provide a valid day of a week, a + * week of a month and a month in the dstStartTime structure. + * For a fixed date, the user needs to enter a valid day of a month and a month + * in the dstStartTime structure. The hour value is optional and if invalid + * taken as 00 hrs. Invalid entries are not stored and the DST start date + * retains a previous value or no value at all. + * + * \param dstStartTime + * The DST Start time register value, see \ref RTC_DST_TIME + * + * \param type + * Defines the DST operation mode, see \ref RTC_DST_DATETYPE_ENUM. + * + *******************************************************************************/ + void RTC_SetDSTStartTime(const RTC_DST_TIME* dstStartTime, + RTC_DST_DATETYPE_ENUM type) + { + RTC_dstStartTime.timeFormat = (uint8)type; + RTC_dstStartTime.hour = dstStartTime->hour; + RTC_dstStartTime.dayOfWeek = dstStartTime->dayOfWeek; + RTC_dstStartTime.weekOfMonth = dstStartTime->weekOfMonth; + RTC_dstStartTime.dayOfMonth = dstStartTime->dayOfMonth; + RTC_dstStartTime.month = dstStartTime->month; + + RTC_unixTimeDstStart = RTC_GetDstUnixTime(&RTC_dstStartTime); + + if((RTC_unixTime >= RTC_unixTimeDstStart) && + (RTC_unixTime <= RTC_unixTimeDstStop)) + { + RTC_dstStatus = 1u; + RTC_dstTimeOffset = RTC_SECONDS_PER_HOUR; + } + else + { + RTC_dstStatus = 0u; + RTC_dstTimeOffset = 0uL; + } + } + + + /******************************************************************************* + * Function Name: RTC_SetDSTStopTime + ****************************************************************************//** + * + * Stores the DST Stop time. + * + * Only generated if DST is enabled. The date passed can be relative or fixed. + * For a relative date, the user needs to provide a valid day of a week, a week + * of a month and a month in the dstStopTime structure. + * For a fixed date, the user needs to enter a valid day of a month and a month + * in the dstSoptTime structure. The hour value is optional and if invalid + * taken as 00 hrs. Invalid entries are not stored and the DST start date + * retains a previous value or no value at all. + * + * \param dstStopTime + * DST Stop time register values, see \ref RTC_DST_TIME + * + * \param type + * Defines the DST operation mode, see \ref RTC_DST_DATETYPE_ENUM. + * + *******************************************************************************/ + void RTC_SetDSTStopTime(const RTC_DST_TIME* dstStopTime, + RTC_DST_DATETYPE_ENUM type) + { + + RTC_dstStopTime.timeFormat = (uint8)type; + RTC_dstStopTime.hour = dstStopTime->hour; + RTC_dstStopTime.dayOfWeek = dstStopTime->dayOfWeek; + RTC_dstStopTime.weekOfMonth = dstStopTime->weekOfMonth; + RTC_dstStopTime.dayOfMonth = dstStopTime->dayOfMonth; + RTC_dstStopTime.month = dstStopTime->month; + + RTC_unixTimeDstStop = RTC_GetDstUnixTime(&RTC_dstStopTime); + + if((RTC_unixTime >= RTC_unixTimeDstStart) && + (RTC_unixTime <= RTC_unixTimeDstStop)) + { + RTC_dstStatus = 1u; + RTC_dstTimeOffset = RTC_SECONDS_PER_HOUR; + } + else + { + RTC_dstStatus = 0u; + RTC_dstTimeOffset = 0uL; + } + } + + + /******************************************************************************* + * Function Name: RTC_GetDstUnixTime + ****************************************************************************//** + * + * Calculates the DST Start/Stop time in the UNIX format. + * + * \param dstTime + * The DST Start/Stop time in the regular time format, + * see \ref RTC_DST_TIME + * + * \return + * The DST Start/Stop time in the UNIX format. + * + *******************************************************************************/ + uint64 RTC_GetDstUnixTime(const RTC_DST_TIME* dstTime) + { + uint32 tmpYear; + uint32 tmpDate; + uint64 dstUnixTime; + + RTC_DATE_TIME tmpTimeDate; + + RTC_UnixToDateTime(&tmpTimeDate, RTC_unixTime, RTC_INITIAL_TIME_FORMAT); + tmpYear = RTC_GetYear(tmpTimeDate.date); + + if(dstTime->timeFormat == (uint8)RTC_DST_DATE_FIXED) + { + tmpDate = RTC_ConstructDate(dstTime->month, dstTime->dayOfMonth, tmpYear); + } + else + { + tmpDate = + RTC_RelativeToFixed(dstTime->dayOfWeek, dstTime->weekOfMonth, dstTime->month, tmpYear); + } + + tmpTimeDate.time = + RTC_ConstructTime((uint32)RTC_24_HOURS_FORMAT, 0u, dstTime->hour, 0u, 0u); + dstUnixTime = RTC_DateTimeToUnix(tmpDate, tmpTimeDate.time); + + return(dstUnixTime); + } + +#endif /* (0u != RTC_INITIAL_DST_STATUS) */ + + +/******************************************************************************* +* Function Name: RTC_ConvertBCDToDec +****************************************************************************//** +* +* Converts a 4-byte BCD number into a 4-byte hexadecimal number. Each byte is +* converted individually and returned as an individual byte in the 32-bit +* variable. +* +* \param bcdNum +* A 4-byte BCD number. Each byte represents BCD. +* 0x11223344 -> 4 bytes 0x11, 0x22, 0x33 and 0x44 the in BCD format. +* +* \return +* decNum A 4-byte hexadecimal equivalent number of the BCD number. +* BCD number 0x11223344 -> returned hexadecimal number 0x0B16212C. +* +*******************************************************************************/ +uint32 RTC_ConvertBCDToDec(uint32 bcdNum) +{ + uint32 i; + uint32 mult; + uint32 retVal; + + mult = 1u; + retVal = 0u; + + for(i = 0u; i < 16u; i++) + { + retVal += (bcdNum & RTC_BCD_ONE_DIGIT_MASK) * mult; + bcdNum >>= RTC_BCD_NUMBER_SIZE; + mult *= 10u; + } + + return(retVal); +} + + +/******************************************************************************* +* Function Name: RTC_ConvertDecToBCD +****************************************************************************//** +* +* Converts a 4-byte hexadecimal number into a 4-byte BCD number. Each byte +* is converted individually and returned as an individual byte in the 32-bit +* variable. +* +* \param decNum +* A 4-byte hexadecimal number. Each byte is represented in hex. +* 0x11223344 -> 4 bytes 0x11, 0x22, 0x33 and 0x44 in the hex format. +* +* \return +* bcdNum - A 4-byte BCD equivalent of the passed hexadecimal number. +* Hexadecimal number 0x11223344 -> returned BCD number 0x17345168. +* +*******************************************************************************/ +uint32 RTC_ConvertDecToBCD(uint32 decNum) +{ + uint32 shift; + uint32 tmpVal; + uint32 retVal; + + shift = 0u; + retVal = 0u; + tmpVal = decNum; + + do + { + retVal |= ((tmpVal % 10u) << shift); + tmpVal /= 10u; + shift += RTC_BCD_NUMBER_SIZE; + } + while(tmpVal >= 10u); + + retVal |= (tmpVal << shift); + + return(retVal); +} + + +/******************************************************************************* +* Function Name: RTC_Update +****************************************************************************//** +* +* This API updates the time registers and performs alarm/DST check. +* +* This function increments the time/date registers by an input clock period. +* The period is set by RTC_SetPeriod() API or WDT period selected +* for RTC in the clocks configuration window (low frequency clocks tab) +* interface every time it is called. +* +* API is automatically mapped to the callback slot of WDT or DeepSleep Timer +* and period, if the configuration is as follows: +* 1) Option "Implement RTC update manually" in the customizer is unchecked +* 2) One of WDTs or DeeSleep Timers is selected in the "Use for RTC" panel of +* the low frequency clocks tab +* 3) Option "Implementation by IDE" is selected in the "Timer (WDT) ISR" panel. +* +* If option "Implement RTC update manually" is checked in the customizer or +* option "None" is selected in the "Use for RTC" panel, it is the user's +* responsibility: +* 1) to call this API from the clock ISR to be used as the RTC's input +* 2) set the period of the RTC through RTC_SetPeriod() API. +* +* \note Updates the Unix time register, updates the alarm and DST status. +* +*******************************************************************************/ +void RTC_Update(void) +{ + static uint32 RTC_currentTickNumber = 0u; + RTC_currentTickNumber += RTC_updateTimePeriod; + + if(RTC_currentTickNumber >= RTC_tickRefOneSec) + { + RTC_unixTime++; + RTC_currentTickNumber = + (uint32) RTC_currentTickNumber - RTC_tickRefOneSec; + + #if(0u != RTC_INITIAL_DST_STATUS) + if(RTC_unixTime == RTC_unixTimeDstStart) + { + RTC_dstStatus = 1u; + RTC_dstTimeOffset = RTC_SECONDS_PER_HOUR; + } + + if(RTC_unixTime == (RTC_unixTimeDstStop - RTC_dstTimeOffset)) + { + RTC_dstStatus = 0u; + RTC_dstTimeOffset = 0u; + RTC_unixTimeDstStart = RTC_GetDstUnixTime(&RTC_dstStartTime); + RTC_unixTimeDstStop = RTC_GetDstUnixTime(&RTC_dstStopTime); + } + #endif /* (0u != RTC_INITIAL_DST_STATUS) */ + + #if(0u != RTC_INITIAL_ALARM_STATUS) + if((RTC_unixTime + RTC_dstTimeOffset) == RTC_unixTimeAlarm) + { + RTC_currentTimeDate.status |= (1uL << RTC_STATUS_ALARM_OFFSET); + RTC_alarmCurStatus = RTC_alarmCfgMask; + + RTC_unixTimeAlarm = + RTC_GetNexAlarmTime(RTC_unixTime + RTC_dstTimeOffset, + (uint8)RTC_alarmCfgMask); + + /* Call callback function only after new alarm time is obtained. + * Cypress ticket #264756 + */ + if (RTC_alarmCallbackPtr != NULL) + { + RTC_alarmCallbackPtr(); + } + } + #endif/* (0u != RTC_INITIAL_ALARM_STATUS) */ + } +} + + +/******************************************************************************* +* Function Name: RTC_DateTimeToUnix +****************************************************************************//** +* +* This is an internal function to convert the date and time from the regular +* time format into the UNIX time format. +* +* \param inputDate +* The date in the selected in the customizer "date format" +* +* \param inputTime +* The time in the defined "time format" +* +* \return +* Returns the date and time in the UNIX format +* +*******************************************************************************/ +uint64 RTC_DateTimeToUnix(uint32 inputDate, uint32 inputTime) +{ + uint32 i; + uint32 tmpYear; + uint32 tmpMonth; + uint32 tmpVal; + uint64 unixTime; + + unixTime = 0u; + tmpYear = RTC_GetYear(inputDate); + + /* Calculate seconds from epoch start up to (but not including) current year */ + for(i = RTC_YEAR_0; i < tmpYear; i++) + { + if(0u != RTC_LeapYear(i)) + { + unixTime += RTC_SECONDS_PER_LEAP_YEAR; + } + else + { + unixTime += RTC_SECONDS_PER_NONLEAP_YEAR; + } + } + + /* Calculates how many seconds had elapsed in this year prior to the current month */ + tmpMonth = RTC_GetMonth(inputDate); + tmpVal = RTC_DaysBeforeMonth(tmpMonth, tmpYear); + + /* Calculates how many seconds are in current month days prior to today */ + unixTime += (uint64) tmpVal * RTC_SECONDS_PER_DAY; + unixTime += ((uint64) RTC_GetDay(inputDate) - 1u) * RTC_SECONDS_PER_DAY; + + /* Calculates how many seconds have elapsed today up to the current hour */ + tmpVal = RTC_GetHours(inputTime); + if ((uint32)RTC_24_HOURS_FORMAT != RTC_GetTimeFormat(inputTime)) + { + uint32 curAmpm; + + curAmpm = RTC_GetAmPm(inputTime); + + /* Add 12 hours as it is past midday period */ + if (((uint32)RTC_AM != curAmpm) && (tmpVal < 12u)) + { + tmpVal += RTC_HOURS_PER_HALF_DAY; + } + /* Set hours to zero as it is a midnight */ + else if (((uint32)RTC_AM == curAmpm) && (tmpVal == 12u)) + { + tmpVal = 0U; + } + else + { + /* Do nothing */ + } + } + unixTime += (uint64)tmpVal * RTC_SECONDS_PER_HOUR; + + /* Calculates how many seconds have elapsed today up to the current minute */ + unixTime += ((uint64) RTC_GetMinutes(inputTime)) * RTC_SECONDS_PER_MINUTE; + + /* Add remaining seconds of current minute */ + unixTime += RTC_GetSecond(inputTime); + + return(unixTime); +} + + +/******************************************************************************* +* Function Name: RTC_UnixToDateTime +****************************************************************************//** +* +* This is an internal function to convert the date and time from the UNIX time +* format into the regular time format +* +* \param RTC_DATE_TIME* dateTime +* The time and date structure which will be updated time from unixTime value +* +* \param unixTime +* The time in unix format +* +* \param timeFormat +* dst format of time, see \ref RTC_DST_DATETYPE_ENUM +* +*******************************************************************************/ +void RTC_UnixToDateTime(RTC_DATE_TIME* dateTime, uint64 unixTime, uint32 timeFormat) +{ + uint32 tmpMinute; + uint32 tmpHour; + uint32 tmpAmPmState; + + uint32 tmpDay; + uint32 tmpMonth; + uint32 tmpYear; + + uint32 tmpVar; + + tmpAmPmState = 0u; + tmpYear = RTC_YEAR_0; + tmpVar = RTC_SECONDS_PER_NONLEAP_YEAR; + + /* Calculates current year value. Variable tmpYear + * increments while it contains value greater than number + * of seconds in current year. + */ + while(unixTime >= tmpVar) + { + unixTime -= tmpVar; + tmpYear++; + + if(0u != RTC_LeapYear(tmpYear)) + { + tmpVar = RTC_SECONDS_PER_LEAP_YEAR; + } + else + { + tmpVar = RTC_SECONDS_PER_NONLEAP_YEAR; + } + } + + /* Calculates current month value. The tmpMonth variable increments while + * unixTime variable value is greater than time interval from beginning + * of current year to beginning of current month + */ + tmpMonth = (uint32)RTC_JANUARY; + tmpVar = RTC_DaysInMonth(tmpMonth, tmpYear) * RTC_SECONDS_PER_DAY; + + while(unixTime >= tmpVar) + { + unixTime -= tmpVar; + tmpMonth++; + tmpVar = RTC_DaysInMonth(tmpMonth, tmpYear) * RTC_SECONDS_PER_DAY; + } + + /* Calculates current day value */ + tmpDay = (uint32) (unixTime / RTC_SECONDS_PER_DAY); + tmpVar = tmpDay * RTC_SECONDS_PER_DAY; + unixTime -= (unixTime >= tmpVar) ? tmpVar : 0u; + tmpDay += 1u; + + /* Calculates current hour value. If function works in 12-Hour mode, + * it converts time to 12-Hours mode and calculates AmPm status */ + tmpHour = (uint32) (unixTime / RTC_SECONDS_PER_HOUR); + tmpVar = tmpHour * RTC_SECONDS_PER_HOUR; + if((uint32)RTC_24_HOURS_FORMAT != timeFormat) + { + if(unixTime > RTC_UNIX_TIME_PM) + { + tmpAmPmState = RTC_PM; + tmpHour = (tmpHour > 12u) ? (tmpHour - 12u) : tmpHour; + } + else + { + tmpAmPmState = RTC_AM; + tmpHour = (0u != tmpHour) ? tmpHour : 12u; + } + } + unixTime -= (unixTime >= tmpVar) ? tmpVar : 0u; + + /* Calculates current minute */ + tmpMinute = (uint32) (unixTime / RTC_SECONDS_PER_MINUTE); + tmpVar = tmpMinute * RTC_SECONDS_PER_MINUTE; + + /* Calculates current second */ + unixTime -= (unixTime >= (uint64) tmpVar) ? (uint64) tmpVar : 0ul; + + dateTime->date = RTC_ConstructDate(tmpMonth, tmpDay, tmpYear); + dateTime->time = RTC_ConstructTime(timeFormat, tmpAmPmState, tmpHour, tmpMinute, (uint32) unixTime); + dateTime->dayOfWeek = RTC_GetDayOfWeek(tmpDay, tmpMonth, tmpYear); +} + + +/******************************************************************************* +* Function Name: RTC_RelativeToFixed +****************************************************************************//** +* +* This is an internal function to convert a relative date into a fixed date. +* +* \param dayOfWeek +* A day of a week, see \ref group_rtc_day_of_the_week +* +* \param weekOfMonth +* A week of a month, see \ref group_rtc_dst_week_of_month +* +* \param month +* A month of a year, see \ref group_rtc_month +* +* \param year +* A year value +* +* \return A date in the "date format" +* +*******************************************************************************/ +uint32 RTC_RelativeToFixed(uint32 dayOfWeek, uint32 weekOfMonth, uint32 month, uint32 year) +{ + uint32 curDay; + uint32 curWeek; + uint32 daysInMonth; + uint32 dayOfMonthTmp; + + uint32 retVal; + + curDay = 1u; + curWeek = (uint32)RTC_FIRST; + daysInMonth = RTC_DaysInMonth(month, year); + dayOfMonthTmp = curDay; + + while((curWeek <= weekOfMonth) && (curDay <= daysInMonth)) + { + if(dayOfWeek == RTC_GetDayOfWeek(curDay, month, year)) + { + dayOfMonthTmp = curDay; + curWeek++; + } + curDay++; + } + + retVal = RTC_ConstructDate(month, dayOfMonthTmp, year); + + return(retVal); +} + + +/******************************************************************************* +* Function Name: RTC_DaysInMonth +****************************************************************************//** +* +* Returns a number of days in a month passed through the parameters. +* +* \param month +* A month of a year, see \ref group_rtc_month. +* +* \param year +* A year value. +* +* \return +* A number of days in a month in the year passed through the parameters +* +*******************************************************************************/ +uint32 RTC_DaysInMonth(uint32 month, uint32 year) +{ + uint32 retVal; + + retVal = RTC_daysInMonthTbl[month - 1u]; + if((uint32)RTC_FEBRUARY == month) + { + if(0u != RTC_LeapYear(year)) + { + retVal++; + } + } + + return(retVal); +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/RTC.h b/cores/asr650x/projects/PSoC4/RTC.h new file mode 100644 index 00000000..c2e52401 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/RTC.h @@ -0,0 +1,1425 @@ +/***************************************************************************//** +* \file Name: RTC.h +* \version 1.30 +* +* This file provides constants and parameter values for the RTC_P4 Component. +* +******************************************************************************** +* Copyright 2015-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_RTC_P4_RTC_H) +#define CY_RTC_P4_RTC_H + +#include +#include + + +/******************************************************************************* +* Data types definition +*******************************************************************************/ +/** +* \addtogroup group_enums +* \{ +*/ +/** Daylight saving Time format enumeration */ +typedef enum +{ + RTC_DST_DATE_RELATIVE = 0u, /**< Relative DST format */ + RTC_DST_DATE_FIXED = 1u /**< Fixed DST format */ +}RTC_DST_DATETYPE_ENUM; +/** \} group_enums */ + +/** +* \addtogroup group_structures +* \{ +*/ + +/** RTC_DATE_TIME structure is the data structure that is used to +* save the current time and date (RTC_currentTimeDate), and Alarm time and date +*(RTC_alarmCfgTimeDate) +* +*/ +typedef struct +{ + uint32 time; /**< Time in the format used in API*/ + uint32 date; /**< Date in the format used in API*/ + uint32 dayOfWeek; /**< Day of the week, see \ref group_rtc_day_of_the_week */ + uint32 status; /**< RTC status, see \ref group_rtc_status */ +}RTC_DATE_TIME; + +/* +* RTC_DST_TIME structure is the data structure that is used to +* save time and date values for Daylight Savings Time Start and Stop +* (RTC_dstTimeDateStart and RTC_dstTimeDateStop) +*/ +typedef struct +{ + uint32 hour; /**< Hour value */ + uint32 dayOfWeek; /**< Day of the week, see \ref group_rtc_day_of_the_week */ + uint32 dayOfMonth; /**< Day of the month */ + uint32 weekOfMonth; /**< Week of the month, see \ref group_rtc_dst_week_of_month */ + uint32 month; /**< Month value, see \ref group_rtc_month */ + uint8 timeFormat; /**< The DST operation mode, see \ref + RTC_DST_DATETYPE_ENUM */ +}RTC_DST_TIME; +/** \} group_structures */ + +/******************************************************************************* +* Enumerated Types and Parameters +*******************************************************************************/ +/* Time Format setting constants */ +#define RTC__HOUR_12 1 +#define RTC__HOUR_24 0 + +/* Date Format setting constants */ +#define RTC__MM_DD_YYYY 0 +#define RTC__DD_MM_YYYY 1 +#define RTC__YYYY_MM_DD 2 + +/* Date Type setting constants */ +#define RTC__RELATIVE 0 +#define RTC__FIXED 1 + +/* DST Hour setting constants */ +#define RTC__H0000 0 +#define RTC__H0100 1 +#define RTC__H0200 2 +#define RTC__H0300 3 +#define RTC__H0400 4 +#define RTC__H0500 5 +#define RTC__H0600 6 +#define RTC__H0700 7 +#define RTC__H0800 8 +#define RTC__H0900 9 +#define RTC__H1000 10 +#define RTC__H1100 11 +#define RTC__H1200 12 +#define RTC__H1300 13 +#define RTC__H1400 14 +#define RTC__H1500 15 +#define RTC__H1600 16 +#define RTC__H1700 17 +#define RTC__H1800 18 +#define RTC__H1900 19 +#define RTC__H2000 20 +#define RTC__H2100 21 +#define RTC__H2200 22 +#define RTC__H2300 23 + +/* DST DayOfWeek setting constants */ +#define RTC__SUNDAY 1 +#define RTC__MONDAY 2 +#define RTC__TUESDAY 3 +#define RTC__WEDNESDAY 4 +#define RTC__THURSDAY 5 +#define RTC__FRIDAY 6 +#define RTC__SATURDAY 7 + +/* DST Month setting constants */ +#define RTC__JAN 1 +#define RTC__FEB 2 +#define RTC__MAR 3 +#define RTC__APR 4 +#define RTC__MAY 5 +#define RTC__JUN 6 +#define RTC__JUL 7 +#define RTC__AUG 8 +#define RTC__SEP 9 +#define RTC__OCT 10 +#define RTC__NOV 11 +#define RTC__DEC 12 + +/* DST WeekOfMonth setting constants */ +#define RTC__FIRST 1 +#define RTC__SECOND 2 +#define RTC__THIRD 3 +#define RTC__FOURTH 4 +#define RTC__FIFTH 5 +#define RTC__LAST 6 + + +#define RTC_INITIAL_DATA_FORMAT (0u) +#define RTC_INITIAL_TIME_FORMAT (0u) +#define RTC_INITIAL_UPDATE_MODE (0u) +#define RTC_INITIAL_SECOND (0u) +#define RTC_INITIAL_MINUTE (0u) +#define RTC_INITIAL_HOUR (0u) +#define RTC_INITIAL_DAY (1u) +#define RTC_INITIAL_MONTH (1u) +#define RTC_INITIAL_YEAR (1970u) + +#define RTC_INITIAL_ALARM_STATUS (1u) + +#define RTC_INITIAL_DST_STATUS (0u) +#define RTC_INITIAL_DST_DATE_TYPE (0u) +#define RTC_INITIAL_DST_START_MONTH (3uL) +#define RTC_INITIAL_DST_START_WOM (6uL) +#define RTC_INITIAL_DST_START_DOM (22uL) +#define RTC_INITIAL_DST_START_DOW (1uL) +#define RTC_INITIAL_DST_START_HRS (0uL) +#define RTC_INITIAL_DST_STOP_MONTH (10uL) +#define RTC_INITIAL_DST_STOP_DOM (22uL) +#define RTC_INITIAL_DST_STOP_DOW (1uL) +#define RTC_INITIAL_DST_STOP_WOM (6uL) +#define RTC_INITIAL_DST_STOP_HRS (0uL) + +/** +* \addtogroup group_constants +* \{ +*/ + +/** +* \defgroup group_rtc_day_of_the_week Day of the week definitions +* \{ +* Definitions of days in the week +*/ +#define RTC_SUNDAY (RTC__SUNDAY) /**< Sequential number of Sunday in the week */ +#define RTC_MONDAY (RTC__MONDAY) /**< Sequential number of Monday in the week */ +#define RTC_TUESDAY (RTC__TUESDAY) /**< Sequential number of Tuesday in the week */ +#define RTC_WEDNESDAY (RTC__WEDNESDAY) /**< Sequential number of Wednesday in the week */ +#define RTC_THURSDAY (RTC__THURSDAY) /**< Sequential number of Thursday in the week */ +#define RTC_FRIDAY (RTC__FRIDAY) /**< Sequential number of Friday in the week */ +#define RTC_SATURDAY (RTC__SATURDAY) /**< Sequential number of Saturday in the week */ +/** \} group_rtc_day_of_the_week */ + +/** +* \defgroup group_rtc_dst_week_of_month DST Week of month setting constants definitions +* \{ +* Week of month setting constants definitions for Daylight Saving Time feature +*/ +#define RTC_FIRST (RTC__FIRST) /**< First week in the month */ +#define RTC_SECOND (RTC__SECOND) /**< Second week in the month */ +#define RTC_THIRD (RTC__THIRD) /**< Third week in the month */ +#define RTC_FOURTH (RTC__FOURTH) /**< Fourth week in the month */ +#define RTC_FIFTH (RTC__FIFTH) /**< Fifth week in the month */ +#define RTC_LAST (RTC__LAST) /**< Last week in the month */ +/** \} group_rtc_dst_week_of_month */ + +/** +* \defgroup group_rtc_month Month definitions +* \{ +* Constants definition for Months +*/ +#define RTC_JANUARY (RTC__JAN) /**< Sequential number of January in the year */ +#define RTC_FEBRUARY (RTC__FEB) /**< Sequential number of February in the year */ +#define RTC_MARCH (RTC__MAR) /**< Sequential number of March in the year */ +#define RTC_APRIL (RTC__APR) /**< Sequential number of April in the year */ +#define RTC_MAY (RTC__MAY) /**< Sequential number of May in the year */ +#define RTC_JUNE (RTC__JUN) /**< Sequential number of June in the year */ +#define RTC_JULY (RTC__JUL) /**< Sequential number of July in the year */ +#define RTC_AUGUST (RTC__AUG) /**< Sequential number of August in the year */ +#define RTC_SEPTEMBER (RTC__SEP) /**< Sequential number of September in the year */ +#define RTC_OCTOBER (RTC__OCT) /**< Sequential number of October in the year */ +#define RTC_NOVEMBER (RTC__NOV) /**< Sequential number of November in the year */ +#define RTC_DECEMBER (RTC__DEC) /**< Sequential number of December in the year */ +/** \} group_rtc_month */ + +/** +* \defgroup group_rtc_am_pm AM/PM status definitions +* \{ +* Definitions for 12 hour format for indicating the AM/PM period of day +*/ +#define RTC_AM (0u) /**< AM period of day */ +#define RTC_PM (1u) /**< PM period of day */ +/** \} group_rtc_am_pm */ + +/** +* \defgroup group_rtc_hour_format Hour format definitions +* \{ +* Definitions for hour format +*/ +#define RTC_12_HOURS_FORMAT (RTC__HOUR_12) /**< The 12 hour (AM/PM) format */ +#define RTC_24_HOURS_FORMAT (RTC__HOUR_24) /**< The 24 hour format */ +/** \} group_rtc_hour_format */ + +/** +* \defgroup group_rtc_days_in_month Number of days in month definitions +* \{ +* Definition of days in current month +*/ +#define RTC_DAYS_IN_JANUARY (31u) /**< Number of days in January */ +#define RTC_DAYS_IN_FEBRUARY (28u) /**< Number of days in February */ +#define RTC_DAYS_IN_MARCH (31u) /**< Number of days in March */ +#define RTC_DAYS_IN_APRIL (30u) /**< Number of days in April */ +#define RTC_DAYS_IN_MAY (31u) /**< Number of days in May */ +#define RTC_DAYS_IN_JUNE (30u) /**< Number of days in June */ +#define RTC_DAYS_IN_JULY (31u) /**< Number of days in July */ +#define RTC_DAYS_IN_AUGUST (31u) /**< Number of days in August */ +#define RTC_DAYS_IN_SEPTEMBER (30u) /**< Number of days in September */ +#define RTC_DAYS_IN_OCTOBER (31u) /**< Number of days in October */ +#define RTC_DAYS_IN_NOVEMBER (30u) /**< Number of days in November */ +#define RTC_DAYS_IN_DECEMBER (31u) /**< Number of days in December */ +/** \} group_rtc_days_in_month */ + +/** +* \defgroup group_rtc_status Definitions of the RTC status values +* \{ +* Definitions for status software register, which has flags for DST (DST), +* Leap Year (LY), AM/PM (AM_PM). +*/ + +/** Status of Daylight Saving Time. This bit +* goes high when the current time and date match the DST time and date and the +* time is incremented. This bit goes low after the DST interval and the time is +* decremented. +*/ +#define RTC_STATUS_DST (1uL << RTC_STATUS_DST_OFFSET) + +/** Status of Leap Year. This bit goes high when the current year is a leap year */ +#define RTC_STATUS_LY (1uL << RTC_STATUS_LY_OFFSET) + +/** Status of Current Time. This bit is low from midnight to noon and high from +* noon to midnight. */ +#define RTC_STATUS_AM_PM (1uL << RTC_STATUS_AM_PM_OFFSET) +/** \} group_rtc_status */ + +/** +* \defgroup group_rtc_alarm_mask Definitions for Alarm Mask software register +* \{ +* Definitions for Alarm Mask software register. These masks allow +* matching the alarm value register with the current value register. +*/ + +/** The second alarm mask allows matching the alarm second register with the +* current second register. +*/ +#define RTC_ALARM_SEC_MASK (0x00000001uL) + +/** The minute alarm mask allows matching the alarm minute register with the +* current minute register. +*/ +#define RTC_ALARM_MIN_MASK (0x00000002uL) + +/** The hour alarm mask allows matching the alarm hour register with the +* current hour register. +*/ +#define RTC_ALARM_HOUR_MASK (0x00000004uL) + +/** The day of the week alarm mask allows matching the alarm hour register with +* the current day of the week register. +*/ +#define RTC_ALARM_DAYOFWEEK_MASK (0x00000008uL) + +/** The day of the Month alarm mask allows matching the alarm hour register with +* the current day of the Month register. +*/ +#define RTC_ALARM_DAYOFMONTH_MASK (0x00000010uL) + +/** The month alarm mask allows matching the alarm hour register with the +* current month register. +*/ +#define RTC_ALARM_MONTH_MASK (0x00000020uL) + +/** The year alarm mask allows matching the alarm hour register with the +* current year register. +*/ +#define RTC_ALARM_YEAR_MASK (0x00000040uL) + +/** \} group_rtc_alarm_mask */ +/** \} group_constants */ + +#define RTC_DAYS_PER_WEEK (7u) + +#define RTC_MONTHS_PER_YEAR (12uL) + +#define RTC_HOURS_PER_DAY (24uL) +#define RTC_HOURS_PER_HALF_DAY (12uL) + +#define RTC_SECONDS_PER_MINUTE (60uL) +#define RTC_SECONDS_PER_HOUR (3600uL) +#define RTC_SECONDS_PER_DAY (24uL * 3600uL) + +#define RTC_SECONDS_PER_LEAP_YEAR (366uL * 24uL * 3600uL) +#define RTC_SECONDS_PER_NONLEAP_YEAR (365uL * 24uL * 3600uL) + +#define RTC_UNIX_TIME_PM ((12uL * 3600uL) + 1uL) + +/* Unix time begins in 1970 year */ +#define RTC_YEAR_0 (1970u) + +/* Definition of date register fields */ +#if(RTC_INITIAL_DATA_FORMAT == RTC__MM_DD_YYYY) + #define RTC_10_MONTH_OFFSET (28u) + #define RTC_MONTH_OFFSET (24u) + #define RTC_10_DAY_OFFSET (20u) + #define RTC_DAY_OFFSET (16u) + #define RTC_1000_YEAR_OFFSET (12u) + #define RTC_100_YEAR_OFFSET (8u) + #define RTC_10_YEAR_OFFSET (4u) + #define RTC_YEAR_OFFSET (0u) +#elif(RTC_INITIAL_DATA_FORMAT == RTC__DD_MM_YYYY) + #define RTC_10_MONTH_OFFSET (20u) + #define RTC_MONTH_OFFSET (16u) + #define RTC_10_DAY_OFFSET (28u) + #define RTC_DAY_OFFSET (24u) + #define RTC_1000_YEAR_OFFSET (12u) + #define RTC_100_YEAR_OFFSET (8u) + #define RTC_10_YEAR_OFFSET (4u) + #define RTC_YEAR_OFFSET (0u) +#else + #define RTC_10_MONTH_OFFSET (12u) + #define RTC_MONTH_OFFSET (8u) + #define RTC_10_DAY_OFFSET (4u) + #define RTC_DAY_OFFSET (0u) + #define RTC_1000_YEAR_OFFSET (28u) + #define RTC_100_YEAR_OFFSET (24u) + #define RTC_10_YEAR_OFFSET (20u) + #define RTC_YEAR_OFFSET (16u) +#endif /* (RTC_INITIAL_DATA_FORMAT == RTC__MM_DD_YYYY) */ + +#define RTC_10_MONTH_MASK (0x00000001uL << RTC_10_MONTH_OFFSET) +#define RTC_MONTH_MASK (0x0000000FuL << RTC_MONTH_OFFSET) +#define RTC_10_DAY_MASK (0x00000003uL << RTC_10_DAY_OFFSET) +#define RTC_DAY_MASK (0x0000000FuL << RTC_DAY_OFFSET) +#define RTC_1000_YEAR_MASK (0x00000003uL << RTC_1000_YEAR_OFFSET) +#define RTC_100_YEAR_MASK (0x0000000FuL << RTC_100_YEAR_OFFSET) +#define RTC_10_YEAR_MASK (0x0000000FuL << RTC_10_YEAR_OFFSET) +#define RTC_YEAR_MASK (0x0000000FuL << RTC_YEAR_OFFSET) + +#define RTC_MONTH_FULL_MASK (RTC_10_MONTH_MASK | RTC_MONTH_MASK) +#define RTC_DAY_FULL_MASK (RTC_10_DAY_MASK | RTC_DAY_MASK) +#define RTC_YEAR_FULL_MASK (RTC_1000_YEAR_MASK | RTC_100_YEAR_MASK |\ + RTC_10_YEAR_MASK | RTC_YEAR_MASK) + +/* Definition of time register fields */ +#define RTC_TIME_FORMAT_OFFSET (23u) +#define RTC_PERIOD_OF_DAY_OFFSET (22u) +#define RTC_10_HOURS_OFFSET (20u) +#define RTC_HOURS_OFFSET (16u) +#define RTC_10_MINUTES_OFFSET (12u) +#define RTC_MINUTES_OFFSET (8u) +#define RTC_10_SECONDS_OFFSET (4u) +#define RTC_SECONDS_OFFSET (0u) + +#define RTC_TIME_FORMAT_MASK (0x00000001uL << RTC_TIME_FORMAT_OFFSET) +#define RTC_PERIOD_OF_DAY_MASK (0x00000001uL << RTC_PERIOD_OF_DAY_OFFSET) +#define RTC_10_HOURS_MASK (0x00000003uL << RTC_10_HOURS_OFFSET) +#define RTC_HOURS_MASK (0x0000000FuL << RTC_HOURS_OFFSET) +#define RTC_10_MINUTES_MASK (0x00000007uL << RTC_10_MINUTES_OFFSET) +#define RTC_MINUTES_MASK (0x0000000FuL << RTC_MINUTES_OFFSET) +#define RTC_10_SECONDS_MASK (0x00000007uL << RTC_10_SECONDS_OFFSET) +#define RTC_SECONDS_MASK (0x0000000FuL << RTC_SECONDS_OFFSET) + +#define RTC_HOURS_FULL_MASK (RTC_10_HOURS_MASK | RTC_HOURS_MASK) +#define RTC_MINUTES_FULL_MASK (RTC_10_MINUTES_MASK | RTC_MINUTES_MASK) +#define RTC_SECONDS_FULL_MASK (RTC_10_SECONDS_MASK | RTC_SECONDS_MASK) + +#define RTC_STATUS_DST_OFFSET (1u) +#define RTC_STATUS_ALARM_OFFSET (2u) +#define RTC_STATUS_LY_OFFSET (3u) +#define RTC_STATUS_AM_PM_OFFSET (4u) + +/* Number of bits per one BCD digit */ +#define RTC_BCD_NUMBER_SIZE (4u) +#define RTC_BCD_ONE_DIGIT_MASK (0x0000000FuL) + + +/******************************************************************************* +* External Variables +*******************************************************************************/ +/** +* \addtogroup group_globals +* \{ +*/ + +/** +* Indicates whether the RTC has been initialized; The variable is initialized to +* 0 and set to 1 the first time RTC_Start() is called. This allows the component +* to restart without reinitialization after the first call to the RTC_Start() +* routine. +*/ +extern uint8 RTC_initVar; + +/** The DST start/stop status */ +extern uint8 RTC_dstStatus; + +/** +* The uint64 variable represents the standard Unix time (number of seconds +* elapsed from January 1, 1970 00:00 hours UTC) in 64-bit +*/ +extern volatile uint64 RTC_unixTime; + +/** The values for the time and date of the DST start */ +extern RTC_DST_TIME RTC_dstStartTime; + +/** The values for the time and date of the DST stop */ +extern RTC_DST_TIME RTC_dstStopTime; + +/** +* The last updated time and date values are stored in this structure (update +* happens in Get time/date APIs) +*/ +extern RTC_DATE_TIME RTC_currentTimeDate; + +/** The alarm time and date values are stored in this variable */ +extern RTC_DATE_TIME RTC_alarmCfgTimeDate; + +/** +* This variable is used to mask alarm events; mask seconds alarm, mask minutes +* alarm, and so on. It will have bit masks for each time item masking that item +* for alarm generation +*/ +extern uint32 RTC_alarmCfgMask; + +/** +* This variable is used to indicate current active alarm status per time item +* used in the alarm; whether seconds alarm is active, minute's alarm is active, +* and so on. It will have bit masks for each time item (seconds, minutes, hours, +* day, and so on) showing the status +*/ +extern uint32 RTC_alarmCurStatus; + +/** \} group_globals */ + +extern void (*RTC_alarmCallbackPtr)(void); + +extern const uint16 RTC_daysBeforeMonthTbl[RTC_MONTHS_PER_YEAR]; +extern const uint8 RTC_daysInMonthTbl[RTC_MONTHS_PER_YEAR]; + + +/******************************************************************************* +* Function Prototypes +*******************************************************************************/ +/** +* \addtogroup group_general +* \{ +*/ +void RTC_Start(void); +void RTC_Stop(void); +void RTC_Init(void); +void RTC_SetUnixTime(uint64 unixTime); +uint64 RTC_GetUnixTime(void); +void RTC_SetPeriod(uint32 ticks, uint32 refOneSecTicks); +uint32 RTC_GetPeriod(void); +uint32 RTC_GetRefOneSec(void); +void RTC_SetDateAndTime(uint32 inputTime, uint32 inputDate); +void RTC_GetDateAndTime(RTC_DATE_TIME* dateTime); +uint32 RTC_GetTime(void); +uint32 RTC_GetDate(void); +void RTC_SetAlarmDateAndTime(const RTC_DATE_TIME* alarmTime); +void RTC_GetAlarmDateAndTime(RTC_DATE_TIME* alarmTimeDate); +void RTC_SetAlarmMask(uint32 mask); +uint32 RTC_GetAlarmMask(void); +uint32 RTC_ReadStatus(void); +uint32 RTC_GetAlarmStatus(void); +void RTC_ClearAlarmStatus(void); +void RTC_SetDSTStartTime(const RTC_DST_TIME* dstStartTime, + RTC_DST_DATETYPE_ENUM type); +void RTC_SetDSTStopTime(const RTC_DST_TIME* dstStopTime, + RTC_DST_DATETYPE_ENUM type); +uint32 RTC_ConvertBCDToDec(uint32 bcdNum); +uint32 RTC_ConvertDecToBCD(uint32 decNum); +void RTC_Update(void); +void* RTC_SetAlarmHandler(void (*CallbackFunction)(void)); + +static uint32 RTC_ConstructDate(uint32 month, uint32 day, uint32 year); +static uint32 RTC_ConstructTime(uint32 timeFormat, uint32 stateAmPm, uint32 hour, uint32 min, uint32 sec); +/** \} group_general */ + +static uint32 RTC_GetTimeFormat(uint32 inputTime); +static uint32 RTC_SetTimeFormat(uint32 inputTime, uint32 timeFormat); + +/** +* \addtogroup group_general +* \{ +*/ +static uint32 RTC_LeapYear(uint32 year); +static uint32 RTC_IsBitSet(uint32 var, uint32 mask); +static uint32 RTC_GetSecond(uint32 inputTime); +static uint32 RTC_GetMinutes(uint32 inputTime); +static uint32 RTC_GetHours(uint32 inputTime); +static uint32 RTC_GetAmPm(uint32 inputTime); +static uint32 RTC_GetDay(uint32 date); +static uint32 RTC_GetMonth(uint32 date); +static uint32 RTC_GetYear(uint32 date); +/** \} group_general */ + +static uint32 RTC_SetSecond(uint32 inputTime, uint32 inputSecond); +static uint32 RTC_SetMinutes(uint32 inputTime, uint32 inputMinute); +static uint32 RTC_SetHours(uint32 inputTime, uint32 inputHours); +static uint32 RTC_SetAmPm(uint32 inputTime, uint32 periodOfDay); +static uint32 RTC_SetDay(uint32 inputDate, uint32 inputDay); +static uint32 RTC_SetMonth(uint32 inputDate, uint32 inputMonth); +static uint32 RTC_SetYear(uint32 inputDate, uint32 inputYear); + +uint64 RTC_ConstructUnixAlarmTime(const RTC_DATE_TIME* alarmTime, uint8 alarmCfgMask); +uint64 RTC_GetDstUnixTime(const RTC_DST_TIME* dstTime); +uint64 RTC_GetNexAlarmTime(uint64 curUnixTime, uint8 alarmCfgMask); + +static uint32 RTC_GetNextMinSec(uint32 curVal); +static uint32 RTC_GetNextHour(uint32 curVal); +static uint32 RTC_GetNextDay(uint32 curYear, uint32 curMonth, uint32 curDay, uint32 alarmCfgMask); +static uint32 RTC_GetNextMonth(uint32 curMonth); +static uint32 RTC_GetNextYear(uint32 curYear); +static uint32 RTC_GetDayOfWeek(uint32 day, uint32 month, uint32 year); +static uint32 RTC_DaysBeforeMonth(uint32 month, uint32 year); + +uint32 RTC_DaysInMonth(uint32 month, uint32 year); + +/** +* \addtogroup group_general +* \{ +*/ +void RTC_UnixToDateTime(RTC_DATE_TIME* dateTime, uint64 unixTime, uint32 timeFormat); +uint64 RTC_DateTimeToUnix(uint32 inputDate, uint32 inputTime); + +#if defined(CYDEV_RTC_SOURCE_WDT) + #if((0u != CYDEV_WDT_GENERATE_ISR) && (0u == RTC_INITIAL_UPDATE_MODE)) + static void RTC_CySysRtcSetCallback(uint32 wdtNumber); + static void RTC_CySysRtcResetCallback(uint32 wdtNumber); + #endif /* ((0u != CYDEV_WDT_GENERATE_ISR) && (0u == RTC_INITIAL_UPDATE_MODE)) */ +#endif /* (CYDEV_RTC_SOURCE_WDT) */ + +/** \} group_general */ + +uint32 RTC_RelativeToFixed(uint32 dayOfWeek, uint32 weekOfMonth, uint32 month, uint32 year); + + + +/******************************************************************************* +* Function Name: RTC_IsBitSet +****************************************************************************//** +* +* Checks the state of a bit passed through parameter. +* +* \param var +* The variable to be checked. +* +* \param mask +* The mask for a bit to be checked. +* +* \return +* 0u - Bit is not set.
1u - Bit is set. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_IsBitSet(uint32 var, uint32 mask) +{ + return ((mask == (var & mask)) ? 1Lu : 0Lu); +} + + +/******************************************************************************* +* Function Name: RTC_LeapYear +****************************************************************************//** +* +* Checks whether the year passed through the parameter is leap or no. +* +* \param year +* The year to be checked. +* +* \return +* 0u - The year is not leap
1u - The year is leap. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_LeapYear(uint32 year) +{ + uint32 retVal; + + if(((0u == (year % 4Lu)) && (0u != (year % 100Lu))) || (0u == (year % 400Lu))) + { + retVal = 1uL; + } + else + { + retVal = 0uL; + } + + return(retVal); +} + + +/******************************************************************************* +* Function Name: RTC_GetSecond +****************************************************************************//** +* +* Returns the seconds value from the time value that is passed as a/the +* parameter. +* +* \param inputTime +* The time value. +* +* \return +* The seconds value. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetSecond(uint32 inputTime) +{ + uint32 retVal; + + retVal = ((inputTime & RTC_10_SECONDS_MASK) >> RTC_10_SECONDS_OFFSET) * 10u; + retVal += (inputTime & RTC_SECONDS_MASK) >> RTC_SECONDS_OFFSET; + + return (retVal); +} + + +/******************************************************************************* +* Function Name: RTC_GetMinutes +****************************************************************************//** +* +* Returns the minutes value from the time value that is passed as a/the +* parameter. +* +* \param inputTime +* The time value. +* +* \return +* The minutes value. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetMinutes(uint32 inputTime) +{ + uint32 retVal; + + retVal = ((inputTime & RTC_10_MINUTES_MASK) >> RTC_10_MINUTES_OFFSET) * 10u; + retVal += (inputTime & RTC_MINUTES_MASK) >> RTC_MINUTES_OFFSET; + + return (retVal); +} + + +/******************************************************************************* +* Function Name: RTC_GetHours +****************************************************************************//** +* +* Returns the hours value from the time value that is passed as a/the parameter. +* +* \param inputTime +* The time value. +* +* \return +* The hours value. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetHours(uint32 inputTime) +{ + uint32 retVal; + + retVal = ((inputTime & RTC_10_HOURS_MASK) >> RTC_10_HOURS_OFFSET) * 10u; + retVal += (inputTime & RTC_HOURS_MASK) >> RTC_HOURS_OFFSET; + + return (retVal); +} + + +/******************************************************************************* +* Function Name: RTC_GetAmPm +****************************************************************************//** +* +* Returns the AM/PM status from the time value that is passed as parameter. +* +* \param inputTime +* The time value. +* +* \return +* The am/pm period of day, see \ref group_rtc_am_pm. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetAmPm(uint32 inputTime) +{ + return (RTC_IsBitSet(inputTime, RTC_PERIOD_OF_DAY_MASK)); +} + + +/******************************************************************************* +* Function Name: RTC_GetDay +****************************************************************************//** +* +* Returns the day value from the date value that is passed as parameter. +* +* \param date +* The date value. +* +* \return +* The day value. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetDay(uint32 date) +{ + uint32 retVal; + + retVal = ((date & RTC_10_DAY_MASK) >> RTC_10_DAY_OFFSET) * 10u; + retVal += (date & RTC_DAY_MASK) >> RTC_DAY_OFFSET; + + return (retVal); +} + + +/******************************************************************************* +* Function Name: RTC_GetMonth +****************************************************************************//** +* +* Returns the month value from the date value that is passed as parameter. +* +* \param date +* The date value. +* +* \return +* The month value. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetMonth(uint32 date) +{ + uint32 retVal; + + retVal = ((date & RTC_10_MONTH_MASK) >> RTC_10_MONTH_OFFSET) * 10u; + retVal += (date & RTC_MONTH_MASK) >> RTC_MONTH_OFFSET; + + return (retVal); +} + + +/******************************************************************************* +* Function Name: RTC_GetYear +****************************************************************************//** +* +* Returns the year value from the date value that is passed as parameter. +* +* \param date +* The date value. +* +* \return +* The year value. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetYear(uint32 date) +{ + uint32 retVal; + + retVal = ((date & RTC_1000_YEAR_MASK) >> RTC_1000_YEAR_OFFSET) * 1000u; + retVal += ((date & RTC_100_YEAR_MASK) >> RTC_100_YEAR_OFFSET) * 100u; + retVal += ((date & RTC_10_YEAR_MASK) >> RTC_10_YEAR_OFFSET) * 10u; + retVal += (date & RTC_YEAR_MASK) >> RTC_YEAR_OFFSET; + + return (retVal); +} + + +/******************************************************************************* +* Function Name: RTC_SetSecond +****************************************************************************//** +* \internal +* Updates the time with the new second value. +* +* \param inputTime +* The current date. +* +* \param inputSecond +* The seconds value to be set to the time variable. +* +* \return +* The updated time variable. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_SetSecond(uint32 inputTime, uint32 inputSecond) +{ + inputTime &= ~(RTC_SECONDS_FULL_MASK); + + inputTime |= (inputSecond / 10u) << RTC_10_SECONDS_OFFSET; + inputTime |= (inputSecond % 10u) << RTC_SECONDS_OFFSET; + + return(inputTime); +} + + +/******************************************************************************* +* Function Name: RTC_SetMinutes +****************************************************************************//** +* \internal +* Updates the time with the new minute value. +* +* \param inputTime +* The current date. +* +* \param inputMinute +* The minutes value to be set to the time variable. +* +* \return +* The updated time variable. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_SetMinutes(uint32 inputTime, uint32 inputMinute) +{ + inputTime &= ~(RTC_MINUTES_FULL_MASK); + + inputTime |= (inputMinute / 10u) << RTC_10_MINUTES_OFFSET; + inputTime |= (inputMinute % 10u) << RTC_MINUTES_OFFSET; + + return(inputTime); +} + + +/******************************************************************************* +* Function Name: RTC_SetHours +****************************************************************************//** +* \internal +* Updates the time with the new hour value. +* +* \param inputTime +* The current date. +* +* \param inputHours +* The hours value to be set to the time variable. +* +* \return +* The updated time variable. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_SetHours(uint32 inputTime, uint32 inputHours) +{ + inputTime &= ~(RTC_HOURS_FULL_MASK); + + inputTime |= (inputHours / 10u) << RTC_10_HOURS_OFFSET; + inputTime |= (inputHours % 10u) << RTC_HOURS_OFFSET; + + return(inputTime); +} + + +/******************************************************************************* +* Function Name: RTC_SetAmPm +****************************************************************************//** +* \internal +* Updates the time variable with the AmPm status. +* +* \param inputTime +* The current date. +* +* \param periodOfDay +* The AmPm status to be set to the time variable. +* +* \return +* The updated time variable. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_SetAmPm(uint32 inputTime, uint32 periodOfDay) +{ + if(0u != periodOfDay) + { + inputTime &= ~(RTC_PERIOD_OF_DAY_MASK); + } + else + { + inputTime |= RTC_PERIOD_OF_DAY_MASK; + } + + return(inputTime); +} + + +/******************************************************************************* +* Function Name: RTC_SetDay +****************************************************************************//** +* \internal +* Updates the date variable with the new day value. +* +* \param inputDate +* The current date. +* +* \param inputDay +* day The month to be set to the date variable. +* +* \return +* The updated date variable. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_SetDay(uint32 inputDate, uint32 inputDay) +{ + inputDate &= ~(RTC_DAY_FULL_MASK); + + inputDate |= (inputDay / 10u) << RTC_10_DAY_OFFSET; + inputDate |= (inputDay % 10u) << RTC_DAY_OFFSET; + + return(inputDate); +} + + +/******************************************************************************* +* Function Name: RTC_SetMonth +****************************************************************************//** +* \internal +* Updates the date variable with the new month value. +* +* \param inputDate +* The current date. +* +* \param inputMonth +* The month that to be set to the date variable. +* +* \return +* The updated date variable. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_SetMonth(uint32 inputDate, uint32 inputMonth) +{ + inputDate &= ~(RTC_MONTH_FULL_MASK); + + inputDate |= (inputMonth / 10u) << RTC_10_MONTH_OFFSET; + inputDate |= (inputMonth % 10u) << RTC_MONTH_OFFSET; + + return(inputDate); +} + + +/******************************************************************************* +* Function Name: RTC_SetYear +****************************************************************************//** +*\internal +* Updates the date variable with the new year value. +* +* \param inputDate +* The current date. +* +* \param inputYear +* The year to be set to the date variable. +* +* \return +* The updated date variable. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_SetYear(uint32 inputDate, uint32 inputYear) +{ + inputDate &= ~(RTC_YEAR_FULL_MASK); + + inputDate |= (inputYear / 1000u) << RTC_1000_YEAR_OFFSET; + inputYear %= 1000u; + + inputDate |= (inputYear / 100u) << RTC_100_YEAR_OFFSET; + inputYear %= 100u; + + inputDate |= (inputYear / 10u) << RTC_10_YEAR_OFFSET; + inputDate |= (inputYear % 10u) << RTC_YEAR_OFFSET; + + return(inputDate); +} + + +/******************************************************************************* +* Function Name: RTC_GetNextMinSec +****************************************************************************//** +*\internal +* This is an internal function that calculates the value of the next Second/Minute +* that follows after the current Minute/Second. +* +* \param curVal +* The current Second/Minute value. +* +* \return +* Returns the Second/Minute which follows after the current Second/Minute. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetNextMinSec(uint32 curVal) +{ + return((curVal < 59u) ? (curVal + 1u) : 0u); +} + + +/******************************************************************************* +* Function Name: RTC_GetNextHour +****************************************************************************//** +* \internal +* This is an internal function that calculates the value of the next Hour +* that follows after the current Hour. +* +* \param curVal +* The current Hour value. +* +* \return +* Returns the Hour which follows after the current Hour. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetNextHour(uint32 curVal) +{ + return((curVal < 23u) ? (curVal + 1u) : 0u); +} + + +/******************************************************************************* +* Function Name: RTC_GetNextDay +****************************************************************************//** +* \internal +* This is an internal function that calculates the value of the next Day +* that follows after the current Day. +* +* \param curYear +* The current year. +* +* \param curMonth +* The current month. +* +* \param curDay +* The current day. +* +* \param alarmCfgMask +* Alarm Config Mask. +* +* \return +* Returns the day which follows after the current Day. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetNextDay(uint32 curYear, uint32 curMonth, + uint32 curDay, uint32 alarmCfgMask) +{ + uint32 daysInMonth; + uint32 tmpVal; + + daysInMonth = RTC_DaysInMonth(curMonth, curYear); + + if(0u != (alarmCfgMask & RTC_ALARM_DAYOFWEEK_MASK)) + { + tmpVal = curDay + RTC_DAYS_PER_WEEK; + tmpVal = (tmpVal > daysInMonth) ? (tmpVal - daysInMonth) : tmpVal; + } + else + { + tmpVal = (curDay < daysInMonth) ? (curDay + 1u) : 1u; + } + + return(tmpVal); +} + + +/******************************************************************************* +* Function Name: RTC_GetNextMonth +****************************************************************************//** +* \internal +* This is an internal function that calculates the value of the next month +* that follows after the current month. +* +* \param curMonth +* The current month. +* +* \return +* Returns the month which follows after the current month. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetNextMonth(uint32 curMonth) +{ + return((curMonth < 12u) ? (curMonth + 1u) : 1u); +} + + +/******************************************************************************* +* Function Name: RTC_GetNextYear +****************************************************************************//** +* \internal +* This is an internal function that calculates the value of the next year +* that follows after the current year. +* +* \param curYear +* The current year. +* +* \return +* Returns the year which follows after the current year. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetNextYear(uint32 curYear) +{ + return(curYear + 1u); +} + + +/******************************************************************************* +* Function Name: RTC_SetTimeFormat +****************************************************************************//** +* \internal +* Updates the "Time Format" value in the variable that contains time in the +* "HH:MM:SS" format. +* +* \param inputTime +* The current value of the time in the "HH:MM:SS" format. +* +* \param timeFormat +* Required time format +* +* \return +* Returns the updated value of the time in the "HH:MM:SS" format. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_SetTimeFormat(uint32 inputTime, uint32 timeFormat) +{ + inputTime &= ~(RTC_TIME_FORMAT_MASK); + + if((uint32)RTC_12_HOURS_FORMAT != timeFormat) + { + inputTime |= RTC_TIME_FORMAT_MASK; + } + + return(inputTime); +} + + +/******************************************************************************* +* Function Name: RTC_GetTimeFormat +****************************************************************************//** +* \internal +* Reads the time format from the variable that contains time in the +* "HH:MM:SS" format. +* +* \param inputTime +* The current value of the time in the "HH:MM:SS" format. +* +* \return +* Returns the time format that is stored in the variable that contains time +* in the "HH:MM:SS" format. +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetTimeFormat(uint32 inputTime) +{ + return ((0uL != (inputTime & (1uL << RTC_TIME_FORMAT_OFFSET))) ? + (uint32)RTC_12_HOURS_FORMAT : + (uint32)RTC_24_HOURS_FORMAT); +} + + +/******************************************************************************* +* Function Name: RTC_ConstructTime +****************************************************************************//** +* +* Returns the time in the format used in APIs from individual elements +* passed (hour, min, sec etc) +* +* \param timeFormat +* The 12/24 hours time format, see \ref group_rtc_hour_format +* +* \param stateAmPm +* The AM/PM status, see \ref group_rtc_am_pm. +* +* \param hour +* The hour. +* +* \param min +* The minute. +* +* \param sec +* The second. +* +* \return +* Time in the format used in API. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_ConstructTime(uint32 timeFormat, uint32 stateAmPm, + uint32 hour, uint32 min, uint32 sec) +{ + uint32 retVal; + + retVal = timeFormat << RTC_TIME_FORMAT_OFFSET; + retVal |= stateAmPm << RTC_PERIOD_OF_DAY_OFFSET; + + retVal |= (hour / 10u) << RTC_10_HOURS_OFFSET; + retVal |= (hour % 10u) << RTC_HOURS_OFFSET; + + retVal |= (min / 10u) << RTC_10_MINUTES_OFFSET; + retVal |= (min % 10u) << RTC_MINUTES_OFFSET; + + retVal |= (sec / 10u) << RTC_10_SECONDS_OFFSET; + retVal |= (sec % 10u) << RTC_SECONDS_OFFSET; + + return (retVal); +} + + +/******************************************************************************* +* Function Name: RTC_ConstructDate +****************************************************************************//** +* +* Returns the date in the format used in APIs from individual elements +* passed (day. Month and year) +* +* \param month +* The month. +* +* \param day +* The day. +* +* \param year +* The year. +* +* \return +* The date in the format used in API. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_ConstructDate(uint32 month, uint32 day, uint32 year) +{ + uint32 retVal; + uint32 tmpVal = year; + + retVal = (month / 10u) << RTC_10_MONTH_OFFSET; + retVal |= (month % 10u) << RTC_MONTH_OFFSET; + + retVal |= (day / 10u) << RTC_10_DAY_OFFSET; + retVal |= (day % 10u) << RTC_DAY_OFFSET; + + retVal |= (year / 1000u) << RTC_1000_YEAR_OFFSET; + tmpVal %= 1000u; + + retVal |= (tmpVal / 100u) << RTC_100_YEAR_OFFSET; + tmpVal %= 100u; + + retVal |= (tmpVal / 10u) << RTC_10_YEAR_OFFSET; + retVal |= (tmpVal % 10u) << RTC_YEAR_OFFSET; + + return (retVal); +} + + +/******************************************************************************* +* Function Name: RTC_GetDayOfWeek +****************************************************************************//** +* \internal +* +* Returns a day of the week for a year, month, and day of month that are passed +* through parameters. Zeller's congruence is used to calculate the day of +* the week. +* +* For the Georgian calendar, Zeller's congruence is: +* h = (q + [13 * (m + 1)] + K + [K/4] + [J/4] - 2J) mod 7; +* +* h - The day of the week (0 = Saturday, 1 = Sunday, 2 = Monday, ..., +* 6 = Friday). +* q - The day of the month. +* m - The month (3 = March, 4 = April, 5 = May, ..., 14 = February). +* K - The year of the century (year \mod 100). +* J - The zero-based century (actually [year/100]) For example, the zero-based +* centuries for 1995 and 2000 are 19 and 20 respectively (not to be +* confused with the common ordinal century enumeration which indicates +* 20th for both cases). +* +* \note +* In this algorithm January and February are counted as months 13 and 14 +* of the previous year. +* +* \param day +* The day of the month(1..31) +* +* \param month +* The month of the year, see \ref group_rtc_month +* +* \param year +* The year value. +* +* \return +* Returns a day of the week, see \ref group_rtc_day_of_the_week. +* +* \endinternal +*******************************************************************************/ +static CY_INLINE uint32 RTC_GetDayOfWeek(uint32 day, uint32 month, uint32 year) +{ + uint32 retVal; + + /* Converts month number from regular convention + * (1=January,..., 12=December) to convention required for this + * algorithm(January and February are counted as months 13 and 14 of + * previous year). + */ + if(month < (uint32)RTC_MARCH) + { + month = 12u + month; + year--; + } + + /* Calculates Day of Week using Zeller's congruence algorithms */ + retVal = (day + (((month + 1u) * 26u) / 10u) + year + (year / 4u) + (6u * (year / 100u)) + (year / 400u)) % 7u; + + /* Makes correction for Saturday. Saturday number should be 7 instead of 0. */ + if(0u == retVal) + { + retVal = (uint32)RTC_SATURDAY; + } + + return(retVal); +} + + +/******************************************************************************* +* Function Name: RTC_DaysBeforeMonth +****************************************************************************//** +* +* Calculates how many days elapsed from the beginning of the year to the +* beginning of the current month. +* +* \param month +* A month of a year, see \ref group_rtc_month +* +* \param year +* A year value. +* +* \return +* A number of days elapsed from the beginning of the year to the +* beginning of the current month passed through the parameters. +* +*******************************************************************************/ +static CY_INLINE uint32 RTC_DaysBeforeMonth(uint32 month, uint32 year) +{ + uint32 retVal; + + retVal = RTC_daysBeforeMonthTbl[month - 1u]; + if((0u != RTC_LeapYear(year)) && (month > (uint32)RTC_FEBRUARY)) + { + retVal++; + } + + return(retVal); +} + +#if defined(CYDEV_RTC_SOURCE_WDT) + #if((0u != CYDEV_WDT_GENERATE_ISR) && (0u == RTC_INITIAL_UPDATE_MODE)) + + /******************************************************************************* + * Function Name: RTC_CySysRtcSetCallback + ****************************************************************************//** + * + * This is an internal function that registers a callback for the + * RTC_Update() function by address "0". + * + * \param wdtNumber + * The number of the WDT or DeepSleep Timer to be used to pull the + * RTC_Update() function. + * + * The callback registered before by address "0" is replaced + * by the RTC_Update() function. + * + *******************************************************************************/ + static CY_INLINE void RTC_CySysRtcSetCallback(uint32 wdtNumber) + { + #if((0u != CY_IP_WCO_WDT_EN) && (0u != CY_IP_SRSSLT)) + (void)CySysTimerSetInterruptCallback(wdtNumber, &RTC_Update); + #else + (void)CySysWdtSetIsrCallback(wdtNumber, &RTC_Update); + #endif /* ((0u != CY_IP_WCO_WDT_EN) && (0u != CY_IP_SRSSLT)) */ + } + + + /******************************************************************************* + * Function Name: RTC_CySysRtcResetCallback + ****************************************************************************//** + * + * This is an internal function that clears a callback by address "0". + * + * \param wdtNumber + * The number of the WDT or DeeSleep Timer to be cleared callback for. + * + * The callback registered before by address "0" is replaced + * by the NULL pointer. + * + *******************************************************************************/ + static CY_INLINE void RTC_CySysRtcResetCallback(uint32 wdtNumber) + { + #if((0u != CY_IP_WCO_WDT_EN) && (0u != CY_IP_SRSSLT)) + (void)CySysTimerSetInterruptCallback(wdtNumber, (void *)0); + #else + (void)CySysWdtSetIsrCallback(wdtNumber, (void *)0); + #endif /* ((0u != CY_IP_WCO_WDT_EN) && (0u != CY_IP_SRSSLT)) */ + } + + #endif /* ((0u != CYDEV_WDT_GENERATE_ISR) && (0u == RTC_INITIAL_UPDATE_MODE)) */ +#endif /* (CYDEV_RTC_SOURCE_WDT) */ + +#endif /* CY_RTC_P4_RTC_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1.c b/cores/asr650x/projects/PSoC4/SPI_1.c new file mode 100644 index 00000000..e0144332 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1.c @@ -0,0 +1,818 @@ +/***************************************************************************//** +* \file SPI_1.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SPI_1_PVT.h" + +#if (SPI_1_SCB_MODE_I2C_INC) + #include "SPI_1_I2C_PVT.h" +#endif /* (SPI_1_SCB_MODE_I2C_INC) */ + +#if (SPI_1_SCB_MODE_EZI2C_INC) + #include "SPI_1_EZI2C_PVT.h" +#endif /* (SPI_1_SCB_MODE_EZI2C_INC) */ + +#if (SPI_1_SCB_MODE_SPI_INC || SPI_1_SCB_MODE_UART_INC) + #include "SPI_1_SPI_UART_PVT.h" +#endif /* (SPI_1_SCB_MODE_SPI_INC || SPI_1_SCB_MODE_UART_INC) */ + + +/*************************************** +* Run Time Configuration Vars +***************************************/ + +/* Stores internal component configuration for Unconfigured mode */ +#if (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + /* Common configuration variables */ + uint8 SPI_1_scbMode = SPI_1_SCB_MODE_UNCONFIG; + uint8 SPI_1_scbEnableWake; + uint8 SPI_1_scbEnableIntr; + + /* I2C configuration variables */ + uint8 SPI_1_mode; + uint8 SPI_1_acceptAddr; + + /* SPI/UART configuration variables */ + volatile uint8 * SPI_1_rxBuffer; + uint8 SPI_1_rxDataBits; + uint32 SPI_1_rxBufferSize; + + volatile uint8 * SPI_1_txBuffer; + uint8 SPI_1_txDataBits; + uint32 SPI_1_txBufferSize; + + /* EZI2C configuration variables */ + uint8 SPI_1_numberOfAddr; + uint8 SPI_1_subAddrSize; +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Common SCB Vars +***************************************/ +/** +* \addtogroup group_general +* \{ +*/ + +/** SPI_1_initVar indicates whether the SPI_1 +* component has been initialized. The variable is initialized to 0 +* and set to 1 the first time SCB_Start() is called. This allows +* the component to restart without reinitialization after the first +* call to the SPI_1_Start() routine. +* +* If re-initialization of the component is required, then the +* SPI_1_Init() function can be called before the +* SPI_1_Start() or SPI_1_Enable() function. +*/ +uint8 SPI_1_initVar = 0u; + + +#if (! (SPI_1_SCB_MODE_I2C_CONST_CFG || \ + SPI_1_SCB_MODE_EZI2C_CONST_CFG)) + /** This global variable stores TX interrupt sources after + * SPI_1_Stop() is called. Only these TX interrupt sources + * will be restored on a subsequent SPI_1_Enable() call. + */ + uint16 SPI_1_IntrTxMask = 0u; +#endif /* (! (SPI_1_SCB_MODE_I2C_CONST_CFG || \ + SPI_1_SCB_MODE_EZI2C_CONST_CFG)) */ +/** \} globals */ + +#if (SPI_1_SCB_IRQ_INTERNAL) +#if !defined (CY_REMOVE_SPI_1_CUSTOM_INTR_HANDLER) + void (*SPI_1_customIntrHandler)(void) = NULL; +#endif /* !defined (CY_REMOVE_SPI_1_CUSTOM_INTR_HANDLER) */ +#endif /* (SPI_1_SCB_IRQ_INTERNAL) */ + + +/*************************************** +* Private Function Prototypes +***************************************/ + +static void SPI_1_ScbEnableIntr(void); +static void SPI_1_ScbModeStop(void); +static void SPI_1_ScbModePostEnable(void); + + +/******************************************************************************* +* Function Name: SPI_1_Init +****************************************************************************//** +* +* Initializes the SPI_1 component to operate in one of the selected +* configurations: I2C, SPI, UART or EZI2C. +* When the configuration is set to "Unconfigured SCB", this function does +* not do any initialization. Use mode-specific initialization APIs instead: +* SPI_1_I2CInit, SPI_1_SpiInit, +* SPI_1_UartInit or SPI_1_EzI2CInit. +* +*******************************************************************************/ +void SPI_1_Init(void) +{ +#if (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + if (SPI_1_SCB_MODE_UNCONFIG_RUNTM_CFG) + { + SPI_1_initVar = 0u; + } + else + { + /* Initialization was done before this function call */ + } + +#elif (SPI_1_SCB_MODE_I2C_CONST_CFG) + SPI_1_I2CInit(); + +#elif (SPI_1_SCB_MODE_SPI_CONST_CFG) + SPI_1_SpiInit(); + +#elif (SPI_1_SCB_MODE_UART_CONST_CFG) + SPI_1_UartInit(); + +#elif (SPI_1_SCB_MODE_EZI2C_CONST_CFG) + SPI_1_EzI2CInit(); + +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: SPI_1_Enable +****************************************************************************//** +* +* Enables SPI_1 component operation: activates the hardware and +* internal interrupt. It also restores TX interrupt sources disabled after the +* SPI_1_Stop() function was called (note that level-triggered TX +* interrupt sources remain disabled to not cause code lock-up). +* For I2C and EZI2C modes the interrupt is internal and mandatory for +* operation. For SPI and UART modes the interrupt can be configured as none, +* internal or external. +* The SPI_1 configuration should be not changed when the component +* is enabled. Any configuration changes should be made after disabling the +* component. +* When configuration is set to 鈥淯nconfigured SPI_1鈥, the component +* must first be initialized to operate in one of the following configurations: +* I2C, SPI, UART or EZ I2C, using the mode-specific initialization API. +* Otherwise this function does not enable the component. +* +*******************************************************************************/ +void SPI_1_Enable(void) +{ +#if (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + /* Enable SCB block, only if it is already configured */ + if (!SPI_1_SCB_MODE_UNCONFIG_RUNTM_CFG) + { + SPI_1_CTRL_REG |= SPI_1_CTRL_ENABLED; + + SPI_1_ScbEnableIntr(); + + /* Call PostEnable function specific to current operation mode */ + SPI_1_ScbModePostEnable(); + } +#else + SPI_1_CTRL_REG |= SPI_1_CTRL_ENABLED; + + SPI_1_ScbEnableIntr(); + + /* Call PostEnable function specific to current operation mode */ + SPI_1_ScbModePostEnable(); +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: SPI_1_Start +****************************************************************************//** +* +* Invokes SPI_1_Init() and SPI_1_Enable(). +* After this function call, the component is enabled and ready for operation. +* When configuration is set to "Unconfigured SCB", the component must first be +* initialized to operate in one of the following configurations: I2C, SPI, UART +* or EZI2C. Otherwise this function does not enable the component. +* +* \globalvars +* SPI_1_initVar - used to check initial configuration, modified +* on first function call. +* +*******************************************************************************/ +void SPI_1_Start(void) +{ + if (0u == SPI_1_initVar) + { + SPI_1_Init(); + SPI_1_initVar = 1u; /* Component was initialized */ + } + + SPI_1_Enable(); +} + + +/******************************************************************************* +* Function Name: SPI_1_Stop +****************************************************************************//** +* +* Disables the SPI_1 component: disable the hardware and internal +* interrupt. It also disables all TX interrupt sources so as not to cause an +* unexpected interrupt trigger because after the component is enabled, the +* TX FIFO is empty. +* Refer to the function SPI_1_Enable() for the interrupt +* configuration details. +* This function disables the SCB component without checking to see if +* communication is in progress. Before calling this function it may be +* necessary to check the status of communication to make sure communication +* is complete. If this is not done then communication could be stopped mid +* byte and corrupted data could result. +* +*******************************************************************************/ +void SPI_1_Stop(void) +{ +#if (SPI_1_SCB_IRQ_INTERNAL) + SPI_1_DisableInt(); +#endif /* (SPI_1_SCB_IRQ_INTERNAL) */ + + /* Call Stop function specific to current operation mode */ + SPI_1_ScbModeStop(); + + /* Disable SCB IP */ + SPI_1_CTRL_REG &= (uint32) ~SPI_1_CTRL_ENABLED; + + /* Disable all TX interrupt sources so as not to cause an unexpected + * interrupt trigger after the component will be enabled because the + * TX FIFO is empty. + * For SCB IP v0, it is critical as it does not mask-out interrupt + * sources when it is disabled. This can cause a code lock-up in the + * interrupt handler because TX FIFO cannot be loaded after the block + * is disabled. + */ + SPI_1_SetTxInterruptMode(SPI_1_NO_INTR_SOURCES); + +#if (SPI_1_SCB_IRQ_INTERNAL) + SPI_1_ClearPendingInt(); +#endif /* (SPI_1_SCB_IRQ_INTERNAL) */ +} + + +/******************************************************************************* +* Function Name: SPI_1_SetRxFifoLevel +****************************************************************************//** +* +* Sets level in the RX FIFO to generate a RX level interrupt. +* When the RX FIFO has more entries than the RX FIFO level an RX level +* interrupt request is generated. +* +* \param level: Level in the RX FIFO to generate RX level interrupt. +* The range of valid level values is between 0 and RX FIFO depth - 1. +* +*******************************************************************************/ +void SPI_1_SetRxFifoLevel(uint32 level) +{ + uint32 rxFifoCtrl; + + rxFifoCtrl = SPI_1_RX_FIFO_CTRL_REG; + + rxFifoCtrl &= ((uint32) ~SPI_1_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + rxFifoCtrl |= ((uint32) (SPI_1_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK & level)); + + SPI_1_RX_FIFO_CTRL_REG = rxFifoCtrl; +} + + +/******************************************************************************* +* Function Name: SPI_1_SetTxFifoLevel +****************************************************************************//** +* +* Sets level in the TX FIFO to generate a TX level interrupt. +* When the TX FIFO has less entries than the TX FIFO level an TX level +* interrupt request is generated. +* +* \param level: Level in the TX FIFO to generate TX level interrupt. +* The range of valid level values is between 0 and TX FIFO depth - 1. +* +*******************************************************************************/ +void SPI_1_SetTxFifoLevel(uint32 level) +{ + uint32 txFifoCtrl; + + txFifoCtrl = SPI_1_TX_FIFO_CTRL_REG; + + txFifoCtrl &= ((uint32) ~SPI_1_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + txFifoCtrl |= ((uint32) (SPI_1_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK & level)); + + SPI_1_TX_FIFO_CTRL_REG = txFifoCtrl; +} + + +#if (SPI_1_SCB_IRQ_INTERNAL) + /******************************************************************************* + * Function Name: SPI_1_SetCustomInterruptHandler + ****************************************************************************//** + * + * Registers a function to be called by the internal interrupt handler. + * First the function that is registered is called, then the internal interrupt + * handler performs any operation such as software buffer management functions + * before the interrupt returns. It is the user's responsibility not to break + * the software buffer operations. Only one custom handler is supported, which + * is the function provided by the most recent call. + * At the initialization time no custom handler is registered. + * + * \param func: Pointer to the function to register. + * The value NULL indicates to remove the current custom interrupt + * handler. + * + *******************************************************************************/ + void SPI_1_SetCustomInterruptHandler(void (*func)(void)) + { + #if !defined (CY_REMOVE_SPI_1_CUSTOM_INTR_HANDLER) + SPI_1_customIntrHandler = func; /* Register interrupt handler */ + #else + if (NULL != func) + { + /* Suppress compiler warning */ + } + #endif /* !defined (CY_REMOVE_SPI_1_CUSTOM_INTR_HANDLER) */ + } +#endif /* (SPI_1_SCB_IRQ_INTERNAL) */ + + +/******************************************************************************* +* Function Name: SPI_1_ScbModeEnableIntr +****************************************************************************//** +* +* Enables an interrupt for a specific mode. +* +*******************************************************************************/ +static void SPI_1_ScbEnableIntr(void) +{ +#if (SPI_1_SCB_IRQ_INTERNAL) + /* Enable interrupt in NVIC */ + #if (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + if (0u != SPI_1_scbEnableIntr) + { + SPI_1_EnableInt(); + } + + #else + SPI_1_EnableInt(); + + #endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +#endif /* (SPI_1_SCB_IRQ_INTERNAL) */ +} + + +/******************************************************************************* +* Function Name: SPI_1_ScbModePostEnable +****************************************************************************//** +* +* Calls the PostEnable function for a specific operation mode. +* +*******************************************************************************/ +static void SPI_1_ScbModePostEnable(void) +{ +#if (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) +#if (!SPI_1_CY_SCBIP_V1) + if (SPI_1_SCB_MODE_SPI_RUNTM_CFG) + { + SPI_1_SpiPostEnable(); + } + else if (SPI_1_SCB_MODE_UART_RUNTM_CFG) + { + SPI_1_UartPostEnable(); + } + else + { + /* Unknown mode: do nothing */ + } +#endif /* (!SPI_1_CY_SCBIP_V1) */ + +#elif (SPI_1_SCB_MODE_SPI_CONST_CFG) + SPI_1_SpiPostEnable(); + +#elif (SPI_1_SCB_MODE_UART_CONST_CFG) + SPI_1_UartPostEnable(); + +#else + /* Unknown mode: do nothing */ +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: SPI_1_ScbModeStop +****************************************************************************//** +* +* Calls the Stop function for a specific operation mode. +* +*******************************************************************************/ +static void SPI_1_ScbModeStop(void) +{ +#if (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + if (SPI_1_SCB_MODE_I2C_RUNTM_CFG) + { + SPI_1_I2CStop(); + } + else if (SPI_1_SCB_MODE_EZI2C_RUNTM_CFG) + { + SPI_1_EzI2CStop(); + } +#if (!SPI_1_CY_SCBIP_V1) + else if (SPI_1_SCB_MODE_SPI_RUNTM_CFG) + { + SPI_1_SpiStop(); + } + else if (SPI_1_SCB_MODE_UART_RUNTM_CFG) + { + SPI_1_UartStop(); + } +#endif /* (!SPI_1_CY_SCBIP_V1) */ + else + { + /* Unknown mode: do nothing */ + } +#elif (SPI_1_SCB_MODE_I2C_CONST_CFG) + SPI_1_I2CStop(); + +#elif (SPI_1_SCB_MODE_EZI2C_CONST_CFG) + SPI_1_EzI2CStop(); + +#elif (SPI_1_SCB_MODE_SPI_CONST_CFG) + SPI_1_SpiStop(); + +#elif (SPI_1_SCB_MODE_UART_CONST_CFG) + SPI_1_UartStop(); + +#else + /* Unknown mode: do nothing */ +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +#if (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + /******************************************************************************* + * Function Name: SPI_1_SetPins + ****************************************************************************//** + * + * Sets the pins settings accordingly to the selected operation mode. + * Only available in the Unconfigured operation mode. The mode specific + * initialization function calls it. + * Pins configuration is set by PSoC Creator when a specific mode of operation + * is selected in design time. + * + * \param mode: Mode of SCB operation. + * \param subMode: Sub-mode of SCB operation. It is only required for SPI and UART + * modes. + * \param uartEnableMask: enables TX or RX direction and RTS and CTS signals. + * + *******************************************************************************/ + void SPI_1_SetPins(uint32 mode, uint32 subMode, uint32 uartEnableMask) + { + uint32 pinsDm[SPI_1_SCB_PINS_NUMBER]; + uint32 i; + + #if (!SPI_1_CY_SCBIP_V1) + uint32 pinsInBuf = 0u; + #endif /* (!SPI_1_CY_SCBIP_V1) */ + + uint32 hsiomSel[SPI_1_SCB_PINS_NUMBER] = + { + SPI_1_RX_SCL_MOSI_HSIOM_SEL_GPIO, + SPI_1_TX_SDA_MISO_HSIOM_SEL_GPIO, + 0u, + 0u, + 0u, + 0u, + 0u, + }; + + #if (SPI_1_CY_SCBIP_V1) + /* Supress compiler warning. */ + if ((0u == subMode) || (0u == uartEnableMask)) + { + } + #endif /* (SPI_1_CY_SCBIP_V1) */ + + /* Set default HSIOM to GPIO and Drive Mode to Analog Hi-Z */ + for (i = 0u; i < SPI_1_SCB_PINS_NUMBER; i++) + { + pinsDm[i] = SPI_1_PIN_DM_ALG_HIZ; + } + + if ((SPI_1_SCB_MODE_I2C == mode) || + (SPI_1_SCB_MODE_EZI2C == mode)) + { + #if (SPI_1_RX_SCL_MOSI_PIN) + hsiomSel[SPI_1_RX_SCL_MOSI_PIN_INDEX] = SPI_1_RX_SCL_MOSI_HSIOM_SEL_I2C; + pinsDm [SPI_1_RX_SCL_MOSI_PIN_INDEX] = SPI_1_PIN_DM_OD_LO; + #elif (SPI_1_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[SPI_1_RX_WAKE_SCL_MOSI_PIN_INDEX] = SPI_1_RX_WAKE_SCL_MOSI_HSIOM_SEL_I2C; + pinsDm [SPI_1_RX_WAKE_SCL_MOSI_PIN_INDEX] = SPI_1_PIN_DM_OD_LO; + #else + #endif /* (SPI_1_RX_SCL_MOSI_PIN) */ + + #if (SPI_1_TX_SDA_MISO_PIN) + hsiomSel[SPI_1_TX_SDA_MISO_PIN_INDEX] = SPI_1_TX_SDA_MISO_HSIOM_SEL_I2C; + pinsDm [SPI_1_TX_SDA_MISO_PIN_INDEX] = SPI_1_PIN_DM_OD_LO; + #endif /* (SPI_1_TX_SDA_MISO_PIN) */ + } + #if (!SPI_1_CY_SCBIP_V1) + else if (SPI_1_SCB_MODE_SPI == mode) + { + #if (SPI_1_RX_SCL_MOSI_PIN) + hsiomSel[SPI_1_RX_SCL_MOSI_PIN_INDEX] = SPI_1_RX_SCL_MOSI_HSIOM_SEL_SPI; + #elif (SPI_1_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[SPI_1_RX_WAKE_SCL_MOSI_PIN_INDEX] = SPI_1_RX_WAKE_SCL_MOSI_HSIOM_SEL_SPI; + #else + #endif /* (SPI_1_RX_SCL_MOSI_PIN) */ + + #if (SPI_1_TX_SDA_MISO_PIN) + hsiomSel[SPI_1_TX_SDA_MISO_PIN_INDEX] = SPI_1_TX_SDA_MISO_HSIOM_SEL_SPI; + #endif /* (SPI_1_TX_SDA_MISO_PIN) */ + + #if (SPI_1_CTS_SCLK_PIN) + hsiomSel[SPI_1_CTS_SCLK_PIN_INDEX] = SPI_1_CTS_SCLK_HSIOM_SEL_SPI; + #endif /* (SPI_1_CTS_SCLK_PIN) */ + + if (SPI_1_SPI_SLAVE == subMode) + { + /* Slave */ + pinsDm[SPI_1_RX_SCL_MOSI_PIN_INDEX] = SPI_1_PIN_DM_DIG_HIZ; + pinsDm[SPI_1_TX_SDA_MISO_PIN_INDEX] = SPI_1_PIN_DM_STRONG; + pinsDm[SPI_1_CTS_SCLK_PIN_INDEX] = SPI_1_PIN_DM_DIG_HIZ; + + #if (SPI_1_RTS_SS0_PIN) + /* Only SS0 is valid choice for Slave */ + hsiomSel[SPI_1_RTS_SS0_PIN_INDEX] = SPI_1_RTS_SS0_HSIOM_SEL_SPI; + pinsDm [SPI_1_RTS_SS0_PIN_INDEX] = SPI_1_PIN_DM_DIG_HIZ; + #endif /* (SPI_1_RTS_SS0_PIN) */ + + #if (SPI_1_TX_SDA_MISO_PIN) + /* Disable input buffer */ + pinsInBuf |= SPI_1_TX_SDA_MISO_PIN_MASK; + #endif /* (SPI_1_TX_SDA_MISO_PIN) */ + } + else + { + /* (Master) */ + pinsDm[SPI_1_RX_SCL_MOSI_PIN_INDEX] = SPI_1_PIN_DM_STRONG; + pinsDm[SPI_1_TX_SDA_MISO_PIN_INDEX] = SPI_1_PIN_DM_DIG_HIZ; + pinsDm[SPI_1_CTS_SCLK_PIN_INDEX] = SPI_1_PIN_DM_STRONG; + + #if (SPI_1_RTS_SS0_PIN) + hsiomSel [SPI_1_RTS_SS0_PIN_INDEX] = SPI_1_RTS_SS0_HSIOM_SEL_SPI; + pinsDm [SPI_1_RTS_SS0_PIN_INDEX] = SPI_1_PIN_DM_STRONG; + pinsInBuf |= SPI_1_RTS_SS0_PIN_MASK; + #endif /* (SPI_1_RTS_SS0_PIN) */ + + #if (SPI_1_SS1_PIN) + hsiomSel [SPI_1_SS1_PIN_INDEX] = SPI_1_SS1_HSIOM_SEL_SPI; + pinsDm [SPI_1_SS1_PIN_INDEX] = SPI_1_PIN_DM_STRONG; + pinsInBuf |= SPI_1_SS1_PIN_MASK; + #endif /* (SPI_1_SS1_PIN) */ + + #if (SPI_1_SS2_PIN) + hsiomSel [SPI_1_SS2_PIN_INDEX] = SPI_1_SS2_HSIOM_SEL_SPI; + pinsDm [SPI_1_SS2_PIN_INDEX] = SPI_1_PIN_DM_STRONG; + pinsInBuf |= SPI_1_SS2_PIN_MASK; + #endif /* (SPI_1_SS2_PIN) */ + + #if (SPI_1_SS3_PIN) + hsiomSel [SPI_1_SS3_PIN_INDEX] = SPI_1_SS3_HSIOM_SEL_SPI; + pinsDm [SPI_1_SS3_PIN_INDEX] = SPI_1_PIN_DM_STRONG; + pinsInBuf |= SPI_1_SS3_PIN_MASK; + #endif /* (SPI_1_SS3_PIN) */ + + /* Disable input buffers */ + #if (SPI_1_RX_SCL_MOSI_PIN) + pinsInBuf |= SPI_1_RX_SCL_MOSI_PIN_MASK; + #elif (SPI_1_RX_WAKE_SCL_MOSI_PIN) + pinsInBuf |= SPI_1_RX_WAKE_SCL_MOSI_PIN_MASK; + #else + #endif /* (SPI_1_RX_SCL_MOSI_PIN) */ + + #if (SPI_1_CTS_SCLK_PIN) + pinsInBuf |= SPI_1_CTS_SCLK_PIN_MASK; + #endif /* (SPI_1_CTS_SCLK_PIN) */ + } + } + else /* UART */ + { + if (SPI_1_UART_MODE_SMARTCARD == subMode) + { + /* SmartCard */ + #if (SPI_1_TX_SDA_MISO_PIN) + hsiomSel[SPI_1_TX_SDA_MISO_PIN_INDEX] = SPI_1_TX_SDA_MISO_HSIOM_SEL_UART; + pinsDm [SPI_1_TX_SDA_MISO_PIN_INDEX] = SPI_1_PIN_DM_OD_LO; + #endif /* (SPI_1_TX_SDA_MISO_PIN) */ + } + else /* Standard or IrDA */ + { + if (0u != (SPI_1_UART_RX_PIN_ENABLE & uartEnableMask)) + { + #if (SPI_1_RX_SCL_MOSI_PIN) + hsiomSel[SPI_1_RX_SCL_MOSI_PIN_INDEX] = SPI_1_RX_SCL_MOSI_HSIOM_SEL_UART; + pinsDm [SPI_1_RX_SCL_MOSI_PIN_INDEX] = SPI_1_PIN_DM_DIG_HIZ; + #elif (SPI_1_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[SPI_1_RX_WAKE_SCL_MOSI_PIN_INDEX] = SPI_1_RX_WAKE_SCL_MOSI_HSIOM_SEL_UART; + pinsDm [SPI_1_RX_WAKE_SCL_MOSI_PIN_INDEX] = SPI_1_PIN_DM_DIG_HIZ; + #else + #endif /* (SPI_1_RX_SCL_MOSI_PIN) */ + } + + if (0u != (SPI_1_UART_TX_PIN_ENABLE & uartEnableMask)) + { + #if (SPI_1_TX_SDA_MISO_PIN) + hsiomSel[SPI_1_TX_SDA_MISO_PIN_INDEX] = SPI_1_TX_SDA_MISO_HSIOM_SEL_UART; + pinsDm [SPI_1_TX_SDA_MISO_PIN_INDEX] = SPI_1_PIN_DM_STRONG; + + /* Disable input buffer */ + pinsInBuf |= SPI_1_TX_SDA_MISO_PIN_MASK; + #endif /* (SPI_1_TX_SDA_MISO_PIN) */ + } + + #if !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + if (SPI_1_UART_MODE_STD == subMode) + { + if (0u != (SPI_1_UART_CTS_PIN_ENABLE & uartEnableMask)) + { + /* CTS input is multiplexed with SCLK */ + #if (SPI_1_CTS_SCLK_PIN) + hsiomSel[SPI_1_CTS_SCLK_PIN_INDEX] = SPI_1_CTS_SCLK_HSIOM_SEL_UART; + pinsDm [SPI_1_CTS_SCLK_PIN_INDEX] = SPI_1_PIN_DM_DIG_HIZ; + #endif /* (SPI_1_CTS_SCLK_PIN) */ + } + + if (0u != (SPI_1_UART_RTS_PIN_ENABLE & uartEnableMask)) + { + /* RTS output is multiplexed with SS0 */ + #if (SPI_1_RTS_SS0_PIN) + hsiomSel[SPI_1_RTS_SS0_PIN_INDEX] = SPI_1_RTS_SS0_HSIOM_SEL_UART; + pinsDm [SPI_1_RTS_SS0_PIN_INDEX] = SPI_1_PIN_DM_STRONG; + + /* Disable input buffer */ + pinsInBuf |= SPI_1_RTS_SS0_PIN_MASK; + #endif /* (SPI_1_RTS_SS0_PIN) */ + } + } + #endif /* !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ + } + } + #endif /* (!SPI_1_CY_SCBIP_V1) */ + + /* Configure pins: set HSIOM, DM and InputBufEnable */ + /* Note: the DR register settings do not effect the pin output if HSIOM is other than GPIO */ + + #if (SPI_1_RX_SCL_MOSI_PIN) + SPI_1_SET_HSIOM_SEL(SPI_1_RX_SCL_MOSI_HSIOM_REG, + SPI_1_RX_SCL_MOSI_HSIOM_MASK, + SPI_1_RX_SCL_MOSI_HSIOM_POS, + hsiomSel[SPI_1_RX_SCL_MOSI_PIN_INDEX]); + + SPI_1_uart_rx_i2c_scl_spi_mosi_SetDriveMode((uint8) pinsDm[SPI_1_RX_SCL_MOSI_PIN_INDEX]); + + #if (!SPI_1_CY_SCBIP_V1) + SPI_1_SET_INP_DIS(SPI_1_uart_rx_i2c_scl_spi_mosi_INP_DIS, + SPI_1_uart_rx_i2c_scl_spi_mosi_MASK, + (0u != (pinsInBuf & SPI_1_RX_SCL_MOSI_PIN_MASK))); + #endif /* (!SPI_1_CY_SCBIP_V1) */ + + #elif (SPI_1_RX_WAKE_SCL_MOSI_PIN) + SPI_1_SET_HSIOM_SEL(SPI_1_RX_WAKE_SCL_MOSI_HSIOM_REG, + SPI_1_RX_WAKE_SCL_MOSI_HSIOM_MASK, + SPI_1_RX_WAKE_SCL_MOSI_HSIOM_POS, + hsiomSel[SPI_1_RX_WAKE_SCL_MOSI_PIN_INDEX]); + + SPI_1_uart_rx_wake_i2c_scl_spi_mosi_SetDriveMode((uint8) + pinsDm[SPI_1_RX_WAKE_SCL_MOSI_PIN_INDEX]); + + SPI_1_SET_INP_DIS(SPI_1_uart_rx_wake_i2c_scl_spi_mosi_INP_DIS, + SPI_1_uart_rx_wake_i2c_scl_spi_mosi_MASK, + (0u != (pinsInBuf & SPI_1_RX_WAKE_SCL_MOSI_PIN_MASK))); + + /* Set interrupt on falling edge */ + SPI_1_SET_INCFG_TYPE(SPI_1_RX_WAKE_SCL_MOSI_INTCFG_REG, + SPI_1_RX_WAKE_SCL_MOSI_INTCFG_TYPE_MASK, + SPI_1_RX_WAKE_SCL_MOSI_INTCFG_TYPE_POS, + SPI_1_INTCFG_TYPE_FALLING_EDGE); + #else + #endif /* (SPI_1_RX_WAKE_SCL_MOSI_PIN) */ + + #if (SPI_1_TX_SDA_MISO_PIN) + SPI_1_SET_HSIOM_SEL(SPI_1_TX_SDA_MISO_HSIOM_REG, + SPI_1_TX_SDA_MISO_HSIOM_MASK, + SPI_1_TX_SDA_MISO_HSIOM_POS, + hsiomSel[SPI_1_TX_SDA_MISO_PIN_INDEX]); + + SPI_1_uart_tx_i2c_sda_spi_miso_SetDriveMode((uint8) pinsDm[SPI_1_TX_SDA_MISO_PIN_INDEX]); + + #if (!SPI_1_CY_SCBIP_V1) + SPI_1_SET_INP_DIS(SPI_1_uart_tx_i2c_sda_spi_miso_INP_DIS, + SPI_1_uart_tx_i2c_sda_spi_miso_MASK, + (0u != (pinsInBuf & SPI_1_TX_SDA_MISO_PIN_MASK))); + #endif /* (!SPI_1_CY_SCBIP_V1) */ + #endif /* (SPI_1_RX_SCL_MOSI_PIN) */ + + #if (SPI_1_CTS_SCLK_PIN) + SPI_1_SET_HSIOM_SEL(SPI_1_CTS_SCLK_HSIOM_REG, + SPI_1_CTS_SCLK_HSIOM_MASK, + SPI_1_CTS_SCLK_HSIOM_POS, + hsiomSel[SPI_1_CTS_SCLK_PIN_INDEX]); + + SPI_1_uart_cts_spi_sclk_SetDriveMode((uint8) pinsDm[SPI_1_CTS_SCLK_PIN_INDEX]); + + SPI_1_SET_INP_DIS(SPI_1_uart_cts_spi_sclk_INP_DIS, + SPI_1_uart_cts_spi_sclk_MASK, + (0u != (pinsInBuf & SPI_1_CTS_SCLK_PIN_MASK))); + #endif /* (SPI_1_CTS_SCLK_PIN) */ + + #if (SPI_1_RTS_SS0_PIN) + SPI_1_SET_HSIOM_SEL(SPI_1_RTS_SS0_HSIOM_REG, + SPI_1_RTS_SS0_HSIOM_MASK, + SPI_1_RTS_SS0_HSIOM_POS, + hsiomSel[SPI_1_RTS_SS0_PIN_INDEX]); + + SPI_1_uart_rts_spi_ss0_SetDriveMode((uint8) pinsDm[SPI_1_RTS_SS0_PIN_INDEX]); + + SPI_1_SET_INP_DIS(SPI_1_uart_rts_spi_ss0_INP_DIS, + SPI_1_uart_rts_spi_ss0_MASK, + (0u != (pinsInBuf & SPI_1_RTS_SS0_PIN_MASK))); + #endif /* (SPI_1_RTS_SS0_PIN) */ + + #if (SPI_1_SS1_PIN) + SPI_1_SET_HSIOM_SEL(SPI_1_SS1_HSIOM_REG, + SPI_1_SS1_HSIOM_MASK, + SPI_1_SS1_HSIOM_POS, + hsiomSel[SPI_1_SS1_PIN_INDEX]); + + SPI_1_spi_ss1_SetDriveMode((uint8) pinsDm[SPI_1_SS1_PIN_INDEX]); + + SPI_1_SET_INP_DIS(SPI_1_spi_ss1_INP_DIS, + SPI_1_spi_ss1_MASK, + (0u != (pinsInBuf & SPI_1_SS1_PIN_MASK))); + #endif /* (SPI_1_SS1_PIN) */ + + #if (SPI_1_SS2_PIN) + SPI_1_SET_HSIOM_SEL(SPI_1_SS2_HSIOM_REG, + SPI_1_SS2_HSIOM_MASK, + SPI_1_SS2_HSIOM_POS, + hsiomSel[SPI_1_SS2_PIN_INDEX]); + + SPI_1_spi_ss2_SetDriveMode((uint8) pinsDm[SPI_1_SS2_PIN_INDEX]); + + SPI_1_SET_INP_DIS(SPI_1_spi_ss2_INP_DIS, + SPI_1_spi_ss2_MASK, + (0u != (pinsInBuf & SPI_1_SS2_PIN_MASK))); + #endif /* (SPI_1_SS2_PIN) */ + + #if (SPI_1_SS3_PIN) + SPI_1_SET_HSIOM_SEL(SPI_1_SS3_HSIOM_REG, + SPI_1_SS3_HSIOM_MASK, + SPI_1_SS3_HSIOM_POS, + hsiomSel[SPI_1_SS3_PIN_INDEX]); + + SPI_1_spi_ss3_SetDriveMode((uint8) pinsDm[SPI_1_SS3_PIN_INDEX]); + + SPI_1_SET_INP_DIS(SPI_1_spi_ss3_INP_DIS, + SPI_1_spi_ss3_MASK, + (0u != (pinsInBuf & SPI_1_SS3_PIN_MASK))); + #endif /* (SPI_1_SS3_PIN) */ + } + +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +#if (SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + /******************************************************************************* + * Function Name: SPI_1_I2CSlaveNackGeneration + ****************************************************************************//** + * + * Sets command to generate NACK to the address or data. + * + *******************************************************************************/ + void SPI_1_I2CSlaveNackGeneration(void) + { + /* Check for EC_AM toggle condition: EC_AM and clock stretching for address are enabled */ + if ((0u != (SPI_1_CTRL_REG & SPI_1_CTRL_EC_AM_MODE)) && + (0u == (SPI_1_I2C_CTRL_REG & SPI_1_I2C_CTRL_S_NOT_READY_ADDR_NACK))) + { + /* Toggle EC_AM before NACK generation */ + SPI_1_CTRL_REG &= ~SPI_1_CTRL_EC_AM_MODE; + SPI_1_CTRL_REG |= SPI_1_CTRL_EC_AM_MODE; + } + + SPI_1_I2C_SLAVE_CMD_REG = SPI_1_I2C_SLAVE_CMD_S_NACK; + } +#endif /* (SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1.h b/cores/asr650x/projects/PSoC4/SPI_1.h new file mode 100644 index 00000000..85e92562 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1.h @@ -0,0 +1,2133 @@ +/***************************************************************************//** +* \file SPI_1.h +* \version 4.0 +* +* \brief +* This file provides constants and parameter values for the SCB Component. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(CY_SCB_SPI_1_H) +#define CY_SCB_SPI_1_H + +#include +#include +#include +#include + +/* SCB IP block v0 is available in PSoC 4100/PSoC 4200 */ +#define SPI_1_CY_SCBIP_V0 (CYIPBLOCK_m0s8scb_VERSION == 0u) +/* SCB IP block v1 is available in PSoC 4000 */ +#define SPI_1_CY_SCBIP_V1 (CYIPBLOCK_m0s8scb_VERSION == 1u) +/* SCB IP block v2 is available in all other devices */ +#define SPI_1_CY_SCBIP_V2 (CYIPBLOCK_m0s8scb_VERSION >= 2u) + +/** Component version major.minor */ +#define SPI_1_COMP_VERSION_MAJOR (4) +#define SPI_1_COMP_VERSION_MINOR (0) + +#define SPI_1_SCB_MODE (2u) + +/* SCB modes enum */ +#define SPI_1_SCB_MODE_I2C (0x01u) +#define SPI_1_SCB_MODE_SPI (0x02u) +#define SPI_1_SCB_MODE_UART (0x04u) +#define SPI_1_SCB_MODE_EZI2C (0x08u) +#define SPI_1_SCB_MODE_UNCONFIG (0xFFu) + +/* Condition compilation depends on operation mode: Unconfigured implies apply to all modes */ +#define SPI_1_SCB_MODE_I2C_CONST_CFG (SPI_1_SCB_MODE_I2C == SPI_1_SCB_MODE) +#define SPI_1_SCB_MODE_SPI_CONST_CFG (SPI_1_SCB_MODE_SPI == SPI_1_SCB_MODE) +#define SPI_1_SCB_MODE_UART_CONST_CFG (SPI_1_SCB_MODE_UART == SPI_1_SCB_MODE) +#define SPI_1_SCB_MODE_EZI2C_CONST_CFG (SPI_1_SCB_MODE_EZI2C == SPI_1_SCB_MODE) +#define SPI_1_SCB_MODE_UNCONFIG_CONST_CFG (SPI_1_SCB_MODE_UNCONFIG == SPI_1_SCB_MODE) + +/* Condition compilation for includes */ +#define SPI_1_SCB_MODE_I2C_INC (0u !=(SPI_1_SCB_MODE_I2C & SPI_1_SCB_MODE)) +#define SPI_1_SCB_MODE_EZI2C_INC (0u !=(SPI_1_SCB_MODE_EZI2C & SPI_1_SCB_MODE)) +#if (!SPI_1_CY_SCBIP_V1) + #define SPI_1_SCB_MODE_SPI_INC (0u !=(SPI_1_SCB_MODE_SPI & SPI_1_SCB_MODE)) + #define SPI_1_SCB_MODE_UART_INC (0u !=(SPI_1_SCB_MODE_UART & SPI_1_SCB_MODE)) +#else + #define SPI_1_SCB_MODE_SPI_INC (0u) + #define SPI_1_SCB_MODE_UART_INC (0u) +#endif /* (!SPI_1_CY_SCBIP_V1) */ + +/* Interrupts remove options */ +#define SPI_1_REMOVE_SCB_IRQ (1u) +#define SPI_1_SCB_IRQ_INTERNAL (0u == SPI_1_REMOVE_SCB_IRQ) + +#define SPI_1_REMOVE_UART_RX_WAKEUP_IRQ (1u) +#define SPI_1_UART_RX_WAKEUP_IRQ (0u == SPI_1_REMOVE_UART_RX_WAKEUP_IRQ) + +/* SCB interrupt enum */ +#define SPI_1_SCB_INTR_MODE_NONE (0u) +#define SPI_1_SCB_INTR_MODE_INTERNAL (1u) +#define SPI_1_SCB_INTR_MODE_EXTERNAL (2u) + +/* Internal clock remove option */ +#define SPI_1_REMOVE_SCB_CLK (0u) +#define SPI_1_SCB_CLK_INTERNAL (0u == SPI_1_REMOVE_SCB_CLK) + + +/*************************************** +* Includes +****************************************/ + +#include "SPI_1_PINS.h" + +#if (SPI_1_SCB_CLK_INTERNAL) + #include "SPI_1_SCBCLK.h" +#endif /* (SPI_1_SCB_CLK_INTERNAL) */ + + +/*************************************** +* Type Definitions +***************************************/ + +typedef struct +{ + uint8 enableState; +} SPI_1_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ + +/* Start and Stop APIs */ +void SPI_1_Init(void); +void SPI_1_Enable(void); +void SPI_1_Start(void); +void SPI_1_Stop(void); + +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +/* Sleep and Wakeup APis */ +void SPI_1_Sleep(void); +void SPI_1_Wakeup(void); +/** @} power */ + +/** +* \addtogroup group_interrupt +* @{ +*/ +#if (SPI_1_SCB_IRQ_INTERNAL) + /* Custom interrupt handler */ + void SPI_1_SetCustomInterruptHandler(void (*func)(void)); +#endif /* (SPI_1_SCB_IRQ_INTERNAL) */ +/** @} interrupt */ + +/* Interface to internal interrupt component */ +#if (SPI_1_SCB_IRQ_INTERNAL) + /** + * \addtogroup group_interrupt + * @{ + */ + /******************************************************************************* + * Function Name: SPI_1_EnableInt + ****************************************************************************//** + * + * When using an Internal interrupt, this enables the interrupt in the NVIC. + * When using an external interrupt the API for the interrupt component must + * be used to enable the interrupt. + * + *******************************************************************************/ + #define SPI_1_EnableInt() CyIntEnable(SPI_1_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: SPI_1_DisableInt + ****************************************************************************//** + * + * When using an Internal interrupt, this disables the interrupt in the NVIC. + * When using an external interrupt the API for the interrupt component must + * be used to disable the interrupt. + * + *******************************************************************************/ + #define SPI_1_DisableInt() CyIntDisable(SPI_1_ISR_NUMBER) + /** @} interrupt */ + + /******************************************************************************* + * Function Name: SPI_1_ClearPendingInt + ****************************************************************************//** + * + * This function clears the interrupt pending status in the NVIC. + * + *******************************************************************************/ + #define SPI_1_ClearPendingInt() CyIntClearPending(SPI_1_ISR_NUMBER) +#endif /* (SPI_1_SCB_IRQ_INTERNAL) */ + +#if (SPI_1_UART_RX_WAKEUP_IRQ) + /******************************************************************************* + * Function Name: SPI_1_RxWakeEnableInt + ****************************************************************************//** + * + * This function enables the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define SPI_1_RxWakeEnableInt() CyIntEnable(SPI_1_RX_WAKE_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: SPI_1_RxWakeDisableInt + ****************************************************************************//** + * + * This function disables the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define SPI_1_RxWakeDisableInt() CyIntDisable(SPI_1_RX_WAKE_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: SPI_1_RxWakeClearPendingInt + ****************************************************************************//** + * + * This function clears the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define SPI_1_RxWakeClearPendingInt() CyIntClearPending(SPI_1_RX_WAKE_ISR_NUMBER) +#endif /* (SPI_1_UART_RX_WAKEUP_IRQ) */ + +/** +* \addtogroup group_interrupt +* @{ +*/ +/* Get interrupt cause */ +/******************************************************************************* +* Function Name: SPI_1_GetInterruptCause +****************************************************************************//** +* +* Returns a mask of bits showing the source of the current triggered interrupt. +* This is useful for modes of operation where an interrupt can be generated by +* conditions in multiple interrupt source registers. +* +* \return +* Mask with the OR of the following conditions that have been triggered. +* - SPI_1_INTR_CAUSE_MASTER - Interrupt from Master +* - SPI_1_INTR_CAUSE_SLAVE - Interrupt from Slave +* - SPI_1_INTR_CAUSE_TX - Interrupt from TX +* - SPI_1_INTR_CAUSE_RX - Interrupt from RX +* +*******************************************************************************/ +#define SPI_1_GetInterruptCause() (SPI_1_INTR_CAUSE_REG) + + +/* APIs to service INTR_RX register */ +/******************************************************************************* +* Function Name: SPI_1_GetRxInterruptSource +****************************************************************************//** +* +* Returns RX interrupt request register. This register contains current status +* of RX interrupt sources. +* +* \return +* Current status of RX interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - SPI_1_INTR_RX_FIFO_LEVEL - The number of data elements in the + RX FIFO is greater than the value of RX FIFO level. +* - SPI_1_INTR_RX_NOT_EMPTY - Receiver FIFO is not empty. +* - SPI_1_INTR_RX_FULL - Receiver FIFO is full. +* - SPI_1_INTR_RX_OVERFLOW - Attempt to write to a full +* receiver FIFO. +* - SPI_1_INTR_RX_UNDERFLOW - Attempt to read from an empty +* receiver FIFO. +* - SPI_1_INTR_RX_FRAME_ERROR - UART framing error detected. +* - SPI_1_INTR_RX_PARITY_ERROR - UART parity error detected. +* +*******************************************************************************/ +#define SPI_1_GetRxInterruptSource() (SPI_1_INTR_RX_REG) + + +/******************************************************************************* +* Function Name: SPI_1_SetRxInterruptMode +****************************************************************************//** +* +* Writes RX interrupt mask register. This register configures which bits from +* RX interrupt request register will trigger an interrupt event. +* +* \param interruptMask: RX interrupt sources to be enabled (refer to +* SPI_1_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define SPI_1_SetRxInterruptMode(interruptMask) SPI_1_WRITE_INTR_RX_MASK(interruptMask) + + +/******************************************************************************* +* Function Name: SPI_1_GetRxInterruptMode +****************************************************************************//** +* +* Returns RX interrupt mask register This register specifies which bits from +* RX interrupt request register will trigger an interrupt event. +* +* \return +* RX interrupt sources to be enabled (refer to +* SPI_1_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define SPI_1_GetRxInterruptMode() (SPI_1_INTR_RX_MASK_REG) + + +/******************************************************************************* +* Function Name: SPI_1_GetRxInterruptSourceMasked +****************************************************************************//** +* +* Returns RX interrupt masked request register. This register contains logical +* AND of corresponding bits from RX interrupt request and mask registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled RX interrupt sources cause interrupt event. +* +* \return +* Current status of enabled RX interrupt sources (refer to +* SPI_1_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define SPI_1_GetRxInterruptSourceMasked() (SPI_1_INTR_RX_MASKED_REG) + + +/******************************************************************************* +* Function Name: SPI_1_ClearRxInterruptSource +****************************************************************************//** +* +* Clears RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to be cleared (refer to +* SPI_1_GetRxInterruptSource() function for bit fields values). +* +* \sideeffects +* The side effects are listed in the table below for each +* affected interrupt source. Refer to section RX FIFO interrupt sources for +* detailed description. +* - SPI_1_INTR_RX_FIFO_LEVEL Interrupt source is not cleared when +* the receiver FIFO has more entries than level. +* - SPI_1_INTR_RX_NOT_EMPTY Interrupt source is not cleared when +* receiver FIFO is not empty. +* - SPI_1_INTR_RX_FULL Interrupt source is not cleared when +* receiver FIFO is full. +* +*******************************************************************************/ +#define SPI_1_ClearRxInterruptSource(interruptMask) SPI_1_CLEAR_INTR_RX(interruptMask) + + +/******************************************************************************* +* Function Name: SPI_1_SetRxInterrupt +****************************************************************************//** +* +* Sets RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to set in the RX interrupt request +* register (refer to SPI_1_GetRxInterruptSource() function for bit +* fields values). +* +*******************************************************************************/ +#define SPI_1_SetRxInterrupt(interruptMask) SPI_1_SET_INTR_RX(interruptMask) + +void SPI_1_SetRxFifoLevel(uint32 level); + + +/* APIs to service INTR_TX register */ +/******************************************************************************* +* Function Name: SPI_1_GetTxInterruptSource +****************************************************************************//** +* +* Returns TX interrupt request register. This register contains current status +* of TX interrupt sources. +* +* \return +* Current status of TX interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - SPI_1_INTR_TX_FIFO_LEVEL - The number of data elements in the +* TX FIFO is less than the value of TX FIFO level. +* - SPI_1_INTR_TX_NOT_FULL - Transmitter FIFO is not full. +* - SPI_1_INTR_TX_EMPTY - Transmitter FIFO is empty. +* - SPI_1_INTR_TX_OVERFLOW - Attempt to write to a full +* transmitter FIFO. +* - SPI_1_INTR_TX_UNDERFLOW - Attempt to read from an empty +* transmitter FIFO. +* - SPI_1_INTR_TX_UART_NACK - UART received a NACK in SmartCard +* mode. +* - SPI_1_INTR_TX_UART_DONE - UART transfer is complete. +* All data elements from the TX FIFO are sent. +* - SPI_1_INTR_TX_UART_ARB_LOST - Value on the TX line of the UART +* does not match the value on the RX line. +* +*******************************************************************************/ +#define SPI_1_GetTxInterruptSource() (SPI_1_INTR_TX_REG) + + +/******************************************************************************* +* Function Name: SPI_1_SetTxInterruptMode +****************************************************************************//** +* +* Writes TX interrupt mask register. This register configures which bits from +* TX interrupt request register will trigger an interrupt event. +* +* \param interruptMask: TX interrupt sources to be enabled (refer to +* SPI_1_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define SPI_1_SetTxInterruptMode(interruptMask) SPI_1_WRITE_INTR_TX_MASK(interruptMask) + + +/******************************************************************************* +* Function Name: SPI_1_GetTxInterruptMode +****************************************************************************//** +* +* Returns TX interrupt mask register This register specifies which bits from +* TX interrupt request register will trigger an interrupt event. +* +* \return +* Enabled TX interrupt sources (refer to +* SPI_1_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define SPI_1_GetTxInterruptMode() (SPI_1_INTR_TX_MASK_REG) + + +/******************************************************************************* +* Function Name: SPI_1_GetTxInterruptSourceMasked +****************************************************************************//** +* +* Returns TX interrupt masked request register. This register contains logical +* AND of corresponding bits from TX interrupt request and mask registers. +* This function is intended to be used in the interrupt service routine to identify +* which of enabled TX interrupt sources cause interrupt event. +* +* \return +* Current status of enabled TX interrupt sources (refer to +* SPI_1_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define SPI_1_GetTxInterruptSourceMasked() (SPI_1_INTR_TX_MASKED_REG) + + +/******************************************************************************* +* Function Name: SPI_1_ClearTxInterruptSource +****************************************************************************//** +* +* Clears TX interrupt sources in the interrupt request register. +* +* \param interruptMask: TX interrupt sources to be cleared (refer to +* SPI_1_GetTxInterruptSource() function for bit field values). +* +* \sideeffects +* The side effects are listed in the table below for each affected interrupt +* source. Refer to section TX FIFO interrupt sources for detailed description. +* - SPI_1_INTR_TX_FIFO_LEVEL - Interrupt source is not cleared when +* transmitter FIFO has less entries than level. +* - SPI_1_INTR_TX_NOT_FULL - Interrupt source is not cleared when +* transmitter FIFO has empty entries. +* - SPI_1_INTR_TX_EMPTY - Interrupt source is not cleared when +* transmitter FIFO is empty. +* - SPI_1_INTR_TX_UNDERFLOW - Interrupt source is not cleared when +* transmitter FIFO is empty and I2C mode with clock stretching is selected. +* Put data into the transmitter FIFO before clearing it. This behavior only +* applicable for PSoC 4100/PSoC 4200 devices. +* +*******************************************************************************/ +#define SPI_1_ClearTxInterruptSource(interruptMask) SPI_1_CLEAR_INTR_TX(interruptMask) + + +/******************************************************************************* +* Function Name: SPI_1_SetTxInterrupt +****************************************************************************//** +* +* Sets RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to set in the RX interrupt request +* register (refer to SPI_1_GetRxInterruptSource() function for bit +* fields values). +* +*******************************************************************************/ +#define SPI_1_SetTxInterrupt(interruptMask) SPI_1_SET_INTR_TX(interruptMask) + +void SPI_1_SetTxFifoLevel(uint32 level); + + +/* APIs to service INTR_MASTER register */ +/******************************************************************************* +* Function Name: SPI_1_GetMasterInterruptSource +****************************************************************************//** +* +* Returns Master interrupt request register. This register contains current +* status of Master interrupt sources. +* +* \return +* Current status of Master interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - SPI_1_INTR_MASTER_SPI_DONE - SPI master transfer is complete. +* Refer to Interrupt sources section for detailed description. +* - SPI_1_INTR_MASTER_I2C_ARB_LOST - I2C master lost arbitration. +* - SPI_1_INTR_MASTER_I2C_NACK - I2C master received negative +* acknowledgement (NAK). +* - SPI_1_INTR_MASTER_I2C_ACK - I2C master received acknowledgement. +* - SPI_1_INTR_MASTER_I2C_STOP - I2C master generated STOP. +* - SPI_1_INTR_MASTER_I2C_BUS_ERROR - I2C master bus error +* (detection of unexpected START or STOP condition). +* +*******************************************************************************/ +#define SPI_1_GetMasterInterruptSource() (SPI_1_INTR_MASTER_REG) + +/******************************************************************************* +* Function Name: SPI_1_SetMasterInterruptMode +****************************************************************************//** +* +* Writes Master interrupt mask register. This register configures which bits +* from Master interrupt request register will trigger an interrupt event. +* +* \param interruptMask: Master interrupt sources to be enabled (refer to +* SPI_1_GetMasterInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define SPI_1_SetMasterInterruptMode(interruptMask) SPI_1_WRITE_INTR_MASTER_MASK(interruptMask) + +/******************************************************************************* +* Function Name: SPI_1_GetMasterInterruptMode +****************************************************************************//** +* +* Returns Master interrupt mask register This register specifies which bits +* from Master interrupt request register will trigger an interrupt event. +* +* \return +* Enabled Master interrupt sources (refer to +* SPI_1_GetMasterInterruptSource() function for return values). +* +*******************************************************************************/ +#define SPI_1_GetMasterInterruptMode() (SPI_1_INTR_MASTER_MASK_REG) + +/******************************************************************************* +* Function Name: SPI_1_GetMasterInterruptSourceMasked +****************************************************************************//** +* +* Returns Master interrupt masked request register. This register contains +* logical AND of corresponding bits from Master interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled Master interrupt sources cause interrupt event. +* +* \return +* Current status of enabled Master interrupt sources (refer to +* SPI_1_GetMasterInterruptSource() function for return values). +* +*******************************************************************************/ +#define SPI_1_GetMasterInterruptSourceMasked() (SPI_1_INTR_MASTER_MASKED_REG) + +/******************************************************************************* +* Function Name: SPI_1_ClearMasterInterruptSource +****************************************************************************//** +* +* Clears Master interrupt sources in the interrupt request register. +* +* \param interruptMask: Master interrupt sources to be cleared (refer to +* SPI_1_GetMasterInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define SPI_1_ClearMasterInterruptSource(interruptMask) SPI_1_CLEAR_INTR_MASTER(interruptMask) + +/******************************************************************************* +* Function Name: SPI_1_SetMasterInterrupt +****************************************************************************//** +* +* Sets Master interrupt sources in the interrupt request register. +* +* \param interruptMask: Master interrupt sources to set in the Master interrupt +* request register (refer to SPI_1_GetMasterInterruptSource() +* function for bit field values). +* +*******************************************************************************/ +#define SPI_1_SetMasterInterrupt(interruptMask) SPI_1_SET_INTR_MASTER(interruptMask) + + +/* APIs to service INTR_SLAVE register */ +/******************************************************************************* +* Function Name: SPI_1_GetSlaveInterruptSource +****************************************************************************//** +* +* Returns Slave interrupt request register. This register contains current +* status of Slave interrupt sources. +* +* \return +* Current status of Slave interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - SPI_1_INTR_SLAVE_I2C_ARB_LOST - I2C slave lost arbitration: +* the value driven on the SDA line is not the same as the value observed +* on the SDA line. +* - SPI_1_INTR_SLAVE_I2C_NACK - I2C slave received negative +* acknowledgement (NAK). +* - SPI_1_INTR_SLAVE_I2C_ACK - I2C slave received +* acknowledgement (ACK). +* - SPI_1_INTR_SLAVE_I2C_WRITE_STOP - Stop or Repeated Start +* event for write transfer intended for this slave (address matching +* is performed). +* - SPI_1_INTR_SLAVE_I2C_STOP - Stop or Repeated Start event +* for (read or write) transfer intended for this slave (address matching +* is performed). +* - SPI_1_INTR_SLAVE_I2C_START - I2C slave received Start +* condition. +* - SPI_1_INTR_SLAVE_I2C_ADDR_MATCH - I2C slave received matching +* address. +* - SPI_1_INTR_SLAVE_I2C_GENERAL - I2C Slave received general +* call address. +* - SPI_1_INTR_SLAVE_I2C_BUS_ERROR - I2C slave bus error (detection +* of unexpected Start or Stop condition). +* - SPI_1_INTR_SLAVE_SPI_BUS_ERROR - SPI slave select line is +* deselected at an expected time while the SPI transfer. +* +*******************************************************************************/ +#define SPI_1_GetSlaveInterruptSource() (SPI_1_INTR_SLAVE_REG) + +/******************************************************************************* +* Function Name: SPI_1_SetSlaveInterruptMode +****************************************************************************//** +* +* Writes Slave interrupt mask register. +* This register configures which bits from Slave interrupt request register +* will trigger an interrupt event. +* +* \param interruptMask: Slave interrupt sources to be enabled (refer to +* SPI_1_GetSlaveInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define SPI_1_SetSlaveInterruptMode(interruptMask) SPI_1_WRITE_INTR_SLAVE_MASK(interruptMask) + +/******************************************************************************* +* Function Name: SPI_1_GetSlaveInterruptMode +****************************************************************************//** +* +* Returns Slave interrupt mask register. +* This register specifies which bits from Slave interrupt request register +* will trigger an interrupt event. +* +* \return +* Enabled Slave interrupt sources(refer to +* SPI_1_GetSlaveInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define SPI_1_GetSlaveInterruptMode() (SPI_1_INTR_SLAVE_MASK_REG) + +/******************************************************************************* +* Function Name: SPI_1_GetSlaveInterruptSourceMasked +****************************************************************************//** +* +* Returns Slave interrupt masked request register. This register contains +* logical AND of corresponding bits from Slave interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled Slave interrupt sources cause interrupt event. +* +* \return +* Current status of enabled Slave interrupt sources (refer to +* SPI_1_GetSlaveInterruptSource() function for return values). +* +*******************************************************************************/ +#define SPI_1_GetSlaveInterruptSourceMasked() (SPI_1_INTR_SLAVE_MASKED_REG) + +/******************************************************************************* +* Function Name: SPI_1_ClearSlaveInterruptSource +****************************************************************************//** +* +* Clears Slave interrupt sources in the interrupt request register. +* +* \param interruptMask: Slave interrupt sources to be cleared (refer to +* SPI_1_GetSlaveInterruptSource() function for return values). +* +*******************************************************************************/ +#define SPI_1_ClearSlaveInterruptSource(interruptMask) SPI_1_CLEAR_INTR_SLAVE(interruptMask) + +/******************************************************************************* +* Function Name: SPI_1_SetSlaveInterrupt +****************************************************************************//** +* +* Sets Slave interrupt sources in the interrupt request register. +* +* \param interruptMask: Slave interrupt sources to set in the Slave interrupt +* request register (refer to SPI_1_GetSlaveInterruptSource() +* function for return values). +* +*******************************************************************************/ +#define SPI_1_SetSlaveInterrupt(interruptMask) SPI_1_SET_INTR_SLAVE(interruptMask) + +/** @} interrupt */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +/** +* \addtogroup group_globals +* @{ +*/ + +/** SPI_1_initVar indicates whether the SPI_1 +* component has been initialized. The variable is initialized to 0 +* and set to 1 the first time SCB_Start() is called. This allows +* the component to restart without reinitialization after the first +* call to the SPI_1_Start() routine. +* +* If re-initialization of the component is required, then the +* SPI_1_Init() function can be called before the +* SPI_1_Start() or SPI_1_Enable() function. +*/ +extern uint8 SPI_1_initVar; +/** @} globals */ + +/*************************************** +* Registers +***************************************/ + +#define SPI_1_CTRL_REG (*(reg32 *) SPI_1_SCB__CTRL) +#define SPI_1_CTRL_PTR ( (reg32 *) SPI_1_SCB__CTRL) + +#define SPI_1_STATUS_REG (*(reg32 *) SPI_1_SCB__STATUS) +#define SPI_1_STATUS_PTR ( (reg32 *) SPI_1_SCB__STATUS) + +#if (!SPI_1_CY_SCBIP_V1) + #define SPI_1_SPI_CTRL_REG (*(reg32 *) SPI_1_SCB__SPI_CTRL) + #define SPI_1_SPI_CTRL_PTR ( (reg32 *) SPI_1_SCB__SPI_CTRL) + + #define SPI_1_SPI_STATUS_REG (*(reg32 *) SPI_1_SCB__SPI_STATUS) + #define SPI_1_SPI_STATUS_PTR ( (reg32 *) SPI_1_SCB__SPI_STATUS) + + #define SPI_1_UART_CTRL_REG (*(reg32 *) SPI_1_SCB__UART_CTRL) + #define SPI_1_UART_CTRL_PTR ( (reg32 *) SPI_1_SCB__UART_CTRL) + + #define SPI_1_UART_TX_CTRL_REG (*(reg32 *) SPI_1_SCB__UART_TX_CTRL) + #define SPI_1_UART_TX_CTRL_PTR ( (reg32 *) SPI_1_SCB__UART_TX_CTRL) + + #define SPI_1_UART_RX_CTRL_REG (*(reg32 *) SPI_1_SCB__UART_RX_CTRL) + #define SPI_1_UART_RX_CTRL_PTR ( (reg32 *) SPI_1_SCB__UART_RX_CTRL) + + #define SPI_1_UART_RX_STATUS_REG (*(reg32 *) SPI_1_SCB__UART_RX_STATUS) + #define SPI_1_UART_RX_STATUS_PTR ( (reg32 *) SPI_1_SCB__UART_RX_STATUS) +#endif /* (!SPI_1_CY_SCBIP_V1) */ + +#if !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + #define SPI_1_UART_FLOW_CTRL_REG (*(reg32 *) SPI_1_SCB__UART_FLOW_CTRL) + #define SPI_1_UART_FLOW_CTRL_PTR ( (reg32 *) SPI_1_SCB__UART_FLOW_CTRL) +#endif /* !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ + +#define SPI_1_I2C_CTRL_REG (*(reg32 *) SPI_1_SCB__I2C_CTRL) +#define SPI_1_I2C_CTRL_PTR ( (reg32 *) SPI_1_SCB__I2C_CTRL) + +#define SPI_1_I2C_STATUS_REG (*(reg32 *) SPI_1_SCB__I2C_STATUS) +#define SPI_1_I2C_STATUS_PTR ( (reg32 *) SPI_1_SCB__I2C_STATUS) + +#define SPI_1_I2C_MASTER_CMD_REG (*(reg32 *) SPI_1_SCB__I2C_M_CMD) +#define SPI_1_I2C_MASTER_CMD_PTR ( (reg32 *) SPI_1_SCB__I2C_M_CMD) + +#define SPI_1_I2C_SLAVE_CMD_REG (*(reg32 *) SPI_1_SCB__I2C_S_CMD) +#define SPI_1_I2C_SLAVE_CMD_PTR ( (reg32 *) SPI_1_SCB__I2C_S_CMD) + +#define SPI_1_I2C_CFG_REG (*(reg32 *) SPI_1_SCB__I2C_CFG) +#define SPI_1_I2C_CFG_PTR ( (reg32 *) SPI_1_SCB__I2C_CFG) + +#define SPI_1_TX_CTRL_REG (*(reg32 *) SPI_1_SCB__TX_CTRL) +#define SPI_1_TX_CTRL_PTR ( (reg32 *) SPI_1_SCB__TX_CTRL) + +#define SPI_1_TX_FIFO_CTRL_REG (*(reg32 *) SPI_1_SCB__TX_FIFO_CTRL) +#define SPI_1_TX_FIFO_CTRL_PTR ( (reg32 *) SPI_1_SCB__TX_FIFO_CTRL) + +#define SPI_1_TX_FIFO_STATUS_REG (*(reg32 *) SPI_1_SCB__TX_FIFO_STATUS) +#define SPI_1_TX_FIFO_STATUS_PTR ( (reg32 *) SPI_1_SCB__TX_FIFO_STATUS) + +#define SPI_1_TX_FIFO_WR_REG (*(reg32 *) SPI_1_SCB__TX_FIFO_WR) +#define SPI_1_TX_FIFO_WR_PTR ( (reg32 *) SPI_1_SCB__TX_FIFO_WR) + +#define SPI_1_RX_CTRL_REG (*(reg32 *) SPI_1_SCB__RX_CTRL) +#define SPI_1_RX_CTRL_PTR ( (reg32 *) SPI_1_SCB__RX_CTRL) + +#define SPI_1_RX_FIFO_CTRL_REG (*(reg32 *) SPI_1_SCB__RX_FIFO_CTRL) +#define SPI_1_RX_FIFO_CTRL_PTR ( (reg32 *) SPI_1_SCB__RX_FIFO_CTRL) + +#define SPI_1_RX_FIFO_STATUS_REG (*(reg32 *) SPI_1_SCB__RX_FIFO_STATUS) +#define SPI_1_RX_FIFO_STATUS_PTR ( (reg32 *) SPI_1_SCB__RX_FIFO_STATUS) + +#define SPI_1_RX_MATCH_REG (*(reg32 *) SPI_1_SCB__RX_MATCH) +#define SPI_1_RX_MATCH_PTR ( (reg32 *) SPI_1_SCB__RX_MATCH) + +#define SPI_1_RX_FIFO_RD_REG (*(reg32 *) SPI_1_SCB__RX_FIFO_RD) +#define SPI_1_RX_FIFO_RD_PTR ( (reg32 *) SPI_1_SCB__RX_FIFO_RD) + +#define SPI_1_RX_FIFO_RD_SILENT_REG (*(reg32 *) SPI_1_SCB__RX_FIFO_RD_SILENT) +#define SPI_1_RX_FIFO_RD_SILENT_PTR ( (reg32 *) SPI_1_SCB__RX_FIFO_RD_SILENT) + +#ifdef SPI_1_SCB__EZ_DATA0 + #define SPI_1_EZBUF_DATA0_REG (*(reg32 *) SPI_1_SCB__EZ_DATA0) + #define SPI_1_EZBUF_DATA0_PTR ( (reg32 *) SPI_1_SCB__EZ_DATA0) +#else + #define SPI_1_EZBUF_DATA0_REG (*(reg32 *) SPI_1_SCB__EZ_DATA00) + #define SPI_1_EZBUF_DATA0_PTR ( (reg32 *) SPI_1_SCB__EZ_DATA00) +#endif /* SPI_1_SCB__EZ_DATA00 */ + +#define SPI_1_INTR_CAUSE_REG (*(reg32 *) SPI_1_SCB__INTR_CAUSE) +#define SPI_1_INTR_CAUSE_PTR ( (reg32 *) SPI_1_SCB__INTR_CAUSE) + +#define SPI_1_INTR_I2C_EC_REG (*(reg32 *) SPI_1_SCB__INTR_I2C_EC) +#define SPI_1_INTR_I2C_EC_PTR ( (reg32 *) SPI_1_SCB__INTR_I2C_EC) + +#define SPI_1_INTR_I2C_EC_MASK_REG (*(reg32 *) SPI_1_SCB__INTR_I2C_EC_MASK) +#define SPI_1_INTR_I2C_EC_MASK_PTR ( (reg32 *) SPI_1_SCB__INTR_I2C_EC_MASK) + +#define SPI_1_INTR_I2C_EC_MASKED_REG (*(reg32 *) SPI_1_SCB__INTR_I2C_EC_MASKED) +#define SPI_1_INTR_I2C_EC_MASKED_PTR ( (reg32 *) SPI_1_SCB__INTR_I2C_EC_MASKED) + +#if (!SPI_1_CY_SCBIP_V1) + #define SPI_1_INTR_SPI_EC_REG (*(reg32 *) SPI_1_SCB__INTR_SPI_EC) + #define SPI_1_INTR_SPI_EC_PTR ( (reg32 *) SPI_1_SCB__INTR_SPI_EC) + + #define SPI_1_INTR_SPI_EC_MASK_REG (*(reg32 *) SPI_1_SCB__INTR_SPI_EC_MASK) + #define SPI_1_INTR_SPI_EC_MASK_PTR ( (reg32 *) SPI_1_SCB__INTR_SPI_EC_MASK) + + #define SPI_1_INTR_SPI_EC_MASKED_REG (*(reg32 *) SPI_1_SCB__INTR_SPI_EC_MASKED) + #define SPI_1_INTR_SPI_EC_MASKED_PTR ( (reg32 *) SPI_1_SCB__INTR_SPI_EC_MASKED) +#endif /* (!SPI_1_CY_SCBIP_V1) */ + +#define SPI_1_INTR_MASTER_REG (*(reg32 *) SPI_1_SCB__INTR_M) +#define SPI_1_INTR_MASTER_PTR ( (reg32 *) SPI_1_SCB__INTR_M) + +#define SPI_1_INTR_MASTER_SET_REG (*(reg32 *) SPI_1_SCB__INTR_M_SET) +#define SPI_1_INTR_MASTER_SET_PTR ( (reg32 *) SPI_1_SCB__INTR_M_SET) + +#define SPI_1_INTR_MASTER_MASK_REG (*(reg32 *) SPI_1_SCB__INTR_M_MASK) +#define SPI_1_INTR_MASTER_MASK_PTR ( (reg32 *) SPI_1_SCB__INTR_M_MASK) + +#define SPI_1_INTR_MASTER_MASKED_REG (*(reg32 *) SPI_1_SCB__INTR_M_MASKED) +#define SPI_1_INTR_MASTER_MASKED_PTR ( (reg32 *) SPI_1_SCB__INTR_M_MASKED) + +#define SPI_1_INTR_SLAVE_REG (*(reg32 *) SPI_1_SCB__INTR_S) +#define SPI_1_INTR_SLAVE_PTR ( (reg32 *) SPI_1_SCB__INTR_S) + +#define SPI_1_INTR_SLAVE_SET_REG (*(reg32 *) SPI_1_SCB__INTR_S_SET) +#define SPI_1_INTR_SLAVE_SET_PTR ( (reg32 *) SPI_1_SCB__INTR_S_SET) + +#define SPI_1_INTR_SLAVE_MASK_REG (*(reg32 *) SPI_1_SCB__INTR_S_MASK) +#define SPI_1_INTR_SLAVE_MASK_PTR ( (reg32 *) SPI_1_SCB__INTR_S_MASK) + +#define SPI_1_INTR_SLAVE_MASKED_REG (*(reg32 *) SPI_1_SCB__INTR_S_MASKED) +#define SPI_1_INTR_SLAVE_MASKED_PTR ( (reg32 *) SPI_1_SCB__INTR_S_MASKED) + +#define SPI_1_INTR_TX_REG (*(reg32 *) SPI_1_SCB__INTR_TX) +#define SPI_1_INTR_TX_PTR ( (reg32 *) SPI_1_SCB__INTR_TX) + +#define SPI_1_INTR_TX_SET_REG (*(reg32 *) SPI_1_SCB__INTR_TX_SET) +#define SPI_1_INTR_TX_SET_PTR ( (reg32 *) SPI_1_SCB__INTR_TX_SET) + +#define SPI_1_INTR_TX_MASK_REG (*(reg32 *) SPI_1_SCB__INTR_TX_MASK) +#define SPI_1_INTR_TX_MASK_PTR ( (reg32 *) SPI_1_SCB__INTR_TX_MASK) + +#define SPI_1_INTR_TX_MASKED_REG (*(reg32 *) SPI_1_SCB__INTR_TX_MASKED) +#define SPI_1_INTR_TX_MASKED_PTR ( (reg32 *) SPI_1_SCB__INTR_TX_MASKED) + +#define SPI_1_INTR_RX_REG (*(reg32 *) SPI_1_SCB__INTR_RX) +#define SPI_1_INTR_RX_PTR ( (reg32 *) SPI_1_SCB__INTR_RX) + +#define SPI_1_INTR_RX_SET_REG (*(reg32 *) SPI_1_SCB__INTR_RX_SET) +#define SPI_1_INTR_RX_SET_PTR ( (reg32 *) SPI_1_SCB__INTR_RX_SET) + +#define SPI_1_INTR_RX_MASK_REG (*(reg32 *) SPI_1_SCB__INTR_RX_MASK) +#define SPI_1_INTR_RX_MASK_PTR ( (reg32 *) SPI_1_SCB__INTR_RX_MASK) + +#define SPI_1_INTR_RX_MASKED_REG (*(reg32 *) SPI_1_SCB__INTR_RX_MASKED) +#define SPI_1_INTR_RX_MASKED_PTR ( (reg32 *) SPI_1_SCB__INTR_RX_MASKED) + +/* Defines get from SCB IP parameters. */ +#define SPI_1_FIFO_SIZE (8u) /* TX or RX FIFO size. */ +#define SPI_1_EZ_DATA_NR (32u) /* Number of words in EZ memory. */ +#define SPI_1_ONE_BYTE_WIDTH (8u) /* Number of bits in one byte. */ +#define SPI_1_FF_DATA_NR_LOG2_MASK (0x0Fu) /* Number of bits to represent a FIFO address. */ +#define SPI_1_FF_DATA_NR_LOG2_PLUS1_MASK (0x1Fu) /* Number of bits to represent #bytes in FIFO. */ + + +/*************************************** +* Registers Constants +***************************************/ + +#if (SPI_1_SCB_IRQ_INTERNAL) + #define SPI_1_ISR_NUMBER ((uint8) SPI_1_SCB_IRQ__INTC_NUMBER) + #define SPI_1_ISR_PRIORITY ((uint8) SPI_1_SCB_IRQ__INTC_PRIOR_NUM) +#endif /* (SPI_1_SCB_IRQ_INTERNAL) */ + +#if (SPI_1_UART_RX_WAKEUP_IRQ) + #define SPI_1_RX_WAKE_ISR_NUMBER ((uint8) SPI_1_RX_WAKEUP_IRQ__INTC_NUMBER) + #define SPI_1_RX_WAKE_ISR_PRIORITY ((uint8) SPI_1_RX_WAKEUP_IRQ__INTC_PRIOR_NUM) +#endif /* (SPI_1_UART_RX_WAKEUP_IRQ) */ + +/* SPI_1_CTRL_REG */ +#define SPI_1_CTRL_OVS_POS (0u) /* [3:0] Oversampling factor */ +#define SPI_1_CTRL_EC_AM_MODE_POS (8u) /* [8] Externally clocked address match */ +#define SPI_1_CTRL_EC_OP_MODE_POS (9u) /* [9] Externally clocked operation mode */ +#define SPI_1_CTRL_EZBUF_MODE_POS (10u) /* [10] EZ buffer is enabled */ +#if !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + #define SPI_1_CTRL_BYTE_MODE_POS (11u) /* [11] Determines the number of bits per FIFO data element */ +#endif /* !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ +#define SPI_1_CTRL_ADDR_ACCEPT_POS (16u) /* [16] Put matched address in RX FIFO */ +#define SPI_1_CTRL_BLOCK_POS (17u) /* [17] Ext and Int logic to resolve collide */ +#define SPI_1_CTRL_MODE_POS (24u) /* [25:24] Operation mode */ +#define SPI_1_CTRL_ENABLED_POS (31u) /* [31] Enable SCB block */ +#define SPI_1_CTRL_OVS_MASK ((uint32) 0x0Fu) +#define SPI_1_CTRL_EC_AM_MODE ((uint32) 0x01u << SPI_1_CTRL_EC_AM_MODE_POS) +#define SPI_1_CTRL_EC_OP_MODE ((uint32) 0x01u << SPI_1_CTRL_EC_OP_MODE_POS) +#define SPI_1_CTRL_EZBUF_MODE ((uint32) 0x01u << SPI_1_CTRL_EZBUF_MODE_POS) +#if !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + #define SPI_1_CTRL_BYTE_MODE ((uint32) 0x01u << SPI_1_CTRL_BYTE_MODE_POS) +#endif /* !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ +#define SPI_1_CTRL_ADDR_ACCEPT ((uint32) 0x01u << SPI_1_CTRL_ADDR_ACCEPT_POS) +#define SPI_1_CTRL_BLOCK ((uint32) 0x01u << SPI_1_CTRL_BLOCK_POS) +#define SPI_1_CTRL_MODE_MASK ((uint32) 0x03u << SPI_1_CTRL_MODE_POS) +#define SPI_1_CTRL_MODE_I2C ((uint32) 0x00u) +#define SPI_1_CTRL_MODE_SPI ((uint32) 0x01u << SPI_1_CTRL_MODE_POS) +#define SPI_1_CTRL_MODE_UART ((uint32) 0x02u << SPI_1_CTRL_MODE_POS) +#define SPI_1_CTRL_ENABLED ((uint32) 0x01u << SPI_1_CTRL_ENABLED_POS) + +/* SPI_1_STATUS_REG */ +#define SPI_1_STATUS_EC_BUSY_POS (0u) /* [0] Bus busy. Externally clocked logic access to EZ memory */ +#define SPI_1_STATUS_EC_BUSY ((uint32) 0x0Fu) + +/* SPI_1_SPI_CTRL_REG */ +#define SPI_1_SPI_CTRL_CONTINUOUS_POS (0u) /* [0] Continuous or Separated SPI data transfers */ +#define SPI_1_SPI_CTRL_SELECT_PRECEDE_POS (1u) /* [1] Precedes or coincides start of data frame */ +#define SPI_1_SPI_CTRL_CPHA_POS (2u) /* [2] SCLK phase */ +#define SPI_1_SPI_CTRL_CPOL_POS (3u) /* [3] SCLK polarity */ +#define SPI_1_SPI_CTRL_LATE_MISO_SAMPLE_POS (4u) /* [4] Late MISO sample enabled */ +#if !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + #define SPI_1_SPI_CTRL_SCLK_CONTINUOUS_POS (5u) /* [5] Enable continuous SCLK generation */ + #define SPI_1_SPI_CTRL_SSEL0_POLARITY_POS (8u) /* [8] SS0 polarity */ + #define SPI_1_SPI_CTRL_SSEL1_POLARITY_POS (9u) /* [9] SS1 polarity */ + #define SPI_1_SPI_CTRL_SSEL2_POLARITY_POS (10u) /* [10] SS2 polarity */ + #define SPI_1_SPI_CTRL_SSEL3_POLARITY_POS (11u) /* [11] SS3 polarity */ +#endif /* !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ +#define SPI_1_SPI_CTRL_LOOPBACK_POS (16u) /* [16] Local loop-back control enabled */ +#define SPI_1_SPI_CTRL_MODE_POS (24u) /* [25:24] Submode of SPI operation */ +#define SPI_1_SPI_CTRL_SLAVE_SELECT_POS (26u) /* [27:26] Selects SPI SS signal */ +#define SPI_1_SPI_CTRL_MASTER_MODE_POS (31u) /* [31] Master mode enabled */ +#define SPI_1_SPI_CTRL_CONTINUOUS ((uint32) 0x01u) +#define SPI_1_SPI_CTRL_SELECT_PRECEDE ((uint32) 0x01u << SPI_1_SPI_CTRL_SELECT_PRECEDE_POS) +#define SPI_1_SPI_CTRL_SCLK_MODE_MASK ((uint32) 0x03u << SPI_1_SPI_CTRL_CPHA_POS) +#define SPI_1_SPI_CTRL_CPHA ((uint32) 0x01u << SPI_1_SPI_CTRL_CPHA_POS) +#define SPI_1_SPI_CTRL_CPOL ((uint32) 0x01u << SPI_1_SPI_CTRL_CPOL_POS) +#define SPI_1_SPI_CTRL_LATE_MISO_SAMPLE ((uint32) 0x01u << \ + SPI_1_SPI_CTRL_LATE_MISO_SAMPLE_POS) +#if !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + #define SPI_1_SPI_CTRL_SCLK_CONTINUOUS ((uint32) 0x01u << SPI_1_SPI_CTRL_SCLK_CONTINUOUS_POS) + #define SPI_1_SPI_CTRL_SSEL0_POLARITY ((uint32) 0x01u << SPI_1_SPI_CTRL_SSEL0_POLARITY_POS) + #define SPI_1_SPI_CTRL_SSEL1_POLARITY ((uint32) 0x01u << SPI_1_SPI_CTRL_SSEL1_POLARITY_POS) + #define SPI_1_SPI_CTRL_SSEL2_POLARITY ((uint32) 0x01u << SPI_1_SPI_CTRL_SSEL2_POLARITY_POS) + #define SPI_1_SPI_CTRL_SSEL3_POLARITY ((uint32) 0x01u << SPI_1_SPI_CTRL_SSEL3_POLARITY_POS) + #define SPI_1_SPI_CTRL_SSEL_POLARITY_MASK ((uint32)0x0Fu << SPI_1_SPI_CTRL_SSEL0_POLARITY_POS) +#endif /* !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ + +#define SPI_1_SPI_CTRL_LOOPBACK ((uint32) 0x01u << SPI_1_SPI_CTRL_LOOPBACK_POS) +#define SPI_1_SPI_CTRL_MODE_MASK ((uint32) 0x03u << SPI_1_SPI_CTRL_MODE_POS) +#define SPI_1_SPI_CTRL_MODE_MOTOROLA ((uint32) 0x00u) +#define SPI_1_SPI_CTRL_MODE_TI ((uint32) 0x01u << SPI_1_CTRL_MODE_POS) +#define SPI_1_SPI_CTRL_MODE_NS ((uint32) 0x02u << SPI_1_CTRL_MODE_POS) +#define SPI_1_SPI_CTRL_SLAVE_SELECT_MASK ((uint32) 0x03u << SPI_1_SPI_CTRL_SLAVE_SELECT_POS) +#define SPI_1_SPI_CTRL_SLAVE_SELECT0 ((uint32) 0x00u) +#define SPI_1_SPI_CTRL_SLAVE_SELECT1 ((uint32) 0x01u << SPI_1_SPI_CTRL_SLAVE_SELECT_POS) +#define SPI_1_SPI_CTRL_SLAVE_SELECT2 ((uint32) 0x02u << SPI_1_SPI_CTRL_SLAVE_SELECT_POS) +#define SPI_1_SPI_CTRL_SLAVE_SELECT3 ((uint32) 0x03u << SPI_1_SPI_CTRL_SLAVE_SELECT_POS) +#define SPI_1_SPI_CTRL_MASTER ((uint32) 0x01u << SPI_1_SPI_CTRL_MASTER_MODE_POS) +#define SPI_1_SPI_CTRL_SLAVE ((uint32) 0x00u) + +/* SPI_1_SPI_STATUS_REG */ +#define SPI_1_SPI_STATUS_BUS_BUSY_POS (0u) /* [0] Bus busy - slave selected */ +#define SPI_1_SPI_STATUS_EZBUF_ADDR_POS (8u) /* [15:8] EzAddress */ +#define SPI_1_SPI_STATUS_BUS_BUSY ((uint32) 0x01u) +#define SPI_1_SPI_STATUS_EZBUF_ADDR_MASK ((uint32) 0xFFu << SPI_1_I2C_STATUS_EZBUF_ADDR_POS) + +/* SPI_1_UART_CTRL */ +#define SPI_1_UART_CTRL_LOOPBACK_POS (16u) /* [16] Loop-back */ +#define SPI_1_UART_CTRL_MODE_POS (24u) /* [24] UART subMode */ +#define SPI_1_UART_CTRL_LOOPBACK ((uint32) 0x01u << SPI_1_UART_CTRL_LOOPBACK_POS) +#define SPI_1_UART_CTRL_MODE_UART_STD ((uint32) 0x00u) +#define SPI_1_UART_CTRL_MODE_UART_SMARTCARD ((uint32) 0x01u << SPI_1_UART_CTRL_MODE_POS) +#define SPI_1_UART_CTRL_MODE_UART_IRDA ((uint32) 0x02u << SPI_1_UART_CTRL_MODE_POS) +#define SPI_1_UART_CTRL_MODE_MASK ((uint32) 0x03u << SPI_1_UART_CTRL_MODE_POS) + +/* SPI_1_UART_TX_CTRL */ +#define SPI_1_UART_TX_CTRL_STOP_BITS_POS (0u) /* [2:0] Stop bits: (Stop bits + 1) * 0.5 period */ +#define SPI_1_UART_TX_CTRL_PARITY_POS (4u) /* [4] Parity bit */ +#define SPI_1_UART_TX_CTRL_PARITY_ENABLED_POS (5u) /* [5] Parity enable */ +#define SPI_1_UART_TX_CTRL_RETRY_ON_NACK_POS (8u) /* [8] Smart Card: re-send frame on NACK */ +#define SPI_1_UART_TX_CTRL_ONE_STOP_BIT ((uint32) 0x01u) +#define SPI_1_UART_TX_CTRL_ONE_HALF_STOP_BITS ((uint32) 0x02u) +#define SPI_1_UART_TX_CTRL_TWO_STOP_BITS ((uint32) 0x03u) +#define SPI_1_UART_TX_CTRL_STOP_BITS_MASK ((uint32) 0x07u) +#define SPI_1_UART_TX_CTRL_PARITY ((uint32) 0x01u << \ + SPI_1_UART_TX_CTRL_PARITY_POS) +#define SPI_1_UART_TX_CTRL_PARITY_ENABLED ((uint32) 0x01u << \ + SPI_1_UART_TX_CTRL_PARITY_ENABLED_POS) +#define SPI_1_UART_TX_CTRL_RETRY_ON_NACK ((uint32) 0x01u << \ + SPI_1_UART_TX_CTRL_RETRY_ON_NACK_POS) + +/* SPI_1_UART_RX_CTRL */ +#define SPI_1_UART_RX_CTRL_STOP_BITS_POS (0u) /* [2:0] Stop bits: (Stop bits + 1) * 0.5 period*/ +#define SPI_1_UART_RX_CTRL_PARITY_POS (4u) /* [4] Parity bit */ +#define SPI_1_UART_RX_CTRL_PARITY_ENABLED_POS (5u) /* [5] Parity enable */ +#define SPI_1_UART_RX_CTRL_POLARITY_POS (6u) /* [6] IrDA: inverts polarity of RX signal */ +#define SPI_1_UART_RX_CTRL_DROP_ON_PARITY_ERR_POS (8u) /* [8] Drop and lost RX FIFO on parity error */ +#define SPI_1_UART_RX_CTRL_DROP_ON_FRAME_ERR_POS (9u) /* [9] Drop and lost RX FIFO on frame error */ +#define SPI_1_UART_RX_CTRL_MP_MODE_POS (10u) /* [10] Multi-processor mode */ +#define SPI_1_UART_RX_CTRL_LIN_MODE_POS (12u) /* [12] Lin mode: applicable for UART Standard */ +#define SPI_1_UART_RX_CTRL_SKIP_START_POS (13u) /* [13] Skip start not: only for UART Standard */ +#define SPI_1_UART_RX_CTRL_BREAK_WIDTH_POS (16u) /* [19:16] Break width: (Break width + 1) */ +#define SPI_1_UART_TX_CTRL_ONE_STOP_BIT ((uint32) 0x01u) +#define SPI_1_UART_TX_CTRL_ONE_HALF_STOP_BITS ((uint32) 0x02u) +#define SPI_1_UART_TX_CTRL_TWO_STOP_BITS ((uint32) 0x03u) +#define SPI_1_UART_RX_CTRL_STOP_BITS_MASK ((uint32) 0x07u) +#define SPI_1_UART_RX_CTRL_PARITY ((uint32) 0x01u << \ + SPI_1_UART_RX_CTRL_PARITY_POS) +#define SPI_1_UART_RX_CTRL_PARITY_ENABLED ((uint32) 0x01u << \ + SPI_1_UART_RX_CTRL_PARITY_ENABLED_POS) +#define SPI_1_UART_RX_CTRL_POLARITY ((uint32) 0x01u << \ + SPI_1_UART_RX_CTRL_POLARITY_POS) +#define SPI_1_UART_RX_CTRL_DROP_ON_PARITY_ERR ((uint32) 0x01u << \ + SPI_1_UART_RX_CTRL_DROP_ON_PARITY_ERR_POS) +#define SPI_1_UART_RX_CTRL_DROP_ON_FRAME_ERR ((uint32) 0x01u << \ + SPI_1_UART_RX_CTRL_DROP_ON_FRAME_ERR_POS) +#define SPI_1_UART_RX_CTRL_MP_MODE ((uint32) 0x01u << \ + SPI_1_UART_RX_CTRL_MP_MODE_POS) +#define SPI_1_UART_RX_CTRL_LIN_MODE ((uint32) 0x01u << \ + SPI_1_UART_RX_CTRL_LIN_MODE_POS) +#define SPI_1_UART_RX_CTRL_SKIP_START ((uint32) 0x01u << \ + SPI_1_UART_RX_CTRL_SKIP_START_POS) +#define SPI_1_UART_RX_CTRL_BREAK_WIDTH_MASK ((uint32) 0x0Fu << \ + SPI_1_UART_RX_CTRL_BREAK_WIDTH_POS) +/* SPI_1_UART_RX_STATUS_REG */ +#define SPI_1_UART_RX_STATUS_BR_COUNTER_POS (0u) /* [11:0] Baud Rate counter */ +#define SPI_1_UART_RX_STATUS_BR_COUNTER_MASK ((uint32) 0xFFFu) + +#if !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + /* SPI_1_UART_FLOW_CTRL_REG */ + #define SPI_1_UART_FLOW_CTRL_TRIGGER_LEVEL_POS (0u) /* [7:0] RTS RX FIFO trigger level */ + #define SPI_1_UART_FLOW_CTRL_RTS_POLARITY_POS (16u) /* [16] Polarity of the RTS output signal */ + #define SPI_1_UART_FLOW_CTRL_CTS_POLARITY_POS (24u) /* [24] Polarity of the CTS input signal */ + #define SPI_1_UART_FLOW_CTRL_CTS_ENABLED_POS (25u) /* [25] Enable CTS signal */ + #define SPI_1_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK ((uint32) SPI_1_FF_DATA_NR_LOG2_MASK) + #define SPI_1_UART_FLOW_CTRL_RTS_POLARITY ((uint32) 0x01u << \ + SPI_1_UART_FLOW_CTRL_RTS_POLARITY_POS) + #define SPI_1_UART_FLOW_CTRL_CTS_POLARITY ((uint32) 0x01u << \ + SPI_1_UART_FLOW_CTRL_CTS_POLARITY_POS) + #define SPI_1_UART_FLOW_CTRL_CTS_ENABLE ((uint32) 0x01u << \ + SPI_1_UART_FLOW_CTRL_CTS_ENABLED_POS) +#endif /* !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ + +/* SPI_1_I2C_CTRL */ +#define SPI_1_I2C_CTRL_HIGH_PHASE_OVS_POS (0u) /* [3:0] Oversampling factor high: master only */ +#define SPI_1_I2C_CTRL_LOW_PHASE_OVS_POS (4u) /* [7:4] Oversampling factor low: master only */ +#define SPI_1_I2C_CTRL_M_READY_DATA_ACK_POS (8u) /* [8] Master ACKs data while RX FIFO != FULL*/ +#define SPI_1_I2C_CTRL_M_NOT_READY_DATA_NACK_POS (9u) /* [9] Master NACKs data if RX FIFO == FULL */ +#define SPI_1_I2C_CTRL_S_GENERAL_IGNORE_POS (11u) /* [11] Slave ignores General call */ +#define SPI_1_I2C_CTRL_S_READY_ADDR_ACK_POS (12u) /* [12] Slave ACKs Address if RX FIFO != FULL */ +#define SPI_1_I2C_CTRL_S_READY_DATA_ACK_POS (13u) /* [13] Slave ACKs data while RX FIFO == FULL */ +#define SPI_1_I2C_CTRL_S_NOT_READY_ADDR_NACK_POS (14u) /* [14] Slave NACKs address if RX FIFO == FULL*/ +#define SPI_1_I2C_CTRL_S_NOT_READY_DATA_NACK_POS (15u) /* [15] Slave NACKs data if RX FIFO is FULL */ +#define SPI_1_I2C_CTRL_LOOPBACK_POS (16u) /* [16] Loop-back */ +#define SPI_1_I2C_CTRL_SLAVE_MODE_POS (30u) /* [30] Slave mode enabled */ +#define SPI_1_I2C_CTRL_MASTER_MODE_POS (31u) /* [31] Master mode enabled */ +#define SPI_1_I2C_CTRL_HIGH_PHASE_OVS_MASK ((uint32) 0x0Fu) +#define SPI_1_I2C_CTRL_LOW_PHASE_OVS_MASK ((uint32) 0x0Fu << \ + SPI_1_I2C_CTRL_LOW_PHASE_OVS_POS) +#define SPI_1_I2C_CTRL_M_READY_DATA_ACK ((uint32) 0x01u << \ + SPI_1_I2C_CTRL_M_READY_DATA_ACK_POS) +#define SPI_1_I2C_CTRL_M_NOT_READY_DATA_NACK ((uint32) 0x01u << \ + SPI_1_I2C_CTRL_M_NOT_READY_DATA_NACK_POS) +#define SPI_1_I2C_CTRL_S_GENERAL_IGNORE ((uint32) 0x01u << \ + SPI_1_I2C_CTRL_S_GENERAL_IGNORE_POS) +#define SPI_1_I2C_CTRL_S_READY_ADDR_ACK ((uint32) 0x01u << \ + SPI_1_I2C_CTRL_S_READY_ADDR_ACK_POS) +#define SPI_1_I2C_CTRL_S_READY_DATA_ACK ((uint32) 0x01u << \ + SPI_1_I2C_CTRL_S_READY_DATA_ACK_POS) +#define SPI_1_I2C_CTRL_S_NOT_READY_ADDR_NACK ((uint32) 0x01u << \ + SPI_1_I2C_CTRL_S_NOT_READY_ADDR_NACK_POS) +#define SPI_1_I2C_CTRL_S_NOT_READY_DATA_NACK ((uint32) 0x01u << \ + SPI_1_I2C_CTRL_S_NOT_READY_DATA_NACK_POS) +#define SPI_1_I2C_CTRL_LOOPBACK ((uint32) 0x01u << \ + SPI_1_I2C_CTRL_LOOPBACK_POS) +#define SPI_1_I2C_CTRL_SLAVE_MODE ((uint32) 0x01u << \ + SPI_1_I2C_CTRL_SLAVE_MODE_POS) +#define SPI_1_I2C_CTRL_MASTER_MODE ((uint32) 0x01u << \ + SPI_1_I2C_CTRL_MASTER_MODE_POS) +#define SPI_1_I2C_CTRL_SLAVE_MASTER_MODE_MASK ((uint32) 0x03u << \ + SPI_1_I2C_CTRL_SLAVE_MODE_POS) + +/* SPI_1_I2C_STATUS_REG */ +#define SPI_1_I2C_STATUS_BUS_BUSY_POS (0u) /* [0] Bus busy: internally clocked */ +#define SPI_1_I2C_STATUS_S_READ_POS (4u) /* [4] Slave is read by master */ +#define SPI_1_I2C_STATUS_M_READ_POS (5u) /* [5] Master reads Slave */ +#define SPI_1_I2C_STATUS_EZBUF_ADDR_POS (8u) /* [15:8] EZAddress */ +#define SPI_1_I2C_STATUS_BUS_BUSY ((uint32) 0x01u) +#define SPI_1_I2C_STATUS_S_READ ((uint32) 0x01u << SPI_1_I2C_STATUS_S_READ_POS) +#define SPI_1_I2C_STATUS_M_READ ((uint32) 0x01u << SPI_1_I2C_STATUS_M_READ_POS) +#define SPI_1_I2C_STATUS_EZBUF_ADDR_MASK ((uint32) 0xFFu << SPI_1_I2C_STATUS_EZBUF_ADDR_POS) + +/* SPI_1_I2C_MASTER_CMD_REG */ +#define SPI_1_I2C_MASTER_CMD_M_START_POS (0u) /* [0] Master generate Start */ +#define SPI_1_I2C_MASTER_CMD_M_START_ON_IDLE_POS (1u) /* [1] Master generate Start if bus is free */ +#define SPI_1_I2C_MASTER_CMD_M_ACK_POS (2u) /* [2] Master generate ACK */ +#define SPI_1_I2C_MASTER_CMD_M_NACK_POS (3u) /* [3] Master generate NACK */ +#define SPI_1_I2C_MASTER_CMD_M_STOP_POS (4u) /* [4] Master generate Stop */ +#define SPI_1_I2C_MASTER_CMD_M_START ((uint32) 0x01u) +#define SPI_1_I2C_MASTER_CMD_M_START_ON_IDLE ((uint32) 0x01u << \ + SPI_1_I2C_MASTER_CMD_M_START_ON_IDLE_POS) +#define SPI_1_I2C_MASTER_CMD_M_ACK ((uint32) 0x01u << \ + SPI_1_I2C_MASTER_CMD_M_ACK_POS) +#define SPI_1_I2C_MASTER_CMD_M_NACK ((uint32) 0x01u << \ + SPI_1_I2C_MASTER_CMD_M_NACK_POS) +#define SPI_1_I2C_MASTER_CMD_M_STOP ((uint32) 0x01u << \ + SPI_1_I2C_MASTER_CMD_M_STOP_POS) + +/* SPI_1_I2C_SLAVE_CMD_REG */ +#define SPI_1_I2C_SLAVE_CMD_S_ACK_POS (0u) /* [0] Slave generate ACK */ +#define SPI_1_I2C_SLAVE_CMD_S_NACK_POS (1u) /* [1] Slave generate NACK */ +#define SPI_1_I2C_SLAVE_CMD_S_ACK ((uint32) 0x01u) +#define SPI_1_I2C_SLAVE_CMD_S_NACK ((uint32) 0x01u << SPI_1_I2C_SLAVE_CMD_S_NACK_POS) + +#define SPI_1_I2C_SLAVE_CMD_S_ACK_POS (0u) /* [0] Slave generate ACK */ +#define SPI_1_I2C_SLAVE_CMD_S_NACK_POS (1u) /* [1] Slave generate NACK */ +#define SPI_1_I2C_SLAVE_CMD_S_ACK ((uint32) 0x01u) +#define SPI_1_I2C_SLAVE_CMD_S_NACK ((uint32) 0x01u << SPI_1_I2C_SLAVE_CMD_S_NACK_POS) + +/* SPI_1_I2C_CFG_REG */ +#if (SPI_1_CY_SCBIP_V0) +#define SPI_1_I2C_CFG_SDA_FILT_HYS_POS (0u) /* [1:0] Trim bits for the I2C SDA filter */ +#define SPI_1_I2C_CFG_SDA_FILT_TRIM_POS (2u) /* [3:2] Trim bits for the I2C SDA filter */ +#define SPI_1_I2C_CFG_SCL_FILT_HYS_POS (4u) /* [5:4] Trim bits for the I2C SCL filter */ +#define SPI_1_I2C_CFG_SCL_FILT_TRIM_POS (6u) /* [7:6] Trim bits for the I2C SCL filter */ +#define SPI_1_I2C_CFG_SDA_FILT_OUT_HYS_POS (8u) /* [9:8] Trim bits for I2C SDA filter output path */ +#define SPI_1_I2C_CFG_SDA_FILT_OUT_TRIM_POS (10u) /* [11:10] Trim bits for I2C SDA filter output path */ +#define SPI_1_I2C_CFG_SDA_FILT_HS_POS (16u) /* [16] '0': 50 ns filter, '1': 10 ns filter */ +#define SPI_1_I2C_CFG_SDA_FILT_ENABLED_POS (17u) /* [17] I2C SDA filter enabled */ +#define SPI_1_I2C_CFG_SCL_FILT_HS_POS (24u) /* [24] '0': 50 ns filter, '1': 10 ns filter */ +#define SPI_1_I2C_CFG_SCL_FILT_ENABLED_POS (25u) /* [25] I2C SCL filter enabled */ +#define SPI_1_I2C_CFG_SDA_FILT_OUT_HS_POS (26u) /* [26] '0': 50 ns filter, '1': 10 ns filter */ +#define SPI_1_I2C_CFG_SDA_FILT_OUT_ENABLED_POS (27u) /* [27] I2C SDA output delay filter enabled */ +#define SPI_1_I2C_CFG_SDA_FILT_HYS_MASK ((uint32) 0x03u) +#define SPI_1_I2C_CFG_SDA_FILT_TRIM_MASK ((uint32) 0x03u << \ + SPI_1_I2C_CFG_SDA_FILT_TRIM_POS) +#define SPI_1_I2C_CFG_SCL_FILT_HYS_MASK ((uint32) 0x03u << \ + SPI_1_I2C_CFG_SCL_FILT_HYS_POS) +#define SPI_1_I2C_CFG_SCL_FILT_TRIM_MASK ((uint32) 0x03u << \ + SPI_1_I2C_CFG_SCL_FILT_TRIM_POS) +#define SPI_1_I2C_CFG_SDA_FILT_OUT_HYS_MASK ((uint32) 0x03u << \ + SPI_1_I2C_CFG_SDA_FILT_OUT_HYS_POS) +#define SPI_1_I2C_CFG_SDA_FILT_OUT_TRIM_MASK ((uint32) 0x03u << \ + SPI_1_I2C_CFG_SDA_FILT_OUT_TRIM_POS) +#define SPI_1_I2C_CFG_SDA_FILT_HS ((uint32) 0x01u << \ + SPI_1_I2C_CFG_SDA_FILT_HS_POS) +#define SPI_1_I2C_CFG_SDA_FILT_ENABLED ((uint32) 0x01u << \ + SPI_1_I2C_CFG_SDA_FILT_ENABLED_POS) +#define SPI_1_I2C_CFG_SCL_FILT_HS ((uint32) 0x01u << \ + SPI_1_I2C_CFG_SCL_FILT_HS_POS) +#define SPI_1_I2C_CFG_SCL_FILT_ENABLED ((uint32) 0x01u << \ + SPI_1_I2C_CFG_SCL_FILT_ENABLED_POS) +#define SPI_1_I2C_CFG_SDA_FILT_OUT_HS ((uint32) 0x01u << \ + SPI_1_I2C_CFG_SDA_FILT_OUT_HS_POS) +#define SPI_1_I2C_CFG_SDA_FILT_OUT_ENABLED ((uint32) 0x01u << \ + SPI_1_I2C_CFG_SDA_FILT_OUT_ENABLED_POS) +#else +#define SPI_1_I2C_CFG_SDA_IN_FILT_TRIM_POS (0u) /* [1:0] Trim bits for "i2c_sda_in" 50 ns filter */ +#define SPI_1_I2C_CFG_SDA_IN_FILT_SEL_POS (4u) /* [4] "i2c_sda_in" filter delay: 0 ns and 50 ns */ +#define SPI_1_I2C_CFG_SCL_IN_FILT_TRIM_POS (8u) /* [9:8] Trim bits for "i2c_scl_in" 50 ns filter */ +#define SPI_1_I2C_CFG_SCL_IN_FILT_SEL_POS (12u) /* [12] "i2c_scl_in" filter delay: 0 ns and 50 ns */ +#define SPI_1_I2C_CFG_SDA_OUT_FILT0_TRIM_POS (16u) /* [17:16] Trim bits for "i2c_sda_out" 50 ns filter 0 */ +#define SPI_1_I2C_CFG_SDA_OUT_FILT1_TRIM_POS (18u) /* [19:18] Trim bits for "i2c_sda_out" 50 ns filter 1 */ +#define SPI_1_I2C_CFG_SDA_OUT_FILT2_TRIM_POS (20u) /* [21:20] Trim bits for "i2c_sda_out" 50 ns filter 2 */ +#define SPI_1_I2C_CFG_SDA_OUT_FILT_SEL_POS (28u) /* [29:28] Cumulative "i2c_sda_out" filter delay: */ + +#define SPI_1_I2C_CFG_SDA_IN_FILT_TRIM_MASK ((uint32) 0x03u) +#define SPI_1_I2C_CFG_SDA_IN_FILT_SEL ((uint32) 0x01u << SPI_1_I2C_CFG_SDA_IN_FILT_SEL_POS) +#define SPI_1_I2C_CFG_SCL_IN_FILT_TRIM_MASK ((uint32) 0x03u << \ + SPI_1_I2C_CFG_SCL_IN_FILT_TRIM_POS) +#define SPI_1_I2C_CFG_SCL_IN_FILT_SEL ((uint32) 0x01u << SPI_1_I2C_CFG_SCL_IN_FILT_SEL_POS) +#define SPI_1_I2C_CFG_SDA_OUT_FILT0_TRIM_MASK ((uint32) 0x03u << \ + SPI_1_I2C_CFG_SDA_OUT_FILT0_TRIM_POS) +#define SPI_1_I2C_CFG_SDA_OUT_FILT1_TRIM_MASK ((uint32) 0x03u << \ + SPI_1_I2C_CFG_SDA_OUT_FILT1_TRIM_POS) +#define SPI_1_I2C_CFG_SDA_OUT_FILT2_TRIM_MASK ((uint32) 0x03u << \ + SPI_1_I2C_CFG_SDA_OUT_FILT2_TRIM_POS) +#define SPI_1_I2C_CFG_SDA_OUT_FILT_SEL_MASK ((uint32) 0x03u << \ + SPI_1_I2C_CFG_SDA_OUT_FILT_SEL_POS) +#endif /* (SPI_1_CY_SCBIP_V0) */ + + +/* SPI_1_TX_CTRL_REG */ +#define SPI_1_TX_CTRL_DATA_WIDTH_POS (0u) /* [3:0] Data frame width: (Data width - 1) */ +#define SPI_1_TX_CTRL_MSB_FIRST_POS (8u) /* [8] MSB first shifter-out */ +#define SPI_1_TX_CTRL_ENABLED_POS (31u) /* [31] Transmitter enabled */ +#define SPI_1_TX_CTRL_DATA_WIDTH_MASK ((uint32) 0x0Fu) +#define SPI_1_TX_CTRL_MSB_FIRST ((uint32) 0x01u << SPI_1_TX_CTRL_MSB_FIRST_POS) +#define SPI_1_TX_CTRL_LSB_FIRST ((uint32) 0x00u) +#define SPI_1_TX_CTRL_ENABLED ((uint32) 0x01u << SPI_1_TX_CTRL_ENABLED_POS) + +/* SPI_1_TX_CTRL_FIFO_REG */ +#define SPI_1_TX_FIFO_CTRL_TRIGGER_LEVEL_POS (0u) /* [2:0] Trigger level */ +#define SPI_1_TX_FIFO_CTRL_CLEAR_POS (16u) /* [16] Clear TX FIFO: cleared after set */ +#define SPI_1_TX_FIFO_CTRL_FREEZE_POS (17u) /* [17] Freeze TX FIFO: HW do not inc read pointer */ +#define SPI_1_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK ((uint32) SPI_1_FF_DATA_NR_LOG2_MASK) +#define SPI_1_TX_FIFO_CTRL_CLEAR ((uint32) 0x01u << SPI_1_TX_FIFO_CTRL_CLEAR_POS) +#define SPI_1_TX_FIFO_CTRL_FREEZE ((uint32) 0x01u << SPI_1_TX_FIFO_CTRL_FREEZE_POS) + +/* SPI_1_TX_FIFO_STATUS_REG */ +#define SPI_1_TX_FIFO_STATUS_USED_POS (0u) /* [3:0] Amount of entries in TX FIFO */ +#define SPI_1_TX_FIFO_SR_VALID_POS (15u) /* [15] Shifter status of TX FIFO */ +#define SPI_1_TX_FIFO_STATUS_RD_PTR_POS (16u) /* [18:16] TX FIFO read pointer */ +#define SPI_1_TX_FIFO_STATUS_WR_PTR_POS (24u) /* [26:24] TX FIFO write pointer */ +#define SPI_1_TX_FIFO_STATUS_USED_MASK ((uint32) SPI_1_FF_DATA_NR_LOG2_PLUS1_MASK) +#define SPI_1_TX_FIFO_SR_VALID ((uint32) 0x01u << SPI_1_TX_FIFO_SR_VALID_POS) +#define SPI_1_TX_FIFO_STATUS_RD_PTR_MASK ((uint32) SPI_1_FF_DATA_NR_LOG2_MASK << \ + SPI_1_TX_FIFO_STATUS_RD_PTR_POS) +#define SPI_1_TX_FIFO_STATUS_WR_PTR_MASK ((uint32) SPI_1_FF_DATA_NR_LOG2_MASK << \ + SPI_1_TX_FIFO_STATUS_WR_PTR_POS) + +/* SPI_1_TX_FIFO_WR_REG */ +#define SPI_1_TX_FIFO_WR_POS (0u) /* [15:0] Data written into TX FIFO */ +#define SPI_1_TX_FIFO_WR_MASK ((uint32) 0xFFu) + +/* SPI_1_RX_CTRL_REG */ +#define SPI_1_RX_CTRL_DATA_WIDTH_POS (0u) /* [3:0] Data frame width: (Data width - 1) */ +#define SPI_1_RX_CTRL_MSB_FIRST_POS (8u) /* [8] MSB first shifter-out */ +#define SPI_1_RX_CTRL_MEDIAN_POS (9u) /* [9] Median filter */ +#define SPI_1_RX_CTRL_ENABLED_POS (31u) /* [31] Receiver enabled */ +#define SPI_1_RX_CTRL_DATA_WIDTH_MASK ((uint32) 0x0Fu) +#define SPI_1_RX_CTRL_MSB_FIRST ((uint32) 0x01u << SPI_1_RX_CTRL_MSB_FIRST_POS) +#define SPI_1_RX_CTRL_LSB_FIRST ((uint32) 0x00u) +#define SPI_1_RX_CTRL_MEDIAN ((uint32) 0x01u << SPI_1_RX_CTRL_MEDIAN_POS) +#define SPI_1_RX_CTRL_ENABLED ((uint32) 0x01u << SPI_1_RX_CTRL_ENABLED_POS) + + +/* SPI_1_RX_FIFO_CTRL_REG */ +#define SPI_1_RX_FIFO_CTRL_TRIGGER_LEVEL_POS (0u) /* [2:0] Trigger level */ +#define SPI_1_RX_FIFO_CTRL_CLEAR_POS (16u) /* [16] Clear RX FIFO: clear after set */ +#define SPI_1_RX_FIFO_CTRL_FREEZE_POS (17u) /* [17] Freeze RX FIFO: HW writes has not effect */ +#define SPI_1_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK ((uint32) SPI_1_FF_DATA_NR_LOG2_MASK) +#define SPI_1_RX_FIFO_CTRL_CLEAR ((uint32) 0x01u << SPI_1_RX_FIFO_CTRL_CLEAR_POS) +#define SPI_1_RX_FIFO_CTRL_FREEZE ((uint32) 0x01u << SPI_1_RX_FIFO_CTRL_FREEZE_POS) + +/* SPI_1_RX_FIFO_STATUS_REG */ +#define SPI_1_RX_FIFO_STATUS_USED_POS (0u) /* [3:0] Amount of entries in RX FIFO */ +#define SPI_1_RX_FIFO_SR_VALID_POS (15u) /* [15] Shifter status of RX FIFO */ +#define SPI_1_RX_FIFO_STATUS_RD_PTR_POS (16u) /* [18:16] RX FIFO read pointer */ +#define SPI_1_RX_FIFO_STATUS_WR_PTR_POS (24u) /* [26:24] RX FIFO write pointer */ +#define SPI_1_RX_FIFO_STATUS_USED_MASK ((uint32) SPI_1_FF_DATA_NR_LOG2_PLUS1_MASK) +#define SPI_1_RX_FIFO_SR_VALID ((uint32) 0x01u << SPI_1_RX_FIFO_SR_VALID_POS) +#define SPI_1_RX_FIFO_STATUS_RD_PTR_MASK ((uint32) SPI_1_FF_DATA_NR_LOG2_MASK << \ + SPI_1_RX_FIFO_STATUS_RD_PTR_POS) +#define SPI_1_RX_FIFO_STATUS_WR_PTR_MASK ((uint32) SPI_1_FF_DATA_NR_LOG2_MASK << \ + SPI_1_RX_FIFO_STATUS_WR_PTR_POS) + +/* SPI_1_RX_MATCH_REG */ +#define SPI_1_RX_MATCH_ADDR_POS (0u) /* [7:0] Slave address */ +#define SPI_1_RX_MATCH_MASK_POS (16u) /* [23:16] Slave address mask: 0 - doesn't care */ +#define SPI_1_RX_MATCH_ADDR_MASK ((uint32) 0xFFu) +#define SPI_1_RX_MATCH_MASK_MASK ((uint32) 0xFFu << SPI_1_RX_MATCH_MASK_POS) + +/* SPI_1_RX_FIFO_WR_REG */ +#define SPI_1_RX_FIFO_RD_POS (0u) /* [15:0] Data read from RX FIFO */ +#define SPI_1_RX_FIFO_RD_MASK ((uint32) 0xFFu) + +/* SPI_1_RX_FIFO_RD_SILENT_REG */ +#define SPI_1_RX_FIFO_RD_SILENT_POS (0u) /* [15:0] Data read from RX FIFO: not remove data from FIFO */ +#define SPI_1_RX_FIFO_RD_SILENT_MASK ((uint32) 0xFFu) + +/* SPI_1_RX_FIFO_RD_SILENT_REG */ +#define SPI_1_RX_FIFO_RD_SILENT_POS (0u) /* [15:0] Data read from RX FIFO: not remove data from FIFO */ +#define SPI_1_RX_FIFO_RD_SILENT_MASK ((uint32) 0xFFu) + +/* SPI_1_EZBUF_DATA_REG */ +#define SPI_1_EZBUF_DATA_POS (0u) /* [7:0] Data from EZ Memory */ +#define SPI_1_EZBUF_DATA_MASK ((uint32) 0xFFu) + +/* SPI_1_INTR_CAUSE_REG */ +#define SPI_1_INTR_CAUSE_MASTER_POS (0u) /* [0] Master interrupt active */ +#define SPI_1_INTR_CAUSE_SLAVE_POS (1u) /* [1] Slave interrupt active */ +#define SPI_1_INTR_CAUSE_TX_POS (2u) /* [2] Transmitter interrupt active */ +#define SPI_1_INTR_CAUSE_RX_POS (3u) /* [3] Receiver interrupt active */ +#define SPI_1_INTR_CAUSE_I2C_EC_POS (4u) /* [4] Externally clock I2C interrupt active */ +#define SPI_1_INTR_CAUSE_SPI_EC_POS (5u) /* [5] Externally clocked SPI interrupt active */ +#define SPI_1_INTR_CAUSE_MASTER ((uint32) 0x01u) +#define SPI_1_INTR_CAUSE_SLAVE ((uint32) 0x01u << SPI_1_INTR_CAUSE_SLAVE_POS) +#define SPI_1_INTR_CAUSE_TX ((uint32) 0x01u << SPI_1_INTR_CAUSE_TX_POS) +#define SPI_1_INTR_CAUSE_RX ((uint32) 0x01u << SPI_1_INTR_CAUSE_RX_POS) +#define SPI_1_INTR_CAUSE_I2C_EC ((uint32) 0x01u << SPI_1_INTR_CAUSE_I2C_EC_POS) +#define SPI_1_INTR_CAUSE_SPI_EC ((uint32) 0x01u << SPI_1_INTR_CAUSE_SPI_EC_POS) + +/* SPI_1_INTR_SPI_EC_REG, SPI_1_INTR_SPI_EC_MASK_REG, SPI_1_INTR_SPI_EC_MASKED_REG */ +#define SPI_1_INTR_SPI_EC_WAKE_UP_POS (0u) /* [0] Address match: triggers wakeup of chip */ +#define SPI_1_INTR_SPI_EC_EZBUF_STOP_POS (1u) /* [1] Externally clocked Stop detected */ +#define SPI_1_INTR_SPI_EC_EZBUF_WRITE_STOP_POS (2u) /* [2] Externally clocked Write Stop detected */ +#define SPI_1_INTR_SPI_EC_WAKE_UP ((uint32) 0x01u) +#define SPI_1_INTR_SPI_EC_EZBUF_STOP ((uint32) 0x01u << \ + SPI_1_INTR_SPI_EC_EZBUF_STOP_POS) +#define SPI_1_INTR_SPI_EC_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + SPI_1_INTR_SPI_EC_EZBUF_WRITE_STOP_POS) + +/* SPI_1_INTR_I2C_EC, SPI_1_INTR_I2C_EC_MASK, SPI_1_INTR_I2C_EC_MASKED */ +#define SPI_1_INTR_I2C_EC_WAKE_UP_POS (0u) /* [0] Address match: triggers wakeup of chip */ +#define SPI_1_INTR_I2C_EC_EZBUF_STOP_POS (1u) /* [1] Externally clocked Stop detected */ +#define SPI_1_INTR_I2C_EC_EZBUF_WRITE_STOP_POS (2u) /* [2] Externally clocked Write Stop detected */ +#define SPI_1_INTR_I2C_EC_WAKE_UP ((uint32) 0x01u) +#define SPI_1_INTR_I2C_EC_EZBUF_STOP ((uint32) 0x01u << \ + SPI_1_INTR_I2C_EC_EZBUF_STOP_POS) +#define SPI_1_INTR_I2C_EC_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + SPI_1_INTR_I2C_EC_EZBUF_WRITE_STOP_POS) + +/* SPI_1_INTR_MASTER, SPI_1_INTR_MASTER_SET, + SPI_1_INTR_MASTER_MASK, SPI_1_INTR_MASTER_MASKED */ +#define SPI_1_INTR_MASTER_I2C_ARB_LOST_POS (0u) /* [0] Master lost arbitration */ +#define SPI_1_INTR_MASTER_I2C_NACK_POS (1u) /* [1] Master receives NACK: address or write to slave */ +#define SPI_1_INTR_MASTER_I2C_ACK_POS (2u) /* [2] Master receives NACK: address or write to slave */ +#define SPI_1_INTR_MASTER_I2C_STOP_POS (4u) /* [4] Master detects the Stop: only self generated Stop*/ +#define SPI_1_INTR_MASTER_I2C_BUS_ERROR_POS (8u) /* [8] Master detects bus error: misplaced Start or Stop*/ +#define SPI_1_INTR_MASTER_SPI_DONE_POS (9u) /* [9] Master complete transfer: Only for SPI */ +#define SPI_1_INTR_MASTER_I2C_ARB_LOST ((uint32) 0x01u) +#define SPI_1_INTR_MASTER_I2C_NACK ((uint32) 0x01u << SPI_1_INTR_MASTER_I2C_NACK_POS) +#define SPI_1_INTR_MASTER_I2C_ACK ((uint32) 0x01u << SPI_1_INTR_MASTER_I2C_ACK_POS) +#define SPI_1_INTR_MASTER_I2C_STOP ((uint32) 0x01u << SPI_1_INTR_MASTER_I2C_STOP_POS) +#define SPI_1_INTR_MASTER_I2C_BUS_ERROR ((uint32) 0x01u << \ + SPI_1_INTR_MASTER_I2C_BUS_ERROR_POS) +#define SPI_1_INTR_MASTER_SPI_DONE ((uint32) 0x01u << SPI_1_INTR_MASTER_SPI_DONE_POS) + +/* +* SPI_1_INTR_SLAVE, SPI_1_INTR_SLAVE_SET, +* SPI_1_INTR_SLAVE_MASK, SPI_1_INTR_SLAVE_MASKED +*/ +#define SPI_1_INTR_SLAVE_I2C_ARB_LOST_POS (0u) /* [0] Slave lost arbitration */ +#define SPI_1_INTR_SLAVE_I2C_NACK_POS (1u) /* [1] Slave receives NACK: master reads data */ +#define SPI_1_INTR_SLAVE_I2C_ACK_POS (2u) /* [2] Slave receives ACK: master reads data */ +#define SPI_1_INTR_SLAVE_I2C_WRITE_STOP_POS (3u) /* [3] Slave detects end of write transaction */ +#define SPI_1_INTR_SLAVE_I2C_STOP_POS (4u) /* [4] Slave detects end of transaction intended */ +#define SPI_1_INTR_SLAVE_I2C_START_POS (5u) /* [5] Slave detects Start */ +#define SPI_1_INTR_SLAVE_I2C_ADDR_MATCH_POS (6u) /* [6] Slave address matches */ +#define SPI_1_INTR_SLAVE_I2C_GENERAL_POS (7u) /* [7] General call received */ +#define SPI_1_INTR_SLAVE_I2C_BUS_ERROR_POS (8u) /* [8] Slave detects bus error */ +#define SPI_1_INTR_SLAVE_SPI_EZBUF_WRITE_STOP_POS (9u) /* [9] Slave write complete: Only for SPI */ +#define SPI_1_INTR_SLAVE_SPI_EZBUF_STOP_POS (10u) /* [10] Slave end of transaction: Only for SPI */ +#define SPI_1_INTR_SLAVE_SPI_BUS_ERROR_POS (11u) /* [11] Slave detects bus error: Only for SPI */ +#define SPI_1_INTR_SLAVE_I2C_ARB_LOST ((uint32) 0x01u) +#define SPI_1_INTR_SLAVE_I2C_NACK ((uint32) 0x01u << \ + SPI_1_INTR_SLAVE_I2C_NACK_POS) +#define SPI_1_INTR_SLAVE_I2C_ACK ((uint32) 0x01u << \ + SPI_1_INTR_SLAVE_I2C_ACK_POS) +#define SPI_1_INTR_SLAVE_I2C_WRITE_STOP ((uint32) 0x01u << \ + SPI_1_INTR_SLAVE_I2C_WRITE_STOP_POS) +#define SPI_1_INTR_SLAVE_I2C_STOP ((uint32) 0x01u << \ + SPI_1_INTR_SLAVE_I2C_STOP_POS) +#define SPI_1_INTR_SLAVE_I2C_START ((uint32) 0x01u << \ + SPI_1_INTR_SLAVE_I2C_START_POS) +#define SPI_1_INTR_SLAVE_I2C_ADDR_MATCH ((uint32) 0x01u << \ + SPI_1_INTR_SLAVE_I2C_ADDR_MATCH_POS) +#define SPI_1_INTR_SLAVE_I2C_GENERAL ((uint32) 0x01u << \ + SPI_1_INTR_SLAVE_I2C_GENERAL_POS) +#define SPI_1_INTR_SLAVE_I2C_BUS_ERROR ((uint32) 0x01u << \ + SPI_1_INTR_SLAVE_I2C_BUS_ERROR_POS) +#define SPI_1_INTR_SLAVE_SPI_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + SPI_1_INTR_SLAVE_SPI_EZBUF_WRITE_STOP_POS) +#define SPI_1_INTR_SLAVE_SPI_EZBUF_STOP ((uint32) 0x01u << \ + SPI_1_INTR_SLAVE_SPI_EZBUF_STOP_POS) +#define SPI_1_INTR_SLAVE_SPI_BUS_ERROR ((uint32) 0x01u << \ + SPI_1_INTR_SLAVE_SPI_BUS_ERROR_POS) + +/* +* SPI_1_INTR_TX, SPI_1_INTR_TX_SET, +* SPI_1_INTR_TX_MASK, SPI_1_INTR_TX_MASKED +*/ +#define SPI_1_INTR_TX_TRIGGER_POS (0u) /* [0] Trigger on TX FIFO entires */ +#define SPI_1_INTR_TX_NOT_FULL_POS (1u) /* [1] TX FIFO is not full */ +#define SPI_1_INTR_TX_EMPTY_POS (4u) /* [4] TX FIFO is empty */ +#define SPI_1_INTR_TX_OVERFLOW_POS (5u) /* [5] Attempt to write to a full TX FIFO */ +#define SPI_1_INTR_TX_UNDERFLOW_POS (6u) /* [6] Attempt to read from an empty TX FIFO */ +#define SPI_1_INTR_TX_BLOCKED_POS (7u) /* [7] No access to the EZ memory */ +#define SPI_1_INTR_TX_UART_NACK_POS (8u) /* [8] UART transmitter received a NACK: SmartCard mode */ +#define SPI_1_INTR_TX_UART_DONE_POS (9u) /* [9] UART transmitter done even */ +#define SPI_1_INTR_TX_UART_ARB_LOST_POS (10u) /* [10] UART lost arbitration: LIN or SmartCard */ +#define SPI_1_INTR_TX_TRIGGER ((uint32) 0x01u) +#define SPI_1_INTR_TX_FIFO_LEVEL (SPI_1_INTR_TX_TRIGGER) +#define SPI_1_INTR_TX_NOT_FULL ((uint32) 0x01u << SPI_1_INTR_TX_NOT_FULL_POS) +#define SPI_1_INTR_TX_EMPTY ((uint32) 0x01u << SPI_1_INTR_TX_EMPTY_POS) +#define SPI_1_INTR_TX_OVERFLOW ((uint32) 0x01u << SPI_1_INTR_TX_OVERFLOW_POS) +#define SPI_1_INTR_TX_UNDERFLOW ((uint32) 0x01u << SPI_1_INTR_TX_UNDERFLOW_POS) +#define SPI_1_INTR_TX_BLOCKED ((uint32) 0x01u << SPI_1_INTR_TX_BLOCKED_POS) +#define SPI_1_INTR_TX_UART_NACK ((uint32) 0x01u << SPI_1_INTR_TX_UART_NACK_POS) +#define SPI_1_INTR_TX_UART_DONE ((uint32) 0x01u << SPI_1_INTR_TX_UART_DONE_POS) +#define SPI_1_INTR_TX_UART_ARB_LOST ((uint32) 0x01u << SPI_1_INTR_TX_UART_ARB_LOST_POS) + +/* +* SPI_1_INTR_RX, SPI_1_INTR_RX_SET, +* SPI_1_INTR_RX_MASK, SPI_1_INTR_RX_MASKED +*/ +#define SPI_1_INTR_RX_TRIGGER_POS (0u) /* [0] Trigger on RX FIFO entires */ +#define SPI_1_INTR_RX_NOT_EMPTY_POS (2u) /* [2] RX FIFO is not empty */ +#define SPI_1_INTR_RX_FULL_POS (3u) /* [3] RX FIFO is full */ +#define SPI_1_INTR_RX_OVERFLOW_POS (5u) /* [5] Attempt to write to a full RX FIFO */ +#define SPI_1_INTR_RX_UNDERFLOW_POS (6u) /* [6] Attempt to read from an empty RX FIFO */ +#define SPI_1_INTR_RX_BLOCKED_POS (7u) /* [7] No access to the EZ memory */ +#define SPI_1_INTR_RX_FRAME_ERROR_POS (8u) /* [8] Frame error in received data frame */ +#define SPI_1_INTR_RX_PARITY_ERROR_POS (9u) /* [9] Parity error in received data frame */ +#define SPI_1_INTR_RX_BAUD_DETECT_POS (10u) /* [10] LIN baud rate detection is completed */ +#define SPI_1_INTR_RX_BREAK_DETECT_POS (11u) /* [11] Break detection is successful */ +#define SPI_1_INTR_RX_TRIGGER ((uint32) 0x01u) +#define SPI_1_INTR_RX_FIFO_LEVEL (SPI_1_INTR_RX_TRIGGER) +#define SPI_1_INTR_RX_NOT_EMPTY ((uint32) 0x01u << SPI_1_INTR_RX_NOT_EMPTY_POS) +#define SPI_1_INTR_RX_FULL ((uint32) 0x01u << SPI_1_INTR_RX_FULL_POS) +#define SPI_1_INTR_RX_OVERFLOW ((uint32) 0x01u << SPI_1_INTR_RX_OVERFLOW_POS) +#define SPI_1_INTR_RX_UNDERFLOW ((uint32) 0x01u << SPI_1_INTR_RX_UNDERFLOW_POS) +#define SPI_1_INTR_RX_BLOCKED ((uint32) 0x01u << SPI_1_INTR_RX_BLOCKED_POS) +#define SPI_1_INTR_RX_FRAME_ERROR ((uint32) 0x01u << SPI_1_INTR_RX_FRAME_ERROR_POS) +#define SPI_1_INTR_RX_PARITY_ERROR ((uint32) 0x01u << SPI_1_INTR_RX_PARITY_ERROR_POS) +#define SPI_1_INTR_RX_BAUD_DETECT ((uint32) 0x01u << SPI_1_INTR_RX_BAUD_DETECT_POS) +#define SPI_1_INTR_RX_BREAK_DETECT ((uint32) 0x01u << SPI_1_INTR_RX_BREAK_DETECT_POS) + +/* Define all interrupt sources */ +#define SPI_1_INTR_I2C_EC_ALL (SPI_1_INTR_I2C_EC_WAKE_UP | \ + SPI_1_INTR_I2C_EC_EZBUF_STOP | \ + SPI_1_INTR_I2C_EC_EZBUF_WRITE_STOP) + +#define SPI_1_INTR_SPI_EC_ALL (SPI_1_INTR_SPI_EC_WAKE_UP | \ + SPI_1_INTR_SPI_EC_EZBUF_STOP | \ + SPI_1_INTR_SPI_EC_EZBUF_WRITE_STOP) + +#define SPI_1_INTR_MASTER_ALL (SPI_1_INTR_MASTER_I2C_ARB_LOST | \ + SPI_1_INTR_MASTER_I2C_NACK | \ + SPI_1_INTR_MASTER_I2C_ACK | \ + SPI_1_INTR_MASTER_I2C_STOP | \ + SPI_1_INTR_MASTER_I2C_BUS_ERROR | \ + SPI_1_INTR_MASTER_SPI_DONE) + +#define SPI_1_INTR_SLAVE_ALL (SPI_1_INTR_SLAVE_I2C_ARB_LOST | \ + SPI_1_INTR_SLAVE_I2C_NACK | \ + SPI_1_INTR_SLAVE_I2C_ACK | \ + SPI_1_INTR_SLAVE_I2C_WRITE_STOP | \ + SPI_1_INTR_SLAVE_I2C_STOP | \ + SPI_1_INTR_SLAVE_I2C_START | \ + SPI_1_INTR_SLAVE_I2C_ADDR_MATCH | \ + SPI_1_INTR_SLAVE_I2C_GENERAL | \ + SPI_1_INTR_SLAVE_I2C_BUS_ERROR | \ + SPI_1_INTR_SLAVE_SPI_EZBUF_WRITE_STOP | \ + SPI_1_INTR_SLAVE_SPI_EZBUF_STOP | \ + SPI_1_INTR_SLAVE_SPI_BUS_ERROR) + +#define SPI_1_INTR_TX_ALL (SPI_1_INTR_TX_TRIGGER | \ + SPI_1_INTR_TX_NOT_FULL | \ + SPI_1_INTR_TX_EMPTY | \ + SPI_1_INTR_TX_OVERFLOW | \ + SPI_1_INTR_TX_UNDERFLOW | \ + SPI_1_INTR_TX_BLOCKED | \ + SPI_1_INTR_TX_UART_NACK | \ + SPI_1_INTR_TX_UART_DONE | \ + SPI_1_INTR_TX_UART_ARB_LOST) + +#define SPI_1_INTR_RX_ALL (SPI_1_INTR_RX_TRIGGER | \ + SPI_1_INTR_RX_NOT_EMPTY | \ + SPI_1_INTR_RX_FULL | \ + SPI_1_INTR_RX_OVERFLOW | \ + SPI_1_INTR_RX_UNDERFLOW | \ + SPI_1_INTR_RX_BLOCKED | \ + SPI_1_INTR_RX_FRAME_ERROR | \ + SPI_1_INTR_RX_PARITY_ERROR | \ + SPI_1_INTR_RX_BAUD_DETECT | \ + SPI_1_INTR_RX_BREAK_DETECT) + +/* I2C and EZI2C slave address defines */ +#define SPI_1_I2C_SLAVE_ADDR_POS (0x01u) /* 7-bit address shift */ +#define SPI_1_I2C_SLAVE_ADDR_MASK (0xFEu) /* 8-bit address mask */ + +/* OVS constants for IrDA Low Power operation */ +#define SPI_1_CTRL_OVS_IRDA_LP_OVS16 (0x00u) +#define SPI_1_CTRL_OVS_IRDA_LP_OVS32 (0x01u) +#define SPI_1_CTRL_OVS_IRDA_LP_OVS48 (0x02u) +#define SPI_1_CTRL_OVS_IRDA_LP_OVS96 (0x03u) +#define SPI_1_CTRL_OVS_IRDA_LP_OVS192 (0x04u) +#define SPI_1_CTRL_OVS_IRDA_LP_OVS768 (0x05u) +#define SPI_1_CTRL_OVS_IRDA_LP_OVS1536 (0x06u) + +/* OVS constant for IrDA */ +#define SPI_1_CTRL_OVS_IRDA_OVS16 (SPI_1_UART_IRDA_LP_OVS16) + + +/*************************************** +* Common Macro Definitions +***************************************/ + +/* Re-enables the SCB IP. A clear enable bit has a different effect +* on the scb IP depending on the version: +* CY_SCBIP_V0: resets state, status, TX and RX FIFOs. +* CY_SCBIP_V1 or later: resets state, status, TX and RX FIFOs and interrupt sources. +* Clear I2C command registers are because they are not impacted by re-enable. +*/ +#define SPI_1_SCB_SW_RESET SPI_1_I2CFwBlockReset() + +/* TX FIFO macro */ +#define SPI_1_CLEAR_TX_FIFO \ + do{ \ + SPI_1_TX_FIFO_CTRL_REG |= ((uint32) SPI_1_TX_FIFO_CTRL_CLEAR); \ + SPI_1_TX_FIFO_CTRL_REG &= ((uint32) ~SPI_1_TX_FIFO_CTRL_CLEAR); \ + }while(0) + +#define SPI_1_GET_TX_FIFO_ENTRIES (SPI_1_TX_FIFO_STATUS_REG & \ + SPI_1_TX_FIFO_STATUS_USED_MASK) + +#define SPI_1_GET_TX_FIFO_SR_VALID ((0u != (SPI_1_TX_FIFO_STATUS_REG & \ + SPI_1_TX_FIFO_SR_VALID)) ? (1u) : (0u)) + +/* RX FIFO macro */ +#define SPI_1_CLEAR_RX_FIFO \ + do{ \ + SPI_1_RX_FIFO_CTRL_REG |= ((uint32) SPI_1_RX_FIFO_CTRL_CLEAR); \ + SPI_1_RX_FIFO_CTRL_REG &= ((uint32) ~SPI_1_RX_FIFO_CTRL_CLEAR); \ + }while(0) + +#define SPI_1_GET_RX_FIFO_ENTRIES (SPI_1_RX_FIFO_STATUS_REG & \ + SPI_1_RX_FIFO_STATUS_USED_MASK) + +#define SPI_1_GET_RX_FIFO_SR_VALID ((0u != (SPI_1_RX_FIFO_STATUS_REG & \ + SPI_1_RX_FIFO_SR_VALID)) ? (1u) : (0u)) + +/* Write interrupt source: set sourceMask bits in SPI_1_INTR_X_MASK_REG */ +#define SPI_1_WRITE_INTR_I2C_EC_MASK(sourceMask) \ + do{ \ + SPI_1_INTR_I2C_EC_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#if (!SPI_1_CY_SCBIP_V1) + #define SPI_1_WRITE_INTR_SPI_EC_MASK(sourceMask) \ + do{ \ + SPI_1_INTR_SPI_EC_MASK_REG = (uint32) (sourceMask); \ + }while(0) +#endif /* (!SPI_1_CY_SCBIP_V1) */ + +#define SPI_1_WRITE_INTR_MASTER_MASK(sourceMask) \ + do{ \ + SPI_1_INTR_MASTER_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_WRITE_INTR_SLAVE_MASK(sourceMask) \ + do{ \ + SPI_1_INTR_SLAVE_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_WRITE_INTR_TX_MASK(sourceMask) \ + do{ \ + SPI_1_INTR_TX_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_WRITE_INTR_RX_MASK(sourceMask) \ + do{ \ + SPI_1_INTR_RX_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +/* Enable interrupt source: set sourceMask bits in SPI_1_INTR_X_MASK_REG */ +#define SPI_1_ENABLE_INTR_I2C_EC(sourceMask) \ + do{ \ + SPI_1_INTR_I2C_EC_MASK_REG |= (uint32) (sourceMask); \ + }while(0) +#if (!SPI_1_CY_SCBIP_V1) + #define SPI_1_ENABLE_INTR_SPI_EC(sourceMask) \ + do{ \ + SPI_1_INTR_SPI_EC_MASK_REG |= (uint32) (sourceMask); \ + }while(0) +#endif /* (!SPI_1_CY_SCBIP_V1) */ + +#define SPI_1_ENABLE_INTR_MASTER(sourceMask) \ + do{ \ + SPI_1_INTR_MASTER_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_ENABLE_INTR_SLAVE(sourceMask) \ + do{ \ + SPI_1_INTR_SLAVE_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_ENABLE_INTR_TX(sourceMask) \ + do{ \ + SPI_1_INTR_TX_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_ENABLE_INTR_RX(sourceMask) \ + do{ \ + SPI_1_INTR_RX_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +/* Disable interrupt source: clear sourceMask bits in SPI_1_INTR_X_MASK_REG */ +#define SPI_1_DISABLE_INTR_I2C_EC(sourceMask) \ + do{ \ + SPI_1_INTR_I2C_EC_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#if (!SPI_1_CY_SCBIP_V1) + #define SPI_1_DISABLE_INTR_SPI_EC(sourceMask) \ + do{ \ + SPI_1_INTR_SPI_EC_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) +#endif /* (!SPI_1_CY_SCBIP_V1) */ + +#define SPI_1_DISABLE_INTR_MASTER(sourceMask) \ + do{ \ + SPI_1_INTR_MASTER_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define SPI_1_DISABLE_INTR_SLAVE(sourceMask) \ + do{ \ + SPI_1_INTR_SLAVE_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define SPI_1_DISABLE_INTR_TX(sourceMask) \ + do{ \ + SPI_1_INTR_TX_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define SPI_1_DISABLE_INTR_RX(sourceMask) \ + do{ \ + SPI_1_INTR_RX_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +/* Set interrupt sources: write sourceMask bits in SPI_1_INTR_X_SET_REG */ +#define SPI_1_SET_INTR_MASTER(sourceMask) \ + do{ \ + SPI_1_INTR_MASTER_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_SET_INTR_SLAVE(sourceMask) \ + do{ \ + SPI_1_INTR_SLAVE_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_SET_INTR_TX(sourceMask) \ + do{ \ + SPI_1_INTR_TX_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_SET_INTR_RX(sourceMask) \ + do{ \ + SPI_1_INTR_RX_SET_REG = (uint32) (sourceMask); \ + }while(0) + +/* Clear interrupt sources: write sourceMask bits in SPI_1_INTR_X_REG */ +#define SPI_1_CLEAR_INTR_I2C_EC(sourceMask) \ + do{ \ + SPI_1_INTR_I2C_EC_REG = (uint32) (sourceMask); \ + }while(0) + +#if (!SPI_1_CY_SCBIP_V1) + #define SPI_1_CLEAR_INTR_SPI_EC(sourceMask) \ + do{ \ + SPI_1_INTR_SPI_EC_REG = (uint32) (sourceMask); \ + }while(0) +#endif /* (!SPI_1_CY_SCBIP_V1) */ + +#define SPI_1_CLEAR_INTR_MASTER(sourceMask) \ + do{ \ + SPI_1_INTR_MASTER_REG = (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_CLEAR_INTR_SLAVE(sourceMask) \ + do{ \ + SPI_1_INTR_SLAVE_REG = (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_CLEAR_INTR_TX(sourceMask) \ + do{ \ + SPI_1_INTR_TX_REG = (uint32) (sourceMask); \ + }while(0) + +#define SPI_1_CLEAR_INTR_RX(sourceMask) \ + do{ \ + SPI_1_INTR_RX_REG = (uint32) (sourceMask); \ + }while(0) + +/* Return true if sourceMask is set in SPI_1_INTR_CAUSE_REG */ +#define SPI_1_CHECK_CAUSE_INTR(sourceMask) (0u != (SPI_1_INTR_CAUSE_REG & (sourceMask))) + +/* Return true if sourceMask is set in INTR_X_MASKED_REG */ +#define SPI_1_CHECK_INTR_I2C_EC(sourceMask) (0u != (SPI_1_INTR_I2C_EC_REG & (sourceMask))) +#if (!SPI_1_CY_SCBIP_V1) + #define SPI_1_CHECK_INTR_SPI_EC(sourceMask) (0u != (SPI_1_INTR_SPI_EC_REG & (sourceMask))) +#endif /* (!SPI_1_CY_SCBIP_V1) */ +#define SPI_1_CHECK_INTR_MASTER(sourceMask) (0u != (SPI_1_INTR_MASTER_REG & (sourceMask))) +#define SPI_1_CHECK_INTR_SLAVE(sourceMask) (0u != (SPI_1_INTR_SLAVE_REG & (sourceMask))) +#define SPI_1_CHECK_INTR_TX(sourceMask) (0u != (SPI_1_INTR_TX_REG & (sourceMask))) +#define SPI_1_CHECK_INTR_RX(sourceMask) (0u != (SPI_1_INTR_RX_REG & (sourceMask))) + +/* Return true if sourceMask is set in SPI_1_INTR_X_MASKED_REG */ +#define SPI_1_CHECK_INTR_I2C_EC_MASKED(sourceMask) (0u != (SPI_1_INTR_I2C_EC_MASKED_REG & \ + (sourceMask))) +#if (!SPI_1_CY_SCBIP_V1) + #define SPI_1_CHECK_INTR_SPI_EC_MASKED(sourceMask) (0u != (SPI_1_INTR_SPI_EC_MASKED_REG & \ + (sourceMask))) +#endif /* (!SPI_1_CY_SCBIP_V1) */ +#define SPI_1_CHECK_INTR_MASTER_MASKED(sourceMask) (0u != (SPI_1_INTR_MASTER_MASKED_REG & \ + (sourceMask))) +#define SPI_1_CHECK_INTR_SLAVE_MASKED(sourceMask) (0u != (SPI_1_INTR_SLAVE_MASKED_REG & \ + (sourceMask))) +#define SPI_1_CHECK_INTR_TX_MASKED(sourceMask) (0u != (SPI_1_INTR_TX_MASKED_REG & \ + (sourceMask))) +#define SPI_1_CHECK_INTR_RX_MASKED(sourceMask) (0u != (SPI_1_INTR_RX_MASKED_REG & \ + (sourceMask))) + +/* Return true if sourceMask is set in SPI_1_CTRL_REG: generally is used to check enable bit */ +#define SPI_1_GET_CTRL_ENABLED (0u != (SPI_1_CTRL_REG & SPI_1_CTRL_ENABLED)) + +#define SPI_1_CHECK_SLAVE_AUTO_ADDR_NACK (0u != (SPI_1_I2C_CTRL_REG & \ + SPI_1_I2C_CTRL_S_NOT_READY_DATA_NACK)) + + +/*************************************** +* I2C Macro Definitions +***************************************/ + +/* Enable auto ACK/NACK */ +#define SPI_1_ENABLE_SLAVE_AUTO_ADDR_NACK \ + do{ \ + SPI_1_I2C_CTRL_REG |= SPI_1_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define SPI_1_ENABLE_SLAVE_AUTO_DATA_ACK \ + do{ \ + SPI_1_I2C_CTRL_REG |= SPI_1_I2C_CTRL_S_READY_DATA_ACK; \ + }while(0) + +#define SPI_1_ENABLE_SLAVE_AUTO_DATA_NACK \ + do{ \ + SPI_1_I2C_CTRL_REG |= SPI_1_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define SPI_1_ENABLE_MASTER_AUTO_DATA_ACK \ + do{ \ + SPI_1_I2C_CTRL_REG |= SPI_1_I2C_CTRL_M_READY_DATA_ACK; \ + }while(0) + +#define SPI_1_ENABLE_MASTER_AUTO_DATA_NACK \ + do{ \ + SPI_1_I2C_CTRL_REG |= SPI_1_I2C_CTRL_M_NOT_READY_DATA_NACK; \ + }while(0) + +/* Disable auto ACK/NACK */ +#define SPI_1_DISABLE_SLAVE_AUTO_ADDR_NACK \ + do{ \ + SPI_1_I2C_CTRL_REG &= ~SPI_1_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define SPI_1_DISABLE_SLAVE_AUTO_DATA_ACK \ + do{ \ + SPI_1_I2C_CTRL_REG &= ~SPI_1_I2C_CTRL_S_READY_DATA_ACK; \ + }while(0) + +#define SPI_1_DISABLE_SLAVE_AUTO_DATA_NACK \ + do{ \ + SPI_1_I2C_CTRL_REG &= ~SPI_1_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define SPI_1_DISABLE_MASTER_AUTO_DATA_ACK \ + do{ \ + SPI_1_I2C_CTRL_REG &= ~SPI_1_I2C_CTRL_M_READY_DATA_ACK; \ + }while(0) + +#define SPI_1_DISABLE_MASTER_AUTO_DATA_NACK \ + do{ \ + SPI_1_I2C_CTRL_REG &= ~SPI_1_I2C_CTRL_M_NOT_READY_DATA_NACK; \ + }while(0) + +/* Enable Slave autoACK/NACK Data */ +#define SPI_1_ENABLE_SLAVE_AUTO_DATA \ + do{ \ + SPI_1_I2C_CTRL_REG |= (SPI_1_I2C_CTRL_S_READY_DATA_ACK | \ + SPI_1_I2C_CTRL_S_NOT_READY_DATA_NACK); \ + }while(0) + +/* Disable Slave autoACK/NACK Data */ +#define SPI_1_DISABLE_SLAVE_AUTO_DATA \ + do{ \ + SPI_1_I2C_CTRL_REG &= ((uint32) \ + ~(SPI_1_I2C_CTRL_S_READY_DATA_ACK | \ + SPI_1_I2C_CTRL_S_NOT_READY_DATA_NACK)); \ + }while(0) + +/* Disable Master autoACK/NACK Data */ +#define SPI_1_DISABLE_MASTER_AUTO_DATA \ + do{ \ + SPI_1_I2C_CTRL_REG &= ((uint32) \ + ~(SPI_1_I2C_CTRL_M_READY_DATA_ACK | \ + SPI_1_I2C_CTRL_M_NOT_READY_DATA_NACK)); \ + }while(0) +/* Disables auto data ACK/NACK bits */ +#define SPI_1_DISABLE_AUTO_DATA \ + do{ \ + SPI_1_I2C_CTRL_REG &= ((uint32) ~(SPI_1_I2C_CTRL_M_READY_DATA_ACK | \ + SPI_1_I2C_CTRL_M_NOT_READY_DATA_NACK | \ + SPI_1_I2C_CTRL_S_READY_DATA_ACK | \ + SPI_1_I2C_CTRL_S_NOT_READY_DATA_NACK)); \ + }while(0) + +/* Master commands */ +#define SPI_1_I2C_MASTER_GENERATE_START \ + do{ \ + SPI_1_I2C_MASTER_CMD_REG = SPI_1_I2C_MASTER_CMD_M_START_ON_IDLE; \ + }while(0) + +#define SPI_1_I2C_MASTER_CLEAR_START \ + do{ \ + SPI_1_I2C_MASTER_CMD_REG = ((uint32) 0u); \ + }while(0) + +#define SPI_1_I2C_MASTER_GENERATE_RESTART SPI_1_I2CReStartGeneration() + +#define SPI_1_I2C_MASTER_GENERATE_STOP \ + do{ \ + SPI_1_I2C_MASTER_CMD_REG = \ + (SPI_1_I2C_MASTER_CMD_M_STOP | \ + (SPI_1_CHECK_I2C_STATUS(SPI_1_I2C_STATUS_M_READ) ? \ + (SPI_1_I2C_MASTER_CMD_M_NACK) : (0u))); \ + }while(0) + +#define SPI_1_I2C_MASTER_GENERATE_ACK \ + do{ \ + SPI_1_I2C_MASTER_CMD_REG = SPI_1_I2C_MASTER_CMD_M_ACK; \ + }while(0) + +#define SPI_1_I2C_MASTER_GENERATE_NACK \ + do{ \ + SPI_1_I2C_MASTER_CMD_REG = SPI_1_I2C_MASTER_CMD_M_NACK; \ + }while(0) + +/* Slave commands */ +#define SPI_1_I2C_SLAVE_GENERATE_ACK \ + do{ \ + SPI_1_I2C_SLAVE_CMD_REG = SPI_1_I2C_SLAVE_CMD_S_ACK; \ + }while(0) + +#if (SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + /* Slave NACK generation for EC_AM logic on address phase. Ticket ID #183902 */ + void SPI_1_I2CSlaveNackGeneration(void); + #define SPI_1_I2C_SLAVE_GENERATE_NACK SPI_1_I2CSlaveNackGeneration() + +#else + #define SPI_1_I2C_SLAVE_GENERATE_NACK \ + do{ \ + SPI_1_I2C_SLAVE_CMD_REG = SPI_1_I2C_SLAVE_CMD_S_NACK; \ + }while(0) +#endif /* (SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ + +#define SPI_1_I2C_SLAVE_CLEAR_NACK \ + do{ \ + SPI_1_I2C_SLAVE_CMD_REG = 0u; \ + }while(0) + +/* Return 8-bit address. The input address should be 7-bits */ +#define SPI_1_GET_I2C_8BIT_ADDRESS(addr) (((uint32) ((uint32) (addr) << \ + SPI_1_I2C_SLAVE_ADDR_POS)) & \ + SPI_1_I2C_SLAVE_ADDR_MASK) + +#define SPI_1_GET_I2C_7BIT_ADDRESS(addr) ((uint32) (addr) >> SPI_1_I2C_SLAVE_ADDR_POS) + +/* Adjust SDA filter Trim settings */ +#define SPI_1_DEFAULT_I2C_CFG_SDA_FILT_TRIM (0x02u) +#define SPI_1_EC_AM_I2C_CFG_SDA_FILT_TRIM (0x03u) + +#if (SPI_1_CY_SCBIP_V0) + #define SPI_1_SET_I2C_CFG_SDA_FILT_TRIM(sdaTrim) \ + do{ \ + SPI_1_I2C_CFG_REG = \ + ((SPI_1_I2C_CFG_REG & (uint32) ~SPI_1_I2C_CFG_SDA_FILT_TRIM_MASK) | \ + ((uint32) ((uint32) (sdaTrim) <> \ + (SPI_1_DM_SIZE * (pos)) ) + +#if (SPI_1_TX_SDA_MISO_PIN) + #define SPI_1_CHECK_TX_SDA_MISO_PIN_USED \ + (SPI_1_PIN_DM_ALG_HIZ != \ + SPI_1_GET_P4_PIN_DM(SPI_1_uart_tx_i2c_sda_spi_miso_PC, \ + SPI_1_uart_tx_i2c_sda_spi_miso_SHIFT)) +#endif /* (SPI_1_TX_SDA_MISO_PIN) */ + +#if (SPI_1_RTS_SS0_PIN) + #define SPI_1_CHECK_RTS_SS0_PIN_USED \ + (SPI_1_PIN_DM_ALG_HIZ != \ + SPI_1_GET_P4_PIN_DM(SPI_1_uart_rts_spi_ss0_PC, \ + SPI_1_uart_rts_spi_ss0_SHIFT)) +#endif /* (SPI_1_RTS_SS0_PIN) */ + +/* Set bits-mask in register */ +#define SPI_1_SET_REGISTER_BITS(reg, mask, pos, mode) \ + do \ + { \ + (reg) = (((reg) & ((uint32) ~(uint32) (mask))) | ((uint32) ((uint32) (mode) << (pos)))); \ + }while(0) + +/* Set bit in the register */ +#define SPI_1_SET_REGISTER_BIT(reg, mask, val) \ + ((val) ? ((reg) |= (mask)) : ((reg) &= ((uint32) ~((uint32) (mask))))) + +#define SPI_1_SET_HSIOM_SEL(reg, mask, pos, sel) SPI_1_SET_REGISTER_BITS(reg, mask, pos, sel) +#define SPI_1_SET_INCFG_TYPE(reg, mask, pos, intType) \ + SPI_1_SET_REGISTER_BITS(reg, mask, pos, intType) +#define SPI_1_SET_INP_DIS(reg, mask, val) SPI_1_SET_REGISTER_BIT(reg, mask, val) + +/* SPI_1_SET_I2C_SCL_DR(val) - Sets I2C SCL DR register. +* SPI_1_SET_I2C_SCL_HSIOM_SEL(sel) - Sets I2C SCL HSIOM settings. +*/ +/* SCB I2C: scl signal */ +#if (SPI_1_CY_SCBIP_V0) +#if (SPI_1_I2C_PINS) + #define SPI_1_SET_I2C_SCL_DR(val) SPI_1_scl_Write(val) + + #define SPI_1_SET_I2C_SCL_HSIOM_SEL(sel) \ + SPI_1_SET_HSIOM_SEL(SPI_1_SCL_HSIOM_REG, \ + SPI_1_SCL_HSIOM_MASK, \ + SPI_1_SCL_HSIOM_POS, \ + (sel)) + #define SPI_1_WAIT_SCL_SET_HIGH (0u == SPI_1_scl_Read()) + +/* Unconfigured SCB: scl signal */ +#elif (SPI_1_RX_WAKE_SCL_MOSI_PIN) + #define SPI_1_SET_I2C_SCL_DR(val) \ + SPI_1_uart_rx_wake_i2c_scl_spi_mosi_Write(val) + + #define SPI_1_SET_I2C_SCL_HSIOM_SEL(sel) \ + SPI_1_SET_HSIOM_SEL(SPI_1_RX_WAKE_SCL_MOSI_HSIOM_REG, \ + SPI_1_RX_WAKE_SCL_MOSI_HSIOM_MASK, \ + SPI_1_RX_WAKE_SCL_MOSI_HSIOM_POS, \ + (sel)) + + #define SPI_1_WAIT_SCL_SET_HIGH (0u == SPI_1_uart_rx_wake_i2c_scl_spi_mosi_Read()) + +#elif (SPI_1_RX_SCL_MOSI_PIN) + #define SPI_1_SET_I2C_SCL_DR(val) \ + SPI_1_uart_rx_i2c_scl_spi_mosi_Write(val) + + + #define SPI_1_SET_I2C_SCL_HSIOM_SEL(sel) \ + SPI_1_SET_HSIOM_SEL(SPI_1_RX_SCL_MOSI_HSIOM_REG, \ + SPI_1_RX_SCL_MOSI_HSIOM_MASK, \ + SPI_1_RX_SCL_MOSI_HSIOM_POS, \ + (sel)) + + #define SPI_1_WAIT_SCL_SET_HIGH (0u == SPI_1_uart_rx_i2c_scl_spi_mosi_Read()) + +#else + #define SPI_1_SET_I2C_SCL_DR(val) do{ /* Does nothing */ }while(0) + #define SPI_1_SET_I2C_SCL_HSIOM_SEL(sel) do{ /* Does nothing */ }while(0) + + #define SPI_1_WAIT_SCL_SET_HIGH (0u) +#endif /* (SPI_1_I2C_PINS) */ + +/* SCB I2C: sda signal */ +#if (SPI_1_I2C_PINS) + #define SPI_1_WAIT_SDA_SET_HIGH (0u == SPI_1_sda_Read()) +/* Unconfigured SCB: sda signal */ +#elif (SPI_1_TX_SDA_MISO_PIN) + #define SPI_1_WAIT_SDA_SET_HIGH (0u == SPI_1_uart_tx_i2c_sda_spi_miso_Read()) +#else + #define SPI_1_WAIT_SDA_SET_HIGH (0u) +#endif /* (SPI_1_MOSI_SCL_RX_PIN) */ +#endif /* (SPI_1_CY_SCBIP_V0) */ + +/* Clear UART wakeup source */ +#if (SPI_1_RX_SCL_MOSI_PIN) + #define SPI_1_CLEAR_UART_RX_WAKE_INTR do{ /* Does nothing */ }while(0) + +#elif (SPI_1_RX_WAKE_SCL_MOSI_PIN) + #define SPI_1_CLEAR_UART_RX_WAKE_INTR \ + do{ \ + (void) SPI_1_uart_rx_wake_i2c_scl_spi_mosi_ClearInterrupt(); \ + }while(0) + +#elif(SPI_1_UART_RX_WAKE_PIN) + #define SPI_1_CLEAR_UART_RX_WAKE_INTR \ + do{ \ + (void) SPI_1_rx_wake_ClearInterrupt(); \ + }while(0) +#else +#endif /* (SPI_1_RX_SCL_MOSI_PIN) */ + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +/* Unconfigured pins */ +#define SPI_1_REMOVE_MOSI_SCL_RX_WAKE_PIN SPI_1_REMOVE_RX_WAKE_SCL_MOSI_PIN +#define SPI_1_REMOVE_MOSI_SCL_RX_PIN SPI_1_REMOVE_RX_SCL_MOSI_PIN +#define SPI_1_REMOVE_MISO_SDA_TX_PIN SPI_1_REMOVE_TX_SDA_MISO_PIN +#ifndef SPI_1_REMOVE_SCLK_PIN +#define SPI_1_REMOVE_SCLK_PIN SPI_1_REMOVE_CTS_SCLK_PIN +#endif /* SPI_1_REMOVE_SCLK_PIN */ +#ifndef SPI_1_REMOVE_SS0_PIN +#define SPI_1_REMOVE_SS0_PIN SPI_1_REMOVE_RTS_SS0_PIN +#endif /* SPI_1_REMOVE_SS0_PIN */ + +/* Unconfigured pins */ +#define SPI_1_MOSI_SCL_RX_WAKE_PIN SPI_1_RX_WAKE_SCL_MOSI_PIN +#define SPI_1_MOSI_SCL_RX_PIN SPI_1_RX_SCL_MOSI_PIN +#define SPI_1_MISO_SDA_TX_PIN SPI_1_TX_SDA_MISO_PIN +#ifndef SPI_1_SCLK_PIN +#define SPI_1_SCLK_PIN SPI_1_CTS_SCLK_PIN +#endif /* SPI_1_SCLK_PIN */ +#ifndef SPI_1_SS0_PIN +#define SPI_1_SS0_PIN SPI_1_RTS_SS0_PIN +#endif /* SPI_1_SS0_PIN */ + +#if (SPI_1_MOSI_SCL_RX_WAKE_PIN) + #define SPI_1_MOSI_SCL_RX_WAKE_HSIOM_REG SPI_1_RX_WAKE_SCL_MOSI_HSIOM_REG + #define SPI_1_MOSI_SCL_RX_WAKE_HSIOM_PTR SPI_1_RX_WAKE_SCL_MOSI_HSIOM_REG + #define SPI_1_MOSI_SCL_RX_WAKE_HSIOM_MASK SPI_1_RX_WAKE_SCL_MOSI_HSIOM_REG + #define SPI_1_MOSI_SCL_RX_WAKE_HSIOM_POS SPI_1_RX_WAKE_SCL_MOSI_HSIOM_REG + + #define SPI_1_MOSI_SCL_RX_WAKE_INTCFG_REG SPI_1_RX_WAKE_SCL_MOSI_HSIOM_REG + #define SPI_1_MOSI_SCL_RX_WAKE_INTCFG_PTR SPI_1_RX_WAKE_SCL_MOSI_HSIOM_REG + + #define SPI_1_MOSI_SCL_RX_WAKE_INTCFG_TYPE_POS SPI_1_RX_WAKE_SCL_MOSI_HSIOM_REG + #define SPI_1_MOSI_SCL_RX_WAKE_INTCFG_TYPE_MASK SPI_1_RX_WAKE_SCL_MOSI_HSIOM_REG +#endif /* (SPI_1_RX_WAKE_SCL_MOSI_PIN) */ + +#if (SPI_1_MOSI_SCL_RX_PIN) + #define SPI_1_MOSI_SCL_RX_HSIOM_REG SPI_1_RX_SCL_MOSI_HSIOM_REG + #define SPI_1_MOSI_SCL_RX_HSIOM_PTR SPI_1_RX_SCL_MOSI_HSIOM_PTR + #define SPI_1_MOSI_SCL_RX_HSIOM_MASK SPI_1_RX_SCL_MOSI_HSIOM_MASK + #define SPI_1_MOSI_SCL_RX_HSIOM_POS SPI_1_RX_SCL_MOSI_HSIOM_POS +#endif /* (SPI_1_MOSI_SCL_RX_PIN) */ + +#if (SPI_1_MISO_SDA_TX_PIN) + #define SPI_1_MISO_SDA_TX_HSIOM_REG SPI_1_TX_SDA_MISO_HSIOM_REG + #define SPI_1_MISO_SDA_TX_HSIOM_PTR SPI_1_TX_SDA_MISO_HSIOM_REG + #define SPI_1_MISO_SDA_TX_HSIOM_MASK SPI_1_TX_SDA_MISO_HSIOM_REG + #define SPI_1_MISO_SDA_TX_HSIOM_POS SPI_1_TX_SDA_MISO_HSIOM_REG +#endif /* (SPI_1_MISO_SDA_TX_PIN_PIN) */ + +#if (SPI_1_SCLK_PIN) + #ifndef SPI_1_SCLK_HSIOM_REG + #define SPI_1_SCLK_HSIOM_REG SPI_1_CTS_SCLK_HSIOM_REG + #define SPI_1_SCLK_HSIOM_PTR SPI_1_CTS_SCLK_HSIOM_PTR + #define SPI_1_SCLK_HSIOM_MASK SPI_1_CTS_SCLK_HSIOM_MASK + #define SPI_1_SCLK_HSIOM_POS SPI_1_CTS_SCLK_HSIOM_POS + #endif /* SPI_1_SCLK_HSIOM_REG */ +#endif /* (SPI_1_SCLK_PIN) */ + +#if (SPI_1_SS0_PIN) + #ifndef SPI_1_SS0_HSIOM_REG + #define SPI_1_SS0_HSIOM_REG SPI_1_RTS_SS0_HSIOM_REG + #define SPI_1_SS0_HSIOM_PTR SPI_1_RTS_SS0_HSIOM_PTR + #define SPI_1_SS0_HSIOM_MASK SPI_1_RTS_SS0_HSIOM_MASK + #define SPI_1_SS0_HSIOM_POS SPI_1_RTS_SS0_HSIOM_POS + #endif /* SPI_1_SS0_HSIOM_REG */ +#endif /* (SPI_1_SS0_PIN) */ + +#define SPI_1_MOSI_SCL_RX_WAKE_PIN_INDEX SPI_1_RX_WAKE_SCL_MOSI_PIN_INDEX +#define SPI_1_MOSI_SCL_RX_PIN_INDEX SPI_1_RX_SCL_MOSI_PIN_INDEX +#define SPI_1_MISO_SDA_TX_PIN_INDEX SPI_1_TX_SDA_MISO_PIN_INDEX +#ifndef SPI_1_SCLK_PIN_INDEX +#define SPI_1_SCLK_PIN_INDEX SPI_1_CTS_SCLK_PIN_INDEX +#endif /* SPI_1_SCLK_PIN_INDEX */ +#ifndef SPI_1_SS0_PIN_INDEX +#define SPI_1_SS0_PIN_INDEX SPI_1_RTS_SS0_PIN_INDEX +#endif /* SPI_1_SS0_PIN_INDEX */ + +#define SPI_1_MOSI_SCL_RX_WAKE_PIN_MASK SPI_1_RX_WAKE_SCL_MOSI_PIN_MASK +#define SPI_1_MOSI_SCL_RX_PIN_MASK SPI_1_RX_SCL_MOSI_PIN_MASK +#define SPI_1_MISO_SDA_TX_PIN_MASK SPI_1_TX_SDA_MISO_PIN_MASK +#ifndef SPI_1_SCLK_PIN_MASK +#define SPI_1_SCLK_PIN_MASK SPI_1_CTS_SCLK_PIN_MASK +#endif /* SPI_1_SCLK_PIN_MASK */ +#ifndef SPI_1_SS0_PIN_MASK +#define SPI_1_SS0_PIN_MASK SPI_1_RTS_SS0_PIN_MASK +#endif /* SPI_1_SS0_PIN_MASK */ + +#endif /* (CY_SCB_PINS_SPI_1_H) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_PM.c b/cores/asr650x/projects/PSoC4/SPI_1_PM.c new file mode 100644 index 00000000..c524b840 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_PM.c @@ -0,0 +1,223 @@ +/***************************************************************************//** +* \file SPI_1_PM.c +* \version 4.0 +* +* \brief +* This file provides the source code to the Power Management support for +* the SCB Component. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SPI_1.h" +#include "SPI_1_PVT.h" + +#if(SPI_1_SCB_MODE_I2C_INC) + #include "SPI_1_I2C_PVT.h" +#endif /* (SPI_1_SCB_MODE_I2C_INC) */ + +#if(SPI_1_SCB_MODE_EZI2C_INC) + #include "SPI_1_EZI2C_PVT.h" +#endif /* (SPI_1_SCB_MODE_EZI2C_INC) */ + +#if(SPI_1_SCB_MODE_SPI_INC || SPI_1_SCB_MODE_UART_INC) + #include "SPI_1_SPI_UART_PVT.h" +#endif /* (SPI_1_SCB_MODE_SPI_INC || SPI_1_SCB_MODE_UART_INC) */ + + +/*************************************** +* Backup Structure declaration +***************************************/ + +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG || \ + (SPI_1_SCB_MODE_I2C_CONST_CFG && (!SPI_1_I2C_WAKE_ENABLE_CONST)) || \ + (SPI_1_SCB_MODE_EZI2C_CONST_CFG && (!SPI_1_EZI2C_WAKE_ENABLE_CONST)) || \ + (SPI_1_SCB_MODE_SPI_CONST_CFG && (!SPI_1_SPI_WAKE_ENABLE_CONST)) || \ + (SPI_1_SCB_MODE_UART_CONST_CFG && (!SPI_1_UART_WAKE_ENABLE_CONST))) + + SPI_1_BACKUP_STRUCT SPI_1_backup = + { + 0u, /* enableState */ + }; +#endif + + +/******************************************************************************* +* Function Name: SPI_1_Sleep +****************************************************************************//** +* +* Prepares the SPI_1 component to enter Deep Sleep. +* The 鈥淓nable wakeup from Deep Sleep Mode鈥 selection has an influence on this +* function implementation: +* - Checked: configures the component to be wakeup source from Deep Sleep. +* - Unchecked: stores the current component state (enabled or disabled) and +* disables the component. See SCB_Stop() function for details about component +* disabling. +* +* Call the SPI_1_Sleep() function before calling the +* CyPmSysDeepSleep() function. +* Refer to the PSoC Creator System Reference Guide for more information about +* power management functions and Low power section of this document for the +* selected mode. +* +* This function should not be called before entering Sleep. +* +*******************************************************************************/ +void SPI_1_Sleep(void) +{ +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + + if(SPI_1_SCB_WAKE_ENABLE_CHECK) + { + if(SPI_1_SCB_MODE_I2C_RUNTM_CFG) + { + SPI_1_I2CSaveConfig(); + } + else if(SPI_1_SCB_MODE_EZI2C_RUNTM_CFG) + { + SPI_1_EzI2CSaveConfig(); + } + #if(!SPI_1_CY_SCBIP_V1) + else if(SPI_1_SCB_MODE_SPI_RUNTM_CFG) + { + SPI_1_SpiSaveConfig(); + } + else if(SPI_1_SCB_MODE_UART_RUNTM_CFG) + { + SPI_1_UartSaveConfig(); + } + #endif /* (!SPI_1_CY_SCBIP_V1) */ + else + { + /* Unknown mode */ + } + } + else + { + SPI_1_backup.enableState = (uint8) SPI_1_GET_CTRL_ENABLED; + + if(0u != SPI_1_backup.enableState) + { + SPI_1_Stop(); + } + } + +#else + + #if (SPI_1_SCB_MODE_I2C_CONST_CFG && SPI_1_I2C_WAKE_ENABLE_CONST) + SPI_1_I2CSaveConfig(); + + #elif (SPI_1_SCB_MODE_EZI2C_CONST_CFG && SPI_1_EZI2C_WAKE_ENABLE_CONST) + SPI_1_EzI2CSaveConfig(); + + #elif (SPI_1_SCB_MODE_SPI_CONST_CFG && SPI_1_SPI_WAKE_ENABLE_CONST) + SPI_1_SpiSaveConfig(); + + #elif (SPI_1_SCB_MODE_UART_CONST_CFG && SPI_1_UART_WAKE_ENABLE_CONST) + SPI_1_UartSaveConfig(); + + #else + + SPI_1_backup.enableState = (uint8) SPI_1_GET_CTRL_ENABLED; + + if(0u != SPI_1_backup.enableState) + { + SPI_1_Stop(); + } + + #endif /* defined (SPI_1_SCB_MODE_I2C_CONST_CFG) && (SPI_1_I2C_WAKE_ENABLE_CONST) */ + +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: SPI_1_Wakeup +****************************************************************************//** +* +* Prepares the SPI_1 component for Active mode operation after +* Deep Sleep. +* The 鈥淓nable wakeup from Deep Sleep Mode鈥 selection has influence on this +* function implementation: +* - Checked: restores the component Active mode configuration. +* - Unchecked: enables the component if it was enabled before enter Deep Sleep. +* +* This function should not be called after exiting Sleep. +* +* \sideeffect +* Calling the SPI_1_Wakeup() function without first calling the +* SPI_1_Sleep() function may produce unexpected behavior. +* +*******************************************************************************/ +void SPI_1_Wakeup(void) +{ +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + + if(SPI_1_SCB_WAKE_ENABLE_CHECK) + { + if(SPI_1_SCB_MODE_I2C_RUNTM_CFG) + { + SPI_1_I2CRestoreConfig(); + } + else if(SPI_1_SCB_MODE_EZI2C_RUNTM_CFG) + { + SPI_1_EzI2CRestoreConfig(); + } + #if(!SPI_1_CY_SCBIP_V1) + else if(SPI_1_SCB_MODE_SPI_RUNTM_CFG) + { + SPI_1_SpiRestoreConfig(); + } + else if(SPI_1_SCB_MODE_UART_RUNTM_CFG) + { + SPI_1_UartRestoreConfig(); + } + #endif /* (!SPI_1_CY_SCBIP_V1) */ + else + { + /* Unknown mode */ + } + } + else + { + if(0u != SPI_1_backup.enableState) + { + SPI_1_Enable(); + } + } + +#else + + #if (SPI_1_SCB_MODE_I2C_CONST_CFG && SPI_1_I2C_WAKE_ENABLE_CONST) + SPI_1_I2CRestoreConfig(); + + #elif (SPI_1_SCB_MODE_EZI2C_CONST_CFG && SPI_1_EZI2C_WAKE_ENABLE_CONST) + SPI_1_EzI2CRestoreConfig(); + + #elif (SPI_1_SCB_MODE_SPI_CONST_CFG && SPI_1_SPI_WAKE_ENABLE_CONST) + SPI_1_SpiRestoreConfig(); + + #elif (SPI_1_SCB_MODE_UART_CONST_CFG && SPI_1_UART_WAKE_ENABLE_CONST) + SPI_1_UartRestoreConfig(); + + #else + + if(0u != SPI_1_backup.enableState) + { + SPI_1_Enable(); + } + + #endif /* (SPI_1_I2C_WAKE_ENABLE_CONST) */ + +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_PVT.h b/cores/asr650x/projects/PSoC4/SPI_1_PVT.h new file mode 100644 index 00000000..5282498d --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_PVT.h @@ -0,0 +1,123 @@ +/***************************************************************************//** +* \file .h +* \version 4.0 +* +* \brief +* This private file provides constants and parameter values for the +* SCB Component. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_PVT_SPI_1_H) +#define CY_SCB_PVT_SPI_1_H + +#include "SPI_1.h" + + +/*************************************** +* Private Function Prototypes +***************************************/ + +/* APIs to service INTR_I2C_EC register */ +#define SPI_1_SetI2CExtClkInterruptMode(interruptMask) SPI_1_WRITE_INTR_I2C_EC_MASK(interruptMask) +#define SPI_1_ClearI2CExtClkInterruptSource(interruptMask) SPI_1_CLEAR_INTR_I2C_EC(interruptMask) +#define SPI_1_GetI2CExtClkInterruptSource() (SPI_1_INTR_I2C_EC_REG) +#define SPI_1_GetI2CExtClkInterruptMode() (SPI_1_INTR_I2C_EC_MASK_REG) +#define SPI_1_GetI2CExtClkInterruptSourceMasked() (SPI_1_INTR_I2C_EC_MASKED_REG) + +#if (!SPI_1_CY_SCBIP_V1) + /* APIs to service INTR_SPI_EC register */ + #define SPI_1_SetSpiExtClkInterruptMode(interruptMask) \ + SPI_1_WRITE_INTR_SPI_EC_MASK(interruptMask) + #define SPI_1_ClearSpiExtClkInterruptSource(interruptMask) \ + SPI_1_CLEAR_INTR_SPI_EC(interruptMask) + #define SPI_1_GetExtSpiClkInterruptSource() (SPI_1_INTR_SPI_EC_REG) + #define SPI_1_GetExtSpiClkInterruptMode() (SPI_1_INTR_SPI_EC_MASK_REG) + #define SPI_1_GetExtSpiClkInterruptSourceMasked() (SPI_1_INTR_SPI_EC_MASKED_REG) +#endif /* (!SPI_1_CY_SCBIP_V1) */ + +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + extern void SPI_1_SetPins(uint32 mode, uint32 subMode, uint32 uartEnableMask); +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +#if (SPI_1_SCB_IRQ_INTERNAL) +#if !defined (CY_REMOVE_SPI_1_CUSTOM_INTR_HANDLER) + extern cyisraddress SPI_1_customIntrHandler; +#endif /* !defined (CY_REMOVE_SPI_1_CUSTOM_INTR_HANDLER) */ +#endif /* (SPI_1_SCB_IRQ_INTERNAL) */ + +extern SPI_1_BACKUP_STRUCT SPI_1_backup; + +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + /* Common configuration variables */ + extern uint8 SPI_1_scbMode; + extern uint8 SPI_1_scbEnableWake; + extern uint8 SPI_1_scbEnableIntr; + + /* I2C configuration variables */ + extern uint8 SPI_1_mode; + extern uint8 SPI_1_acceptAddr; + + /* SPI/UART configuration variables */ + extern volatile uint8 * SPI_1_rxBuffer; + extern uint8 SPI_1_rxDataBits; + extern uint32 SPI_1_rxBufferSize; + + extern volatile uint8 * SPI_1_txBuffer; + extern uint8 SPI_1_txDataBits; + extern uint32 SPI_1_txBufferSize; + + /* EZI2C configuration variables */ + extern uint8 SPI_1_numberOfAddr; + extern uint8 SPI_1_subAddrSize; +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if (! (SPI_1_SCB_MODE_I2C_CONST_CFG || \ + SPI_1_SCB_MODE_EZI2C_CONST_CFG)) + extern uint16 SPI_1_IntrTxMask; +#endif /* (! (SPI_1_SCB_MODE_I2C_CONST_CFG || \ + SPI_1_SCB_MODE_EZI2C_CONST_CFG)) */ + + +/*************************************** +* Conditional Macro +****************************************/ + +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + /* Defines run time operation mode */ + #define SPI_1_SCB_MODE_I2C_RUNTM_CFG (SPI_1_SCB_MODE_I2C == SPI_1_scbMode) + #define SPI_1_SCB_MODE_SPI_RUNTM_CFG (SPI_1_SCB_MODE_SPI == SPI_1_scbMode) + #define SPI_1_SCB_MODE_UART_RUNTM_CFG (SPI_1_SCB_MODE_UART == SPI_1_scbMode) + #define SPI_1_SCB_MODE_EZI2C_RUNTM_CFG (SPI_1_SCB_MODE_EZI2C == SPI_1_scbMode) + #define SPI_1_SCB_MODE_UNCONFIG_RUNTM_CFG \ + (SPI_1_SCB_MODE_UNCONFIG == SPI_1_scbMode) + + /* Defines wakeup enable */ + #define SPI_1_SCB_WAKE_ENABLE_CHECK (0u != SPI_1_scbEnableWake) +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + +/* Defines maximum number of SCB pins */ +#if (!SPI_1_CY_SCBIP_V1) + #define SPI_1_SCB_PINS_NUMBER (7u) +#else + #define SPI_1_SCB_PINS_NUMBER (2u) +#endif /* (!SPI_1_CY_SCBIP_V1) */ + +#endif /* (CY_SCB_PVT_SPI_1_H) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_SCBCLK.c b/cores/asr650x/projects/PSoC4/SPI_1_SCBCLK.c new file mode 100644 index 00000000..27ae9cb5 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_SCBCLK.c @@ -0,0 +1,210 @@ +/******************************************************************************* +* File Name: SPI_1_SCBCLK.c +* Version 2.20 +* +* Description: +* Provides system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "SPI_1_SCBCLK.h" + +#if defined CYREG_PERI_DIV_CMD + +/******************************************************************************* +* Function Name: SPI_1_SCBCLK_StartEx +******************************************************************************** +* +* Summary: +* Starts the clock, aligned to the specified running clock. +* +* Parameters: +* alignClkDiv: The divider to which phase alignment is performed when the +* clock is started. +* +* Returns: +* None +* +*******************************************************************************/ +void SPI_1_SCBCLK_StartEx(uint32 alignClkDiv) +{ + /* Make sure any previous start command has finished. */ + while((SPI_1_SCBCLK_CMD_REG & SPI_1_SCBCLK_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and enable. */ + SPI_1_SCBCLK_CMD_REG = + ((uint32)SPI_1_SCBCLK__DIV_ID << SPI_1_SCBCLK_CMD_DIV_SHIFT)| + (alignClkDiv << SPI_1_SCBCLK_CMD_PA_DIV_SHIFT) | + (uint32)SPI_1_SCBCLK_CMD_ENABLE_MASK; +} + +#else + +/******************************************************************************* +* Function Name: SPI_1_SCBCLK_Start +******************************************************************************** +* +* Summary: +* Starts the clock. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ + +void SPI_1_SCBCLK_Start(void) +{ + /* Set the bit to enable the clock. */ + SPI_1_SCBCLK_ENABLE_REG |= SPI_1_SCBCLK__ENABLE_MASK; +} + +#endif /* CYREG_PERI_DIV_CMD */ + + +/******************************************************************************* +* Function Name: SPI_1_SCBCLK_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SPI_1_SCBCLK_Stop(void) +{ +#if defined CYREG_PERI_DIV_CMD + + /* Make sure any previous start command has finished. */ + while((SPI_1_SCBCLK_CMD_REG & SPI_1_SCBCLK_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and disable. */ + SPI_1_SCBCLK_CMD_REG = + ((uint32)SPI_1_SCBCLK__DIV_ID << SPI_1_SCBCLK_CMD_DIV_SHIFT)| + ((uint32)SPI_1_SCBCLK_CMD_DISABLE_MASK); + +#else + + /* Clear the bit to disable the clock. */ + SPI_1_SCBCLK_ENABLE_REG &= (uint32)(~SPI_1_SCBCLK__ENABLE_MASK); + +#endif /* CYREG_PERI_DIV_CMD */ +} + + +/******************************************************************************* +* Function Name: SPI_1_SCBCLK_SetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and the fractional divider. +* +* Parameters: +* clkDivider: Divider register value (0-65535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* fracDivider: Fractional Divider register value (0-31). +* Returns: +* None +* +*******************************************************************************/ +void SPI_1_SCBCLK_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional) +{ + uint32 maskVal; + uint32 regVal; + +#if defined (SPI_1_SCBCLK__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD) + + /* get all but divider bits */ + maskVal = SPI_1_SCBCLK_DIV_REG & + (uint32)(~(uint32)(SPI_1_SCBCLK_DIV_INT_MASK | SPI_1_SCBCLK_DIV_FRAC_MASK)); + /* combine mask and new divider vals into 32-bit value */ + regVal = maskVal | + ((uint32)((uint32)clkDivider << SPI_1_SCBCLK_DIV_INT_SHIFT) & SPI_1_SCBCLK_DIV_INT_MASK) | + ((uint32)((uint32)clkFractional << SPI_1_SCBCLK_DIV_FRAC_SHIFT) & SPI_1_SCBCLK_DIV_FRAC_MASK); + +#else + /* get all but integer divider bits */ + maskVal = SPI_1_SCBCLK_DIV_REG & (uint32)(~(uint32)SPI_1_SCBCLK__DIVIDER_MASK); + /* combine mask and new divider val into 32-bit value */ + regVal = clkDivider | maskVal; + +#endif /* SPI_1_SCBCLK__FRAC_MASK || CYREG_PERI_DIV_CMD */ + + SPI_1_SCBCLK_DIV_REG = regVal; +} + + +/******************************************************************************* +* Function Name: SPI_1_SCBCLK_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 SPI_1_SCBCLK_GetDividerRegister(void) +{ + return (uint16)((SPI_1_SCBCLK_DIV_REG & SPI_1_SCBCLK_DIV_INT_MASK) + >> SPI_1_SCBCLK_DIV_INT_SHIFT); +} + + +/******************************************************************************* +* Function Name: SPI_1_SCBCLK_GetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock fractional divider register value. +* +* Parameters: +* None +* +* Returns: +* Fractional Divide value of the clock +* 0 if the fractional divider is not in use. +* +*******************************************************************************/ +uint8 SPI_1_SCBCLK_GetFractionalDividerRegister(void) +{ +#if defined (SPI_1_SCBCLK__FRAC_MASK) + /* return fractional divider bits */ + return (uint8)((SPI_1_SCBCLK_DIV_REG & SPI_1_SCBCLK_DIV_FRAC_MASK) + >> SPI_1_SCBCLK_DIV_FRAC_SHIFT); +#else + return 0u; +#endif /* SPI_1_SCBCLK__FRAC_MASK */ +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_SCBCLK.h b/cores/asr650x/projects/PSoC4/SPI_1_SCBCLK.h new file mode 100644 index 00000000..6f1b8b76 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_SCBCLK.h @@ -0,0 +1,91 @@ +/******************************************************************************* +* File Name: SPI_1_SCBCLK.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_SPI_1_SCBCLK_H) +#define CY_CLOCK_SPI_1_SCBCLK_H + +#include +#include + + +/*************************************** +* Function Prototypes +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +void SPI_1_SCBCLK_StartEx(uint32 alignClkDiv); +#define SPI_1_SCBCLK_Start() \ + SPI_1_SCBCLK_StartEx(SPI_1_SCBCLK__PA_DIV_ID) + +#else + +void SPI_1_SCBCLK_Start(void); + +#endif/* CYREG_PERI_DIV_CMD */ + +void SPI_1_SCBCLK_Stop(void); + +void SPI_1_SCBCLK_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional); + +uint16 SPI_1_SCBCLK_GetDividerRegister(void); +uint8 SPI_1_SCBCLK_GetFractionalDividerRegister(void); + +#define SPI_1_SCBCLK_Enable() SPI_1_SCBCLK_Start() +#define SPI_1_SCBCLK_Disable() SPI_1_SCBCLK_Stop() +#define SPI_1_SCBCLK_SetDividerRegister(clkDivider, reset) \ + SPI_1_SCBCLK_SetFractionalDividerRegister((clkDivider), 0u) +#define SPI_1_SCBCLK_SetDivider(clkDivider) SPI_1_SCBCLK_SetDividerRegister((clkDivider), 1u) +#define SPI_1_SCBCLK_SetDividerValue(clkDivider) SPI_1_SCBCLK_SetDividerRegister((clkDivider) - 1u, 1u) + + +/*************************************** +* Registers +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +#define SPI_1_SCBCLK_DIV_ID SPI_1_SCBCLK__DIV_ID + +#define SPI_1_SCBCLK_CMD_REG (*(reg32 *)CYREG_PERI_DIV_CMD) +#define SPI_1_SCBCLK_CTRL_REG (*(reg32 *)SPI_1_SCBCLK__CTRL_REGISTER) +#define SPI_1_SCBCLK_DIV_REG (*(reg32 *)SPI_1_SCBCLK__DIV_REGISTER) + +#define SPI_1_SCBCLK_CMD_DIV_SHIFT (0u) +#define SPI_1_SCBCLK_CMD_PA_DIV_SHIFT (8u) +#define SPI_1_SCBCLK_CMD_DISABLE_SHIFT (30u) +#define SPI_1_SCBCLK_CMD_ENABLE_SHIFT (31u) + +#define SPI_1_SCBCLK_CMD_DISABLE_MASK ((uint32)((uint32)1u << SPI_1_SCBCLK_CMD_DISABLE_SHIFT)) +#define SPI_1_SCBCLK_CMD_ENABLE_MASK ((uint32)((uint32)1u << SPI_1_SCBCLK_CMD_ENABLE_SHIFT)) + +#define SPI_1_SCBCLK_DIV_FRAC_MASK (0x000000F8u) +#define SPI_1_SCBCLK_DIV_FRAC_SHIFT (3u) +#define SPI_1_SCBCLK_DIV_INT_MASK (0xFFFFFF00u) +#define SPI_1_SCBCLK_DIV_INT_SHIFT (8u) + +#else + +#define SPI_1_SCBCLK_DIV_REG (*(reg32 *)SPI_1_SCBCLK__REGISTER) +#define SPI_1_SCBCLK_ENABLE_REG SPI_1_SCBCLK_DIV_REG +#define SPI_1_SCBCLK_DIV_FRAC_MASK SPI_1_SCBCLK__FRAC_MASK +#define SPI_1_SCBCLK_DIV_FRAC_SHIFT (16u) +#define SPI_1_SCBCLK_DIV_INT_MASK SPI_1_SCBCLK__DIVIDER_MASK +#define SPI_1_SCBCLK_DIV_INT_SHIFT (0u) + +#endif/* CYREG_PERI_DIV_CMD */ + +#endif /* !defined(CY_CLOCK_SPI_1_SCBCLK_H) */ + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_SPI.c b/cores/asr650x/projects/PSoC4/SPI_1_SPI.c new file mode 100644 index 00000000..54f06e70 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_SPI.c @@ -0,0 +1,549 @@ +/***************************************************************************//** +* \file SPI_1_SPI.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component in +* SPI mode. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SPI_1_PVT.h" +#include "SPI_1_SPI_UART_PVT.h" + +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + + /*************************************** + * Configuration Structure Initialization + ***************************************/ + + const SPI_1_SPI_INIT_STRUCT SPI_1_configSpi = + { + SPI_1_SPI_MODE, + SPI_1_SPI_SUB_MODE, + SPI_1_SPI_CLOCK_MODE, + SPI_1_SPI_OVS_FACTOR, + SPI_1_SPI_MEDIAN_FILTER_ENABLE, + SPI_1_SPI_LATE_MISO_SAMPLE_ENABLE, + SPI_1_SPI_WAKE_ENABLE, + SPI_1_SPI_RX_DATA_BITS_NUM, + SPI_1_SPI_TX_DATA_BITS_NUM, + SPI_1_SPI_BITS_ORDER, + SPI_1_SPI_TRANSFER_SEPARATION, + 0u, + NULL, + 0u, + NULL, + (uint32) SPI_1_SCB_IRQ_INTERNAL, + SPI_1_SPI_INTR_RX_MASK, + SPI_1_SPI_RX_TRIGGER_LEVEL, + SPI_1_SPI_INTR_TX_MASK, + SPI_1_SPI_TX_TRIGGER_LEVEL, + (uint8) SPI_1_SPI_BYTE_MODE_ENABLE, + (uint8) SPI_1_SPI_FREE_RUN_SCLK_ENABLE, + (uint8) SPI_1_SPI_SS_POLARITY + }; + + + /******************************************************************************* + * Function Name: SPI_1_SpiInit + ****************************************************************************//** + * + * Configures the SPI_1 for SPI operation. + * + * This function is intended specifically to be used when the SPI_1 + * configuration is set to 鈥淯nconfigured SPI_1鈥 in the customizer. + * After initializing the SPI_1 in SPI mode using this function, + * the component can be enabled using the SPI_1_Start() or + * SPI_1_Enable() function. + * This function uses a pointer to a structure that provides the configuration + * settings. This structure contains the same information that would otherwise + * be provided by the customizer settings. + * + * \param config: pointer to a structure that contains the following list of + * fields. These fields match the selections available in the customizer. + * Refer to the customizer for further description of the settings. + * + *******************************************************************************/ + void SPI_1_SpiInit(const SPI_1_SPI_INIT_STRUCT *config) + { + if(NULL == config) + { + CYASSERT(0u != 0u); /* Halt execution due to bad function parameter */ + } + else + { + /* Configure pins */ + SPI_1_SetPins(SPI_1_SCB_MODE_SPI, config->mode, SPI_1_DUMMY_PARAM); + + /* Store internal configuration */ + SPI_1_scbMode = (uint8) SPI_1_SCB_MODE_SPI; + SPI_1_scbEnableWake = (uint8) config->enableWake; + SPI_1_scbEnableIntr = (uint8) config->enableInterrupt; + + /* Set RX direction internal variables */ + SPI_1_rxBuffer = config->rxBuffer; + SPI_1_rxDataBits = (uint8) config->rxDataBits; + SPI_1_rxBufferSize = config->rxBufferSize; + + /* Set TX direction internal variables */ + SPI_1_txBuffer = config->txBuffer; + SPI_1_txDataBits = (uint8) config->txDataBits; + SPI_1_txBufferSize = config->txBufferSize; + + /* Configure SPI interface */ + SPI_1_CTRL_REG = SPI_1_GET_CTRL_OVS(config->oversample) | + SPI_1_GET_CTRL_BYTE_MODE(config->enableByteMode) | + SPI_1_GET_CTRL_EC_AM_MODE(config->enableWake) | + SPI_1_CTRL_SPI; + + SPI_1_SPI_CTRL_REG = SPI_1_GET_SPI_CTRL_CONTINUOUS (config->transferSeperation) | + SPI_1_GET_SPI_CTRL_SELECT_PRECEDE(config->submode & + SPI_1_SPI_MODE_TI_PRECEDES_MASK) | + SPI_1_GET_SPI_CTRL_SCLK_MODE (config->sclkMode) | + SPI_1_GET_SPI_CTRL_LATE_MISO_SAMPLE(config->enableLateSampling)| + SPI_1_GET_SPI_CTRL_SCLK_CONTINUOUS(config->enableFreeRunSclk) | + SPI_1_GET_SPI_CTRL_SSEL_POLARITY (config->polaritySs) | + SPI_1_GET_SPI_CTRL_SUB_MODE (config->submode) | + SPI_1_GET_SPI_CTRL_MASTER_MODE (config->mode); + + /* Configure RX direction */ + SPI_1_RX_CTRL_REG = SPI_1_GET_RX_CTRL_DATA_WIDTH(config->rxDataBits) | + SPI_1_GET_RX_CTRL_BIT_ORDER (config->bitOrder) | + SPI_1_GET_RX_CTRL_MEDIAN (config->enableMedianFilter) | + SPI_1_SPI_RX_CTRL; + + SPI_1_RX_FIFO_CTRL_REG = SPI_1_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(config->rxTriggerLevel); + + /* Configure TX direction */ + SPI_1_TX_CTRL_REG = SPI_1_GET_TX_CTRL_DATA_WIDTH(config->txDataBits) | + SPI_1_GET_TX_CTRL_BIT_ORDER (config->bitOrder) | + SPI_1_SPI_TX_CTRL; + + SPI_1_TX_FIFO_CTRL_REG = SPI_1_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(config->txTriggerLevel); + + /* Configure interrupt with SPI handler but do not enable it */ + CyIntDisable (SPI_1_ISR_NUMBER); + CyIntSetPriority(SPI_1_ISR_NUMBER, SPI_1_ISR_PRIORITY); + (void) CyIntSetVector(SPI_1_ISR_NUMBER, &SPI_1_SPI_UART_ISR); + + /* Configure interrupt sources */ + SPI_1_INTR_I2C_EC_MASK_REG = SPI_1_NO_INTR_SOURCES; + SPI_1_INTR_SPI_EC_MASK_REG = SPI_1_NO_INTR_SOURCES; + SPI_1_INTR_SLAVE_MASK_REG = SPI_1_GET_SPI_INTR_SLAVE_MASK(config->rxInterruptMask); + SPI_1_INTR_MASTER_MASK_REG = SPI_1_GET_SPI_INTR_MASTER_MASK(config->txInterruptMask); + SPI_1_INTR_RX_MASK_REG = SPI_1_GET_SPI_INTR_RX_MASK(config->rxInterruptMask); + SPI_1_INTR_TX_MASK_REG = SPI_1_GET_SPI_INTR_TX_MASK(config->txInterruptMask); + + /* Configure TX interrupt sources to restore. */ + SPI_1_IntrTxMask = LO16(SPI_1_INTR_TX_MASK_REG); + + /* Set active SS0 */ + SPI_1_SpiSetActiveSlaveSelect(SPI_1_SPI_SLAVE_SELECT0); + + /* Clear RX buffer indexes */ + SPI_1_rxBufferHead = 0u; + SPI_1_rxBufferTail = 0u; + SPI_1_rxBufferOverflow = 0u; + + /* Clear TX buffer indexes */ + SPI_1_txBufferHead = 0u; + SPI_1_txBufferTail = 0u; + } + } + +#else + + /******************************************************************************* + * Function Name: SPI_1_SpiInit + ****************************************************************************//** + * + * Configures the SCB for the SPI operation. + * + *******************************************************************************/ + void SPI_1_SpiInit(void) + { + /* Configure SPI interface */ + SPI_1_CTRL_REG = SPI_1_SPI_DEFAULT_CTRL; + SPI_1_SPI_CTRL_REG = SPI_1_SPI_DEFAULT_SPI_CTRL; + + /* Configure TX and RX direction */ + SPI_1_RX_CTRL_REG = SPI_1_SPI_DEFAULT_RX_CTRL; + SPI_1_RX_FIFO_CTRL_REG = SPI_1_SPI_DEFAULT_RX_FIFO_CTRL; + + /* Configure TX and RX direction */ + SPI_1_TX_CTRL_REG = SPI_1_SPI_DEFAULT_TX_CTRL; + SPI_1_TX_FIFO_CTRL_REG = SPI_1_SPI_DEFAULT_TX_FIFO_CTRL; + + /* Configure interrupt with SPI handler but do not enable it */ + #if(SPI_1_SCB_IRQ_INTERNAL) + CyIntDisable (SPI_1_ISR_NUMBER); + CyIntSetPriority(SPI_1_ISR_NUMBER, SPI_1_ISR_PRIORITY); + (void) CyIntSetVector(SPI_1_ISR_NUMBER, &SPI_1_SPI_UART_ISR); + #endif /* (SPI_1_SCB_IRQ_INTERNAL) */ + + /* Configure interrupt sources */ + SPI_1_INTR_I2C_EC_MASK_REG = SPI_1_SPI_DEFAULT_INTR_I2C_EC_MASK; + SPI_1_INTR_SPI_EC_MASK_REG = SPI_1_SPI_DEFAULT_INTR_SPI_EC_MASK; + SPI_1_INTR_SLAVE_MASK_REG = SPI_1_SPI_DEFAULT_INTR_SLAVE_MASK; + SPI_1_INTR_MASTER_MASK_REG = SPI_1_SPI_DEFAULT_INTR_MASTER_MASK; + SPI_1_INTR_RX_MASK_REG = SPI_1_SPI_DEFAULT_INTR_RX_MASK; + SPI_1_INTR_TX_MASK_REG = SPI_1_SPI_DEFAULT_INTR_TX_MASK; + + /* Configure TX interrupt sources to restore. */ + SPI_1_IntrTxMask = LO16(SPI_1_INTR_TX_MASK_REG); + + /* Set active SS0 for master */ + #if (SPI_1_SPI_MASTER_CONST) + SPI_1_SpiSetActiveSlaveSelect(SPI_1_SPI_SLAVE_SELECT0); + #endif /* (SPI_1_SPI_MASTER_CONST) */ + + #if(SPI_1_INTERNAL_RX_SW_BUFFER_CONST) + SPI_1_rxBufferHead = 0u; + SPI_1_rxBufferTail = 0u; + SPI_1_rxBufferOverflow = 0u; + #endif /* (SPI_1_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if(SPI_1_INTERNAL_TX_SW_BUFFER_CONST) + SPI_1_txBufferHead = 0u; + SPI_1_txBufferTail = 0u; + #endif /* (SPI_1_INTERNAL_TX_SW_BUFFER_CONST) */ + } +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/******************************************************************************* +* Function Name: SPI_1_SpiPostEnable +****************************************************************************//** +* +* Restores HSIOM settings for the SPI master output pins (SCLK and/or SS0-SS3) +* to be controlled by the SCB SPI. +* +*******************************************************************************/ +void SPI_1_SpiPostEnable(void) +{ +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + + if (SPI_1_CHECK_SPI_MASTER) + { + #if (SPI_1_CTS_SCLK_PIN) + /* Set SCB SPI to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_CTS_SCLK_HSIOM_REG, SPI_1_CTS_SCLK_HSIOM_MASK, + SPI_1_CTS_SCLK_HSIOM_POS, SPI_1_CTS_SCLK_HSIOM_SEL_SPI); + #endif /* (SPI_1_CTS_SCLK_PIN) */ + + #if (SPI_1_RTS_SS0_PIN) + /* Set SCB SPI to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_RTS_SS0_HSIOM_REG, SPI_1_RTS_SS0_HSIOM_MASK, + SPI_1_RTS_SS0_HSIOM_POS, SPI_1_RTS_SS0_HSIOM_SEL_SPI); + #endif /* (SPI_1_RTS_SS0_PIN) */ + + #if (SPI_1_SS1_PIN) + /* Set SCB SPI to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS1_HSIOM_REG, SPI_1_SS1_HSIOM_MASK, + SPI_1_SS1_HSIOM_POS, SPI_1_SS1_HSIOM_SEL_SPI); + #endif /* (SPI_1_SS1_PIN) */ + + #if (SPI_1_SS2_PIN) + /* Set SCB SPI to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS2_HSIOM_REG, SPI_1_SS2_HSIOM_MASK, + SPI_1_SS2_HSIOM_POS, SPI_1_SS2_HSIOM_SEL_SPI); + #endif /* (SPI_1_SS2_PIN) */ + + #if (SPI_1_SS3_PIN) + /* Set SCB SPI to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS3_HSIOM_REG, SPI_1_SS3_HSIOM_MASK, + SPI_1_SS3_HSIOM_POS, SPI_1_SS3_HSIOM_SEL_SPI); + #endif /* (SPI_1_SS3_PIN) */ + } + +#else + + #if (SPI_1_SPI_MASTER_SCLK_PIN) + /* Set SCB SPI to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SCLK_M_HSIOM_REG, SPI_1_SCLK_M_HSIOM_MASK, + SPI_1_SCLK_M_HSIOM_POS, SPI_1_SCLK_M_HSIOM_SEL_SPI); + #endif /* (SPI_1_MISO_SDA_TX_PIN_PIN) */ + + #if (SPI_1_SPI_MASTER_SS0_PIN) + /* Set SCB SPI to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS0_M_HSIOM_REG, SPI_1_SS0_M_HSIOM_MASK, + SPI_1_SS0_M_HSIOM_POS, SPI_1_SS0_M_HSIOM_SEL_SPI); + #endif /* (SPI_1_SPI_MASTER_SS0_PIN) */ + + #if (SPI_1_SPI_MASTER_SS1_PIN) + /* Set SCB SPI to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS1_M_HSIOM_REG, SPI_1_SS1_M_HSIOM_MASK, + SPI_1_SS1_M_HSIOM_POS, SPI_1_SS1_M_HSIOM_SEL_SPI); + #endif /* (SPI_1_SPI_MASTER_SS1_PIN) */ + + #if (SPI_1_SPI_MASTER_SS2_PIN) + /* Set SCB SPI to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS2_M_HSIOM_REG, SPI_1_SS2_M_HSIOM_MASK, + SPI_1_SS2_M_HSIOM_POS, SPI_1_SS2_M_HSIOM_SEL_SPI); + #endif /* (SPI_1_SPI_MASTER_SS2_PIN) */ + + #if (SPI_1_SPI_MASTER_SS3_PIN) + /* Set SCB SPI to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS3_M_HSIOM_REG, SPI_1_SS3_M_HSIOM_MASK, + SPI_1_SS3_M_HSIOM_POS, SPI_1_SS3_M_HSIOM_SEL_SPI); + #endif /* (SPI_1_SPI_MASTER_SS3_PIN) */ + +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + /* Restore TX interrupt sources. */ + SPI_1_SetTxInterruptMode(SPI_1_IntrTxMask); +} + + +/******************************************************************************* +* Function Name: SPI_1_SpiStop +****************************************************************************//** +* +* Changes the HSIOM settings for the SPI master output pins +* (SCLK and/or SS0-SS3) to keep them inactive after the block is disabled. +* The output pins are controlled by the GPIO data register. +* +*******************************************************************************/ +void SPI_1_SpiStop(void) +{ +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + + if (SPI_1_CHECK_SPI_MASTER) + { + #if (SPI_1_CTS_SCLK_PIN) + /* Set output pin state after block is disabled */ + SPI_1_uart_cts_spi_sclk_Write(SPI_1_GET_SPI_SCLK_INACTIVE); + + /* Set GPIO to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_CTS_SCLK_HSIOM_REG, SPI_1_CTS_SCLK_HSIOM_MASK, + SPI_1_CTS_SCLK_HSIOM_POS, SPI_1_CTS_SCLK_HSIOM_SEL_GPIO); + #endif /* (SPI_1_uart_cts_spi_sclk_PIN) */ + + #if (SPI_1_RTS_SS0_PIN) + /* Set output pin state after block is disabled */ + SPI_1_uart_rts_spi_ss0_Write(SPI_1_GET_SPI_SS0_INACTIVE); + + /* Set GPIO to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_RTS_SS0_HSIOM_REG, SPI_1_RTS_SS0_HSIOM_MASK, + SPI_1_RTS_SS0_HSIOM_POS, SPI_1_RTS_SS0_HSIOM_SEL_GPIO); + #endif /* (SPI_1_uart_rts_spi_ss0_PIN) */ + + #if (SPI_1_SS1_PIN) + /* Set output pin state after block is disabled */ + SPI_1_spi_ss1_Write(SPI_1_GET_SPI_SS1_INACTIVE); + + /* Set GPIO to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS1_HSIOM_REG, SPI_1_SS1_HSIOM_MASK, + SPI_1_SS1_HSIOM_POS, SPI_1_SS1_HSIOM_SEL_GPIO); + #endif /* (SPI_1_SS1_PIN) */ + + #if (SPI_1_SS2_PIN) + /* Set output pin state after block is disabled */ + SPI_1_spi_ss2_Write(SPI_1_GET_SPI_SS2_INACTIVE); + + /* Set GPIO to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS2_HSIOM_REG, SPI_1_SS2_HSIOM_MASK, + SPI_1_SS2_HSIOM_POS, SPI_1_SS2_HSIOM_SEL_GPIO); + #endif /* (SPI_1_SS2_PIN) */ + + #if (SPI_1_SS3_PIN) + /* Set output pin state after block is disabled */ + SPI_1_spi_ss3_Write(SPI_1_GET_SPI_SS3_INACTIVE); + + /* Set GPIO to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS3_HSIOM_REG, SPI_1_SS3_HSIOM_MASK, + SPI_1_SS3_HSIOM_POS, SPI_1_SS3_HSIOM_SEL_GPIO); + #endif /* (SPI_1_SS3_PIN) */ + + /* Store TX interrupt sources (exclude level triggered) for master. */ + SPI_1_IntrTxMask = LO16(SPI_1_GetTxInterruptMode() & SPI_1_INTR_SPIM_TX_RESTORE); + } + else + { + /* Store TX interrupt sources (exclude level triggered) for slave. */ + SPI_1_IntrTxMask = LO16(SPI_1_GetTxInterruptMode() & SPI_1_INTR_SPIS_TX_RESTORE); + } + +#else + +#if (SPI_1_SPI_MASTER_SCLK_PIN) + /* Set output pin state after block is disabled */ + SPI_1_sclk_m_Write(SPI_1_GET_SPI_SCLK_INACTIVE); + + /* Set GPIO to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SCLK_M_HSIOM_REG, SPI_1_SCLK_M_HSIOM_MASK, + SPI_1_SCLK_M_HSIOM_POS, SPI_1_SCLK_M_HSIOM_SEL_GPIO); +#endif /* (SPI_1_MISO_SDA_TX_PIN_PIN) */ + +#if (SPI_1_SPI_MASTER_SS0_PIN) + /* Set output pin state after block is disabled */ + SPI_1_ss0_m_Write(SPI_1_GET_SPI_SS0_INACTIVE); + + /* Set GPIO to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS0_M_HSIOM_REG, SPI_1_SS0_M_HSIOM_MASK, + SPI_1_SS0_M_HSIOM_POS, SPI_1_SS0_M_HSIOM_SEL_GPIO); +#endif /* (SPI_1_SPI_MASTER_SS0_PIN) */ + +#if (SPI_1_SPI_MASTER_SS1_PIN) + /* Set output pin state after block is disabled */ + SPI_1_ss1_m_Write(SPI_1_GET_SPI_SS1_INACTIVE); + + /* Set GPIO to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS1_M_HSIOM_REG, SPI_1_SS1_M_HSIOM_MASK, + SPI_1_SS1_M_HSIOM_POS, SPI_1_SS1_M_HSIOM_SEL_GPIO); +#endif /* (SPI_1_SPI_MASTER_SS1_PIN) */ + +#if (SPI_1_SPI_MASTER_SS2_PIN) + /* Set output pin state after block is disabled */ + SPI_1_ss2_m_Write(SPI_1_GET_SPI_SS2_INACTIVE); + + /* Set GPIO to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS2_M_HSIOM_REG, SPI_1_SS2_M_HSIOM_MASK, + SPI_1_SS2_M_HSIOM_POS, SPI_1_SS2_M_HSIOM_SEL_GPIO); +#endif /* (SPI_1_SPI_MASTER_SS2_PIN) */ + +#if (SPI_1_SPI_MASTER_SS3_PIN) + /* Set output pin state after block is disabled */ + SPI_1_ss3_m_Write(SPI_1_GET_SPI_SS3_INACTIVE); + + /* Set GPIO to drive output pin */ + SPI_1_SET_HSIOM_SEL(SPI_1_SS3_M_HSIOM_REG, SPI_1_SS3_M_HSIOM_MASK, + SPI_1_SS3_M_HSIOM_POS, SPI_1_SS3_M_HSIOM_SEL_GPIO); +#endif /* (SPI_1_SPI_MASTER_SS3_PIN) */ + + #if (SPI_1_SPI_MASTER_CONST) + /* Store TX interrupt sources (exclude level triggered). */ + SPI_1_IntrTxMask = LO16(SPI_1_GetTxInterruptMode() & SPI_1_INTR_SPIM_TX_RESTORE); + #else + /* Store TX interrupt sources (exclude level triggered). */ + SPI_1_IntrTxMask = LO16(SPI_1_GetTxInterruptMode() & SPI_1_INTR_SPIS_TX_RESTORE); + #endif /* (SPI_1_SPI_MASTER_CONST) */ + +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +#if (SPI_1_SPI_MASTER_CONST) + /******************************************************************************* + * Function Name: SPI_1_SetActiveSlaveSelect + ****************************************************************************//** + * + * Selects one of the four slave select lines to be active during the transfer. + * After initialization the active slave select line is 0. + * The component should be in one of the following states to change the active + * slave select signal source correctly: + * - The component is disabled. + * - The component has completed transfer (TX FIFO is empty and the + * SCB_INTR_MASTER_SPI_DONE status is set). + * + * This function does not check that these conditions are met. + * This function is only applicable to SPI Master mode of operation. + * + * \param slaveSelect: slave select line which will be active while the following + * transfer. + * - SPI_1_SPI_SLAVE_SELECT0 - Slave select 0. + * - SPI_1_SPI_SLAVE_SELECT1 - Slave select 1. + * - SPI_1_SPI_SLAVE_SELECT2 - Slave select 2. + * - SPI_1_SPI_SLAVE_SELECT3 - Slave select 3. + * + *******************************************************************************/ + void SPI_1_SpiSetActiveSlaveSelect(uint32 slaveSelect) + { + uint32 spiCtrl; + + spiCtrl = SPI_1_SPI_CTRL_REG; + + spiCtrl &= (uint32) ~SPI_1_SPI_CTRL_SLAVE_SELECT_MASK; + spiCtrl |= (uint32) SPI_1_GET_SPI_CTRL_SS(slaveSelect); + + SPI_1_SPI_CTRL_REG = spiCtrl; + } +#endif /* (SPI_1_SPI_MASTER_CONST) */ + + +#if !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + /******************************************************************************* + * Function Name: SPI_1_SpiSetSlaveSelectPolarity + ****************************************************************************//** + * + * Sets active polarity for slave select line. + * The component should be in one of the following states to change the active + * slave select signal source correctly: + * - The component is disabled. + * - The component has completed transfer. + * + * This function does not check that these conditions are met. + * + * \param slaveSelect: slave select line to change active polarity. + * - SPI_1_SPI_SLAVE_SELECT0 - Slave select 0. + * - SPI_1_SPI_SLAVE_SELECT1 - Slave select 1. + * - SPI_1_SPI_SLAVE_SELECT2 - Slave select 2. + * - SPI_1_SPI_SLAVE_SELECT3 - Slave select 3. + * + * \param polarity: active polarity of slave select line. + * - SPI_1_SPI_SS_ACTIVE_LOW - Slave select is active low. + * - SPI_1_SPI_SS_ACTIVE_HIGH - Slave select is active high. + * + *******************************************************************************/ + void SPI_1_SpiSetSlaveSelectPolarity(uint32 slaveSelect, uint32 polarity) + { + uint32 ssPolarity; + + /* Get position of the polarity bit associated with slave select line */ + ssPolarity = SPI_1_GET_SPI_CTRL_SSEL_POLARITY((uint32) 1u << slaveSelect); + + if (0u != polarity) + { + SPI_1_SPI_CTRL_REG |= (uint32) ssPolarity; + } + else + { + SPI_1_SPI_CTRL_REG &= (uint32) ~ssPolarity; + } + } +#endif /* !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ + + +#if(SPI_1_SPI_WAKE_ENABLE_CONST) + /******************************************************************************* + * Function Name: SPI_1_SpiSaveConfig + ****************************************************************************//** + * + * Clears INTR_SPI_EC.WAKE_UP and enables it. This interrupt + * source triggers when the master assigns the SS line and wakes up the device. + * + *******************************************************************************/ + void SPI_1_SpiSaveConfig(void) + { + /* Clear and enable SPI wakeup interrupt source */ + SPI_1_ClearSpiExtClkInterruptSource(SPI_1_INTR_SPI_EC_WAKE_UP); + SPI_1_SetSpiExtClkInterruptMode(SPI_1_INTR_SPI_EC_WAKE_UP); + } + + + /******************************************************************************* + * Function Name: SPI_1_SpiRestoreConfig + ****************************************************************************//** + * + * Disables the INTR_SPI_EC.WAKE_UP interrupt source. After wakeup + * slave does not drive the MISO line and the master receives 0xFF. + * + *******************************************************************************/ + void SPI_1_SpiRestoreConfig(void) + { + /* Disable SPI wakeup interrupt source */ + SPI_1_SetSpiExtClkInterruptMode(SPI_1_NO_INTR_SOURCES); + } +#endif /* (SPI_1_SPI_WAKE_ENABLE_CONST) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_SPI_BOOT.c b/cores/asr650x/projects/PSoC4/SPI_1_SPI_BOOT.c new file mode 100644 index 00000000..c94da22a --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_SPI_BOOT.c @@ -0,0 +1,209 @@ +/***************************************************************************//** +* \file SPI_1_SPI_BOOT.c +* \version 4.0 +* +* \brief +* This file provides the source code of the bootloader communication APIs +* for the SCB Component SPI mode. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SPI_1_BOOT.h" +#include "SPI_1_SPI_UART.h" + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && (SPI_1_SPI_BTLDR_COMM_ENABLED) + +/******************************************************************************* +* Function Name: SPI_1_SpiCyBtldrCommStart +****************************************************************************//** +* +* Starts the SPI component. +* +*******************************************************************************/ +void SPI_1_SpiCyBtldrCommStart(void) +{ + SPI_1_Start(); +} + + +/******************************************************************************* +* Function Name: SPI_1_SpiCyBtldrCommStop +****************************************************************************//** +* +* Disables the SPI component. +* +*******************************************************************************/ +void SPI_1_SpiCyBtldrCommStop(void) +{ + SPI_1_Stop(); +} + + +/******************************************************************************* +* Function Name: SPI_1_SpiCyBtldrCommReset +****************************************************************************//** +* +* Resets the receive and transmit communication buffers. +* +*******************************************************************************/ +void SPI_1_SpiCyBtldrCommReset(void) +{ + /* Clear RX and TX buffers */ + SPI_1_SpiUartClearRxBuffer(); + SPI_1_SpiUartClearTxBuffer(); +} + + +/******************************************************************************* +* Function Name: SPI_1_SpiCyBtldrCommRead +****************************************************************************//** +* +* Allows the caller to read data from the bootloader host (the host writes the +* data). The function handles polling to allow a block of data to be completely +* received from the host device. +* +* \param pData: Pointer to storage for the block of data to be read from the +* bootloader host +* \param size: Number of bytes to be read. +* \param count: Pointer to the variable to write the number of bytes actually +* read. +* \param timeOut: Number of units in 10 ms to wait before returning +* because of a timeout. +* +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value +* that best describes the problem. For more information refer to the +* "Return Codes" section of the System Reference Guide. +* +*******************************************************************************/ +cystatus SPI_1_SpiCyBtldrCommRead(uint8 pData[], uint16 size, uint16 * count, uint8 timeOut) +{ + cystatus status; + uint32 byteCount; + uint32 timeoutMs; + uint32 i; + + status = CYRET_BAD_PARAM; + + if ((NULL != pData) && (size > 0u)) + { + status = CYRET_TIMEOUT; + timeoutMs = ((uint32) 10u * timeOut); /* Convert from 10mS check to 1mS checks */ + + /* Wait with timeout 1mS for packet start */ + byteCount = 0u; + do + { + /* Check packet start */ + if (0u != SPI_1_SpiUartGetRxBufferSize()) + { + /* Wait for packet end */ + do + { + byteCount = SPI_1_SpiUartGetRxBufferSize(); + CyDelayUs(SPI_1_SPI_BYTE_TO_BYTE); + } + while (byteCount != SPI_1_SpiUartGetRxBufferSize()); + + /* Disable data reception into RX FIFO */ + SPI_1_RX_FIFO_CTRL_REG |= SPI_1_RX_FIFO_CTRL_FREEZE; + + byteCount = SPI_1_BYTES_TO_COPY(byteCount, size); + *count = (uint16) byteCount; + status = CYRET_SUCCESS; + + break; + } + + CyDelay(SPI_1_WAIT_1_MS); + --timeoutMs; + } + while (0u != timeoutMs); + + /* Get data from the RX buffer into bootloader buffer */ + for (i = 0u; i < byteCount; ++i) + { + pData[i] = (uint8) SPI_1_SpiUartReadRxData(); + } + } + + return (status); +} + + +/******************************************************************************* +* Function Name: SPI_1_SpiCyBtldrCommWrite +****************************************************************************//** +* +* Allows the caller to read data from the bootloader host (the host writes the +* data). The function handles polling to allow a block of data to be completely +* received from the host device. +* +* \param pData: Pointer to the block of data to be written to the bootloader +* host. +* \param size: Number of bytes to be written. +* \param count: Pointer to the variable to write the number of bytes actually +* written. +* \param timeOut: Number of units in 10 ms to wait before returning +* because of a timeout. +* +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value +* that best describes the problem. For more information refer to the +* "Return Codes" section of the System Reference Guide. +* +*******************************************************************************/ +cystatus SPI_1_SpiCyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 * count, uint8 timeOut) +{ + cystatus status; + uint32 timeoutMs; + + status = CYRET_BAD_PARAM; + + if ((NULL != pData) && (size > 0u)) + { + status = CYRET_TIMEOUT; + timeoutMs = ((uint32) 10u * timeOut); /* Convert from 10mS check to 1mS checks */ + + /* Put data into TX buffer */ + SPI_1_SpiUartPutArray(pData, (uint32) size); + + /* Wait with timeout 1mS for packet end */ + do + { + /* Check for packet end */ + if ((0u == SPI_1_SpiUartGetTxBufferSize()) && + (0u == (SPI_1_SPI_STATUS_REG & SPI_1_SPI_STATUS_BUS_BUSY)) && + (0u == (SPI_1_TX_FIFO_STATUS_REG & SPI_1_TX_FIFO_SR_VALID))) + { + *count = size; + status = CYRET_SUCCESS; + + break; + } + + CyDelay(SPI_1_WAIT_1_MS); + --timeoutMs; + } + while (0u != timeoutMs); + + /* Enable data reception into RX FIFO */ + SPI_1_SpiUartClearRxBuffer(); + SPI_1_RX_FIFO_CTRL_REG &= (uint32) ~SPI_1_RX_FIFO_CTRL_FREEZE; + } + + return (status); +} + +#endif /* defined(CYDEV_BOOTLOADER_IO_COMP) && (SPI_1_SPI_BTLDR_COMM_ENABLED) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_SPI_UART.c b/cores/asr650x/projects/PSoC4/SPI_1_SPI_UART.c new file mode 100644 index 00000000..2b4b02eb --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_SPI_UART.c @@ -0,0 +1,603 @@ +/***************************************************************************//** +* \file SPI_1_SPI_UART.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component in +* SPI and UART modes. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SPI_1_PVT.h" +#include "SPI_1_SPI_UART_PVT.h" + +/*************************************** +* SPI/UART Private Vars +***************************************/ + +#if(SPI_1_INTERNAL_RX_SW_BUFFER_CONST) + /* Start index to put data into the software receive buffer.*/ + volatile uint32 SPI_1_rxBufferHead; + /* Start index to get data from the software receive buffer.*/ + volatile uint32 SPI_1_rxBufferTail; + /** + * \addtogroup group_globals + * \{ + */ + /** Sets when internal software receive buffer overflow + * was occurred. + */ + volatile uint8 SPI_1_rxBufferOverflow; + /** \} globals */ +#endif /* (SPI_1_INTERNAL_RX_SW_BUFFER_CONST) */ + +#if(SPI_1_INTERNAL_TX_SW_BUFFER_CONST) + /* Start index to put data into the software transmit buffer.*/ + volatile uint32 SPI_1_txBufferHead; + /* Start index to get data from the software transmit buffer.*/ + volatile uint32 SPI_1_txBufferTail; +#endif /* (SPI_1_INTERNAL_TX_SW_BUFFER_CONST) */ + +#if(SPI_1_INTERNAL_RX_SW_BUFFER) + /* Add one element to the buffer to receive full packet. One byte in receive buffer is always empty */ + volatile uint8 SPI_1_rxBufferInternal[SPI_1_INTERNAL_RX_BUFFER_SIZE]; +#endif /* (SPI_1_INTERNAL_RX_SW_BUFFER) */ + +#if(SPI_1_INTERNAL_TX_SW_BUFFER) + volatile uint8 SPI_1_txBufferInternal[SPI_1_TX_BUFFER_SIZE]; +#endif /* (SPI_1_INTERNAL_TX_SW_BUFFER) */ + + +#if(SPI_1_RX_DIRECTION) + /******************************************************************************* + * Function Name: SPI_1_SpiUartReadRxData + ****************************************************************************//** + * + * Retrieves the next data element from the receive buffer. + * - RX software buffer is disabled: Returns data element retrieved from + * RX FIFO. Undefined data will be returned if the RX FIFO is empty. + * - RX software buffer is enabled: Returns data element from the software + * receive buffer. Zero value is returned if the software receive buffer + * is empty. + * + * \return + * Next data element from the receive buffer. + * The amount of data bits to be received depends on RX data bits selection + * (the data bit counting starts from LSB of return value). + * + * \globalvars + * SPI_1_rxBufferHead - the start index to put data into the + * software receive buffer. + * SPI_1_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + uint32 SPI_1_SpiUartReadRxData(void) + { + uint32 rxData = 0u; + + #if (SPI_1_INTERNAL_RX_SW_BUFFER_CONST) + uint32 locTail; + #endif /* (SPI_1_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if (SPI_1_CHECK_RX_SW_BUFFER) + { + if (SPI_1_rxBufferHead != SPI_1_rxBufferTail) + { + /* There is data in RX software buffer */ + + /* Calculate index to read from */ + locTail = (SPI_1_rxBufferTail + 1u); + + if (SPI_1_INTERNAL_RX_BUFFER_SIZE == locTail) + { + locTail = 0u; + } + + /* Get data from RX software buffer */ + rxData = SPI_1_GetWordFromRxBuffer(locTail); + + /* Change index in the buffer */ + SPI_1_rxBufferTail = locTail; + + #if (SPI_1_CHECK_UART_RTS_CONTROL_FLOW) + { + /* Check if RX Not Empty is disabled in the interrupt */ + if (0u == (SPI_1_INTR_RX_MASK_REG & SPI_1_INTR_RX_NOT_EMPTY)) + { + /* Enable RX Not Empty interrupt source to continue + * receiving data into software buffer. + */ + SPI_1_INTR_RX_MASK_REG |= SPI_1_INTR_RX_NOT_EMPTY; + } + } + #endif + + } + } + #else + { + /* Read data from RX FIFO */ + rxData = SPI_1_RX_FIFO_RD_REG; + } + #endif + + return (rxData); + } + + + /******************************************************************************* + * Function Name: SPI_1_SpiUartGetRxBufferSize + ****************************************************************************//** + * + * Returns the number of received data elements in the receive buffer. + * - RX software buffer disabled: returns the number of used entries in + * RX FIFO. + * - RX software buffer enabled: returns the number of elements which were + * placed in the receive buffer. This does not include the hardware RX FIFO. + * + * \return + * Number of received data elements. + * + * \globalvars + * SPI_1_rxBufferHead - the start index to put data into the + * software receive buffer. + * SPI_1_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + uint32 SPI_1_SpiUartGetRxBufferSize(void) + { + uint32 size; + #if (SPI_1_INTERNAL_RX_SW_BUFFER_CONST) + uint32 locHead; + #endif /* (SPI_1_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if (SPI_1_CHECK_RX_SW_BUFFER) + { + locHead = SPI_1_rxBufferHead; + + if(locHead >= SPI_1_rxBufferTail) + { + size = (locHead - SPI_1_rxBufferTail); + } + else + { + size = (locHead + (SPI_1_INTERNAL_RX_BUFFER_SIZE - SPI_1_rxBufferTail)); + } + } + #else + { + size = SPI_1_GET_RX_FIFO_ENTRIES; + } + #endif + + return (size); + } + + + /******************************************************************************* + * Function Name: SPI_1_SpiUartClearRxBuffer + ****************************************************************************//** + * + * Clears the receive buffer and RX FIFO. + * + * \globalvars + * SPI_1_rxBufferHead - the start index to put data into the + * software receive buffer. + * SPI_1_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + void SPI_1_SpiUartClearRxBuffer(void) + { + #if (SPI_1_CHECK_RX_SW_BUFFER) + { + /* Lock from component interruption */ + SPI_1_DisableInt(); + + /* Flush RX software buffer */ + SPI_1_rxBufferHead = SPI_1_rxBufferTail; + SPI_1_rxBufferOverflow = 0u; + + SPI_1_CLEAR_RX_FIFO; + SPI_1_ClearRxInterruptSource(SPI_1_INTR_RX_ALL); + + #if (SPI_1_CHECK_UART_RTS_CONTROL_FLOW) + { + /* Enable RX Not Empty interrupt source to continue receiving + * data into software buffer. + */ + SPI_1_INTR_RX_MASK_REG |= SPI_1_INTR_RX_NOT_EMPTY; + } + #endif + + /* Release lock */ + SPI_1_EnableInt(); + } + #else + { + SPI_1_CLEAR_RX_FIFO; + } + #endif + } + +#endif /* (SPI_1_RX_DIRECTION) */ + + +#if(SPI_1_TX_DIRECTION) + /******************************************************************************* + * Function Name: SPI_1_SpiUartWriteTxData + ****************************************************************************//** + * + * Places a data entry into the transmit buffer to be sent at the next available + * bus time. + * This function is blocking and waits until there is space available to put the + * requested data in the transmit buffer. + * + * \param txDataByte: the data to be transmitted. + * The amount of data bits to be transmitted depends on TX data bits selection + * (the data bit counting starts from LSB of txDataByte). + * + * \globalvars + * SPI_1_txBufferHead - the start index to put data into the + * software transmit buffer. + * SPI_1_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void SPI_1_SpiUartWriteTxData(uint32 txData) + { + #if (SPI_1_INTERNAL_TX_SW_BUFFER_CONST) + uint32 locHead; + #endif /* (SPI_1_INTERNAL_TX_SW_BUFFER_CONST) */ + + #if (SPI_1_CHECK_TX_SW_BUFFER) + { + /* Put data directly into the TX FIFO */ + if ((SPI_1_txBufferHead == SPI_1_txBufferTail) && + (SPI_1_SPI_UART_FIFO_SIZE != SPI_1_GET_TX_FIFO_ENTRIES)) + { + /* TX software buffer is empty: put data directly in TX FIFO */ + SPI_1_TX_FIFO_WR_REG = txData; + } + /* Put data into TX software buffer */ + else + { + /* Head index to put data */ + locHead = (SPI_1_txBufferHead + 1u); + + /* Adjust TX software buffer index */ + if (SPI_1_TX_BUFFER_SIZE == locHead) + { + locHead = 0u; + } + + /* Wait for space in TX software buffer */ + while (locHead == SPI_1_txBufferTail) + { + } + + /* TX software buffer has at least one room */ + + /* Clear old status of INTR_TX_NOT_FULL. It sets at the end of transfer when TX FIFO is empty. */ + SPI_1_ClearTxInterruptSource(SPI_1_INTR_TX_NOT_FULL); + + SPI_1_PutWordInTxBuffer(locHead, txData); + + SPI_1_txBufferHead = locHead; + + /* Check if TX Not Full is disabled in interrupt */ + if (0u == (SPI_1_INTR_TX_MASK_REG & SPI_1_INTR_TX_NOT_FULL)) + { + /* Enable TX Not Full interrupt source to transmit from software buffer */ + SPI_1_INTR_TX_MASK_REG |= (uint32) SPI_1_INTR_TX_NOT_FULL; + } + } + } + #else + { + /* Wait until TX FIFO has space to put data element */ + while (SPI_1_SPI_UART_FIFO_SIZE == SPI_1_GET_TX_FIFO_ENTRIES) + { + } + + SPI_1_TX_FIFO_WR_REG = txData; + } + #endif + } + + + /******************************************************************************* + * Function Name: SPI_1_SpiUartPutArray + ****************************************************************************//** + * + * Places an array of data into the transmit buffer to be sent. + * This function is blocking and waits until there is a space available to put + * all the requested data in the transmit buffer. The array size can be greater + * than transmit buffer size. + * + * \param wrBuf: pointer to an array of data to be placed in transmit buffer. + * The width of the data to be transmitted depends on TX data width selection + * (the data bit counting starts from LSB for each array element). + * \param count: number of data elements to be placed in the transmit buffer. + * + * \globalvars + * SPI_1_txBufferHead - the start index to put data into the + * software transmit buffer. + * SPI_1_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void SPI_1_SpiUartPutArray(const uint8 wrBuf[], uint32 count) + { + uint32 i; + + for (i=0u; i < count; i++) + { + SPI_1_SpiUartWriteTxData((uint32) wrBuf[i]); + } + } + + + /******************************************************************************* + * Function Name: SPI_1_SpiUartGetTxBufferSize + ****************************************************************************//** + * + * Returns the number of elements currently in the transmit buffer. + * - TX software buffer is disabled: returns the number of used entries in + * TX FIFO. + * - TX software buffer is enabled: returns the number of elements currently + * used in the transmit buffer. This number does not include used entries in + * the TX FIFO. The transmit buffer size is zero until the TX FIFO is + * not full. + * + * \return + * Number of data elements ready to transmit. + * + * \globalvars + * SPI_1_txBufferHead - the start index to put data into the + * software transmit buffer. + * SPI_1_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + uint32 SPI_1_SpiUartGetTxBufferSize(void) + { + uint32 size; + #if (SPI_1_INTERNAL_TX_SW_BUFFER_CONST) + uint32 locTail; + #endif /* (SPI_1_INTERNAL_TX_SW_BUFFER_CONST) */ + + #if (SPI_1_CHECK_TX_SW_BUFFER) + { + /* Get current Tail index */ + locTail = SPI_1_txBufferTail; + + if (SPI_1_txBufferHead >= locTail) + { + size = (SPI_1_txBufferHead - locTail); + } + else + { + size = (SPI_1_txBufferHead + (SPI_1_TX_BUFFER_SIZE - locTail)); + } + } + #else + { + size = SPI_1_GET_TX_FIFO_ENTRIES; + } + #endif + + return (size); + } + + + /******************************************************************************* + * Function Name: SPI_1_SpiUartClearTxBuffer + ****************************************************************************//** + * + * Clears the transmit buffer and TX FIFO. + * + * \globalvars + * SPI_1_txBufferHead - the start index to put data into the + * software transmit buffer. + * SPI_1_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void SPI_1_SpiUartClearTxBuffer(void) + { + #if (SPI_1_CHECK_TX_SW_BUFFER) + { + /* Lock from component interruption */ + SPI_1_DisableInt(); + + /* Flush TX software buffer */ + SPI_1_txBufferHead = SPI_1_txBufferTail; + + SPI_1_INTR_TX_MASK_REG &= (uint32) ~SPI_1_INTR_TX_NOT_FULL; + SPI_1_CLEAR_TX_FIFO; + SPI_1_ClearTxInterruptSource(SPI_1_INTR_TX_ALL); + + /* Release lock */ + SPI_1_EnableInt(); + } + #else + { + SPI_1_CLEAR_TX_FIFO; + } + #endif + } + +#endif /* (SPI_1_TX_DIRECTION) */ + + +/******************************************************************************* +* Function Name: SPI_1_SpiUartDisableIntRx +****************************************************************************//** +* +* Disables the RX interrupt sources. +* +* \return +* Returns the RX interrupt sources enabled before the function call. +* +*******************************************************************************/ +uint32 SPI_1_SpiUartDisableIntRx(void) +{ + uint32 intSource; + + intSource = SPI_1_GetRxInterruptMode(); + + SPI_1_SetRxInterruptMode(SPI_1_NO_INTR_SOURCES); + + return (intSource); +} + + +/******************************************************************************* +* Function Name: SPI_1_SpiUartDisableIntTx +****************************************************************************//** +* +* Disables TX interrupt sources. +* +* \return +* Returns TX interrupt sources enabled before function call. +* +*******************************************************************************/ +uint32 SPI_1_SpiUartDisableIntTx(void) +{ + uint32 intSourceMask; + + intSourceMask = SPI_1_GetTxInterruptMode(); + + SPI_1_SetTxInterruptMode(SPI_1_NO_INTR_SOURCES); + + return (intSourceMask); +} + + +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + /******************************************************************************* + * Function Name: SPI_1_PutWordInRxBuffer + ****************************************************************************//** + * + * Stores a byte/word into the RX buffer. + * Only available in the Unconfigured operation mode. + * + * \param index: index to store data byte/word in the RX buffer. + * \param rxDataByte: byte/word to store. + * + *******************************************************************************/ + void SPI_1_PutWordInRxBuffer(uint32 idx, uint32 rxDataByte) + { + /* Put data in buffer */ + if (SPI_1_ONE_BYTE_WIDTH == SPI_1_rxDataBits) + { + SPI_1_rxBuffer[idx] = ((uint8) rxDataByte); + } + else + { + SPI_1_rxBuffer[(uint32)(idx << 1u)] = LO8(LO16(rxDataByte)); + SPI_1_rxBuffer[(uint32)(idx << 1u) + 1u] = HI8(LO16(rxDataByte)); + } + } + + + /******************************************************************************* + * Function Name: SPI_1_GetWordFromRxBuffer + ****************************************************************************//** + * + * Reads byte/word from RX buffer. + * Only available in the Unconfigured operation mode. + * + * \return + * Returns byte/word read from RX buffer. + * + *******************************************************************************/ + uint32 SPI_1_GetWordFromRxBuffer(uint32 idx) + { + uint32 value; + + if (SPI_1_ONE_BYTE_WIDTH == SPI_1_rxDataBits) + { + value = SPI_1_rxBuffer[idx]; + } + else + { + value = (uint32) SPI_1_rxBuffer[(uint32)(idx << 1u)]; + value |= (uint32) ((uint32)SPI_1_rxBuffer[(uint32)(idx << 1u) + 1u] << 8u); + } + + return (value); + } + + + /******************************************************************************* + * Function Name: SPI_1_PutWordInTxBuffer + ****************************************************************************//** + * + * Stores byte/word into the TX buffer. + * Only available in the Unconfigured operation mode. + * + * \param idx: index to store data byte/word in the TX buffer. + * \param txDataByte: byte/word to store. + * + *******************************************************************************/ + void SPI_1_PutWordInTxBuffer(uint32 idx, uint32 txDataByte) + { + /* Put data in buffer */ + if (SPI_1_ONE_BYTE_WIDTH == SPI_1_txDataBits) + { + SPI_1_txBuffer[idx] = ((uint8) txDataByte); + } + else + { + SPI_1_txBuffer[(uint32)(idx << 1u)] = LO8(LO16(txDataByte)); + SPI_1_txBuffer[(uint32)(idx << 1u) + 1u] = HI8(LO16(txDataByte)); + } + } + + + /******************************************************************************* + * Function Name: SPI_1_GetWordFromTxBuffer + ****************************************************************************//** + * + * Reads byte/word from the TX buffer. + * Only available in the Unconfigured operation mode. + * + * \param idx: index to get data byte/word from the TX buffer. + * + * \return + * Returns byte/word read from the TX buffer. + * + *******************************************************************************/ + uint32 SPI_1_GetWordFromTxBuffer(uint32 idx) + { + uint32 value; + + if (SPI_1_ONE_BYTE_WIDTH == SPI_1_txDataBits) + { + value = (uint32) SPI_1_txBuffer[idx]; + } + else + { + value = (uint32) SPI_1_txBuffer[(uint32)(idx << 1u)]; + value |= (uint32) ((uint32) SPI_1_txBuffer[(uint32)(idx << 1u) + 1u] << 8u); + } + + return (value); + } + +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_SPI_UART.h b/cores/asr650x/projects/PSoC4/SPI_1_SPI_UART.h new file mode 100644 index 00000000..48cd8b19 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_SPI_UART.h @@ -0,0 +1,1239 @@ +/***************************************************************************//** +* \file SPI_1_SPI_UART.h +* \version 4.0 +* +* \brief +* This file provides constants and parameter values for the SCB Component in +* SPI and UART modes. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + + +#if !defined(CY_SCB_SPI_UART_SPI_1_H) +#define CY_SCB_SPI_UART_SPI_1_H + +#include "SPI_1.h" + + +/*************************************** +* SPI Initial Parameter Constants +****************************************/ + +#define SPI_1_SPI_MODE (1u) +#define SPI_1_SPI_SUB_MODE (0u) +#define SPI_1_SPI_CLOCK_MODE (0u) +#define SPI_1_SPI_OVS_FACTOR (8u) +#define SPI_1_SPI_MEDIAN_FILTER_ENABLE (0u) +#define SPI_1_SPI_LATE_MISO_SAMPLE_ENABLE (0u) +#define SPI_1_SPI_RX_DATA_BITS_NUM (8u) +#define SPI_1_SPI_TX_DATA_BITS_NUM (8u) +#define SPI_1_SPI_WAKE_ENABLE (0u) +#define SPI_1_SPI_BITS_ORDER (1u) +#define SPI_1_SPI_TRANSFER_SEPARATION (1u) +#define SPI_1_SPI_NUMBER_OF_SS_LINES (0u) +#define SPI_1_SPI_RX_BUFFER_SIZE (8u) +#define SPI_1_SPI_TX_BUFFER_SIZE (8u) + +#define SPI_1_SPI_INTERRUPT_MODE (0u) + +#define SPI_1_SPI_INTR_RX_MASK (0x0u) +#define SPI_1_SPI_INTR_TX_MASK (0x0u) + +#define SPI_1_SPI_RX_TRIGGER_LEVEL (7u) +#define SPI_1_SPI_TX_TRIGGER_LEVEL (0u) + +#define SPI_1_SPI_BYTE_MODE_ENABLE (0u) +#define SPI_1_SPI_FREE_RUN_SCLK_ENABLE (0u) +#define SPI_1_SPI_SS0_POLARITY (0u) +#define SPI_1_SPI_SS1_POLARITY (0u) +#define SPI_1_SPI_SS2_POLARITY (0u) +#define SPI_1_SPI_SS3_POLARITY (0u) + + +/*************************************** +* UART Initial Parameter Constants +****************************************/ + +#define SPI_1_UART_SUB_MODE (0u) +#define SPI_1_UART_DIRECTION (3u) +#define SPI_1_UART_DATA_BITS_NUM (8u) +#define SPI_1_UART_PARITY_TYPE (2u) +#define SPI_1_UART_STOP_BITS_NUM (2u) +#define SPI_1_UART_OVS_FACTOR (12u) +#define SPI_1_UART_IRDA_LOW_POWER (0u) +#define SPI_1_UART_MEDIAN_FILTER_ENABLE (0u) +#define SPI_1_UART_RETRY_ON_NACK (0u) +#define SPI_1_UART_IRDA_POLARITY (0u) +#define SPI_1_UART_DROP_ON_FRAME_ERR (0u) +#define SPI_1_UART_DROP_ON_PARITY_ERR (0u) +#define SPI_1_UART_WAKE_ENABLE (0u) +#define SPI_1_UART_RX_BUFFER_SIZE (8u) +#define SPI_1_UART_TX_BUFFER_SIZE (8u) +#define SPI_1_UART_MP_MODE_ENABLE (0u) +#define SPI_1_UART_MP_ACCEPT_ADDRESS (0u) +#define SPI_1_UART_MP_RX_ADDRESS (0x2u) +#define SPI_1_UART_MP_RX_ADDRESS_MASK (0xFFu) + +#define SPI_1_UART_INTERRUPT_MODE (0u) + +#define SPI_1_UART_INTR_RX_MASK (0x0u) +#define SPI_1_UART_INTR_TX_MASK (0x0u) + +#define SPI_1_UART_RX_TRIGGER_LEVEL (7u) +#define SPI_1_UART_TX_TRIGGER_LEVEL (0u) + +#define SPI_1_UART_BYTE_MODE_ENABLE (0u) +#define SPI_1_UART_CTS_ENABLE (0u) +#define SPI_1_UART_CTS_POLARITY (0u) +#define SPI_1_UART_RTS_ENABLE (0u) +#define SPI_1_UART_RTS_POLARITY (0u) +#define SPI_1_UART_RTS_FIFO_LEVEL (4u) + +#define SPI_1_UART_RX_BREAK_WIDTH (11u) + +/* SPI mode enum */ +#define SPI_1_SPI_SLAVE (0u) +#define SPI_1_SPI_MASTER (1u) + +/* UART direction enum */ +#define SPI_1_UART_RX (1u) +#define SPI_1_UART_TX (2u) +#define SPI_1_UART_TX_RX (3u) + + +/*************************************** +* Conditional Compilation Parameters +****************************************/ + +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + + /* Mode */ + #define SPI_1_SPI_SLAVE_CONST (1u) + #define SPI_1_SPI_MASTER_CONST (1u) + + /* Direction */ + #define SPI_1_RX_DIRECTION (1u) + #define SPI_1_TX_DIRECTION (1u) + #define SPI_1_UART_RX_DIRECTION (1u) + #define SPI_1_UART_TX_DIRECTION (1u) + + /* Only external RX and TX buffer for Uncofigured mode */ + #define SPI_1_INTERNAL_RX_SW_BUFFER (0u) + #define SPI_1_INTERNAL_TX_SW_BUFFER (0u) + + /* Get RX and TX buffer size */ + #define SPI_1_INTERNAL_RX_BUFFER_SIZE (SPI_1_rxBufferSize + 1u) + #define SPI_1_RX_BUFFER_SIZE (SPI_1_rxBufferSize) + #define SPI_1_TX_BUFFER_SIZE (SPI_1_txBufferSize) + + /* Return true if buffer is provided */ + #define SPI_1_CHECK_RX_SW_BUFFER (NULL != SPI_1_rxBuffer) + #define SPI_1_CHECK_TX_SW_BUFFER (NULL != SPI_1_txBuffer) + + /* Always provide global variables to support RX and TX buffers */ + #define SPI_1_INTERNAL_RX_SW_BUFFER_CONST (1u) + #define SPI_1_INTERNAL_TX_SW_BUFFER_CONST (1u) + + /* Get wakeup enable option */ + #define SPI_1_SPI_WAKE_ENABLE_CONST (1u) + #define SPI_1_UART_WAKE_ENABLE_CONST (1u) + #define SPI_1_CHECK_SPI_WAKE_ENABLE ((0u != SPI_1_scbEnableWake) && SPI_1_SCB_MODE_SPI_RUNTM_CFG) + #define SPI_1_CHECK_UART_WAKE_ENABLE ((0u != SPI_1_scbEnableWake) && SPI_1_SCB_MODE_UART_RUNTM_CFG) + + /* SPI/UART: TX or RX FIFO size */ + #if (SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + #define SPI_1_SPI_UART_FIFO_SIZE (SPI_1_FIFO_SIZE) + #define SPI_1_CHECK_UART_RTS_CONTROL_FLOW (0u) + #else + #define SPI_1_SPI_UART_FIFO_SIZE (SPI_1_GET_FIFO_SIZE(SPI_1_CTRL_REG & \ + SPI_1_CTRL_BYTE_MODE)) + + #define SPI_1_CHECK_UART_RTS_CONTROL_FLOW \ + ((SPI_1_SCB_MODE_UART_RUNTM_CFG) && \ + (0u != SPI_1_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(SPI_1_UART_FLOW_CTRL_REG))) + #endif /* (SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ + +#else + + /* Internal RX and TX buffer: for SPI or UART */ + #if (SPI_1_SCB_MODE_SPI_CONST_CFG) + + /* SPI Direction */ + #define SPI_1_SPI_RX_DIRECTION (1u) + #define SPI_1_SPI_TX_DIRECTION (1u) + + /* Get FIFO size */ + #define SPI_1_SPI_UART_FIFO_SIZE SPI_1_GET_FIFO_SIZE(SPI_1_SPI_BYTE_MODE_ENABLE) + + /* SPI internal RX and TX buffers */ + #define SPI_1_INTERNAL_SPI_RX_SW_BUFFER (SPI_1_SPI_RX_BUFFER_SIZE > \ + SPI_1_SPI_UART_FIFO_SIZE) + #define SPI_1_INTERNAL_SPI_TX_SW_BUFFER (SPI_1_SPI_TX_BUFFER_SIZE > \ + SPI_1_SPI_UART_FIFO_SIZE) + + /* Internal SPI RX and TX buffer */ + #define SPI_1_INTERNAL_RX_SW_BUFFER (SPI_1_INTERNAL_SPI_RX_SW_BUFFER) + #define SPI_1_INTERNAL_TX_SW_BUFFER (SPI_1_INTERNAL_SPI_TX_SW_BUFFER) + + /* Internal SPI RX and TX buffer size */ + #define SPI_1_INTERNAL_RX_BUFFER_SIZE (SPI_1_SPI_RX_BUFFER_SIZE + 1u) + #define SPI_1_RX_BUFFER_SIZE (SPI_1_SPI_RX_BUFFER_SIZE) + #define SPI_1_TX_BUFFER_SIZE (SPI_1_SPI_TX_BUFFER_SIZE) + + /* Get wakeup enable option */ + #define SPI_1_SPI_WAKE_ENABLE_CONST (0u != SPI_1_SPI_WAKE_ENABLE) + #define SPI_1_UART_WAKE_ENABLE_CONST (0u) + + #else + + /* UART Direction */ + #define SPI_1_UART_RX_DIRECTION (0u != (SPI_1_UART_DIRECTION & SPI_1_UART_RX)) + #define SPI_1_UART_TX_DIRECTION (0u != (SPI_1_UART_DIRECTION & SPI_1_UART_TX)) + + /* Get FIFO size */ + #define SPI_1_SPI_UART_FIFO_SIZE SPI_1_GET_FIFO_SIZE(SPI_1_UART_BYTE_MODE_ENABLE) + + /* UART internal RX and TX buffers */ + #define SPI_1_INTERNAL_UART_RX_SW_BUFFER (SPI_1_UART_RX_BUFFER_SIZE > \ + SPI_1_SPI_UART_FIFO_SIZE) + #define SPI_1_INTERNAL_UART_TX_SW_BUFFER (SPI_1_UART_TX_BUFFER_SIZE > \ + SPI_1_SPI_UART_FIFO_SIZE) + + /* Internal UART RX and TX buffer */ + #define SPI_1_INTERNAL_RX_SW_BUFFER (SPI_1_INTERNAL_UART_RX_SW_BUFFER) + #define SPI_1_INTERNAL_TX_SW_BUFFER (SPI_1_INTERNAL_UART_TX_SW_BUFFER) + + /* Internal UART RX and TX buffer size */ + #define SPI_1_INTERNAL_RX_BUFFER_SIZE (SPI_1_UART_RX_BUFFER_SIZE + 1u) + #define SPI_1_RX_BUFFER_SIZE (SPI_1_UART_RX_BUFFER_SIZE) + #define SPI_1_TX_BUFFER_SIZE (SPI_1_UART_TX_BUFFER_SIZE) + + /* Get wakeup enable option */ + #define SPI_1_SPI_WAKE_ENABLE_CONST (0u) + #define SPI_1_UART_WAKE_ENABLE_CONST (0u != SPI_1_UART_WAKE_ENABLE) + + #endif /* (SPI_1_SCB_MODE_SPI_CONST_CFG) */ + + /* Mode */ + #define SPI_1_SPI_SLAVE_CONST (SPI_1_SPI_MODE == SPI_1_SPI_SLAVE) + #define SPI_1_SPI_MASTER_CONST (SPI_1_SPI_MODE == SPI_1_SPI_MASTER) + + /* Direction */ + #define SPI_1_RX_DIRECTION ((SPI_1_SCB_MODE_SPI_CONST_CFG) ? \ + (SPI_1_SPI_RX_DIRECTION) : (SPI_1_UART_RX_DIRECTION)) + + #define SPI_1_TX_DIRECTION ((SPI_1_SCB_MODE_SPI_CONST_CFG) ? \ + (SPI_1_SPI_TX_DIRECTION) : (SPI_1_UART_TX_DIRECTION)) + + /* Internal RX and TX buffer: for SPI or UART. Used in conditional compilation check */ + #define SPI_1_CHECK_RX_SW_BUFFER (SPI_1_INTERNAL_RX_SW_BUFFER) + #define SPI_1_CHECK_TX_SW_BUFFER (SPI_1_INTERNAL_TX_SW_BUFFER) + + /* Provide global variables to support RX and TX buffers */ + #define SPI_1_INTERNAL_RX_SW_BUFFER_CONST (SPI_1_INTERNAL_RX_SW_BUFFER) + #define SPI_1_INTERNAL_TX_SW_BUFFER_CONST (SPI_1_INTERNAL_TX_SW_BUFFER) + + /* Wake up enable */ + #define SPI_1_CHECK_SPI_WAKE_ENABLE (SPI_1_SPI_WAKE_ENABLE_CONST) + #define SPI_1_CHECK_UART_WAKE_ENABLE (SPI_1_UART_WAKE_ENABLE_CONST) + + /* UART flow control: not applicable for CY_SCBIP_V0 || CY_SCBIP_V1 */ + #define SPI_1_CHECK_UART_RTS_CONTROL_FLOW (SPI_1_SCB_MODE_UART_CONST_CFG && \ + SPI_1_UART_RTS_ENABLE) + +#endif /* End (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Type Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* SPI_1_SPI_INIT_STRUCT */ +typedef struct +{ + /** Mode of operation for SPI. The following defines are available choices: + * - SPI_1_SPI_SLAVE + * - SPI_1_SPI_MASTE + */ + uint32 mode; + + /** Submode of operation for SPI. The following defines are available + * choices: + * - SPI_1_SPI_MODE_MOTOROLA + * - SPI_1_SPI_MODE_TI_COINCIDES + * - SPI_1_SPI_MODE_TI_PRECEDES + * - SPI_1_SPI_MODE_NATIONAL + */ + uint32 submode; + + /** Determines the sclk relationship for Motorola submode. Ignored + * for other submodes. The following defines are available choices: + * - SPI_1_SPI_SCLK_CPHA0_CPOL0 + * - SPI_1_SPI_SCLK_CPHA0_CPOL1 + * - SPI_1_SPI_SCLK_CPHA1_CPOL0 + * - SPI_1_SPI_SCLK_CPHA1_CPOL1 + */ + uint32 sclkMode; + + /** Oversampling factor for the SPI clock. Ignored for Slave mode operation. + */ + uint32 oversample; + + /** Applies median filter on the input lines: 0 鈥?not applied, 1 鈥?applied. + */ + uint32 enableMedianFilter; + + /** Applies late sampling of MISO line: 0 鈥?not applied, 1 鈥?applied. + * Ignored for slave mode. + */ + uint32 enableLateSampling; + + /** Enables wakeup from low power mode: 0 鈥?disable, 1 鈥?enable. + * Ignored for master mode. + */ + uint32 enableWake; + + /** Number of data bits for RX direction. + * Different dataBitsRx and dataBitsTx are only allowed for National + * submode. + */ + uint32 rxDataBits; + + /** Number of data bits for TX direction. + * Different dataBitsRx and dataBitsTx are only allowed for National + * submode. + */ + uint32 txDataBits; + + /** Determines the bit ordering. The following defines are available + * choices: + * - SPI_1_BITS_ORDER_LSB_FIRST + * - SPI_1_BITS_ORDER_MSB_FIRST + */ + uint32 bitOrder; + + /** Determines whether transfers are back to back or have SS disabled + * between words. Ignored for slave mode. The following defines are + * available choices: + * - SPI_1_SPI_TRANSFER_CONTINUOUS + * - SPI_1_SPI_TRANSFER_SEPARATED + */ + uint32 transferSeperation; + + /** Size of the RX buffer in bytes/words (depends on rxDataBits parameter). + * A value equal to the RX FIFO depth implies the usage of buffering in + * hardware. A value greater than the RX FIFO depth results in a software + * buffer. + * The SPI_1_INTR _RX_NOT_EMPTY interrupt has to be enabled to + * transfer data into the software buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 rxBufferSize; + + /** Buffer space provided for a RX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal (rxBufferSize + 1) in bytes if + * dataBitsRx is less or equal to 8, otherwise (2 * (rxBufferSize + 1)) + * in bytes. The software RX buffer always keeps one element empty. + * For correct operation the allocated RX buffer has to be one element + * greater than maximum packet size expected to be received. + */ + uint8* rxBuffer; + + /** Size of the TX buffer in bytes/words(depends on txDataBits parameter). + * A value equal to the TX FIFO depth implies the usage of buffering in + * hardware. A value greater than the TX FIFO depth results in a software + * buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 txBufferSize; + + /** Buffer space provided for a TX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal txBufferSize if dataBitsTx is + * less or equal to 8, otherwise (2* txBufferSize). + */ + uint8* txBuffer; + + /** Enables component interrupt: 0 鈥?disable, 1 鈥?enable. + * The interrupt has to be enabled if software buffer is used. + */ + uint32 enableInterrupt; + + /** Mask of enabled interrupt sources for the RX direction. This mask is + * written regardless of the setting of the enable Interrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - SPI_1_INTR_RX_FIFO_LEVEL + * - SPI_1_INTR_RX_NOT_EMPTY + * - SPI_1_INTR_RX_FULL + * - SPI_1_INTR_RX_OVERFLOW + * - SPI_1_INTR_RX_UNDERFLOW + * - SPI_1_INTR_SLAVE_SPI_BUS_ERROR + */ + uint32 rxInterruptMask; + + /** FIFO level for an RX FIFO level interrupt. This value is written + * regardless of whether the RX FIFO level interrupt source is enabled. + */ + uint32 rxTriggerLevel; + + /** Mask of enabled interrupt sources for the TX direction. This mask is + * written regardless of the setting of the enable Interrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - SPI_1_INTR_TX_FIFO_LEVEL + * - SPI_1_INTR_TX_NOT_FULL + * - SPI_1_INTR_TX_EMPTY + * - SPI_1_INTR_TX_OVERFLOW + * - SPI_1_INTR_TX_UNDERFLOW + * - SPI_1_INTR_MASTER_SPI_DONE + */ + uint32 txInterruptMask; + + /** FIFO level for a TX FIFO level interrupt. This value is written + * regardless of whether the TX FIFO level interrupt source is enabled. + */ + uint32 txTriggerLevel; + + /** When enabled the TX and RX FIFO depth is doubled and equal to + * 16 bytes: 0 鈥?disable, 1 鈥?enable. This implies that number of + * TX and RX data bits must be less than or equal to 8. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableByteMode; + + /** Enables continuous SCLK generation by the SPI master: 0 鈥?disable, + * 1 鈥?enable. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableFreeRunSclk; + + /** Active polarity of slave select lines 0-3. This is bit mask where bit + * SPI_1_SPI_SLAVE_SELECT0 corresponds to slave select 0 + * polarity, bit SPI_1_SPI_SLAVE_SELECT1 鈥?slave select 1 + * polarity and so on. Polarity constants are: + * - SPI_1_SPI_SS_ACTIVE_LOW + * - SPI_1_SPI_SS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 polaritySs; +} SPI_1_SPI_INIT_STRUCT; + + +/* SPI_1_UART_INIT_STRUCT */ +typedef struct +{ + /** Mode of operation for the UART. The following defines are available + * choices: + * - SPI_1_UART_MODE_STD + * - SPI_1_UART_MODE_SMARTCARD + * - SPI_1_UART_MODE_IRDA + */ + uint32 mode; + + /** Direction of operation for the UART. The following defines are available + * choices: + * - SPI_1_UART_TX_RX + * - SPI_1_UART_RX + * - SPI_1_UART_TX + */ + uint32 direction; + + /** Number of data bits. + */ + uint32 dataBits; + + /** Determines the parity. The following defines are available choices: + * - SPI_1_UART_PARITY_EVEN + * - SPI_1_UART_PARITY_ODD + * - SPI_1_UART_PARITY_NONE + */ + uint32 parity; + + /** Determines the number of stop bits. The following defines are available + * choices: + * - SPI_1_UART_STOP_BITS_1 + * - SPI_1_UART_STOP_BITS_1_5 + * - SPI_1_UART_STOP_BITS_2 + */ + uint32 stopBits; + + /** Oversampling factor for the UART. + * + * Note The oversampling factor values are changed when enableIrdaLowPower + * is enabled: + * - SPI_1_UART_IRDA_LP_OVS16 + * - SPI_1_UART_IRDA_LP_OVS32 + * - SPI_1_UART_IRDA_LP_OVS48 + * - SPI_1_UART_IRDA_LP_OVS96 + * - SPI_1_UART_IRDA_LP_OVS192 + * - SPI_1_UART_IRDA_LP_OVS768 + * - SPI_1_UART_IRDA_LP_OVS1536 + */ + uint32 oversample; + + /** Enables IrDA low power RX mode operation: 0 鈥?disable, 1 鈥?enable. + * The TX functionality does not work when enabled. + */ + uint32 enableIrdaLowPower; + + /** Applies median filter on the input lines: 0 鈥?not applied, 1 鈥?applied. + */ + uint32 enableMedianFilter; + + /** Enables retry when NACK response was received: 0 鈥?disable, 1 鈥?enable. + * Only current content of TX FIFO is re-sent. + * Ignored for modes other than SmartCard. + */ + uint32 enableRetryNack; + + /** Inverts polarity of RX line: 0 鈥?non-inverting, 1 鈥?inverting. + * Ignored for modes other than IrDA. + */ + uint32 enableInvertedRx; + + /** Drop data from RX FIFO if parity error is detected: 0 鈥?disable, + * 1 鈥?enable. + */ + uint32 dropOnParityErr; + + /** Drop data from RX FIFO if a frame error is detected: 0 鈥?disable, + * 1 鈥?enable. + */ + uint32 dropOnFrameErr; + + /** Enables wakeup from low power mode: 0 鈥?disable, 1 鈥?enable. + * Ignored for modes other than standard UART. The RX functionality + * has to be enabled. + */ + uint32 enableWake; + + /** Size of the RX buffer in bytes/words (depends on rxDataBits parameter). + * A value equal to the RX FIFO depth implies the usage of buffering in + * hardware. A value greater than the RX FIFO depth results in a software + * buffer. + * The SPI_1_INTR _RX_NOT_EMPTY interrupt has to be enabled to + * transfer data into the software buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 rxBufferSize; + + /** Buffer space provided for a RX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal (rxBufferSize + 1) in bytes if + * dataBitsRx is less or equal to 8, otherwise (2 * (rxBufferSize + 1)) + * in bytes. The software RX buffer always keeps one element empty. + * For correct operation the allocated RX buffer has to be one element + * greater than maximum packet size expected to be received. + */ + uint8* rxBuffer; + + /** Size of the TX buffer in bytes/words(depends on txDataBits parameter). + * A value equal to the TX FIFO depth implies the usage of buffering in + * hardware. A value greater than the TX FIFO depth results in a software + * buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 txBufferSize; + + /** Buffer space provided for a TX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal txBufferSize if dataBitsTx is + * less or equal to 8, otherwise (2* txBufferSize). + */ + uint8* txBuffer; + + /** Enables multiprocessor mode: 0 鈥?disable, 1 鈥?enable. + */ + uint32 enableMultiproc; + + /** Enables matched address to be accepted: 0 鈥?disable, 1 鈥?enable. + */ + uint32 multiprocAcceptAddr; + + /** 8 bit address to match in Multiprocessor mode. Ignored for other modes. + */ + uint32 multiprocAddr; + + /** 8 bit mask of address bits that are compared for a Multiprocessor + * address match. Ignored for other modes. + * - Bit value 0 鈥?excludes bit from address comparison. + * - Bit value 1 鈥?the bit needs to match with the corresponding bit + * of the device address. + */ + uint32 multiprocAddrMask; + + /** Enables component interrupt: 0 鈥?disable, 1 鈥?enable. + * The interrupt has to be enabled if software buffer is used. + */ + uint32 enableInterrupt; + + /** Mask of interrupt sources to enable in the RX direction. This mask is + * written regardless of the setting of the enableInterrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - SPI_1_INTR_RX_FIFO_LEVEL + * - SPI_1_INTR_RX_NOT_EMPTY + * - SPI_1_INTR_RX_FULL + * - SPI_1_INTR_RX_OVERFLOW + * - SPI_1_INTR_RX_UNDERFLOW + * - SPI_1_INTR_RX_FRAME_ERROR + * - SPI_1_INTR_RX_PARITY_ERROR + */ + uint32 rxInterruptMask; + + /** FIFO level for an RX FIFO level interrupt. This value is written + * regardless of whether the RX FIFO level interrupt source is enabled. + */ + uint32 rxTriggerLevel; + + /** Mask of interrupt sources to enable in the TX direction. This mask is + * written regardless of the setting of the enableInterrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - SPI_1_INTR_TX_FIFO_LEVEL + * - SPI_1_INTR_TX_NOT_FULL + * - SPI_1_INTR_TX_EMPTY + * - SPI_1_INTR_TX_OVERFLOW + * - SPI_1_INTR_TX_UNDERFLOW + * - SPI_1_INTR_TX_UART_DONE + * - SPI_1_INTR_TX_UART_NACK + * - SPI_1_INTR_TX_UART_ARB_LOST + */ + uint32 txInterruptMask; + + /** FIFO level for a TX FIFO level interrupt. This value is written + * regardless of whether the TX FIFO level interrupt source is enabled. + */ + uint32 txTriggerLevel; + + /** When enabled the TX and RX FIFO depth is doubled and equal to + * 16 bytes: 0 鈥?disable, 1 鈥?enable. This implies that number of + * Data bits must be less than or equal to 8. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableByteMode; + + /** Enables usage of CTS input signal by the UART transmitter : 0 鈥?disable, + * 1 鈥?enable. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableCts; + + /** Sets active polarity of CTS input signal: + * - SPI_1_UART_CTS_ACTIVE_LOW + * - SPI_1_UART_CTS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 ctsPolarity; + + /** RX FIFO level for RTS signal activation. While the RX FIFO has fewer + * entries than the RTS FIFO level value the RTS signal remains active, + * otherwise the RTS signal becomes inactive. By setting this field to 0, + * RTS signal activation is disabled. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 rtsRxFifoLevel; + + /** Sets active polarity of RTS output signal: + * - SPI_1_UART_RTS_ ACTIVE_LOW + * - SPI_1_UART_RTS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 rtsPolarity; + + /** Configures the width of a break signal in that triggers the break + * detection interrupt source. A Break is a low level on the RX line. + * Valid range is 1-16 UART bits times. + */ + uint8 breakWidth; +} SPI_1_UART_INIT_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_spi +* @{ +*/ +/* SPI specific functions */ +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + void SPI_1_SpiInit(const SPI_1_SPI_INIT_STRUCT *config); +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +#if(SPI_1_SCB_MODE_SPI_INC) + /******************************************************************************* + * Function Name: SPI_1_SpiIsBusBusy + ****************************************************************************//** + * + * Returns the current status on the bus. The bus status is determined using + * the slave select signal. + * - Motorola and National Semiconductor sub-modes: The bus is busy after + * the slave select line is activated and lasts until the slave select line + * is deactivated. + * - Texas Instrument sub-modes: The bus is busy at the moment of the initial + * pulse on the slave select line and lasts until the transfer is complete. + * If SPI Master is configured to use "Separated transfers" + * (see Continuous versus Separated Transfer Separation), the bus is busy + * during each element transfer and is free between each element transfer. + * The Master does not activate SS line immediately after data has been + * written into the TX FIFO. + * + * \return slaveSelect: Current status on the bus. + * If the returned value is nonzero, the bus is busy. + * If zero is returned, the bus is free. The bus status is determined using + * the slave select signal. + * + *******************************************************************************/ + #define SPI_1_SpiIsBusBusy() ((uint32) (0u != (SPI_1_SPI_STATUS_REG & \ + SPI_1_SPI_STATUS_BUS_BUSY))) + + #if (SPI_1_SPI_MASTER_CONST) + void SPI_1_SpiSetActiveSlaveSelect(uint32 slaveSelect); + #endif /*(SPI_1_SPI_MASTER_CONST) */ + + #if !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + void SPI_1_SpiSetSlaveSelectPolarity(uint32 slaveSelect, uint32 polarity); + #endif /* !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ +#endif /* (SPI_1_SCB_MODE_SPI_INC) */ +/** @} spi */ + +/** +* \addtogroup group_uart +* @{ +*/ +/* UART specific functions */ +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + void SPI_1_UartInit(const SPI_1_UART_INIT_STRUCT *config); +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if(SPI_1_SCB_MODE_UART_INC) + void SPI_1_UartSetRxAddress(uint32 address); + void SPI_1_UartSetRxAddressMask(uint32 addressMask); + + + /* UART RX direction APIs */ + #if(SPI_1_UART_RX_DIRECTION) + uint32 SPI_1_UartGetChar(void); + uint32 SPI_1_UartGetByte(void); + + #if !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + /* UART APIs for Flow Control */ + void SPI_1_UartSetRtsPolarity(uint32 polarity); + void SPI_1_UartSetRtsFifoLevel(uint32 level); + #endif /* !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ + #endif /* (SPI_1_UART_RX_DIRECTION) */ + + /* UART TX direction APIs */ + #if(SPI_1_UART_TX_DIRECTION) + /******************************************************************************* + * Function Name: SPI_1_UartPutChar + ****************************************************************************//** + * + * Places a byte of data in the transmit buffer to be sent at the next available + * bus time. This function is blocking and waits until there is a space + * available to put requested data in the transmit buffer. + * For UART Multi Processor mode this function can send 9-bits data as well. + * Use SPI_1_UART_MP_MARK to add a mark to create an address byte. + * + * \param txDataByte: the data to be transmitted. + * + *******************************************************************************/ + #define SPI_1_UartPutChar(ch) SPI_1_SpiUartWriteTxData((uint32)(ch)) + + void SPI_1_UartPutString(const char8 string[]); + void SPI_1_UartPutCRLF(uint32 txDataByte); + void SPI_1_UartSendBreakBlocking(uint32 breakWidth); + + #if !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) + /* UART APIs for Flow Control */ + void SPI_1_UartEnableCts(void); + void SPI_1_UartDisableCts(void); + void SPI_1_UartSetCtsPolarity(uint32 polarity); + #endif /* !(SPI_1_CY_SCBIP_V0 || SPI_1_CY_SCBIP_V1) */ + #endif /* (SPI_1_UART_TX_DIRECTION) */ +#endif /* (SPI_1_SCB_MODE_UART_INC) */ +/** @} uart */ + +/** +* \addtogroup group_spi_uart +* @{ +*/ +#if(SPI_1_RX_DIRECTION) + uint32 SPI_1_SpiUartReadRxData(void); + uint32 SPI_1_SpiUartGetRxBufferSize(void); + void SPI_1_SpiUartClearRxBuffer(void); +#endif /* (SPI_1_RX_DIRECTION) */ + +/* Common APIs TX direction */ +#if(SPI_1_TX_DIRECTION) + void SPI_1_SpiUartWriteTxData(uint32 txData); + void SPI_1_SpiUartPutArray(const uint8 wrBuf[], uint32 count); + uint32 SPI_1_SpiUartGetTxBufferSize(void); + void SPI_1_SpiUartClearTxBuffer(void); +#endif /* (SPI_1_TX_DIRECTION) */ +/** @} spi_uart */ + +CY_ISR_PROTO(SPI_1_SPI_UART_ISR); + +#if(SPI_1_UART_RX_WAKEUP_IRQ) + CY_ISR_PROTO(SPI_1_UART_WAKEUP_ISR); +#endif /* (SPI_1_UART_RX_WAKEUP_IRQ) */ + + +/*************************************** +* Buffer Access Macro Definitions +***************************************/ + +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + /* RX direction */ + void SPI_1_PutWordInRxBuffer (uint32 idx, uint32 rxDataByte); + uint32 SPI_1_GetWordFromRxBuffer(uint32 idx); + + /* TX direction */ + void SPI_1_PutWordInTxBuffer (uint32 idx, uint32 txDataByte); + uint32 SPI_1_GetWordFromTxBuffer(uint32 idx); + +#else + /* RX direction */ + #if(SPI_1_INTERNAL_RX_SW_BUFFER_CONST) + #define SPI_1_PutWordInRxBuffer(idx, rxDataByte) \ + do{ \ + SPI_1_rxBufferInternal[(idx)] = ((uint8) (rxDataByte)); \ + }while(0) + + #define SPI_1_GetWordFromRxBuffer(idx) SPI_1_rxBufferInternal[(idx)] + + #endif /* (SPI_1_INTERNAL_RX_SW_BUFFER_CONST) */ + + /* TX direction */ + #if(SPI_1_INTERNAL_TX_SW_BUFFER_CONST) + #define SPI_1_PutWordInTxBuffer(idx, txDataByte) \ + do{ \ + SPI_1_txBufferInternal[(idx)] = ((uint8) (txDataByte)); \ + }while(0) + + #define SPI_1_GetWordFromTxBuffer(idx) SPI_1_txBufferInternal[(idx)] + + #endif /* (SPI_1_INTERNAL_TX_SW_BUFFER_CONST) */ + +#endif /* (SPI_1_TX_SW_BUFFER_ENABLE) */ + + +/*************************************** +* SPI API Constants +***************************************/ + +/* SPI sub mode enum */ +#define SPI_1_SPI_MODE_MOTOROLA (0x00u) +#define SPI_1_SPI_MODE_TI_COINCIDES (0x01u) +#define SPI_1_SPI_MODE_TI_PRECEDES (0x11u) +#define SPI_1_SPI_MODE_NATIONAL (0x02u) +#define SPI_1_SPI_MODE_MASK (0x03u) +#define SPI_1_SPI_MODE_TI_PRECEDES_MASK (0x10u) +#define SPI_1_SPI_MODE_NS_MICROWIRE (SPI_1_SPI_MODE_NATIONAL) + +/* SPI phase and polarity mode enum */ +#define SPI_1_SPI_SCLK_CPHA0_CPOL0 (0x00u) +#define SPI_1_SPI_SCLK_CPHA0_CPOL1 (0x02u) +#define SPI_1_SPI_SCLK_CPHA1_CPOL0 (0x01u) +#define SPI_1_SPI_SCLK_CPHA1_CPOL1 (0x03u) + +/* SPI bits order enum */ +#define SPI_1_BITS_ORDER_LSB_FIRST (0u) +#define SPI_1_BITS_ORDER_MSB_FIRST (1u) + +/* SPI transfer separation enum */ +#define SPI_1_SPI_TRANSFER_SEPARATED (0u) +#define SPI_1_SPI_TRANSFER_CONTINUOUS (1u) + +/* SPI slave select constants */ +#define SPI_1_SPI_SLAVE_SELECT0 (SPI_1_SCB__SS0_POSISTION) +#define SPI_1_SPI_SLAVE_SELECT1 (SPI_1_SCB__SS1_POSISTION) +#define SPI_1_SPI_SLAVE_SELECT2 (SPI_1_SCB__SS2_POSISTION) +#define SPI_1_SPI_SLAVE_SELECT3 (SPI_1_SCB__SS3_POSISTION) + +/* SPI slave select polarity settings */ +#define SPI_1_SPI_SS_ACTIVE_LOW (0u) +#define SPI_1_SPI_SS_ACTIVE_HIGH (1u) + +#define SPI_1_INTR_SPIM_TX_RESTORE (SPI_1_INTR_TX_OVERFLOW) + +#define SPI_1_INTR_SPIS_TX_RESTORE (SPI_1_INTR_TX_OVERFLOW | \ + SPI_1_INTR_TX_UNDERFLOW) + +/*************************************** +* UART API Constants +***************************************/ + +/* UART sub-modes enum */ +#define SPI_1_UART_MODE_STD (0u) +#define SPI_1_UART_MODE_SMARTCARD (1u) +#define SPI_1_UART_MODE_IRDA (2u) + +/* UART direction enum */ +#define SPI_1_UART_RX (1u) +#define SPI_1_UART_TX (2u) +#define SPI_1_UART_TX_RX (3u) + +/* UART parity enum */ +#define SPI_1_UART_PARITY_EVEN (0u) +#define SPI_1_UART_PARITY_ODD (1u) +#define SPI_1_UART_PARITY_NONE (2u) + +/* UART stop bits enum */ +#define SPI_1_UART_STOP_BITS_1 (2u) +#define SPI_1_UART_STOP_BITS_1_5 (3u) +#define SPI_1_UART_STOP_BITS_2 (4u) + +/* UART IrDA low power OVS enum */ +#define SPI_1_UART_IRDA_LP_OVS16 (16u) +#define SPI_1_UART_IRDA_LP_OVS32 (32u) +#define SPI_1_UART_IRDA_LP_OVS48 (48u) +#define SPI_1_UART_IRDA_LP_OVS96 (96u) +#define SPI_1_UART_IRDA_LP_OVS192 (192u) +#define SPI_1_UART_IRDA_LP_OVS768 (768u) +#define SPI_1_UART_IRDA_LP_OVS1536 (1536u) + +/* Uart MP: mark (address) and space (data) bit definitions */ +#define SPI_1_UART_MP_MARK (0x100u) +#define SPI_1_UART_MP_SPACE (0x000u) + +/* UART CTS/RTS polarity settings */ +#define SPI_1_UART_CTS_ACTIVE_LOW (0u) +#define SPI_1_UART_CTS_ACTIVE_HIGH (1u) +#define SPI_1_UART_RTS_ACTIVE_LOW (0u) +#define SPI_1_UART_RTS_ACTIVE_HIGH (1u) + +/* Sources of RX errors */ +#define SPI_1_INTR_RX_ERR (SPI_1_INTR_RX_OVERFLOW | \ + SPI_1_INTR_RX_UNDERFLOW | \ + SPI_1_INTR_RX_FRAME_ERROR | \ + SPI_1_INTR_RX_PARITY_ERROR) + +/* Shifted INTR_RX_ERR defines ONLY for SPI_1_UartGetByte() */ +#define SPI_1_UART_RX_OVERFLOW (SPI_1_INTR_RX_OVERFLOW << 8u) +#define SPI_1_UART_RX_UNDERFLOW (SPI_1_INTR_RX_UNDERFLOW << 8u) +#define SPI_1_UART_RX_FRAME_ERROR (SPI_1_INTR_RX_FRAME_ERROR << 8u) +#define SPI_1_UART_RX_PARITY_ERROR (SPI_1_INTR_RX_PARITY_ERROR << 8u) +#define SPI_1_UART_RX_ERROR_MASK (SPI_1_UART_RX_OVERFLOW | \ + SPI_1_UART_RX_UNDERFLOW | \ + SPI_1_UART_RX_FRAME_ERROR | \ + SPI_1_UART_RX_PARITY_ERROR) + +#define SPI_1_INTR_UART_TX_RESTORE (SPI_1_INTR_TX_OVERFLOW | \ + SPI_1_INTR_TX_UART_NACK | \ + SPI_1_INTR_TX_UART_DONE | \ + SPI_1_INTR_TX_UART_ARB_LOST) + + +/*************************************** +* Vars with External Linkage +***************************************/ + +#if(SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) + extern const SPI_1_SPI_INIT_STRUCT SPI_1_configSpi; + extern const SPI_1_UART_INIT_STRUCT SPI_1_configUart; +#endif /* (SPI_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if (SPI_1_UART_WAKE_ENABLE_CONST && SPI_1_UART_RX_WAKEUP_IRQ) + extern uint8 SPI_1_skipStart; +#endif /* (SPI_1_UART_WAKE_ENABLE_CONST && SPI_1_UART_RX_WAKEUP_IRQ) */ + + +/*************************************** +* Specific SPI Macro Definitions +***************************************/ + +#define SPI_1_GET_SPI_INTR_SLAVE_MASK(sourceMask) ((sourceMask) & SPI_1_INTR_SLAVE_SPI_BUS_ERROR) +#define SPI_1_GET_SPI_INTR_MASTER_MASK(sourceMask) ((sourceMask) & SPI_1_INTR_MASTER_SPI_DONE) +#define SPI_1_GET_SPI_INTR_RX_MASK(sourceMask) \ + ((sourceMask) & (uint32) ~SPI_1_INTR_SLAVE_SPI_BUS_ERROR) + +#define SPI_1_GET_SPI_INTR_TX_MASK(sourceMask) \ + ((sourceMask) & (uint32) ~SPI_1_INTR_MASTER_SPI_DONE) + + +/*************************************** +* Specific UART Macro Definitions +***************************************/ + +#define SPI_1_UART_GET_CTRL_OVS_IRDA_LP(oversample) \ + ((SPI_1_UART_IRDA_LP_OVS16 == (oversample)) ? SPI_1_CTRL_OVS_IRDA_LP_OVS16 : \ + ((SPI_1_UART_IRDA_LP_OVS32 == (oversample)) ? SPI_1_CTRL_OVS_IRDA_LP_OVS32 : \ + ((SPI_1_UART_IRDA_LP_OVS48 == (oversample)) ? SPI_1_CTRL_OVS_IRDA_LP_OVS48 : \ + ((SPI_1_UART_IRDA_LP_OVS96 == (oversample)) ? SPI_1_CTRL_OVS_IRDA_LP_OVS96 : \ + ((SPI_1_UART_IRDA_LP_OVS192 == (oversample)) ? SPI_1_CTRL_OVS_IRDA_LP_OVS192 : \ + ((SPI_1_UART_IRDA_LP_OVS768 == (oversample)) ? SPI_1_CTRL_OVS_IRDA_LP_OVS768 : \ + ((SPI_1_UART_IRDA_LP_OVS1536 == (oversample)) ? SPI_1_CTRL_OVS_IRDA_LP_OVS1536 : \ + SPI_1_CTRL_OVS_IRDA_LP_OVS16))))))) + +#define SPI_1_GET_UART_RX_CTRL_ENABLED(direction) ((0u != (SPI_1_UART_RX & (direction))) ? \ + (SPI_1_RX_CTRL_ENABLED) : (0u)) + +#define SPI_1_GET_UART_TX_CTRL_ENABLED(direction) ((0u != (SPI_1_UART_TX & (direction))) ? \ + (SPI_1_TX_CTRL_ENABLED) : (0u)) + + +/*************************************** +* SPI Register Settings +***************************************/ + +#define SPI_1_CTRL_SPI (SPI_1_CTRL_MODE_SPI) +#define SPI_1_SPI_RX_CTRL (SPI_1_RX_CTRL_ENABLED) +#define SPI_1_SPI_TX_CTRL (SPI_1_TX_CTRL_ENABLED) + + +/*************************************** +* SPI Init Register Settings +***************************************/ + +#define SPI_1_SPI_SS_POLARITY \ + (((uint32) SPI_1_SPI_SS0_POLARITY << SPI_1_SPI_SLAVE_SELECT0) | \ + ((uint32) SPI_1_SPI_SS1_POLARITY << SPI_1_SPI_SLAVE_SELECT1) | \ + ((uint32) SPI_1_SPI_SS2_POLARITY << SPI_1_SPI_SLAVE_SELECT2) | \ + ((uint32) SPI_1_SPI_SS3_POLARITY << SPI_1_SPI_SLAVE_SELECT3)) + +#if(SPI_1_SCB_MODE_SPI_CONST_CFG) + + /* SPI Configuration */ + #define SPI_1_SPI_DEFAULT_CTRL \ + (SPI_1_GET_CTRL_OVS(SPI_1_SPI_OVS_FACTOR) | \ + SPI_1_GET_CTRL_BYTE_MODE (SPI_1_SPI_BYTE_MODE_ENABLE) | \ + SPI_1_GET_CTRL_EC_AM_MODE(SPI_1_SPI_WAKE_ENABLE) | \ + SPI_1_CTRL_SPI) + + #define SPI_1_SPI_DEFAULT_SPI_CTRL \ + (SPI_1_GET_SPI_CTRL_CONTINUOUS (SPI_1_SPI_TRANSFER_SEPARATION) | \ + SPI_1_GET_SPI_CTRL_SELECT_PRECEDE(SPI_1_SPI_SUB_MODE & \ + SPI_1_SPI_MODE_TI_PRECEDES_MASK) | \ + SPI_1_GET_SPI_CTRL_SCLK_MODE (SPI_1_SPI_CLOCK_MODE) | \ + SPI_1_GET_SPI_CTRL_LATE_MISO_SAMPLE(SPI_1_SPI_LATE_MISO_SAMPLE_ENABLE) | \ + SPI_1_GET_SPI_CTRL_SCLK_CONTINUOUS(SPI_1_SPI_FREE_RUN_SCLK_ENABLE) | \ + SPI_1_GET_SPI_CTRL_SSEL_POLARITY (SPI_1_SPI_SS_POLARITY) | \ + SPI_1_GET_SPI_CTRL_SUB_MODE (SPI_1_SPI_SUB_MODE) | \ + SPI_1_GET_SPI_CTRL_MASTER_MODE (SPI_1_SPI_MODE)) + + /* RX direction */ + #define SPI_1_SPI_DEFAULT_RX_CTRL \ + (SPI_1_GET_RX_CTRL_DATA_WIDTH(SPI_1_SPI_RX_DATA_BITS_NUM) | \ + SPI_1_GET_RX_CTRL_BIT_ORDER (SPI_1_SPI_BITS_ORDER) | \ + SPI_1_GET_RX_CTRL_MEDIAN (SPI_1_SPI_MEDIAN_FILTER_ENABLE) | \ + SPI_1_SPI_RX_CTRL) + + #define SPI_1_SPI_DEFAULT_RX_FIFO_CTRL \ + SPI_1_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(SPI_1_SPI_RX_TRIGGER_LEVEL) + + /* TX direction */ + #define SPI_1_SPI_DEFAULT_TX_CTRL \ + (SPI_1_GET_TX_CTRL_DATA_WIDTH(SPI_1_SPI_TX_DATA_BITS_NUM) | \ + SPI_1_GET_TX_CTRL_BIT_ORDER (SPI_1_SPI_BITS_ORDER) | \ + SPI_1_SPI_TX_CTRL) + + #define SPI_1_SPI_DEFAULT_TX_FIFO_CTRL \ + SPI_1_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(SPI_1_SPI_TX_TRIGGER_LEVEL) + + /* Interrupt sources */ + #define SPI_1_SPI_DEFAULT_INTR_SPI_EC_MASK (SPI_1_NO_INTR_SOURCES) + + #define SPI_1_SPI_DEFAULT_INTR_I2C_EC_MASK (SPI_1_NO_INTR_SOURCES) + #define SPI_1_SPI_DEFAULT_INTR_SLAVE_MASK \ + (SPI_1_SPI_INTR_RX_MASK & SPI_1_INTR_SLAVE_SPI_BUS_ERROR) + + #define SPI_1_SPI_DEFAULT_INTR_MASTER_MASK \ + (SPI_1_SPI_INTR_TX_MASK & SPI_1_INTR_MASTER_SPI_DONE) + + #define SPI_1_SPI_DEFAULT_INTR_RX_MASK \ + (SPI_1_SPI_INTR_RX_MASK & (uint32) ~SPI_1_INTR_SLAVE_SPI_BUS_ERROR) + + #define SPI_1_SPI_DEFAULT_INTR_TX_MASK \ + (SPI_1_SPI_INTR_TX_MASK & (uint32) ~SPI_1_INTR_MASTER_SPI_DONE) + +#endif /* (SPI_1_SCB_MODE_SPI_CONST_CFG) */ + + +/*************************************** +* UART Register Settings +***************************************/ + +#define SPI_1_CTRL_UART (SPI_1_CTRL_MODE_UART) +#define SPI_1_UART_RX_CTRL (SPI_1_RX_CTRL_LSB_FIRST) /* LSB for UART goes first */ +#define SPI_1_UART_TX_CTRL (SPI_1_TX_CTRL_LSB_FIRST) /* LSB for UART goes first */ + + +/*************************************** +* UART Init Register Settings +***************************************/ + +#if(SPI_1_SCB_MODE_UART_CONST_CFG) + + /* UART configuration */ + #if(SPI_1_UART_MODE_IRDA == SPI_1_UART_SUB_MODE) + + #define SPI_1_DEFAULT_CTRL_OVS ((0u != SPI_1_UART_IRDA_LOW_POWER) ? \ + (SPI_1_UART_GET_CTRL_OVS_IRDA_LP(SPI_1_UART_OVS_FACTOR)) : \ + (SPI_1_CTRL_OVS_IRDA_OVS16)) + + #else + + #define SPI_1_DEFAULT_CTRL_OVS SPI_1_GET_CTRL_OVS(SPI_1_UART_OVS_FACTOR) + + #endif /* (SPI_1_UART_MODE_IRDA == SPI_1_UART_SUB_MODE) */ + + #define SPI_1_UART_DEFAULT_CTRL \ + (SPI_1_GET_CTRL_BYTE_MODE (SPI_1_UART_BYTE_MODE_ENABLE) | \ + SPI_1_GET_CTRL_ADDR_ACCEPT(SPI_1_UART_MP_ACCEPT_ADDRESS) | \ + SPI_1_DEFAULT_CTRL_OVS | \ + SPI_1_CTRL_UART) + + #define SPI_1_UART_DEFAULT_UART_CTRL \ + (SPI_1_GET_UART_CTRL_MODE(SPI_1_UART_SUB_MODE)) + + /* RX direction */ + #define SPI_1_UART_DEFAULT_RX_CTRL_PARITY \ + ((SPI_1_UART_PARITY_NONE != SPI_1_UART_PARITY_TYPE) ? \ + (SPI_1_GET_UART_RX_CTRL_PARITY(SPI_1_UART_PARITY_TYPE) | \ + SPI_1_UART_RX_CTRL_PARITY_ENABLED) : (0u)) + + #define SPI_1_UART_DEFAULT_UART_RX_CTRL \ + (SPI_1_GET_UART_RX_CTRL_MODE(SPI_1_UART_STOP_BITS_NUM) | \ + SPI_1_GET_UART_RX_CTRL_POLARITY(SPI_1_UART_IRDA_POLARITY) | \ + SPI_1_GET_UART_RX_CTRL_MP_MODE(SPI_1_UART_MP_MODE_ENABLE) | \ + SPI_1_GET_UART_RX_CTRL_DROP_ON_PARITY_ERR(SPI_1_UART_DROP_ON_PARITY_ERR) | \ + SPI_1_GET_UART_RX_CTRL_DROP_ON_FRAME_ERR(SPI_1_UART_DROP_ON_FRAME_ERR) | \ + SPI_1_GET_UART_RX_CTRL_BREAK_WIDTH(SPI_1_UART_RX_BREAK_WIDTH) | \ + SPI_1_UART_DEFAULT_RX_CTRL_PARITY) + + + #define SPI_1_UART_DEFAULT_RX_CTRL \ + (SPI_1_GET_RX_CTRL_DATA_WIDTH(SPI_1_UART_DATA_BITS_NUM) | \ + SPI_1_GET_RX_CTRL_MEDIAN (SPI_1_UART_MEDIAN_FILTER_ENABLE) | \ + SPI_1_GET_UART_RX_CTRL_ENABLED(SPI_1_UART_DIRECTION)) + + #define SPI_1_UART_DEFAULT_RX_FIFO_CTRL \ + SPI_1_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(SPI_1_UART_RX_TRIGGER_LEVEL) + + #define SPI_1_UART_DEFAULT_RX_MATCH_REG ((0u != SPI_1_UART_MP_MODE_ENABLE) ? \ + (SPI_1_GET_RX_MATCH_ADDR(SPI_1_UART_MP_RX_ADDRESS) | \ + SPI_1_GET_RX_MATCH_MASK(SPI_1_UART_MP_RX_ADDRESS_MASK)) : (0u)) + + /* TX direction */ + #define SPI_1_UART_DEFAULT_TX_CTRL_PARITY (SPI_1_UART_DEFAULT_RX_CTRL_PARITY) + + #define SPI_1_UART_DEFAULT_UART_TX_CTRL \ + (SPI_1_GET_UART_TX_CTRL_MODE(SPI_1_UART_STOP_BITS_NUM) | \ + SPI_1_GET_UART_TX_CTRL_RETRY_NACK(SPI_1_UART_RETRY_ON_NACK) | \ + SPI_1_UART_DEFAULT_TX_CTRL_PARITY) + + #define SPI_1_UART_DEFAULT_TX_CTRL \ + (SPI_1_GET_TX_CTRL_DATA_WIDTH(SPI_1_UART_DATA_BITS_NUM) | \ + SPI_1_GET_UART_TX_CTRL_ENABLED(SPI_1_UART_DIRECTION)) + + #define SPI_1_UART_DEFAULT_TX_FIFO_CTRL \ + SPI_1_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(SPI_1_UART_TX_TRIGGER_LEVEL) + + #define SPI_1_UART_DEFAULT_FLOW_CTRL \ + (SPI_1_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(SPI_1_UART_RTS_FIFO_LEVEL) | \ + SPI_1_GET_UART_FLOW_CTRL_RTS_POLARITY (SPI_1_UART_RTS_POLARITY) | \ + SPI_1_GET_UART_FLOW_CTRL_CTS_POLARITY (SPI_1_UART_CTS_POLARITY) | \ + SPI_1_GET_UART_FLOW_CTRL_CTS_ENABLE (SPI_1_UART_CTS_ENABLE)) + + /* Interrupt sources */ + #define SPI_1_UART_DEFAULT_INTR_I2C_EC_MASK (SPI_1_NO_INTR_SOURCES) + #define SPI_1_UART_DEFAULT_INTR_SPI_EC_MASK (SPI_1_NO_INTR_SOURCES) + #define SPI_1_UART_DEFAULT_INTR_SLAVE_MASK (SPI_1_NO_INTR_SOURCES) + #define SPI_1_UART_DEFAULT_INTR_MASTER_MASK (SPI_1_NO_INTR_SOURCES) + #define SPI_1_UART_DEFAULT_INTR_RX_MASK (SPI_1_UART_INTR_RX_MASK) + #define SPI_1_UART_DEFAULT_INTR_TX_MASK (SPI_1_UART_INTR_TX_MASK) + +#endif /* (SPI_1_SCB_MODE_UART_CONST_CFG) */ + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +#define SPI_1_SPIM_ACTIVE_SS0 (SPI_1_SPI_SLAVE_SELECT0) +#define SPI_1_SPIM_ACTIVE_SS1 (SPI_1_SPI_SLAVE_SELECT1) +#define SPI_1_SPIM_ACTIVE_SS2 (SPI_1_SPI_SLAVE_SELECT2) +#define SPI_1_SPIM_ACTIVE_SS3 (SPI_1_SPI_SLAVE_SELECT3) + +#endif /* CY_SCB_SPI_UART_SPI_1_H */ + +#ifdef __cplusplus +} +#endif + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_SPI_UART_PVT.h b/cores/asr650x/projects/PSoC4/SPI_1_SPI_UART_PVT.h new file mode 100644 index 00000000..ddefc497 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_SPI_UART_PVT.h @@ -0,0 +1,117 @@ +/***************************************************************************//** +* \file SPI_1_SPI_UART_PVT.h +* \version 4.0 +* +* \brief +* This private file provides constants and parameter values for the +* SCB Component in SPI and UART modes. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_SPI_UART_PVT_SPI_1_H) +#define CY_SCB_SPI_UART_PVT_SPI_1_H + +#include "SPI_1_SPI_UART.h" + + +/*************************************** +* Internal Global Vars +***************************************/ + +#if (SPI_1_INTERNAL_RX_SW_BUFFER_CONST) + extern volatile uint32 SPI_1_rxBufferHead; + extern volatile uint32 SPI_1_rxBufferTail; + + /** + * \addtogroup group_globals + * @{ + */ + + /** Sets when internal software receive buffer overflow + * was occurred. + */ + extern volatile uint8 SPI_1_rxBufferOverflow; + /** @} globals */ +#endif /* (SPI_1_INTERNAL_RX_SW_BUFFER_CONST) */ + +#if (SPI_1_INTERNAL_TX_SW_BUFFER_CONST) + extern volatile uint32 SPI_1_txBufferHead; + extern volatile uint32 SPI_1_txBufferTail; +#endif /* (SPI_1_INTERNAL_TX_SW_BUFFER_CONST) */ + +#if (SPI_1_INTERNAL_RX_SW_BUFFER) + extern volatile uint8 SPI_1_rxBufferInternal[SPI_1_INTERNAL_RX_BUFFER_SIZE]; +#endif /* (SPI_1_INTERNAL_RX_SW_BUFFER) */ + +#if (SPI_1_INTERNAL_TX_SW_BUFFER) + extern volatile uint8 SPI_1_txBufferInternal[SPI_1_TX_BUFFER_SIZE]; +#endif /* (SPI_1_INTERNAL_TX_SW_BUFFER) */ + + +/*************************************** +* Private Function Prototypes +***************************************/ + +void SPI_1_SpiPostEnable(void); +void SPI_1_SpiStop(void); + +#if (SPI_1_SCB_MODE_SPI_CONST_CFG) + void SPI_1_SpiInit(void); +#endif /* (SPI_1_SCB_MODE_SPI_CONST_CFG) */ + +#if (SPI_1_SPI_WAKE_ENABLE_CONST) + void SPI_1_SpiSaveConfig(void); + void SPI_1_SpiRestoreConfig(void); +#endif /* (SPI_1_SPI_WAKE_ENABLE_CONST) */ + +void SPI_1_UartPostEnable(void); +void SPI_1_UartStop(void); + +#if (SPI_1_SCB_MODE_UART_CONST_CFG) + void SPI_1_UartInit(void); +#endif /* (SPI_1_SCB_MODE_UART_CONST_CFG) */ + +#if (SPI_1_UART_WAKE_ENABLE_CONST) + void SPI_1_UartSaveConfig(void); + void SPI_1_UartRestoreConfig(void); +#endif /* (SPI_1_UART_WAKE_ENABLE_CONST) */ + + +/*************************************** +* UART API Constants +***************************************/ + +/* UART RX and TX position to be used in SPI_1_SetPins() */ +#define SPI_1_UART_RX_PIN_ENABLE (SPI_1_UART_RX) +#define SPI_1_UART_TX_PIN_ENABLE (SPI_1_UART_TX) + +/* UART RTS and CTS position to be used in SPI_1_SetPins() */ +#define SPI_1_UART_RTS_PIN_ENABLE (0x10u) +#define SPI_1_UART_CTS_PIN_ENABLE (0x20u) + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +/* Interrupt processing */ +#define SPI_1_SpiUartEnableIntRx(intSourceMask) SPI_1_SetRxInterruptMode(intSourceMask) +#define SPI_1_SpiUartEnableIntTx(intSourceMask) SPI_1_SetTxInterruptMode(intSourceMask) +uint32 SPI_1_SpiUartDisableIntRx(void); +uint32 SPI_1_SpiUartDisableIntTx(void); + + +#endif /* (CY_SCB_SPI_UART_PVT_SPI_1_H) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_miso_m.c b/cores/asr650x/projects/PSoC4/SPI_1_miso_m.c new file mode 100644 index 00000000..2fc464dc --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_miso_m.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* File Name: SPI_1_miso_m.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SPI_1_miso_m.h" + + +#if defined(SPI_1_miso_m__PC) + #define SPI_1_miso_m_SetP4PinDriveMode(shift, mode) \ + do { \ + SPI_1_miso_m_PC = (SPI_1_miso_m_PC & \ + (uint32)(~(uint32)(SPI_1_miso_m_DRIVE_MODE_IND_MASK << \ + (SPI_1_miso_m_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (SPI_1_miso_m_DRIVE_MODE_BITS * (shift))); \ + } while (0) +#else + #if (CY_PSOC4_4200L) + #define SPI_1_miso_m_SetP4PinDriveMode(shift, mode) \ + do { \ + SPI_1_miso_m_USBIO_CTRL_REG = (SPI_1_miso_m_USBIO_CTRL_REG & \ + (uint32)(~(uint32)(SPI_1_miso_m_DRIVE_MODE_IND_MASK << \ + (SPI_1_miso_m_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (SPI_1_miso_m_DRIVE_MODE_BITS * (shift))); \ + } while (0) + #endif +#endif + + +#if defined(SPI_1_miso_m__PC) || (CY_PSOC4_4200L) + /******************************************************************************* + * Function Name: SPI_1_miso_m_SetDriveMode + ****************************************************************************//** + * + * \brief Sets the drive mode for each of the Pins component's pins. + * + * Note This affects all pins in the Pins component instance. Use the + * Per-Pin APIs if you wish to control individual pin's drive modes. + * + * Note USBIOs have limited drive functionality. Refer to the Drive Mode + * parameter for more information. + * + * \param mode + * Mode for the selected signals. Valid options are documented in + * \ref driveMode. + * + * \return + * None + * + * \sideeffect + * If you use read-modify-write operations that are not atomic, the ISR can + * cause corruption of this function. An ISR that interrupts this function + * and performs writes to the Pins component Drive Mode registers can cause + * corrupted port data. To avoid this issue, you should either use the Per-Pin + * APIs (primary method) or disable interrupts around this function. + * + * \funcusage + * \snippet SPI_1_miso_m_SUT.c usage_SPI_1_miso_m_SetDriveMode + *******************************************************************************/ + void SPI_1_miso_m_SetDriveMode(uint8 mode) + { + SPI_1_miso_m_SetP4PinDriveMode(SPI_1_miso_m__0__SHIFT, mode); + } +#endif + + +/******************************************************************************* +* Function Name: SPI_1_miso_m_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SPI_1_miso_m_SUT.c usage_SPI_1_miso_m_Write +*******************************************************************************/ +void SPI_1_miso_m_Write(uint8 value) +{ + uint8 drVal = (uint8)(SPI_1_miso_m_DR & (uint8)(~SPI_1_miso_m_MASK)); + drVal = (drVal | ((uint8)(value << SPI_1_miso_m_SHIFT) & SPI_1_miso_m_MASK)); + SPI_1_miso_m_DR = (uint32)drVal; +} + + +/******************************************************************************* +* Function Name: SPI_1_miso_m_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SPI_1_miso_m_SUT.c usage_SPI_1_miso_m_Read +*******************************************************************************/ +uint8 SPI_1_miso_m_Read(void) +{ + return (uint8)((SPI_1_miso_m_PS & SPI_1_miso_m_MASK) >> SPI_1_miso_m_SHIFT); +} + + +/******************************************************************************* +* Function Name: SPI_1_miso_m_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SPI_1_miso_m_Read() API because the +* SPI_1_miso_m_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SPI_1_miso_m_SUT.c usage_SPI_1_miso_m_ReadDataReg +*******************************************************************************/ +uint8 SPI_1_miso_m_ReadDataReg(void) +{ + return (uint8)((SPI_1_miso_m_DR & SPI_1_miso_m_MASK) >> SPI_1_miso_m_SHIFT); +} + + +/******************************************************************************* +* Function Name: SPI_1_miso_m_SetInterruptMode +****************************************************************************//** +* +* \brief Configures the interrupt mode for each of the Pins component's +* pins. Alternatively you may set the interrupt mode for all the pins +* specified in the Pins component. +* +* Note The interrupt is port-wide and therefore any enabled pin +* interrupt may trigger it. +* +* \param position +* The pin position as listed in the Pins component. You may OR these to be +* able to configure the interrupt mode of multiple pins within a Pins +* component. Or you may use SPI_1_miso_m_INTR_ALL to configure the +* interrupt mode of all the pins in the Pins component. +* - SPI_1_miso_m_0_INTR (First pin in the list) +* - SPI_1_miso_m_1_INTR (Second pin in the list) +* - ... +* - SPI_1_miso_m_INTR_ALL (All pins in Pins component) +* +* \param mode +* Interrupt mode for the selected pins. Valid options are documented in +* \ref intrMode. +* +* \return +* None +* +* \sideeffect +* It is recommended that the interrupt be disabled before calling this +* function to avoid unintended interrupt requests. Note that the interrupt +* type is port wide, and therefore will trigger for any enabled pin on the +* port. +* +* \funcusage +* \snippet SPI_1_miso_m_SUT.c usage_SPI_1_miso_m_SetInterruptMode +*******************************************************************************/ +void SPI_1_miso_m_SetInterruptMode(uint16 position, uint16 mode) +{ + uint32 intrCfg; + + intrCfg = SPI_1_miso_m_INTCFG & (uint32)(~(uint32)position); + SPI_1_miso_m_INTCFG = intrCfg | ((uint32)position & (uint32)mode); +} + + +/******************************************************************************* +* Function Name: SPI_1_miso_m_ClearInterrupt +****************************************************************************//** +* +* \brief Clears any active interrupts attached with the component and returns +* the value of the interrupt status register allowing determination of which +* pins generated an interrupt event. +* +* \return +* The right-shifted current value of the interrupt status register. Each pin +* has one bit set if it generated an interrupt event. For example, bit 0 is +* for pin 0 and bit 1 is for pin 1 of the Pins component. +* +* \sideeffect +* Clears all bits of the physical port's interrupt status register, not just +* those associated with the Pins component. +* +* \funcusage +* \snippet SPI_1_miso_m_SUT.c usage_SPI_1_miso_m_ClearInterrupt +*******************************************************************************/ +uint8 SPI_1_miso_m_ClearInterrupt(void) +{ + uint8 maskedStatus = (uint8)(SPI_1_miso_m_INTSTAT & SPI_1_miso_m_MASK); + SPI_1_miso_m_INTSTAT = maskedStatus; + return maskedStatus >> SPI_1_miso_m_SHIFT; +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_miso_m.h b/cores/asr650x/projects/PSoC4/SPI_1_miso_m.h new file mode 100644 index 00000000..956c364b --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_miso_m.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* File Name: SPI_1_miso_m.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_1_miso_m_H) /* Pins SPI_1_miso_m_H */ +#define CY_PINS_SPI_1_miso_m_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "SPI_1_miso_m_aliases.h" + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* Structure for sleep mode support */ +typedef struct +{ + uint32 pcState; /**< State of the port control register */ + uint32 sioState; /**< State of the SIO configuration */ + uint32 usbState; /**< State of the USBIO regulator */ +} SPI_1_miso_m_BACKUP_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +uint8 SPI_1_miso_m_Read(void); +void SPI_1_miso_m_Write(uint8 value); +uint8 SPI_1_miso_m_ReadDataReg(void); +#if defined(SPI_1_miso_m__PC) || (CY_PSOC4_4200L) + void SPI_1_miso_m_SetDriveMode(uint8 mode); +#endif +void SPI_1_miso_m_SetInterruptMode(uint16 position, uint16 mode); +uint8 SPI_1_miso_m_ClearInterrupt(void); +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +void SPI_1_miso_m_Sleep(void); +void SPI_1_miso_m_Wakeup(void); +/** @} power */ + + +/*************************************** +* API Constants +***************************************/ +#if defined(SPI_1_miso_m__PC) || (CY_PSOC4_4200L) + /* Drive Modes */ + #define SPI_1_miso_m_DRIVE_MODE_BITS (3) + #define SPI_1_miso_m_DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - SPI_1_miso_m_DRIVE_MODE_BITS)) + + /** + * \addtogroup group_constants + * @{ + */ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SPI_1_miso_m_SetDriveMode() function. + * @{ + */ + #define SPI_1_miso_m_DM_ALG_HIZ (0x00u) /**< \brief High Impedance Analog */ + #define SPI_1_miso_m_DM_DIG_HIZ (0x01u) /**< \brief High Impedance Digital */ + #define SPI_1_miso_m_DM_RES_UP (0x02u) /**< \brief Resistive Pull Up */ + #define SPI_1_miso_m_DM_RES_DWN (0x03u) /**< \brief Resistive Pull Down */ + #define SPI_1_miso_m_DM_OD_LO (0x04u) /**< \brief Open Drain, Drives Low */ + #define SPI_1_miso_m_DM_OD_HI (0x05u) /**< \brief Open Drain, Drives High */ + #define SPI_1_miso_m_DM_STRONG (0x06u) /**< \brief Strong Drive */ + #define SPI_1_miso_m_DM_RES_UPDWN (0x07u) /**< \brief Resistive Pull Up/Down */ + /** @} driveMode */ + /** @} group_constants */ +#endif + +/* Digital Port Constants */ +#define SPI_1_miso_m_MASK SPI_1_miso_m__MASK +#define SPI_1_miso_m_SHIFT SPI_1_miso_m__SHIFT +#define SPI_1_miso_m_WIDTH 1u + +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SPI_1_miso_m_SetInterruptMode() function. + * @{ + */ + #define SPI_1_miso_m_INTR_NONE ((uint16)(0x0000u)) /**< \brief Disabled */ + #define SPI_1_miso_m_INTR_RISING ((uint16)(0x5555u)) /**< \brief Rising edge trigger */ + #define SPI_1_miso_m_INTR_FALLING ((uint16)(0xaaaau)) /**< \brief Falling edge trigger */ + #define SPI_1_miso_m_INTR_BOTH ((uint16)(0xffffu)) /**< \brief Both edge trigger */ + /** @} intrMode */ +/** @} group_constants */ + +/* SIO LPM definition */ +#if defined(SPI_1_miso_m__SIO) + #define SPI_1_miso_m_SIO_LPM_MASK (0x03u) +#endif + +/* USBIO definitions */ +#if !defined(SPI_1_miso_m__PC) && (CY_PSOC4_4200L) + #define SPI_1_miso_m_USBIO_ENABLE ((uint32)0x80000000u) + #define SPI_1_miso_m_USBIO_DISABLE ((uint32)(~SPI_1_miso_m_USBIO_ENABLE)) + #define SPI_1_miso_m_USBIO_SUSPEND_SHIFT CYFLD_USBDEVv2_USB_SUSPEND__OFFSET + #define SPI_1_miso_m_USBIO_SUSPEND_DEL_SHIFT CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET + #define SPI_1_miso_m_USBIO_ENTER_SLEEP ((uint32)((1u << SPI_1_miso_m_USBIO_SUSPEND_SHIFT) \ + | (1u << SPI_1_miso_m_USBIO_SUSPEND_DEL_SHIFT))) + #define SPI_1_miso_m_USBIO_EXIT_SLEEP_PH1 ((uint32)~((uint32)(1u << SPI_1_miso_m_USBIO_SUSPEND_SHIFT))) + #define SPI_1_miso_m_USBIO_EXIT_SLEEP_PH2 ((uint32)~((uint32)(1u << SPI_1_miso_m_USBIO_SUSPEND_DEL_SHIFT))) + #define SPI_1_miso_m_USBIO_CR1_OFF ((uint32)0xfffffffeu) +#endif + + +/*************************************** +* Registers +***************************************/ +/* Main Port Registers */ +#if defined(SPI_1_miso_m__PC) + /* Port Configuration */ + #define SPI_1_miso_m_PC (* (reg32 *) SPI_1_miso_m__PC) +#endif +/* Pin State */ +#define SPI_1_miso_m_PS (* (reg32 *) SPI_1_miso_m__PS) +/* Data Register */ +#define SPI_1_miso_m_DR (* (reg32 *) SPI_1_miso_m__DR) +/* Input Buffer Disable Override */ +#define SPI_1_miso_m_INP_DIS (* (reg32 *) SPI_1_miso_m__PC2) + +/* Interrupt configuration Registers */ +#define SPI_1_miso_m_INTCFG (* (reg32 *) SPI_1_miso_m__INTCFG) +#define SPI_1_miso_m_INTSTAT (* (reg32 *) SPI_1_miso_m__INTSTAT) + +/* "Interrupt cause" register for Combined Port Interrupt (AllPortInt) in GSRef component */ +#if defined (CYREG_GPIO_INTR_CAUSE) + #define SPI_1_miso_m_INTR_CAUSE (* (reg32 *) CYREG_GPIO_INTR_CAUSE) +#endif + +/* SIO register */ +#if defined(SPI_1_miso_m__SIO) + #define SPI_1_miso_m_SIO_REG (* (reg32 *) SPI_1_miso_m__SIO) +#endif /* (SPI_1_miso_m__SIO_CFG) */ + +/* USBIO registers */ +#if !defined(SPI_1_miso_m__PC) && (CY_PSOC4_4200L) + #define SPI_1_miso_m_USB_POWER_REG (* (reg32 *) CYREG_USBDEVv2_USB_POWER_CTRL) + #define SPI_1_miso_m_CR1_REG (* (reg32 *) CYREG_USBDEVv2_CR1) + #define SPI_1_miso_m_USBIO_CTRL_REG (* (reg32 *) CYREG_USBDEVv2_USB_USBIO_CTRL) +#endif + + +/*************************************** +* The following code is DEPRECATED and +* must not be used in new designs. +***************************************/ +/** +* \addtogroup group_deprecated +* @{ +*/ +#define SPI_1_miso_m_DRIVE_MODE_SHIFT (0x00u) +#define SPI_1_miso_m_DRIVE_MODE_MASK (0x07u << SPI_1_miso_m_DRIVE_MODE_SHIFT) +/** @} deprecated */ + +#endif /* End Pins SPI_1_miso_m_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_miso_m_PM.c b/cores/asr650x/projects/PSoC4/SPI_1_miso_m_PM.c new file mode 100644 index 00000000..4bd32e07 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_miso_m_PM.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: SPI_1_miso_m.c +* Version 2.20 +* +* Description: +* This file contains APIs to set up the Pins component for low power modes. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SPI_1_miso_m.h" + +static SPI_1_miso_m_BACKUP_STRUCT SPI_1_miso_m_backup = {0u, 0u, 0u}; + + +/******************************************************************************* +* Function Name: SPI_1_miso_m_Sleep +****************************************************************************//** +* +* \brief Stores the pin configuration and prepares the pin for entering chip +* deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. +* It should not be called for GPIO or GPIO_OVT pins. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \sideeffect +* For SIO pins, this function configures the pin input threshold to CMOS and +* drive level to Vddio. This is needed for SIO pins when in device +* deep-sleep/hibernate modes. +* +* \funcusage +* \snippet SPI_1_miso_m_SUT.c usage_SPI_1_miso_m_Sleep_Wakeup +*******************************************************************************/ +void SPI_1_miso_m_Sleep(void) +{ + #if defined(SPI_1_miso_m__PC) + SPI_1_miso_m_backup.pcState = SPI_1_miso_m_PC; + #else + #if (CY_PSOC4_4200L) + /* Save the regulator state and put the PHY into suspend mode */ + SPI_1_miso_m_backup.usbState = SPI_1_miso_m_CR1_REG; + SPI_1_miso_m_USB_POWER_REG |= SPI_1_miso_m_USBIO_ENTER_SLEEP; + SPI_1_miso_m_CR1_REG &= SPI_1_miso_m_USBIO_CR1_OFF; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(SPI_1_miso_m__SIO) + SPI_1_miso_m_backup.sioState = SPI_1_miso_m_SIO_REG; + /* SIO requires unregulated output buffer and single ended input buffer */ + SPI_1_miso_m_SIO_REG &= (uint32)(~SPI_1_miso_m_SIO_LPM_MASK); + #endif +} + + +/******************************************************************************* +* Function Name: SPI_1_miso_m_Wakeup +****************************************************************************//** +* +* \brief Restores the pin configuration that was saved during Pin_Sleep(). This +* function applies only to SIO and USBIO pins. It should not be called for +* GPIO or GPIO_OVT pins. +* +* For USBIO pins, the wakeup is only triggered for falling edge interrupts. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \funcusage +* Refer to SPI_1_miso_m_Sleep() for an example usage. +*******************************************************************************/ +void SPI_1_miso_m_Wakeup(void) +{ + #if defined(SPI_1_miso_m__PC) + SPI_1_miso_m_PC = SPI_1_miso_m_backup.pcState; + #else + #if (CY_PSOC4_4200L) + /* Restore the regulator state and come out of suspend mode */ + SPI_1_miso_m_USB_POWER_REG &= SPI_1_miso_m_USBIO_EXIT_SLEEP_PH1; + SPI_1_miso_m_CR1_REG = SPI_1_miso_m_backup.usbState; + SPI_1_miso_m_USB_POWER_REG &= SPI_1_miso_m_USBIO_EXIT_SLEEP_PH2; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(SPI_1_miso_m__SIO) + SPI_1_miso_m_SIO_REG = SPI_1_miso_m_backup.sioState; + #endif +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_miso_m_aliases.h b/cores/asr650x/projects/PSoC4/SPI_1_miso_m_aliases.h new file mode 100644 index 00000000..0654d061 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_miso_m_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SPI_1_miso_m.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_1_miso_m_ALIASES_H) /* Pins SPI_1_miso_m_ALIASES_H */ +#define CY_PINS_SPI_1_miso_m_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" + + +/*************************************** +* Constants +***************************************/ +#define SPI_1_miso_m_0 (SPI_1_miso_m__0__PC) +#define SPI_1_miso_m_0_PS (SPI_1_miso_m__0__PS) +#define SPI_1_miso_m_0_PC (SPI_1_miso_m__0__PC) +#define SPI_1_miso_m_0_DR (SPI_1_miso_m__0__DR) +#define SPI_1_miso_m_0_SHIFT (SPI_1_miso_m__0__SHIFT) +#define SPI_1_miso_m_0_INTR ((uint16)((uint16)0x0003u << (SPI_1_miso_m__0__SHIFT*2u))) + +#define SPI_1_miso_m_INTR_ALL ((uint16)(SPI_1_miso_m_0_INTR)) + + +#endif /* End Pins SPI_1_miso_m_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_mosi_m.c b/cores/asr650x/projects/PSoC4/SPI_1_mosi_m.c new file mode 100644 index 00000000..fd7af445 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_mosi_m.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* File Name: SPI_1_mosi_m.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SPI_1_mosi_m.h" + + +#if defined(SPI_1_mosi_m__PC) + #define SPI_1_mosi_m_SetP4PinDriveMode(shift, mode) \ + do { \ + SPI_1_mosi_m_PC = (SPI_1_mosi_m_PC & \ + (uint32)(~(uint32)(SPI_1_mosi_m_DRIVE_MODE_IND_MASK << \ + (SPI_1_mosi_m_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (SPI_1_mosi_m_DRIVE_MODE_BITS * (shift))); \ + } while (0) +#else + #if (CY_PSOC4_4200L) + #define SPI_1_mosi_m_SetP4PinDriveMode(shift, mode) \ + do { \ + SPI_1_mosi_m_USBIO_CTRL_REG = (SPI_1_mosi_m_USBIO_CTRL_REG & \ + (uint32)(~(uint32)(SPI_1_mosi_m_DRIVE_MODE_IND_MASK << \ + (SPI_1_mosi_m_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (SPI_1_mosi_m_DRIVE_MODE_BITS * (shift))); \ + } while (0) + #endif +#endif + + +#if defined(SPI_1_mosi_m__PC) || (CY_PSOC4_4200L) + /******************************************************************************* + * Function Name: SPI_1_mosi_m_SetDriveMode + ****************************************************************************//** + * + * \brief Sets the drive mode for each of the Pins component's pins. + * + * Note This affects all pins in the Pins component instance. Use the + * Per-Pin APIs if you wish to control individual pin's drive modes. + * + * Note USBIOs have limited drive functionality. Refer to the Drive Mode + * parameter for more information. + * + * \param mode + * Mode for the selected signals. Valid options are documented in + * \ref driveMode. + * + * \return + * None + * + * \sideeffect + * If you use read-modify-write operations that are not atomic, the ISR can + * cause corruption of this function. An ISR that interrupts this function + * and performs writes to the Pins component Drive Mode registers can cause + * corrupted port data. To avoid this issue, you should either use the Per-Pin + * APIs (primary method) or disable interrupts around this function. + * + * \funcusage + * \snippet SPI_1_mosi_m_SUT.c usage_SPI_1_mosi_m_SetDriveMode + *******************************************************************************/ + void SPI_1_mosi_m_SetDriveMode(uint8 mode) + { + SPI_1_mosi_m_SetP4PinDriveMode(SPI_1_mosi_m__0__SHIFT, mode); + } +#endif + + +/******************************************************************************* +* Function Name: SPI_1_mosi_m_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SPI_1_mosi_m_SUT.c usage_SPI_1_mosi_m_Write +*******************************************************************************/ +void SPI_1_mosi_m_Write(uint8 value) +{ + uint8 drVal = (uint8)(SPI_1_mosi_m_DR & (uint8)(~SPI_1_mosi_m_MASK)); + drVal = (drVal | ((uint8)(value << SPI_1_mosi_m_SHIFT) & SPI_1_mosi_m_MASK)); + SPI_1_mosi_m_DR = (uint32)drVal; +} + + +/******************************************************************************* +* Function Name: SPI_1_mosi_m_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SPI_1_mosi_m_SUT.c usage_SPI_1_mosi_m_Read +*******************************************************************************/ +uint8 SPI_1_mosi_m_Read(void) +{ + return (uint8)((SPI_1_mosi_m_PS & SPI_1_mosi_m_MASK) >> SPI_1_mosi_m_SHIFT); +} + + +/******************************************************************************* +* Function Name: SPI_1_mosi_m_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SPI_1_mosi_m_Read() API because the +* SPI_1_mosi_m_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SPI_1_mosi_m_SUT.c usage_SPI_1_mosi_m_ReadDataReg +*******************************************************************************/ +uint8 SPI_1_mosi_m_ReadDataReg(void) +{ + return (uint8)((SPI_1_mosi_m_DR & SPI_1_mosi_m_MASK) >> SPI_1_mosi_m_SHIFT); +} + + +/******************************************************************************* +* Function Name: SPI_1_mosi_m_SetInterruptMode +****************************************************************************//** +* +* \brief Configures the interrupt mode for each of the Pins component's +* pins. Alternatively you may set the interrupt mode for all the pins +* specified in the Pins component. +* +* Note The interrupt is port-wide and therefore any enabled pin +* interrupt may trigger it. +* +* \param position +* The pin position as listed in the Pins component. You may OR these to be +* able to configure the interrupt mode of multiple pins within a Pins +* component. Or you may use SPI_1_mosi_m_INTR_ALL to configure the +* interrupt mode of all the pins in the Pins component. +* - SPI_1_mosi_m_0_INTR (First pin in the list) +* - SPI_1_mosi_m_1_INTR (Second pin in the list) +* - ... +* - SPI_1_mosi_m_INTR_ALL (All pins in Pins component) +* +* \param mode +* Interrupt mode for the selected pins. Valid options are documented in +* \ref intrMode. +* +* \return +* None +* +* \sideeffect +* It is recommended that the interrupt be disabled before calling this +* function to avoid unintended interrupt requests. Note that the interrupt +* type is port wide, and therefore will trigger for any enabled pin on the +* port. +* +* \funcusage +* \snippet SPI_1_mosi_m_SUT.c usage_SPI_1_mosi_m_SetInterruptMode +*******************************************************************************/ +void SPI_1_mosi_m_SetInterruptMode(uint16 position, uint16 mode) +{ + uint32 intrCfg; + + intrCfg = SPI_1_mosi_m_INTCFG & (uint32)(~(uint32)position); + SPI_1_mosi_m_INTCFG = intrCfg | ((uint32)position & (uint32)mode); +} + + +/******************************************************************************* +* Function Name: SPI_1_mosi_m_ClearInterrupt +****************************************************************************//** +* +* \brief Clears any active interrupts attached with the component and returns +* the value of the interrupt status register allowing determination of which +* pins generated an interrupt event. +* +* \return +* The right-shifted current value of the interrupt status register. Each pin +* has one bit set if it generated an interrupt event. For example, bit 0 is +* for pin 0 and bit 1 is for pin 1 of the Pins component. +* +* \sideeffect +* Clears all bits of the physical port's interrupt status register, not just +* those associated with the Pins component. +* +* \funcusage +* \snippet SPI_1_mosi_m_SUT.c usage_SPI_1_mosi_m_ClearInterrupt +*******************************************************************************/ +uint8 SPI_1_mosi_m_ClearInterrupt(void) +{ + uint8 maskedStatus = (uint8)(SPI_1_mosi_m_INTSTAT & SPI_1_mosi_m_MASK); + SPI_1_mosi_m_INTSTAT = maskedStatus; + return maskedStatus >> SPI_1_mosi_m_SHIFT; +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_mosi_m.h b/cores/asr650x/projects/PSoC4/SPI_1_mosi_m.h new file mode 100644 index 00000000..e10dd72c --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_mosi_m.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* File Name: SPI_1_mosi_m.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_1_mosi_m_H) /* Pins SPI_1_mosi_m_H */ +#define CY_PINS_SPI_1_mosi_m_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "SPI_1_mosi_m_aliases.h" + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* Structure for sleep mode support */ +typedef struct +{ + uint32 pcState; /**< State of the port control register */ + uint32 sioState; /**< State of the SIO configuration */ + uint32 usbState; /**< State of the USBIO regulator */ +} SPI_1_mosi_m_BACKUP_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +uint8 SPI_1_mosi_m_Read(void); +void SPI_1_mosi_m_Write(uint8 value); +uint8 SPI_1_mosi_m_ReadDataReg(void); +#if defined(SPI_1_mosi_m__PC) || (CY_PSOC4_4200L) + void SPI_1_mosi_m_SetDriveMode(uint8 mode); +#endif +void SPI_1_mosi_m_SetInterruptMode(uint16 position, uint16 mode); +uint8 SPI_1_mosi_m_ClearInterrupt(void); +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +void SPI_1_mosi_m_Sleep(void); +void SPI_1_mosi_m_Wakeup(void); +/** @} power */ + + +/*************************************** +* API Constants +***************************************/ +#if defined(SPI_1_mosi_m__PC) || (CY_PSOC4_4200L) + /* Drive Modes */ + #define SPI_1_mosi_m_DRIVE_MODE_BITS (3) + #define SPI_1_mosi_m_DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - SPI_1_mosi_m_DRIVE_MODE_BITS)) + + /** + * \addtogroup group_constants + * @{ + */ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SPI_1_mosi_m_SetDriveMode() function. + * @{ + */ + #define SPI_1_mosi_m_DM_ALG_HIZ (0x00u) /**< \brief High Impedance Analog */ + #define SPI_1_mosi_m_DM_DIG_HIZ (0x01u) /**< \brief High Impedance Digital */ + #define SPI_1_mosi_m_DM_RES_UP (0x02u) /**< \brief Resistive Pull Up */ + #define SPI_1_mosi_m_DM_RES_DWN (0x03u) /**< \brief Resistive Pull Down */ + #define SPI_1_mosi_m_DM_OD_LO (0x04u) /**< \brief Open Drain, Drives Low */ + #define SPI_1_mosi_m_DM_OD_HI (0x05u) /**< \brief Open Drain, Drives High */ + #define SPI_1_mosi_m_DM_STRONG (0x06u) /**< \brief Strong Drive */ + #define SPI_1_mosi_m_DM_RES_UPDWN (0x07u) /**< \brief Resistive Pull Up/Down */ + /** @} driveMode */ + /** @} group_constants */ +#endif + +/* Digital Port Constants */ +#define SPI_1_mosi_m_MASK SPI_1_mosi_m__MASK +#define SPI_1_mosi_m_SHIFT SPI_1_mosi_m__SHIFT +#define SPI_1_mosi_m_WIDTH 1u + +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SPI_1_mosi_m_SetInterruptMode() function. + * @{ + */ + #define SPI_1_mosi_m_INTR_NONE ((uint16)(0x0000u)) /**< \brief Disabled */ + #define SPI_1_mosi_m_INTR_RISING ((uint16)(0x5555u)) /**< \brief Rising edge trigger */ + #define SPI_1_mosi_m_INTR_FALLING ((uint16)(0xaaaau)) /**< \brief Falling edge trigger */ + #define SPI_1_mosi_m_INTR_BOTH ((uint16)(0xffffu)) /**< \brief Both edge trigger */ + /** @} intrMode */ +/** @} group_constants */ + +/* SIO LPM definition */ +#if defined(SPI_1_mosi_m__SIO) + #define SPI_1_mosi_m_SIO_LPM_MASK (0x03u) +#endif + +/* USBIO definitions */ +#if !defined(SPI_1_mosi_m__PC) && (CY_PSOC4_4200L) + #define SPI_1_mosi_m_USBIO_ENABLE ((uint32)0x80000000u) + #define SPI_1_mosi_m_USBIO_DISABLE ((uint32)(~SPI_1_mosi_m_USBIO_ENABLE)) + #define SPI_1_mosi_m_USBIO_SUSPEND_SHIFT CYFLD_USBDEVv2_USB_SUSPEND__OFFSET + #define SPI_1_mosi_m_USBIO_SUSPEND_DEL_SHIFT CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET + #define SPI_1_mosi_m_USBIO_ENTER_SLEEP ((uint32)((1u << SPI_1_mosi_m_USBIO_SUSPEND_SHIFT) \ + | (1u << SPI_1_mosi_m_USBIO_SUSPEND_DEL_SHIFT))) + #define SPI_1_mosi_m_USBIO_EXIT_SLEEP_PH1 ((uint32)~((uint32)(1u << SPI_1_mosi_m_USBIO_SUSPEND_SHIFT))) + #define SPI_1_mosi_m_USBIO_EXIT_SLEEP_PH2 ((uint32)~((uint32)(1u << SPI_1_mosi_m_USBIO_SUSPEND_DEL_SHIFT))) + #define SPI_1_mosi_m_USBIO_CR1_OFF ((uint32)0xfffffffeu) +#endif + + +/*************************************** +* Registers +***************************************/ +/* Main Port Registers */ +#if defined(SPI_1_mosi_m__PC) + /* Port Configuration */ + #define SPI_1_mosi_m_PC (* (reg32 *) SPI_1_mosi_m__PC) +#endif +/* Pin State */ +#define SPI_1_mosi_m_PS (* (reg32 *) SPI_1_mosi_m__PS) +/* Data Register */ +#define SPI_1_mosi_m_DR (* (reg32 *) SPI_1_mosi_m__DR) +/* Input Buffer Disable Override */ +#define SPI_1_mosi_m_INP_DIS (* (reg32 *) SPI_1_mosi_m__PC2) + +/* Interrupt configuration Registers */ +#define SPI_1_mosi_m_INTCFG (* (reg32 *) SPI_1_mosi_m__INTCFG) +#define SPI_1_mosi_m_INTSTAT (* (reg32 *) SPI_1_mosi_m__INTSTAT) + +/* "Interrupt cause" register for Combined Port Interrupt (AllPortInt) in GSRef component */ +#if defined (CYREG_GPIO_INTR_CAUSE) + #define SPI_1_mosi_m_INTR_CAUSE (* (reg32 *) CYREG_GPIO_INTR_CAUSE) +#endif + +/* SIO register */ +#if defined(SPI_1_mosi_m__SIO) + #define SPI_1_mosi_m_SIO_REG (* (reg32 *) SPI_1_mosi_m__SIO) +#endif /* (SPI_1_mosi_m__SIO_CFG) */ + +/* USBIO registers */ +#if !defined(SPI_1_mosi_m__PC) && (CY_PSOC4_4200L) + #define SPI_1_mosi_m_USB_POWER_REG (* (reg32 *) CYREG_USBDEVv2_USB_POWER_CTRL) + #define SPI_1_mosi_m_CR1_REG (* (reg32 *) CYREG_USBDEVv2_CR1) + #define SPI_1_mosi_m_USBIO_CTRL_REG (* (reg32 *) CYREG_USBDEVv2_USB_USBIO_CTRL) +#endif + + +/*************************************** +* The following code is DEPRECATED and +* must not be used in new designs. +***************************************/ +/** +* \addtogroup group_deprecated +* @{ +*/ +#define SPI_1_mosi_m_DRIVE_MODE_SHIFT (0x00u) +#define SPI_1_mosi_m_DRIVE_MODE_MASK (0x07u << SPI_1_mosi_m_DRIVE_MODE_SHIFT) +/** @} deprecated */ + +#endif /* End Pins SPI_1_mosi_m_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_mosi_m_PM.c b/cores/asr650x/projects/PSoC4/SPI_1_mosi_m_PM.c new file mode 100644 index 00000000..209f43e9 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_mosi_m_PM.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: SPI_1_mosi_m.c +* Version 2.20 +* +* Description: +* This file contains APIs to set up the Pins component for low power modes. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SPI_1_mosi_m.h" + +static SPI_1_mosi_m_BACKUP_STRUCT SPI_1_mosi_m_backup = {0u, 0u, 0u}; + + +/******************************************************************************* +* Function Name: SPI_1_mosi_m_Sleep +****************************************************************************//** +* +* \brief Stores the pin configuration and prepares the pin for entering chip +* deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. +* It should not be called for GPIO or GPIO_OVT pins. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \sideeffect +* For SIO pins, this function configures the pin input threshold to CMOS and +* drive level to Vddio. This is needed for SIO pins when in device +* deep-sleep/hibernate modes. +* +* \funcusage +* \snippet SPI_1_mosi_m_SUT.c usage_SPI_1_mosi_m_Sleep_Wakeup +*******************************************************************************/ +void SPI_1_mosi_m_Sleep(void) +{ + #if defined(SPI_1_mosi_m__PC) + SPI_1_mosi_m_backup.pcState = SPI_1_mosi_m_PC; + #else + #if (CY_PSOC4_4200L) + /* Save the regulator state and put the PHY into suspend mode */ + SPI_1_mosi_m_backup.usbState = SPI_1_mosi_m_CR1_REG; + SPI_1_mosi_m_USB_POWER_REG |= SPI_1_mosi_m_USBIO_ENTER_SLEEP; + SPI_1_mosi_m_CR1_REG &= SPI_1_mosi_m_USBIO_CR1_OFF; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(SPI_1_mosi_m__SIO) + SPI_1_mosi_m_backup.sioState = SPI_1_mosi_m_SIO_REG; + /* SIO requires unregulated output buffer and single ended input buffer */ + SPI_1_mosi_m_SIO_REG &= (uint32)(~SPI_1_mosi_m_SIO_LPM_MASK); + #endif +} + + +/******************************************************************************* +* Function Name: SPI_1_mosi_m_Wakeup +****************************************************************************//** +* +* \brief Restores the pin configuration that was saved during Pin_Sleep(). This +* function applies only to SIO and USBIO pins. It should not be called for +* GPIO or GPIO_OVT pins. +* +* For USBIO pins, the wakeup is only triggered for falling edge interrupts. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \funcusage +* Refer to SPI_1_mosi_m_Sleep() for an example usage. +*******************************************************************************/ +void SPI_1_mosi_m_Wakeup(void) +{ + #if defined(SPI_1_mosi_m__PC) + SPI_1_mosi_m_PC = SPI_1_mosi_m_backup.pcState; + #else + #if (CY_PSOC4_4200L) + /* Restore the regulator state and come out of suspend mode */ + SPI_1_mosi_m_USB_POWER_REG &= SPI_1_mosi_m_USBIO_EXIT_SLEEP_PH1; + SPI_1_mosi_m_CR1_REG = SPI_1_mosi_m_backup.usbState; + SPI_1_mosi_m_USB_POWER_REG &= SPI_1_mosi_m_USBIO_EXIT_SLEEP_PH2; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(SPI_1_mosi_m__SIO) + SPI_1_mosi_m_SIO_REG = SPI_1_mosi_m_backup.sioState; + #endif +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_mosi_m_aliases.h b/cores/asr650x/projects/PSoC4/SPI_1_mosi_m_aliases.h new file mode 100644 index 00000000..7ee6d968 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_mosi_m_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SPI_1_mosi_m.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_1_mosi_m_ALIASES_H) /* Pins SPI_1_mosi_m_ALIASES_H */ +#define CY_PINS_SPI_1_mosi_m_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" + + +/*************************************** +* Constants +***************************************/ +#define SPI_1_mosi_m_0 (SPI_1_mosi_m__0__PC) +#define SPI_1_mosi_m_0_PS (SPI_1_mosi_m__0__PS) +#define SPI_1_mosi_m_0_PC (SPI_1_mosi_m__0__PC) +#define SPI_1_mosi_m_0_DR (SPI_1_mosi_m__0__DR) +#define SPI_1_mosi_m_0_SHIFT (SPI_1_mosi_m__0__SHIFT) +#define SPI_1_mosi_m_0_INTR ((uint16)((uint16)0x0003u << (SPI_1_mosi_m__0__SHIFT*2u))) + +#define SPI_1_mosi_m_INTR_ALL ((uint16)(SPI_1_mosi_m_0_INTR)) + + +#endif /* End Pins SPI_1_mosi_m_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_sclk_m.c b/cores/asr650x/projects/PSoC4/SPI_1_sclk_m.c new file mode 100644 index 00000000..187aefc1 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_sclk_m.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* File Name: SPI_1_sclk_m.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SPI_1_sclk_m.h" + + +#if defined(SPI_1_sclk_m__PC) + #define SPI_1_sclk_m_SetP4PinDriveMode(shift, mode) \ + do { \ + SPI_1_sclk_m_PC = (SPI_1_sclk_m_PC & \ + (uint32)(~(uint32)(SPI_1_sclk_m_DRIVE_MODE_IND_MASK << \ + (SPI_1_sclk_m_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (SPI_1_sclk_m_DRIVE_MODE_BITS * (shift))); \ + } while (0) +#else + #if (CY_PSOC4_4200L) + #define SPI_1_sclk_m_SetP4PinDriveMode(shift, mode) \ + do { \ + SPI_1_sclk_m_USBIO_CTRL_REG = (SPI_1_sclk_m_USBIO_CTRL_REG & \ + (uint32)(~(uint32)(SPI_1_sclk_m_DRIVE_MODE_IND_MASK << \ + (SPI_1_sclk_m_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (SPI_1_sclk_m_DRIVE_MODE_BITS * (shift))); \ + } while (0) + #endif +#endif + + +#if defined(SPI_1_sclk_m__PC) || (CY_PSOC4_4200L) + /******************************************************************************* + * Function Name: SPI_1_sclk_m_SetDriveMode + ****************************************************************************//** + * + * \brief Sets the drive mode for each of the Pins component's pins. + * + * Note This affects all pins in the Pins component instance. Use the + * Per-Pin APIs if you wish to control individual pin's drive modes. + * + * Note USBIOs have limited drive functionality. Refer to the Drive Mode + * parameter for more information. + * + * \param mode + * Mode for the selected signals. Valid options are documented in + * \ref driveMode. + * + * \return + * None + * + * \sideeffect + * If you use read-modify-write operations that are not atomic, the ISR can + * cause corruption of this function. An ISR that interrupts this function + * and performs writes to the Pins component Drive Mode registers can cause + * corrupted port data. To avoid this issue, you should either use the Per-Pin + * APIs (primary method) or disable interrupts around this function. + * + * \funcusage + * \snippet SPI_1_sclk_m_SUT.c usage_SPI_1_sclk_m_SetDriveMode + *******************************************************************************/ + void SPI_1_sclk_m_SetDriveMode(uint8 mode) + { + SPI_1_sclk_m_SetP4PinDriveMode(SPI_1_sclk_m__0__SHIFT, mode); + } +#endif + + +/******************************************************************************* +* Function Name: SPI_1_sclk_m_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SPI_1_sclk_m_SUT.c usage_SPI_1_sclk_m_Write +*******************************************************************************/ +void SPI_1_sclk_m_Write(uint8 value) +{ + uint8 drVal = (uint8)(SPI_1_sclk_m_DR & (uint8)(~SPI_1_sclk_m_MASK)); + drVal = (drVal | ((uint8)(value << SPI_1_sclk_m_SHIFT) & SPI_1_sclk_m_MASK)); + SPI_1_sclk_m_DR = (uint32)drVal; +} + + +/******************************************************************************* +* Function Name: SPI_1_sclk_m_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SPI_1_sclk_m_SUT.c usage_SPI_1_sclk_m_Read +*******************************************************************************/ +uint8 SPI_1_sclk_m_Read(void) +{ + return (uint8)((SPI_1_sclk_m_PS & SPI_1_sclk_m_MASK) >> SPI_1_sclk_m_SHIFT); +} + + +/******************************************************************************* +* Function Name: SPI_1_sclk_m_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SPI_1_sclk_m_Read() API because the +* SPI_1_sclk_m_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SPI_1_sclk_m_SUT.c usage_SPI_1_sclk_m_ReadDataReg +*******************************************************************************/ +uint8 SPI_1_sclk_m_ReadDataReg(void) +{ + return (uint8)((SPI_1_sclk_m_DR & SPI_1_sclk_m_MASK) >> SPI_1_sclk_m_SHIFT); +} + + +/******************************************************************************* +* Function Name: SPI_1_sclk_m_SetInterruptMode +****************************************************************************//** +* +* \brief Configures the interrupt mode for each of the Pins component's +* pins. Alternatively you may set the interrupt mode for all the pins +* specified in the Pins component. +* +* Note The interrupt is port-wide and therefore any enabled pin +* interrupt may trigger it. +* +* \param position +* The pin position as listed in the Pins component. You may OR these to be +* able to configure the interrupt mode of multiple pins within a Pins +* component. Or you may use SPI_1_sclk_m_INTR_ALL to configure the +* interrupt mode of all the pins in the Pins component. +* - SPI_1_sclk_m_0_INTR (First pin in the list) +* - SPI_1_sclk_m_1_INTR (Second pin in the list) +* - ... +* - SPI_1_sclk_m_INTR_ALL (All pins in Pins component) +* +* \param mode +* Interrupt mode for the selected pins. Valid options are documented in +* \ref intrMode. +* +* \return +* None +* +* \sideeffect +* It is recommended that the interrupt be disabled before calling this +* function to avoid unintended interrupt requests. Note that the interrupt +* type is port wide, and therefore will trigger for any enabled pin on the +* port. +* +* \funcusage +* \snippet SPI_1_sclk_m_SUT.c usage_SPI_1_sclk_m_SetInterruptMode +*******************************************************************************/ +void SPI_1_sclk_m_SetInterruptMode(uint16 position, uint16 mode) +{ + uint32 intrCfg; + + intrCfg = SPI_1_sclk_m_INTCFG & (uint32)(~(uint32)position); + SPI_1_sclk_m_INTCFG = intrCfg | ((uint32)position & (uint32)mode); +} + + +/******************************************************************************* +* Function Name: SPI_1_sclk_m_ClearInterrupt +****************************************************************************//** +* +* \brief Clears any active interrupts attached with the component and returns +* the value of the interrupt status register allowing determination of which +* pins generated an interrupt event. +* +* \return +* The right-shifted current value of the interrupt status register. Each pin +* has one bit set if it generated an interrupt event. For example, bit 0 is +* for pin 0 and bit 1 is for pin 1 of the Pins component. +* +* \sideeffect +* Clears all bits of the physical port's interrupt status register, not just +* those associated with the Pins component. +* +* \funcusage +* \snippet SPI_1_sclk_m_SUT.c usage_SPI_1_sclk_m_ClearInterrupt +*******************************************************************************/ +uint8 SPI_1_sclk_m_ClearInterrupt(void) +{ + uint8 maskedStatus = (uint8)(SPI_1_sclk_m_INTSTAT & SPI_1_sclk_m_MASK); + SPI_1_sclk_m_INTSTAT = maskedStatus; + return maskedStatus >> SPI_1_sclk_m_SHIFT; +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_sclk_m.h b/cores/asr650x/projects/PSoC4/SPI_1_sclk_m.h new file mode 100644 index 00000000..ae1ef35b --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_sclk_m.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* File Name: SPI_1_sclk_m.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_1_sclk_m_H) /* Pins SPI_1_sclk_m_H */ +#define CY_PINS_SPI_1_sclk_m_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "SPI_1_sclk_m_aliases.h" + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* Structure for sleep mode support */ +typedef struct +{ + uint32 pcState; /**< State of the port control register */ + uint32 sioState; /**< State of the SIO configuration */ + uint32 usbState; /**< State of the USBIO regulator */ +} SPI_1_sclk_m_BACKUP_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +uint8 SPI_1_sclk_m_Read(void); +void SPI_1_sclk_m_Write(uint8 value); +uint8 SPI_1_sclk_m_ReadDataReg(void); +#if defined(SPI_1_sclk_m__PC) || (CY_PSOC4_4200L) + void SPI_1_sclk_m_SetDriveMode(uint8 mode); +#endif +void SPI_1_sclk_m_SetInterruptMode(uint16 position, uint16 mode); +uint8 SPI_1_sclk_m_ClearInterrupt(void); +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +void SPI_1_sclk_m_Sleep(void); +void SPI_1_sclk_m_Wakeup(void); +/** @} power */ + + +/*************************************** +* API Constants +***************************************/ +#if defined(SPI_1_sclk_m__PC) || (CY_PSOC4_4200L) + /* Drive Modes */ + #define SPI_1_sclk_m_DRIVE_MODE_BITS (3) + #define SPI_1_sclk_m_DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - SPI_1_sclk_m_DRIVE_MODE_BITS)) + + /** + * \addtogroup group_constants + * @{ + */ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SPI_1_sclk_m_SetDriveMode() function. + * @{ + */ + #define SPI_1_sclk_m_DM_ALG_HIZ (0x00u) /**< \brief High Impedance Analog */ + #define SPI_1_sclk_m_DM_DIG_HIZ (0x01u) /**< \brief High Impedance Digital */ + #define SPI_1_sclk_m_DM_RES_UP (0x02u) /**< \brief Resistive Pull Up */ + #define SPI_1_sclk_m_DM_RES_DWN (0x03u) /**< \brief Resistive Pull Down */ + #define SPI_1_sclk_m_DM_OD_LO (0x04u) /**< \brief Open Drain, Drives Low */ + #define SPI_1_sclk_m_DM_OD_HI (0x05u) /**< \brief Open Drain, Drives High */ + #define SPI_1_sclk_m_DM_STRONG (0x06u) /**< \brief Strong Drive */ + #define SPI_1_sclk_m_DM_RES_UPDWN (0x07u) /**< \brief Resistive Pull Up/Down */ + /** @} driveMode */ + /** @} group_constants */ +#endif + +/* Digital Port Constants */ +#define SPI_1_sclk_m_MASK SPI_1_sclk_m__MASK +#define SPI_1_sclk_m_SHIFT SPI_1_sclk_m__SHIFT +#define SPI_1_sclk_m_WIDTH 1u + +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SPI_1_sclk_m_SetInterruptMode() function. + * @{ + */ + #define SPI_1_sclk_m_INTR_NONE ((uint16)(0x0000u)) /**< \brief Disabled */ + #define SPI_1_sclk_m_INTR_RISING ((uint16)(0x5555u)) /**< \brief Rising edge trigger */ + #define SPI_1_sclk_m_INTR_FALLING ((uint16)(0xaaaau)) /**< \brief Falling edge trigger */ + #define SPI_1_sclk_m_INTR_BOTH ((uint16)(0xffffu)) /**< \brief Both edge trigger */ + /** @} intrMode */ +/** @} group_constants */ + +/* SIO LPM definition */ +#if defined(SPI_1_sclk_m__SIO) + #define SPI_1_sclk_m_SIO_LPM_MASK (0x03u) +#endif + +/* USBIO definitions */ +#if !defined(SPI_1_sclk_m__PC) && (CY_PSOC4_4200L) + #define SPI_1_sclk_m_USBIO_ENABLE ((uint32)0x80000000u) + #define SPI_1_sclk_m_USBIO_DISABLE ((uint32)(~SPI_1_sclk_m_USBIO_ENABLE)) + #define SPI_1_sclk_m_USBIO_SUSPEND_SHIFT CYFLD_USBDEVv2_USB_SUSPEND__OFFSET + #define SPI_1_sclk_m_USBIO_SUSPEND_DEL_SHIFT CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET + #define SPI_1_sclk_m_USBIO_ENTER_SLEEP ((uint32)((1u << SPI_1_sclk_m_USBIO_SUSPEND_SHIFT) \ + | (1u << SPI_1_sclk_m_USBIO_SUSPEND_DEL_SHIFT))) + #define SPI_1_sclk_m_USBIO_EXIT_SLEEP_PH1 ((uint32)~((uint32)(1u << SPI_1_sclk_m_USBIO_SUSPEND_SHIFT))) + #define SPI_1_sclk_m_USBIO_EXIT_SLEEP_PH2 ((uint32)~((uint32)(1u << SPI_1_sclk_m_USBIO_SUSPEND_DEL_SHIFT))) + #define SPI_1_sclk_m_USBIO_CR1_OFF ((uint32)0xfffffffeu) +#endif + + +/*************************************** +* Registers +***************************************/ +/* Main Port Registers */ +#if defined(SPI_1_sclk_m__PC) + /* Port Configuration */ + #define SPI_1_sclk_m_PC (* (reg32 *) SPI_1_sclk_m__PC) +#endif +/* Pin State */ +#define SPI_1_sclk_m_PS (* (reg32 *) SPI_1_sclk_m__PS) +/* Data Register */ +#define SPI_1_sclk_m_DR (* (reg32 *) SPI_1_sclk_m__DR) +/* Input Buffer Disable Override */ +#define SPI_1_sclk_m_INP_DIS (* (reg32 *) SPI_1_sclk_m__PC2) + +/* Interrupt configuration Registers */ +#define SPI_1_sclk_m_INTCFG (* (reg32 *) SPI_1_sclk_m__INTCFG) +#define SPI_1_sclk_m_INTSTAT (* (reg32 *) SPI_1_sclk_m__INTSTAT) + +/* "Interrupt cause" register for Combined Port Interrupt (AllPortInt) in GSRef component */ +#if defined (CYREG_GPIO_INTR_CAUSE) + #define SPI_1_sclk_m_INTR_CAUSE (* (reg32 *) CYREG_GPIO_INTR_CAUSE) +#endif + +/* SIO register */ +#if defined(SPI_1_sclk_m__SIO) + #define SPI_1_sclk_m_SIO_REG (* (reg32 *) SPI_1_sclk_m__SIO) +#endif /* (SPI_1_sclk_m__SIO_CFG) */ + +/* USBIO registers */ +#if !defined(SPI_1_sclk_m__PC) && (CY_PSOC4_4200L) + #define SPI_1_sclk_m_USB_POWER_REG (* (reg32 *) CYREG_USBDEVv2_USB_POWER_CTRL) + #define SPI_1_sclk_m_CR1_REG (* (reg32 *) CYREG_USBDEVv2_CR1) + #define SPI_1_sclk_m_USBIO_CTRL_REG (* (reg32 *) CYREG_USBDEVv2_USB_USBIO_CTRL) +#endif + + +/*************************************** +* The following code is DEPRECATED and +* must not be used in new designs. +***************************************/ +/** +* \addtogroup group_deprecated +* @{ +*/ +#define SPI_1_sclk_m_DRIVE_MODE_SHIFT (0x00u) +#define SPI_1_sclk_m_DRIVE_MODE_MASK (0x07u << SPI_1_sclk_m_DRIVE_MODE_SHIFT) +/** @} deprecated */ + +#endif /* End Pins SPI_1_sclk_m_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_sclk_m_PM.c b/cores/asr650x/projects/PSoC4/SPI_1_sclk_m_PM.c new file mode 100644 index 00000000..74c365f2 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_sclk_m_PM.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: SPI_1_sclk_m.c +* Version 2.20 +* +* Description: +* This file contains APIs to set up the Pins component for low power modes. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SPI_1_sclk_m.h" + +static SPI_1_sclk_m_BACKUP_STRUCT SPI_1_sclk_m_backup = {0u, 0u, 0u}; + + +/******************************************************************************* +* Function Name: SPI_1_sclk_m_Sleep +****************************************************************************//** +* +* \brief Stores the pin configuration and prepares the pin for entering chip +* deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. +* It should not be called for GPIO or GPIO_OVT pins. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \sideeffect +* For SIO pins, this function configures the pin input threshold to CMOS and +* drive level to Vddio. This is needed for SIO pins when in device +* deep-sleep/hibernate modes. +* +* \funcusage +* \snippet SPI_1_sclk_m_SUT.c usage_SPI_1_sclk_m_Sleep_Wakeup +*******************************************************************************/ +void SPI_1_sclk_m_Sleep(void) +{ + #if defined(SPI_1_sclk_m__PC) + SPI_1_sclk_m_backup.pcState = SPI_1_sclk_m_PC; + #else + #if (CY_PSOC4_4200L) + /* Save the regulator state and put the PHY into suspend mode */ + SPI_1_sclk_m_backup.usbState = SPI_1_sclk_m_CR1_REG; + SPI_1_sclk_m_USB_POWER_REG |= SPI_1_sclk_m_USBIO_ENTER_SLEEP; + SPI_1_sclk_m_CR1_REG &= SPI_1_sclk_m_USBIO_CR1_OFF; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(SPI_1_sclk_m__SIO) + SPI_1_sclk_m_backup.sioState = SPI_1_sclk_m_SIO_REG; + /* SIO requires unregulated output buffer and single ended input buffer */ + SPI_1_sclk_m_SIO_REG &= (uint32)(~SPI_1_sclk_m_SIO_LPM_MASK); + #endif +} + + +/******************************************************************************* +* Function Name: SPI_1_sclk_m_Wakeup +****************************************************************************//** +* +* \brief Restores the pin configuration that was saved during Pin_Sleep(). This +* function applies only to SIO and USBIO pins. It should not be called for +* GPIO or GPIO_OVT pins. +* +* For USBIO pins, the wakeup is only triggered for falling edge interrupts. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \funcusage +* Refer to SPI_1_sclk_m_Sleep() for an example usage. +*******************************************************************************/ +void SPI_1_sclk_m_Wakeup(void) +{ + #if defined(SPI_1_sclk_m__PC) + SPI_1_sclk_m_PC = SPI_1_sclk_m_backup.pcState; + #else + #if (CY_PSOC4_4200L) + /* Restore the regulator state and come out of suspend mode */ + SPI_1_sclk_m_USB_POWER_REG &= SPI_1_sclk_m_USBIO_EXIT_SLEEP_PH1; + SPI_1_sclk_m_CR1_REG = SPI_1_sclk_m_backup.usbState; + SPI_1_sclk_m_USB_POWER_REG &= SPI_1_sclk_m_USBIO_EXIT_SLEEP_PH2; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(SPI_1_sclk_m__SIO) + SPI_1_sclk_m_SIO_REG = SPI_1_sclk_m_backup.sioState; + #endif +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/SPI_1_sclk_m_aliases.h b/cores/asr650x/projects/PSoC4/SPI_1_sclk_m_aliases.h new file mode 100644 index 00000000..a19486a8 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/SPI_1_sclk_m_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SPI_1_sclk_m.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_1_sclk_m_ALIASES_H) /* Pins SPI_1_sclk_m_ALIASES_H */ +#define CY_PINS_SPI_1_sclk_m_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" + + +/*************************************** +* Constants +***************************************/ +#define SPI_1_sclk_m_0 (SPI_1_sclk_m__0__PC) +#define SPI_1_sclk_m_0_PS (SPI_1_sclk_m__0__PS) +#define SPI_1_sclk_m_0_PC (SPI_1_sclk_m__0__PC) +#define SPI_1_sclk_m_0_DR (SPI_1_sclk_m__0__DR) +#define SPI_1_sclk_m_0_SHIFT (SPI_1_sclk_m__0__SHIFT) +#define SPI_1_sclk_m_0_INTR ((uint16)((uint16)0x0003u << (SPI_1_sclk_m__0__SHIFT*2u))) + +#define SPI_1_sclk_m_INTR_ALL ((uint16)(SPI_1_sclk_m_0_INTR)) + + +#endif /* End Pins SPI_1_sclk_m_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1.c b/cores/asr650x/projects/PSoC4/UART_1.c new file mode 100644 index 00000000..dfb23ded --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1.c @@ -0,0 +1,818 @@ +/***************************************************************************//** +* \file UART_1.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_1_PVT.h" + +#if (UART_1_SCB_MODE_I2C_INC) + #include "UART_1_I2C_PVT.h" +#endif /* (UART_1_SCB_MODE_I2C_INC) */ + +#if (UART_1_SCB_MODE_EZI2C_INC) + #include "UART_1_EZI2C_PVT.h" +#endif /* (UART_1_SCB_MODE_EZI2C_INC) */ + +#if (UART_1_SCB_MODE_SPI_INC || UART_1_SCB_MODE_UART_INC) + #include "UART_1_SPI_UART_PVT.h" +#endif /* (UART_1_SCB_MODE_SPI_INC || UART_1_SCB_MODE_UART_INC) */ + + +/*************************************** +* Run Time Configuration Vars +***************************************/ + +/* Stores internal component configuration for Unconfigured mode */ +#if (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + /* Common configuration variables */ + uint8 UART_1_scbMode = UART_1_SCB_MODE_UNCONFIG; + uint8 UART_1_scbEnableWake; + uint8 UART_1_scbEnableIntr; + + /* I2C configuration variables */ + uint8 UART_1_mode; + uint8 UART_1_acceptAddr; + + /* SPI/UART configuration variables */ + volatile uint8 * UART_1_rxBuffer; + uint8 UART_1_rxDataBits; + uint32 UART_1_rxBufferSize; + + volatile uint8 * UART_1_txBuffer; + uint8 UART_1_txDataBits; + uint32 UART_1_txBufferSize; + + /* EZI2C configuration variables */ + uint8 UART_1_numberOfAddr; + uint8 UART_1_subAddrSize; +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Common SCB Vars +***************************************/ +/** +* \addtogroup group_general +* \{ +*/ + +/** UART_1_initVar indicates whether the UART_1 +* component has been initialized. The variable is initialized to 0 +* and set to 1 the first time SCB_Start() is called. This allows +* the component to restart without reinitialization after the first +* call to the UART_1_Start() routine. +* +* If re-initialization of the component is required, then the +* UART_1_Init() function can be called before the +* UART_1_Start() or UART_1_Enable() function. +*/ +uint8 UART_1_initVar = 0u; + + +#if (! (UART_1_SCB_MODE_I2C_CONST_CFG || \ + UART_1_SCB_MODE_EZI2C_CONST_CFG)) + /** This global variable stores TX interrupt sources after + * UART_1_Stop() is called. Only these TX interrupt sources + * will be restored on a subsequent UART_1_Enable() call. + */ + uint16 UART_1_IntrTxMask = 0u; +#endif /* (! (UART_1_SCB_MODE_I2C_CONST_CFG || \ + UART_1_SCB_MODE_EZI2C_CONST_CFG)) */ +/** \} globals */ + +#if (UART_1_SCB_IRQ_INTERNAL) +#if !defined (CY_REMOVE_UART_1_CUSTOM_INTR_HANDLER) + void (*UART_1_customIntrHandler)(void) = NULL; +#endif /* !defined (CY_REMOVE_UART_1_CUSTOM_INTR_HANDLER) */ +#endif /* (UART_1_SCB_IRQ_INTERNAL) */ + + +/*************************************** +* Private Function Prototypes +***************************************/ + +static void UART_1_ScbEnableIntr(void); +static void UART_1_ScbModeStop(void); +static void UART_1_ScbModePostEnable(void); + + +/******************************************************************************* +* Function Name: UART_1_Init +****************************************************************************//** +* +* Initializes the UART_1 component to operate in one of the selected +* configurations: I2C, SPI, UART or EZI2C. +* When the configuration is set to "Unconfigured SCB", this function does +* not do any initialization. Use mode-specific initialization APIs instead: +* UART_1_I2CInit, UART_1_SpiInit, +* UART_1_UartInit or UART_1_EzI2CInit. +* +*******************************************************************************/ +void UART_1_Init(void) +{ +#if (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + if (UART_1_SCB_MODE_UNCONFIG_RUNTM_CFG) + { + UART_1_initVar = 0u; + } + else + { + /* Initialization was done before this function call */ + } + +#elif (UART_1_SCB_MODE_I2C_CONST_CFG) + UART_1_I2CInit(); + +#elif (UART_1_SCB_MODE_SPI_CONST_CFG) + UART_1_SpiInit(); + +#elif (UART_1_SCB_MODE_UART_CONST_CFG) + UART_1_UartInit(); + +#elif (UART_1_SCB_MODE_EZI2C_CONST_CFG) + UART_1_EzI2CInit(); + +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_1_Enable +****************************************************************************//** +* +* Enables UART_1 component operation: activates the hardware and +* internal interrupt. It also restores TX interrupt sources disabled after the +* UART_1_Stop() function was called (note that level-triggered TX +* interrupt sources remain disabled to not cause code lock-up). +* For I2C and EZI2C modes the interrupt is internal and mandatory for +* operation. For SPI and UART modes the interrupt can be configured as none, +* internal or external. +* The UART_1 configuration should be not changed when the component +* is enabled. Any configuration changes should be made after disabling the +* component. +* When configuration is set to 鈥淯nconfigured UART_1鈥, the component +* must first be initialized to operate in one of the following configurations: +* I2C, SPI, UART or EZ I2C, using the mode-specific initialization API. +* Otherwise this function does not enable the component. +* +*******************************************************************************/ +void UART_1_Enable(void) +{ +#if (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + /* Enable SCB block, only if it is already configured */ + if (!UART_1_SCB_MODE_UNCONFIG_RUNTM_CFG) + { + UART_1_CTRL_REG |= UART_1_CTRL_ENABLED; + + UART_1_ScbEnableIntr(); + + /* Call PostEnable function specific to current operation mode */ + UART_1_ScbModePostEnable(); + } +#else + UART_1_CTRL_REG |= UART_1_CTRL_ENABLED; + + UART_1_ScbEnableIntr(); + + /* Call PostEnable function specific to current operation mode */ + UART_1_ScbModePostEnable(); +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_1_Start +****************************************************************************//** +* +* Invokes UART_1_Init() and UART_1_Enable(). +* After this function call, the component is enabled and ready for operation. +* When configuration is set to "Unconfigured SCB", the component must first be +* initialized to operate in one of the following configurations: I2C, SPI, UART +* or EZI2C. Otherwise this function does not enable the component. +* +* \globalvars +* UART_1_initVar - used to check initial configuration, modified +* on first function call. +* +*******************************************************************************/ +void UART_1_Start(void) +{ + if (0u == UART_1_initVar) + { + UART_1_Init(); + UART_1_initVar = 1u; /* Component was initialized */ + } + + UART_1_Enable(); +} + + +/******************************************************************************* +* Function Name: UART_1_Stop +****************************************************************************//** +* +* Disables the UART_1 component: disable the hardware and internal +* interrupt. It also disables all TX interrupt sources so as not to cause an +* unexpected interrupt trigger because after the component is enabled, the +* TX FIFO is empty. +* Refer to the function UART_1_Enable() for the interrupt +* configuration details. +* This function disables the SCB component without checking to see if +* communication is in progress. Before calling this function it may be +* necessary to check the status of communication to make sure communication +* is complete. If this is not done then communication could be stopped mid +* byte and corrupted data could result. +* +*******************************************************************************/ +void UART_1_Stop(void) +{ +#if (UART_1_SCB_IRQ_INTERNAL) + UART_1_DisableInt(); +#endif /* (UART_1_SCB_IRQ_INTERNAL) */ + + /* Call Stop function specific to current operation mode */ + UART_1_ScbModeStop(); + + /* Disable SCB IP */ + UART_1_CTRL_REG &= (uint32) ~UART_1_CTRL_ENABLED; + + /* Disable all TX interrupt sources so as not to cause an unexpected + * interrupt trigger after the component will be enabled because the + * TX FIFO is empty. + * For SCB IP v0, it is critical as it does not mask-out interrupt + * sources when it is disabled. This can cause a code lock-up in the + * interrupt handler because TX FIFO cannot be loaded after the block + * is disabled. + */ + UART_1_SetTxInterruptMode(UART_1_NO_INTR_SOURCES); + +#if (UART_1_SCB_IRQ_INTERNAL) + UART_1_ClearPendingInt(); +#endif /* (UART_1_SCB_IRQ_INTERNAL) */ +} + + +/******************************************************************************* +* Function Name: UART_1_SetRxFifoLevel +****************************************************************************//** +* +* Sets level in the RX FIFO to generate a RX level interrupt. +* When the RX FIFO has more entries than the RX FIFO level an RX level +* interrupt request is generated. +* +* \param level: Level in the RX FIFO to generate RX level interrupt. +* The range of valid level values is between 0 and RX FIFO depth - 1. +* +*******************************************************************************/ +void UART_1_SetRxFifoLevel(uint32 level) +{ + uint32 rxFifoCtrl; + + rxFifoCtrl = UART_1_RX_FIFO_CTRL_REG; + + rxFifoCtrl &= ((uint32) ~UART_1_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + rxFifoCtrl |= ((uint32) (UART_1_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK & level)); + + UART_1_RX_FIFO_CTRL_REG = rxFifoCtrl; +} + + +/******************************************************************************* +* Function Name: UART_1_SetTxFifoLevel +****************************************************************************//** +* +* Sets level in the TX FIFO to generate a TX level interrupt. +* When the TX FIFO has less entries than the TX FIFO level an TX level +* interrupt request is generated. +* +* \param level: Level in the TX FIFO to generate TX level interrupt. +* The range of valid level values is between 0 and TX FIFO depth - 1. +* +*******************************************************************************/ +void UART_1_SetTxFifoLevel(uint32 level) +{ + uint32 txFifoCtrl; + + txFifoCtrl = UART_1_TX_FIFO_CTRL_REG; + + txFifoCtrl &= ((uint32) ~UART_1_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + txFifoCtrl |= ((uint32) (UART_1_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK & level)); + + UART_1_TX_FIFO_CTRL_REG = txFifoCtrl; +} + + +#if (UART_1_SCB_IRQ_INTERNAL) + /******************************************************************************* + * Function Name: UART_1_SetCustomInterruptHandler + ****************************************************************************//** + * + * Registers a function to be called by the internal interrupt handler. + * First the function that is registered is called, then the internal interrupt + * handler performs any operation such as software buffer management functions + * before the interrupt returns. It is the user's responsibility not to break + * the software buffer operations. Only one custom handler is supported, which + * is the function provided by the most recent call. + * At the initialization time no custom handler is registered. + * + * \param func: Pointer to the function to register. + * The value NULL indicates to remove the current custom interrupt + * handler. + * + *******************************************************************************/ + void UART_1_SetCustomInterruptHandler(void (*func)(void)) + { + #if !defined (CY_REMOVE_UART_1_CUSTOM_INTR_HANDLER) + UART_1_customIntrHandler = func; /* Register interrupt handler */ + #else + if (NULL != func) + { + /* Suppress compiler warning */ + } + #endif /* !defined (CY_REMOVE_UART_1_CUSTOM_INTR_HANDLER) */ + } +#endif /* (UART_1_SCB_IRQ_INTERNAL) */ + + +/******************************************************************************* +* Function Name: UART_1_ScbModeEnableIntr +****************************************************************************//** +* +* Enables an interrupt for a specific mode. +* +*******************************************************************************/ +static void UART_1_ScbEnableIntr(void) +{ +#if (UART_1_SCB_IRQ_INTERNAL) + /* Enable interrupt in NVIC */ + #if (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + if (0u != UART_1_scbEnableIntr) + { + UART_1_EnableInt(); + } + + #else + UART_1_EnableInt(); + + #endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +#endif /* (UART_1_SCB_IRQ_INTERNAL) */ +} + + +/******************************************************************************* +* Function Name: UART_1_ScbModePostEnable +****************************************************************************//** +* +* Calls the PostEnable function for a specific operation mode. +* +*******************************************************************************/ +static void UART_1_ScbModePostEnable(void) +{ +#if (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) +#if (!UART_1_CY_SCBIP_V1) + if (UART_1_SCB_MODE_SPI_RUNTM_CFG) + { + UART_1_SpiPostEnable(); + } + else if (UART_1_SCB_MODE_UART_RUNTM_CFG) + { + UART_1_UartPostEnable(); + } + else + { + /* Unknown mode: do nothing */ + } +#endif /* (!UART_1_CY_SCBIP_V1) */ + +#elif (UART_1_SCB_MODE_SPI_CONST_CFG) + UART_1_SpiPostEnable(); + +#elif (UART_1_SCB_MODE_UART_CONST_CFG) + UART_1_UartPostEnable(); + +#else + /* Unknown mode: do nothing */ +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_1_ScbModeStop +****************************************************************************//** +* +* Calls the Stop function for a specific operation mode. +* +*******************************************************************************/ +static void UART_1_ScbModeStop(void) +{ +#if (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + if (UART_1_SCB_MODE_I2C_RUNTM_CFG) + { + UART_1_I2CStop(); + } + else if (UART_1_SCB_MODE_EZI2C_RUNTM_CFG) + { + UART_1_EzI2CStop(); + } +#if (!UART_1_CY_SCBIP_V1) + else if (UART_1_SCB_MODE_SPI_RUNTM_CFG) + { + UART_1_SpiStop(); + } + else if (UART_1_SCB_MODE_UART_RUNTM_CFG) + { + UART_1_UartStop(); + } +#endif /* (!UART_1_CY_SCBIP_V1) */ + else + { + /* Unknown mode: do nothing */ + } +#elif (UART_1_SCB_MODE_I2C_CONST_CFG) + UART_1_I2CStop(); + +#elif (UART_1_SCB_MODE_EZI2C_CONST_CFG) + UART_1_EzI2CStop(); + +#elif (UART_1_SCB_MODE_SPI_CONST_CFG) + UART_1_SpiStop(); + +#elif (UART_1_SCB_MODE_UART_CONST_CFG) + UART_1_UartStop(); + +#else + /* Unknown mode: do nothing */ +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +#if (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + /******************************************************************************* + * Function Name: UART_1_SetPins + ****************************************************************************//** + * + * Sets the pins settings accordingly to the selected operation mode. + * Only available in the Unconfigured operation mode. The mode specific + * initialization function calls it. + * Pins configuration is set by PSoC Creator when a specific mode of operation + * is selected in design time. + * + * \param mode: Mode of SCB operation. + * \param subMode: Sub-mode of SCB operation. It is only required for SPI and UART + * modes. + * \param uartEnableMask: enables TX or RX direction and RTS and CTS signals. + * + *******************************************************************************/ + void UART_1_SetPins(uint32 mode, uint32 subMode, uint32 uartEnableMask) + { + uint32 pinsDm[UART_1_SCB_PINS_NUMBER]; + uint32 i; + + #if (!UART_1_CY_SCBIP_V1) + uint32 pinsInBuf = 0u; + #endif /* (!UART_1_CY_SCBIP_V1) */ + + uint32 hsiomSel[UART_1_SCB_PINS_NUMBER] = + { + UART_1_RX_SCL_MOSI_HSIOM_SEL_GPIO, + UART_1_TX_SDA_MISO_HSIOM_SEL_GPIO, + 0u, + 0u, + 0u, + 0u, + 0u, + }; + + #if (UART_1_CY_SCBIP_V1) + /* Supress compiler warning. */ + if ((0u == subMode) || (0u == uartEnableMask)) + { + } + #endif /* (UART_1_CY_SCBIP_V1) */ + + /* Set default HSIOM to GPIO and Drive Mode to Analog Hi-Z */ + for (i = 0u; i < UART_1_SCB_PINS_NUMBER; i++) + { + pinsDm[i] = UART_1_PIN_DM_ALG_HIZ; + } + + if ((UART_1_SCB_MODE_I2C == mode) || + (UART_1_SCB_MODE_EZI2C == mode)) + { + #if (UART_1_RX_SCL_MOSI_PIN) + hsiomSel[UART_1_RX_SCL_MOSI_PIN_INDEX] = UART_1_RX_SCL_MOSI_HSIOM_SEL_I2C; + pinsDm [UART_1_RX_SCL_MOSI_PIN_INDEX] = UART_1_PIN_DM_OD_LO; + #elif (UART_1_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[UART_1_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_1_RX_WAKE_SCL_MOSI_HSIOM_SEL_I2C; + pinsDm [UART_1_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_1_PIN_DM_OD_LO; + #else + #endif /* (UART_1_RX_SCL_MOSI_PIN) */ + + #if (UART_1_TX_SDA_MISO_PIN) + hsiomSel[UART_1_TX_SDA_MISO_PIN_INDEX] = UART_1_TX_SDA_MISO_HSIOM_SEL_I2C; + pinsDm [UART_1_TX_SDA_MISO_PIN_INDEX] = UART_1_PIN_DM_OD_LO; + #endif /* (UART_1_TX_SDA_MISO_PIN) */ + } + #if (!UART_1_CY_SCBIP_V1) + else if (UART_1_SCB_MODE_SPI == mode) + { + #if (UART_1_RX_SCL_MOSI_PIN) + hsiomSel[UART_1_RX_SCL_MOSI_PIN_INDEX] = UART_1_RX_SCL_MOSI_HSIOM_SEL_SPI; + #elif (UART_1_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[UART_1_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_1_RX_WAKE_SCL_MOSI_HSIOM_SEL_SPI; + #else + #endif /* (UART_1_RX_SCL_MOSI_PIN) */ + + #if (UART_1_TX_SDA_MISO_PIN) + hsiomSel[UART_1_TX_SDA_MISO_PIN_INDEX] = UART_1_TX_SDA_MISO_HSIOM_SEL_SPI; + #endif /* (UART_1_TX_SDA_MISO_PIN) */ + + #if (UART_1_CTS_SCLK_PIN) + hsiomSel[UART_1_CTS_SCLK_PIN_INDEX] = UART_1_CTS_SCLK_HSIOM_SEL_SPI; + #endif /* (UART_1_CTS_SCLK_PIN) */ + + if (UART_1_SPI_SLAVE == subMode) + { + /* Slave */ + pinsDm[UART_1_RX_SCL_MOSI_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; + pinsDm[UART_1_TX_SDA_MISO_PIN_INDEX] = UART_1_PIN_DM_STRONG; + pinsDm[UART_1_CTS_SCLK_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; + + #if (UART_1_RTS_SS0_PIN) + /* Only SS0 is valid choice for Slave */ + hsiomSel[UART_1_RTS_SS0_PIN_INDEX] = UART_1_RTS_SS0_HSIOM_SEL_SPI; + pinsDm [UART_1_RTS_SS0_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; + #endif /* (UART_1_RTS_SS0_PIN) */ + + #if (UART_1_TX_SDA_MISO_PIN) + /* Disable input buffer */ + pinsInBuf |= UART_1_TX_SDA_MISO_PIN_MASK; + #endif /* (UART_1_TX_SDA_MISO_PIN) */ + } + else + { + /* (Master) */ + pinsDm[UART_1_RX_SCL_MOSI_PIN_INDEX] = UART_1_PIN_DM_STRONG; + pinsDm[UART_1_TX_SDA_MISO_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; + pinsDm[UART_1_CTS_SCLK_PIN_INDEX] = UART_1_PIN_DM_STRONG; + + #if (UART_1_RTS_SS0_PIN) + hsiomSel [UART_1_RTS_SS0_PIN_INDEX] = UART_1_RTS_SS0_HSIOM_SEL_SPI; + pinsDm [UART_1_RTS_SS0_PIN_INDEX] = UART_1_PIN_DM_STRONG; + pinsInBuf |= UART_1_RTS_SS0_PIN_MASK; + #endif /* (UART_1_RTS_SS0_PIN) */ + + #if (UART_1_SS1_PIN) + hsiomSel [UART_1_SS1_PIN_INDEX] = UART_1_SS1_HSIOM_SEL_SPI; + pinsDm [UART_1_SS1_PIN_INDEX] = UART_1_PIN_DM_STRONG; + pinsInBuf |= UART_1_SS1_PIN_MASK; + #endif /* (UART_1_SS1_PIN) */ + + #if (UART_1_SS2_PIN) + hsiomSel [UART_1_SS2_PIN_INDEX] = UART_1_SS2_HSIOM_SEL_SPI; + pinsDm [UART_1_SS2_PIN_INDEX] = UART_1_PIN_DM_STRONG; + pinsInBuf |= UART_1_SS2_PIN_MASK; + #endif /* (UART_1_SS2_PIN) */ + + #if (UART_1_SS3_PIN) + hsiomSel [UART_1_SS3_PIN_INDEX] = UART_1_SS3_HSIOM_SEL_SPI; + pinsDm [UART_1_SS3_PIN_INDEX] = UART_1_PIN_DM_STRONG; + pinsInBuf |= UART_1_SS3_PIN_MASK; + #endif /* (UART_1_SS3_PIN) */ + + /* Disable input buffers */ + #if (UART_1_RX_SCL_MOSI_PIN) + pinsInBuf |= UART_1_RX_SCL_MOSI_PIN_MASK; + #elif (UART_1_RX_WAKE_SCL_MOSI_PIN) + pinsInBuf |= UART_1_RX_WAKE_SCL_MOSI_PIN_MASK; + #else + #endif /* (UART_1_RX_SCL_MOSI_PIN) */ + + #if (UART_1_CTS_SCLK_PIN) + pinsInBuf |= UART_1_CTS_SCLK_PIN_MASK; + #endif /* (UART_1_CTS_SCLK_PIN) */ + } + } + else /* UART */ + { + if (UART_1_UART_MODE_SMARTCARD == subMode) + { + /* SmartCard */ + #if (UART_1_TX_SDA_MISO_PIN) + hsiomSel[UART_1_TX_SDA_MISO_PIN_INDEX] = UART_1_TX_SDA_MISO_HSIOM_SEL_UART; + pinsDm [UART_1_TX_SDA_MISO_PIN_INDEX] = UART_1_PIN_DM_OD_LO; + #endif /* (UART_1_TX_SDA_MISO_PIN) */ + } + else /* Standard or IrDA */ + { + if (0u != (UART_1_UART_RX_PIN_ENABLE & uartEnableMask)) + { + #if (UART_1_RX_SCL_MOSI_PIN) + hsiomSel[UART_1_RX_SCL_MOSI_PIN_INDEX] = UART_1_RX_SCL_MOSI_HSIOM_SEL_UART; + pinsDm [UART_1_RX_SCL_MOSI_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; + #elif (UART_1_RX_WAKE_SCL_MOSI_PIN) + hsiomSel[UART_1_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_1_RX_WAKE_SCL_MOSI_HSIOM_SEL_UART; + pinsDm [UART_1_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; + #else + #endif /* (UART_1_RX_SCL_MOSI_PIN) */ + } + + if (0u != (UART_1_UART_TX_PIN_ENABLE & uartEnableMask)) + { + #if (UART_1_TX_SDA_MISO_PIN) + hsiomSel[UART_1_TX_SDA_MISO_PIN_INDEX] = UART_1_TX_SDA_MISO_HSIOM_SEL_UART; + pinsDm [UART_1_TX_SDA_MISO_PIN_INDEX] = UART_1_PIN_DM_STRONG; + + /* Disable input buffer */ + pinsInBuf |= UART_1_TX_SDA_MISO_PIN_MASK; + #endif /* (UART_1_TX_SDA_MISO_PIN) */ + } + + #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + if (UART_1_UART_MODE_STD == subMode) + { + if (0u != (UART_1_UART_CTS_PIN_ENABLE & uartEnableMask)) + { + /* CTS input is multiplexed with SCLK */ + #if (UART_1_CTS_SCLK_PIN) + hsiomSel[UART_1_CTS_SCLK_PIN_INDEX] = UART_1_CTS_SCLK_HSIOM_SEL_UART; + pinsDm [UART_1_CTS_SCLK_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; + #endif /* (UART_1_CTS_SCLK_PIN) */ + } + + if (0u != (UART_1_UART_RTS_PIN_ENABLE & uartEnableMask)) + { + /* RTS output is multiplexed with SS0 */ + #if (UART_1_RTS_SS0_PIN) + hsiomSel[UART_1_RTS_SS0_PIN_INDEX] = UART_1_RTS_SS0_HSIOM_SEL_UART; + pinsDm [UART_1_RTS_SS0_PIN_INDEX] = UART_1_PIN_DM_STRONG; + + /* Disable input buffer */ + pinsInBuf |= UART_1_RTS_SS0_PIN_MASK; + #endif /* (UART_1_RTS_SS0_PIN) */ + } + } + #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + } + } + #endif /* (!UART_1_CY_SCBIP_V1) */ + + /* Configure pins: set HSIOM, DM and InputBufEnable */ + /* Note: the DR register settings do not effect the pin output if HSIOM is other than GPIO */ + + #if (UART_1_RX_SCL_MOSI_PIN) + UART_1_SET_HSIOM_SEL(UART_1_RX_SCL_MOSI_HSIOM_REG, + UART_1_RX_SCL_MOSI_HSIOM_MASK, + UART_1_RX_SCL_MOSI_HSIOM_POS, + hsiomSel[UART_1_RX_SCL_MOSI_PIN_INDEX]); + + UART_1_uart_rx_i2c_scl_spi_mosi_SetDriveMode((uint8) pinsDm[UART_1_RX_SCL_MOSI_PIN_INDEX]); + + #if (!UART_1_CY_SCBIP_V1) + UART_1_SET_INP_DIS(UART_1_uart_rx_i2c_scl_spi_mosi_INP_DIS, + UART_1_uart_rx_i2c_scl_spi_mosi_MASK, + (0u != (pinsInBuf & UART_1_RX_SCL_MOSI_PIN_MASK))); + #endif /* (!UART_1_CY_SCBIP_V1) */ + + #elif (UART_1_RX_WAKE_SCL_MOSI_PIN) + UART_1_SET_HSIOM_SEL(UART_1_RX_WAKE_SCL_MOSI_HSIOM_REG, + UART_1_RX_WAKE_SCL_MOSI_HSIOM_MASK, + UART_1_RX_WAKE_SCL_MOSI_HSIOM_POS, + hsiomSel[UART_1_RX_WAKE_SCL_MOSI_PIN_INDEX]); + + UART_1_uart_rx_wake_i2c_scl_spi_mosi_SetDriveMode((uint8) + pinsDm[UART_1_RX_WAKE_SCL_MOSI_PIN_INDEX]); + + UART_1_SET_INP_DIS(UART_1_uart_rx_wake_i2c_scl_spi_mosi_INP_DIS, + UART_1_uart_rx_wake_i2c_scl_spi_mosi_MASK, + (0u != (pinsInBuf & UART_1_RX_WAKE_SCL_MOSI_PIN_MASK))); + + /* Set interrupt on falling edge */ + UART_1_SET_INCFG_TYPE(UART_1_RX_WAKE_SCL_MOSI_INTCFG_REG, + UART_1_RX_WAKE_SCL_MOSI_INTCFG_TYPE_MASK, + UART_1_RX_WAKE_SCL_MOSI_INTCFG_TYPE_POS, + UART_1_INTCFG_TYPE_FALLING_EDGE); + #else + #endif /* (UART_1_RX_WAKE_SCL_MOSI_PIN) */ + + #if (UART_1_TX_SDA_MISO_PIN) + UART_1_SET_HSIOM_SEL(UART_1_TX_SDA_MISO_HSIOM_REG, + UART_1_TX_SDA_MISO_HSIOM_MASK, + UART_1_TX_SDA_MISO_HSIOM_POS, + hsiomSel[UART_1_TX_SDA_MISO_PIN_INDEX]); + + UART_1_uart_tx_i2c_sda_spi_miso_SetDriveMode((uint8) pinsDm[UART_1_TX_SDA_MISO_PIN_INDEX]); + + #if (!UART_1_CY_SCBIP_V1) + UART_1_SET_INP_DIS(UART_1_uart_tx_i2c_sda_spi_miso_INP_DIS, + UART_1_uart_tx_i2c_sda_spi_miso_MASK, + (0u != (pinsInBuf & UART_1_TX_SDA_MISO_PIN_MASK))); + #endif /* (!UART_1_CY_SCBIP_V1) */ + #endif /* (UART_1_RX_SCL_MOSI_PIN) */ + + #if (UART_1_CTS_SCLK_PIN) + UART_1_SET_HSIOM_SEL(UART_1_CTS_SCLK_HSIOM_REG, + UART_1_CTS_SCLK_HSIOM_MASK, + UART_1_CTS_SCLK_HSIOM_POS, + hsiomSel[UART_1_CTS_SCLK_PIN_INDEX]); + + UART_1_uart_cts_spi_sclk_SetDriveMode((uint8) pinsDm[UART_1_CTS_SCLK_PIN_INDEX]); + + UART_1_SET_INP_DIS(UART_1_uart_cts_spi_sclk_INP_DIS, + UART_1_uart_cts_spi_sclk_MASK, + (0u != (pinsInBuf & UART_1_CTS_SCLK_PIN_MASK))); + #endif /* (UART_1_CTS_SCLK_PIN) */ + + #if (UART_1_RTS_SS0_PIN) + UART_1_SET_HSIOM_SEL(UART_1_RTS_SS0_HSIOM_REG, + UART_1_RTS_SS0_HSIOM_MASK, + UART_1_RTS_SS0_HSIOM_POS, + hsiomSel[UART_1_RTS_SS0_PIN_INDEX]); + + UART_1_uart_rts_spi_ss0_SetDriveMode((uint8) pinsDm[UART_1_RTS_SS0_PIN_INDEX]); + + UART_1_SET_INP_DIS(UART_1_uart_rts_spi_ss0_INP_DIS, + UART_1_uart_rts_spi_ss0_MASK, + (0u != (pinsInBuf & UART_1_RTS_SS0_PIN_MASK))); + #endif /* (UART_1_RTS_SS0_PIN) */ + + #if (UART_1_SS1_PIN) + UART_1_SET_HSIOM_SEL(UART_1_SS1_HSIOM_REG, + UART_1_SS1_HSIOM_MASK, + UART_1_SS1_HSIOM_POS, + hsiomSel[UART_1_SS1_PIN_INDEX]); + + UART_1_spi_ss1_SetDriveMode((uint8) pinsDm[UART_1_SS1_PIN_INDEX]); + + UART_1_SET_INP_DIS(UART_1_spi_ss1_INP_DIS, + UART_1_spi_ss1_MASK, + (0u != (pinsInBuf & UART_1_SS1_PIN_MASK))); + #endif /* (UART_1_SS1_PIN) */ + + #if (UART_1_SS2_PIN) + UART_1_SET_HSIOM_SEL(UART_1_SS2_HSIOM_REG, + UART_1_SS2_HSIOM_MASK, + UART_1_SS2_HSIOM_POS, + hsiomSel[UART_1_SS2_PIN_INDEX]); + + UART_1_spi_ss2_SetDriveMode((uint8) pinsDm[UART_1_SS2_PIN_INDEX]); + + UART_1_SET_INP_DIS(UART_1_spi_ss2_INP_DIS, + UART_1_spi_ss2_MASK, + (0u != (pinsInBuf & UART_1_SS2_PIN_MASK))); + #endif /* (UART_1_SS2_PIN) */ + + #if (UART_1_SS3_PIN) + UART_1_SET_HSIOM_SEL(UART_1_SS3_HSIOM_REG, + UART_1_SS3_HSIOM_MASK, + UART_1_SS3_HSIOM_POS, + hsiomSel[UART_1_SS3_PIN_INDEX]); + + UART_1_spi_ss3_SetDriveMode((uint8) pinsDm[UART_1_SS3_PIN_INDEX]); + + UART_1_SET_INP_DIS(UART_1_spi_ss3_INP_DIS, + UART_1_spi_ss3_MASK, + (0u != (pinsInBuf & UART_1_SS3_PIN_MASK))); + #endif /* (UART_1_SS3_PIN) */ + } + +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +#if (UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + /******************************************************************************* + * Function Name: UART_1_I2CSlaveNackGeneration + ****************************************************************************//** + * + * Sets command to generate NACK to the address or data. + * + *******************************************************************************/ + void UART_1_I2CSlaveNackGeneration(void) + { + /* Check for EC_AM toggle condition: EC_AM and clock stretching for address are enabled */ + if ((0u != (UART_1_CTRL_REG & UART_1_CTRL_EC_AM_MODE)) && + (0u == (UART_1_I2C_CTRL_REG & UART_1_I2C_CTRL_S_NOT_READY_ADDR_NACK))) + { + /* Toggle EC_AM before NACK generation */ + UART_1_CTRL_REG &= ~UART_1_CTRL_EC_AM_MODE; + UART_1_CTRL_REG |= UART_1_CTRL_EC_AM_MODE; + } + + UART_1_I2C_SLAVE_CMD_REG = UART_1_I2C_SLAVE_CMD_S_NACK; + } +#endif /* (UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1.h b/cores/asr650x/projects/PSoC4/UART_1.h new file mode 100644 index 00000000..430dafa1 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1.h @@ -0,0 +1,2136 @@ +/***************************************************************************//** +* \file UART_1.h +* \version 4.0 +* +* \brief +* This file provides constants and parameter values for the SCB Component. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + + + +#if !defined(CY_SCB_UART_1_H) +#define CY_SCB_UART_1_H + +#include +#include +#include +#include + +/* SCB IP block v0 is available in PSoC 4100/PSoC 4200 */ +#define UART_1_CY_SCBIP_V0 (CYIPBLOCK_m0s8scb_VERSION == 0u) +/* SCB IP block v1 is available in PSoC 4000 */ +#define UART_1_CY_SCBIP_V1 (CYIPBLOCK_m0s8scb_VERSION == 1u) +/* SCB IP block v2 is available in all other devices */ +#define UART_1_CY_SCBIP_V2 (CYIPBLOCK_m0s8scb_VERSION >= 2u) + +/** Component version major.minor */ +#define UART_1_COMP_VERSION_MAJOR (4) +#define UART_1_COMP_VERSION_MINOR (0) + +#define UART_1_SCB_MODE (4u) + +/* SCB modes enum */ +#define UART_1_SCB_MODE_I2C (0x01u) +#define UART_1_SCB_MODE_SPI (0x02u) +#define UART_1_SCB_MODE_UART (0x04u) +#define UART_1_SCB_MODE_EZI2C (0x08u) +#define UART_1_SCB_MODE_UNCONFIG (0xFFu) + +/* Condition compilation depends on operation mode: Unconfigured implies apply to all modes */ +#define UART_1_SCB_MODE_I2C_CONST_CFG (UART_1_SCB_MODE_I2C == UART_1_SCB_MODE) +#define UART_1_SCB_MODE_SPI_CONST_CFG (UART_1_SCB_MODE_SPI == UART_1_SCB_MODE) +#define UART_1_SCB_MODE_UART_CONST_CFG (UART_1_SCB_MODE_UART == UART_1_SCB_MODE) +#define UART_1_SCB_MODE_EZI2C_CONST_CFG (UART_1_SCB_MODE_EZI2C == UART_1_SCB_MODE) +#define UART_1_SCB_MODE_UNCONFIG_CONST_CFG (UART_1_SCB_MODE_UNCONFIG == UART_1_SCB_MODE) + +/* Condition compilation for includes */ +#define UART_1_SCB_MODE_I2C_INC (0u !=(UART_1_SCB_MODE_I2C & UART_1_SCB_MODE)) +#define UART_1_SCB_MODE_EZI2C_INC (0u !=(UART_1_SCB_MODE_EZI2C & UART_1_SCB_MODE)) +#if (!UART_1_CY_SCBIP_V1) + #define UART_1_SCB_MODE_SPI_INC (0u !=(UART_1_SCB_MODE_SPI & UART_1_SCB_MODE)) + #define UART_1_SCB_MODE_UART_INC (0u !=(UART_1_SCB_MODE_UART & UART_1_SCB_MODE)) +#else + #define UART_1_SCB_MODE_SPI_INC (0u) + #define UART_1_SCB_MODE_UART_INC (0u) +#endif /* (!UART_1_CY_SCBIP_V1) */ + +/* Interrupts remove options */ +#define UART_1_REMOVE_SCB_IRQ (0u) +#define UART_1_SCB_IRQ_INTERNAL (0u == UART_1_REMOVE_SCB_IRQ) + +#define UART_1_REMOVE_UART_RX_WAKEUP_IRQ (0u) +#define UART_1_UART_RX_WAKEUP_IRQ (0u == UART_1_REMOVE_UART_RX_WAKEUP_IRQ) + +/* SCB interrupt enum */ +#define UART_1_SCB_INTR_MODE_NONE (0u) +#define UART_1_SCB_INTR_MODE_INTERNAL (1u) +#define UART_1_SCB_INTR_MODE_EXTERNAL (2u) + +/* Internal clock remove option */ +#define UART_1_REMOVE_SCB_CLK (0u) +#define UART_1_SCB_CLK_INTERNAL (0u == UART_1_REMOVE_SCB_CLK) + + +/*************************************** +* Includes +****************************************/ + +#include "UART_1_PINS.h" + +#if (UART_1_SCB_CLK_INTERNAL) + #include "UART_1_SCBCLK.h" +#endif /* (UART_1_SCB_CLK_INTERNAL) */ + + +/*************************************** +* Type Definitions +***************************************/ + +typedef struct +{ + uint8 enableState; +} UART_1_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ + +/* Start and Stop APIs */ +void UART_1_Init(void); +void UART_1_Enable(void); +void UART_1_Start(void); +void UART_1_Stop(void); + +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +/* Sleep and Wakeup APis */ +void UART_1_Sleep(void); +void UART_1_Wakeup(void); +/** @} power */ + +/** +* \addtogroup group_interrupt +* @{ +*/ +#if (UART_1_SCB_IRQ_INTERNAL) + /* Custom interrupt handler */ + void UART_1_SetCustomInterruptHandler(void (*func)(void)); +#endif /* (UART_1_SCB_IRQ_INTERNAL) */ +/** @} interrupt */ + +/* Interface to internal interrupt component */ +#if (UART_1_SCB_IRQ_INTERNAL) + /** + * \addtogroup group_interrupt + * @{ + */ + /******************************************************************************* + * Function Name: UART_1_EnableInt + ****************************************************************************//** + * + * When using an Internal interrupt, this enables the interrupt in the NVIC. + * When using an external interrupt the API for the interrupt component must + * be used to enable the interrupt. + * + *******************************************************************************/ + #define UART_1_EnableInt() CyIntEnable(UART_1_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: UART_1_DisableInt + ****************************************************************************//** + * + * When using an Internal interrupt, this disables the interrupt in the NVIC. + * When using an external interrupt the API for the interrupt component must + * be used to disable the interrupt. + * + *******************************************************************************/ + #define UART_1_DisableInt() CyIntDisable(UART_1_ISR_NUMBER) + /** @} interrupt */ + + /******************************************************************************* + * Function Name: UART_1_ClearPendingInt + ****************************************************************************//** + * + * This function clears the interrupt pending status in the NVIC. + * + *******************************************************************************/ + #define UART_1_ClearPendingInt() CyIntClearPending(UART_1_ISR_NUMBER) +#endif /* (UART_1_SCB_IRQ_INTERNAL) */ + +#if (UART_1_UART_RX_WAKEUP_IRQ) + /******************************************************************************* + * Function Name: UART_1_RxWakeEnableInt + ****************************************************************************//** + * + * This function enables the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define UART_1_RxWakeEnableInt() CyIntEnable(UART_1_RX_WAKE_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: UART_1_RxWakeDisableInt + ****************************************************************************//** + * + * This function disables the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define UART_1_RxWakeDisableInt() CyIntDisable(UART_1_RX_WAKE_ISR_NUMBER) + + + /******************************************************************************* + * Function Name: UART_1_RxWakeClearPendingInt + ****************************************************************************//** + * + * This function clears the interrupt (RX_WAKE) pending status in the NVIC. + * + *******************************************************************************/ + #define UART_1_RxWakeClearPendingInt() CyIntClearPending(UART_1_RX_WAKE_ISR_NUMBER) +#endif /* (UART_1_UART_RX_WAKEUP_IRQ) */ + +/** +* \addtogroup group_interrupt +* @{ +*/ +/* Get interrupt cause */ +/******************************************************************************* +* Function Name: UART_1_GetInterruptCause +****************************************************************************//** +* +* Returns a mask of bits showing the source of the current triggered interrupt. +* This is useful for modes of operation where an interrupt can be generated by +* conditions in multiple interrupt source registers. +* +* \return +* Mask with the OR of the following conditions that have been triggered. +* - UART_1_INTR_CAUSE_MASTER - Interrupt from Master +* - UART_1_INTR_CAUSE_SLAVE - Interrupt from Slave +* - UART_1_INTR_CAUSE_TX - Interrupt from TX +* - UART_1_INTR_CAUSE_RX - Interrupt from RX +* +*******************************************************************************/ +#define UART_1_GetInterruptCause() (UART_1_INTR_CAUSE_REG) + + +/* APIs to service INTR_RX register */ +/******************************************************************************* +* Function Name: UART_1_GetRxInterruptSource +****************************************************************************//** +* +* Returns RX interrupt request register. This register contains current status +* of RX interrupt sources. +* +* \return +* Current status of RX interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_1_INTR_RX_FIFO_LEVEL - The number of data elements in the + RX FIFO is greater than the value of RX FIFO level. +* - UART_1_INTR_RX_NOT_EMPTY - Receiver FIFO is not empty. +* - UART_1_INTR_RX_FULL - Receiver FIFO is full. +* - UART_1_INTR_RX_OVERFLOW - Attempt to write to a full +* receiver FIFO. +* - UART_1_INTR_RX_UNDERFLOW - Attempt to read from an empty +* receiver FIFO. +* - UART_1_INTR_RX_FRAME_ERROR - UART framing error detected. +* - UART_1_INTR_RX_PARITY_ERROR - UART parity error detected. +* +*******************************************************************************/ +#define UART_1_GetRxInterruptSource() (UART_1_INTR_RX_REG) + + +/******************************************************************************* +* Function Name: UART_1_SetRxInterruptMode +****************************************************************************//** +* +* Writes RX interrupt mask register. This register configures which bits from +* RX interrupt request register will trigger an interrupt event. +* +* \param interruptMask: RX interrupt sources to be enabled (refer to +* UART_1_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define UART_1_SetRxInterruptMode(interruptMask) UART_1_WRITE_INTR_RX_MASK(interruptMask) + + +/******************************************************************************* +* Function Name: UART_1_GetRxInterruptMode +****************************************************************************//** +* +* Returns RX interrupt mask register This register specifies which bits from +* RX interrupt request register will trigger an interrupt event. +* +* \return +* RX interrupt sources to be enabled (refer to +* UART_1_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define UART_1_GetRxInterruptMode() (UART_1_INTR_RX_MASK_REG) + + +/******************************************************************************* +* Function Name: UART_1_GetRxInterruptSourceMasked +****************************************************************************//** +* +* Returns RX interrupt masked request register. This register contains logical +* AND of corresponding bits from RX interrupt request and mask registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled RX interrupt sources cause interrupt event. +* +* \return +* Current status of enabled RX interrupt sources (refer to +* UART_1_GetRxInterruptSource() function for bit fields values). +* +*******************************************************************************/ +#define UART_1_GetRxInterruptSourceMasked() (UART_1_INTR_RX_MASKED_REG) + + +/******************************************************************************* +* Function Name: UART_1_ClearRxInterruptSource +****************************************************************************//** +* +* Clears RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to be cleared (refer to +* UART_1_GetRxInterruptSource() function for bit fields values). +* +* \sideeffects +* The side effects are listed in the table below for each +* affected interrupt source. Refer to section RX FIFO interrupt sources for +* detailed description. +* - UART_1_INTR_RX_FIFO_LEVEL Interrupt source is not cleared when +* the receiver FIFO has more entries than level. +* - UART_1_INTR_RX_NOT_EMPTY Interrupt source is not cleared when +* receiver FIFO is not empty. +* - UART_1_INTR_RX_FULL Interrupt source is not cleared when +* receiver FIFO is full. +* +*******************************************************************************/ +#define UART_1_ClearRxInterruptSource(interruptMask) UART_1_CLEAR_INTR_RX(interruptMask) + + +/******************************************************************************* +* Function Name: UART_1_SetRxInterrupt +****************************************************************************//** +* +* Sets RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to set in the RX interrupt request +* register (refer to UART_1_GetRxInterruptSource() function for bit +* fields values). +* +*******************************************************************************/ +#define UART_1_SetRxInterrupt(interruptMask) UART_1_SET_INTR_RX(interruptMask) + +void UART_1_SetRxFifoLevel(uint32 level); + + +/* APIs to service INTR_TX register */ +/******************************************************************************* +* Function Name: UART_1_GetTxInterruptSource +****************************************************************************//** +* +* Returns TX interrupt request register. This register contains current status +* of TX interrupt sources. +* +* \return +* Current status of TX interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_1_INTR_TX_FIFO_LEVEL - The number of data elements in the +* TX FIFO is less than the value of TX FIFO level. +* - UART_1_INTR_TX_NOT_FULL - Transmitter FIFO is not full. +* - UART_1_INTR_TX_EMPTY - Transmitter FIFO is empty. +* - UART_1_INTR_TX_OVERFLOW - Attempt to write to a full +* transmitter FIFO. +* - UART_1_INTR_TX_UNDERFLOW - Attempt to read from an empty +* transmitter FIFO. +* - UART_1_INTR_TX_UART_NACK - UART received a NACK in SmartCard +* mode. +* - UART_1_INTR_TX_UART_DONE - UART transfer is complete. +* All data elements from the TX FIFO are sent. +* - UART_1_INTR_TX_UART_ARB_LOST - Value on the TX line of the UART +* does not match the value on the RX line. +* +*******************************************************************************/ +#define UART_1_GetTxInterruptSource() (UART_1_INTR_TX_REG) + + +/******************************************************************************* +* Function Name: UART_1_SetTxInterruptMode +****************************************************************************//** +* +* Writes TX interrupt mask register. This register configures which bits from +* TX interrupt request register will trigger an interrupt event. +* +* \param interruptMask: TX interrupt sources to be enabled (refer to +* UART_1_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_1_SetTxInterruptMode(interruptMask) UART_1_WRITE_INTR_TX_MASK(interruptMask) + + +/******************************************************************************* +* Function Name: UART_1_GetTxInterruptMode +****************************************************************************//** +* +* Returns TX interrupt mask register This register specifies which bits from +* TX interrupt request register will trigger an interrupt event. +* +* \return +* Enabled TX interrupt sources (refer to +* UART_1_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_1_GetTxInterruptMode() (UART_1_INTR_TX_MASK_REG) + + +/******************************************************************************* +* Function Name: UART_1_GetTxInterruptSourceMasked +****************************************************************************//** +* +* Returns TX interrupt masked request register. This register contains logical +* AND of corresponding bits from TX interrupt request and mask registers. +* This function is intended to be used in the interrupt service routine to identify +* which of enabled TX interrupt sources cause interrupt event. +* +* \return +* Current status of enabled TX interrupt sources (refer to +* UART_1_GetTxInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_1_GetTxInterruptSourceMasked() (UART_1_INTR_TX_MASKED_REG) + + +/******************************************************************************* +* Function Name: UART_1_ClearTxInterruptSource +****************************************************************************//** +* +* Clears TX interrupt sources in the interrupt request register. +* +* \param interruptMask: TX interrupt sources to be cleared (refer to +* UART_1_GetTxInterruptSource() function for bit field values). +* +* \sideeffects +* The side effects are listed in the table below for each affected interrupt +* source. Refer to section TX FIFO interrupt sources for detailed description. +* - UART_1_INTR_TX_FIFO_LEVEL - Interrupt source is not cleared when +* transmitter FIFO has less entries than level. +* - UART_1_INTR_TX_NOT_FULL - Interrupt source is not cleared when +* transmitter FIFO has empty entries. +* - UART_1_INTR_TX_EMPTY - Interrupt source is not cleared when +* transmitter FIFO is empty. +* - UART_1_INTR_TX_UNDERFLOW - Interrupt source is not cleared when +* transmitter FIFO is empty and I2C mode with clock stretching is selected. +* Put data into the transmitter FIFO before clearing it. This behavior only +* applicable for PSoC 4100/PSoC 4200 devices. +* +*******************************************************************************/ +#define UART_1_ClearTxInterruptSource(interruptMask) UART_1_CLEAR_INTR_TX(interruptMask) + + +/******************************************************************************* +* Function Name: UART_1_SetTxInterrupt +****************************************************************************//** +* +* Sets RX interrupt sources in the interrupt request register. +* +* \param interruptMask: RX interrupt sources to set in the RX interrupt request +* register (refer to UART_1_GetRxInterruptSource() function for bit +* fields values). +* +*******************************************************************************/ +#define UART_1_SetTxInterrupt(interruptMask) UART_1_SET_INTR_TX(interruptMask) + +void UART_1_SetTxFifoLevel(uint32 level); + + +/* APIs to service INTR_MASTER register */ +/******************************************************************************* +* Function Name: UART_1_GetMasterInterruptSource +****************************************************************************//** +* +* Returns Master interrupt request register. This register contains current +* status of Master interrupt sources. +* +* \return +* Current status of Master interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_1_INTR_MASTER_SPI_DONE - SPI master transfer is complete. +* Refer to Interrupt sources section for detailed description. +* - UART_1_INTR_MASTER_I2C_ARB_LOST - I2C master lost arbitration. +* - UART_1_INTR_MASTER_I2C_NACK - I2C master received negative +* acknowledgement (NAK). +* - UART_1_INTR_MASTER_I2C_ACK - I2C master received acknowledgement. +* - UART_1_INTR_MASTER_I2C_STOP - I2C master generated STOP. +* - UART_1_INTR_MASTER_I2C_BUS_ERROR - I2C master bus error +* (detection of unexpected START or STOP condition). +* +*******************************************************************************/ +#define UART_1_GetMasterInterruptSource() (UART_1_INTR_MASTER_REG) + +/******************************************************************************* +* Function Name: UART_1_SetMasterInterruptMode +****************************************************************************//** +* +* Writes Master interrupt mask register. This register configures which bits +* from Master interrupt request register will trigger an interrupt event. +* +* \param interruptMask: Master interrupt sources to be enabled (refer to +* UART_1_GetMasterInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_1_SetMasterInterruptMode(interruptMask) UART_1_WRITE_INTR_MASTER_MASK(interruptMask) + +/******************************************************************************* +* Function Name: UART_1_GetMasterInterruptMode +****************************************************************************//** +* +* Returns Master interrupt mask register This register specifies which bits +* from Master interrupt request register will trigger an interrupt event. +* +* \return +* Enabled Master interrupt sources (refer to +* UART_1_GetMasterInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_1_GetMasterInterruptMode() (UART_1_INTR_MASTER_MASK_REG) + +/******************************************************************************* +* Function Name: UART_1_GetMasterInterruptSourceMasked +****************************************************************************//** +* +* Returns Master interrupt masked request register. This register contains +* logical AND of corresponding bits from Master interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled Master interrupt sources cause interrupt event. +* +* \return +* Current status of enabled Master interrupt sources (refer to +* UART_1_GetMasterInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_1_GetMasterInterruptSourceMasked() (UART_1_INTR_MASTER_MASKED_REG) + +/******************************************************************************* +* Function Name: UART_1_ClearMasterInterruptSource +****************************************************************************//** +* +* Clears Master interrupt sources in the interrupt request register. +* +* \param interruptMask: Master interrupt sources to be cleared (refer to +* UART_1_GetMasterInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_1_ClearMasterInterruptSource(interruptMask) UART_1_CLEAR_INTR_MASTER(interruptMask) + +/******************************************************************************* +* Function Name: UART_1_SetMasterInterrupt +****************************************************************************//** +* +* Sets Master interrupt sources in the interrupt request register. +* +* \param interruptMask: Master interrupt sources to set in the Master interrupt +* request register (refer to UART_1_GetMasterInterruptSource() +* function for bit field values). +* +*******************************************************************************/ +#define UART_1_SetMasterInterrupt(interruptMask) UART_1_SET_INTR_MASTER(interruptMask) + + +/* APIs to service INTR_SLAVE register */ +/******************************************************************************* +* Function Name: UART_1_GetSlaveInterruptSource +****************************************************************************//** +* +* Returns Slave interrupt request register. This register contains current +* status of Slave interrupt sources. +* +* \return +* Current status of Slave interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* - UART_1_INTR_SLAVE_I2C_ARB_LOST - I2C slave lost arbitration: +* the value driven on the SDA line is not the same as the value observed +* on the SDA line. +* - UART_1_INTR_SLAVE_I2C_NACK - I2C slave received negative +* acknowledgement (NAK). +* - UART_1_INTR_SLAVE_I2C_ACK - I2C slave received +* acknowledgement (ACK). +* - UART_1_INTR_SLAVE_I2C_WRITE_STOP - Stop or Repeated Start +* event for write transfer intended for this slave (address matching +* is performed). +* - UART_1_INTR_SLAVE_I2C_STOP - Stop or Repeated Start event +* for (read or write) transfer intended for this slave (address matching +* is performed). +* - UART_1_INTR_SLAVE_I2C_START - I2C slave received Start +* condition. +* - UART_1_INTR_SLAVE_I2C_ADDR_MATCH - I2C slave received matching +* address. +* - UART_1_INTR_SLAVE_I2C_GENERAL - I2C Slave received general +* call address. +* - UART_1_INTR_SLAVE_I2C_BUS_ERROR - I2C slave bus error (detection +* of unexpected Start or Stop condition). +* - UART_1_INTR_SLAVE_SPI_BUS_ERROR - SPI slave select line is +* deselected at an expected time while the SPI transfer. +* +*******************************************************************************/ +#define UART_1_GetSlaveInterruptSource() (UART_1_INTR_SLAVE_REG) + +/******************************************************************************* +* Function Name: UART_1_SetSlaveInterruptMode +****************************************************************************//** +* +* Writes Slave interrupt mask register. +* This register configures which bits from Slave interrupt request register +* will trigger an interrupt event. +* +* \param interruptMask: Slave interrupt sources to be enabled (refer to +* UART_1_GetSlaveInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_1_SetSlaveInterruptMode(interruptMask) UART_1_WRITE_INTR_SLAVE_MASK(interruptMask) + +/******************************************************************************* +* Function Name: UART_1_GetSlaveInterruptMode +****************************************************************************//** +* +* Returns Slave interrupt mask register. +* This register specifies which bits from Slave interrupt request register +* will trigger an interrupt event. +* +* \return +* Enabled Slave interrupt sources(refer to +* UART_1_GetSlaveInterruptSource() function for bit field values). +* +*******************************************************************************/ +#define UART_1_GetSlaveInterruptMode() (UART_1_INTR_SLAVE_MASK_REG) + +/******************************************************************************* +* Function Name: UART_1_GetSlaveInterruptSourceMasked +****************************************************************************//** +* +* Returns Slave interrupt masked request register. This register contains +* logical AND of corresponding bits from Slave interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled Slave interrupt sources cause interrupt event. +* +* \return +* Current status of enabled Slave interrupt sources (refer to +* UART_1_GetSlaveInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_1_GetSlaveInterruptSourceMasked() (UART_1_INTR_SLAVE_MASKED_REG) + +/******************************************************************************* +* Function Name: UART_1_ClearSlaveInterruptSource +****************************************************************************//** +* +* Clears Slave interrupt sources in the interrupt request register. +* +* \param interruptMask: Slave interrupt sources to be cleared (refer to +* UART_1_GetSlaveInterruptSource() function for return values). +* +*******************************************************************************/ +#define UART_1_ClearSlaveInterruptSource(interruptMask) UART_1_CLEAR_INTR_SLAVE(interruptMask) + +/******************************************************************************* +* Function Name: UART_1_SetSlaveInterrupt +****************************************************************************//** +* +* Sets Slave interrupt sources in the interrupt request register. +* +* \param interruptMask: Slave interrupt sources to set in the Slave interrupt +* request register (refer to UART_1_GetSlaveInterruptSource() +* function for return values). +* +*******************************************************************************/ +#define UART_1_SetSlaveInterrupt(interruptMask) UART_1_SET_INTR_SLAVE(interruptMask) + +/** @} interrupt */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +/** +* \addtogroup group_globals +* @{ +*/ + +/** UART_1_initVar indicates whether the UART_1 +* component has been initialized. The variable is initialized to 0 +* and set to 1 the first time SCB_Start() is called. This allows +* the component to restart without reinitialization after the first +* call to the UART_1_Start() routine. +* +* If re-initialization of the component is required, then the +* UART_1_Init() function can be called before the +* UART_1_Start() or UART_1_Enable() function. +*/ +extern uint8 UART_1_initVar; +/** @} globals */ + +/*************************************** +* Registers +***************************************/ + +#define UART_1_CTRL_REG (*(reg32 *) UART_1_SCB__CTRL) +#define UART_1_CTRL_PTR ( (reg32 *) UART_1_SCB__CTRL) + +#define UART_1_STATUS_REG (*(reg32 *) UART_1_SCB__STATUS) +#define UART_1_STATUS_PTR ( (reg32 *) UART_1_SCB__STATUS) + +#if (!UART_1_CY_SCBIP_V1) + #define UART_1_SPI_CTRL_REG (*(reg32 *) UART_1_SCB__SPI_CTRL) + #define UART_1_SPI_CTRL_PTR ( (reg32 *) UART_1_SCB__SPI_CTRL) + + #define UART_1_SPI_STATUS_REG (*(reg32 *) UART_1_SCB__SPI_STATUS) + #define UART_1_SPI_STATUS_PTR ( (reg32 *) UART_1_SCB__SPI_STATUS) + + #define UART_1_UART_CTRL_REG (*(reg32 *) UART_1_SCB__UART_CTRL) + #define UART_1_UART_CTRL_PTR ( (reg32 *) UART_1_SCB__UART_CTRL) + + #define UART_1_UART_TX_CTRL_REG (*(reg32 *) UART_1_SCB__UART_TX_CTRL) + #define UART_1_UART_TX_CTRL_PTR ( (reg32 *) UART_1_SCB__UART_TX_CTRL) + + #define UART_1_UART_RX_CTRL_REG (*(reg32 *) UART_1_SCB__UART_RX_CTRL) + #define UART_1_UART_RX_CTRL_PTR ( (reg32 *) UART_1_SCB__UART_RX_CTRL) + + #define UART_1_UART_RX_STATUS_REG (*(reg32 *) UART_1_SCB__UART_RX_STATUS) + #define UART_1_UART_RX_STATUS_PTR ( (reg32 *) UART_1_SCB__UART_RX_STATUS) +#endif /* (!UART_1_CY_SCBIP_V1) */ + +#if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + #define UART_1_UART_FLOW_CTRL_REG (*(reg32 *) UART_1_SCB__UART_FLOW_CTRL) + #define UART_1_UART_FLOW_CTRL_PTR ( (reg32 *) UART_1_SCB__UART_FLOW_CTRL) +#endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + +#define UART_1_I2C_CTRL_REG (*(reg32 *) UART_1_SCB__I2C_CTRL) +#define UART_1_I2C_CTRL_PTR ( (reg32 *) UART_1_SCB__I2C_CTRL) + +#define UART_1_I2C_STATUS_REG (*(reg32 *) UART_1_SCB__I2C_STATUS) +#define UART_1_I2C_STATUS_PTR ( (reg32 *) UART_1_SCB__I2C_STATUS) + +#define UART_1_I2C_MASTER_CMD_REG (*(reg32 *) UART_1_SCB__I2C_M_CMD) +#define UART_1_I2C_MASTER_CMD_PTR ( (reg32 *) UART_1_SCB__I2C_M_CMD) + +#define UART_1_I2C_SLAVE_CMD_REG (*(reg32 *) UART_1_SCB__I2C_S_CMD) +#define UART_1_I2C_SLAVE_CMD_PTR ( (reg32 *) UART_1_SCB__I2C_S_CMD) + +#define UART_1_I2C_CFG_REG (*(reg32 *) UART_1_SCB__I2C_CFG) +#define UART_1_I2C_CFG_PTR ( (reg32 *) UART_1_SCB__I2C_CFG) + +#define UART_1_TX_CTRL_REG (*(reg32 *) UART_1_SCB__TX_CTRL) +#define UART_1_TX_CTRL_PTR ( (reg32 *) UART_1_SCB__TX_CTRL) + +#define UART_1_TX_FIFO_CTRL_REG (*(reg32 *) UART_1_SCB__TX_FIFO_CTRL) +#define UART_1_TX_FIFO_CTRL_PTR ( (reg32 *) UART_1_SCB__TX_FIFO_CTRL) + +#define UART_1_TX_FIFO_STATUS_REG (*(reg32 *) UART_1_SCB__TX_FIFO_STATUS) +#define UART_1_TX_FIFO_STATUS_PTR ( (reg32 *) UART_1_SCB__TX_FIFO_STATUS) + +#define UART_1_TX_FIFO_WR_REG (*(reg32 *) UART_1_SCB__TX_FIFO_WR) +#define UART_1_TX_FIFO_WR_PTR ( (reg32 *) UART_1_SCB__TX_FIFO_WR) + +#define UART_1_RX_CTRL_REG (*(reg32 *) UART_1_SCB__RX_CTRL) +#define UART_1_RX_CTRL_PTR ( (reg32 *) UART_1_SCB__RX_CTRL) + +#define UART_1_RX_FIFO_CTRL_REG (*(reg32 *) UART_1_SCB__RX_FIFO_CTRL) +#define UART_1_RX_FIFO_CTRL_PTR ( (reg32 *) UART_1_SCB__RX_FIFO_CTRL) + +#define UART_1_RX_FIFO_STATUS_REG (*(reg32 *) UART_1_SCB__RX_FIFO_STATUS) +#define UART_1_RX_FIFO_STATUS_PTR ( (reg32 *) UART_1_SCB__RX_FIFO_STATUS) + +#define UART_1_RX_MATCH_REG (*(reg32 *) UART_1_SCB__RX_MATCH) +#define UART_1_RX_MATCH_PTR ( (reg32 *) UART_1_SCB__RX_MATCH) + +#define UART_1_RX_FIFO_RD_REG (*(reg32 *) UART_1_SCB__RX_FIFO_RD) +#define UART_1_RX_FIFO_RD_PTR ( (reg32 *) UART_1_SCB__RX_FIFO_RD) + +#define UART_1_RX_FIFO_RD_SILENT_REG (*(reg32 *) UART_1_SCB__RX_FIFO_RD_SILENT) +#define UART_1_RX_FIFO_RD_SILENT_PTR ( (reg32 *) UART_1_SCB__RX_FIFO_RD_SILENT) + +#ifdef UART_1_SCB__EZ_DATA0 + #define UART_1_EZBUF_DATA0_REG (*(reg32 *) UART_1_SCB__EZ_DATA0) + #define UART_1_EZBUF_DATA0_PTR ( (reg32 *) UART_1_SCB__EZ_DATA0) +#else + #define UART_1_EZBUF_DATA0_REG (*(reg32 *) UART_1_SCB__EZ_DATA00) + #define UART_1_EZBUF_DATA0_PTR ( (reg32 *) UART_1_SCB__EZ_DATA00) +#endif /* UART_1_SCB__EZ_DATA00 */ + +#define UART_1_INTR_CAUSE_REG (*(reg32 *) UART_1_SCB__INTR_CAUSE) +#define UART_1_INTR_CAUSE_PTR ( (reg32 *) UART_1_SCB__INTR_CAUSE) + +#define UART_1_INTR_I2C_EC_REG (*(reg32 *) UART_1_SCB__INTR_I2C_EC) +#define UART_1_INTR_I2C_EC_PTR ( (reg32 *) UART_1_SCB__INTR_I2C_EC) + +#define UART_1_INTR_I2C_EC_MASK_REG (*(reg32 *) UART_1_SCB__INTR_I2C_EC_MASK) +#define UART_1_INTR_I2C_EC_MASK_PTR ( (reg32 *) UART_1_SCB__INTR_I2C_EC_MASK) + +#define UART_1_INTR_I2C_EC_MASKED_REG (*(reg32 *) UART_1_SCB__INTR_I2C_EC_MASKED) +#define UART_1_INTR_I2C_EC_MASKED_PTR ( (reg32 *) UART_1_SCB__INTR_I2C_EC_MASKED) + +#if (!UART_1_CY_SCBIP_V1) + #define UART_1_INTR_SPI_EC_REG (*(reg32 *) UART_1_SCB__INTR_SPI_EC) + #define UART_1_INTR_SPI_EC_PTR ( (reg32 *) UART_1_SCB__INTR_SPI_EC) + + #define UART_1_INTR_SPI_EC_MASK_REG (*(reg32 *) UART_1_SCB__INTR_SPI_EC_MASK) + #define UART_1_INTR_SPI_EC_MASK_PTR ( (reg32 *) UART_1_SCB__INTR_SPI_EC_MASK) + + #define UART_1_INTR_SPI_EC_MASKED_REG (*(reg32 *) UART_1_SCB__INTR_SPI_EC_MASKED) + #define UART_1_INTR_SPI_EC_MASKED_PTR ( (reg32 *) UART_1_SCB__INTR_SPI_EC_MASKED) +#endif /* (!UART_1_CY_SCBIP_V1) */ + +#define UART_1_INTR_MASTER_REG (*(reg32 *) UART_1_SCB__INTR_M) +#define UART_1_INTR_MASTER_PTR ( (reg32 *) UART_1_SCB__INTR_M) + +#define UART_1_INTR_MASTER_SET_REG (*(reg32 *) UART_1_SCB__INTR_M_SET) +#define UART_1_INTR_MASTER_SET_PTR ( (reg32 *) UART_1_SCB__INTR_M_SET) + +#define UART_1_INTR_MASTER_MASK_REG (*(reg32 *) UART_1_SCB__INTR_M_MASK) +#define UART_1_INTR_MASTER_MASK_PTR ( (reg32 *) UART_1_SCB__INTR_M_MASK) + +#define UART_1_INTR_MASTER_MASKED_REG (*(reg32 *) UART_1_SCB__INTR_M_MASKED) +#define UART_1_INTR_MASTER_MASKED_PTR ( (reg32 *) UART_1_SCB__INTR_M_MASKED) + +#define UART_1_INTR_SLAVE_REG (*(reg32 *) UART_1_SCB__INTR_S) +#define UART_1_INTR_SLAVE_PTR ( (reg32 *) UART_1_SCB__INTR_S) + +#define UART_1_INTR_SLAVE_SET_REG (*(reg32 *) UART_1_SCB__INTR_S_SET) +#define UART_1_INTR_SLAVE_SET_PTR ( (reg32 *) UART_1_SCB__INTR_S_SET) + +#define UART_1_INTR_SLAVE_MASK_REG (*(reg32 *) UART_1_SCB__INTR_S_MASK) +#define UART_1_INTR_SLAVE_MASK_PTR ( (reg32 *) UART_1_SCB__INTR_S_MASK) + +#define UART_1_INTR_SLAVE_MASKED_REG (*(reg32 *) UART_1_SCB__INTR_S_MASKED) +#define UART_1_INTR_SLAVE_MASKED_PTR ( (reg32 *) UART_1_SCB__INTR_S_MASKED) + +#define UART_1_INTR_TX_REG (*(reg32 *) UART_1_SCB__INTR_TX) +#define UART_1_INTR_TX_PTR ( (reg32 *) UART_1_SCB__INTR_TX) + +#define UART_1_INTR_TX_SET_REG (*(reg32 *) UART_1_SCB__INTR_TX_SET) +#define UART_1_INTR_TX_SET_PTR ( (reg32 *) UART_1_SCB__INTR_TX_SET) + +#define UART_1_INTR_TX_MASK_REG (*(reg32 *) UART_1_SCB__INTR_TX_MASK) +#define UART_1_INTR_TX_MASK_PTR ( (reg32 *) UART_1_SCB__INTR_TX_MASK) + +#define UART_1_INTR_TX_MASKED_REG (*(reg32 *) UART_1_SCB__INTR_TX_MASKED) +#define UART_1_INTR_TX_MASKED_PTR ( (reg32 *) UART_1_SCB__INTR_TX_MASKED) + +#define UART_1_INTR_RX_REG (*(reg32 *) UART_1_SCB__INTR_RX) +#define UART_1_INTR_RX_PTR ( (reg32 *) UART_1_SCB__INTR_RX) + +#define UART_1_INTR_RX_SET_REG (*(reg32 *) UART_1_SCB__INTR_RX_SET) +#define UART_1_INTR_RX_SET_PTR ( (reg32 *) UART_1_SCB__INTR_RX_SET) + +#define UART_1_INTR_RX_MASK_REG (*(reg32 *) UART_1_SCB__INTR_RX_MASK) +#define UART_1_INTR_RX_MASK_PTR ( (reg32 *) UART_1_SCB__INTR_RX_MASK) + +#define UART_1_INTR_RX_MASKED_REG (*(reg32 *) UART_1_SCB__INTR_RX_MASKED) +#define UART_1_INTR_RX_MASKED_PTR ( (reg32 *) UART_1_SCB__INTR_RX_MASKED) + +/* Defines get from SCB IP parameters. */ +#define UART_1_FIFO_SIZE (8u) /* TX or RX FIFO size. */ +#define UART_1_EZ_DATA_NR (32u) /* Number of words in EZ memory. */ +#define UART_1_ONE_BYTE_WIDTH (8u) /* Number of bits in one byte. */ +#define UART_1_FF_DATA_NR_LOG2_MASK (0x0Fu) /* Number of bits to represent a FIFO address. */ +#define UART_1_FF_DATA_NR_LOG2_PLUS1_MASK (0x1Fu) /* Number of bits to represent #bytes in FIFO. */ + + +/*************************************** +* Registers Constants +***************************************/ + +#if (UART_1_SCB_IRQ_INTERNAL) + #define UART_1_ISR_NUMBER ((uint8) UART_1_SCB_IRQ__INTC_NUMBER) + #define UART_1_ISR_PRIORITY ((uint8) UART_1_SCB_IRQ__INTC_PRIOR_NUM) +#endif /* (UART_1_SCB_IRQ_INTERNAL) */ + +#if (UART_1_UART_RX_WAKEUP_IRQ) + #define UART_1_RX_WAKE_ISR_NUMBER ((uint8) UART_1_RX_WAKEUP_IRQ__INTC_NUMBER) + #define UART_1_RX_WAKE_ISR_PRIORITY ((uint8) UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_NUM) +#endif /* (UART_1_UART_RX_WAKEUP_IRQ) */ + +/* UART_1_CTRL_REG */ +#define UART_1_CTRL_OVS_POS (0u) /* [3:0] Oversampling factor */ +#define UART_1_CTRL_EC_AM_MODE_POS (8u) /* [8] Externally clocked address match */ +#define UART_1_CTRL_EC_OP_MODE_POS (9u) /* [9] Externally clocked operation mode */ +#define UART_1_CTRL_EZBUF_MODE_POS (10u) /* [10] EZ buffer is enabled */ +#if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + #define UART_1_CTRL_BYTE_MODE_POS (11u) /* [11] Determines the number of bits per FIFO data element */ +#endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ +#define UART_1_CTRL_ADDR_ACCEPT_POS (16u) /* [16] Put matched address in RX FIFO */ +#define UART_1_CTRL_BLOCK_POS (17u) /* [17] Ext and Int logic to resolve collide */ +#define UART_1_CTRL_MODE_POS (24u) /* [25:24] Operation mode */ +#define UART_1_CTRL_ENABLED_POS (31u) /* [31] Enable SCB block */ +#define UART_1_CTRL_OVS_MASK ((uint32) 0x0Fu) +#define UART_1_CTRL_EC_AM_MODE ((uint32) 0x01u << UART_1_CTRL_EC_AM_MODE_POS) +#define UART_1_CTRL_EC_OP_MODE ((uint32) 0x01u << UART_1_CTRL_EC_OP_MODE_POS) +#define UART_1_CTRL_EZBUF_MODE ((uint32) 0x01u << UART_1_CTRL_EZBUF_MODE_POS) +#if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + #define UART_1_CTRL_BYTE_MODE ((uint32) 0x01u << UART_1_CTRL_BYTE_MODE_POS) +#endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ +#define UART_1_CTRL_ADDR_ACCEPT ((uint32) 0x01u << UART_1_CTRL_ADDR_ACCEPT_POS) +#define UART_1_CTRL_BLOCK ((uint32) 0x01u << UART_1_CTRL_BLOCK_POS) +#define UART_1_CTRL_MODE_MASK ((uint32) 0x03u << UART_1_CTRL_MODE_POS) +#define UART_1_CTRL_MODE_I2C ((uint32) 0x00u) +#define UART_1_CTRL_MODE_SPI ((uint32) 0x01u << UART_1_CTRL_MODE_POS) +#define UART_1_CTRL_MODE_UART ((uint32) 0x02u << UART_1_CTRL_MODE_POS) +#define UART_1_CTRL_ENABLED ((uint32) 0x01u << UART_1_CTRL_ENABLED_POS) + +/* UART_1_STATUS_REG */ +#define UART_1_STATUS_EC_BUSY_POS (0u) /* [0] Bus busy. Externally clocked logic access to EZ memory */ +#define UART_1_STATUS_EC_BUSY ((uint32) 0x0Fu) + +/* UART_1_SPI_CTRL_REG */ +#define UART_1_SPI_CTRL_CONTINUOUS_POS (0u) /* [0] Continuous or Separated SPI data transfers */ +#define UART_1_SPI_CTRL_SELECT_PRECEDE_POS (1u) /* [1] Precedes or coincides start of data frame */ +#define UART_1_SPI_CTRL_CPHA_POS (2u) /* [2] SCLK phase */ +#define UART_1_SPI_CTRL_CPOL_POS (3u) /* [3] SCLK polarity */ +#define UART_1_SPI_CTRL_LATE_MISO_SAMPLE_POS (4u) /* [4] Late MISO sample enabled */ +#if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + #define UART_1_SPI_CTRL_SCLK_CONTINUOUS_POS (5u) /* [5] Enable continuous SCLK generation */ + #define UART_1_SPI_CTRL_SSEL0_POLARITY_POS (8u) /* [8] SS0 polarity */ + #define UART_1_SPI_CTRL_SSEL1_POLARITY_POS (9u) /* [9] SS1 polarity */ + #define UART_1_SPI_CTRL_SSEL2_POLARITY_POS (10u) /* [10] SS2 polarity */ + #define UART_1_SPI_CTRL_SSEL3_POLARITY_POS (11u) /* [11] SS3 polarity */ +#endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ +#define UART_1_SPI_CTRL_LOOPBACK_POS (16u) /* [16] Local loop-back control enabled */ +#define UART_1_SPI_CTRL_MODE_POS (24u) /* [25:24] Submode of SPI operation */ +#define UART_1_SPI_CTRL_SLAVE_SELECT_POS (26u) /* [27:26] Selects SPI SS signal */ +#define UART_1_SPI_CTRL_MASTER_MODE_POS (31u) /* [31] Master mode enabled */ +#define UART_1_SPI_CTRL_CONTINUOUS ((uint32) 0x01u) +#define UART_1_SPI_CTRL_SELECT_PRECEDE ((uint32) 0x01u << UART_1_SPI_CTRL_SELECT_PRECEDE_POS) +#define UART_1_SPI_CTRL_SCLK_MODE_MASK ((uint32) 0x03u << UART_1_SPI_CTRL_CPHA_POS) +#define UART_1_SPI_CTRL_CPHA ((uint32) 0x01u << UART_1_SPI_CTRL_CPHA_POS) +#define UART_1_SPI_CTRL_CPOL ((uint32) 0x01u << UART_1_SPI_CTRL_CPOL_POS) +#define UART_1_SPI_CTRL_LATE_MISO_SAMPLE ((uint32) 0x01u << \ + UART_1_SPI_CTRL_LATE_MISO_SAMPLE_POS) +#if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + #define UART_1_SPI_CTRL_SCLK_CONTINUOUS ((uint32) 0x01u << UART_1_SPI_CTRL_SCLK_CONTINUOUS_POS) + #define UART_1_SPI_CTRL_SSEL0_POLARITY ((uint32) 0x01u << UART_1_SPI_CTRL_SSEL0_POLARITY_POS) + #define UART_1_SPI_CTRL_SSEL1_POLARITY ((uint32) 0x01u << UART_1_SPI_CTRL_SSEL1_POLARITY_POS) + #define UART_1_SPI_CTRL_SSEL2_POLARITY ((uint32) 0x01u << UART_1_SPI_CTRL_SSEL2_POLARITY_POS) + #define UART_1_SPI_CTRL_SSEL3_POLARITY ((uint32) 0x01u << UART_1_SPI_CTRL_SSEL3_POLARITY_POS) + #define UART_1_SPI_CTRL_SSEL_POLARITY_MASK ((uint32)0x0Fu << UART_1_SPI_CTRL_SSEL0_POLARITY_POS) +#endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + +#define UART_1_SPI_CTRL_LOOPBACK ((uint32) 0x01u << UART_1_SPI_CTRL_LOOPBACK_POS) +#define UART_1_SPI_CTRL_MODE_MASK ((uint32) 0x03u << UART_1_SPI_CTRL_MODE_POS) +#define UART_1_SPI_CTRL_MODE_MOTOROLA ((uint32) 0x00u) +#define UART_1_SPI_CTRL_MODE_TI ((uint32) 0x01u << UART_1_CTRL_MODE_POS) +#define UART_1_SPI_CTRL_MODE_NS ((uint32) 0x02u << UART_1_CTRL_MODE_POS) +#define UART_1_SPI_CTRL_SLAVE_SELECT_MASK ((uint32) 0x03u << UART_1_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_1_SPI_CTRL_SLAVE_SELECT0 ((uint32) 0x00u) +#define UART_1_SPI_CTRL_SLAVE_SELECT1 ((uint32) 0x01u << UART_1_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_1_SPI_CTRL_SLAVE_SELECT2 ((uint32) 0x02u << UART_1_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_1_SPI_CTRL_SLAVE_SELECT3 ((uint32) 0x03u << UART_1_SPI_CTRL_SLAVE_SELECT_POS) +#define UART_1_SPI_CTRL_MASTER ((uint32) 0x01u << UART_1_SPI_CTRL_MASTER_MODE_POS) +#define UART_1_SPI_CTRL_SLAVE ((uint32) 0x00u) + +/* UART_1_SPI_STATUS_REG */ +#define UART_1_SPI_STATUS_BUS_BUSY_POS (0u) /* [0] Bus busy - slave selected */ +#define UART_1_SPI_STATUS_EZBUF_ADDR_POS (8u) /* [15:8] EzAddress */ +#define UART_1_SPI_STATUS_BUS_BUSY ((uint32) 0x01u) +#define UART_1_SPI_STATUS_EZBUF_ADDR_MASK ((uint32) 0xFFu << UART_1_I2C_STATUS_EZBUF_ADDR_POS) + +/* UART_1_UART_CTRL */ +#define UART_1_UART_CTRL_LOOPBACK_POS (16u) /* [16] Loop-back */ +#define UART_1_UART_CTRL_MODE_POS (24u) /* [24] UART subMode */ +#define UART_1_UART_CTRL_LOOPBACK ((uint32) 0x01u << UART_1_UART_CTRL_LOOPBACK_POS) +#define UART_1_UART_CTRL_MODE_UART_STD ((uint32) 0x00u) +#define UART_1_UART_CTRL_MODE_UART_SMARTCARD ((uint32) 0x01u << UART_1_UART_CTRL_MODE_POS) +#define UART_1_UART_CTRL_MODE_UART_IRDA ((uint32) 0x02u << UART_1_UART_CTRL_MODE_POS) +#define UART_1_UART_CTRL_MODE_MASK ((uint32) 0x03u << UART_1_UART_CTRL_MODE_POS) + +/* UART_1_UART_TX_CTRL */ +#define UART_1_UART_TX_CTRL_STOP_BITS_POS (0u) /* [2:0] Stop bits: (Stop bits + 1) * 0.5 period */ +#define UART_1_UART_TX_CTRL_PARITY_POS (4u) /* [4] Parity bit */ +#define UART_1_UART_TX_CTRL_PARITY_ENABLED_POS (5u) /* [5] Parity enable */ +#define UART_1_UART_TX_CTRL_RETRY_ON_NACK_POS (8u) /* [8] Smart Card: re-send frame on NACK */ +#define UART_1_UART_TX_CTRL_ONE_STOP_BIT ((uint32) 0x01u) +#define UART_1_UART_TX_CTRL_ONE_HALF_STOP_BITS ((uint32) 0x02u) +#define UART_1_UART_TX_CTRL_TWO_STOP_BITS ((uint32) 0x03u) +#define UART_1_UART_TX_CTRL_STOP_BITS_MASK ((uint32) 0x07u) +#define UART_1_UART_TX_CTRL_PARITY ((uint32) 0x01u << \ + UART_1_UART_TX_CTRL_PARITY_POS) +#define UART_1_UART_TX_CTRL_PARITY_ENABLED ((uint32) 0x01u << \ + UART_1_UART_TX_CTRL_PARITY_ENABLED_POS) +#define UART_1_UART_TX_CTRL_RETRY_ON_NACK ((uint32) 0x01u << \ + UART_1_UART_TX_CTRL_RETRY_ON_NACK_POS) + +/* UART_1_UART_RX_CTRL */ +#define UART_1_UART_RX_CTRL_STOP_BITS_POS (0u) /* [2:0] Stop bits: (Stop bits + 1) * 0.5 period*/ +#define UART_1_UART_RX_CTRL_PARITY_POS (4u) /* [4] Parity bit */ +#define UART_1_UART_RX_CTRL_PARITY_ENABLED_POS (5u) /* [5] Parity enable */ +#define UART_1_UART_RX_CTRL_POLARITY_POS (6u) /* [6] IrDA: inverts polarity of RX signal */ +#define UART_1_UART_RX_CTRL_DROP_ON_PARITY_ERR_POS (8u) /* [8] Drop and lost RX FIFO on parity error */ +#define UART_1_UART_RX_CTRL_DROP_ON_FRAME_ERR_POS (9u) /* [9] Drop and lost RX FIFO on frame error */ +#define UART_1_UART_RX_CTRL_MP_MODE_POS (10u) /* [10] Multi-processor mode */ +#define UART_1_UART_RX_CTRL_LIN_MODE_POS (12u) /* [12] Lin mode: applicable for UART Standard */ +#define UART_1_UART_RX_CTRL_SKIP_START_POS (13u) /* [13] Skip start not: only for UART Standard */ +#define UART_1_UART_RX_CTRL_BREAK_WIDTH_POS (16u) /* [19:16] Break width: (Break width + 1) */ +#define UART_1_UART_TX_CTRL_ONE_STOP_BIT ((uint32) 0x01u) +#define UART_1_UART_TX_CTRL_ONE_HALF_STOP_BITS ((uint32) 0x02u) +#define UART_1_UART_TX_CTRL_TWO_STOP_BITS ((uint32) 0x03u) +#define UART_1_UART_RX_CTRL_STOP_BITS_MASK ((uint32) 0x07u) +#define UART_1_UART_RX_CTRL_PARITY ((uint32) 0x01u << \ + UART_1_UART_RX_CTRL_PARITY_POS) +#define UART_1_UART_RX_CTRL_PARITY_ENABLED ((uint32) 0x01u << \ + UART_1_UART_RX_CTRL_PARITY_ENABLED_POS) +#define UART_1_UART_RX_CTRL_POLARITY ((uint32) 0x01u << \ + UART_1_UART_RX_CTRL_POLARITY_POS) +#define UART_1_UART_RX_CTRL_DROP_ON_PARITY_ERR ((uint32) 0x01u << \ + UART_1_UART_RX_CTRL_DROP_ON_PARITY_ERR_POS) +#define UART_1_UART_RX_CTRL_DROP_ON_FRAME_ERR ((uint32) 0x01u << \ + UART_1_UART_RX_CTRL_DROP_ON_FRAME_ERR_POS) +#define UART_1_UART_RX_CTRL_MP_MODE ((uint32) 0x01u << \ + UART_1_UART_RX_CTRL_MP_MODE_POS) +#define UART_1_UART_RX_CTRL_LIN_MODE ((uint32) 0x01u << \ + UART_1_UART_RX_CTRL_LIN_MODE_POS) +#define UART_1_UART_RX_CTRL_SKIP_START ((uint32) 0x01u << \ + UART_1_UART_RX_CTRL_SKIP_START_POS) +#define UART_1_UART_RX_CTRL_BREAK_WIDTH_MASK ((uint32) 0x0Fu << \ + UART_1_UART_RX_CTRL_BREAK_WIDTH_POS) +/* UART_1_UART_RX_STATUS_REG */ +#define UART_1_UART_RX_STATUS_BR_COUNTER_POS (0u) /* [11:0] Baud Rate counter */ +#define UART_1_UART_RX_STATUS_BR_COUNTER_MASK ((uint32) 0xFFFu) + +#if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + /* UART_1_UART_FLOW_CTRL_REG */ + #define UART_1_UART_FLOW_CTRL_TRIGGER_LEVEL_POS (0u) /* [7:0] RTS RX FIFO trigger level */ + #define UART_1_UART_FLOW_CTRL_RTS_POLARITY_POS (16u) /* [16] Polarity of the RTS output signal */ + #define UART_1_UART_FLOW_CTRL_CTS_POLARITY_POS (24u) /* [24] Polarity of the CTS input signal */ + #define UART_1_UART_FLOW_CTRL_CTS_ENABLED_POS (25u) /* [25] Enable CTS signal */ + #define UART_1_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK ((uint32) UART_1_FF_DATA_NR_LOG2_MASK) + #define UART_1_UART_FLOW_CTRL_RTS_POLARITY ((uint32) 0x01u << \ + UART_1_UART_FLOW_CTRL_RTS_POLARITY_POS) + #define UART_1_UART_FLOW_CTRL_CTS_POLARITY ((uint32) 0x01u << \ + UART_1_UART_FLOW_CTRL_CTS_POLARITY_POS) + #define UART_1_UART_FLOW_CTRL_CTS_ENABLE ((uint32) 0x01u << \ + UART_1_UART_FLOW_CTRL_CTS_ENABLED_POS) +#endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + +/* UART_1_I2C_CTRL */ +#define UART_1_I2C_CTRL_HIGH_PHASE_OVS_POS (0u) /* [3:0] Oversampling factor high: master only */ +#define UART_1_I2C_CTRL_LOW_PHASE_OVS_POS (4u) /* [7:4] Oversampling factor low: master only */ +#define UART_1_I2C_CTRL_M_READY_DATA_ACK_POS (8u) /* [8] Master ACKs data while RX FIFO != FULL*/ +#define UART_1_I2C_CTRL_M_NOT_READY_DATA_NACK_POS (9u) /* [9] Master NACKs data if RX FIFO == FULL */ +#define UART_1_I2C_CTRL_S_GENERAL_IGNORE_POS (11u) /* [11] Slave ignores General call */ +#define UART_1_I2C_CTRL_S_READY_ADDR_ACK_POS (12u) /* [12] Slave ACKs Address if RX FIFO != FULL */ +#define UART_1_I2C_CTRL_S_READY_DATA_ACK_POS (13u) /* [13] Slave ACKs data while RX FIFO == FULL */ +#define UART_1_I2C_CTRL_S_NOT_READY_ADDR_NACK_POS (14u) /* [14] Slave NACKs address if RX FIFO == FULL*/ +#define UART_1_I2C_CTRL_S_NOT_READY_DATA_NACK_POS (15u) /* [15] Slave NACKs data if RX FIFO is FULL */ +#define UART_1_I2C_CTRL_LOOPBACK_POS (16u) /* [16] Loop-back */ +#define UART_1_I2C_CTRL_SLAVE_MODE_POS (30u) /* [30] Slave mode enabled */ +#define UART_1_I2C_CTRL_MASTER_MODE_POS (31u) /* [31] Master mode enabled */ +#define UART_1_I2C_CTRL_HIGH_PHASE_OVS_MASK ((uint32) 0x0Fu) +#define UART_1_I2C_CTRL_LOW_PHASE_OVS_MASK ((uint32) 0x0Fu << \ + UART_1_I2C_CTRL_LOW_PHASE_OVS_POS) +#define UART_1_I2C_CTRL_M_READY_DATA_ACK ((uint32) 0x01u << \ + UART_1_I2C_CTRL_M_READY_DATA_ACK_POS) +#define UART_1_I2C_CTRL_M_NOT_READY_DATA_NACK ((uint32) 0x01u << \ + UART_1_I2C_CTRL_M_NOT_READY_DATA_NACK_POS) +#define UART_1_I2C_CTRL_S_GENERAL_IGNORE ((uint32) 0x01u << \ + UART_1_I2C_CTRL_S_GENERAL_IGNORE_POS) +#define UART_1_I2C_CTRL_S_READY_ADDR_ACK ((uint32) 0x01u << \ + UART_1_I2C_CTRL_S_READY_ADDR_ACK_POS) +#define UART_1_I2C_CTRL_S_READY_DATA_ACK ((uint32) 0x01u << \ + UART_1_I2C_CTRL_S_READY_DATA_ACK_POS) +#define UART_1_I2C_CTRL_S_NOT_READY_ADDR_NACK ((uint32) 0x01u << \ + UART_1_I2C_CTRL_S_NOT_READY_ADDR_NACK_POS) +#define UART_1_I2C_CTRL_S_NOT_READY_DATA_NACK ((uint32) 0x01u << \ + UART_1_I2C_CTRL_S_NOT_READY_DATA_NACK_POS) +#define UART_1_I2C_CTRL_LOOPBACK ((uint32) 0x01u << \ + UART_1_I2C_CTRL_LOOPBACK_POS) +#define UART_1_I2C_CTRL_SLAVE_MODE ((uint32) 0x01u << \ + UART_1_I2C_CTRL_SLAVE_MODE_POS) +#define UART_1_I2C_CTRL_MASTER_MODE ((uint32) 0x01u << \ + UART_1_I2C_CTRL_MASTER_MODE_POS) +#define UART_1_I2C_CTRL_SLAVE_MASTER_MODE_MASK ((uint32) 0x03u << \ + UART_1_I2C_CTRL_SLAVE_MODE_POS) + +/* UART_1_I2C_STATUS_REG */ +#define UART_1_I2C_STATUS_BUS_BUSY_POS (0u) /* [0] Bus busy: internally clocked */ +#define UART_1_I2C_STATUS_S_READ_POS (4u) /* [4] Slave is read by master */ +#define UART_1_I2C_STATUS_M_READ_POS (5u) /* [5] Master reads Slave */ +#define UART_1_I2C_STATUS_EZBUF_ADDR_POS (8u) /* [15:8] EZAddress */ +#define UART_1_I2C_STATUS_BUS_BUSY ((uint32) 0x01u) +#define UART_1_I2C_STATUS_S_READ ((uint32) 0x01u << UART_1_I2C_STATUS_S_READ_POS) +#define UART_1_I2C_STATUS_M_READ ((uint32) 0x01u << UART_1_I2C_STATUS_M_READ_POS) +#define UART_1_I2C_STATUS_EZBUF_ADDR_MASK ((uint32) 0xFFu << UART_1_I2C_STATUS_EZBUF_ADDR_POS) + +/* UART_1_I2C_MASTER_CMD_REG */ +#define UART_1_I2C_MASTER_CMD_M_START_POS (0u) /* [0] Master generate Start */ +#define UART_1_I2C_MASTER_CMD_M_START_ON_IDLE_POS (1u) /* [1] Master generate Start if bus is free */ +#define UART_1_I2C_MASTER_CMD_M_ACK_POS (2u) /* [2] Master generate ACK */ +#define UART_1_I2C_MASTER_CMD_M_NACK_POS (3u) /* [3] Master generate NACK */ +#define UART_1_I2C_MASTER_CMD_M_STOP_POS (4u) /* [4] Master generate Stop */ +#define UART_1_I2C_MASTER_CMD_M_START ((uint32) 0x01u) +#define UART_1_I2C_MASTER_CMD_M_START_ON_IDLE ((uint32) 0x01u << \ + UART_1_I2C_MASTER_CMD_M_START_ON_IDLE_POS) +#define UART_1_I2C_MASTER_CMD_M_ACK ((uint32) 0x01u << \ + UART_1_I2C_MASTER_CMD_M_ACK_POS) +#define UART_1_I2C_MASTER_CMD_M_NACK ((uint32) 0x01u << \ + UART_1_I2C_MASTER_CMD_M_NACK_POS) +#define UART_1_I2C_MASTER_CMD_M_STOP ((uint32) 0x01u << \ + UART_1_I2C_MASTER_CMD_M_STOP_POS) + +/* UART_1_I2C_SLAVE_CMD_REG */ +#define UART_1_I2C_SLAVE_CMD_S_ACK_POS (0u) /* [0] Slave generate ACK */ +#define UART_1_I2C_SLAVE_CMD_S_NACK_POS (1u) /* [1] Slave generate NACK */ +#define UART_1_I2C_SLAVE_CMD_S_ACK ((uint32) 0x01u) +#define UART_1_I2C_SLAVE_CMD_S_NACK ((uint32) 0x01u << UART_1_I2C_SLAVE_CMD_S_NACK_POS) + +#define UART_1_I2C_SLAVE_CMD_S_ACK_POS (0u) /* [0] Slave generate ACK */ +#define UART_1_I2C_SLAVE_CMD_S_NACK_POS (1u) /* [1] Slave generate NACK */ +#define UART_1_I2C_SLAVE_CMD_S_ACK ((uint32) 0x01u) +#define UART_1_I2C_SLAVE_CMD_S_NACK ((uint32) 0x01u << UART_1_I2C_SLAVE_CMD_S_NACK_POS) + +/* UART_1_I2C_CFG_REG */ +#if (UART_1_CY_SCBIP_V0) +#define UART_1_I2C_CFG_SDA_FILT_HYS_POS (0u) /* [1:0] Trim bits for the I2C SDA filter */ +#define UART_1_I2C_CFG_SDA_FILT_TRIM_POS (2u) /* [3:2] Trim bits for the I2C SDA filter */ +#define UART_1_I2C_CFG_SCL_FILT_HYS_POS (4u) /* [5:4] Trim bits for the I2C SCL filter */ +#define UART_1_I2C_CFG_SCL_FILT_TRIM_POS (6u) /* [7:6] Trim bits for the I2C SCL filter */ +#define UART_1_I2C_CFG_SDA_FILT_OUT_HYS_POS (8u) /* [9:8] Trim bits for I2C SDA filter output path */ +#define UART_1_I2C_CFG_SDA_FILT_OUT_TRIM_POS (10u) /* [11:10] Trim bits for I2C SDA filter output path */ +#define UART_1_I2C_CFG_SDA_FILT_HS_POS (16u) /* [16] '0': 50 ns filter, '1': 10 ns filter */ +#define UART_1_I2C_CFG_SDA_FILT_ENABLED_POS (17u) /* [17] I2C SDA filter enabled */ +#define UART_1_I2C_CFG_SCL_FILT_HS_POS (24u) /* [24] '0': 50 ns filter, '1': 10 ns filter */ +#define UART_1_I2C_CFG_SCL_FILT_ENABLED_POS (25u) /* [25] I2C SCL filter enabled */ +#define UART_1_I2C_CFG_SDA_FILT_OUT_HS_POS (26u) /* [26] '0': 50 ns filter, '1': 10 ns filter */ +#define UART_1_I2C_CFG_SDA_FILT_OUT_ENABLED_POS (27u) /* [27] I2C SDA output delay filter enabled */ +#define UART_1_I2C_CFG_SDA_FILT_HYS_MASK ((uint32) 0x03u) +#define UART_1_I2C_CFG_SDA_FILT_TRIM_MASK ((uint32) 0x03u << \ + UART_1_I2C_CFG_SDA_FILT_TRIM_POS) +#define UART_1_I2C_CFG_SCL_FILT_HYS_MASK ((uint32) 0x03u << \ + UART_1_I2C_CFG_SCL_FILT_HYS_POS) +#define UART_1_I2C_CFG_SCL_FILT_TRIM_MASK ((uint32) 0x03u << \ + UART_1_I2C_CFG_SCL_FILT_TRIM_POS) +#define UART_1_I2C_CFG_SDA_FILT_OUT_HYS_MASK ((uint32) 0x03u << \ + UART_1_I2C_CFG_SDA_FILT_OUT_HYS_POS) +#define UART_1_I2C_CFG_SDA_FILT_OUT_TRIM_MASK ((uint32) 0x03u << \ + UART_1_I2C_CFG_SDA_FILT_OUT_TRIM_POS) +#define UART_1_I2C_CFG_SDA_FILT_HS ((uint32) 0x01u << \ + UART_1_I2C_CFG_SDA_FILT_HS_POS) +#define UART_1_I2C_CFG_SDA_FILT_ENABLED ((uint32) 0x01u << \ + UART_1_I2C_CFG_SDA_FILT_ENABLED_POS) +#define UART_1_I2C_CFG_SCL_FILT_HS ((uint32) 0x01u << \ + UART_1_I2C_CFG_SCL_FILT_HS_POS) +#define UART_1_I2C_CFG_SCL_FILT_ENABLED ((uint32) 0x01u << \ + UART_1_I2C_CFG_SCL_FILT_ENABLED_POS) +#define UART_1_I2C_CFG_SDA_FILT_OUT_HS ((uint32) 0x01u << \ + UART_1_I2C_CFG_SDA_FILT_OUT_HS_POS) +#define UART_1_I2C_CFG_SDA_FILT_OUT_ENABLED ((uint32) 0x01u << \ + UART_1_I2C_CFG_SDA_FILT_OUT_ENABLED_POS) +#else +#define UART_1_I2C_CFG_SDA_IN_FILT_TRIM_POS (0u) /* [1:0] Trim bits for "i2c_sda_in" 50 ns filter */ +#define UART_1_I2C_CFG_SDA_IN_FILT_SEL_POS (4u) /* [4] "i2c_sda_in" filter delay: 0 ns and 50 ns */ +#define UART_1_I2C_CFG_SCL_IN_FILT_TRIM_POS (8u) /* [9:8] Trim bits for "i2c_scl_in" 50 ns filter */ +#define UART_1_I2C_CFG_SCL_IN_FILT_SEL_POS (12u) /* [12] "i2c_scl_in" filter delay: 0 ns and 50 ns */ +#define UART_1_I2C_CFG_SDA_OUT_FILT0_TRIM_POS (16u) /* [17:16] Trim bits for "i2c_sda_out" 50 ns filter 0 */ +#define UART_1_I2C_CFG_SDA_OUT_FILT1_TRIM_POS (18u) /* [19:18] Trim bits for "i2c_sda_out" 50 ns filter 1 */ +#define UART_1_I2C_CFG_SDA_OUT_FILT2_TRIM_POS (20u) /* [21:20] Trim bits for "i2c_sda_out" 50 ns filter 2 */ +#define UART_1_I2C_CFG_SDA_OUT_FILT_SEL_POS (28u) /* [29:28] Cumulative "i2c_sda_out" filter delay: */ + +#define UART_1_I2C_CFG_SDA_IN_FILT_TRIM_MASK ((uint32) 0x03u) +#define UART_1_I2C_CFG_SDA_IN_FILT_SEL ((uint32) 0x01u << UART_1_I2C_CFG_SDA_IN_FILT_SEL_POS) +#define UART_1_I2C_CFG_SCL_IN_FILT_TRIM_MASK ((uint32) 0x03u << \ + UART_1_I2C_CFG_SCL_IN_FILT_TRIM_POS) +#define UART_1_I2C_CFG_SCL_IN_FILT_SEL ((uint32) 0x01u << UART_1_I2C_CFG_SCL_IN_FILT_SEL_POS) +#define UART_1_I2C_CFG_SDA_OUT_FILT0_TRIM_MASK ((uint32) 0x03u << \ + UART_1_I2C_CFG_SDA_OUT_FILT0_TRIM_POS) +#define UART_1_I2C_CFG_SDA_OUT_FILT1_TRIM_MASK ((uint32) 0x03u << \ + UART_1_I2C_CFG_SDA_OUT_FILT1_TRIM_POS) +#define UART_1_I2C_CFG_SDA_OUT_FILT2_TRIM_MASK ((uint32) 0x03u << \ + UART_1_I2C_CFG_SDA_OUT_FILT2_TRIM_POS) +#define UART_1_I2C_CFG_SDA_OUT_FILT_SEL_MASK ((uint32) 0x03u << \ + UART_1_I2C_CFG_SDA_OUT_FILT_SEL_POS) +#endif /* (UART_1_CY_SCBIP_V0) */ + + +/* UART_1_TX_CTRL_REG */ +#define UART_1_TX_CTRL_DATA_WIDTH_POS (0u) /* [3:0] Data frame width: (Data width - 1) */ +#define UART_1_TX_CTRL_MSB_FIRST_POS (8u) /* [8] MSB first shifter-out */ +#define UART_1_TX_CTRL_ENABLED_POS (31u) /* [31] Transmitter enabled */ +#define UART_1_TX_CTRL_DATA_WIDTH_MASK ((uint32) 0x0Fu) +#define UART_1_TX_CTRL_MSB_FIRST ((uint32) 0x01u << UART_1_TX_CTRL_MSB_FIRST_POS) +#define UART_1_TX_CTRL_LSB_FIRST ((uint32) 0x00u) +#define UART_1_TX_CTRL_ENABLED ((uint32) 0x01u << UART_1_TX_CTRL_ENABLED_POS) + +/* UART_1_TX_CTRL_FIFO_REG */ +#define UART_1_TX_FIFO_CTRL_TRIGGER_LEVEL_POS (0u) /* [2:0] Trigger level */ +#define UART_1_TX_FIFO_CTRL_CLEAR_POS (16u) /* [16] Clear TX FIFO: cleared after set */ +#define UART_1_TX_FIFO_CTRL_FREEZE_POS (17u) /* [17] Freeze TX FIFO: HW do not inc read pointer */ +#define UART_1_TX_FIFO_CTRL_TRIGGER_LEVEL_MASK ((uint32) UART_1_FF_DATA_NR_LOG2_MASK) +#define UART_1_TX_FIFO_CTRL_CLEAR ((uint32) 0x01u << UART_1_TX_FIFO_CTRL_CLEAR_POS) +#define UART_1_TX_FIFO_CTRL_FREEZE ((uint32) 0x01u << UART_1_TX_FIFO_CTRL_FREEZE_POS) + +/* UART_1_TX_FIFO_STATUS_REG */ +#define UART_1_TX_FIFO_STATUS_USED_POS (0u) /* [3:0] Amount of entries in TX FIFO */ +#define UART_1_TX_FIFO_SR_VALID_POS (15u) /* [15] Shifter status of TX FIFO */ +#define UART_1_TX_FIFO_STATUS_RD_PTR_POS (16u) /* [18:16] TX FIFO read pointer */ +#define UART_1_TX_FIFO_STATUS_WR_PTR_POS (24u) /* [26:24] TX FIFO write pointer */ +#define UART_1_TX_FIFO_STATUS_USED_MASK ((uint32) UART_1_FF_DATA_NR_LOG2_PLUS1_MASK) +#define UART_1_TX_FIFO_SR_VALID ((uint32) 0x01u << UART_1_TX_FIFO_SR_VALID_POS) +#define UART_1_TX_FIFO_STATUS_RD_PTR_MASK ((uint32) UART_1_FF_DATA_NR_LOG2_MASK << \ + UART_1_TX_FIFO_STATUS_RD_PTR_POS) +#define UART_1_TX_FIFO_STATUS_WR_PTR_MASK ((uint32) UART_1_FF_DATA_NR_LOG2_MASK << \ + UART_1_TX_FIFO_STATUS_WR_PTR_POS) + +/* UART_1_TX_FIFO_WR_REG */ +#define UART_1_TX_FIFO_WR_POS (0u) /* [15:0] Data written into TX FIFO */ +#define UART_1_TX_FIFO_WR_MASK ((uint32) 0xFFu) + +/* UART_1_RX_CTRL_REG */ +#define UART_1_RX_CTRL_DATA_WIDTH_POS (0u) /* [3:0] Data frame width: (Data width - 1) */ +#define UART_1_RX_CTRL_MSB_FIRST_POS (8u) /* [8] MSB first shifter-out */ +#define UART_1_RX_CTRL_MEDIAN_POS (9u) /* [9] Median filter */ +#define UART_1_RX_CTRL_ENABLED_POS (31u) /* [31] Receiver enabled */ +#define UART_1_RX_CTRL_DATA_WIDTH_MASK ((uint32) 0x0Fu) +#define UART_1_RX_CTRL_MSB_FIRST ((uint32) 0x01u << UART_1_RX_CTRL_MSB_FIRST_POS) +#define UART_1_RX_CTRL_LSB_FIRST ((uint32) 0x00u) +#define UART_1_RX_CTRL_MEDIAN ((uint32) 0x01u << UART_1_RX_CTRL_MEDIAN_POS) +#define UART_1_RX_CTRL_ENABLED ((uint32) 0x01u << UART_1_RX_CTRL_ENABLED_POS) + + +/* UART_1_RX_FIFO_CTRL_REG */ +#define UART_1_RX_FIFO_CTRL_TRIGGER_LEVEL_POS (0u) /* [2:0] Trigger level */ +#define UART_1_RX_FIFO_CTRL_CLEAR_POS (16u) /* [16] Clear RX FIFO: clear after set */ +#define UART_1_RX_FIFO_CTRL_FREEZE_POS (17u) /* [17] Freeze RX FIFO: HW writes has not effect */ +#define UART_1_RX_FIFO_CTRL_TRIGGER_LEVEL_MASK ((uint32) UART_1_FF_DATA_NR_LOG2_MASK) +#define UART_1_RX_FIFO_CTRL_CLEAR ((uint32) 0x01u << UART_1_RX_FIFO_CTRL_CLEAR_POS) +#define UART_1_RX_FIFO_CTRL_FREEZE ((uint32) 0x01u << UART_1_RX_FIFO_CTRL_FREEZE_POS) + +/* UART_1_RX_FIFO_STATUS_REG */ +#define UART_1_RX_FIFO_STATUS_USED_POS (0u) /* [3:0] Amount of entries in RX FIFO */ +#define UART_1_RX_FIFO_SR_VALID_POS (15u) /* [15] Shifter status of RX FIFO */ +#define UART_1_RX_FIFO_STATUS_RD_PTR_POS (16u) /* [18:16] RX FIFO read pointer */ +#define UART_1_RX_FIFO_STATUS_WR_PTR_POS (24u) /* [26:24] RX FIFO write pointer */ +#define UART_1_RX_FIFO_STATUS_USED_MASK ((uint32) UART_1_FF_DATA_NR_LOG2_PLUS1_MASK) +#define UART_1_RX_FIFO_SR_VALID ((uint32) 0x01u << UART_1_RX_FIFO_SR_VALID_POS) +#define UART_1_RX_FIFO_STATUS_RD_PTR_MASK ((uint32) UART_1_FF_DATA_NR_LOG2_MASK << \ + UART_1_RX_FIFO_STATUS_RD_PTR_POS) +#define UART_1_RX_FIFO_STATUS_WR_PTR_MASK ((uint32) UART_1_FF_DATA_NR_LOG2_MASK << \ + UART_1_RX_FIFO_STATUS_WR_PTR_POS) + +/* UART_1_RX_MATCH_REG */ +#define UART_1_RX_MATCH_ADDR_POS (0u) /* [7:0] Slave address */ +#define UART_1_RX_MATCH_MASK_POS (16u) /* [23:16] Slave address mask: 0 - doesn't care */ +#define UART_1_RX_MATCH_ADDR_MASK ((uint32) 0xFFu) +#define UART_1_RX_MATCH_MASK_MASK ((uint32) 0xFFu << UART_1_RX_MATCH_MASK_POS) + +/* UART_1_RX_FIFO_WR_REG */ +#define UART_1_RX_FIFO_RD_POS (0u) /* [15:0] Data read from RX FIFO */ +#define UART_1_RX_FIFO_RD_MASK ((uint32) 0xFFu) + +/* UART_1_RX_FIFO_RD_SILENT_REG */ +#define UART_1_RX_FIFO_RD_SILENT_POS (0u) /* [15:0] Data read from RX FIFO: not remove data from FIFO */ +#define UART_1_RX_FIFO_RD_SILENT_MASK ((uint32) 0xFFu) + +/* UART_1_RX_FIFO_RD_SILENT_REG */ +#define UART_1_RX_FIFO_RD_SILENT_POS (0u) /* [15:0] Data read from RX FIFO: not remove data from FIFO */ +#define UART_1_RX_FIFO_RD_SILENT_MASK ((uint32) 0xFFu) + +/* UART_1_EZBUF_DATA_REG */ +#define UART_1_EZBUF_DATA_POS (0u) /* [7:0] Data from EZ Memory */ +#define UART_1_EZBUF_DATA_MASK ((uint32) 0xFFu) + +/* UART_1_INTR_CAUSE_REG */ +#define UART_1_INTR_CAUSE_MASTER_POS (0u) /* [0] Master interrupt active */ +#define UART_1_INTR_CAUSE_SLAVE_POS (1u) /* [1] Slave interrupt active */ +#define UART_1_INTR_CAUSE_TX_POS (2u) /* [2] Transmitter interrupt active */ +#define UART_1_INTR_CAUSE_RX_POS (3u) /* [3] Receiver interrupt active */ +#define UART_1_INTR_CAUSE_I2C_EC_POS (4u) /* [4] Externally clock I2C interrupt active */ +#define UART_1_INTR_CAUSE_SPI_EC_POS (5u) /* [5] Externally clocked SPI interrupt active */ +#define UART_1_INTR_CAUSE_MASTER ((uint32) 0x01u) +#define UART_1_INTR_CAUSE_SLAVE ((uint32) 0x01u << UART_1_INTR_CAUSE_SLAVE_POS) +#define UART_1_INTR_CAUSE_TX ((uint32) 0x01u << UART_1_INTR_CAUSE_TX_POS) +#define UART_1_INTR_CAUSE_RX ((uint32) 0x01u << UART_1_INTR_CAUSE_RX_POS) +#define UART_1_INTR_CAUSE_I2C_EC ((uint32) 0x01u << UART_1_INTR_CAUSE_I2C_EC_POS) +#define UART_1_INTR_CAUSE_SPI_EC ((uint32) 0x01u << UART_1_INTR_CAUSE_SPI_EC_POS) + +/* UART_1_INTR_SPI_EC_REG, UART_1_INTR_SPI_EC_MASK_REG, UART_1_INTR_SPI_EC_MASKED_REG */ +#define UART_1_INTR_SPI_EC_WAKE_UP_POS (0u) /* [0] Address match: triggers wakeup of chip */ +#define UART_1_INTR_SPI_EC_EZBUF_STOP_POS (1u) /* [1] Externally clocked Stop detected */ +#define UART_1_INTR_SPI_EC_EZBUF_WRITE_STOP_POS (2u) /* [2] Externally clocked Write Stop detected */ +#define UART_1_INTR_SPI_EC_WAKE_UP ((uint32) 0x01u) +#define UART_1_INTR_SPI_EC_EZBUF_STOP ((uint32) 0x01u << \ + UART_1_INTR_SPI_EC_EZBUF_STOP_POS) +#define UART_1_INTR_SPI_EC_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + UART_1_INTR_SPI_EC_EZBUF_WRITE_STOP_POS) + +/* UART_1_INTR_I2C_EC, UART_1_INTR_I2C_EC_MASK, UART_1_INTR_I2C_EC_MASKED */ +#define UART_1_INTR_I2C_EC_WAKE_UP_POS (0u) /* [0] Address match: triggers wakeup of chip */ +#define UART_1_INTR_I2C_EC_EZBUF_STOP_POS (1u) /* [1] Externally clocked Stop detected */ +#define UART_1_INTR_I2C_EC_EZBUF_WRITE_STOP_POS (2u) /* [2] Externally clocked Write Stop detected */ +#define UART_1_INTR_I2C_EC_WAKE_UP ((uint32) 0x01u) +#define UART_1_INTR_I2C_EC_EZBUF_STOP ((uint32) 0x01u << \ + UART_1_INTR_I2C_EC_EZBUF_STOP_POS) +#define UART_1_INTR_I2C_EC_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + UART_1_INTR_I2C_EC_EZBUF_WRITE_STOP_POS) + +/* UART_1_INTR_MASTER, UART_1_INTR_MASTER_SET, + UART_1_INTR_MASTER_MASK, UART_1_INTR_MASTER_MASKED */ +#define UART_1_INTR_MASTER_I2C_ARB_LOST_POS (0u) /* [0] Master lost arbitration */ +#define UART_1_INTR_MASTER_I2C_NACK_POS (1u) /* [1] Master receives NACK: address or write to slave */ +#define UART_1_INTR_MASTER_I2C_ACK_POS (2u) /* [2] Master receives NACK: address or write to slave */ +#define UART_1_INTR_MASTER_I2C_STOP_POS (4u) /* [4] Master detects the Stop: only self generated Stop*/ +#define UART_1_INTR_MASTER_I2C_BUS_ERROR_POS (8u) /* [8] Master detects bus error: misplaced Start or Stop*/ +#define UART_1_INTR_MASTER_SPI_DONE_POS (9u) /* [9] Master complete transfer: Only for SPI */ +#define UART_1_INTR_MASTER_I2C_ARB_LOST ((uint32) 0x01u) +#define UART_1_INTR_MASTER_I2C_NACK ((uint32) 0x01u << UART_1_INTR_MASTER_I2C_NACK_POS) +#define UART_1_INTR_MASTER_I2C_ACK ((uint32) 0x01u << UART_1_INTR_MASTER_I2C_ACK_POS) +#define UART_1_INTR_MASTER_I2C_STOP ((uint32) 0x01u << UART_1_INTR_MASTER_I2C_STOP_POS) +#define UART_1_INTR_MASTER_I2C_BUS_ERROR ((uint32) 0x01u << \ + UART_1_INTR_MASTER_I2C_BUS_ERROR_POS) +#define UART_1_INTR_MASTER_SPI_DONE ((uint32) 0x01u << UART_1_INTR_MASTER_SPI_DONE_POS) + +/* +* UART_1_INTR_SLAVE, UART_1_INTR_SLAVE_SET, +* UART_1_INTR_SLAVE_MASK, UART_1_INTR_SLAVE_MASKED +*/ +#define UART_1_INTR_SLAVE_I2C_ARB_LOST_POS (0u) /* [0] Slave lost arbitration */ +#define UART_1_INTR_SLAVE_I2C_NACK_POS (1u) /* [1] Slave receives NACK: master reads data */ +#define UART_1_INTR_SLAVE_I2C_ACK_POS (2u) /* [2] Slave receives ACK: master reads data */ +#define UART_1_INTR_SLAVE_I2C_WRITE_STOP_POS (3u) /* [3] Slave detects end of write transaction */ +#define UART_1_INTR_SLAVE_I2C_STOP_POS (4u) /* [4] Slave detects end of transaction intended */ +#define UART_1_INTR_SLAVE_I2C_START_POS (5u) /* [5] Slave detects Start */ +#define UART_1_INTR_SLAVE_I2C_ADDR_MATCH_POS (6u) /* [6] Slave address matches */ +#define UART_1_INTR_SLAVE_I2C_GENERAL_POS (7u) /* [7] General call received */ +#define UART_1_INTR_SLAVE_I2C_BUS_ERROR_POS (8u) /* [8] Slave detects bus error */ +#define UART_1_INTR_SLAVE_SPI_EZBUF_WRITE_STOP_POS (9u) /* [9] Slave write complete: Only for SPI */ +#define UART_1_INTR_SLAVE_SPI_EZBUF_STOP_POS (10u) /* [10] Slave end of transaction: Only for SPI */ +#define UART_1_INTR_SLAVE_SPI_BUS_ERROR_POS (11u) /* [11] Slave detects bus error: Only for SPI */ +#define UART_1_INTR_SLAVE_I2C_ARB_LOST ((uint32) 0x01u) +#define UART_1_INTR_SLAVE_I2C_NACK ((uint32) 0x01u << \ + UART_1_INTR_SLAVE_I2C_NACK_POS) +#define UART_1_INTR_SLAVE_I2C_ACK ((uint32) 0x01u << \ + UART_1_INTR_SLAVE_I2C_ACK_POS) +#define UART_1_INTR_SLAVE_I2C_WRITE_STOP ((uint32) 0x01u << \ + UART_1_INTR_SLAVE_I2C_WRITE_STOP_POS) +#define UART_1_INTR_SLAVE_I2C_STOP ((uint32) 0x01u << \ + UART_1_INTR_SLAVE_I2C_STOP_POS) +#define UART_1_INTR_SLAVE_I2C_START ((uint32) 0x01u << \ + UART_1_INTR_SLAVE_I2C_START_POS) +#define UART_1_INTR_SLAVE_I2C_ADDR_MATCH ((uint32) 0x01u << \ + UART_1_INTR_SLAVE_I2C_ADDR_MATCH_POS) +#define UART_1_INTR_SLAVE_I2C_GENERAL ((uint32) 0x01u << \ + UART_1_INTR_SLAVE_I2C_GENERAL_POS) +#define UART_1_INTR_SLAVE_I2C_BUS_ERROR ((uint32) 0x01u << \ + UART_1_INTR_SLAVE_I2C_BUS_ERROR_POS) +#define UART_1_INTR_SLAVE_SPI_EZBUF_WRITE_STOP ((uint32) 0x01u << \ + UART_1_INTR_SLAVE_SPI_EZBUF_WRITE_STOP_POS) +#define UART_1_INTR_SLAVE_SPI_EZBUF_STOP ((uint32) 0x01u << \ + UART_1_INTR_SLAVE_SPI_EZBUF_STOP_POS) +#define UART_1_INTR_SLAVE_SPI_BUS_ERROR ((uint32) 0x01u << \ + UART_1_INTR_SLAVE_SPI_BUS_ERROR_POS) + +/* +* UART_1_INTR_TX, UART_1_INTR_TX_SET, +* UART_1_INTR_TX_MASK, UART_1_INTR_TX_MASKED +*/ +#define UART_1_INTR_TX_TRIGGER_POS (0u) /* [0] Trigger on TX FIFO entires */ +#define UART_1_INTR_TX_NOT_FULL_POS (1u) /* [1] TX FIFO is not full */ +#define UART_1_INTR_TX_EMPTY_POS (4u) /* [4] TX FIFO is empty */ +#define UART_1_INTR_TX_OVERFLOW_POS (5u) /* [5] Attempt to write to a full TX FIFO */ +#define UART_1_INTR_TX_UNDERFLOW_POS (6u) /* [6] Attempt to read from an empty TX FIFO */ +#define UART_1_INTR_TX_BLOCKED_POS (7u) /* [7] No access to the EZ memory */ +#define UART_1_INTR_TX_UART_NACK_POS (8u) /* [8] UART transmitter received a NACK: SmartCard mode */ +#define UART_1_INTR_TX_UART_DONE_POS (9u) /* [9] UART transmitter done even */ +#define UART_1_INTR_TX_UART_ARB_LOST_POS (10u) /* [10] UART lost arbitration: LIN or SmartCard */ +#define UART_1_INTR_TX_TRIGGER ((uint32) 0x01u) +#define UART_1_INTR_TX_FIFO_LEVEL (UART_1_INTR_TX_TRIGGER) +#define UART_1_INTR_TX_NOT_FULL ((uint32) 0x01u << UART_1_INTR_TX_NOT_FULL_POS) +#define UART_1_INTR_TX_EMPTY ((uint32) 0x01u << UART_1_INTR_TX_EMPTY_POS) +#define UART_1_INTR_TX_OVERFLOW ((uint32) 0x01u << UART_1_INTR_TX_OVERFLOW_POS) +#define UART_1_INTR_TX_UNDERFLOW ((uint32) 0x01u << UART_1_INTR_TX_UNDERFLOW_POS) +#define UART_1_INTR_TX_BLOCKED ((uint32) 0x01u << UART_1_INTR_TX_BLOCKED_POS) +#define UART_1_INTR_TX_UART_NACK ((uint32) 0x01u << UART_1_INTR_TX_UART_NACK_POS) +#define UART_1_INTR_TX_UART_DONE ((uint32) 0x01u << UART_1_INTR_TX_UART_DONE_POS) +#define UART_1_INTR_TX_UART_ARB_LOST ((uint32) 0x01u << UART_1_INTR_TX_UART_ARB_LOST_POS) + +/* +* UART_1_INTR_RX, UART_1_INTR_RX_SET, +* UART_1_INTR_RX_MASK, UART_1_INTR_RX_MASKED +*/ +#define UART_1_INTR_RX_TRIGGER_POS (0u) /* [0] Trigger on RX FIFO entires */ +#define UART_1_INTR_RX_NOT_EMPTY_POS (2u) /* [2] RX FIFO is not empty */ +#define UART_1_INTR_RX_FULL_POS (3u) /* [3] RX FIFO is full */ +#define UART_1_INTR_RX_OVERFLOW_POS (5u) /* [5] Attempt to write to a full RX FIFO */ +#define UART_1_INTR_RX_UNDERFLOW_POS (6u) /* [6] Attempt to read from an empty RX FIFO */ +#define UART_1_INTR_RX_BLOCKED_POS (7u) /* [7] No access to the EZ memory */ +#define UART_1_INTR_RX_FRAME_ERROR_POS (8u) /* [8] Frame error in received data frame */ +#define UART_1_INTR_RX_PARITY_ERROR_POS (9u) /* [9] Parity error in received data frame */ +#define UART_1_INTR_RX_BAUD_DETECT_POS (10u) /* [10] LIN baud rate detection is completed */ +#define UART_1_INTR_RX_BREAK_DETECT_POS (11u) /* [11] Break detection is successful */ +#define UART_1_INTR_RX_TRIGGER ((uint32) 0x01u) +#define UART_1_INTR_RX_FIFO_LEVEL (UART_1_INTR_RX_TRIGGER) +#define UART_1_INTR_RX_NOT_EMPTY ((uint32) 0x01u << UART_1_INTR_RX_NOT_EMPTY_POS) +#define UART_1_INTR_RX_FULL ((uint32) 0x01u << UART_1_INTR_RX_FULL_POS) +#define UART_1_INTR_RX_OVERFLOW ((uint32) 0x01u << UART_1_INTR_RX_OVERFLOW_POS) +#define UART_1_INTR_RX_UNDERFLOW ((uint32) 0x01u << UART_1_INTR_RX_UNDERFLOW_POS) +#define UART_1_INTR_RX_BLOCKED ((uint32) 0x01u << UART_1_INTR_RX_BLOCKED_POS) +#define UART_1_INTR_RX_FRAME_ERROR ((uint32) 0x01u << UART_1_INTR_RX_FRAME_ERROR_POS) +#define UART_1_INTR_RX_PARITY_ERROR ((uint32) 0x01u << UART_1_INTR_RX_PARITY_ERROR_POS) +#define UART_1_INTR_RX_BAUD_DETECT ((uint32) 0x01u << UART_1_INTR_RX_BAUD_DETECT_POS) +#define UART_1_INTR_RX_BREAK_DETECT ((uint32) 0x01u << UART_1_INTR_RX_BREAK_DETECT_POS) + +/* Define all interrupt sources */ +#define UART_1_INTR_I2C_EC_ALL (UART_1_INTR_I2C_EC_WAKE_UP | \ + UART_1_INTR_I2C_EC_EZBUF_STOP | \ + UART_1_INTR_I2C_EC_EZBUF_WRITE_STOP) + +#define UART_1_INTR_SPI_EC_ALL (UART_1_INTR_SPI_EC_WAKE_UP | \ + UART_1_INTR_SPI_EC_EZBUF_STOP | \ + UART_1_INTR_SPI_EC_EZBUF_WRITE_STOP) + +#define UART_1_INTR_MASTER_ALL (UART_1_INTR_MASTER_I2C_ARB_LOST | \ + UART_1_INTR_MASTER_I2C_NACK | \ + UART_1_INTR_MASTER_I2C_ACK | \ + UART_1_INTR_MASTER_I2C_STOP | \ + UART_1_INTR_MASTER_I2C_BUS_ERROR | \ + UART_1_INTR_MASTER_SPI_DONE) + +#define UART_1_INTR_SLAVE_ALL (UART_1_INTR_SLAVE_I2C_ARB_LOST | \ + UART_1_INTR_SLAVE_I2C_NACK | \ + UART_1_INTR_SLAVE_I2C_ACK | \ + UART_1_INTR_SLAVE_I2C_WRITE_STOP | \ + UART_1_INTR_SLAVE_I2C_STOP | \ + UART_1_INTR_SLAVE_I2C_START | \ + UART_1_INTR_SLAVE_I2C_ADDR_MATCH | \ + UART_1_INTR_SLAVE_I2C_GENERAL | \ + UART_1_INTR_SLAVE_I2C_BUS_ERROR | \ + UART_1_INTR_SLAVE_SPI_EZBUF_WRITE_STOP | \ + UART_1_INTR_SLAVE_SPI_EZBUF_STOP | \ + UART_1_INTR_SLAVE_SPI_BUS_ERROR) + +#define UART_1_INTR_TX_ALL (UART_1_INTR_TX_TRIGGER | \ + UART_1_INTR_TX_NOT_FULL | \ + UART_1_INTR_TX_EMPTY | \ + UART_1_INTR_TX_OVERFLOW | \ + UART_1_INTR_TX_UNDERFLOW | \ + UART_1_INTR_TX_BLOCKED | \ + UART_1_INTR_TX_UART_NACK | \ + UART_1_INTR_TX_UART_DONE | \ + UART_1_INTR_TX_UART_ARB_LOST) + +#define UART_1_INTR_RX_ALL (UART_1_INTR_RX_TRIGGER | \ + UART_1_INTR_RX_NOT_EMPTY | \ + UART_1_INTR_RX_FULL | \ + UART_1_INTR_RX_OVERFLOW | \ + UART_1_INTR_RX_UNDERFLOW | \ + UART_1_INTR_RX_BLOCKED | \ + UART_1_INTR_RX_FRAME_ERROR | \ + UART_1_INTR_RX_PARITY_ERROR | \ + UART_1_INTR_RX_BAUD_DETECT | \ + UART_1_INTR_RX_BREAK_DETECT) + +/* I2C and EZI2C slave address defines */ +#define UART_1_I2C_SLAVE_ADDR_POS (0x01u) /* 7-bit address shift */ +#define UART_1_I2C_SLAVE_ADDR_MASK (0xFEu) /* 8-bit address mask */ + +/* OVS constants for IrDA Low Power operation */ +#define UART_1_CTRL_OVS_IRDA_LP_OVS16 (0x00u) +#define UART_1_CTRL_OVS_IRDA_LP_OVS32 (0x01u) +#define UART_1_CTRL_OVS_IRDA_LP_OVS48 (0x02u) +#define UART_1_CTRL_OVS_IRDA_LP_OVS96 (0x03u) +#define UART_1_CTRL_OVS_IRDA_LP_OVS192 (0x04u) +#define UART_1_CTRL_OVS_IRDA_LP_OVS768 (0x05u) +#define UART_1_CTRL_OVS_IRDA_LP_OVS1536 (0x06u) + +/* OVS constant for IrDA */ +#define UART_1_CTRL_OVS_IRDA_OVS16 (UART_1_UART_IRDA_LP_OVS16) + + +/*************************************** +* Common Macro Definitions +***************************************/ + +/* Re-enables the SCB IP. A clear enable bit has a different effect +* on the scb IP depending on the version: +* CY_SCBIP_V0: resets state, status, TX and RX FIFOs. +* CY_SCBIP_V1 or later: resets state, status, TX and RX FIFOs and interrupt sources. +* Clear I2C command registers are because they are not impacted by re-enable. +*/ +#define UART_1_SCB_SW_RESET UART_1_I2CFwBlockReset() + +/* TX FIFO macro */ +#define UART_1_CLEAR_TX_FIFO \ + do{ \ + UART_1_TX_FIFO_CTRL_REG |= ((uint32) UART_1_TX_FIFO_CTRL_CLEAR); \ + UART_1_TX_FIFO_CTRL_REG &= ((uint32) ~UART_1_TX_FIFO_CTRL_CLEAR); \ + }while(0) + +#define UART_1_GET_TX_FIFO_ENTRIES (UART_1_TX_FIFO_STATUS_REG & \ + UART_1_TX_FIFO_STATUS_USED_MASK) + +#define UART_1_GET_TX_FIFO_SR_VALID ((0u != (UART_1_TX_FIFO_STATUS_REG & \ + UART_1_TX_FIFO_SR_VALID)) ? (1u) : (0u)) + +/* RX FIFO macro */ +#define UART_1_CLEAR_RX_FIFO \ + do{ \ + UART_1_RX_FIFO_CTRL_REG |= ((uint32) UART_1_RX_FIFO_CTRL_CLEAR); \ + UART_1_RX_FIFO_CTRL_REG &= ((uint32) ~UART_1_RX_FIFO_CTRL_CLEAR); \ + }while(0) + +#define UART_1_GET_RX_FIFO_ENTRIES (UART_1_RX_FIFO_STATUS_REG & \ + UART_1_RX_FIFO_STATUS_USED_MASK) + +#define UART_1_GET_RX_FIFO_SR_VALID ((0u != (UART_1_RX_FIFO_STATUS_REG & \ + UART_1_RX_FIFO_SR_VALID)) ? (1u) : (0u)) + +/* Write interrupt source: set sourceMask bits in UART_1_INTR_X_MASK_REG */ +#define UART_1_WRITE_INTR_I2C_EC_MASK(sourceMask) \ + do{ \ + UART_1_INTR_I2C_EC_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#if (!UART_1_CY_SCBIP_V1) + #define UART_1_WRITE_INTR_SPI_EC_MASK(sourceMask) \ + do{ \ + UART_1_INTR_SPI_EC_MASK_REG = (uint32) (sourceMask); \ + }while(0) +#endif /* (!UART_1_CY_SCBIP_V1) */ + +#define UART_1_WRITE_INTR_MASTER_MASK(sourceMask) \ + do{ \ + UART_1_INTR_MASTER_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_1_WRITE_INTR_SLAVE_MASK(sourceMask) \ + do{ \ + UART_1_INTR_SLAVE_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_1_WRITE_INTR_TX_MASK(sourceMask) \ + do{ \ + UART_1_INTR_TX_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_1_WRITE_INTR_RX_MASK(sourceMask) \ + do{ \ + UART_1_INTR_RX_MASK_REG = (uint32) (sourceMask); \ + }while(0) + +/* Enable interrupt source: set sourceMask bits in UART_1_INTR_X_MASK_REG */ +#define UART_1_ENABLE_INTR_I2C_EC(sourceMask) \ + do{ \ + UART_1_INTR_I2C_EC_MASK_REG |= (uint32) (sourceMask); \ + }while(0) +#if (!UART_1_CY_SCBIP_V1) + #define UART_1_ENABLE_INTR_SPI_EC(sourceMask) \ + do{ \ + UART_1_INTR_SPI_EC_MASK_REG |= (uint32) (sourceMask); \ + }while(0) +#endif /* (!UART_1_CY_SCBIP_V1) */ + +#define UART_1_ENABLE_INTR_MASTER(sourceMask) \ + do{ \ + UART_1_INTR_MASTER_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define UART_1_ENABLE_INTR_SLAVE(sourceMask) \ + do{ \ + UART_1_INTR_SLAVE_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define UART_1_ENABLE_INTR_TX(sourceMask) \ + do{ \ + UART_1_INTR_TX_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +#define UART_1_ENABLE_INTR_RX(sourceMask) \ + do{ \ + UART_1_INTR_RX_MASK_REG |= (uint32) (sourceMask); \ + }while(0) + +/* Disable interrupt source: clear sourceMask bits in UART_1_INTR_X_MASK_REG */ +#define UART_1_DISABLE_INTR_I2C_EC(sourceMask) \ + do{ \ + UART_1_INTR_I2C_EC_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#if (!UART_1_CY_SCBIP_V1) + #define UART_1_DISABLE_INTR_SPI_EC(sourceMask) \ + do{ \ + UART_1_INTR_SPI_EC_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) +#endif /* (!UART_1_CY_SCBIP_V1) */ + +#define UART_1_DISABLE_INTR_MASTER(sourceMask) \ + do{ \ + UART_1_INTR_MASTER_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define UART_1_DISABLE_INTR_SLAVE(sourceMask) \ + do{ \ + UART_1_INTR_SLAVE_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define UART_1_DISABLE_INTR_TX(sourceMask) \ + do{ \ + UART_1_INTR_TX_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +#define UART_1_DISABLE_INTR_RX(sourceMask) \ + do{ \ + UART_1_INTR_RX_MASK_REG &= ((uint32) ~((uint32) (sourceMask))); \ + }while(0) + +/* Set interrupt sources: write sourceMask bits in UART_1_INTR_X_SET_REG */ +#define UART_1_SET_INTR_MASTER(sourceMask) \ + do{ \ + UART_1_INTR_MASTER_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_1_SET_INTR_SLAVE(sourceMask) \ + do{ \ + UART_1_INTR_SLAVE_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_1_SET_INTR_TX(sourceMask) \ + do{ \ + UART_1_INTR_TX_SET_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_1_SET_INTR_RX(sourceMask) \ + do{ \ + UART_1_INTR_RX_SET_REG = (uint32) (sourceMask); \ + }while(0) + +/* Clear interrupt sources: write sourceMask bits in UART_1_INTR_X_REG */ +#define UART_1_CLEAR_INTR_I2C_EC(sourceMask) \ + do{ \ + UART_1_INTR_I2C_EC_REG = (uint32) (sourceMask); \ + }while(0) + +#if (!UART_1_CY_SCBIP_V1) + #define UART_1_CLEAR_INTR_SPI_EC(sourceMask) \ + do{ \ + UART_1_INTR_SPI_EC_REG = (uint32) (sourceMask); \ + }while(0) +#endif /* (!UART_1_CY_SCBIP_V1) */ + +#define UART_1_CLEAR_INTR_MASTER(sourceMask) \ + do{ \ + UART_1_INTR_MASTER_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_1_CLEAR_INTR_SLAVE(sourceMask) \ + do{ \ + UART_1_INTR_SLAVE_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_1_CLEAR_INTR_TX(sourceMask) \ + do{ \ + UART_1_INTR_TX_REG = (uint32) (sourceMask); \ + }while(0) + +#define UART_1_CLEAR_INTR_RX(sourceMask) \ + do{ \ + UART_1_INTR_RX_REG = (uint32) (sourceMask); \ + }while(0) + +/* Return true if sourceMask is set in UART_1_INTR_CAUSE_REG */ +#define UART_1_CHECK_CAUSE_INTR(sourceMask) (0u != (UART_1_INTR_CAUSE_REG & (sourceMask))) + +/* Return true if sourceMask is set in INTR_X_MASKED_REG */ +#define UART_1_CHECK_INTR_I2C_EC(sourceMask) (0u != (UART_1_INTR_I2C_EC_REG & (sourceMask))) +#if (!UART_1_CY_SCBIP_V1) + #define UART_1_CHECK_INTR_SPI_EC(sourceMask) (0u != (UART_1_INTR_SPI_EC_REG & (sourceMask))) +#endif /* (!UART_1_CY_SCBIP_V1) */ +#define UART_1_CHECK_INTR_MASTER(sourceMask) (0u != (UART_1_INTR_MASTER_REG & (sourceMask))) +#define UART_1_CHECK_INTR_SLAVE(sourceMask) (0u != (UART_1_INTR_SLAVE_REG & (sourceMask))) +#define UART_1_CHECK_INTR_TX(sourceMask) (0u != (UART_1_INTR_TX_REG & (sourceMask))) +#define UART_1_CHECK_INTR_RX(sourceMask) (0u != (UART_1_INTR_RX_REG & (sourceMask))) + +/* Return true if sourceMask is set in UART_1_INTR_X_MASKED_REG */ +#define UART_1_CHECK_INTR_I2C_EC_MASKED(sourceMask) (0u != (UART_1_INTR_I2C_EC_MASKED_REG & \ + (sourceMask))) +#if (!UART_1_CY_SCBIP_V1) + #define UART_1_CHECK_INTR_SPI_EC_MASKED(sourceMask) (0u != (UART_1_INTR_SPI_EC_MASKED_REG & \ + (sourceMask))) +#endif /* (!UART_1_CY_SCBIP_V1) */ +#define UART_1_CHECK_INTR_MASTER_MASKED(sourceMask) (0u != (UART_1_INTR_MASTER_MASKED_REG & \ + (sourceMask))) +#define UART_1_CHECK_INTR_SLAVE_MASKED(sourceMask) (0u != (UART_1_INTR_SLAVE_MASKED_REG & \ + (sourceMask))) +#define UART_1_CHECK_INTR_TX_MASKED(sourceMask) (0u != (UART_1_INTR_TX_MASKED_REG & \ + (sourceMask))) +#define UART_1_CHECK_INTR_RX_MASKED(sourceMask) (0u != (UART_1_INTR_RX_MASKED_REG & \ + (sourceMask))) + +/* Return true if sourceMask is set in UART_1_CTRL_REG: generally is used to check enable bit */ +#define UART_1_GET_CTRL_ENABLED (0u != (UART_1_CTRL_REG & UART_1_CTRL_ENABLED)) + +#define UART_1_CHECK_SLAVE_AUTO_ADDR_NACK (0u != (UART_1_I2C_CTRL_REG & \ + UART_1_I2C_CTRL_S_NOT_READY_DATA_NACK)) + + +/*************************************** +* I2C Macro Definitions +***************************************/ + +/* Enable auto ACK/NACK */ +#define UART_1_ENABLE_SLAVE_AUTO_ADDR_NACK \ + do{ \ + UART_1_I2C_CTRL_REG |= UART_1_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_1_ENABLE_SLAVE_AUTO_DATA_ACK \ + do{ \ + UART_1_I2C_CTRL_REG |= UART_1_I2C_CTRL_S_READY_DATA_ACK; \ + }while(0) + +#define UART_1_ENABLE_SLAVE_AUTO_DATA_NACK \ + do{ \ + UART_1_I2C_CTRL_REG |= UART_1_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_1_ENABLE_MASTER_AUTO_DATA_ACK \ + do{ \ + UART_1_I2C_CTRL_REG |= UART_1_I2C_CTRL_M_READY_DATA_ACK; \ + }while(0) + +#define UART_1_ENABLE_MASTER_AUTO_DATA_NACK \ + do{ \ + UART_1_I2C_CTRL_REG |= UART_1_I2C_CTRL_M_NOT_READY_DATA_NACK; \ + }while(0) + +/* Disable auto ACK/NACK */ +#define UART_1_DISABLE_SLAVE_AUTO_ADDR_NACK \ + do{ \ + UART_1_I2C_CTRL_REG &= ~UART_1_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_1_DISABLE_SLAVE_AUTO_DATA_ACK \ + do{ \ + UART_1_I2C_CTRL_REG &= ~UART_1_I2C_CTRL_S_READY_DATA_ACK; \ + }while(0) + +#define UART_1_DISABLE_SLAVE_AUTO_DATA_NACK \ + do{ \ + UART_1_I2C_CTRL_REG &= ~UART_1_I2C_CTRL_S_NOT_READY_DATA_NACK; \ + }while(0) + +#define UART_1_DISABLE_MASTER_AUTO_DATA_ACK \ + do{ \ + UART_1_I2C_CTRL_REG &= ~UART_1_I2C_CTRL_M_READY_DATA_ACK; \ + }while(0) + +#define UART_1_DISABLE_MASTER_AUTO_DATA_NACK \ + do{ \ + UART_1_I2C_CTRL_REG &= ~UART_1_I2C_CTRL_M_NOT_READY_DATA_NACK; \ + }while(0) + +/* Enable Slave autoACK/NACK Data */ +#define UART_1_ENABLE_SLAVE_AUTO_DATA \ + do{ \ + UART_1_I2C_CTRL_REG |= (UART_1_I2C_CTRL_S_READY_DATA_ACK | \ + UART_1_I2C_CTRL_S_NOT_READY_DATA_NACK); \ + }while(0) + +/* Disable Slave autoACK/NACK Data */ +#define UART_1_DISABLE_SLAVE_AUTO_DATA \ + do{ \ + UART_1_I2C_CTRL_REG &= ((uint32) \ + ~(UART_1_I2C_CTRL_S_READY_DATA_ACK | \ + UART_1_I2C_CTRL_S_NOT_READY_DATA_NACK)); \ + }while(0) + +/* Disable Master autoACK/NACK Data */ +#define UART_1_DISABLE_MASTER_AUTO_DATA \ + do{ \ + UART_1_I2C_CTRL_REG &= ((uint32) \ + ~(UART_1_I2C_CTRL_M_READY_DATA_ACK | \ + UART_1_I2C_CTRL_M_NOT_READY_DATA_NACK)); \ + }while(0) +/* Disables auto data ACK/NACK bits */ +#define UART_1_DISABLE_AUTO_DATA \ + do{ \ + UART_1_I2C_CTRL_REG &= ((uint32) ~(UART_1_I2C_CTRL_M_READY_DATA_ACK | \ + UART_1_I2C_CTRL_M_NOT_READY_DATA_NACK | \ + UART_1_I2C_CTRL_S_READY_DATA_ACK | \ + UART_1_I2C_CTRL_S_NOT_READY_DATA_NACK)); \ + }while(0) + +/* Master commands */ +#define UART_1_I2C_MASTER_GENERATE_START \ + do{ \ + UART_1_I2C_MASTER_CMD_REG = UART_1_I2C_MASTER_CMD_M_START_ON_IDLE; \ + }while(0) + +#define UART_1_I2C_MASTER_CLEAR_START \ + do{ \ + UART_1_I2C_MASTER_CMD_REG = ((uint32) 0u); \ + }while(0) + +#define UART_1_I2C_MASTER_GENERATE_RESTART UART_1_I2CReStartGeneration() + +#define UART_1_I2C_MASTER_GENERATE_STOP \ + do{ \ + UART_1_I2C_MASTER_CMD_REG = \ + (UART_1_I2C_MASTER_CMD_M_STOP | \ + (UART_1_CHECK_I2C_STATUS(UART_1_I2C_STATUS_M_READ) ? \ + (UART_1_I2C_MASTER_CMD_M_NACK) : (0u))); \ + }while(0) + +#define UART_1_I2C_MASTER_GENERATE_ACK \ + do{ \ + UART_1_I2C_MASTER_CMD_REG = UART_1_I2C_MASTER_CMD_M_ACK; \ + }while(0) + +#define UART_1_I2C_MASTER_GENERATE_NACK \ + do{ \ + UART_1_I2C_MASTER_CMD_REG = UART_1_I2C_MASTER_CMD_M_NACK; \ + }while(0) + +/* Slave commands */ +#define UART_1_I2C_SLAVE_GENERATE_ACK \ + do{ \ + UART_1_I2C_SLAVE_CMD_REG = UART_1_I2C_SLAVE_CMD_S_ACK; \ + }while(0) + +#if (UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + /* Slave NACK generation for EC_AM logic on address phase. Ticket ID #183902 */ + void UART_1_I2CSlaveNackGeneration(void); + #define UART_1_I2C_SLAVE_GENERATE_NACK UART_1_I2CSlaveNackGeneration() + +#else + #define UART_1_I2C_SLAVE_GENERATE_NACK \ + do{ \ + UART_1_I2C_SLAVE_CMD_REG = UART_1_I2C_SLAVE_CMD_S_NACK; \ + }while(0) +#endif /* (UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + +#define UART_1_I2C_SLAVE_CLEAR_NACK \ + do{ \ + UART_1_I2C_SLAVE_CMD_REG = 0u; \ + }while(0) + +/* Return 8-bit address. The input address should be 7-bits */ +#define UART_1_GET_I2C_8BIT_ADDRESS(addr) (((uint32) ((uint32) (addr) << \ + UART_1_I2C_SLAVE_ADDR_POS)) & \ + UART_1_I2C_SLAVE_ADDR_MASK) + +#define UART_1_GET_I2C_7BIT_ADDRESS(addr) ((uint32) (addr) >> UART_1_I2C_SLAVE_ADDR_POS) + +/* Adjust SDA filter Trim settings */ +#define UART_1_DEFAULT_I2C_CFG_SDA_FILT_TRIM (0x02u) +#define UART_1_EC_AM_I2C_CFG_SDA_FILT_TRIM (0x03u) + +#if (UART_1_CY_SCBIP_V0) + #define UART_1_SET_I2C_CFG_SDA_FILT_TRIM(sdaTrim) \ + do{ \ + UART_1_I2C_CFG_REG = \ + ((UART_1_I2C_CFG_REG & (uint32) ~UART_1_I2C_CFG_SDA_FILT_TRIM_MASK) | \ + ((uint32) ((uint32) (sdaTrim) <> \ + (UART_1_DM_SIZE * (pos)) ) + +#if (UART_1_TX_SDA_MISO_PIN) + #define UART_1_CHECK_TX_SDA_MISO_PIN_USED \ + (UART_1_PIN_DM_ALG_HIZ != \ + UART_1_GET_P4_PIN_DM(UART_1_uart_tx_i2c_sda_spi_miso_PC, \ + UART_1_uart_tx_i2c_sda_spi_miso_SHIFT)) +#endif /* (UART_1_TX_SDA_MISO_PIN) */ + +#if (UART_1_RTS_SS0_PIN) + #define UART_1_CHECK_RTS_SS0_PIN_USED \ + (UART_1_PIN_DM_ALG_HIZ != \ + UART_1_GET_P4_PIN_DM(UART_1_uart_rts_spi_ss0_PC, \ + UART_1_uart_rts_spi_ss0_SHIFT)) +#endif /* (UART_1_RTS_SS0_PIN) */ + +/* Set bits-mask in register */ +#define UART_1_SET_REGISTER_BITS(reg, mask, pos, mode) \ + do \ + { \ + (reg) = (((reg) & ((uint32) ~(uint32) (mask))) | ((uint32) ((uint32) (mode) << (pos)))); \ + }while(0) + +/* Set bit in the register */ +#define UART_1_SET_REGISTER_BIT(reg, mask, val) \ + ((val) ? ((reg) |= (mask)) : ((reg) &= ((uint32) ~((uint32) (mask))))) + +#define UART_1_SET_HSIOM_SEL(reg, mask, pos, sel) UART_1_SET_REGISTER_BITS(reg, mask, pos, sel) +#define UART_1_SET_INCFG_TYPE(reg, mask, pos, intType) \ + UART_1_SET_REGISTER_BITS(reg, mask, pos, intType) +#define UART_1_SET_INP_DIS(reg, mask, val) UART_1_SET_REGISTER_BIT(reg, mask, val) + +/* UART_1_SET_I2C_SCL_DR(val) - Sets I2C SCL DR register. +* UART_1_SET_I2C_SCL_HSIOM_SEL(sel) - Sets I2C SCL HSIOM settings. +*/ +/* SCB I2C: scl signal */ +#if (UART_1_CY_SCBIP_V0) +#if (UART_1_I2C_PINS) + #define UART_1_SET_I2C_SCL_DR(val) UART_1_scl_Write(val) + + #define UART_1_SET_I2C_SCL_HSIOM_SEL(sel) \ + UART_1_SET_HSIOM_SEL(UART_1_SCL_HSIOM_REG, \ + UART_1_SCL_HSIOM_MASK, \ + UART_1_SCL_HSIOM_POS, \ + (sel)) + #define UART_1_WAIT_SCL_SET_HIGH (0u == UART_1_scl_Read()) + +/* Unconfigured SCB: scl signal */ +#elif (UART_1_RX_WAKE_SCL_MOSI_PIN) + #define UART_1_SET_I2C_SCL_DR(val) \ + UART_1_uart_rx_wake_i2c_scl_spi_mosi_Write(val) + + #define UART_1_SET_I2C_SCL_HSIOM_SEL(sel) \ + UART_1_SET_HSIOM_SEL(UART_1_RX_WAKE_SCL_MOSI_HSIOM_REG, \ + UART_1_RX_WAKE_SCL_MOSI_HSIOM_MASK, \ + UART_1_RX_WAKE_SCL_MOSI_HSIOM_POS, \ + (sel)) + + #define UART_1_WAIT_SCL_SET_HIGH (0u == UART_1_uart_rx_wake_i2c_scl_spi_mosi_Read()) + +#elif (UART_1_RX_SCL_MOSI_PIN) + #define UART_1_SET_I2C_SCL_DR(val) \ + UART_1_uart_rx_i2c_scl_spi_mosi_Write(val) + + + #define UART_1_SET_I2C_SCL_HSIOM_SEL(sel) \ + UART_1_SET_HSIOM_SEL(UART_1_RX_SCL_MOSI_HSIOM_REG, \ + UART_1_RX_SCL_MOSI_HSIOM_MASK, \ + UART_1_RX_SCL_MOSI_HSIOM_POS, \ + (sel)) + + #define UART_1_WAIT_SCL_SET_HIGH (0u == UART_1_uart_rx_i2c_scl_spi_mosi_Read()) + +#else + #define UART_1_SET_I2C_SCL_DR(val) do{ /* Does nothing */ }while(0) + #define UART_1_SET_I2C_SCL_HSIOM_SEL(sel) do{ /* Does nothing */ }while(0) + + #define UART_1_WAIT_SCL_SET_HIGH (0u) +#endif /* (UART_1_I2C_PINS) */ + +/* SCB I2C: sda signal */ +#if (UART_1_I2C_PINS) + #define UART_1_WAIT_SDA_SET_HIGH (0u == UART_1_sda_Read()) +/* Unconfigured SCB: sda signal */ +#elif (UART_1_TX_SDA_MISO_PIN) + #define UART_1_WAIT_SDA_SET_HIGH (0u == UART_1_uart_tx_i2c_sda_spi_miso_Read()) +#else + #define UART_1_WAIT_SDA_SET_HIGH (0u) +#endif /* (UART_1_MOSI_SCL_RX_PIN) */ +#endif /* (UART_1_CY_SCBIP_V0) */ + +/* Clear UART wakeup source */ +#if (UART_1_RX_SCL_MOSI_PIN) + #define UART_1_CLEAR_UART_RX_WAKE_INTR do{ /* Does nothing */ }while(0) + +#elif (UART_1_RX_WAKE_SCL_MOSI_PIN) + #define UART_1_CLEAR_UART_RX_WAKE_INTR \ + do{ \ + (void) UART_1_uart_rx_wake_i2c_scl_spi_mosi_ClearInterrupt(); \ + }while(0) + +#elif(UART_1_UART_RX_WAKE_PIN) + #define UART_1_CLEAR_UART_RX_WAKE_INTR \ + do{ \ + (void) UART_1_rx_wake_ClearInterrupt(); \ + }while(0) +#else +#endif /* (UART_1_RX_SCL_MOSI_PIN) */ + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +/* Unconfigured pins */ +#define UART_1_REMOVE_MOSI_SCL_RX_WAKE_PIN UART_1_REMOVE_RX_WAKE_SCL_MOSI_PIN +#define UART_1_REMOVE_MOSI_SCL_RX_PIN UART_1_REMOVE_RX_SCL_MOSI_PIN +#define UART_1_REMOVE_MISO_SDA_TX_PIN UART_1_REMOVE_TX_SDA_MISO_PIN +#ifndef UART_1_REMOVE_SCLK_PIN +#define UART_1_REMOVE_SCLK_PIN UART_1_REMOVE_CTS_SCLK_PIN +#endif /* UART_1_REMOVE_SCLK_PIN */ +#ifndef UART_1_REMOVE_SS0_PIN +#define UART_1_REMOVE_SS0_PIN UART_1_REMOVE_RTS_SS0_PIN +#endif /* UART_1_REMOVE_SS0_PIN */ + +/* Unconfigured pins */ +#define UART_1_MOSI_SCL_RX_WAKE_PIN UART_1_RX_WAKE_SCL_MOSI_PIN +#define UART_1_MOSI_SCL_RX_PIN UART_1_RX_SCL_MOSI_PIN +#define UART_1_MISO_SDA_TX_PIN UART_1_TX_SDA_MISO_PIN +#ifndef UART_1_SCLK_PIN +#define UART_1_SCLK_PIN UART_1_CTS_SCLK_PIN +#endif /* UART_1_SCLK_PIN */ +#ifndef UART_1_SS0_PIN +#define UART_1_SS0_PIN UART_1_RTS_SS0_PIN +#endif /* UART_1_SS0_PIN */ + +#if (UART_1_MOSI_SCL_RX_WAKE_PIN) + #define UART_1_MOSI_SCL_RX_WAKE_HSIOM_REG UART_1_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_1_MOSI_SCL_RX_WAKE_HSIOM_PTR UART_1_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_1_MOSI_SCL_RX_WAKE_HSIOM_MASK UART_1_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_1_MOSI_SCL_RX_WAKE_HSIOM_POS UART_1_RX_WAKE_SCL_MOSI_HSIOM_REG + + #define UART_1_MOSI_SCL_RX_WAKE_INTCFG_REG UART_1_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_1_MOSI_SCL_RX_WAKE_INTCFG_PTR UART_1_RX_WAKE_SCL_MOSI_HSIOM_REG + + #define UART_1_MOSI_SCL_RX_WAKE_INTCFG_TYPE_POS UART_1_RX_WAKE_SCL_MOSI_HSIOM_REG + #define UART_1_MOSI_SCL_RX_WAKE_INTCFG_TYPE_MASK UART_1_RX_WAKE_SCL_MOSI_HSIOM_REG +#endif /* (UART_1_RX_WAKE_SCL_MOSI_PIN) */ + +#if (UART_1_MOSI_SCL_RX_PIN) + #define UART_1_MOSI_SCL_RX_HSIOM_REG UART_1_RX_SCL_MOSI_HSIOM_REG + #define UART_1_MOSI_SCL_RX_HSIOM_PTR UART_1_RX_SCL_MOSI_HSIOM_PTR + #define UART_1_MOSI_SCL_RX_HSIOM_MASK UART_1_RX_SCL_MOSI_HSIOM_MASK + #define UART_1_MOSI_SCL_RX_HSIOM_POS UART_1_RX_SCL_MOSI_HSIOM_POS +#endif /* (UART_1_MOSI_SCL_RX_PIN) */ + +#if (UART_1_MISO_SDA_TX_PIN) + #define UART_1_MISO_SDA_TX_HSIOM_REG UART_1_TX_SDA_MISO_HSIOM_REG + #define UART_1_MISO_SDA_TX_HSIOM_PTR UART_1_TX_SDA_MISO_HSIOM_REG + #define UART_1_MISO_SDA_TX_HSIOM_MASK UART_1_TX_SDA_MISO_HSIOM_REG + #define UART_1_MISO_SDA_TX_HSIOM_POS UART_1_TX_SDA_MISO_HSIOM_REG +#endif /* (UART_1_MISO_SDA_TX_PIN_PIN) */ + +#if (UART_1_SCLK_PIN) + #ifndef UART_1_SCLK_HSIOM_REG + #define UART_1_SCLK_HSIOM_REG UART_1_CTS_SCLK_HSIOM_REG + #define UART_1_SCLK_HSIOM_PTR UART_1_CTS_SCLK_HSIOM_PTR + #define UART_1_SCLK_HSIOM_MASK UART_1_CTS_SCLK_HSIOM_MASK + #define UART_1_SCLK_HSIOM_POS UART_1_CTS_SCLK_HSIOM_POS + #endif /* UART_1_SCLK_HSIOM_REG */ +#endif /* (UART_1_SCLK_PIN) */ + +#if (UART_1_SS0_PIN) + #ifndef UART_1_SS0_HSIOM_REG + #define UART_1_SS0_HSIOM_REG UART_1_RTS_SS0_HSIOM_REG + #define UART_1_SS0_HSIOM_PTR UART_1_RTS_SS0_HSIOM_PTR + #define UART_1_SS0_HSIOM_MASK UART_1_RTS_SS0_HSIOM_MASK + #define UART_1_SS0_HSIOM_POS UART_1_RTS_SS0_HSIOM_POS + #endif /* UART_1_SS0_HSIOM_REG */ +#endif /* (UART_1_SS0_PIN) */ + +#define UART_1_MOSI_SCL_RX_WAKE_PIN_INDEX UART_1_RX_WAKE_SCL_MOSI_PIN_INDEX +#define UART_1_MOSI_SCL_RX_PIN_INDEX UART_1_RX_SCL_MOSI_PIN_INDEX +#define UART_1_MISO_SDA_TX_PIN_INDEX UART_1_TX_SDA_MISO_PIN_INDEX +#ifndef UART_1_SCLK_PIN_INDEX +#define UART_1_SCLK_PIN_INDEX UART_1_CTS_SCLK_PIN_INDEX +#endif /* UART_1_SCLK_PIN_INDEX */ +#ifndef UART_1_SS0_PIN_INDEX +#define UART_1_SS0_PIN_INDEX UART_1_RTS_SS0_PIN_INDEX +#endif /* UART_1_SS0_PIN_INDEX */ + +#define UART_1_MOSI_SCL_RX_WAKE_PIN_MASK UART_1_RX_WAKE_SCL_MOSI_PIN_MASK +#define UART_1_MOSI_SCL_RX_PIN_MASK UART_1_RX_SCL_MOSI_PIN_MASK +#define UART_1_MISO_SDA_TX_PIN_MASK UART_1_TX_SDA_MISO_PIN_MASK +#ifndef UART_1_SCLK_PIN_MASK +#define UART_1_SCLK_PIN_MASK UART_1_CTS_SCLK_PIN_MASK +#endif /* UART_1_SCLK_PIN_MASK */ +#ifndef UART_1_SS0_PIN_MASK +#define UART_1_SS0_PIN_MASK UART_1_RTS_SS0_PIN_MASK +#endif /* UART_1_SS0_PIN_MASK */ + +#endif /* (CY_SCB_PINS_UART_1_H) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_PM.c b/cores/asr650x/projects/PSoC4/UART_1_PM.c new file mode 100644 index 00000000..a8614823 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_PM.c @@ -0,0 +1,223 @@ +/***************************************************************************//** +* \file UART_1_PM.c +* \version 4.0 +* +* \brief +* This file provides the source code to the Power Management support for +* the SCB Component. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_1.h" +#include "UART_1_PVT.h" + +#if(UART_1_SCB_MODE_I2C_INC) + #include "UART_1_I2C_PVT.h" +#endif /* (UART_1_SCB_MODE_I2C_INC) */ + +#if(UART_1_SCB_MODE_EZI2C_INC) + #include "UART_1_EZI2C_PVT.h" +#endif /* (UART_1_SCB_MODE_EZI2C_INC) */ + +#if(UART_1_SCB_MODE_SPI_INC || UART_1_SCB_MODE_UART_INC) + #include "UART_1_SPI_UART_PVT.h" +#endif /* (UART_1_SCB_MODE_SPI_INC || UART_1_SCB_MODE_UART_INC) */ + + +/*************************************** +* Backup Structure declaration +***************************************/ + +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG || \ + (UART_1_SCB_MODE_I2C_CONST_CFG && (!UART_1_I2C_WAKE_ENABLE_CONST)) || \ + (UART_1_SCB_MODE_EZI2C_CONST_CFG && (!UART_1_EZI2C_WAKE_ENABLE_CONST)) || \ + (UART_1_SCB_MODE_SPI_CONST_CFG && (!UART_1_SPI_WAKE_ENABLE_CONST)) || \ + (UART_1_SCB_MODE_UART_CONST_CFG && (!UART_1_UART_WAKE_ENABLE_CONST))) + + UART_1_BACKUP_STRUCT UART_1_backup = + { + 0u, /* enableState */ + }; +#endif + + +/******************************************************************************* +* Function Name: UART_1_Sleep +****************************************************************************//** +* +* Prepares the UART_1 component to enter Deep Sleep. +* The 鈥淓nable wakeup from Deep Sleep Mode鈥 selection has an influence on this +* function implementation: +* - Checked: configures the component to be wakeup source from Deep Sleep. +* - Unchecked: stores the current component state (enabled or disabled) and +* disables the component. See SCB_Stop() function for details about component +* disabling. +* +* Call the UART_1_Sleep() function before calling the +* CyPmSysDeepSleep() function. +* Refer to the PSoC Creator System Reference Guide for more information about +* power management functions and Low power section of this document for the +* selected mode. +* +* This function should not be called before entering Sleep. +* +*******************************************************************************/ +void UART_1_Sleep(void) +{ +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + + if(UART_1_SCB_WAKE_ENABLE_CHECK) + { + if(UART_1_SCB_MODE_I2C_RUNTM_CFG) + { + UART_1_I2CSaveConfig(); + } + else if(UART_1_SCB_MODE_EZI2C_RUNTM_CFG) + { + UART_1_EzI2CSaveConfig(); + } + #if(!UART_1_CY_SCBIP_V1) + else if(UART_1_SCB_MODE_SPI_RUNTM_CFG) + { + UART_1_SpiSaveConfig(); + } + else if(UART_1_SCB_MODE_UART_RUNTM_CFG) + { + UART_1_UartSaveConfig(); + } + #endif /* (!UART_1_CY_SCBIP_V1) */ + else + { + /* Unknown mode */ + } + } + else + { + UART_1_backup.enableState = (uint8) UART_1_GET_CTRL_ENABLED; + + if(0u != UART_1_backup.enableState) + { + UART_1_Stop(); + } + } + +#else + + #if (UART_1_SCB_MODE_I2C_CONST_CFG && UART_1_I2C_WAKE_ENABLE_CONST) + UART_1_I2CSaveConfig(); + + #elif (UART_1_SCB_MODE_EZI2C_CONST_CFG && UART_1_EZI2C_WAKE_ENABLE_CONST) + UART_1_EzI2CSaveConfig(); + + #elif (UART_1_SCB_MODE_SPI_CONST_CFG && UART_1_SPI_WAKE_ENABLE_CONST) + UART_1_SpiSaveConfig(); + + #elif (UART_1_SCB_MODE_UART_CONST_CFG && UART_1_UART_WAKE_ENABLE_CONST) + UART_1_UartSaveConfig(); + + #else + + UART_1_backup.enableState = (uint8) UART_1_GET_CTRL_ENABLED; + + if(0u != UART_1_backup.enableState) + { + UART_1_Stop(); + } + + #endif /* defined (UART_1_SCB_MODE_I2C_CONST_CFG) && (UART_1_I2C_WAKE_ENABLE_CONST) */ + +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/******************************************************************************* +* Function Name: UART_1_Wakeup +****************************************************************************//** +* +* Prepares the UART_1 component for Active mode operation after +* Deep Sleep. +* The 鈥淓nable wakeup from Deep Sleep Mode鈥 selection has influence on this +* function implementation: +* - Checked: restores the component Active mode configuration. +* - Unchecked: enables the component if it was enabled before enter Deep Sleep. +* +* This function should not be called after exiting Sleep. +* +* \sideeffect +* Calling the UART_1_Wakeup() function without first calling the +* UART_1_Sleep() function may produce unexpected behavior. +* +*******************************************************************************/ +void UART_1_Wakeup(void) +{ +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + + if(UART_1_SCB_WAKE_ENABLE_CHECK) + { + if(UART_1_SCB_MODE_I2C_RUNTM_CFG) + { + UART_1_I2CRestoreConfig(); + } + else if(UART_1_SCB_MODE_EZI2C_RUNTM_CFG) + { + UART_1_EzI2CRestoreConfig(); + } + #if(!UART_1_CY_SCBIP_V1) + else if(UART_1_SCB_MODE_SPI_RUNTM_CFG) + { + UART_1_SpiRestoreConfig(); + } + else if(UART_1_SCB_MODE_UART_RUNTM_CFG) + { + UART_1_UartRestoreConfig(); + } + #endif /* (!UART_1_CY_SCBIP_V1) */ + else + { + /* Unknown mode */ + } + } + else + { + if(0u != UART_1_backup.enableState) + { + UART_1_Enable(); + } + } + +#else + + #if (UART_1_SCB_MODE_I2C_CONST_CFG && UART_1_I2C_WAKE_ENABLE_CONST) + UART_1_I2CRestoreConfig(); + + #elif (UART_1_SCB_MODE_EZI2C_CONST_CFG && UART_1_EZI2C_WAKE_ENABLE_CONST) + UART_1_EzI2CRestoreConfig(); + + #elif (UART_1_SCB_MODE_SPI_CONST_CFG && UART_1_SPI_WAKE_ENABLE_CONST) + UART_1_SpiRestoreConfig(); + + #elif (UART_1_SCB_MODE_UART_CONST_CFG && UART_1_UART_WAKE_ENABLE_CONST) + UART_1_UartRestoreConfig(); + + #else + + if(0u != UART_1_backup.enableState) + { + UART_1_Enable(); + } + + #endif /* (UART_1_I2C_WAKE_ENABLE_CONST) */ + +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_PVT.h b/cores/asr650x/projects/PSoC4/UART_1_PVT.h new file mode 100644 index 00000000..07954045 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_PVT.h @@ -0,0 +1,123 @@ +/***************************************************************************//** +* \file .h +* \version 4.0 +* +* \brief +* This private file provides constants and parameter values for the +* SCB Component. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_PVT_UART_1_H) +#define CY_SCB_PVT_UART_1_H + +#include "UART_1.h" + + +/*************************************** +* Private Function Prototypes +***************************************/ + +/* APIs to service INTR_I2C_EC register */ +#define UART_1_SetI2CExtClkInterruptMode(interruptMask) UART_1_WRITE_INTR_I2C_EC_MASK(interruptMask) +#define UART_1_ClearI2CExtClkInterruptSource(interruptMask) UART_1_CLEAR_INTR_I2C_EC(interruptMask) +#define UART_1_GetI2CExtClkInterruptSource() (UART_1_INTR_I2C_EC_REG) +#define UART_1_GetI2CExtClkInterruptMode() (UART_1_INTR_I2C_EC_MASK_REG) +#define UART_1_GetI2CExtClkInterruptSourceMasked() (UART_1_INTR_I2C_EC_MASKED_REG) + +#if (!UART_1_CY_SCBIP_V1) + /* APIs to service INTR_SPI_EC register */ + #define UART_1_SetSpiExtClkInterruptMode(interruptMask) \ + UART_1_WRITE_INTR_SPI_EC_MASK(interruptMask) + #define UART_1_ClearSpiExtClkInterruptSource(interruptMask) \ + UART_1_CLEAR_INTR_SPI_EC(interruptMask) + #define UART_1_GetExtSpiClkInterruptSource() (UART_1_INTR_SPI_EC_REG) + #define UART_1_GetExtSpiClkInterruptMode() (UART_1_INTR_SPI_EC_MASK_REG) + #define UART_1_GetExtSpiClkInterruptSourceMasked() (UART_1_INTR_SPI_EC_MASKED_REG) +#endif /* (!UART_1_CY_SCBIP_V1) */ + +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + extern void UART_1_SetPins(uint32 mode, uint32 subMode, uint32 uartEnableMask); +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +#if (UART_1_SCB_IRQ_INTERNAL) +#if !defined (CY_REMOVE_UART_1_CUSTOM_INTR_HANDLER) + extern cyisraddress UART_1_customIntrHandler; +#endif /* !defined (CY_REMOVE_UART_1_CUSTOM_INTR_HANDLER) */ +#endif /* (UART_1_SCB_IRQ_INTERNAL) */ + +extern UART_1_BACKUP_STRUCT UART_1_backup; + +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + /* Common configuration variables */ + extern uint8 UART_1_scbMode; + extern uint8 UART_1_scbEnableWake; + extern uint8 UART_1_scbEnableIntr; + + /* I2C configuration variables */ + extern uint8 UART_1_mode; + extern uint8 UART_1_acceptAddr; + + /* SPI/UART configuration variables */ + extern volatile uint8 * UART_1_rxBuffer; + extern uint8 UART_1_rxDataBits; + extern uint32 UART_1_rxBufferSize; + + extern volatile uint8 * UART_1_txBuffer; + extern uint8 UART_1_txDataBits; + extern uint32 UART_1_txBufferSize; + + /* EZI2C configuration variables */ + extern uint8 UART_1_numberOfAddr; + extern uint8 UART_1_subAddrSize; +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if (! (UART_1_SCB_MODE_I2C_CONST_CFG || \ + UART_1_SCB_MODE_EZI2C_CONST_CFG)) + extern uint16 UART_1_IntrTxMask; +#endif /* (! (UART_1_SCB_MODE_I2C_CONST_CFG || \ + UART_1_SCB_MODE_EZI2C_CONST_CFG)) */ + + +/*************************************** +* Conditional Macro +****************************************/ + +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + /* Defines run time operation mode */ + #define UART_1_SCB_MODE_I2C_RUNTM_CFG (UART_1_SCB_MODE_I2C == UART_1_scbMode) + #define UART_1_SCB_MODE_SPI_RUNTM_CFG (UART_1_SCB_MODE_SPI == UART_1_scbMode) + #define UART_1_SCB_MODE_UART_RUNTM_CFG (UART_1_SCB_MODE_UART == UART_1_scbMode) + #define UART_1_SCB_MODE_EZI2C_RUNTM_CFG (UART_1_SCB_MODE_EZI2C == UART_1_scbMode) + #define UART_1_SCB_MODE_UNCONFIG_RUNTM_CFG \ + (UART_1_SCB_MODE_UNCONFIG == UART_1_scbMode) + + /* Defines wakeup enable */ + #define UART_1_SCB_WAKE_ENABLE_CHECK (0u != UART_1_scbEnableWake) +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + +/* Defines maximum number of SCB pins */ +#if (!UART_1_CY_SCBIP_V1) + #define UART_1_SCB_PINS_NUMBER (7u) +#else + #define UART_1_SCB_PINS_NUMBER (2u) +#endif /* (!UART_1_CY_SCBIP_V1) */ + +#endif /* (CY_SCB_PVT_UART_1_H) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_RX_WAKEUP_IRQ.c b/cores/asr650x/projects/PSoC4/UART_1_RX_WAKEUP_IRQ.c new file mode 100644 index 00000000..c67f4520 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_RX_WAKEUP_IRQ.c @@ -0,0 +1,406 @@ +/******************************************************************************* +* File Name: UART_1_RX_WAKEUP_IRQ.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include +#include "cyapicallbacks.h" + +#if !defined(UART_1_RX_WAKEUP_IRQ__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START UART_1_RX_WAKEUP_IRQ_intc` */ + +/* `#END` */ + +extern cyisraddress CyRamVectors[CYINT_IRQ_BASE + CY_NUM_INTERRUPTS]; + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_RX_WAKEUP_IRQ_Start(void) +{ + /* For all we know the interrupt is active. */ + UART_1_RX_WAKEUP_IRQ_Disable(); + + /* Set the ISR to point to the UART_1_RX_WAKEUP_IRQ Interrupt. */ + UART_1_RX_WAKEUP_IRQ_SetVector(&UART_1_RX_WAKEUP_IRQ_Interrupt); + + /* Set the priority. */ + UART_1_RX_WAKEUP_IRQ_SetPriority((uint8)UART_1_RX_WAKEUP_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + UART_1_RX_WAKEUP_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_RX_WAKEUP_IRQ_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + UART_1_RX_WAKEUP_IRQ_Disable(); + + /* Set the ISR to point to the UART_1_RX_WAKEUP_IRQ Interrupt. */ + UART_1_RX_WAKEUP_IRQ_SetVector(address); + + /* Set the priority. */ + UART_1_RX_WAKEUP_IRQ_SetPriority((uint8)UART_1_RX_WAKEUP_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + UART_1_RX_WAKEUP_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_RX_WAKEUP_IRQ_Stop(void) +{ + /* Disable this interrupt. */ + UART_1_RX_WAKEUP_IRQ_Disable(); + + /* Set the ISR to point to the passive one. */ + UART_1_RX_WAKEUP_IRQ_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for UART_1_RX_WAKEUP_IRQ. +* +* Add custom code between the START and END comments to keep the next version +* of this file from over-writing your code. +* +* Note You may use either the default ISR by using this API, or you may define +* your own separate ISR through ISR_StartEx(). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(UART_1_RX_WAKEUP_IRQ_Interrupt) +{ + #ifdef UART_1_RX_WAKEUP_IRQ_INTERRUPT_INTERRUPT_CALLBACK + UART_1_RX_WAKEUP_IRQ_Interrupt_InterruptCallback(); + #endif /* UART_1_RX_WAKEUP_IRQ_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START UART_1_RX_WAKEUP_IRQ_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling UART_1_RX_WAKEUP_IRQ_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use UART_1_RX_WAKEUP_IRQ_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_RX_WAKEUP_IRQ_SetVector(cyisraddress address) +{ + CyRamVectors[CYINT_IRQ_BASE + UART_1_RX_WAKEUP_IRQ__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress UART_1_RX_WAKEUP_IRQ_GetVector(void) +{ + return CyRamVectors[CYINT_IRQ_BASE + UART_1_RX_WAKEUP_IRQ__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling UART_1_RX_WAKEUP_IRQ_Start or UART_1_RX_WAKEUP_IRQ_StartEx will +* override any effect this API would have had. This API should only be called +* after UART_1_RX_WAKEUP_IRQ_Start or UART_1_RX_WAKEUP_IRQ_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_RX_WAKEUP_IRQ_SetPriority(uint8 priority) +{ + uint8 interruptState; + uint32 priorityOffset = ((UART_1_RX_WAKEUP_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + interruptState = CyEnterCriticalSection(); + *UART_1_RX_WAKEUP_IRQ_INTC_PRIOR = (*UART_1_RX_WAKEUP_IRQ_INTC_PRIOR & (uint32)(~UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_MASK)) | + ((uint32)priority << priorityOffset); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 UART_1_RX_WAKEUP_IRQ_GetPriority(void) +{ + uint32 priority; + uint32 priorityOffset = ((UART_1_RX_WAKEUP_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + priority = (*UART_1_RX_WAKEUP_IRQ_INTC_PRIOR & UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_MASK) >> priorityOffset; + + return (uint8)priority; +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_RX_WAKEUP_IRQ_Enable(void) +{ + /* Enable the general interrupt. */ + *UART_1_RX_WAKEUP_IRQ_INTC_SET_EN = UART_1_RX_WAKEUP_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 UART_1_RX_WAKEUP_IRQ_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*UART_1_RX_WAKEUP_IRQ_INTC_SET_EN & (uint32)UART_1_RX_WAKEUP_IRQ__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_RX_WAKEUP_IRQ_Disable(void) +{ + /* Disable the general interrupt. */ + *UART_1_RX_WAKEUP_IRQ_INTC_CLR_EN = UART_1_RX_WAKEUP_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void UART_1_RX_WAKEUP_IRQ_SetPending(void) +{ + *UART_1_RX_WAKEUP_IRQ_INTC_SET_PD = UART_1_RX_WAKEUP_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: UART_1_RX_WAKEUP_IRQ_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_RX_WAKEUP_IRQ_ClearPending(void) +{ + *UART_1_RX_WAKEUP_IRQ_INTC_CLR_PD = UART_1_RX_WAKEUP_IRQ__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_RX_WAKEUP_IRQ.h b/cores/asr650x/projects/PSoC4/UART_1_RX_WAKEUP_IRQ.h new file mode 100644 index 00000000..cc57f129 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_RX_WAKEUP_IRQ.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* File Name: UART_1_RX_WAKEUP_IRQ.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_UART_1_RX_WAKEUP_IRQ_H) +#define CY_ISR_UART_1_RX_WAKEUP_IRQ_H + + +#include +#include + +/* Interrupt Controller API. */ +void UART_1_RX_WAKEUP_IRQ_Start(void); +void UART_1_RX_WAKEUP_IRQ_StartEx(cyisraddress address); +void UART_1_RX_WAKEUP_IRQ_Stop(void); + +CY_ISR_PROTO(UART_1_RX_WAKEUP_IRQ_Interrupt); + +void UART_1_RX_WAKEUP_IRQ_SetVector(cyisraddress address); +cyisraddress UART_1_RX_WAKEUP_IRQ_GetVector(void); + +void UART_1_RX_WAKEUP_IRQ_SetPriority(uint8 priority); +uint8 UART_1_RX_WAKEUP_IRQ_GetPriority(void); + +void UART_1_RX_WAKEUP_IRQ_Enable(void); +uint8 UART_1_RX_WAKEUP_IRQ_GetState(void); +void UART_1_RX_WAKEUP_IRQ_Disable(void); + +void UART_1_RX_WAKEUP_IRQ_SetPending(void); +void UART_1_RX_WAKEUP_IRQ_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the UART_1_RX_WAKEUP_IRQ ISR. */ +#define UART_1_RX_WAKEUP_IRQ_INTC_VECTOR ((reg32 *) UART_1_RX_WAKEUP_IRQ__INTC_VECT) + +/* Address of the UART_1_RX_WAKEUP_IRQ ISR priority. */ +#define UART_1_RX_WAKEUP_IRQ_INTC_PRIOR ((reg32 *) UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_REG) + +/* Priority of the UART_1_RX_WAKEUP_IRQ interrupt. */ +#define UART_1_RX_WAKEUP_IRQ_INTC_PRIOR_NUMBER UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable UART_1_RX_WAKEUP_IRQ interrupt. */ +#define UART_1_RX_WAKEUP_IRQ_INTC_SET_EN ((reg32 *) UART_1_RX_WAKEUP_IRQ__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the UART_1_RX_WAKEUP_IRQ interrupt. */ +#define UART_1_RX_WAKEUP_IRQ_INTC_CLR_EN ((reg32 *) UART_1_RX_WAKEUP_IRQ__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the UART_1_RX_WAKEUP_IRQ interrupt state to pending. */ +#define UART_1_RX_WAKEUP_IRQ_INTC_SET_PD ((reg32 *) UART_1_RX_WAKEUP_IRQ__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the UART_1_RX_WAKEUP_IRQ interrupt. */ +#define UART_1_RX_WAKEUP_IRQ_INTC_CLR_PD ((reg32 *) UART_1_RX_WAKEUP_IRQ__INTC_CLR_PD_REG) + + + +#endif /* CY_ISR_UART_1_RX_WAKEUP_IRQ_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_SCBCLK.c b/cores/asr650x/projects/PSoC4/UART_1_SCBCLK.c new file mode 100644 index 00000000..7568a2e6 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_SCBCLK.c @@ -0,0 +1,210 @@ +/******************************************************************************* +* File Name: UART_1_SCBCLK.c +* Version 2.20 +* +* Description: +* Provides system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "UART_1_SCBCLK.h" + +#if defined CYREG_PERI_DIV_CMD + +/******************************************************************************* +* Function Name: UART_1_SCBCLK_StartEx +******************************************************************************** +* +* Summary: +* Starts the clock, aligned to the specified running clock. +* +* Parameters: +* alignClkDiv: The divider to which phase alignment is performed when the +* clock is started. +* +* Returns: +* None +* +*******************************************************************************/ +void UART_1_SCBCLK_StartEx(uint32 alignClkDiv) +{ + /* Make sure any previous start command has finished. */ + while((UART_1_SCBCLK_CMD_REG & UART_1_SCBCLK_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and enable. */ + UART_1_SCBCLK_CMD_REG = + ((uint32)UART_1_SCBCLK__DIV_ID << UART_1_SCBCLK_CMD_DIV_SHIFT)| + (alignClkDiv << UART_1_SCBCLK_CMD_PA_DIV_SHIFT) | + (uint32)UART_1_SCBCLK_CMD_ENABLE_MASK; +} + +#else + +/******************************************************************************* +* Function Name: UART_1_SCBCLK_Start +******************************************************************************** +* +* Summary: +* Starts the clock. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ + +void UART_1_SCBCLK_Start(void) +{ + /* Set the bit to enable the clock. */ + UART_1_SCBCLK_ENABLE_REG |= UART_1_SCBCLK__ENABLE_MASK; +} + +#endif /* CYREG_PERI_DIV_CMD */ + + +/******************************************************************************* +* Function Name: UART_1_SCBCLK_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void UART_1_SCBCLK_Stop(void) +{ +#if defined CYREG_PERI_DIV_CMD + + /* Make sure any previous start command has finished. */ + while((UART_1_SCBCLK_CMD_REG & UART_1_SCBCLK_CMD_ENABLE_MASK) != 0u) + { + } + + /* Specify the target divider and it's alignment divider, and disable. */ + UART_1_SCBCLK_CMD_REG = + ((uint32)UART_1_SCBCLK__DIV_ID << UART_1_SCBCLK_CMD_DIV_SHIFT)| + ((uint32)UART_1_SCBCLK_CMD_DISABLE_MASK); + +#else + + /* Clear the bit to disable the clock. */ + UART_1_SCBCLK_ENABLE_REG &= (uint32)(~UART_1_SCBCLK__ENABLE_MASK); + +#endif /* CYREG_PERI_DIV_CMD */ +} + + +/******************************************************************************* +* Function Name: UART_1_SCBCLK_SetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and the fractional divider. +* +* Parameters: +* clkDivider: Divider register value (0-65535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* fracDivider: Fractional Divider register value (0-31). +* Returns: +* None +* +*******************************************************************************/ +void UART_1_SCBCLK_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional) +{ + uint32 maskVal; + uint32 regVal; + +#if defined (UART_1_SCBCLK__FRAC_MASK) || defined (CYREG_PERI_DIV_CMD) + + /* get all but divider bits */ + maskVal = UART_1_SCBCLK_DIV_REG & + (uint32)(~(uint32)(UART_1_SCBCLK_DIV_INT_MASK | UART_1_SCBCLK_DIV_FRAC_MASK)); + /* combine mask and new divider vals into 32-bit value */ + regVal = maskVal | + ((uint32)((uint32)clkDivider << UART_1_SCBCLK_DIV_INT_SHIFT) & UART_1_SCBCLK_DIV_INT_MASK) | + ((uint32)((uint32)clkFractional << UART_1_SCBCLK_DIV_FRAC_SHIFT) & UART_1_SCBCLK_DIV_FRAC_MASK); + +#else + /* get all but integer divider bits */ + maskVal = UART_1_SCBCLK_DIV_REG & (uint32)(~(uint32)UART_1_SCBCLK__DIVIDER_MASK); + /* combine mask and new divider val into 32-bit value */ + regVal = clkDivider | maskVal; + +#endif /* UART_1_SCBCLK__FRAC_MASK || CYREG_PERI_DIV_CMD */ + + UART_1_SCBCLK_DIV_REG = regVal; +} + + +/******************************************************************************* +* Function Name: UART_1_SCBCLK_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 UART_1_SCBCLK_GetDividerRegister(void) +{ + return (uint16)((UART_1_SCBCLK_DIV_REG & UART_1_SCBCLK_DIV_INT_MASK) + >> UART_1_SCBCLK_DIV_INT_SHIFT); +} + + +/******************************************************************************* +* Function Name: UART_1_SCBCLK_GetFractionalDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock fractional divider register value. +* +* Parameters: +* None +* +* Returns: +* Fractional Divide value of the clock +* 0 if the fractional divider is not in use. +* +*******************************************************************************/ +uint8 UART_1_SCBCLK_GetFractionalDividerRegister(void) +{ +#if defined (UART_1_SCBCLK__FRAC_MASK) + /* return fractional divider bits */ + return (uint8)((UART_1_SCBCLK_DIV_REG & UART_1_SCBCLK_DIV_FRAC_MASK) + >> UART_1_SCBCLK_DIV_FRAC_SHIFT); +#else + return 0u; +#endif /* UART_1_SCBCLK__FRAC_MASK */ +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_SCBCLK.h b/cores/asr650x/projects/PSoC4/UART_1_SCBCLK.h new file mode 100644 index 00000000..048bdbda --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_SCBCLK.h @@ -0,0 +1,91 @@ +/******************************************************************************* +* File Name: UART_1_SCBCLK.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_UART_1_SCBCLK_H) +#define CY_CLOCK_UART_1_SCBCLK_H + +#include +#include + + +/*************************************** +* Function Prototypes +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +void UART_1_SCBCLK_StartEx(uint32 alignClkDiv); +#define UART_1_SCBCLK_Start() \ + UART_1_SCBCLK_StartEx(UART_1_SCBCLK__PA_DIV_ID) + +#else + +void UART_1_SCBCLK_Start(void); + +#endif/* CYREG_PERI_DIV_CMD */ + +void UART_1_SCBCLK_Stop(void); + +void UART_1_SCBCLK_SetFractionalDividerRegister(uint16 clkDivider, uint8 clkFractional); + +uint16 UART_1_SCBCLK_GetDividerRegister(void); +uint8 UART_1_SCBCLK_GetFractionalDividerRegister(void); + +#define UART_1_SCBCLK_Enable() UART_1_SCBCLK_Start() +#define UART_1_SCBCLK_Disable() UART_1_SCBCLK_Stop() +#define UART_1_SCBCLK_SetDividerRegister(clkDivider, reset) \ + UART_1_SCBCLK_SetFractionalDividerRegister((clkDivider), 0u) +#define UART_1_SCBCLK_SetDivider(clkDivider) UART_1_SCBCLK_SetDividerRegister((clkDivider), 1u) +#define UART_1_SCBCLK_SetDividerValue(clkDivider) UART_1_SCBCLK_SetDividerRegister((clkDivider) - 1u, 1u) + + +/*************************************** +* Registers +***************************************/ +#if defined CYREG_PERI_DIV_CMD + +#define UART_1_SCBCLK_DIV_ID UART_1_SCBCLK__DIV_ID + +#define UART_1_SCBCLK_CMD_REG (*(reg32 *)CYREG_PERI_DIV_CMD) +#define UART_1_SCBCLK_CTRL_REG (*(reg32 *)UART_1_SCBCLK__CTRL_REGISTER) +#define UART_1_SCBCLK_DIV_REG (*(reg32 *)UART_1_SCBCLK__DIV_REGISTER) + +#define UART_1_SCBCLK_CMD_DIV_SHIFT (0u) +#define UART_1_SCBCLK_CMD_PA_DIV_SHIFT (8u) +#define UART_1_SCBCLK_CMD_DISABLE_SHIFT (30u) +#define UART_1_SCBCLK_CMD_ENABLE_SHIFT (31u) + +#define UART_1_SCBCLK_CMD_DISABLE_MASK ((uint32)((uint32)1u << UART_1_SCBCLK_CMD_DISABLE_SHIFT)) +#define UART_1_SCBCLK_CMD_ENABLE_MASK ((uint32)((uint32)1u << UART_1_SCBCLK_CMD_ENABLE_SHIFT)) + +#define UART_1_SCBCLK_DIV_FRAC_MASK (0x000000F8u) +#define UART_1_SCBCLK_DIV_FRAC_SHIFT (3u) +#define UART_1_SCBCLK_DIV_INT_MASK (0xFFFFFF00u) +#define UART_1_SCBCLK_DIV_INT_SHIFT (8u) + +#else + +#define UART_1_SCBCLK_DIV_REG (*(reg32 *)UART_1_SCBCLK__REGISTER) +#define UART_1_SCBCLK_ENABLE_REG UART_1_SCBCLK_DIV_REG +#define UART_1_SCBCLK_DIV_FRAC_MASK UART_1_SCBCLK__FRAC_MASK +#define UART_1_SCBCLK_DIV_FRAC_SHIFT (16u) +#define UART_1_SCBCLK_DIV_INT_MASK UART_1_SCBCLK__DIVIDER_MASK +#define UART_1_SCBCLK_DIV_INT_SHIFT (0u) + +#endif/* CYREG_PERI_DIV_CMD */ + +#endif /* !defined(CY_CLOCK_UART_1_SCBCLK_H) */ + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_SCB_IRQ.c b/cores/asr650x/projects/PSoC4/UART_1_SCB_IRQ.c new file mode 100644 index 00000000..8f8e421b --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_SCB_IRQ.c @@ -0,0 +1,406 @@ +/******************************************************************************* +* File Name: UART_1_SCB_IRQ.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include +#include "cyapicallbacks.h" + +#if !defined(UART_1_SCB_IRQ__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START UART_1_SCB_IRQ_intc` */ + +/* `#END` */ + +extern cyisraddress CyRamVectors[CYINT_IRQ_BASE + CY_NUM_INTERRUPTS]; + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_SCB_IRQ_Start(void) +{ + /* For all we know the interrupt is active. */ + UART_1_SCB_IRQ_Disable(); + + /* Set the ISR to point to the UART_1_SCB_IRQ Interrupt. */ + UART_1_SCB_IRQ_SetVector(&UART_1_SCB_IRQ_Interrupt); + + /* Set the priority. */ + UART_1_SCB_IRQ_SetPriority((uint8)UART_1_SCB_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + UART_1_SCB_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_SCB_IRQ_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + UART_1_SCB_IRQ_Disable(); + + /* Set the ISR to point to the UART_1_SCB_IRQ Interrupt. */ + UART_1_SCB_IRQ_SetVector(address); + + /* Set the priority. */ + UART_1_SCB_IRQ_SetPriority((uint8)UART_1_SCB_IRQ_INTC_PRIOR_NUMBER); + + /* Enable it. */ + UART_1_SCB_IRQ_Enable(); +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_SCB_IRQ_Stop(void) +{ + /* Disable this interrupt. */ + UART_1_SCB_IRQ_Disable(); + + /* Set the ISR to point to the passive one. */ + UART_1_SCB_IRQ_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for UART_1_SCB_IRQ. +* +* Add custom code between the START and END comments to keep the next version +* of this file from over-writing your code. +* +* Note You may use either the default ISR by using this API, or you may define +* your own separate ISR through ISR_StartEx(). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(UART_1_SCB_IRQ_Interrupt) +{ + #ifdef UART_1_SCB_IRQ_INTERRUPT_INTERRUPT_CALLBACK + UART_1_SCB_IRQ_Interrupt_InterruptCallback(); + #endif /* UART_1_SCB_IRQ_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START UART_1_SCB_IRQ_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling UART_1_SCB_IRQ_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use UART_1_SCB_IRQ_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_SCB_IRQ_SetVector(cyisraddress address) +{ + CyRamVectors[CYINT_IRQ_BASE + UART_1_SCB_IRQ__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress UART_1_SCB_IRQ_GetVector(void) +{ + return CyRamVectors[CYINT_IRQ_BASE + UART_1_SCB_IRQ__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling UART_1_SCB_IRQ_Start or UART_1_SCB_IRQ_StartEx will +* override any effect this API would have had. This API should only be called +* after UART_1_SCB_IRQ_Start or UART_1_SCB_IRQ_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_SCB_IRQ_SetPriority(uint8 priority) +{ + uint8 interruptState; + uint32 priorityOffset = ((UART_1_SCB_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + interruptState = CyEnterCriticalSection(); + *UART_1_SCB_IRQ_INTC_PRIOR = (*UART_1_SCB_IRQ_INTC_PRIOR & (uint32)(~UART_1_SCB_IRQ__INTC_PRIOR_MASK)) | + ((uint32)priority << priorityOffset); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 UART_1_SCB_IRQ_GetPriority(void) +{ + uint32 priority; + uint32 priorityOffset = ((UART_1_SCB_IRQ__INTC_NUMBER % 4u) * 8u) + 6u; + + priority = (*UART_1_SCB_IRQ_INTC_PRIOR & UART_1_SCB_IRQ__INTC_PRIOR_MASK) >> priorityOffset; + + return (uint8)priority; +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_SCB_IRQ_Enable(void) +{ + /* Enable the general interrupt. */ + *UART_1_SCB_IRQ_INTC_SET_EN = UART_1_SCB_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 UART_1_SCB_IRQ_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*UART_1_SCB_IRQ_INTC_SET_EN & (uint32)UART_1_SCB_IRQ__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_SCB_IRQ_Disable(void) +{ + /* Disable the general interrupt. */ + *UART_1_SCB_IRQ_INTC_CLR_EN = UART_1_SCB_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void UART_1_SCB_IRQ_SetPending(void) +{ + *UART_1_SCB_IRQ_INTC_SET_PD = UART_1_SCB_IRQ__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: UART_1_SCB_IRQ_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void UART_1_SCB_IRQ_ClearPending(void) +{ + *UART_1_SCB_IRQ_INTC_CLR_PD = UART_1_SCB_IRQ__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_SCB_IRQ.h b/cores/asr650x/projects/PSoC4/UART_1_SCB_IRQ.h new file mode 100644 index 00000000..6aae9693 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_SCB_IRQ.h @@ -0,0 +1,80 @@ +/******************************************************************************* +* File Name: UART_1_SCB_IRQ.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + + +#if !defined(CY_ISR_UART_1_SCB_IRQ_H) +#define CY_ISR_UART_1_SCB_IRQ_H + + +#include +#include + +/* Interrupt Controller API. */ +void UART_1_SCB_IRQ_Start(void); +void UART_1_SCB_IRQ_StartEx(cyisraddress address); +void UART_1_SCB_IRQ_Stop(void); + +CY_ISR_PROTO(UART_1_SCB_IRQ_Interrupt); + +void UART_1_SCB_IRQ_SetVector(cyisraddress address); +cyisraddress UART_1_SCB_IRQ_GetVector(void); + +void UART_1_SCB_IRQ_SetPriority(uint8 priority); +uint8 UART_1_SCB_IRQ_GetPriority(void); + +void UART_1_SCB_IRQ_Enable(void); +uint8 UART_1_SCB_IRQ_GetState(void); +void UART_1_SCB_IRQ_Disable(void); + +void UART_1_SCB_IRQ_SetPending(void); +void UART_1_SCB_IRQ_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the UART_1_SCB_IRQ ISR. */ +#define UART_1_SCB_IRQ_INTC_VECTOR ((reg32 *) UART_1_SCB_IRQ__INTC_VECT) + +/* Address of the UART_1_SCB_IRQ ISR priority. */ +#define UART_1_SCB_IRQ_INTC_PRIOR ((reg32 *) UART_1_SCB_IRQ__INTC_PRIOR_REG) + +/* Priority of the UART_1_SCB_IRQ interrupt. */ +#define UART_1_SCB_IRQ_INTC_PRIOR_NUMBER UART_1_SCB_IRQ__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable UART_1_SCB_IRQ interrupt. */ +#define UART_1_SCB_IRQ_INTC_SET_EN ((reg32 *) UART_1_SCB_IRQ__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the UART_1_SCB_IRQ interrupt. */ +#define UART_1_SCB_IRQ_INTC_CLR_EN ((reg32 *) UART_1_SCB_IRQ__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the UART_1_SCB_IRQ interrupt state to pending. */ +#define UART_1_SCB_IRQ_INTC_SET_PD ((reg32 *) UART_1_SCB_IRQ__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the UART_1_SCB_IRQ interrupt. */ +#define UART_1_SCB_IRQ_INTC_CLR_PD ((reg32 *) UART_1_SCB_IRQ__INTC_CLR_PD_REG) + + + +#endif /* CY_ISR_UART_1_SCB_IRQ_H */ + + +#ifdef __cplusplus +} +#endif + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_SPI_UART.c b/cores/asr650x/projects/PSoC4/UART_1_SPI_UART.c new file mode 100644 index 00000000..643ca0be --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_SPI_UART.c @@ -0,0 +1,603 @@ +/***************************************************************************//** +* \file UART_1_SPI_UART.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component in +* SPI and UART modes. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_1_PVT.h" +#include "UART_1_SPI_UART_PVT.h" + +/*************************************** +* SPI/UART Private Vars +***************************************/ + +#if(UART_1_INTERNAL_RX_SW_BUFFER_CONST) + /* Start index to put data into the software receive buffer.*/ + volatile uint32 UART_1_rxBufferHead; + /* Start index to get data from the software receive buffer.*/ + volatile uint32 UART_1_rxBufferTail; + /** + * \addtogroup group_globals + * \{ + */ + /** Sets when internal software receive buffer overflow + * was occurred. + */ + volatile uint8 UART_1_rxBufferOverflow; + /** \} globals */ +#endif /* (UART_1_INTERNAL_RX_SW_BUFFER_CONST) */ + +#if(UART_1_INTERNAL_TX_SW_BUFFER_CONST) + /* Start index to put data into the software transmit buffer.*/ + volatile uint32 UART_1_txBufferHead; + /* Start index to get data from the software transmit buffer.*/ + volatile uint32 UART_1_txBufferTail; +#endif /* (UART_1_INTERNAL_TX_SW_BUFFER_CONST) */ + +#if(UART_1_INTERNAL_RX_SW_BUFFER) + /* Add one element to the buffer to receive full packet. One byte in receive buffer is always empty */ + volatile uint8 UART_1_rxBufferInternal[UART_1_INTERNAL_RX_BUFFER_SIZE]; +#endif /* (UART_1_INTERNAL_RX_SW_BUFFER) */ + +#if(UART_1_INTERNAL_TX_SW_BUFFER) + volatile uint8 UART_1_txBufferInternal[UART_1_TX_BUFFER_SIZE]; +#endif /* (UART_1_INTERNAL_TX_SW_BUFFER) */ + + +#if(UART_1_RX_DIRECTION) + /******************************************************************************* + * Function Name: UART_1_SpiUartReadRxData + ****************************************************************************//** + * + * Retrieves the next data element from the receive buffer. + * - RX software buffer is disabled: Returns data element retrieved from + * RX FIFO. Undefined data will be returned if the RX FIFO is empty. + * - RX software buffer is enabled: Returns data element from the software + * receive buffer. Zero value is returned if the software receive buffer + * is empty. + * + * \return + * Next data element from the receive buffer. + * The amount of data bits to be received depends on RX data bits selection + * (the data bit counting starts from LSB of return value). + * + * \globalvars + * UART_1_rxBufferHead - the start index to put data into the + * software receive buffer. + * UART_1_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + uint32 UART_1_SpiUartReadRxData(void) + { + uint32 rxData = 0u; + + #if (UART_1_INTERNAL_RX_SW_BUFFER_CONST) + uint32 locTail; + #endif /* (UART_1_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if (UART_1_CHECK_RX_SW_BUFFER) + { + if (UART_1_rxBufferHead != UART_1_rxBufferTail) + { + /* There is data in RX software buffer */ + + /* Calculate index to read from */ + locTail = (UART_1_rxBufferTail + 1u); + + if (UART_1_INTERNAL_RX_BUFFER_SIZE == locTail) + { + locTail = 0u; + } + + /* Get data from RX software buffer */ + rxData = UART_1_GetWordFromRxBuffer(locTail); + + /* Change index in the buffer */ + UART_1_rxBufferTail = locTail; + + #if (UART_1_CHECK_UART_RTS_CONTROL_FLOW) + { + /* Check if RX Not Empty is disabled in the interrupt */ + if (0u == (UART_1_INTR_RX_MASK_REG & UART_1_INTR_RX_NOT_EMPTY)) + { + /* Enable RX Not Empty interrupt source to continue + * receiving data into software buffer. + */ + UART_1_INTR_RX_MASK_REG |= UART_1_INTR_RX_NOT_EMPTY; + } + } + #endif + + } + } + #else + { + /* Read data from RX FIFO */ + rxData = UART_1_RX_FIFO_RD_REG; + } + #endif + + return (rxData); + } + + + /******************************************************************************* + * Function Name: UART_1_SpiUartGetRxBufferSize + ****************************************************************************//** + * + * Returns the number of received data elements in the receive buffer. + * - RX software buffer disabled: returns the number of used entries in + * RX FIFO. + * - RX software buffer enabled: returns the number of elements which were + * placed in the receive buffer. This does not include the hardware RX FIFO. + * + * \return + * Number of received data elements. + * + * \globalvars + * UART_1_rxBufferHead - the start index to put data into the + * software receive buffer. + * UART_1_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + uint32 UART_1_SpiUartGetRxBufferSize(void) + { + uint32 size; + #if (UART_1_INTERNAL_RX_SW_BUFFER_CONST) + uint32 locHead; + #endif /* (UART_1_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if (UART_1_CHECK_RX_SW_BUFFER) + { + locHead = UART_1_rxBufferHead; + + if(locHead >= UART_1_rxBufferTail) + { + size = (locHead - UART_1_rxBufferTail); + } + else + { + size = (locHead + (UART_1_INTERNAL_RX_BUFFER_SIZE - UART_1_rxBufferTail)); + } + } + #else + { + size = UART_1_GET_RX_FIFO_ENTRIES; + } + #endif + + return (size); + } + + + /******************************************************************************* + * Function Name: UART_1_SpiUartClearRxBuffer + ****************************************************************************//** + * + * Clears the receive buffer and RX FIFO. + * + * \globalvars + * UART_1_rxBufferHead - the start index to put data into the + * software receive buffer. + * UART_1_rxBufferTail - the start index to get data from the + * software receive buffer. + * + *******************************************************************************/ + void UART_1_SpiUartClearRxBuffer(void) + { + #if (UART_1_CHECK_RX_SW_BUFFER) + { + /* Lock from component interruption */ + UART_1_DisableInt(); + + /* Flush RX software buffer */ + UART_1_rxBufferHead = UART_1_rxBufferTail; + UART_1_rxBufferOverflow = 0u; + + UART_1_CLEAR_RX_FIFO; + UART_1_ClearRxInterruptSource(UART_1_INTR_RX_ALL); + + #if (UART_1_CHECK_UART_RTS_CONTROL_FLOW) + { + /* Enable RX Not Empty interrupt source to continue receiving + * data into software buffer. + */ + UART_1_INTR_RX_MASK_REG |= UART_1_INTR_RX_NOT_EMPTY; + } + #endif + + /* Release lock */ + UART_1_EnableInt(); + } + #else + { + UART_1_CLEAR_RX_FIFO; + } + #endif + } + +#endif /* (UART_1_RX_DIRECTION) */ + + +#if(UART_1_TX_DIRECTION) + /******************************************************************************* + * Function Name: UART_1_SpiUartWriteTxData + ****************************************************************************//** + * + * Places a data entry into the transmit buffer to be sent at the next available + * bus time. + * This function is blocking and waits until there is space available to put the + * requested data in the transmit buffer. + * + * \param txDataByte: the data to be transmitted. + * The amount of data bits to be transmitted depends on TX data bits selection + * (the data bit counting starts from LSB of txDataByte). + * + * \globalvars + * UART_1_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_1_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void UART_1_SpiUartWriteTxData(uint32 txData) + { + #if (UART_1_INTERNAL_TX_SW_BUFFER_CONST) + uint32 locHead; + #endif /* (UART_1_INTERNAL_TX_SW_BUFFER_CONST) */ + + #if (UART_1_CHECK_TX_SW_BUFFER) + { + /* Put data directly into the TX FIFO */ + if ((UART_1_txBufferHead == UART_1_txBufferTail) && + (UART_1_SPI_UART_FIFO_SIZE != UART_1_GET_TX_FIFO_ENTRIES)) + { + /* TX software buffer is empty: put data directly in TX FIFO */ + UART_1_TX_FIFO_WR_REG = txData; + } + /* Put data into TX software buffer */ + else + { + /* Head index to put data */ + locHead = (UART_1_txBufferHead + 1u); + + /* Adjust TX software buffer index */ + if (UART_1_TX_BUFFER_SIZE == locHead) + { + locHead = 0u; + } + + /* Wait for space in TX software buffer */ + while (locHead == UART_1_txBufferTail) + { + } + + /* TX software buffer has at least one room */ + + /* Clear old status of INTR_TX_NOT_FULL. It sets at the end of transfer when TX FIFO is empty. */ + UART_1_ClearTxInterruptSource(UART_1_INTR_TX_NOT_FULL); + + UART_1_PutWordInTxBuffer(locHead, txData); + + UART_1_txBufferHead = locHead; + + /* Check if TX Not Full is disabled in interrupt */ + if (0u == (UART_1_INTR_TX_MASK_REG & UART_1_INTR_TX_NOT_FULL)) + { + /* Enable TX Not Full interrupt source to transmit from software buffer */ + UART_1_INTR_TX_MASK_REG |= (uint32) UART_1_INTR_TX_NOT_FULL; + } + } + } + #else + { + /* Wait until TX FIFO has space to put data element */ + while (UART_1_SPI_UART_FIFO_SIZE == UART_1_GET_TX_FIFO_ENTRIES) + { + } + + UART_1_TX_FIFO_WR_REG = txData; + } + #endif + } + + + /******************************************************************************* + * Function Name: UART_1_SpiUartPutArray + ****************************************************************************//** + * + * Places an array of data into the transmit buffer to be sent. + * This function is blocking and waits until there is a space available to put + * all the requested data in the transmit buffer. The array size can be greater + * than transmit buffer size. + * + * \param wrBuf: pointer to an array of data to be placed in transmit buffer. + * The width of the data to be transmitted depends on TX data width selection + * (the data bit counting starts from LSB for each array element). + * \param count: number of data elements to be placed in the transmit buffer. + * + * \globalvars + * UART_1_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_1_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void UART_1_SpiUartPutArray(const uint8 wrBuf[], uint32 count) + { + uint32 i; + + for (i=0u; i < count; i++) + { + UART_1_SpiUartWriteTxData((uint32) wrBuf[i]); + } + } + + + /******************************************************************************* + * Function Name: UART_1_SpiUartGetTxBufferSize + ****************************************************************************//** + * + * Returns the number of elements currently in the transmit buffer. + * - TX software buffer is disabled: returns the number of used entries in + * TX FIFO. + * - TX software buffer is enabled: returns the number of elements currently + * used in the transmit buffer. This number does not include used entries in + * the TX FIFO. The transmit buffer size is zero until the TX FIFO is + * not full. + * + * \return + * Number of data elements ready to transmit. + * + * \globalvars + * UART_1_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_1_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + uint32 UART_1_SpiUartGetTxBufferSize(void) + { + uint32 size; + #if (UART_1_INTERNAL_TX_SW_BUFFER_CONST) + uint32 locTail; + #endif /* (UART_1_INTERNAL_TX_SW_BUFFER_CONST) */ + + #if (UART_1_CHECK_TX_SW_BUFFER) + { + /* Get current Tail index */ + locTail = UART_1_txBufferTail; + + if (UART_1_txBufferHead >= locTail) + { + size = (UART_1_txBufferHead - locTail); + } + else + { + size = (UART_1_txBufferHead + (UART_1_TX_BUFFER_SIZE - locTail)); + } + } + #else + { + size = UART_1_GET_TX_FIFO_ENTRIES; + } + #endif + + return (size); + } + + + /******************************************************************************* + * Function Name: UART_1_SpiUartClearTxBuffer + ****************************************************************************//** + * + * Clears the transmit buffer and TX FIFO. + * + * \globalvars + * UART_1_txBufferHead - the start index to put data into the + * software transmit buffer. + * UART_1_txBufferTail - start index to get data from the software + * transmit buffer. + * + *******************************************************************************/ + void UART_1_SpiUartClearTxBuffer(void) + { + #if (UART_1_CHECK_TX_SW_BUFFER) + { + /* Lock from component interruption */ + UART_1_DisableInt(); + + /* Flush TX software buffer */ + UART_1_txBufferHead = UART_1_txBufferTail; + + UART_1_INTR_TX_MASK_REG &= (uint32) ~UART_1_INTR_TX_NOT_FULL; + UART_1_CLEAR_TX_FIFO; + UART_1_ClearTxInterruptSource(UART_1_INTR_TX_ALL); + + /* Release lock */ + UART_1_EnableInt(); + } + #else + { + UART_1_CLEAR_TX_FIFO; + } + #endif + } + +#endif /* (UART_1_TX_DIRECTION) */ + + +/******************************************************************************* +* Function Name: UART_1_SpiUartDisableIntRx +****************************************************************************//** +* +* Disables the RX interrupt sources. +* +* \return +* Returns the RX interrupt sources enabled before the function call. +* +*******************************************************************************/ +uint32 UART_1_SpiUartDisableIntRx(void) +{ + uint32 intSource; + + intSource = UART_1_GetRxInterruptMode(); + + UART_1_SetRxInterruptMode(UART_1_NO_INTR_SOURCES); + + return (intSource); +} + + +/******************************************************************************* +* Function Name: UART_1_SpiUartDisableIntTx +****************************************************************************//** +* +* Disables TX interrupt sources. +* +* \return +* Returns TX interrupt sources enabled before function call. +* +*******************************************************************************/ +uint32 UART_1_SpiUartDisableIntTx(void) +{ + uint32 intSourceMask; + + intSourceMask = UART_1_GetTxInterruptMode(); + + UART_1_SetTxInterruptMode(UART_1_NO_INTR_SOURCES); + + return (intSourceMask); +} + + +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + /******************************************************************************* + * Function Name: UART_1_PutWordInRxBuffer + ****************************************************************************//** + * + * Stores a byte/word into the RX buffer. + * Only available in the Unconfigured operation mode. + * + * \param index: index to store data byte/word in the RX buffer. + * \param rxDataByte: byte/word to store. + * + *******************************************************************************/ + void UART_1_PutWordInRxBuffer(uint32 idx, uint32 rxDataByte) + { + /* Put data in buffer */ + if (UART_1_ONE_BYTE_WIDTH == UART_1_rxDataBits) + { + UART_1_rxBuffer[idx] = ((uint8) rxDataByte); + } + else + { + UART_1_rxBuffer[(uint32)(idx << 1u)] = LO8(LO16(rxDataByte)); + UART_1_rxBuffer[(uint32)(idx << 1u) + 1u] = HI8(LO16(rxDataByte)); + } + } + + + /******************************************************************************* + * Function Name: UART_1_GetWordFromRxBuffer + ****************************************************************************//** + * + * Reads byte/word from RX buffer. + * Only available in the Unconfigured operation mode. + * + * \return + * Returns byte/word read from RX buffer. + * + *******************************************************************************/ + uint32 UART_1_GetWordFromRxBuffer(uint32 idx) + { + uint32 value; + + if (UART_1_ONE_BYTE_WIDTH == UART_1_rxDataBits) + { + value = UART_1_rxBuffer[idx]; + } + else + { + value = (uint32) UART_1_rxBuffer[(uint32)(idx << 1u)]; + value |= (uint32) ((uint32)UART_1_rxBuffer[(uint32)(idx << 1u) + 1u] << 8u); + } + + return (value); + } + + + /******************************************************************************* + * Function Name: UART_1_PutWordInTxBuffer + ****************************************************************************//** + * + * Stores byte/word into the TX buffer. + * Only available in the Unconfigured operation mode. + * + * \param idx: index to store data byte/word in the TX buffer. + * \param txDataByte: byte/word to store. + * + *******************************************************************************/ + void UART_1_PutWordInTxBuffer(uint32 idx, uint32 txDataByte) + { + /* Put data in buffer */ + if (UART_1_ONE_BYTE_WIDTH == UART_1_txDataBits) + { + UART_1_txBuffer[idx] = ((uint8) txDataByte); + } + else + { + UART_1_txBuffer[(uint32)(idx << 1u)] = LO8(LO16(txDataByte)); + UART_1_txBuffer[(uint32)(idx << 1u) + 1u] = HI8(LO16(txDataByte)); + } + } + + + /******************************************************************************* + * Function Name: UART_1_GetWordFromTxBuffer + ****************************************************************************//** + * + * Reads byte/word from the TX buffer. + * Only available in the Unconfigured operation mode. + * + * \param idx: index to get data byte/word from the TX buffer. + * + * \return + * Returns byte/word read from the TX buffer. + * + *******************************************************************************/ + uint32 UART_1_GetWordFromTxBuffer(uint32 idx) + { + uint32 value; + + if (UART_1_ONE_BYTE_WIDTH == UART_1_txDataBits) + { + value = (uint32) UART_1_txBuffer[idx]; + } + else + { + value = (uint32) UART_1_txBuffer[(uint32)(idx << 1u)]; + value |= (uint32) ((uint32) UART_1_txBuffer[(uint32)(idx << 1u) + 1u] << 8u); + } + + return (value); + } + +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_SPI_UART.h b/cores/asr650x/projects/PSoC4/UART_1_SPI_UART.h new file mode 100644 index 00000000..78ef174c --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_SPI_UART.h @@ -0,0 +1,1241 @@ +/***************************************************************************//** +* \file UART_1_SPI_UART.h +* \version 4.0 +* +* \brief +* This file provides constants and parameter values for the SCB Component in +* SPI and UART modes. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + + + +#if !defined(CY_SCB_SPI_UART_UART_1_H) +#define CY_SCB_SPI_UART_UART_1_H + +#include "UART_1.h" + + +/*************************************** +* SPI Initial Parameter Constants +****************************************/ + +#define UART_1_SPI_MODE (0u) +#define UART_1_SPI_SUB_MODE (0u) +#define UART_1_SPI_CLOCK_MODE (0u) +#define UART_1_SPI_OVS_FACTOR (16u) +#define UART_1_SPI_MEDIAN_FILTER_ENABLE (0u) +#define UART_1_SPI_LATE_MISO_SAMPLE_ENABLE (0u) +#define UART_1_SPI_RX_DATA_BITS_NUM (8u) +#define UART_1_SPI_TX_DATA_BITS_NUM (8u) +#define UART_1_SPI_WAKE_ENABLE (0u) +#define UART_1_SPI_BITS_ORDER (1u) +#define UART_1_SPI_TRANSFER_SEPARATION (1u) +#define UART_1_SPI_NUMBER_OF_SS_LINES (1u) +#define UART_1_SPI_RX_BUFFER_SIZE (8u) +#define UART_1_SPI_TX_BUFFER_SIZE (8u) + +#define UART_1_SPI_INTERRUPT_MODE (0u) + +#define UART_1_SPI_INTR_RX_MASK (0x0u) +#define UART_1_SPI_INTR_TX_MASK (0x0u) + +#define UART_1_SPI_RX_TRIGGER_LEVEL (7u) +#define UART_1_SPI_TX_TRIGGER_LEVEL (0u) + +#define UART_1_SPI_BYTE_MODE_ENABLE (0u) +#define UART_1_SPI_FREE_RUN_SCLK_ENABLE (0u) +#define UART_1_SPI_SS0_POLARITY (0u) +#define UART_1_SPI_SS1_POLARITY (0u) +#define UART_1_SPI_SS2_POLARITY (0u) +#define UART_1_SPI_SS3_POLARITY (0u) + + +/*************************************** +* UART Initial Parameter Constants +****************************************/ + +#define UART_1_UART_SUB_MODE (0u) +#define UART_1_UART_DIRECTION (3u) +#define UART_1_UART_DATA_BITS_NUM (8u) +#define UART_1_UART_PARITY_TYPE (2u) +#define UART_1_UART_STOP_BITS_NUM (2u) +#define UART_1_UART_OVS_FACTOR (13u) +#define UART_1_UART_IRDA_LOW_POWER (0u) +#define UART_1_UART_MEDIAN_FILTER_ENABLE (0u) +#define UART_1_UART_RETRY_ON_NACK (0u) +#define UART_1_UART_IRDA_POLARITY (0u) +#define UART_1_UART_DROP_ON_FRAME_ERR (0u) +#define UART_1_UART_DROP_ON_PARITY_ERR (0u) +#define UART_1_UART_WAKE_ENABLE (1u) +#define UART_1_UART_RX_BUFFER_SIZE (8u) +#define UART_1_UART_TX_BUFFER_SIZE (8u) +#define UART_1_UART_MP_MODE_ENABLE (0u) +#define UART_1_UART_MP_ACCEPT_ADDRESS (0u) +#define UART_1_UART_MP_RX_ADDRESS (0x2u) +#define UART_1_UART_MP_RX_ADDRESS_MASK (0xFFu) + +#define UART_1_UART_INTERRUPT_MODE (1u) + +#define UART_1_UART_INTR_RX_MASK (0x4u) +#define UART_1_UART_INTR_TX_MASK (0x0u) + +#define UART_1_UART_RX_TRIGGER_LEVEL (7u) +#define UART_1_UART_TX_TRIGGER_LEVEL (0u) + +#define UART_1_UART_BYTE_MODE_ENABLE (0u) +#define UART_1_UART_CTS_ENABLE (0u) +#define UART_1_UART_CTS_POLARITY (0u) +#define UART_1_UART_RTS_ENABLE (0u) +#define UART_1_UART_RTS_POLARITY (0u) +#define UART_1_UART_RTS_FIFO_LEVEL (4u) + +#define UART_1_UART_RX_BREAK_WIDTH (11u) + +/* SPI mode enum */ +#define UART_1_SPI_SLAVE (0u) +#define UART_1_SPI_MASTER (1u) + +/* UART direction enum */ +#define UART_1_UART_RX (1u) +#define UART_1_UART_TX (2u) +#define UART_1_UART_TX_RX (3u) + + +/*************************************** +* Conditional Compilation Parameters +****************************************/ + +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + + /* Mode */ + #define UART_1_SPI_SLAVE_CONST (1u) + #define UART_1_SPI_MASTER_CONST (1u) + + /* Direction */ + #define UART_1_RX_DIRECTION (1u) + #define UART_1_TX_DIRECTION (1u) + #define UART_1_UART_RX_DIRECTION (1u) + #define UART_1_UART_TX_DIRECTION (1u) + + /* Only external RX and TX buffer for Uncofigured mode */ + #define UART_1_INTERNAL_RX_SW_BUFFER (0u) + #define UART_1_INTERNAL_TX_SW_BUFFER (0u) + + /* Get RX and TX buffer size */ + #define UART_1_INTERNAL_RX_BUFFER_SIZE (UART_1_rxBufferSize + 1u) + #define UART_1_RX_BUFFER_SIZE (UART_1_rxBufferSize) + #define UART_1_TX_BUFFER_SIZE (UART_1_txBufferSize) + + /* Return true if buffer is provided */ + #define UART_1_CHECK_RX_SW_BUFFER (NULL != UART_1_rxBuffer) + #define UART_1_CHECK_TX_SW_BUFFER (NULL != UART_1_txBuffer) + + /* Always provide global variables to support RX and TX buffers */ + #define UART_1_INTERNAL_RX_SW_BUFFER_CONST (1u) + #define UART_1_INTERNAL_TX_SW_BUFFER_CONST (1u) + + /* Get wakeup enable option */ + #define UART_1_SPI_WAKE_ENABLE_CONST (1u) + #define UART_1_UART_WAKE_ENABLE_CONST (1u) + #define UART_1_CHECK_SPI_WAKE_ENABLE ((0u != UART_1_scbEnableWake) && UART_1_SCB_MODE_SPI_RUNTM_CFG) + #define UART_1_CHECK_UART_WAKE_ENABLE ((0u != UART_1_scbEnableWake) && UART_1_SCB_MODE_UART_RUNTM_CFG) + + /* SPI/UART: TX or RX FIFO size */ + #if (UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + #define UART_1_SPI_UART_FIFO_SIZE (UART_1_FIFO_SIZE) + #define UART_1_CHECK_UART_RTS_CONTROL_FLOW (0u) + #else + #define UART_1_SPI_UART_FIFO_SIZE (UART_1_GET_FIFO_SIZE(UART_1_CTRL_REG & \ + UART_1_CTRL_BYTE_MODE)) + + #define UART_1_CHECK_UART_RTS_CONTROL_FLOW \ + ((UART_1_SCB_MODE_UART_RUNTM_CFG) && \ + (0u != UART_1_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(UART_1_UART_FLOW_CTRL_REG))) + #endif /* (UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + +#else + + /* Internal RX and TX buffer: for SPI or UART */ + #if (UART_1_SCB_MODE_SPI_CONST_CFG) + + /* SPI Direction */ + #define UART_1_SPI_RX_DIRECTION (1u) + #define UART_1_SPI_TX_DIRECTION (1u) + + /* Get FIFO size */ + #define UART_1_SPI_UART_FIFO_SIZE UART_1_GET_FIFO_SIZE(UART_1_SPI_BYTE_MODE_ENABLE) + + /* SPI internal RX and TX buffers */ + #define UART_1_INTERNAL_SPI_RX_SW_BUFFER (UART_1_SPI_RX_BUFFER_SIZE > \ + UART_1_SPI_UART_FIFO_SIZE) + #define UART_1_INTERNAL_SPI_TX_SW_BUFFER (UART_1_SPI_TX_BUFFER_SIZE > \ + UART_1_SPI_UART_FIFO_SIZE) + + /* Internal SPI RX and TX buffer */ + #define UART_1_INTERNAL_RX_SW_BUFFER (UART_1_INTERNAL_SPI_RX_SW_BUFFER) + #define UART_1_INTERNAL_TX_SW_BUFFER (UART_1_INTERNAL_SPI_TX_SW_BUFFER) + + /* Internal SPI RX and TX buffer size */ + #define UART_1_INTERNAL_RX_BUFFER_SIZE (UART_1_SPI_RX_BUFFER_SIZE + 1u) + #define UART_1_RX_BUFFER_SIZE (UART_1_SPI_RX_BUFFER_SIZE) + #define UART_1_TX_BUFFER_SIZE (UART_1_SPI_TX_BUFFER_SIZE) + + /* Get wakeup enable option */ + #define UART_1_SPI_WAKE_ENABLE_CONST (0u != UART_1_SPI_WAKE_ENABLE) + #define UART_1_UART_WAKE_ENABLE_CONST (0u) + + #else + + /* UART Direction */ + #define UART_1_UART_RX_DIRECTION (0u != (UART_1_UART_DIRECTION & UART_1_UART_RX)) + #define UART_1_UART_TX_DIRECTION (0u != (UART_1_UART_DIRECTION & UART_1_UART_TX)) + + /* Get FIFO size */ + #define UART_1_SPI_UART_FIFO_SIZE UART_1_GET_FIFO_SIZE(UART_1_UART_BYTE_MODE_ENABLE) + + /* UART internal RX and TX buffers */ + #define UART_1_INTERNAL_UART_RX_SW_BUFFER (UART_1_UART_RX_BUFFER_SIZE > \ + UART_1_SPI_UART_FIFO_SIZE) + #define UART_1_INTERNAL_UART_TX_SW_BUFFER (UART_1_UART_TX_BUFFER_SIZE > \ + UART_1_SPI_UART_FIFO_SIZE) + + /* Internal UART RX and TX buffer */ + #define UART_1_INTERNAL_RX_SW_BUFFER (UART_1_INTERNAL_UART_RX_SW_BUFFER) + #define UART_1_INTERNAL_TX_SW_BUFFER (UART_1_INTERNAL_UART_TX_SW_BUFFER) + + /* Internal UART RX and TX buffer size */ + #define UART_1_INTERNAL_RX_BUFFER_SIZE (UART_1_UART_RX_BUFFER_SIZE + 1u) + #define UART_1_RX_BUFFER_SIZE (UART_1_UART_RX_BUFFER_SIZE) + #define UART_1_TX_BUFFER_SIZE (UART_1_UART_TX_BUFFER_SIZE) + + /* Get wakeup enable option */ + #define UART_1_SPI_WAKE_ENABLE_CONST (0u) + #define UART_1_UART_WAKE_ENABLE_CONST (0u != UART_1_UART_WAKE_ENABLE) + + #endif /* (UART_1_SCB_MODE_SPI_CONST_CFG) */ + + /* Mode */ + #define UART_1_SPI_SLAVE_CONST (UART_1_SPI_MODE == UART_1_SPI_SLAVE) + #define UART_1_SPI_MASTER_CONST (UART_1_SPI_MODE == UART_1_SPI_MASTER) + + /* Direction */ + #define UART_1_RX_DIRECTION ((UART_1_SCB_MODE_SPI_CONST_CFG) ? \ + (UART_1_SPI_RX_DIRECTION) : (UART_1_UART_RX_DIRECTION)) + + #define UART_1_TX_DIRECTION ((UART_1_SCB_MODE_SPI_CONST_CFG) ? \ + (UART_1_SPI_TX_DIRECTION) : (UART_1_UART_TX_DIRECTION)) + + /* Internal RX and TX buffer: for SPI or UART. Used in conditional compilation check */ + #define UART_1_CHECK_RX_SW_BUFFER (UART_1_INTERNAL_RX_SW_BUFFER) + #define UART_1_CHECK_TX_SW_BUFFER (UART_1_INTERNAL_TX_SW_BUFFER) + + /* Provide global variables to support RX and TX buffers */ + #define UART_1_INTERNAL_RX_SW_BUFFER_CONST (UART_1_INTERNAL_RX_SW_BUFFER) + #define UART_1_INTERNAL_TX_SW_BUFFER_CONST (UART_1_INTERNAL_TX_SW_BUFFER) + + /* Wake up enable */ + #define UART_1_CHECK_SPI_WAKE_ENABLE (UART_1_SPI_WAKE_ENABLE_CONST) + #define UART_1_CHECK_UART_WAKE_ENABLE (UART_1_UART_WAKE_ENABLE_CONST) + + /* UART flow control: not applicable for CY_SCBIP_V0 || CY_SCBIP_V1 */ + #define UART_1_CHECK_UART_RTS_CONTROL_FLOW (UART_1_SCB_MODE_UART_CONST_CFG && \ + UART_1_UART_RTS_ENABLE) + +#endif /* End (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/*************************************** +* Type Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* UART_1_SPI_INIT_STRUCT */ +typedef struct +{ + /** Mode of operation for SPI. The following defines are available choices: + * - UART_1_SPI_SLAVE + * - UART_1_SPI_MASTE + */ + uint32 mode; + + /** Submode of operation for SPI. The following defines are available + * choices: + * - UART_1_SPI_MODE_MOTOROLA + * - UART_1_SPI_MODE_TI_COINCIDES + * - UART_1_SPI_MODE_TI_PRECEDES + * - UART_1_SPI_MODE_NATIONAL + */ + uint32 submode; + + /** Determines the sclk relationship for Motorola submode. Ignored + * for other submodes. The following defines are available choices: + * - UART_1_SPI_SCLK_CPHA0_CPOL0 + * - UART_1_SPI_SCLK_CPHA0_CPOL1 + * - UART_1_SPI_SCLK_CPHA1_CPOL0 + * - UART_1_SPI_SCLK_CPHA1_CPOL1 + */ + uint32 sclkMode; + + /** Oversampling factor for the SPI clock. Ignored for Slave mode operation. + */ + uint32 oversample; + + /** Applies median filter on the input lines: 0 鈥?not applied, 1 鈥?applied. + */ + uint32 enableMedianFilter; + + /** Applies late sampling of MISO line: 0 鈥?not applied, 1 鈥?applied. + * Ignored for slave mode. + */ + uint32 enableLateSampling; + + /** Enables wakeup from low power mode: 0 鈥?disable, 1 鈥?enable. + * Ignored for master mode. + */ + uint32 enableWake; + + /** Number of data bits for RX direction. + * Different dataBitsRx and dataBitsTx are only allowed for National + * submode. + */ + uint32 rxDataBits; + + /** Number of data bits for TX direction. + * Different dataBitsRx and dataBitsTx are only allowed for National + * submode. + */ + uint32 txDataBits; + + /** Determines the bit ordering. The following defines are available + * choices: + * - UART_1_BITS_ORDER_LSB_FIRST + * - UART_1_BITS_ORDER_MSB_FIRST + */ + uint32 bitOrder; + + /** Determines whether transfers are back to back or have SS disabled + * between words. Ignored for slave mode. The following defines are + * available choices: + * - UART_1_SPI_TRANSFER_CONTINUOUS + * - UART_1_SPI_TRANSFER_SEPARATED + */ + uint32 transferSeperation; + + /** Size of the RX buffer in bytes/words (depends on rxDataBits parameter). + * A value equal to the RX FIFO depth implies the usage of buffering in + * hardware. A value greater than the RX FIFO depth results in a software + * buffer. + * The UART_1_INTR _RX_NOT_EMPTY interrupt has to be enabled to + * transfer data into the software buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 rxBufferSize; + + /** Buffer space provided for a RX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal (rxBufferSize + 1) in bytes if + * dataBitsRx is less or equal to 8, otherwise (2 * (rxBufferSize + 1)) + * in bytes. The software RX buffer always keeps one element empty. + * For correct operation the allocated RX buffer has to be one element + * greater than maximum packet size expected to be received. + */ + uint8* rxBuffer; + + /** Size of the TX buffer in bytes/words(depends on txDataBits parameter). + * A value equal to the TX FIFO depth implies the usage of buffering in + * hardware. A value greater than the TX FIFO depth results in a software + * buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 txBufferSize; + + /** Buffer space provided for a TX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal txBufferSize if dataBitsTx is + * less or equal to 8, otherwise (2* txBufferSize). + */ + uint8* txBuffer; + + /** Enables component interrupt: 0 鈥?disable, 1 鈥?enable. + * The interrupt has to be enabled if software buffer is used. + */ + uint32 enableInterrupt; + + /** Mask of enabled interrupt sources for the RX direction. This mask is + * written regardless of the setting of the enable Interrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_1_INTR_RX_FIFO_LEVEL + * - UART_1_INTR_RX_NOT_EMPTY + * - UART_1_INTR_RX_FULL + * - UART_1_INTR_RX_OVERFLOW + * - UART_1_INTR_RX_UNDERFLOW + * - UART_1_INTR_SLAVE_SPI_BUS_ERROR + */ + uint32 rxInterruptMask; + + /** FIFO level for an RX FIFO level interrupt. This value is written + * regardless of whether the RX FIFO level interrupt source is enabled. + */ + uint32 rxTriggerLevel; + + /** Mask of enabled interrupt sources for the TX direction. This mask is + * written regardless of the setting of the enable Interrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_1_INTR_TX_FIFO_LEVEL + * - UART_1_INTR_TX_NOT_FULL + * - UART_1_INTR_TX_EMPTY + * - UART_1_INTR_TX_OVERFLOW + * - UART_1_INTR_TX_UNDERFLOW + * - UART_1_INTR_MASTER_SPI_DONE + */ + uint32 txInterruptMask; + + /** FIFO level for a TX FIFO level interrupt. This value is written + * regardless of whether the TX FIFO level interrupt source is enabled. + */ + uint32 txTriggerLevel; + + /** When enabled the TX and RX FIFO depth is doubled and equal to + * 16 bytes: 0 鈥?disable, 1 鈥?enable. This implies that number of + * TX and RX data bits must be less than or equal to 8. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableByteMode; + + /** Enables continuous SCLK generation by the SPI master: 0 鈥?disable, + * 1 鈥?enable. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableFreeRunSclk; + + /** Active polarity of slave select lines 0-3. This is bit mask where bit + * UART_1_SPI_SLAVE_SELECT0 corresponds to slave select 0 + * polarity, bit UART_1_SPI_SLAVE_SELECT1 鈥?slave select 1 + * polarity and so on. Polarity constants are: + * - UART_1_SPI_SS_ACTIVE_LOW + * - UART_1_SPI_SS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 polaritySs; +} UART_1_SPI_INIT_STRUCT; + + +/* UART_1_UART_INIT_STRUCT */ +typedef struct +{ + /** Mode of operation for the UART. The following defines are available + * choices: + * - UART_1_UART_MODE_STD + * - UART_1_UART_MODE_SMARTCARD + * - UART_1_UART_MODE_IRDA + */ + uint32 mode; + + /** Direction of operation for the UART. The following defines are available + * choices: + * - UART_1_UART_TX_RX + * - UART_1_UART_RX + * - UART_1_UART_TX + */ + uint32 direction; + + /** Number of data bits. + */ + uint32 dataBits; + + /** Determines the parity. The following defines are available choices: + * - UART_1_UART_PARITY_EVEN + * - UART_1_UART_PARITY_ODD + * - UART_1_UART_PARITY_NONE + */ + uint32 parity; + + /** Determines the number of stop bits. The following defines are available + * choices: + * - UART_1_UART_STOP_BITS_1 + * - UART_1_UART_STOP_BITS_1_5 + * - UART_1_UART_STOP_BITS_2 + */ + uint32 stopBits; + + /** Oversampling factor for the UART. + * + * Note The oversampling factor values are changed when enableIrdaLowPower + * is enabled: + * - UART_1_UART_IRDA_LP_OVS16 + * - UART_1_UART_IRDA_LP_OVS32 + * - UART_1_UART_IRDA_LP_OVS48 + * - UART_1_UART_IRDA_LP_OVS96 + * - UART_1_UART_IRDA_LP_OVS192 + * - UART_1_UART_IRDA_LP_OVS768 + * - UART_1_UART_IRDA_LP_OVS1536 + */ + uint32 oversample; + + /** Enables IrDA low power RX mode operation: 0 鈥?disable, 1 鈥?enable. + * The TX functionality does not work when enabled. + */ + uint32 enableIrdaLowPower; + + /** Applies median filter on the input lines: 0 鈥?not applied, 1 鈥?applied. + */ + uint32 enableMedianFilter; + + /** Enables retry when NACK response was received: 0 鈥?disable, 1 鈥?enable. + * Only current content of TX FIFO is re-sent. + * Ignored for modes other than SmartCard. + */ + uint32 enableRetryNack; + + /** Inverts polarity of RX line: 0 鈥?non-inverting, 1 鈥?inverting. + * Ignored for modes other than IrDA. + */ + uint32 enableInvertedRx; + + /** Drop data from RX FIFO if parity error is detected: 0 鈥?disable, + * 1 鈥?enable. + */ + uint32 dropOnParityErr; + + /** Drop data from RX FIFO if a frame error is detected: 0 鈥?disable, + * 1 鈥?enable. + */ + uint32 dropOnFrameErr; + + /** Enables wakeup from low power mode: 0 鈥?disable, 1 鈥?enable. + * Ignored for modes other than standard UART. The RX functionality + * has to be enabled. + */ + uint32 enableWake; + + /** Size of the RX buffer in bytes/words (depends on rxDataBits parameter). + * A value equal to the RX FIFO depth implies the usage of buffering in + * hardware. A value greater than the RX FIFO depth results in a software + * buffer. + * The UART_1_INTR _RX_NOT_EMPTY interrupt has to be enabled to + * transfer data into the software buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 rxBufferSize; + + /** Buffer space provided for a RX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal (rxBufferSize + 1) in bytes if + * dataBitsRx is less or equal to 8, otherwise (2 * (rxBufferSize + 1)) + * in bytes. The software RX buffer always keeps one element empty. + * For correct operation the allocated RX buffer has to be one element + * greater than maximum packet size expected to be received. + */ + uint8* rxBuffer; + + /** Size of the TX buffer in bytes/words(depends on txDataBits parameter). + * A value equal to the TX FIFO depth implies the usage of buffering in + * hardware. A value greater than the TX FIFO depth results in a software + * buffer. + * - The RX and TX FIFO depth is equal to 8 bytes/words for PSoC 4100 / + * PSoC 4200 devices. + * - The RX and TX FIFO depth is equal to 8 bytes/words or 16 + * bytes (Byte mode is enabled) for PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor devices. + */ + uint32 txBufferSize; + + /** Buffer space provided for a TX software buffer: + * - A NULL pointer must be provided to use hardware buffering. + * - A pointer to an allocated buffer must be provided to use software + * buffering. The buffer size must equal txBufferSize if dataBitsTx is + * less or equal to 8, otherwise (2* txBufferSize). + */ + uint8* txBuffer; + + /** Enables multiprocessor mode: 0 鈥?disable, 1 鈥?enable. + */ + uint32 enableMultiproc; + + /** Enables matched address to be accepted: 0 鈥?disable, 1 鈥?enable. + */ + uint32 multiprocAcceptAddr; + + /** 8 bit address to match in Multiprocessor mode. Ignored for other modes. + */ + uint32 multiprocAddr; + + /** 8 bit mask of address bits that are compared for a Multiprocessor + * address match. Ignored for other modes. + * - Bit value 0 鈥?excludes bit from address comparison. + * - Bit value 1 鈥?the bit needs to match with the corresponding bit + * of the device address. + */ + uint32 multiprocAddrMask; + + /** Enables component interrupt: 0 鈥?disable, 1 鈥?enable. + * The interrupt has to be enabled if software buffer is used. + */ + uint32 enableInterrupt; + + /** Mask of interrupt sources to enable in the RX direction. This mask is + * written regardless of the setting of the enableInterrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_1_INTR_RX_FIFO_LEVEL + * - UART_1_INTR_RX_NOT_EMPTY + * - UART_1_INTR_RX_FULL + * - UART_1_INTR_RX_OVERFLOW + * - UART_1_INTR_RX_UNDERFLOW + * - UART_1_INTR_RX_FRAME_ERROR + * - UART_1_INTR_RX_PARITY_ERROR + */ + uint32 rxInterruptMask; + + /** FIFO level for an RX FIFO level interrupt. This value is written + * regardless of whether the RX FIFO level interrupt source is enabled. + */ + uint32 rxTriggerLevel; + + /** Mask of interrupt sources to enable in the TX direction. This mask is + * written regardless of the setting of the enableInterrupt field. + * Multiple sources are enabled by providing a value that is the OR of + * all of the following sources to enable: + * - UART_1_INTR_TX_FIFO_LEVEL + * - UART_1_INTR_TX_NOT_FULL + * - UART_1_INTR_TX_EMPTY + * - UART_1_INTR_TX_OVERFLOW + * - UART_1_INTR_TX_UNDERFLOW + * - UART_1_INTR_TX_UART_DONE + * - UART_1_INTR_TX_UART_NACK + * - UART_1_INTR_TX_UART_ARB_LOST + */ + uint32 txInterruptMask; + + /** FIFO level for a TX FIFO level interrupt. This value is written + * regardless of whether the TX FIFO level interrupt source is enabled. + */ + uint32 txTriggerLevel; + + /** When enabled the TX and RX FIFO depth is doubled and equal to + * 16 bytes: 0 鈥?disable, 1 鈥?enable. This implies that number of + * Data bits must be less than or equal to 8. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableByteMode; + + /** Enables usage of CTS input signal by the UART transmitter : 0 鈥?disable, + * 1 鈥?enable. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 enableCts; + + /** Sets active polarity of CTS input signal: + * - UART_1_UART_CTS_ACTIVE_LOW + * - UART_1_UART_CTS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 ctsPolarity; + + /** RX FIFO level for RTS signal activation. While the RX FIFO has fewer + * entries than the RTS FIFO level value the RTS signal remains active, + * otherwise the RTS signal becomes inactive. By setting this field to 0, + * RTS signal activation is disabled. + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 rtsRxFifoLevel; + + /** Sets active polarity of RTS output signal: + * - UART_1_UART_RTS_ ACTIVE_LOW + * - UART_1_UART_RTS_ACTIVE_HIGH + * + * Ignored for all devices other than PSoC 4100 BLE / PSoC 4200 BLE / + * PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / + * PSoC Analog Coprocessor. + */ + uint8 rtsPolarity; + + /** Configures the width of a break signal in that triggers the break + * detection interrupt source. A Break is a low level on the RX line. + * Valid range is 1-16 UART bits times. + */ + uint8 breakWidth; +} UART_1_UART_INIT_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_spi +* @{ +*/ +/* SPI specific functions */ +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + void UART_1_SpiInit(const UART_1_SPI_INIT_STRUCT *config); +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +#if(UART_1_SCB_MODE_SPI_INC) + /******************************************************************************* + * Function Name: UART_1_SpiIsBusBusy + ****************************************************************************//** + * + * Returns the current status on the bus. The bus status is determined using + * the slave select signal. + * - Motorola and National Semiconductor sub-modes: The bus is busy after + * the slave select line is activated and lasts until the slave select line + * is deactivated. + * - Texas Instrument sub-modes: The bus is busy at the moment of the initial + * pulse on the slave select line and lasts until the transfer is complete. + * If SPI Master is configured to use "Separated transfers" + * (see Continuous versus Separated Transfer Separation), the bus is busy + * during each element transfer and is free between each element transfer. + * The Master does not activate SS line immediately after data has been + * written into the TX FIFO. + * + * \return slaveSelect: Current status on the bus. + * If the returned value is nonzero, the bus is busy. + * If zero is returned, the bus is free. The bus status is determined using + * the slave select signal. + * + *******************************************************************************/ + #define UART_1_SpiIsBusBusy() ((uint32) (0u != (UART_1_SPI_STATUS_REG & \ + UART_1_SPI_STATUS_BUS_BUSY))) + + #if (UART_1_SPI_MASTER_CONST) + void UART_1_SpiSetActiveSlaveSelect(uint32 slaveSelect); + #endif /*(UART_1_SPI_MASTER_CONST) */ + + #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + void UART_1_SpiSetSlaveSelectPolarity(uint32 slaveSelect, uint32 polarity); + #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ +#endif /* (UART_1_SCB_MODE_SPI_INC) */ +/** @} spi */ + +/** +* \addtogroup group_uart +* @{ +*/ +/* UART specific functions */ +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + void UART_1_UartInit(const UART_1_UART_INIT_STRUCT *config); +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if(UART_1_SCB_MODE_UART_INC) + void UART_1_UartSetRxAddress(uint32 address); + void UART_1_UartSetRxAddressMask(uint32 addressMask); + + + /* UART RX direction APIs */ + #if(UART_1_UART_RX_DIRECTION) + uint32 UART_1_UartGetChar(void); + uint32 UART_1_UartGetByte(void); + + #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + /* UART APIs for Flow Control */ + void UART_1_UartSetRtsPolarity(uint32 polarity); + void UART_1_UartSetRtsFifoLevel(uint32 level); + #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + #endif /* (UART_1_UART_RX_DIRECTION) */ + + /* UART TX direction APIs */ + #if(UART_1_UART_TX_DIRECTION) + /******************************************************************************* + * Function Name: UART_1_UartPutChar + ****************************************************************************//** + * + * Places a byte of data in the transmit buffer to be sent at the next available + * bus time. This function is blocking and waits until there is a space + * available to put requested data in the transmit buffer. + * For UART Multi Processor mode this function can send 9-bits data as well. + * Use UART_1_UART_MP_MARK to add a mark to create an address byte. + * + * \param txDataByte: the data to be transmitted. + * + *******************************************************************************/ + #define UART_1_UartPutChar(ch) UART_1_SpiUartWriteTxData((uint32)(ch)) + + void UART_1_UartPutString(const char8 string[]); + void UART_1_UartPutCRLF(uint32 txDataByte); + void UART_1_UartSendBreakBlocking(uint32 breakWidth); + + #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + /* UART APIs for Flow Control */ + void UART_1_UartEnableCts(void); + void UART_1_UartDisableCts(void); + void UART_1_UartSetCtsPolarity(uint32 polarity); + #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + #endif /* (UART_1_UART_TX_DIRECTION) */ +#endif /* (UART_1_SCB_MODE_UART_INC) */ +/** @} uart */ + +/** +* \addtogroup group_spi_uart +* @{ +*/ +#if(UART_1_RX_DIRECTION) + uint32 UART_1_SpiUartReadRxData(void); + uint32 UART_1_SpiUartGetRxBufferSize(void); + void UART_1_SpiUartClearRxBuffer(void); +#endif /* (UART_1_RX_DIRECTION) */ + +/* Common APIs TX direction */ +#if(UART_1_TX_DIRECTION) + void UART_1_SpiUartWriteTxData(uint32 txData); + void UART_1_SpiUartPutArray(const uint8 wrBuf[], uint32 count); + uint32 UART_1_SpiUartGetTxBufferSize(void); + void UART_1_SpiUartClearTxBuffer(void); +#endif /* (UART_1_TX_DIRECTION) */ +/** @} spi_uart */ + +CY_ISR_PROTO(UART_1_SPI_UART_ISR); + +#if(UART_1_UART_RX_WAKEUP_IRQ) + CY_ISR_PROTO(UART_1_UART_WAKEUP_ISR); +#endif /* (UART_1_UART_RX_WAKEUP_IRQ) */ + + +/*************************************** +* Buffer Access Macro Definitions +***************************************/ + +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + /* RX direction */ + void UART_1_PutWordInRxBuffer (uint32 idx, uint32 rxDataByte); + uint32 UART_1_GetWordFromRxBuffer(uint32 idx); + + /* TX direction */ + void UART_1_PutWordInTxBuffer (uint32 idx, uint32 txDataByte); + uint32 UART_1_GetWordFromTxBuffer(uint32 idx); + +#else + /* RX direction */ + #if(UART_1_INTERNAL_RX_SW_BUFFER_CONST) + #define UART_1_PutWordInRxBuffer(idx, rxDataByte) \ + do{ \ + UART_1_rxBufferInternal[(idx)] = ((uint8) (rxDataByte)); \ + }while(0) + + #define UART_1_GetWordFromRxBuffer(idx) UART_1_rxBufferInternal[(idx)] + + #endif /* (UART_1_INTERNAL_RX_SW_BUFFER_CONST) */ + + /* TX direction */ + #if(UART_1_INTERNAL_TX_SW_BUFFER_CONST) + #define UART_1_PutWordInTxBuffer(idx, txDataByte) \ + do{ \ + UART_1_txBufferInternal[(idx)] = ((uint8) (txDataByte)); \ + }while(0) + + #define UART_1_GetWordFromTxBuffer(idx) UART_1_txBufferInternal[(idx)] + + #endif /* (UART_1_INTERNAL_TX_SW_BUFFER_CONST) */ + +#endif /* (UART_1_TX_SW_BUFFER_ENABLE) */ + + +/*************************************** +* SPI API Constants +***************************************/ + +/* SPI sub mode enum */ +#define UART_1_SPI_MODE_MOTOROLA (0x00u) +#define UART_1_SPI_MODE_TI_COINCIDES (0x01u) +#define UART_1_SPI_MODE_TI_PRECEDES (0x11u) +#define UART_1_SPI_MODE_NATIONAL (0x02u) +#define UART_1_SPI_MODE_MASK (0x03u) +#define UART_1_SPI_MODE_TI_PRECEDES_MASK (0x10u) +#define UART_1_SPI_MODE_NS_MICROWIRE (UART_1_SPI_MODE_NATIONAL) + +/* SPI phase and polarity mode enum */ +#define UART_1_SPI_SCLK_CPHA0_CPOL0 (0x00u) +#define UART_1_SPI_SCLK_CPHA0_CPOL1 (0x02u) +#define UART_1_SPI_SCLK_CPHA1_CPOL0 (0x01u) +#define UART_1_SPI_SCLK_CPHA1_CPOL1 (0x03u) + +/* SPI bits order enum */ +#define UART_1_BITS_ORDER_LSB_FIRST (0u) +#define UART_1_BITS_ORDER_MSB_FIRST (1u) + +/* SPI transfer separation enum */ +#define UART_1_SPI_TRANSFER_SEPARATED (0u) +#define UART_1_SPI_TRANSFER_CONTINUOUS (1u) + +/* SPI slave select constants */ +#define UART_1_SPI_SLAVE_SELECT0 (UART_1_SCB__SS0_POSISTION) +#define UART_1_SPI_SLAVE_SELECT1 (UART_1_SCB__SS1_POSISTION) +#define UART_1_SPI_SLAVE_SELECT2 (UART_1_SCB__SS2_POSISTION) +#define UART_1_SPI_SLAVE_SELECT3 (UART_1_SCB__SS3_POSISTION) + +/* SPI slave select polarity settings */ +#define UART_1_SPI_SS_ACTIVE_LOW (0u) +#define UART_1_SPI_SS_ACTIVE_HIGH (1u) + +#define UART_1_INTR_SPIM_TX_RESTORE (UART_1_INTR_TX_OVERFLOW) + +#define UART_1_INTR_SPIS_TX_RESTORE (UART_1_INTR_TX_OVERFLOW | \ + UART_1_INTR_TX_UNDERFLOW) + +/*************************************** +* UART API Constants +***************************************/ + +/* UART sub-modes enum */ +#define UART_1_UART_MODE_STD (0u) +#define UART_1_UART_MODE_SMARTCARD (1u) +#define UART_1_UART_MODE_IRDA (2u) + +/* UART direction enum */ +#define UART_1_UART_RX (1u) +#define UART_1_UART_TX (2u) +#define UART_1_UART_TX_RX (3u) + +/* UART parity enum */ +#define UART_1_UART_PARITY_EVEN (0u) +#define UART_1_UART_PARITY_ODD (1u) +#define UART_1_UART_PARITY_NONE (2u) + +/* UART stop bits enum */ +#define UART_1_UART_STOP_BITS_1 (2u) +#define UART_1_UART_STOP_BITS_1_5 (3u) +#define UART_1_UART_STOP_BITS_2 (4u) + +/* UART IrDA low power OVS enum */ +#define UART_1_UART_IRDA_LP_OVS16 (16u) +#define UART_1_UART_IRDA_LP_OVS32 (32u) +#define UART_1_UART_IRDA_LP_OVS48 (48u) +#define UART_1_UART_IRDA_LP_OVS96 (96u) +#define UART_1_UART_IRDA_LP_OVS192 (192u) +#define UART_1_UART_IRDA_LP_OVS768 (768u) +#define UART_1_UART_IRDA_LP_OVS1536 (1536u) + +/* Uart MP: mark (address) and space (data) bit definitions */ +#define UART_1_UART_MP_MARK (0x100u) +#define UART_1_UART_MP_SPACE (0x000u) + +/* UART CTS/RTS polarity settings */ +#define UART_1_UART_CTS_ACTIVE_LOW (0u) +#define UART_1_UART_CTS_ACTIVE_HIGH (1u) +#define UART_1_UART_RTS_ACTIVE_LOW (0u) +#define UART_1_UART_RTS_ACTIVE_HIGH (1u) + +/* Sources of RX errors */ +#define UART_1_INTR_RX_ERR (UART_1_INTR_RX_OVERFLOW | \ + UART_1_INTR_RX_UNDERFLOW | \ + UART_1_INTR_RX_FRAME_ERROR | \ + UART_1_INTR_RX_PARITY_ERROR) + +/* Shifted INTR_RX_ERR defines ONLY for UART_1_UartGetByte() */ +#define UART_1_UART_RX_OVERFLOW (UART_1_INTR_RX_OVERFLOW << 8u) +#define UART_1_UART_RX_UNDERFLOW (UART_1_INTR_RX_UNDERFLOW << 8u) +#define UART_1_UART_RX_FRAME_ERROR (UART_1_INTR_RX_FRAME_ERROR << 8u) +#define UART_1_UART_RX_PARITY_ERROR (UART_1_INTR_RX_PARITY_ERROR << 8u) +#define UART_1_UART_RX_ERROR_MASK (UART_1_UART_RX_OVERFLOW | \ + UART_1_UART_RX_UNDERFLOW | \ + UART_1_UART_RX_FRAME_ERROR | \ + UART_1_UART_RX_PARITY_ERROR) + +#define UART_1_INTR_UART_TX_RESTORE (UART_1_INTR_TX_OVERFLOW | \ + UART_1_INTR_TX_UART_NACK | \ + UART_1_INTR_TX_UART_DONE | \ + UART_1_INTR_TX_UART_ARB_LOST) + + +/*************************************** +* Vars with External Linkage +***************************************/ + +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + extern const UART_1_SPI_INIT_STRUCT UART_1_configSpi; + extern const UART_1_UART_INIT_STRUCT UART_1_configUart; +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if (UART_1_UART_WAKE_ENABLE_CONST && UART_1_UART_RX_WAKEUP_IRQ) + extern uint8 UART_1_skipStart; +#endif /* (UART_1_UART_WAKE_ENABLE_CONST && UART_1_UART_RX_WAKEUP_IRQ) */ + + +/*************************************** +* Specific SPI Macro Definitions +***************************************/ + +#define UART_1_GET_SPI_INTR_SLAVE_MASK(sourceMask) ((sourceMask) & UART_1_INTR_SLAVE_SPI_BUS_ERROR) +#define UART_1_GET_SPI_INTR_MASTER_MASK(sourceMask) ((sourceMask) & UART_1_INTR_MASTER_SPI_DONE) +#define UART_1_GET_SPI_INTR_RX_MASK(sourceMask) \ + ((sourceMask) & (uint32) ~UART_1_INTR_SLAVE_SPI_BUS_ERROR) + +#define UART_1_GET_SPI_INTR_TX_MASK(sourceMask) \ + ((sourceMask) & (uint32) ~UART_1_INTR_MASTER_SPI_DONE) + + +/*************************************** +* Specific UART Macro Definitions +***************************************/ + +#define UART_1_UART_GET_CTRL_OVS_IRDA_LP(oversample) \ + ((UART_1_UART_IRDA_LP_OVS16 == (oversample)) ? UART_1_CTRL_OVS_IRDA_LP_OVS16 : \ + ((UART_1_UART_IRDA_LP_OVS32 == (oversample)) ? UART_1_CTRL_OVS_IRDA_LP_OVS32 : \ + ((UART_1_UART_IRDA_LP_OVS48 == (oversample)) ? UART_1_CTRL_OVS_IRDA_LP_OVS48 : \ + ((UART_1_UART_IRDA_LP_OVS96 == (oversample)) ? UART_1_CTRL_OVS_IRDA_LP_OVS96 : \ + ((UART_1_UART_IRDA_LP_OVS192 == (oversample)) ? UART_1_CTRL_OVS_IRDA_LP_OVS192 : \ + ((UART_1_UART_IRDA_LP_OVS768 == (oversample)) ? UART_1_CTRL_OVS_IRDA_LP_OVS768 : \ + ((UART_1_UART_IRDA_LP_OVS1536 == (oversample)) ? UART_1_CTRL_OVS_IRDA_LP_OVS1536 : \ + UART_1_CTRL_OVS_IRDA_LP_OVS16))))))) + +#define UART_1_GET_UART_RX_CTRL_ENABLED(direction) ((0u != (UART_1_UART_RX & (direction))) ? \ + (UART_1_RX_CTRL_ENABLED) : (0u)) + +#define UART_1_GET_UART_TX_CTRL_ENABLED(direction) ((0u != (UART_1_UART_TX & (direction))) ? \ + (UART_1_TX_CTRL_ENABLED) : (0u)) + + +/*************************************** +* SPI Register Settings +***************************************/ + +#define UART_1_CTRL_SPI (UART_1_CTRL_MODE_SPI) +#define UART_1_SPI_RX_CTRL (UART_1_RX_CTRL_ENABLED) +#define UART_1_SPI_TX_CTRL (UART_1_TX_CTRL_ENABLED) + + +/*************************************** +* SPI Init Register Settings +***************************************/ + +#define UART_1_SPI_SS_POLARITY \ + (((uint32) UART_1_SPI_SS0_POLARITY << UART_1_SPI_SLAVE_SELECT0) | \ + ((uint32) UART_1_SPI_SS1_POLARITY << UART_1_SPI_SLAVE_SELECT1) | \ + ((uint32) UART_1_SPI_SS2_POLARITY << UART_1_SPI_SLAVE_SELECT2) | \ + ((uint32) UART_1_SPI_SS3_POLARITY << UART_1_SPI_SLAVE_SELECT3)) + +#if(UART_1_SCB_MODE_SPI_CONST_CFG) + + /* SPI Configuration */ + #define UART_1_SPI_DEFAULT_CTRL \ + (UART_1_GET_CTRL_OVS(UART_1_SPI_OVS_FACTOR) | \ + UART_1_GET_CTRL_BYTE_MODE (UART_1_SPI_BYTE_MODE_ENABLE) | \ + UART_1_GET_CTRL_EC_AM_MODE(UART_1_SPI_WAKE_ENABLE) | \ + UART_1_CTRL_SPI) + + #define UART_1_SPI_DEFAULT_SPI_CTRL \ + (UART_1_GET_SPI_CTRL_CONTINUOUS (UART_1_SPI_TRANSFER_SEPARATION) | \ + UART_1_GET_SPI_CTRL_SELECT_PRECEDE(UART_1_SPI_SUB_MODE & \ + UART_1_SPI_MODE_TI_PRECEDES_MASK) | \ + UART_1_GET_SPI_CTRL_SCLK_MODE (UART_1_SPI_CLOCK_MODE) | \ + UART_1_GET_SPI_CTRL_LATE_MISO_SAMPLE(UART_1_SPI_LATE_MISO_SAMPLE_ENABLE) | \ + UART_1_GET_SPI_CTRL_SCLK_CONTINUOUS(UART_1_SPI_FREE_RUN_SCLK_ENABLE) | \ + UART_1_GET_SPI_CTRL_SSEL_POLARITY (UART_1_SPI_SS_POLARITY) | \ + UART_1_GET_SPI_CTRL_SUB_MODE (UART_1_SPI_SUB_MODE) | \ + UART_1_GET_SPI_CTRL_MASTER_MODE (UART_1_SPI_MODE)) + + /* RX direction */ + #define UART_1_SPI_DEFAULT_RX_CTRL \ + (UART_1_GET_RX_CTRL_DATA_WIDTH(UART_1_SPI_RX_DATA_BITS_NUM) | \ + UART_1_GET_RX_CTRL_BIT_ORDER (UART_1_SPI_BITS_ORDER) | \ + UART_1_GET_RX_CTRL_MEDIAN (UART_1_SPI_MEDIAN_FILTER_ENABLE) | \ + UART_1_SPI_RX_CTRL) + + #define UART_1_SPI_DEFAULT_RX_FIFO_CTRL \ + UART_1_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(UART_1_SPI_RX_TRIGGER_LEVEL) + + /* TX direction */ + #define UART_1_SPI_DEFAULT_TX_CTRL \ + (UART_1_GET_TX_CTRL_DATA_WIDTH(UART_1_SPI_TX_DATA_BITS_NUM) | \ + UART_1_GET_TX_CTRL_BIT_ORDER (UART_1_SPI_BITS_ORDER) | \ + UART_1_SPI_TX_CTRL) + + #define UART_1_SPI_DEFAULT_TX_FIFO_CTRL \ + UART_1_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(UART_1_SPI_TX_TRIGGER_LEVEL) + + /* Interrupt sources */ + #define UART_1_SPI_DEFAULT_INTR_SPI_EC_MASK (UART_1_NO_INTR_SOURCES) + + #define UART_1_SPI_DEFAULT_INTR_I2C_EC_MASK (UART_1_NO_INTR_SOURCES) + #define UART_1_SPI_DEFAULT_INTR_SLAVE_MASK \ + (UART_1_SPI_INTR_RX_MASK & UART_1_INTR_SLAVE_SPI_BUS_ERROR) + + #define UART_1_SPI_DEFAULT_INTR_MASTER_MASK \ + (UART_1_SPI_INTR_TX_MASK & UART_1_INTR_MASTER_SPI_DONE) + + #define UART_1_SPI_DEFAULT_INTR_RX_MASK \ + (UART_1_SPI_INTR_RX_MASK & (uint32) ~UART_1_INTR_SLAVE_SPI_BUS_ERROR) + + #define UART_1_SPI_DEFAULT_INTR_TX_MASK \ + (UART_1_SPI_INTR_TX_MASK & (uint32) ~UART_1_INTR_MASTER_SPI_DONE) + +#endif /* (UART_1_SCB_MODE_SPI_CONST_CFG) */ + + +/*************************************** +* UART Register Settings +***************************************/ + +#define UART_1_CTRL_UART (UART_1_CTRL_MODE_UART) +#define UART_1_UART_RX_CTRL (UART_1_RX_CTRL_LSB_FIRST) /* LSB for UART goes first */ +#define UART_1_UART_TX_CTRL (UART_1_TX_CTRL_LSB_FIRST) /* LSB for UART goes first */ + + +/*************************************** +* UART Init Register Settings +***************************************/ + +#if(UART_1_SCB_MODE_UART_CONST_CFG) + + /* UART configuration */ + #if(UART_1_UART_MODE_IRDA == UART_1_UART_SUB_MODE) + + #define UART_1_DEFAULT_CTRL_OVS ((0u != UART_1_UART_IRDA_LOW_POWER) ? \ + (UART_1_UART_GET_CTRL_OVS_IRDA_LP(UART_1_UART_OVS_FACTOR)) : \ + (UART_1_CTRL_OVS_IRDA_OVS16)) + + #else + + #define UART_1_DEFAULT_CTRL_OVS UART_1_GET_CTRL_OVS(UART_1_UART_OVS_FACTOR) + + #endif /* (UART_1_UART_MODE_IRDA == UART_1_UART_SUB_MODE) */ + + #define UART_1_UART_DEFAULT_CTRL \ + (UART_1_GET_CTRL_BYTE_MODE (UART_1_UART_BYTE_MODE_ENABLE) | \ + UART_1_GET_CTRL_ADDR_ACCEPT(UART_1_UART_MP_ACCEPT_ADDRESS) | \ + UART_1_DEFAULT_CTRL_OVS | \ + UART_1_CTRL_UART) + + #define UART_1_UART_DEFAULT_UART_CTRL \ + (UART_1_GET_UART_CTRL_MODE(UART_1_UART_SUB_MODE)) + + /* RX direction */ + #define UART_1_UART_DEFAULT_RX_CTRL_PARITY \ + ((UART_1_UART_PARITY_NONE != UART_1_UART_PARITY_TYPE) ? \ + (UART_1_GET_UART_RX_CTRL_PARITY(UART_1_UART_PARITY_TYPE) | \ + UART_1_UART_RX_CTRL_PARITY_ENABLED) : (0u)) + + #define UART_1_UART_DEFAULT_UART_RX_CTRL \ + (UART_1_GET_UART_RX_CTRL_MODE(UART_1_UART_STOP_BITS_NUM) | \ + UART_1_GET_UART_RX_CTRL_POLARITY(UART_1_UART_IRDA_POLARITY) | \ + UART_1_GET_UART_RX_CTRL_MP_MODE(UART_1_UART_MP_MODE_ENABLE) | \ + UART_1_GET_UART_RX_CTRL_DROP_ON_PARITY_ERR(UART_1_UART_DROP_ON_PARITY_ERR) | \ + UART_1_GET_UART_RX_CTRL_DROP_ON_FRAME_ERR(UART_1_UART_DROP_ON_FRAME_ERR) | \ + UART_1_GET_UART_RX_CTRL_BREAK_WIDTH(UART_1_UART_RX_BREAK_WIDTH) | \ + UART_1_UART_DEFAULT_RX_CTRL_PARITY) + + + #define UART_1_UART_DEFAULT_RX_CTRL \ + (UART_1_GET_RX_CTRL_DATA_WIDTH(UART_1_UART_DATA_BITS_NUM) | \ + UART_1_GET_RX_CTRL_MEDIAN (UART_1_UART_MEDIAN_FILTER_ENABLE) | \ + UART_1_GET_UART_RX_CTRL_ENABLED(UART_1_UART_DIRECTION)) + + #define UART_1_UART_DEFAULT_RX_FIFO_CTRL \ + UART_1_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(UART_1_UART_RX_TRIGGER_LEVEL) + + #define UART_1_UART_DEFAULT_RX_MATCH_REG ((0u != UART_1_UART_MP_MODE_ENABLE) ? \ + (UART_1_GET_RX_MATCH_ADDR(UART_1_UART_MP_RX_ADDRESS) | \ + UART_1_GET_RX_MATCH_MASK(UART_1_UART_MP_RX_ADDRESS_MASK)) : (0u)) + + /* TX direction */ + #define UART_1_UART_DEFAULT_TX_CTRL_PARITY (UART_1_UART_DEFAULT_RX_CTRL_PARITY) + + #define UART_1_UART_DEFAULT_UART_TX_CTRL \ + (UART_1_GET_UART_TX_CTRL_MODE(UART_1_UART_STOP_BITS_NUM) | \ + UART_1_GET_UART_TX_CTRL_RETRY_NACK(UART_1_UART_RETRY_ON_NACK) | \ + UART_1_UART_DEFAULT_TX_CTRL_PARITY) + + #define UART_1_UART_DEFAULT_TX_CTRL \ + (UART_1_GET_TX_CTRL_DATA_WIDTH(UART_1_UART_DATA_BITS_NUM) | \ + UART_1_GET_UART_TX_CTRL_ENABLED(UART_1_UART_DIRECTION)) + + #define UART_1_UART_DEFAULT_TX_FIFO_CTRL \ + UART_1_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(UART_1_UART_TX_TRIGGER_LEVEL) + + #define UART_1_UART_DEFAULT_FLOW_CTRL \ + (UART_1_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(UART_1_UART_RTS_FIFO_LEVEL) | \ + UART_1_GET_UART_FLOW_CTRL_RTS_POLARITY (UART_1_UART_RTS_POLARITY) | \ + UART_1_GET_UART_FLOW_CTRL_CTS_POLARITY (UART_1_UART_CTS_POLARITY) | \ + UART_1_GET_UART_FLOW_CTRL_CTS_ENABLE (UART_1_UART_CTS_ENABLE)) + + /* Interrupt sources */ + #define UART_1_UART_DEFAULT_INTR_I2C_EC_MASK (UART_1_NO_INTR_SOURCES) + #define UART_1_UART_DEFAULT_INTR_SPI_EC_MASK (UART_1_NO_INTR_SOURCES) + #define UART_1_UART_DEFAULT_INTR_SLAVE_MASK (UART_1_NO_INTR_SOURCES) + #define UART_1_UART_DEFAULT_INTR_MASTER_MASK (UART_1_NO_INTR_SOURCES) + #define UART_1_UART_DEFAULT_INTR_RX_MASK (UART_1_UART_INTR_RX_MASK) + #define UART_1_UART_DEFAULT_INTR_TX_MASK (UART_1_UART_INTR_TX_MASK) + +#endif /* (UART_1_SCB_MODE_UART_CONST_CFG) */ + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +#define UART_1_SPIM_ACTIVE_SS0 (UART_1_SPI_SLAVE_SELECT0) +#define UART_1_SPIM_ACTIVE_SS1 (UART_1_SPI_SLAVE_SELECT1) +#define UART_1_SPIM_ACTIVE_SS2 (UART_1_SPI_SLAVE_SELECT2) +#define UART_1_SPIM_ACTIVE_SS3 (UART_1_SPI_SLAVE_SELECT3) + +#endif /* CY_SCB_SPI_UART_UART_1_H */ + + +#ifdef __cplusplus +} +#endif + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_SPI_UART_INT.c b/cores/asr650x/projects/PSoC4/UART_1_SPI_UART_INT.c new file mode 100644 index 00000000..9926391a --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_SPI_UART_INT.c @@ -0,0 +1,158 @@ +/***************************************************************************//** +* \file UART_1_SPI_UART_INT.c +* \version 4.0 +* +* \brief +* This file provides the source code to the Interrupt Service Routine for +* the SCB Component in SPI and UART modes. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_1_PVT.h" +#include "UART_1_SPI_UART_PVT.h" +#include "cyapicallbacks.h" + +#if (UART_1_SCB_IRQ_INTERNAL) +/******************************************************************************* +* Function Name: UART_1_SPI_UART_ISR +****************************************************************************//** +* +* Handles the Interrupt Service Routine for the SCB SPI or UART modes. +* +*******************************************************************************/ +CY_ISR(UART_1_SPI_UART_ISR) +{ +#if (UART_1_INTERNAL_RX_SW_BUFFER_CONST) + uint32 locHead; +#endif /* (UART_1_INTERNAL_RX_SW_BUFFER_CONST) */ + +#if (UART_1_INTERNAL_TX_SW_BUFFER_CONST) + uint32 locTail; +#endif /* (UART_1_INTERNAL_TX_SW_BUFFER_CONST) */ + +#ifdef UART_1_SPI_UART_ISR_ENTRY_CALLBACK + UART_1_SPI_UART_ISR_EntryCallback(); +#endif /* UART_1_SPI_UART_ISR_ENTRY_CALLBACK */ + + if (NULL != UART_1_customIntrHandler) + { + UART_1_customIntrHandler(); + } + + #if(UART_1_CHECK_SPI_WAKE_ENABLE) + { + /* Clear SPI wakeup source */ + UART_1_ClearSpiExtClkInterruptSource(UART_1_INTR_SPI_EC_WAKE_UP); + } + #endif + + #if (UART_1_CHECK_RX_SW_BUFFER) + { + if (UART_1_CHECK_INTR_RX_MASKED(UART_1_INTR_RX_NOT_EMPTY)) + { + do + { + /* Move local head index */ + locHead = (UART_1_rxBufferHead + 1u); + + /* Adjust local head index */ + if (UART_1_INTERNAL_RX_BUFFER_SIZE == locHead) + { + locHead = 0u; + } + + if (locHead == UART_1_rxBufferTail) + { + #if (UART_1_CHECK_UART_RTS_CONTROL_FLOW) + { + /* There is no space in the software buffer - disable the + * RX Not Empty interrupt source. The data elements are + * still being received into the RX FIFO until the RTS signal + * stops the transmitter. After the data element is read from the + * buffer, the RX Not Empty interrupt source is enabled to + * move the next data element in the software buffer. + */ + UART_1_INTR_RX_MASK_REG &= ~UART_1_INTR_RX_NOT_EMPTY; + break; + } + #else + { + /* Overflow: through away received data element */ + (void) UART_1_RX_FIFO_RD_REG; + UART_1_rxBufferOverflow = (uint8) UART_1_INTR_RX_OVERFLOW; + } + #endif + } + else + { + /* Store received data */ + UART_1_PutWordInRxBuffer(locHead, UART_1_RX_FIFO_RD_REG); + + /* Move head index */ + UART_1_rxBufferHead = locHead; + } + } + while(0u != UART_1_GET_RX_FIFO_ENTRIES); + + UART_1_ClearRxInterruptSource(UART_1_INTR_RX_NOT_EMPTY); + } + } + #endif + + + #if (UART_1_CHECK_TX_SW_BUFFER) + { + if (UART_1_CHECK_INTR_TX_MASKED(UART_1_INTR_TX_NOT_FULL)) + { + do + { + /* Check for room in TX software buffer */ + if (UART_1_txBufferHead != UART_1_txBufferTail) + { + /* Move local tail index */ + locTail = (UART_1_txBufferTail + 1u); + + /* Adjust local tail index */ + if (UART_1_TX_BUFFER_SIZE == locTail) + { + locTail = 0u; + } + + /* Put data into TX FIFO */ + UART_1_TX_FIFO_WR_REG = UART_1_GetWordFromTxBuffer(locTail); + + /* Move tail index */ + UART_1_txBufferTail = locTail; + } + else + { + /* TX software buffer is empty: complete transfer */ + UART_1_DISABLE_INTR_TX(UART_1_INTR_TX_NOT_FULL); + break; + } + } + while (UART_1_SPI_UART_FIFO_SIZE != UART_1_GET_TX_FIFO_ENTRIES); + + UART_1_ClearTxInterruptSource(UART_1_INTR_TX_NOT_FULL); + } + } + #endif + +#ifdef UART_1_SPI_UART_ISR_EXIT_CALLBACK + UART_1_SPI_UART_ISR_ExitCallback(); +#endif /* UART_1_SPI_UART_ISR_EXIT_CALLBACK */ + +} + +#endif /* (UART_1_SCB_IRQ_INTERNAL) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_SPI_UART_PVT.h b/cores/asr650x/projects/PSoC4/UART_1_SPI_UART_PVT.h new file mode 100644 index 00000000..eda6b2b1 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_SPI_UART_PVT.h @@ -0,0 +1,117 @@ +/***************************************************************************//** +* \file UART_1_SPI_UART_PVT.h +* \version 4.0 +* +* \brief +* This private file provides constants and parameter values for the +* SCB Component in SPI and UART modes. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SCB_SPI_UART_PVT_UART_1_H) +#define CY_SCB_SPI_UART_PVT_UART_1_H + +#include "UART_1_SPI_UART.h" + + +/*************************************** +* Internal Global Vars +***************************************/ + +#if (UART_1_INTERNAL_RX_SW_BUFFER_CONST) + extern volatile uint32 UART_1_rxBufferHead; + extern volatile uint32 UART_1_rxBufferTail; + + /** + * \addtogroup group_globals + * @{ + */ + + /** Sets when internal software receive buffer overflow + * was occurred. + */ + extern volatile uint8 UART_1_rxBufferOverflow; + /** @} globals */ +#endif /* (UART_1_INTERNAL_RX_SW_BUFFER_CONST) */ + +#if (UART_1_INTERNAL_TX_SW_BUFFER_CONST) + extern volatile uint32 UART_1_txBufferHead; + extern volatile uint32 UART_1_txBufferTail; +#endif /* (UART_1_INTERNAL_TX_SW_BUFFER_CONST) */ + +#if (UART_1_INTERNAL_RX_SW_BUFFER) + extern volatile uint8 UART_1_rxBufferInternal[UART_1_INTERNAL_RX_BUFFER_SIZE]; +#endif /* (UART_1_INTERNAL_RX_SW_BUFFER) */ + +#if (UART_1_INTERNAL_TX_SW_BUFFER) + extern volatile uint8 UART_1_txBufferInternal[UART_1_TX_BUFFER_SIZE]; +#endif /* (UART_1_INTERNAL_TX_SW_BUFFER) */ + + +/*************************************** +* Private Function Prototypes +***************************************/ + +void UART_1_SpiPostEnable(void); +void UART_1_SpiStop(void); + +#if (UART_1_SCB_MODE_SPI_CONST_CFG) + void UART_1_SpiInit(void); +#endif /* (UART_1_SCB_MODE_SPI_CONST_CFG) */ + +#if (UART_1_SPI_WAKE_ENABLE_CONST) + void UART_1_SpiSaveConfig(void); + void UART_1_SpiRestoreConfig(void); +#endif /* (UART_1_SPI_WAKE_ENABLE_CONST) */ + +void UART_1_UartPostEnable(void); +void UART_1_UartStop(void); + +#if (UART_1_SCB_MODE_UART_CONST_CFG) + void UART_1_UartInit(void); +#endif /* (UART_1_SCB_MODE_UART_CONST_CFG) */ + +#if (UART_1_UART_WAKE_ENABLE_CONST) + void UART_1_UartSaveConfig(void); + void UART_1_UartRestoreConfig(void); +#endif /* (UART_1_UART_WAKE_ENABLE_CONST) */ + + +/*************************************** +* UART API Constants +***************************************/ + +/* UART RX and TX position to be used in UART_1_SetPins() */ +#define UART_1_UART_RX_PIN_ENABLE (UART_1_UART_RX) +#define UART_1_UART_TX_PIN_ENABLE (UART_1_UART_TX) + +/* UART RTS and CTS position to be used in UART_1_SetPins() */ +#define UART_1_UART_RTS_PIN_ENABLE (0x10u) +#define UART_1_UART_CTS_PIN_ENABLE (0x20u) + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +/* Interrupt processing */ +#define UART_1_SpiUartEnableIntRx(intSourceMask) UART_1_SetRxInterruptMode(intSourceMask) +#define UART_1_SpiUartEnableIntTx(intSourceMask) UART_1_SetTxInterruptMode(intSourceMask) +uint32 UART_1_SpiUartDisableIntRx(void); +uint32 UART_1_SpiUartDisableIntTx(void); + + +#endif /* (CY_SCB_SPI_UART_PVT_UART_1_H) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_UART.c b/cores/asr650x/projects/PSoC4/UART_1_UART.c new file mode 100644 index 00000000..d5fe03a7 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_UART.c @@ -0,0 +1,905 @@ +/***************************************************************************//** +* \file UART_1_UART.c +* \version 4.0 +* +* \brief +* This file provides the source code to the API for the SCB Component in +* UART mode. +* +* Note: +* +******************************************************************************* +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_1_PVT.h" +#include "UART_1_SPI_UART_PVT.h" +#include "cyapicallbacks.h" + +#if (UART_1_UART_WAKE_ENABLE_CONST && UART_1_UART_RX_WAKEUP_IRQ) + /** + * \addtogroup group_globals + * \{ + */ + /** This global variable determines whether to enable Skip Start + * functionality when UART_1_Sleep() function is called: + * 0 鈥 disable, other values 鈥 enable. Default value is 1. + * It is only available when Enable wakeup from Deep Sleep Mode is enabled. + */ + uint8 UART_1_skipStart = 1u; + /** \} globals */ +#endif /* (UART_1_UART_WAKE_ENABLE_CONST && UART_1_UART_RX_WAKEUP_IRQ) */ + +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + + /*************************************** + * Configuration Structure Initialization + ***************************************/ + + const UART_1_UART_INIT_STRUCT UART_1_configUart = + { + UART_1_UART_SUB_MODE, + UART_1_UART_DIRECTION, + UART_1_UART_DATA_BITS_NUM, + UART_1_UART_PARITY_TYPE, + UART_1_UART_STOP_BITS_NUM, + UART_1_UART_OVS_FACTOR, + UART_1_UART_IRDA_LOW_POWER, + UART_1_UART_MEDIAN_FILTER_ENABLE, + UART_1_UART_RETRY_ON_NACK, + UART_1_UART_IRDA_POLARITY, + UART_1_UART_DROP_ON_PARITY_ERR, + UART_1_UART_DROP_ON_FRAME_ERR, + UART_1_UART_WAKE_ENABLE, + 0u, + NULL, + 0u, + NULL, + UART_1_UART_MP_MODE_ENABLE, + UART_1_UART_MP_ACCEPT_ADDRESS, + UART_1_UART_MP_RX_ADDRESS, + UART_1_UART_MP_RX_ADDRESS_MASK, + (uint32) UART_1_SCB_IRQ_INTERNAL, + UART_1_UART_INTR_RX_MASK, + UART_1_UART_RX_TRIGGER_LEVEL, + UART_1_UART_INTR_TX_MASK, + UART_1_UART_TX_TRIGGER_LEVEL, + (uint8) UART_1_UART_BYTE_MODE_ENABLE, + (uint8) UART_1_UART_CTS_ENABLE, + (uint8) UART_1_UART_CTS_POLARITY, + (uint8) UART_1_UART_RTS_POLARITY, + (uint8) UART_1_UART_RTS_FIFO_LEVEL, + (uint8) UART_1_UART_RX_BREAK_WIDTH + }; + + + /******************************************************************************* + * Function Name: UART_1_UartInit + ****************************************************************************//** + * + * Configures the UART_1 for UART operation. + * + * This function is intended specifically to be used when the UART_1 + * configuration is set to 鈥淯nconfigured UART_1鈥 in the customizer. + * After initializing the UART_1 in UART mode using this function, + * the component can be enabled using the UART_1_Start() or + * UART_1_Enable() function. + * This function uses a pointer to a structure that provides the configuration + * settings. This structure contains the same information that would otherwise + * be provided by the customizer settings. + * + * \param config: pointer to a structure that contains the following list of + * fields. These fields match the selections available in the customizer. + * Refer to the customizer for further description of the settings. + * + *******************************************************************************/ + void UART_1_UartInit(const UART_1_UART_INIT_STRUCT *config) + { + uint32 pinsConfig; + + if (NULL == config) + { + CYASSERT(0u != 0u); /* Halt execution due to bad function parameter */ + } + else + { + /* Get direction to configure UART pins: TX, RX or TX+RX */ + pinsConfig = config->direction; + + #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + /* Add RTS and CTS pins to configure */ + pinsConfig |= (0u != config->rtsRxFifoLevel) ? (UART_1_UART_RTS_PIN_ENABLE) : (0u); + pinsConfig |= (0u != config->enableCts) ? (UART_1_UART_CTS_PIN_ENABLE) : (0u); + #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + + /* Configure pins */ + UART_1_SetPins(UART_1_SCB_MODE_UART, config->mode, pinsConfig); + + /* Store internal configuration */ + UART_1_scbMode = (uint8) UART_1_SCB_MODE_UART; + UART_1_scbEnableWake = (uint8) config->enableWake; + UART_1_scbEnableIntr = (uint8) config->enableInterrupt; + + /* Set RX direction internal variables */ + UART_1_rxBuffer = config->rxBuffer; + UART_1_rxDataBits = (uint8) config->dataBits; + UART_1_rxBufferSize = config->rxBufferSize; + + /* Set TX direction internal variables */ + UART_1_txBuffer = config->txBuffer; + UART_1_txDataBits = (uint8) config->dataBits; + UART_1_txBufferSize = config->txBufferSize; + + /* Configure UART interface */ + if(UART_1_UART_MODE_IRDA == config->mode) + { + /* OVS settings: IrDA */ + UART_1_CTRL_REG = ((0u != config->enableIrdaLowPower) ? + (UART_1_UART_GET_CTRL_OVS_IRDA_LP(config->oversample)) : + (UART_1_CTRL_OVS_IRDA_OVS16)); + } + else + { + /* OVS settings: UART and SmartCard */ + UART_1_CTRL_REG = UART_1_GET_CTRL_OVS(config->oversample); + } + + UART_1_CTRL_REG |= UART_1_GET_CTRL_BYTE_MODE (config->enableByteMode) | + UART_1_GET_CTRL_ADDR_ACCEPT(config->multiprocAcceptAddr) | + UART_1_CTRL_UART; + + /* Configure sub-mode: UART, SmartCard or IrDA */ + UART_1_UART_CTRL_REG = UART_1_GET_UART_CTRL_MODE(config->mode); + + /* Configure RX direction */ + UART_1_UART_RX_CTRL_REG = UART_1_GET_UART_RX_CTRL_MODE(config->stopBits) | + UART_1_GET_UART_RX_CTRL_POLARITY(config->enableInvertedRx) | + UART_1_GET_UART_RX_CTRL_MP_MODE(config->enableMultiproc) | + UART_1_GET_UART_RX_CTRL_DROP_ON_PARITY_ERR(config->dropOnParityErr) | + UART_1_GET_UART_RX_CTRL_DROP_ON_FRAME_ERR(config->dropOnFrameErr) | + UART_1_GET_UART_RX_CTRL_BREAK_WIDTH(config->breakWidth); + + if(UART_1_UART_PARITY_NONE != config->parity) + { + UART_1_UART_RX_CTRL_REG |= UART_1_GET_UART_RX_CTRL_PARITY(config->parity) | + UART_1_UART_RX_CTRL_PARITY_ENABLED; + } + + UART_1_RX_CTRL_REG = UART_1_GET_RX_CTRL_DATA_WIDTH(config->dataBits) | + UART_1_GET_RX_CTRL_MEDIAN(config->enableMedianFilter) | + UART_1_GET_UART_RX_CTRL_ENABLED(config->direction); + + UART_1_RX_FIFO_CTRL_REG = UART_1_GET_RX_FIFO_CTRL_TRIGGER_LEVEL(config->rxTriggerLevel); + + /* Configure MP address */ + UART_1_RX_MATCH_REG = UART_1_GET_RX_MATCH_ADDR(config->multiprocAddr) | + UART_1_GET_RX_MATCH_MASK(config->multiprocAddrMask); + + /* Configure RX direction */ + UART_1_UART_TX_CTRL_REG = UART_1_GET_UART_TX_CTRL_MODE(config->stopBits) | + UART_1_GET_UART_TX_CTRL_RETRY_NACK(config->enableRetryNack); + + if(UART_1_UART_PARITY_NONE != config->parity) + { + UART_1_UART_TX_CTRL_REG |= UART_1_GET_UART_TX_CTRL_PARITY(config->parity) | + UART_1_UART_TX_CTRL_PARITY_ENABLED; + } + + UART_1_TX_CTRL_REG = UART_1_GET_TX_CTRL_DATA_WIDTH(config->dataBits) | + UART_1_GET_UART_TX_CTRL_ENABLED(config->direction); + + UART_1_TX_FIFO_CTRL_REG = UART_1_GET_TX_FIFO_CTRL_TRIGGER_LEVEL(config->txTriggerLevel); + + #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + UART_1_UART_FLOW_CTRL_REG = UART_1_GET_UART_FLOW_CTRL_CTS_ENABLE(config->enableCts) | \ + UART_1_GET_UART_FLOW_CTRL_CTS_POLARITY (config->ctsPolarity) | \ + UART_1_GET_UART_FLOW_CTRL_RTS_POLARITY (config->rtsPolarity) | \ + UART_1_GET_UART_FLOW_CTRL_TRIGGER_LEVEL(config->rtsRxFifoLevel); + #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + + /* Configure interrupt with UART handler but do not enable it */ + CyIntDisable (UART_1_ISR_NUMBER); + CyIntSetPriority(UART_1_ISR_NUMBER, UART_1_ISR_PRIORITY); + (void) CyIntSetVector(UART_1_ISR_NUMBER, &UART_1_SPI_UART_ISR); + + /* Configure WAKE interrupt */ + #if(UART_1_UART_RX_WAKEUP_IRQ) + CyIntDisable (UART_1_RX_WAKE_ISR_NUMBER); + CyIntSetPriority(UART_1_RX_WAKE_ISR_NUMBER, UART_1_RX_WAKE_ISR_PRIORITY); + (void) CyIntSetVector(UART_1_RX_WAKE_ISR_NUMBER, &UART_1_UART_WAKEUP_ISR); + #endif /* (UART_1_UART_RX_WAKEUP_IRQ) */ + + /* Configure interrupt sources */ + UART_1_INTR_I2C_EC_MASK_REG = UART_1_NO_INTR_SOURCES; + UART_1_INTR_SPI_EC_MASK_REG = UART_1_NO_INTR_SOURCES; + UART_1_INTR_SLAVE_MASK_REG = UART_1_NO_INTR_SOURCES; + UART_1_INTR_MASTER_MASK_REG = UART_1_NO_INTR_SOURCES; + UART_1_INTR_RX_MASK_REG = config->rxInterruptMask; + UART_1_INTR_TX_MASK_REG = config->txInterruptMask; + + /* Configure TX interrupt sources to restore. */ + UART_1_IntrTxMask = LO16(UART_1_INTR_TX_MASK_REG); + + /* Clear RX buffer indexes */ + UART_1_rxBufferHead = 0u; + UART_1_rxBufferTail = 0u; + UART_1_rxBufferOverflow = 0u; + + /* Clear TX buffer indexes */ + UART_1_txBufferHead = 0u; + UART_1_txBufferTail = 0u; + } + } + +#else + + /******************************************************************************* + * Function Name: UART_1_UartInit + ****************************************************************************//** + * + * Configures the SCB for the UART operation. + * + *******************************************************************************/ + void UART_1_UartInit(void) + { + /* Configure UART interface */ + UART_1_CTRL_REG = UART_1_UART_DEFAULT_CTRL; + + /* Configure sub-mode: UART, SmartCard or IrDA */ + UART_1_UART_CTRL_REG = UART_1_UART_DEFAULT_UART_CTRL; + + /* Configure RX direction */ + UART_1_UART_RX_CTRL_REG = UART_1_UART_DEFAULT_UART_RX_CTRL; + UART_1_RX_CTRL_REG = UART_1_UART_DEFAULT_RX_CTRL; + UART_1_RX_FIFO_CTRL_REG = UART_1_UART_DEFAULT_RX_FIFO_CTRL; + UART_1_RX_MATCH_REG = UART_1_UART_DEFAULT_RX_MATCH_REG; + + /* Configure TX direction */ + UART_1_UART_TX_CTRL_REG = UART_1_UART_DEFAULT_UART_TX_CTRL; + UART_1_TX_CTRL_REG = UART_1_UART_DEFAULT_TX_CTRL; + UART_1_TX_FIFO_CTRL_REG = UART_1_UART_DEFAULT_TX_FIFO_CTRL; + + #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + UART_1_UART_FLOW_CTRL_REG = UART_1_UART_DEFAULT_FLOW_CTRL; + #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + + /* Configure interrupt with UART handler but do not enable it */ + #if(UART_1_SCB_IRQ_INTERNAL) + CyIntDisable (UART_1_ISR_NUMBER); + CyIntSetPriority(UART_1_ISR_NUMBER, UART_1_ISR_PRIORITY); + (void) CyIntSetVector(UART_1_ISR_NUMBER, &UART_1_SPI_UART_ISR); + #endif /* (UART_1_SCB_IRQ_INTERNAL) */ + + /* Configure WAKE interrupt */ + #if(UART_1_UART_RX_WAKEUP_IRQ) + CyIntDisable (UART_1_RX_WAKE_ISR_NUMBER); + CyIntSetPriority(UART_1_RX_WAKE_ISR_NUMBER, UART_1_RX_WAKE_ISR_PRIORITY); + (void) CyIntSetVector(UART_1_RX_WAKE_ISR_NUMBER, &UART_1_UART_WAKEUP_ISR); + #endif /* (UART_1_UART_RX_WAKEUP_IRQ) */ + + /* Configure interrupt sources */ + UART_1_INTR_I2C_EC_MASK_REG = UART_1_UART_DEFAULT_INTR_I2C_EC_MASK; + UART_1_INTR_SPI_EC_MASK_REG = UART_1_UART_DEFAULT_INTR_SPI_EC_MASK; + UART_1_INTR_SLAVE_MASK_REG = UART_1_UART_DEFAULT_INTR_SLAVE_MASK; + UART_1_INTR_MASTER_MASK_REG = UART_1_UART_DEFAULT_INTR_MASTER_MASK; + UART_1_INTR_RX_MASK_REG = UART_1_UART_DEFAULT_INTR_RX_MASK; + UART_1_INTR_TX_MASK_REG = UART_1_UART_DEFAULT_INTR_TX_MASK; + + /* Configure TX interrupt sources to restore. */ + UART_1_IntrTxMask = LO16(UART_1_INTR_TX_MASK_REG); + + #if(UART_1_INTERNAL_RX_SW_BUFFER_CONST) + UART_1_rxBufferHead = 0u; + UART_1_rxBufferTail = 0u; + UART_1_rxBufferOverflow = 0u; + #endif /* (UART_1_INTERNAL_RX_SW_BUFFER_CONST) */ + + #if(UART_1_INTERNAL_TX_SW_BUFFER_CONST) + UART_1_txBufferHead = 0u; + UART_1_txBufferTail = 0u; + #endif /* (UART_1_INTERNAL_TX_SW_BUFFER_CONST) */ + } +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + +/******************************************************************************* +* Function Name: UART_1_UartPostEnable +****************************************************************************//** +* +* Restores HSIOM settings for the UART output pins (TX and/or RTS) to be +* controlled by the SCB UART. +* +*******************************************************************************/ +void UART_1_UartPostEnable(void) +{ +#if (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + #if (UART_1_TX_SDA_MISO_PIN) + if (UART_1_CHECK_TX_SDA_MISO_PIN_USED) + { + /* Set SCB UART to drive the output pin */ + UART_1_SET_HSIOM_SEL(UART_1_TX_SDA_MISO_HSIOM_REG, UART_1_TX_SDA_MISO_HSIOM_MASK, + UART_1_TX_SDA_MISO_HSIOM_POS, UART_1_TX_SDA_MISO_HSIOM_SEL_UART); + } + #endif /* (UART_1_TX_SDA_MISO_PIN_PIN) */ + + #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + #if (UART_1_RTS_SS0_PIN) + if (UART_1_CHECK_RTS_SS0_PIN_USED) + { + /* Set SCB UART to drive the output pin */ + UART_1_SET_HSIOM_SEL(UART_1_RTS_SS0_HSIOM_REG, UART_1_RTS_SS0_HSIOM_MASK, + UART_1_RTS_SS0_HSIOM_POS, UART_1_RTS_SS0_HSIOM_SEL_UART); + } + #endif /* (UART_1_RTS_SS0_PIN) */ + #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + +#else + #if (UART_1_UART_TX_PIN) + /* Set SCB UART to drive the output pin */ + UART_1_SET_HSIOM_SEL(UART_1_TX_HSIOM_REG, UART_1_TX_HSIOM_MASK, + UART_1_TX_HSIOM_POS, UART_1_TX_HSIOM_SEL_UART); + #endif /* (UART_1_UART_TX_PIN) */ + + #if (UART_1_UART_RTS_PIN) + /* Set SCB UART to drive the output pin */ + UART_1_SET_HSIOM_SEL(UART_1_RTS_HSIOM_REG, UART_1_RTS_HSIOM_MASK, + UART_1_RTS_HSIOM_POS, UART_1_RTS_HSIOM_SEL_UART); + #endif /* (UART_1_UART_RTS_PIN) */ +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + + /* Restore TX interrupt sources. */ + UART_1_SetTxInterruptMode(UART_1_IntrTxMask); +} + + +/******************************************************************************* +* Function Name: UART_1_UartStop +****************************************************************************//** +* +* Changes the HSIOM settings for the UART output pins (TX and/or RTS) to keep +* them inactive after the block is disabled. The output pins are controlled by +* the GPIO data register. Also, the function disables the skip start feature +* to not cause it to trigger after the component is enabled. +* +*******************************************************************************/ +void UART_1_UartStop(void) +{ +#if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) + #if (UART_1_TX_SDA_MISO_PIN) + if (UART_1_CHECK_TX_SDA_MISO_PIN_USED) + { + /* Set GPIO to drive output pin */ + UART_1_SET_HSIOM_SEL(UART_1_TX_SDA_MISO_HSIOM_REG, UART_1_TX_SDA_MISO_HSIOM_MASK, + UART_1_TX_SDA_MISO_HSIOM_POS, UART_1_TX_SDA_MISO_HSIOM_SEL_GPIO); + } + #endif /* (UART_1_TX_SDA_MISO_PIN_PIN) */ + + #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + #if (UART_1_RTS_SS0_PIN) + if (UART_1_CHECK_RTS_SS0_PIN_USED) + { + /* Set output pin state after block is disabled */ + UART_1_uart_rts_spi_ss0_Write(UART_1_GET_UART_RTS_INACTIVE); + + /* Set GPIO to drive output pin */ + UART_1_SET_HSIOM_SEL(UART_1_RTS_SS0_HSIOM_REG, UART_1_RTS_SS0_HSIOM_MASK, + UART_1_RTS_SS0_HSIOM_POS, UART_1_RTS_SS0_HSIOM_SEL_GPIO); + } + #endif /* (UART_1_RTS_SS0_PIN) */ + #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + +#else + #if (UART_1_UART_TX_PIN) + /* Set GPIO to drive output pin */ + UART_1_SET_HSIOM_SEL(UART_1_TX_HSIOM_REG, UART_1_TX_HSIOM_MASK, + UART_1_TX_HSIOM_POS, UART_1_TX_HSIOM_SEL_GPIO); + #endif /* (UART_1_UART_TX_PIN) */ + + #if (UART_1_UART_RTS_PIN) + /* Set output pin state after block is disabled */ + UART_1_rts_Write(UART_1_GET_UART_RTS_INACTIVE); + + /* Set GPIO to drive output pin */ + UART_1_SET_HSIOM_SEL(UART_1_RTS_HSIOM_REG, UART_1_RTS_HSIOM_MASK, + UART_1_RTS_HSIOM_POS, UART_1_RTS_HSIOM_SEL_GPIO); + #endif /* (UART_1_UART_RTS_PIN) */ + +#endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ + +#if (UART_1_UART_WAKE_ENABLE_CONST) + /* Disable skip start feature used for wakeup */ + UART_1_UART_RX_CTRL_REG &= (uint32) ~UART_1_UART_RX_CTRL_SKIP_START; +#endif /* (UART_1_UART_WAKE_ENABLE_CONST) */ + + /* Store TX interrupt sources (exclude level triggered). */ + UART_1_IntrTxMask = LO16(UART_1_GetTxInterruptMode() & UART_1_INTR_UART_TX_RESTORE); +} + + +/******************************************************************************* +* Function Name: UART_1_UartSetRxAddress +****************************************************************************//** +* +* Sets the hardware detectable receiver address for the UART in the +* Multiprocessor mode. +* +* \param address: Address for hardware address detection. +* +*******************************************************************************/ +void UART_1_UartSetRxAddress(uint32 address) +{ + uint32 matchReg; + + matchReg = UART_1_RX_MATCH_REG; + + matchReg &= ((uint32) ~UART_1_RX_MATCH_ADDR_MASK); /* Clear address bits */ + matchReg |= ((uint32) (address & UART_1_RX_MATCH_ADDR_MASK)); /* Set address */ + + UART_1_RX_MATCH_REG = matchReg; +} + + +/******************************************************************************* +* Function Name: UART_1_UartSetRxAddressMask +****************************************************************************//** +* +* Sets the hardware address mask for the UART in the Multiprocessor mode. +* +* \param addressMask: Address mask. +* - Bit value 0 鈥 excludes bit from address comparison. +* - Bit value 1 鈥 the bit needs to match with the corresponding bit +* of the address. +* +*******************************************************************************/ +void UART_1_UartSetRxAddressMask(uint32 addressMask) +{ + uint32 matchReg; + + matchReg = UART_1_RX_MATCH_REG; + + matchReg &= ((uint32) ~UART_1_RX_MATCH_MASK_MASK); /* Clear address mask bits */ + matchReg |= ((uint32) (addressMask << UART_1_RX_MATCH_MASK_POS)); + + UART_1_RX_MATCH_REG = matchReg; +} + + +#if(UART_1_UART_RX_DIRECTION) + /******************************************************************************* + * Function Name: UART_1_UartGetChar + ****************************************************************************//** + * + * Retrieves next data element from receive buffer. + * This function is designed for ASCII characters and returns a char where + * 1 to 255 are valid characters and 0 indicates an error occurred or no data + * is present. + * - RX software buffer is disabled: Returns data element retrieved from RX + * FIFO. + * - RX software buffer is enabled: Returns data element from the software + * receive buffer. + * + * \return + * Next data element from the receive buffer. ASCII character values from + * 1 to 255 are valid. A returned zero signifies an error condition or no + * data available. + * + * \sideeffect + * The errors bits may not correspond with reading characters due to + * RX FIFO and software buffer usage. + * RX software buffer is enabled: The internal software buffer overflow + * is not treated as an error condition. + * Check UART_1_rxBufferOverflow to capture that error condition. + * + *******************************************************************************/ + uint32 UART_1_UartGetChar(void) + { + uint32 rxData = 0u; + + /* Reads data only if there is data to read */ + if (0u != UART_1_SpiUartGetRxBufferSize()) + { + rxData = UART_1_SpiUartReadRxData(); + } + + if (UART_1_CHECK_INTR_RX(UART_1_INTR_RX_ERR)) + { + rxData = 0u; /* Error occurred: returns zero */ + UART_1_ClearRxInterruptSource(UART_1_INTR_RX_ERR); + } + + return (rxData); + } + + + /******************************************************************************* + * Function Name: UART_1_UartGetByte + ****************************************************************************//** + * + * Retrieves the next data element from the receive buffer, returns the + * received byte and error condition. + * - The RX software buffer is disabled: returns the data element retrieved + * from the RX FIFO. Undefined data will be returned if the RX FIFO is + * empty. + * - The RX software buffer is enabled: returns data element from the + * software receive buffer. + * + * \return + * Bits 7-0 contain the next data element from the receive buffer and + * other bits contain the error condition. + * - UART_1_UART_RX_OVERFLOW - Attempt to write to a full + * receiver FIFO. + * - UART_1_UART_RX_UNDERFLOW Attempt to read from an empty + * receiver FIFO. + * - UART_1_UART_RX_FRAME_ERROR - UART framing error detected. + * - UART_1_UART_RX_PARITY_ERROR - UART parity error detected. + * + * \sideeffect + * The errors bits may not correspond with reading characters due to + * RX FIFO and software buffer usage. + * RX software buffer is enabled: The internal software buffer overflow + * is not treated as an error condition. + * Check UART_1_rxBufferOverflow to capture that error condition. + * + *******************************************************************************/ + uint32 UART_1_UartGetByte(void) + { + uint32 rxData; + uint32 tmpStatus; + + #if (UART_1_CHECK_RX_SW_BUFFER) + { + UART_1_DisableInt(); + } + #endif + + if (0u != UART_1_SpiUartGetRxBufferSize()) + { + /* Enables interrupt to receive more bytes: at least one byte is in + * buffer. + */ + #if (UART_1_CHECK_RX_SW_BUFFER) + { + UART_1_EnableInt(); + } + #endif + + /* Get received byte */ + rxData = UART_1_SpiUartReadRxData(); + } + else + { + /* Reads a byte directly from RX FIFO: underflow is raised in the + * case of empty. Otherwise the first received byte will be read. + */ + rxData = UART_1_RX_FIFO_RD_REG; + + + /* Enables interrupt to receive more bytes. */ + #if (UART_1_CHECK_RX_SW_BUFFER) + { + + /* The byte has been read from RX FIFO. Clear RX interrupt to + * not involve interrupt handler when RX FIFO is empty. + */ + UART_1_ClearRxInterruptSource(UART_1_INTR_RX_NOT_EMPTY); + + UART_1_EnableInt(); + } + #endif + } + + /* Get and clear RX error mask */ + tmpStatus = (UART_1_GetRxInterruptSource() & UART_1_INTR_RX_ERR); + UART_1_ClearRxInterruptSource(UART_1_INTR_RX_ERR); + + /* Puts together data and error status: + * MP mode and accept address: 9th bit is set to notify mark. + */ + rxData |= ((uint32) (tmpStatus << 8u)); + + return (rxData); + } + + + #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + /******************************************************************************* + * Function Name: UART_1_UartSetRtsPolarity + ****************************************************************************//** + * + * Sets active polarity of RTS output signal. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + * \param polarity: Active polarity of RTS output signal. + * - UART_1_UART_RTS_ACTIVE_LOW - RTS signal is active low. + * - UART_1_UART_RTS_ACTIVE_HIGH - RTS signal is active high. + * + *******************************************************************************/ + void UART_1_UartSetRtsPolarity(uint32 polarity) + { + if(0u != polarity) + { + UART_1_UART_FLOW_CTRL_REG |= (uint32) UART_1_UART_FLOW_CTRL_RTS_POLARITY; + } + else + { + UART_1_UART_FLOW_CTRL_REG &= (uint32) ~UART_1_UART_FLOW_CTRL_RTS_POLARITY; + } + } + + + /******************************************************************************* + * Function Name: UART_1_UartSetRtsFifoLevel + ****************************************************************************//** + * + * Sets level in the RX FIFO for RTS signal activation. + * While the RX FIFO has fewer entries than the RX FIFO level the RTS signal + * remains active, otherwise the RTS signal becomes inactive. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + * \param level: Level in the RX FIFO for RTS signal activation. + * The range of valid level values is between 0 and RX FIFO depth - 1. + * Setting level value to 0 disables RTS signal activation. + * + *******************************************************************************/ + void UART_1_UartSetRtsFifoLevel(uint32 level) + { + uint32 uartFlowCtrl; + + uartFlowCtrl = UART_1_UART_FLOW_CTRL_REG; + + uartFlowCtrl &= ((uint32) ~UART_1_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK); /* Clear level mask bits */ + uartFlowCtrl |= ((uint32) (UART_1_UART_FLOW_CTRL_TRIGGER_LEVEL_MASK & level)); + + UART_1_UART_FLOW_CTRL_REG = uartFlowCtrl; + } + #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + +#endif /* (UART_1_UART_RX_DIRECTION) */ + + +#if(UART_1_UART_TX_DIRECTION) + /******************************************************************************* + * Function Name: UART_1_UartPutString + ****************************************************************************//** + * + * Places a NULL terminated string in the transmit buffer to be sent at the + * next available bus time. + * This function is blocking and waits until there is a space available to put + * requested data in transmit buffer. + * + * \param string: pointer to the null terminated string array to be placed in the + * transmit buffer. + * + *******************************************************************************/ + void UART_1_UartPutString(const char8 string[]) + { + uint32 bufIndex; + + bufIndex = 0u; + + /* Blocks the control flow until all data has been sent */ + while(string[bufIndex] != ((char8) 0)) + { + UART_1_UartPutChar((uint32) string[bufIndex]); + bufIndex++; + } + } + + + /******************************************************************************* + * Function Name: UART_1_UartPutCRLF + ****************************************************************************//** + * + * Places byte of data followed by a carriage return (0x0D) and line feed + * (0x0A) in the transmit buffer. + * This function is blocking and waits until there is a space available to put + * all requested data in transmit buffer. + * + * \param txDataByte: the data to be transmitted. + * + *******************************************************************************/ + void UART_1_UartPutCRLF(uint32 txDataByte) + { + UART_1_UartPutChar(txDataByte); /* Blocks control flow until all data has been sent */ + UART_1_UartPutChar(0x0Du); /* Blocks control flow until all data has been sent */ + UART_1_UartPutChar(0x0Au); /* Blocks control flow until all data has been sent */ + } + + + #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) + /******************************************************************************* + * Function Name: UART_1SCB_UartEnableCts + ****************************************************************************//** + * + * Enables usage of CTS input signal by the UART transmitter. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + *******************************************************************************/ + void UART_1_UartEnableCts(void) + { + UART_1_UART_FLOW_CTRL_REG |= (uint32) UART_1_UART_FLOW_CTRL_CTS_ENABLE; + } + + + /******************************************************************************* + * Function Name: UART_1_UartDisableCts + ****************************************************************************//** + * + * Disables usage of CTS input signal by the UART transmitter. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + *******************************************************************************/ + void UART_1_UartDisableCts(void) + { + UART_1_UART_FLOW_CTRL_REG &= (uint32) ~UART_1_UART_FLOW_CTRL_CTS_ENABLE; + } + + + /******************************************************************************* + * Function Name: UART_1_UartSetCtsPolarity + ****************************************************************************//** + * + * Sets active polarity of CTS input signal. + * Only available for PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / + * PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices. + * + * \param + * polarity: Active polarity of CTS output signal. + * - UART_1_UART_CTS_ACTIVE_LOW - CTS signal is active low. + * - UART_1_UART_CTS_ACTIVE_HIGH - CTS signal is active high. + * + *******************************************************************************/ + void UART_1_UartSetCtsPolarity(uint32 polarity) + { + if (0u != polarity) + { + UART_1_UART_FLOW_CTRL_REG |= (uint32) UART_1_UART_FLOW_CTRL_CTS_POLARITY; + } + else + { + UART_1_UART_FLOW_CTRL_REG &= (uint32) ~UART_1_UART_FLOW_CTRL_CTS_POLARITY; + } + } + #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ + + + /******************************************************************************* + * Function Name: UART_1_UartSendBreakBlocking + ****************************************************************************//** + * + * Sends a break condition (logic low) of specified width on UART TX line. + * Blocks until break is completed. Only call this function when UART TX FIFO + * and shifter are empty. + * + * \param breakWidth + * Width of break condition. Valid range is 4 to 16 bits. + * + * \note + * Before sending break all UART TX interrupt sources are disabled. The state + * of UART TX interrupt sources is restored before function returns. + * + * \sideeffect + * If this function is called while there is data in the TX FIFO or shifter that + * data will be shifted out in packets the size of breakWidth. + * + *******************************************************************************/ + void UART_1_UartSendBreakBlocking(uint32 breakWidth) + { + uint32 txCtrlReg; + uint32 txIntrReg; + + /* Disable all UART TX interrupt source and clear UART TX Done history */ + txIntrReg = UART_1_GetTxInterruptMode(); + UART_1_SetTxInterruptMode(0u); + UART_1_ClearTxInterruptSource(UART_1_INTR_TX_UART_DONE); + + /* Store TX CTRL configuration */ + txCtrlReg = UART_1_TX_CTRL_REG; + + /* Set break width */ + UART_1_TX_CTRL_REG = (UART_1_TX_CTRL_REG & (uint32) ~UART_1_TX_CTRL_DATA_WIDTH_MASK) | + UART_1_GET_TX_CTRL_DATA_WIDTH(breakWidth); + + /* Generate break */ + UART_1_TX_FIFO_WR_REG = 0u; + + /* Wait for break completion */ + while (0u == (UART_1_GetTxInterruptSource() & UART_1_INTR_TX_UART_DONE)) + { + } + + /* Clear all UART TX interrupt sources to */ + UART_1_ClearTxInterruptSource(UART_1_INTR_TX_ALL); + + /* Restore TX interrupt sources and data width */ + UART_1_TX_CTRL_REG = txCtrlReg; + UART_1_SetTxInterruptMode(txIntrReg); + } +#endif /* (UART_1_UART_TX_DIRECTION) */ + + +#if (UART_1_UART_WAKE_ENABLE_CONST) + /******************************************************************************* + * Function Name: UART_1_UartSaveConfig + ****************************************************************************//** + * + * Clears and enables an interrupt on a falling edge of the Rx input. The GPIO + * interrupt does not track in the active mode, therefore requires to be + * cleared by this API. + * + *******************************************************************************/ + void UART_1_UartSaveConfig(void) + { + #if (UART_1_UART_RX_WAKEUP_IRQ) + /* Set SKIP_START if requested (set by default). */ + if (0u != UART_1_skipStart) + { + UART_1_UART_RX_CTRL_REG |= (uint32) UART_1_UART_RX_CTRL_SKIP_START; + } + else + { + UART_1_UART_RX_CTRL_REG &= (uint32) ~UART_1_UART_RX_CTRL_SKIP_START; + } + + /* Clear RX GPIO interrupt status and pending interrupt in NVIC because + * falling edge on RX line occurs while UART communication in active mode. + * Enable interrupt: next interrupt trigger should wakeup device. + */ + UART_1_CLEAR_UART_RX_WAKE_INTR; + UART_1_RxWakeClearPendingInt(); + UART_1_RxWakeEnableInt(); + #endif /* (UART_1_UART_RX_WAKEUP_IRQ) */ + } + + + /******************************************************************************* + * Function Name: UART_1_UartRestoreConfig + ****************************************************************************//** + * + * Disables the RX GPIO interrupt. Until this function is called the interrupt + * remains active and triggers on every falling edge of the UART RX line. + * + *******************************************************************************/ + void UART_1_UartRestoreConfig(void) + { + #if (UART_1_UART_RX_WAKEUP_IRQ) + /* Disable interrupt: no more triggers in active mode */ + UART_1_RxWakeDisableInt(); + #endif /* (UART_1_UART_RX_WAKEUP_IRQ) */ + } + + + #if (UART_1_UART_RX_WAKEUP_IRQ) + /******************************************************************************* + * Function Name: UART_1_UART_WAKEUP_ISR + ****************************************************************************//** + * + * Handles the Interrupt Service Routine for the SCB UART mode GPIO wakeup + * event. This event is configured to trigger on a falling edge of the RX line. + * + *******************************************************************************/ + CY_ISR(UART_1_UART_WAKEUP_ISR) + { + #ifdef UART_1_UART_WAKEUP_ISR_ENTRY_CALLBACK + UART_1_UART_WAKEUP_ISR_EntryCallback(); + #endif /* UART_1_UART_WAKEUP_ISR_ENTRY_CALLBACK */ + + UART_1_CLEAR_UART_RX_WAKE_INTR; + + #ifdef UART_1_UART_WAKEUP_ISR_EXIT_CALLBACK + UART_1_UART_WAKEUP_ISR_ExitCallback(); + #endif /* UART_1_UART_WAKEUP_ISR_EXIT_CALLBACK */ + } + #endif /* (UART_1_UART_RX_WAKEUP_IRQ) */ +#endif /* (UART_1_UART_RX_WAKEUP_IRQ) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_UART_BOOT.c b/cores/asr650x/projects/PSoC4/UART_1_UART_BOOT.c new file mode 100644 index 00000000..36409931 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_UART_BOOT.c @@ -0,0 +1,189 @@ +/***************************************************************************//** +* \file UART_1_UART_BOOT.c +* \version 4.0 +* +* \brief +* This file provides the source code of the bootloader communication APIs +* for the SCB Component UART mode. +* +* Note: +* +******************************************************************************** +* \copyright +* Copyright 2013-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "UART_1_BOOT.h" +#include "UART_1_SPI_UART.h" + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && (UART_1_UART_BTLDR_COMM_ENABLED) + +/******************************************************************************* +* Function Name: UART_1_UartCyBtldrCommStart +****************************************************************************//** +* +* Starts the UART component. +* +*******************************************************************************/ +void UART_1_UartCyBtldrCommStart(void) +{ + UART_1_Start(); +} + + +/******************************************************************************* +* Function Name: UART_1_UartCyBtldrCommStop +****************************************************************************//** +* +* Disables the UART component. +* +*******************************************************************************/ +void UART_1_UartCyBtldrCommStop(void) +{ + UART_1_Stop(); +} + + +/******************************************************************************* +* Function Name: UART_1_UartCyBtldrCommReset +****************************************************************************//** +* +* Resets the receive and transmit communication buffers. +* +*******************************************************************************/ +void UART_1_UartCyBtldrCommReset(void) +{ + /* Clear RX and TX buffers */ + UART_1_SpiUartClearRxBuffer(); + UART_1_SpiUartClearTxBuffer(); +} + + +/******************************************************************************* +* Function Name: UART_1_UartCyBtldrCommRead +****************************************************************************//** +* +* Allows the caller to read data from the bootloader host (the host writes the +* data). The function handles polling to allow a block of data to be completely +* received from the host device. +* +* \param pData: Pointer to storage for the block of data to be read from the +* bootloader host +* \param size: Number of bytes to be read. +* \param count: Pointer to the variable to write the number of bytes actually +* read. +* \param timeOut Number of units in 10 ms to wait before returning +* because of a timeout. +* +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value +* that best describes the problem. For more information refer to the +* "Return Codes" section of the System Reference Guide. +* +*******************************************************************************/ +cystatus UART_1_UartCyBtldrCommRead(uint8 pData[], uint16 size, uint16 * count, uint8 timeOut) +{ + cystatus status; + uint32 byteCount; + uint32 timeoutMs; + uint32 i; + + status = CYRET_BAD_PARAM; + + if ((NULL != pData) && (size > 0u)) + { + status = CYRET_TIMEOUT; + timeoutMs = ((uint32) 10u * timeOut); /* Convert from 10mS check to 1mS checks */ + + /* Wait with timeout 1mS for packet end */ + byteCount = 0u; + do + { + /* Check packet start */ + if (0u != UART_1_SpiUartGetRxBufferSize()) + { + /* Wait for end of packet */ + do + { + byteCount = UART_1_SpiUartGetRxBufferSize(); + CyDelayUs(UART_1_UART_BYTE_TO_BYTE); + } + while (byteCount != UART_1_SpiUartGetRxBufferSize()); + + byteCount = UART_1_BYTES_TO_COPY(byteCount, size); + *count = (uint16) byteCount; + status = CYRET_SUCCESS; + + break; + } + + CyDelay(UART_1_WAIT_1_MS); + --timeoutMs; + } + while (0u != timeoutMs); + + /* Get data from RX buffer into bootloader buffer */ + for (i = 0u; i < byteCount; ++i) + { + pData[i] = (uint8) UART_1_SpiUartReadRxData(); + } + } + + return (status); +} + + +/******************************************************************************* +* Function Name: UART_1_UartCyBtldrCommWrite +****************************************************************************//** +* +* Allows the caller to write data to the bootloader host (the host reads the +* data). The function does not use timeout and returns after data has been +* copied into the transmit buffer. The data transmission starts immediately +* after the first data element is written into the buffer and lasts until all +* data elements from the buffer are sent. +* +* \param pData: Pointer to the block of data to be written to the bootloader +* host. +* \param size: Number of bytes to be written. +* \param count: Pointer to the variable to write the number of bytes actually +* written. +* \param timeOut: The timeout is not used by this function. +* The function returns as soon as data is copied into the transmit buffer. +* +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value +* that best describes the problem. For more information refer to the +* "Return Codes" section of the System Reference Guide. +* +*******************************************************************************/ +cystatus UART_1_UartCyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 * count, uint8 timeOut) +{ + cystatus status; + + status = CYRET_BAD_PARAM; + + if ((NULL != pData) && (size > 0u)) + { + /* Transmit data. This function does not wait until data is sent. */ + UART_1_SpiUartPutArray(pData, (uint32) size); + + *count = size; + status = CYRET_SUCCESS; + + if (0u != timeOut) + { + /* Suppress compiler warning */ + } + } + + return (status); +} + +#endif /* defined(CYDEV_BOOTLOADER_IO_COMP) && (UART_1_UART_BTLDR_COMM_ENABLED) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_rx_wake.c b/cores/asr650x/projects/PSoC4/UART_1_rx_wake.c new file mode 100644 index 00000000..9a798a52 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_rx_wake.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* File Name: UART_1_rx_wake.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "UART_1_rx_wake.h" + + +#if defined(UART_1_rx_wake__PC) + #define UART_1_rx_wake_SetP4PinDriveMode(shift, mode) \ + do { \ + UART_1_rx_wake_PC = (UART_1_rx_wake_PC & \ + (uint32)(~(uint32)(UART_1_rx_wake_DRIVE_MODE_IND_MASK << \ + (UART_1_rx_wake_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (UART_1_rx_wake_DRIVE_MODE_BITS * (shift))); \ + } while (0) +#else + #if (CY_PSOC4_4200L) + #define UART_1_rx_wake_SetP4PinDriveMode(shift, mode) \ + do { \ + UART_1_rx_wake_USBIO_CTRL_REG = (UART_1_rx_wake_USBIO_CTRL_REG & \ + (uint32)(~(uint32)(UART_1_rx_wake_DRIVE_MODE_IND_MASK << \ + (UART_1_rx_wake_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (UART_1_rx_wake_DRIVE_MODE_BITS * (shift))); \ + } while (0) + #endif +#endif + + +#if defined(UART_1_rx_wake__PC) || (CY_PSOC4_4200L) + /******************************************************************************* + * Function Name: UART_1_rx_wake_SetDriveMode + ****************************************************************************//** + * + * \brief Sets the drive mode for each of the Pins component's pins. + * + * Note This affects all pins in the Pins component instance. Use the + * Per-Pin APIs if you wish to control individual pin's drive modes. + * + * Note USBIOs have limited drive functionality. Refer to the Drive Mode + * parameter for more information. + * + * \param mode + * Mode for the selected signals. Valid options are documented in + * \ref driveMode. + * + * \return + * None + * + * \sideeffect + * If you use read-modify-write operations that are not atomic, the ISR can + * cause corruption of this function. An ISR that interrupts this function + * and performs writes to the Pins component Drive Mode registers can cause + * corrupted port data. To avoid this issue, you should either use the Per-Pin + * APIs (primary method) or disable interrupts around this function. + * + * \funcusage + * \snippet UART_1_rx_wake_SUT.c usage_UART_1_rx_wake_SetDriveMode + *******************************************************************************/ + void UART_1_rx_wake_SetDriveMode(uint8 mode) + { + UART_1_rx_wake_SetP4PinDriveMode(UART_1_rx_wake__0__SHIFT, mode); + } +#endif + + +/******************************************************************************* +* Function Name: UART_1_rx_wake_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet UART_1_rx_wake_SUT.c usage_UART_1_rx_wake_Write +*******************************************************************************/ +void UART_1_rx_wake_Write(uint8 value) +{ + uint8 drVal = (uint8)(UART_1_rx_wake_DR & (uint8)(~UART_1_rx_wake_MASK)); + drVal = (drVal | ((uint8)(value << UART_1_rx_wake_SHIFT) & UART_1_rx_wake_MASK)); + UART_1_rx_wake_DR = (uint32)drVal; +} + + +/******************************************************************************* +* Function Name: UART_1_rx_wake_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet UART_1_rx_wake_SUT.c usage_UART_1_rx_wake_Read +*******************************************************************************/ +uint8 UART_1_rx_wake_Read(void) +{ + return (uint8)((UART_1_rx_wake_PS & UART_1_rx_wake_MASK) >> UART_1_rx_wake_SHIFT); +} + + +/******************************************************************************* +* Function Name: UART_1_rx_wake_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred UART_1_rx_wake_Read() API because the +* UART_1_rx_wake_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet UART_1_rx_wake_SUT.c usage_UART_1_rx_wake_ReadDataReg +*******************************************************************************/ +uint8 UART_1_rx_wake_ReadDataReg(void) +{ + return (uint8)((UART_1_rx_wake_DR & UART_1_rx_wake_MASK) >> UART_1_rx_wake_SHIFT); +} + + +/******************************************************************************* +* Function Name: UART_1_rx_wake_SetInterruptMode +****************************************************************************//** +* +* \brief Configures the interrupt mode for each of the Pins component's +* pins. Alternatively you may set the interrupt mode for all the pins +* specified in the Pins component. +* +* Note The interrupt is port-wide and therefore any enabled pin +* interrupt may trigger it. +* +* \param position +* The pin position as listed in the Pins component. You may OR these to be +* able to configure the interrupt mode of multiple pins within a Pins +* component. Or you may use UART_1_rx_wake_INTR_ALL to configure the +* interrupt mode of all the pins in the Pins component. +* - UART_1_rx_wake_0_INTR (First pin in the list) +* - UART_1_rx_wake_1_INTR (Second pin in the list) +* - ... +* - UART_1_rx_wake_INTR_ALL (All pins in Pins component) +* +* \param mode +* Interrupt mode for the selected pins. Valid options are documented in +* \ref intrMode. +* +* \return +* None +* +* \sideeffect +* It is recommended that the interrupt be disabled before calling this +* function to avoid unintended interrupt requests. Note that the interrupt +* type is port wide, and therefore will trigger for any enabled pin on the +* port. +* +* \funcusage +* \snippet UART_1_rx_wake_SUT.c usage_UART_1_rx_wake_SetInterruptMode +*******************************************************************************/ +void UART_1_rx_wake_SetInterruptMode(uint16 position, uint16 mode) +{ + uint32 intrCfg; + + intrCfg = UART_1_rx_wake_INTCFG & (uint32)(~(uint32)position); + UART_1_rx_wake_INTCFG = intrCfg | ((uint32)position & (uint32)mode); +} + + +/******************************************************************************* +* Function Name: UART_1_rx_wake_ClearInterrupt +****************************************************************************//** +* +* \brief Clears any active interrupts attached with the component and returns +* the value of the interrupt status register allowing determination of which +* pins generated an interrupt event. +* +* \return +* The right-shifted current value of the interrupt status register. Each pin +* has one bit set if it generated an interrupt event. For example, bit 0 is +* for pin 0 and bit 1 is for pin 1 of the Pins component. +* +* \sideeffect +* Clears all bits of the physical port's interrupt status register, not just +* those associated with the Pins component. +* +* \funcusage +* \snippet UART_1_rx_wake_SUT.c usage_UART_1_rx_wake_ClearInterrupt +*******************************************************************************/ +uint8 UART_1_rx_wake_ClearInterrupt(void) +{ + uint8 maskedStatus = (uint8)(UART_1_rx_wake_INTSTAT & UART_1_rx_wake_MASK); + UART_1_rx_wake_INTSTAT = maskedStatus; + return maskedStatus >> UART_1_rx_wake_SHIFT; +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_rx_wake.h b/cores/asr650x/projects/PSoC4/UART_1_rx_wake.h new file mode 100644 index 00000000..a7f01467 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_rx_wake.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* File Name: UART_1_rx_wake.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_UART_1_rx_wake_H) /* Pins UART_1_rx_wake_H */ +#define CY_PINS_UART_1_rx_wake_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "UART_1_rx_wake_aliases.h" + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* Structure for sleep mode support */ +typedef struct +{ + uint32 pcState; /**< State of the port control register */ + uint32 sioState; /**< State of the SIO configuration */ + uint32 usbState; /**< State of the USBIO regulator */ +} UART_1_rx_wake_BACKUP_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +uint8 UART_1_rx_wake_Read(void); +void UART_1_rx_wake_Write(uint8 value); +uint8 UART_1_rx_wake_ReadDataReg(void); +#if defined(UART_1_rx_wake__PC) || (CY_PSOC4_4200L) + void UART_1_rx_wake_SetDriveMode(uint8 mode); +#endif +void UART_1_rx_wake_SetInterruptMode(uint16 position, uint16 mode); +uint8 UART_1_rx_wake_ClearInterrupt(void); +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +void UART_1_rx_wake_Sleep(void); +void UART_1_rx_wake_Wakeup(void); +/** @} power */ + + +/*************************************** +* API Constants +***************************************/ +#if defined(UART_1_rx_wake__PC) || (CY_PSOC4_4200L) + /* Drive Modes */ + #define UART_1_rx_wake_DRIVE_MODE_BITS (3) + #define UART_1_rx_wake_DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - UART_1_rx_wake_DRIVE_MODE_BITS)) + + /** + * \addtogroup group_constants + * @{ + */ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the UART_1_rx_wake_SetDriveMode() function. + * @{ + */ + #define UART_1_rx_wake_DM_ALG_HIZ (0x00u) /**< \brief High Impedance Analog */ + #define UART_1_rx_wake_DM_DIG_HIZ (0x01u) /**< \brief High Impedance Digital */ + #define UART_1_rx_wake_DM_RES_UP (0x02u) /**< \brief Resistive Pull Up */ + #define UART_1_rx_wake_DM_RES_DWN (0x03u) /**< \brief Resistive Pull Down */ + #define UART_1_rx_wake_DM_OD_LO (0x04u) /**< \brief Open Drain, Drives Low */ + #define UART_1_rx_wake_DM_OD_HI (0x05u) /**< \brief Open Drain, Drives High */ + #define UART_1_rx_wake_DM_STRONG (0x06u) /**< \brief Strong Drive */ + #define UART_1_rx_wake_DM_RES_UPDWN (0x07u) /**< \brief Resistive Pull Up/Down */ + /** @} driveMode */ + /** @} group_constants */ +#endif + +/* Digital Port Constants */ +#define UART_1_rx_wake_MASK UART_1_rx_wake__MASK +#define UART_1_rx_wake_SHIFT UART_1_rx_wake__SHIFT +#define UART_1_rx_wake_WIDTH 1u + +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in UART_1_rx_wake_SetInterruptMode() function. + * @{ + */ + #define UART_1_rx_wake_INTR_NONE ((uint16)(0x0000u)) /**< \brief Disabled */ + #define UART_1_rx_wake_INTR_RISING ((uint16)(0x5555u)) /**< \brief Rising edge trigger */ + #define UART_1_rx_wake_INTR_FALLING ((uint16)(0xaaaau)) /**< \brief Falling edge trigger */ + #define UART_1_rx_wake_INTR_BOTH ((uint16)(0xffffu)) /**< \brief Both edge trigger */ + /** @} intrMode */ +/** @} group_constants */ + +/* SIO LPM definition */ +#if defined(UART_1_rx_wake__SIO) + #define UART_1_rx_wake_SIO_LPM_MASK (0x03u) +#endif + +/* USBIO definitions */ +#if !defined(UART_1_rx_wake__PC) && (CY_PSOC4_4200L) + #define UART_1_rx_wake_USBIO_ENABLE ((uint32)0x80000000u) + #define UART_1_rx_wake_USBIO_DISABLE ((uint32)(~UART_1_rx_wake_USBIO_ENABLE)) + #define UART_1_rx_wake_USBIO_SUSPEND_SHIFT CYFLD_USBDEVv2_USB_SUSPEND__OFFSET + #define UART_1_rx_wake_USBIO_SUSPEND_DEL_SHIFT CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET + #define UART_1_rx_wake_USBIO_ENTER_SLEEP ((uint32)((1u << UART_1_rx_wake_USBIO_SUSPEND_SHIFT) \ + | (1u << UART_1_rx_wake_USBIO_SUSPEND_DEL_SHIFT))) + #define UART_1_rx_wake_USBIO_EXIT_SLEEP_PH1 ((uint32)~((uint32)(1u << UART_1_rx_wake_USBIO_SUSPEND_SHIFT))) + #define UART_1_rx_wake_USBIO_EXIT_SLEEP_PH2 ((uint32)~((uint32)(1u << UART_1_rx_wake_USBIO_SUSPEND_DEL_SHIFT))) + #define UART_1_rx_wake_USBIO_CR1_OFF ((uint32)0xfffffffeu) +#endif + + +/*************************************** +* Registers +***************************************/ +/* Main Port Registers */ +#if defined(UART_1_rx_wake__PC) + /* Port Configuration */ + #define UART_1_rx_wake_PC (* (reg32 *) UART_1_rx_wake__PC) +#endif +/* Pin State */ +#define UART_1_rx_wake_PS (* (reg32 *) UART_1_rx_wake__PS) +/* Data Register */ +#define UART_1_rx_wake_DR (* (reg32 *) UART_1_rx_wake__DR) +/* Input Buffer Disable Override */ +#define UART_1_rx_wake_INP_DIS (* (reg32 *) UART_1_rx_wake__PC2) + +/* Interrupt configuration Registers */ +#define UART_1_rx_wake_INTCFG (* (reg32 *) UART_1_rx_wake__INTCFG) +#define UART_1_rx_wake_INTSTAT (* (reg32 *) UART_1_rx_wake__INTSTAT) + +/* "Interrupt cause" register for Combined Port Interrupt (AllPortInt) in GSRef component */ +#if defined (CYREG_GPIO_INTR_CAUSE) + #define UART_1_rx_wake_INTR_CAUSE (* (reg32 *) CYREG_GPIO_INTR_CAUSE) +#endif + +/* SIO register */ +#if defined(UART_1_rx_wake__SIO) + #define UART_1_rx_wake_SIO_REG (* (reg32 *) UART_1_rx_wake__SIO) +#endif /* (UART_1_rx_wake__SIO_CFG) */ + +/* USBIO registers */ +#if !defined(UART_1_rx_wake__PC) && (CY_PSOC4_4200L) + #define UART_1_rx_wake_USB_POWER_REG (* (reg32 *) CYREG_USBDEVv2_USB_POWER_CTRL) + #define UART_1_rx_wake_CR1_REG (* (reg32 *) CYREG_USBDEVv2_CR1) + #define UART_1_rx_wake_USBIO_CTRL_REG (* (reg32 *) CYREG_USBDEVv2_USB_USBIO_CTRL) +#endif + + +/*************************************** +* The following code is DEPRECATED and +* must not be used in new designs. +***************************************/ +/** +* \addtogroup group_deprecated +* @{ +*/ +#define UART_1_rx_wake_DRIVE_MODE_SHIFT (0x00u) +#define UART_1_rx_wake_DRIVE_MODE_MASK (0x07u << UART_1_rx_wake_DRIVE_MODE_SHIFT) +/** @} deprecated */ + +#endif /* End Pins UART_1_rx_wake_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_rx_wake_PM.c b/cores/asr650x/projects/PSoC4/UART_1_rx_wake_PM.c new file mode 100644 index 00000000..e2b52268 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_rx_wake_PM.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: UART_1_rx_wake.c +* Version 2.20 +* +* Description: +* This file contains APIs to set up the Pins component for low power modes. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "UART_1_rx_wake.h" + +static UART_1_rx_wake_BACKUP_STRUCT UART_1_rx_wake_backup = {0u, 0u, 0u}; + + +/******************************************************************************* +* Function Name: UART_1_rx_wake_Sleep +****************************************************************************//** +* +* \brief Stores the pin configuration and prepares the pin for entering chip +* deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. +* It should not be called for GPIO or GPIO_OVT pins. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \sideeffect +* For SIO pins, this function configures the pin input threshold to CMOS and +* drive level to Vddio. This is needed for SIO pins when in device +* deep-sleep/hibernate modes. +* +* \funcusage +* \snippet UART_1_rx_wake_SUT.c usage_UART_1_rx_wake_Sleep_Wakeup +*******************************************************************************/ +void UART_1_rx_wake_Sleep(void) +{ + #if defined(UART_1_rx_wake__PC) + UART_1_rx_wake_backup.pcState = UART_1_rx_wake_PC; + #else + #if (CY_PSOC4_4200L) + /* Save the regulator state and put the PHY into suspend mode */ + UART_1_rx_wake_backup.usbState = UART_1_rx_wake_CR1_REG; + UART_1_rx_wake_USB_POWER_REG |= UART_1_rx_wake_USBIO_ENTER_SLEEP; + UART_1_rx_wake_CR1_REG &= UART_1_rx_wake_USBIO_CR1_OFF; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(UART_1_rx_wake__SIO) + UART_1_rx_wake_backup.sioState = UART_1_rx_wake_SIO_REG; + /* SIO requires unregulated output buffer and single ended input buffer */ + UART_1_rx_wake_SIO_REG &= (uint32)(~UART_1_rx_wake_SIO_LPM_MASK); + #endif +} + + +/******************************************************************************* +* Function Name: UART_1_rx_wake_Wakeup +****************************************************************************//** +* +* \brief Restores the pin configuration that was saved during Pin_Sleep(). This +* function applies only to SIO and USBIO pins. It should not be called for +* GPIO or GPIO_OVT pins. +* +* For USBIO pins, the wakeup is only triggered for falling edge interrupts. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \funcusage +* Refer to UART_1_rx_wake_Sleep() for an example usage. +*******************************************************************************/ +void UART_1_rx_wake_Wakeup(void) +{ + #if defined(UART_1_rx_wake__PC) + UART_1_rx_wake_PC = UART_1_rx_wake_backup.pcState; + #else + #if (CY_PSOC4_4200L) + /* Restore the regulator state and come out of suspend mode */ + UART_1_rx_wake_USB_POWER_REG &= UART_1_rx_wake_USBIO_EXIT_SLEEP_PH1; + UART_1_rx_wake_CR1_REG = UART_1_rx_wake_backup.usbState; + UART_1_rx_wake_USB_POWER_REG &= UART_1_rx_wake_USBIO_EXIT_SLEEP_PH2; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(UART_1_rx_wake__SIO) + UART_1_rx_wake_SIO_REG = UART_1_rx_wake_backup.sioState; + #endif +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_rx_wake_aliases.h b/cores/asr650x/projects/PSoC4/UART_1_rx_wake_aliases.h new file mode 100644 index 00000000..3033ca81 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_rx_wake_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: UART_1_rx_wake.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_UART_1_rx_wake_ALIASES_H) /* Pins UART_1_rx_wake_ALIASES_H */ +#define CY_PINS_UART_1_rx_wake_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" + + +/*************************************** +* Constants +***************************************/ +#define UART_1_rx_wake_0 (UART_1_rx_wake__0__PC) +#define UART_1_rx_wake_0_PS (UART_1_rx_wake__0__PS) +#define UART_1_rx_wake_0_PC (UART_1_rx_wake__0__PC) +#define UART_1_rx_wake_0_DR (UART_1_rx_wake__0__DR) +#define UART_1_rx_wake_0_SHIFT (UART_1_rx_wake__0__SHIFT) +#define UART_1_rx_wake_0_INTR ((uint16)((uint16)0x0003u << (UART_1_rx_wake__0__SHIFT*2u))) + +#define UART_1_rx_wake_INTR_ALL ((uint16)(UART_1_rx_wake_0_INTR)) + + +#endif /* End Pins UART_1_rx_wake_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_tx.c b/cores/asr650x/projects/PSoC4/UART_1_tx.c new file mode 100644 index 00000000..1da035fe --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_tx.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* File Name: UART_1_tx.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "UART_1_tx.h" + + +#if defined(UART_1_tx__PC) + #define UART_1_tx_SetP4PinDriveMode(shift, mode) \ + do { \ + UART_1_tx_PC = (UART_1_tx_PC & \ + (uint32)(~(uint32)(UART_1_tx_DRIVE_MODE_IND_MASK << \ + (UART_1_tx_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (UART_1_tx_DRIVE_MODE_BITS * (shift))); \ + } while (0) +#else + #if (CY_PSOC4_4200L) + #define UART_1_tx_SetP4PinDriveMode(shift, mode) \ + do { \ + UART_1_tx_USBIO_CTRL_REG = (UART_1_tx_USBIO_CTRL_REG & \ + (uint32)(~(uint32)(UART_1_tx_DRIVE_MODE_IND_MASK << \ + (UART_1_tx_DRIVE_MODE_BITS * (shift))))) | \ + (uint32)((uint32)(mode) << \ + (UART_1_tx_DRIVE_MODE_BITS * (shift))); \ + } while (0) + #endif +#endif + + +#if defined(UART_1_tx__PC) || (CY_PSOC4_4200L) + /******************************************************************************* + * Function Name: UART_1_tx_SetDriveMode + ****************************************************************************//** + * + * \brief Sets the drive mode for each of the Pins component's pins. + * + * Note This affects all pins in the Pins component instance. Use the + * Per-Pin APIs if you wish to control individual pin's drive modes. + * + * Note USBIOs have limited drive functionality. Refer to the Drive Mode + * parameter for more information. + * + * \param mode + * Mode for the selected signals. Valid options are documented in + * \ref driveMode. + * + * \return + * None + * + * \sideeffect + * If you use read-modify-write operations that are not atomic, the ISR can + * cause corruption of this function. An ISR that interrupts this function + * and performs writes to the Pins component Drive Mode registers can cause + * corrupted port data. To avoid this issue, you should either use the Per-Pin + * APIs (primary method) or disable interrupts around this function. + * + * \funcusage + * \snippet UART_1_tx_SUT.c usage_UART_1_tx_SetDriveMode + *******************************************************************************/ + void UART_1_tx_SetDriveMode(uint8 mode) + { + UART_1_tx_SetP4PinDriveMode(UART_1_tx__0__SHIFT, mode); + } +#endif + + +/******************************************************************************* +* Function Name: UART_1_tx_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet UART_1_tx_SUT.c usage_UART_1_tx_Write +*******************************************************************************/ +void UART_1_tx_Write(uint8 value) +{ + uint8 drVal = (uint8)(UART_1_tx_DR & (uint8)(~UART_1_tx_MASK)); + drVal = (drVal | ((uint8)(value << UART_1_tx_SHIFT) & UART_1_tx_MASK)); + UART_1_tx_DR = (uint32)drVal; +} + + +/******************************************************************************* +* Function Name: UART_1_tx_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet UART_1_tx_SUT.c usage_UART_1_tx_Read +*******************************************************************************/ +uint8 UART_1_tx_Read(void) +{ + return (uint8)((UART_1_tx_PS & UART_1_tx_MASK) >> UART_1_tx_SHIFT); +} + + +/******************************************************************************* +* Function Name: UART_1_tx_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred UART_1_tx_Read() API because the +* UART_1_tx_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet UART_1_tx_SUT.c usage_UART_1_tx_ReadDataReg +*******************************************************************************/ +uint8 UART_1_tx_ReadDataReg(void) +{ + return (uint8)((UART_1_tx_DR & UART_1_tx_MASK) >> UART_1_tx_SHIFT); +} + + +/******************************************************************************* +* Function Name: UART_1_tx_SetInterruptMode +****************************************************************************//** +* +* \brief Configures the interrupt mode for each of the Pins component's +* pins. Alternatively you may set the interrupt mode for all the pins +* specified in the Pins component. +* +* Note The interrupt is port-wide and therefore any enabled pin +* interrupt may trigger it. +* +* \param position +* The pin position as listed in the Pins component. You may OR these to be +* able to configure the interrupt mode of multiple pins within a Pins +* component. Or you may use UART_1_tx_INTR_ALL to configure the +* interrupt mode of all the pins in the Pins component. +* - UART_1_tx_0_INTR (First pin in the list) +* - UART_1_tx_1_INTR (Second pin in the list) +* - ... +* - UART_1_tx_INTR_ALL (All pins in Pins component) +* +* \param mode +* Interrupt mode for the selected pins. Valid options are documented in +* \ref intrMode. +* +* \return +* None +* +* \sideeffect +* It is recommended that the interrupt be disabled before calling this +* function to avoid unintended interrupt requests. Note that the interrupt +* type is port wide, and therefore will trigger for any enabled pin on the +* port. +* +* \funcusage +* \snippet UART_1_tx_SUT.c usage_UART_1_tx_SetInterruptMode +*******************************************************************************/ +void UART_1_tx_SetInterruptMode(uint16 position, uint16 mode) +{ + uint32 intrCfg; + + intrCfg = UART_1_tx_INTCFG & (uint32)(~(uint32)position); + UART_1_tx_INTCFG = intrCfg | ((uint32)position & (uint32)mode); +} + + +/******************************************************************************* +* Function Name: UART_1_tx_ClearInterrupt +****************************************************************************//** +* +* \brief Clears any active interrupts attached with the component and returns +* the value of the interrupt status register allowing determination of which +* pins generated an interrupt event. +* +* \return +* The right-shifted current value of the interrupt status register. Each pin +* has one bit set if it generated an interrupt event. For example, bit 0 is +* for pin 0 and bit 1 is for pin 1 of the Pins component. +* +* \sideeffect +* Clears all bits of the physical port's interrupt status register, not just +* those associated with the Pins component. +* +* \funcusage +* \snippet UART_1_tx_SUT.c usage_UART_1_tx_ClearInterrupt +*******************************************************************************/ +uint8 UART_1_tx_ClearInterrupt(void) +{ + uint8 maskedStatus = (uint8)(UART_1_tx_INTSTAT & UART_1_tx_MASK); + UART_1_tx_INTSTAT = maskedStatus; + return maskedStatus >> UART_1_tx_SHIFT; +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_tx.h b/cores/asr650x/projects/PSoC4/UART_1_tx.h new file mode 100644 index 00000000..e3b47aaf --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_tx.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* File Name: UART_1_tx.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_UART_1_tx_H) /* Pins UART_1_tx_H */ +#define CY_PINS_UART_1_tx_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "UART_1_tx_aliases.h" + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/** +* \addtogroup group_structures +* @{ +*/ + +/* Structure for sleep mode support */ +typedef struct +{ + uint32 pcState; /**< State of the port control register */ + uint32 sioState; /**< State of the SIO configuration */ + uint32 usbState; /**< State of the USBIO regulator */ +} UART_1_tx_BACKUP_STRUCT; + +/** @} structures */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +uint8 UART_1_tx_Read(void); +void UART_1_tx_Write(uint8 value); +uint8 UART_1_tx_ReadDataReg(void); +#if defined(UART_1_tx__PC) || (CY_PSOC4_4200L) + void UART_1_tx_SetDriveMode(uint8 mode); +#endif +void UART_1_tx_SetInterruptMode(uint16 position, uint16 mode); +uint8 UART_1_tx_ClearInterrupt(void); +/** @} general */ + +/** +* \addtogroup group_power +* @{ +*/ +void UART_1_tx_Sleep(void); +void UART_1_tx_Wakeup(void); +/** @} power */ + + +/*************************************** +* API Constants +***************************************/ +#if defined(UART_1_tx__PC) || (CY_PSOC4_4200L) + /* Drive Modes */ + #define UART_1_tx_DRIVE_MODE_BITS (3) + #define UART_1_tx_DRIVE_MODE_IND_MASK (0xFFFFFFFFu >> (32 - UART_1_tx_DRIVE_MODE_BITS)) + + /** + * \addtogroup group_constants + * @{ + */ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the UART_1_tx_SetDriveMode() function. + * @{ + */ + #define UART_1_tx_DM_ALG_HIZ (0x00u) /**< \brief High Impedance Analog */ + #define UART_1_tx_DM_DIG_HIZ (0x01u) /**< \brief High Impedance Digital */ + #define UART_1_tx_DM_RES_UP (0x02u) /**< \brief Resistive Pull Up */ + #define UART_1_tx_DM_RES_DWN (0x03u) /**< \brief Resistive Pull Down */ + #define UART_1_tx_DM_OD_LO (0x04u) /**< \brief Open Drain, Drives Low */ + #define UART_1_tx_DM_OD_HI (0x05u) /**< \brief Open Drain, Drives High */ + #define UART_1_tx_DM_STRONG (0x06u) /**< \brief Strong Drive */ + #define UART_1_tx_DM_RES_UPDWN (0x07u) /**< \brief Resistive Pull Up/Down */ + /** @} driveMode */ + /** @} group_constants */ +#endif + +/* Digital Port Constants */ +#define UART_1_tx_MASK UART_1_tx__MASK +#define UART_1_tx_SHIFT UART_1_tx__SHIFT +#define UART_1_tx_WIDTH 1u + +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in UART_1_tx_SetInterruptMode() function. + * @{ + */ + #define UART_1_tx_INTR_NONE ((uint16)(0x0000u)) /**< \brief Disabled */ + #define UART_1_tx_INTR_RISING ((uint16)(0x5555u)) /**< \brief Rising edge trigger */ + #define UART_1_tx_INTR_FALLING ((uint16)(0xaaaau)) /**< \brief Falling edge trigger */ + #define UART_1_tx_INTR_BOTH ((uint16)(0xffffu)) /**< \brief Both edge trigger */ + /** @} intrMode */ +/** @} group_constants */ + +/* SIO LPM definition */ +#if defined(UART_1_tx__SIO) + #define UART_1_tx_SIO_LPM_MASK (0x03u) +#endif + +/* USBIO definitions */ +#if !defined(UART_1_tx__PC) && (CY_PSOC4_4200L) + #define UART_1_tx_USBIO_ENABLE ((uint32)0x80000000u) + #define UART_1_tx_USBIO_DISABLE ((uint32)(~UART_1_tx_USBIO_ENABLE)) + #define UART_1_tx_USBIO_SUSPEND_SHIFT CYFLD_USBDEVv2_USB_SUSPEND__OFFSET + #define UART_1_tx_USBIO_SUSPEND_DEL_SHIFT CYFLD_USBDEVv2_USB_SUSPEND_DEL__OFFSET + #define UART_1_tx_USBIO_ENTER_SLEEP ((uint32)((1u << UART_1_tx_USBIO_SUSPEND_SHIFT) \ + | (1u << UART_1_tx_USBIO_SUSPEND_DEL_SHIFT))) + #define UART_1_tx_USBIO_EXIT_SLEEP_PH1 ((uint32)~((uint32)(1u << UART_1_tx_USBIO_SUSPEND_SHIFT))) + #define UART_1_tx_USBIO_EXIT_SLEEP_PH2 ((uint32)~((uint32)(1u << UART_1_tx_USBIO_SUSPEND_DEL_SHIFT))) + #define UART_1_tx_USBIO_CR1_OFF ((uint32)0xfffffffeu) +#endif + + +/*************************************** +* Registers +***************************************/ +/* Main Port Registers */ +#if defined(UART_1_tx__PC) + /* Port Configuration */ + #define UART_1_tx_PC (* (reg32 *) UART_1_tx__PC) +#endif +/* Pin State */ +#define UART_1_tx_PS (* (reg32 *) UART_1_tx__PS) +/* Data Register */ +#define UART_1_tx_DR (* (reg32 *) UART_1_tx__DR) +/* Input Buffer Disable Override */ +#define UART_1_tx_INP_DIS (* (reg32 *) UART_1_tx__PC2) + +/* Interrupt configuration Registers */ +#define UART_1_tx_INTCFG (* (reg32 *) UART_1_tx__INTCFG) +#define UART_1_tx_INTSTAT (* (reg32 *) UART_1_tx__INTSTAT) + +/* "Interrupt cause" register for Combined Port Interrupt (AllPortInt) in GSRef component */ +#if defined (CYREG_GPIO_INTR_CAUSE) + #define UART_1_tx_INTR_CAUSE (* (reg32 *) CYREG_GPIO_INTR_CAUSE) +#endif + +/* SIO register */ +#if defined(UART_1_tx__SIO) + #define UART_1_tx_SIO_REG (* (reg32 *) UART_1_tx__SIO) +#endif /* (UART_1_tx__SIO_CFG) */ + +/* USBIO registers */ +#if !defined(UART_1_tx__PC) && (CY_PSOC4_4200L) + #define UART_1_tx_USB_POWER_REG (* (reg32 *) CYREG_USBDEVv2_USB_POWER_CTRL) + #define UART_1_tx_CR1_REG (* (reg32 *) CYREG_USBDEVv2_CR1) + #define UART_1_tx_USBIO_CTRL_REG (* (reg32 *) CYREG_USBDEVv2_USB_USBIO_CTRL) +#endif + + +/*************************************** +* The following code is DEPRECATED and +* must not be used in new designs. +***************************************/ +/** +* \addtogroup group_deprecated +* @{ +*/ +#define UART_1_tx_DRIVE_MODE_SHIFT (0x00u) +#define UART_1_tx_DRIVE_MODE_MASK (0x07u << UART_1_tx_DRIVE_MODE_SHIFT) +/** @} deprecated */ + +#endif /* End Pins UART_1_tx_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_tx_PM.c b/cores/asr650x/projects/PSoC4/UART_1_tx_PM.c new file mode 100644 index 00000000..3ed3e2fb --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_tx_PM.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: UART_1_tx.c +* Version 2.20 +* +* Description: +* This file contains APIs to set up the Pins component for low power modes. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "UART_1_tx.h" + +static UART_1_tx_BACKUP_STRUCT UART_1_tx_backup = {0u, 0u, 0u}; + + +/******************************************************************************* +* Function Name: UART_1_tx_Sleep +****************************************************************************//** +* +* \brief Stores the pin configuration and prepares the pin for entering chip +* deep-sleep/hibernate modes. This function applies only to SIO and USBIO pins. +* It should not be called for GPIO or GPIO_OVT pins. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \sideeffect +* For SIO pins, this function configures the pin input threshold to CMOS and +* drive level to Vddio. This is needed for SIO pins when in device +* deep-sleep/hibernate modes. +* +* \funcusage +* \snippet UART_1_tx_SUT.c usage_UART_1_tx_Sleep_Wakeup +*******************************************************************************/ +void UART_1_tx_Sleep(void) +{ + #if defined(UART_1_tx__PC) + UART_1_tx_backup.pcState = UART_1_tx_PC; + #else + #if (CY_PSOC4_4200L) + /* Save the regulator state and put the PHY into suspend mode */ + UART_1_tx_backup.usbState = UART_1_tx_CR1_REG; + UART_1_tx_USB_POWER_REG |= UART_1_tx_USBIO_ENTER_SLEEP; + UART_1_tx_CR1_REG &= UART_1_tx_USBIO_CR1_OFF; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(UART_1_tx__SIO) + UART_1_tx_backup.sioState = UART_1_tx_SIO_REG; + /* SIO requires unregulated output buffer and single ended input buffer */ + UART_1_tx_SIO_REG &= (uint32)(~UART_1_tx_SIO_LPM_MASK); + #endif +} + + +/******************************************************************************* +* Function Name: UART_1_tx_Wakeup +****************************************************************************//** +* +* \brief Restores the pin configuration that was saved during Pin_Sleep(). This +* function applies only to SIO and USBIO pins. It should not be called for +* GPIO or GPIO_OVT pins. +* +* For USBIO pins, the wakeup is only triggered for falling edge interrupts. +* +* Note This function is available in PSoC 4 only. +* +* \return +* None +* +* \funcusage +* Refer to UART_1_tx_Sleep() for an example usage. +*******************************************************************************/ +void UART_1_tx_Wakeup(void) +{ + #if defined(UART_1_tx__PC) + UART_1_tx_PC = UART_1_tx_backup.pcState; + #else + #if (CY_PSOC4_4200L) + /* Restore the regulator state and come out of suspend mode */ + UART_1_tx_USB_POWER_REG &= UART_1_tx_USBIO_EXIT_SLEEP_PH1; + UART_1_tx_CR1_REG = UART_1_tx_backup.usbState; + UART_1_tx_USB_POWER_REG &= UART_1_tx_USBIO_EXIT_SLEEP_PH2; + #endif + #endif + #if defined(CYIPBLOCK_m0s8ioss_VERSION) && defined(UART_1_tx__SIO) + UART_1_tx_SIO_REG = UART_1_tx_backup.sioState; + #endif +} + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/UART_1_tx_aliases.h b/cores/asr650x/projects/PSoC4/UART_1_tx_aliases.h new file mode 100644 index 00000000..fb9f5f1e --- /dev/null +++ b/cores/asr650x/projects/PSoC4/UART_1_tx_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: UART_1_tx.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_UART_1_tx_ALIASES_H) /* Pins UART_1_tx_ALIASES_H */ +#define CY_PINS_UART_1_tx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" + + +/*************************************** +* Constants +***************************************/ +#define UART_1_tx_0 (UART_1_tx__0__PC) +#define UART_1_tx_0_PS (UART_1_tx__0__PS) +#define UART_1_tx_0_PC (UART_1_tx__0__PC) +#define UART_1_tx_0_DR (UART_1_tx__0__DR) +#define UART_1_tx_0_SHIFT (UART_1_tx__0__SHIFT) +#define UART_1_tx_0_INTR ((uint16)((uint16)0x0003u << (UART_1_tx__0__SHIFT*2u))) + +#define UART_1_tx_INTR_ALL ((uint16)(UART_1_tx_0_INTR)) + + +#endif /* End Pins UART_1_tx_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/cm0plusgcc.ld b/cores/asr650x/projects/PSoC4/cm0plusgcc.ld new file mode 100644 index 00000000..58336647 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cm0plusgcc.ld @@ -0,0 +1,480 @@ +/* Linker script for ARM M-profile Simulator + * + * Version: Sourcery G++ Lite 2010q1-188 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(Reset) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + + +/* Code sharing support */ +INCLUDE cycodeshareexport.ld +INCLUDE cycodeshareimport.ld + + +MEMORY +{ + rom (rx) : ORIGIN = 0x0, LENGTH = 131072 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16384 +} + + +CY_APPL_ORIGIN = 0; +CY_FLASH_ROW_SIZE = 256; +CY_APPL_NUM = 1; +CY_APPL_MAX = 1; +CY_METADATA_SIZE = 64; +CY_APPL_LOADABLE = 1; +CY_CHECKSUM_EXCLUDE_SIZE = ALIGN(0, CY_FLASH_ROW_SIZE); +CY_APP_FOR_STACK_AND_COPIER = 0; + + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(Reset) + +/* Bring in the interrupt routines & vector */ +EXTERN(main) + +/* Bring in the romvector */ +EXTERN(RomVectors) + +/* Bring in the ramvector */ +EXTERN(CyRamVectors) + +/* Bring in the meta data */ +EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader) +EXTERN(cy_meta_flashprotect cy_metadata cy_meta_chipprotect) +EXTERN(cy_heap) + +/* Provide fall-back values */ +PROVIDE(__cy_heap_start = _end); +PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16); + +/* Set stack top to end of RAM, and stack limit move down by + * size of .stack section. + */ +PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram)); + +PROVIDE(__cy_heap_end = __cy_stack - 0x0800); + + +SECTIONS +{ + /* The bootloader location */ + .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom + + /* Calculate where the loadables should start */ + appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE); + appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE); + appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start; + + + cy_project_type_bootloader = (appl_start == 0) ? 1 : 0; + cy_project_type_app_for_stack_and_copier = (CY_APP_FOR_STACK_AND_COPIER == 1) ? 1 : 0; + + + .text appl_start : + { + CREATE_OBJECT_SYMBOLS + PROVIDE(__cy_interrupt_vector = RomVectors); + + KEEP(*(.romvectors)) + + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cy_interrupt_vector, "No interrupt vector"); + + ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location"); + + PROVIDE(__cy_reset = Reset); + + *(.text.Reset) + + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cy_reset, "No reset code"); + + *(.psocinit) + + /* The first 0x100 Flash bytes become unavailable right after remapping of the vector table to RAM. */ + . = MAX(., 0x100); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */ + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + } >rom + + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + } >rom + + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) + } >rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + + __exidx_end = .; + + + .rodata : ALIGN (4) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cy_regions = .; + LONG (__cy_region_init_ram) + LONG (__cy_region_start_data) + LONG (__cy_region_init_size_ram) + LONG (__cy_region_zero_size_ram) + __cy_regions_end = .; + + . = ALIGN (8); + _etext = .; + } >rom + + + /*************************************************************************** + * Checksum Exclude Section for non-bootloadable projects. See below. + ***************************************************************************/ + + + + .ramvectors (NOLOAD) : ALIGN(8) + { + __cy_region_start_ram = .; + KEEP(*(.ramvectors)) + } + + + .btldr_run (NOLOAD) : ALIGN(8) + { + KEEP(*(.bootloaderruntype)) + } + + + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } + + .data : ALIGN(8) + { + __cy_region_start_data = .; + + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN (8); + *(.ram) + _edata = .; + } >ram AT>rom + + .bss : ALIGN(8) + { + PROVIDE(__bss_start__ = .); + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + *(.ram.b) + _end = .; + __end = .; + } >ram AT>rom + + + + PROVIDE(end = .); + PROVIDE(__bss_end__ = .); + + __cy_region_init_ram = LOADADDR (.data); + __cy_region_init_size_ram = _edata - ADDR (.data); + __cy_region_zero_size_ram = _end - _edata; + + /* The .stack and .heap sections don't contain any symbols. + * They are only used for linker to calculate RAM utilization. + */ + .heap (NOLOAD) : + { + . = _end; + . += 0x1000; + __cy_heap_limit = .; + } >ram + + .stack (__cy_stack - 0x0800) (NOLOAD) : + { + __cy_stack_limit = .; + . += 0x0800; + } >ram + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack") + + + /*************************************************************************** + * Checksum Exclude Section + *************************************************************************** + * + * For the normal and bootloader projects this section is placed at any + * place. For the Bootloadable applications, it is placed at the specific + * address. + * + * Case # 1. Bootloadable application + * + * _______________________________ + * | Metadata (BTLDBL) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | | + * | | + * | BTLDBL | + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDR | + * |_______________________________| + * + * + * Case # 2. Bootloadable application for Dual-Application Bootloader + * + * _______________________________ + * | Metadata (BTLDBL # 1) | + * |-------------------------------| + * | Metadata (BTLDBL # 2) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL # 2) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDBL # 2 | + * |_______________________________|____BTLDBL # 2 Start address___ + * | Checksum Exclude (BTLDBL # 1) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDBL # 1 | + * | | + * |-------------------------------| + * | BTLDR | + * |_______________________________| + * + * + * Case # 3. OTA updatable stack + * + * _______________________________ + * | Metadata (BTLDBL # 1) | + * |-------------------------------| + * | Metadata (BTLDBL # 2) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL # 2) | + * |-------------------------------| + * | | + * | | + * | | + * | | + * |-------------------------------| + * |_______________________________|____Temporary location for BTLDBL # 1 update(Former BTLDBL # 2 start)___ + * | | + * | BTLDBL # 2 | + * | | + * |-------------------------------| + * | Checksum Exclude (BTLDBL # 1) | + * |-------------------------------| + * | | + * | BTLDBL # 1 | + * | | + * |-------------------------------| + * | BTLDR | + * |_______________________________| + */ + .cy_checksum_exclude ((LENGTH(rom) - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE): { KEEP(*(.cy_checksum_exclude)) } + + + /* Bootloadable applications only: verify that size of the data in the section is within the specified limit. */ + cy_checksum_exclude_size = (CY_APPL_LOADABLE == 1) ? SIZEOF(.cy_checksum_exclude) : 0; + ASSERT(cy_checksum_exclude_size <= CY_CHECKSUM_EXCLUDE_SIZE, "CY_BOOT: Section .cy_checksum_exclude size exceedes specified limit.") + + + /*************************************************************************** + * Bootloader Metadata Section + *************************************************************************** + * + * Case # 1. Bootloader project + * + * _______________________________ + * | BTLDR Metadata | + * |-------------------------------| + * | | + * | | + * | | + * | | + * |-------------------------------| + * | | + * | Bootloader (BTLDR) | + * |_______________________________| + * + * + * Case # 2. Code sharing + * + * _______________________________ + * | SP/L Metadata | CY_APPL_METADATA_SLOT_NUM == 0 + * |-------------------------------| + * | App for SP+L Metadata | CY_APPL_METADATA_SLOT_NUM == 1 + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | App for SP+L | ((CYDEV_IS_IMPORTING_CODE == 1) && (CY_FIRST_AVAILABLE_META_ROW == 2)) + * | | + * |-------------------------------| + * | | + * | Stack Project (SP) | (CYDEV_IS_EXPORTING_CODE == 1) + * | | + * |-------------------------------| + * | | + * | Launcher (L) | + * |_______________________________| + * + * Notes: + * - App for SP+L start just after the SP + * - SP treated as a single bootloadable application + * - App for SP+L treats SP+L as a bootloader + */ + + /* For the bootloader project, place bootloader metadata at the last flash row, otherwise place beyond map */ + cyloadermeta_start = (cy_project_type_bootloader || cy_project_type_app_for_stack_and_copier) ? + (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000; + .cyloadermeta (cyloadermeta_start) : + { + KEEP(*(.cyloadermeta)) + } : NONE + + + cyloadablemeta_start = (cy_project_type_app_for_stack_and_copier) ? + (LENGTH(rom) - CY_FLASH_ROW_SIZE - CY_METADATA_SIZE) : (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE); + .cyloadablemeta (cyloadablemeta_start) : + { + KEEP(*(.cyloadablemeta)) + } >rom + + .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE + .cychipprotect 0x90600000 : { KEEP(*(.cychipprotect)) } :NONE + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} + diff --git a/cores/asr650x/projects/PSoC4/cmsis_armcc.h b/cores/asr650x/projects/PSoC4/cmsis_armcc.h new file mode 100644 index 00000000..234ea5e0 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cmsis_armcc.h @@ -0,0 +1,791 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V5.00 + * @date 27. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if (defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/cores/asr650x/projects/PSoC4/cmsis_compiler.h b/cores/asr650x/projects/PSoC4/cmsis_compiler.h new file mode 100644 index 00000000..658bd964 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cmsis_compiler.h @@ -0,0 +1,210 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V5.00 + * @date 09. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * ARM Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #include + + #ifndef __NO_RETURN + #define __NO_RETURN __noreturn + #endif + #ifndef __USED + #define __USED __root + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + __packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED __packed + #endif + + +/* + * TI ARM Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/cores/asr650x/projects/PSoC4/cmsis_gcc.h b/cores/asr650x/projects/PSoC4/cmsis_gcc.h new file mode 100644 index 00000000..1b85b910 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cmsis_gcc.h @@ -0,0 +1,1894 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V5.00 + * @date 28. October 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef _WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1U)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1U)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1U)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1U)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +//{ +// __ASM volatile ("nop"); +//} +#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +//{ +// __ASM volatile ("wfi"); +//} +#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +//{ +// __ASM volatile ("wfe"); +//} +#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +//{ +// __ASM volatile ("sev"); +//} +#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/cores/asr650x/projects/PSoC4/core_cm0plus.h b/cores/asr650x/projects/PSoC4/core_cm0plus.h new file mode 100644 index 00000000..854b284e --- /dev/null +++ b/cores/asr650x/projects/PSoC4/core_cm0plus.h @@ -0,0 +1,969 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.00 + * @date 13. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + #define NVIC_USER_IRQ_OFFSET 16 + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} +#endif + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/cores/asr650x/projects/PSoC4/core_cm0plus_psoc4.h b/cores/asr650x/projects/PSoC4/core_cm0plus_psoc4.h new file mode 100644 index 00000000..214a6ef9 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/core_cm0plus_psoc4.h @@ -0,0 +1,46 @@ +/***************************************************************************//** +* \file core_cm0plus_psoc4.h +* \version 5.70 +* +* \brief Provides important type information for the PSOC4 device family. +* This includes types necessary for core_cm0.h. +* +* \note Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_BOOT_CORE_CM0_PSOC4_H) +#define CY_BOOT_CORE_CM0_PSOC4_H + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1 /*!< 15 Cortex-M0 System Tick Interrupt */ +/****** PSOC4 Peripheral Interrupt Numbers *******************************************************/ + /* Not relevant. All peripheral interrupts are defined by the user */ +} IRQn_Type; + +#define __CHECK_DEVICE_DEFINES + +#define __CM0PLUS_REV 0x0000 +#define __VTOR_PRESENT 0U +#define __MPU_PRESENT 1U +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + +#include + +#endif /* CY_BOOT_CORE_CM0_PSOC4_H */ diff --git a/cores/asr650x/projects/PSoC4/core_cmFunc.h b/cores/asr650x/projects/PSoC4/core_cmFunc.h new file mode 100644 index 00000000..652a48af --- /dev/null +++ b/cores/asr650x/projects/PSoC4/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/cores/asr650x/projects/PSoC4/core_cmInstr.h b/cores/asr650x/projects/PSoC4/core_cmInstr.h new file mode 100644 index 00000000..f474b0e6 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/cores/asr650x/projects/PSoC4/cyPm.c b/cores/asr650x/projects/PSoC4/cyPm.c new file mode 100644 index 00000000..3181e33a --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cyPm.c @@ -0,0 +1,435 @@ +/***************************************************************************//** +* \file cyPm.c +* \version 5.70 +* +* \brief Provides an API for the power management. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2011-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cyPm.h" +#include "CyLib.h" +#include "CyFlash.h" + + +/******************************************************************************* +* Function Name: CySysPmSleep +****************************************************************************//** +* +* Puts the part into the Sleep state. This is a CPU-centric power mode. +* It means that the CPU has indicated that it is in the sleep mode and +* its main clock can be removed. It is identical to Active from a peripheral +* point of view. Any enabled interrupts can cause wakeup from the Sleep mode. +* +*******************************************************************************/ +void CySysPmSleep(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* CPU enters Sleep mode upon execution of WFI */ + CY_PM_CPU_SCR_REG &= (uint32) (~CY_PM_CPU_SCR_SLEEPDEEP); + + /* Sleep and wait for interrupt */ + CY_PM_WFI; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySysPmDeepSleep +****************************************************************************//** +* +* Puts the part into the Deep Sleep state. If the firmware attempts to enter +* this mode before the system is ready (that is, when +* PWR_CONTROL.LPM_READY = 0), then the device will go into the Sleep mode +* instead and automatically enter the originally intended mode when the +* holdoff expires. +* +* The wakeup occurs when an interrupt is received from a DeepSleep or +* Hibernate peripheral. For more details, see a corresponding +* peripheral's datasheet. +* +*******************************************************************************/ +void CySysPmDeepSleep(void) +{ + uint8 interruptState; + #if(CY_IP_SRSSV2) + volatile uint32 clkSelectReg; + #endif /* (CY_IP_SRSSV2) */ + + #if(CY_IP_ECO_SRSSLT) + volatile uint32 pllResoreFlag = 0u; + #endif /* (CY_IP_ECO_SRSSLT) */ + + interruptState = CyEnterCriticalSection(); + + #if(CY_IP_ECO_SRSSLT) + if(0u != (CY_SYS_ECO_CLK_SELECT_REG & CY_SYS_ECO_CLK_SELECT_ECO_PLL_MASK)) + { + pllResoreFlag = 1u; + + /* Set default state = IMO for HFCLK_SEL bit mask */ + CY_SYS_CLK_SELECT_REG &= (uint32)(~CY_SYS_CLK_SELECT_DIRECT_SEL_MASK); + } + #endif /* (CY_IP_ECO_SRSSLT) */ + + #if(CY_IP_SRSSV2) + /* Device enters DeepSleep mode when CPU asserts SLEEPDEEP signal */ + CY_PM_PWR_CONTROL_REG &= (uint32) (~CY_PM_PWR_CONTROL_HIBERNATE); + #endif /* (CY_IP_SRSSV2) */ + + #if (CY_IP_CPUSS && CY_IP_SRSSV2) + CY_PM_CPUSS_CONFIG_REG |= CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS; + #endif /* (CY_IP_CPUSS && CY_IP_SRSSV2) */ + + /* Adjust delay to wait for references to settle on wakeup from Deep Sleep */ + CY_PM_PWR_KEY_DELAY_REG = CY_SFLASH_DPSLP_KEY_DELAY_REG; + + /* CPU enters DeepSleep/Hibernate mode upon execution of WFI */ + CY_PM_CPU_SCR_REG |= CY_PM_CPU_SCR_SLEEPDEEP; + + #if(CY_IP_SRSSV2) + /* Preserve system clock configuration and + * reduce sysclk to <=12 MHz (Cypress ID #158710, #179888). + */ + clkSelectReg = CY_SYS_CLK_SELECT_REG; + CySysClkWriteSysclkDiv(CY_SYS_CLK_SYSCLK_DIV4); + #endif /* (CY_IP_SRSSV2) */ + + /* Sleep and wait for interrupt */ + CY_PM_WFI; + + #if(CY_IP_SRSSV2) + /* Restore system clock configuration */ + CY_SYS_CLK_SELECT_REG = clkSelectReg; + #endif /* (CY_IP_SRSSV2) */ + + #if (CY_IP_CPUSS && CY_IP_SRSSV2) + CY_PM_CPUSS_CONFIG_REG &= (uint32) (~CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS); + #endif /* (CY_IP_CPUSS && CY_IP_SRSSV2) */ + + #if(CY_IP_ECO_SRSSLT) + if(0u != pllResoreFlag) + { + CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_PLL0); + } + #endif /* (CY_IP_ECO_SRSSLT) */ + + CyExitCriticalSection(interruptState); +} + + +#if(CY_IP_SRSSV2) + + /******************************************************************************* + * Function Name: CySysPmHibernate + ****************************************************************************//** + * + * Puts the part into the Hibernate state. Only SRAM and UDBs are retained; + * most internal supplies are off. Wakeup is possible from a pin or a hibernate + * comparator only. + * + * It is expected that the firmware has already frozen the IO-Cells using + * CySysPmFreezeIo() function before the call to this function. If this is + * omitted, the IO-cells will be frozen in the same way as they are + * in the Active to Deep Sleep transition, but will lose their state on wake up + * (because of the reset occurring at that time). + * + * Because all the CPU state is lost, the CPU will start up at the reset vector. + * To save the firmware state through the Hibernate low power mode, a + * corresponding variable should be defined with CY_NOINIT attribute. It + * prevents data from being initialized to zero on startup. The interrupt + * cause of the hibernate peripheral is retained, such that it can be either + * read by the firmware or cause an interrupt after the firmware has booted and + * enabled the corresponding interrupt. To distinguish the wakeup from + * the Hibernate mode and the general Reset event, the + * \ref CySysPmGetResetReason() function could be used. + * + *******************************************************************************/ + void CySysPmHibernate(void) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if (CY_IP_HOBTO_DEVICE) + /* Disable input buffers for all ports */ + CySysPmHibPinsDisableInputBuf(); + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Device enters Hibernate mode when CPU asserts SLEEPDEEP signal */ + CY_PM_PWR_CONTROL_REG |= CY_PM_PWR_CONTROL_HIBERNATE; + + /* Adjust delay to wait for references to settle on wakeup from hibernate */ + CY_PM_PWR_KEY_DELAY_REG = CY_SFLASH_HIB_KEY_DELAY_REG; + + /* CPU enters DeepSleep/Hibernate mode upon execution of WFI */ + CY_PM_CPU_SCR_REG |= CY_PM_CPU_SCR_SLEEPDEEP; + + /* Save token that will retain through a STOP/WAKEUP sequence + * thus could be used by CySysPmGetResetReason() to differentiate + * WAKEUP from a general RESET event. + */ + CY_PM_PWR_STOP_REG = (CY_PM_PWR_STOP_REG & (uint32)(~CY_PM_PWR_STOP_TOKEN_MASK)) | CY_PM_PWR_STOP_TOKEN_HIB; + + /* Sleep and wait for interrupt. Wakeup from Hibernate is performed + * through RESET state, causing a normal Boot procedure to occur. + * The WFI instruction doesn't put the core to sleep if its wake condition + * is true when the instruction is executed. + */ + CY_PM_WFI; + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysPmStop + ****************************************************************************//** + * + * Puts the part into the Stop state. All internal supplies are off; + * no state is retained. + * + * Wakeup from Stop is performed by toggling the wakeup pin, causing + * a normal boot procedure to occur. To configure the wakeup pin, + * the Digital Input Pin component should be placed on the schematic, + * assigned to the wakeup pin, and resistively pulled up or down to the inverse + * state of the wakeup polarity. To distinguish the wakeup from the Stop mode + * and the general Reset event, \ref CySysPmGetResetReason() function could be + * used. The wakeup pin is active low by default. The wakeup pin polarity + * could be changed with the \ref CySysPmSetWakeupPolarity() function. + * + * This function freezes IO cells implicitly. It is not possible to enter + * the STOP mode before freezing the IO cells. The IO cells remain frozen after + * awake from the Stop mode until the firmware unfreezes them after booting + * explicitly with \ref CySysPmUnfreezeIo() function call. + * + *******************************************************************************/ + void CySysPmStop(void) + { + (void) CyEnterCriticalSection(); + + /* Update token to indicate Stop mode transition. Preserve only polarity. */ + CY_PM_PWR_STOP_REG = (CY_PM_PWR_STOP_REG & CY_PM_PWR_STOP_POLARITY) | CY_PM_PWR_STOP_TOKEN_STOP; + + /* Freeze IO-Cells to save IO-Cell state */ + CySysPmFreezeIo(); + + /* Initiates transition to Stop state */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_REG | CY_PM_PWR_STOP_STOP; + + /* Depending on the clock frequency and internal timing delays, + * the final AHB transaction may or may not complete. To guard against + * accidentally executing an unintended instruction, it is recommended + * to add 2 NOP cycles after the final write to the STOP register. + */ + CY_NOP; + CY_NOP; + + /* Should never get to this WFI instruction */ + CY_PM_WFI; + + /* Wakeup from Stop is performed by toggling of Wakeup pin, + * causing a normal Boot procedure to occur. No need to exit + * from the critical section. + */ + } + + + /******************************************************************************* + * Function Name: CySysPmSetWakeupPolarity + ****************************************************************************//** + * + * Wake up from the stop mode is performed by toggling the wakeup pin, + * causing a normal boot procedure to occur. This function assigns + * the wakeup pin active level. Setting the wakeup pin to this level will cause + * the wakeup from stop mode. The wakeup pin is active low by default. + * + * \param polarity + * - \ref CY_PM_STOP_WAKEUP_ACTIVE_LOW Logical zero will wakeup the chip + * - \ref CY_PM_STOP_WAKEUP_ACTIVE_HIGH Logical one will wakeup the chip + * + *******************************************************************************/ + void CySysPmSetWakeupPolarity(uint32 polarity) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_PM_PWR_STOP_REG = (CY_PM_STOP_WAKEUP_ACTIVE_LOW != polarity) ? + (CY_PM_PWR_STOP_REG | CY_PM_PWR_STOP_POLARITY) : + (CY_PM_PWR_STOP_REG & (uint32) (~CY_PM_PWR_STOP_POLARITY)); + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysPmGetResetReason + ****************************************************************************//** + * + * Retrieves the last reset reason - transition from OFF/XRES/STOP/HIBERNATE to + * the RESET state. Note that waking up from STOP using XRES will be perceived + * as a general RESET. + * + * \return CY_PM_RESET_REASON_UNKN Unknown reset reason. + * \return CY_PM_RESET_REASON_XRES Transition from OFF/XRES to RESET + * \return CY_PM_RESET_REASON_WAKEUP_HIB Transition/wakeup from HIBERNATE to RESET + * \return CY_PM_RESET_REASON_WAKEUP_STOP Transition/wakeup from STOP to RESET + * + *******************************************************************************/ + uint32 CySysPmGetResetReason(void) + { + uint32 reason = CY_PM_RESET_REASON_UNKN; + + switch(CY_PM_PWR_STOP_REG & CY_PM_PWR_STOP_TOKEN_MASK) + { + /* Power up, XRES */ + case CY_PM_PWR_STOP_TOKEN_XRES: + reason = CY_PM_RESET_REASON_XRES; + break; + + /* Wakeup from Hibernate */ + case CY_PM_PWR_STOP_TOKEN_HIB: + reason = CY_PM_RESET_REASON_WAKEUP_HIB; + break; + + /* Wakeup from Stop (through WAKEUP pin assert) */ + case CY_PM_PWR_STOP_TOKEN_STOP: + reason = CY_PM_RESET_REASON_WAKEUP_STOP; + break; + + /* Unknown reason */ + default: + break; + } + + return (reason); + } + + + /******************************************************************************* + * Function Name: CySysPmFreezeIo + ****************************************************************************//** + * + * Freezes IO-Cells directly to save the IO-Cell state on wake up from the + * Hibernate or Stop state. It is not required to call this function before + * entering the Stop mode, since \ref CySysPmStop() function freezes IO-Cells + * implicitly. + * + * This API is not available for PSoC 4000 family of devices. + * + *******************************************************************************/ + void CySysPmFreezeIo(void) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Check FREEZE state to avoid recurrent IO-Cells freeze attempt, + * since the second call to this function will cause accidental switch + * to the STOP mode (the system will enter STOP mode immediately after + * writing to STOP bit since both UNLOCK and FREEZE have been set correctly + * in a previous call to this function). + */ + if (0u == (CY_PM_PWR_STOP_REG & CY_PM_PWR_STOP_FREEZE)) + { + /* Preserve last reset reason and disable overrides the next freeze command by peripherals */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_STOP | CY_PM_PWR_STOP_FREEZE | CY_PM_PWR_STOP_UNLOCK | + (CY_PM_PWR_STOP_REG & (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY)); + + /* If reading after writing, read this register three times to delay + * enough time for internal settling. + */ + (void) CY_PM_PWR_STOP_REG; + (void) CY_PM_PWR_STOP_REG; + + /* Second write causes the freeze of IO-Cells to save IO-Cell state */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_REG; + } + + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CySysPmUnfreezeIo + ****************************************************************************//** + * + * The IO-Cells remain frozen after awake from Hibernate or Stop mode until + * the firmware unfreezes them after booting. The call of this function + * unfreezes IO-Cells explicitly. + * + * If the firmware intent is to retain the data value on the port, then the + * value must be read and re-written to the data register before calling this + * API. Furthermore, the drive mode must be re-programmed. If this is not done, + * the pin state will change to default state the moment the freeze is removed. + * + * This API is not available for PSoC 4000 family of devices. + * + *******************************************************************************/ + void CySysPmUnfreezeIo(void) + { + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Preserve last reset reason and wakeup polarity. Then, unfreeze I/O: + * write PWR_STOP.FREEZE=0, .UNLOCK=0x3A, .STOP=0, .TOKEN + */ + CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_UNLOCK | + (CY_PM_PWR_STOP_REG & (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY)); + + /* If reading after writing, read this register three times to delay + * enough time for internal settling. + */ + (void) CY_PM_PWR_STOP_REG; + (void) CY_PM_PWR_STOP_REG; + + /* Lock STOP mode: write PWR_STOP.FREEZE=0, UNLOCK=0x00, STOP=0, .TOKEN */ + CY_PM_PWR_STOP_REG &= (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY); + + CyExitCriticalSection(interruptState); + } + +#else + + /******************************************************************************* + * Function Name: CySysPmSetWakeupHoldoff + ****************************************************************************//** + * + * Sets the Deep Sleep wakeup time by scaling the hold-off to the HFCLK + * frequency. + * + * This function must be called before increasing HFCLK clock frequency. It can + * optionally be called after lowering HFCLK clock frequency in order to improve + * Deep Sleep wakeup time. + * + * It is functionally acceptable to leave the default hold-off setting, but + * Deep Sleep wakeup time may exceed the specification. + * + * This function is applicable only for the 4000 device family. + * + * \param hfclkFrequencyMhz The HFCLK frequency in MHz. + * + *******************************************************************************/ + void CySysPmSetWakeupHoldoff(uint32 hfclkFrequencyMhz) + { + CY_PM_PWR_KEY_DELAY_REG = ((((uint32)(CY_PM_PWR_KEY_DELAY_REG_DEFAULT << 16u) / + CY_PM_PWR_KEY_DELAY_FREQ_DEFAULT) * hfclkFrequencyMhz) >> 16u) + 1u; + } + +#endif /* (CY_IP_SRSSV2) */ + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/cyPm.h b/cores/asr650x/projects/PSoC4/cyPm.h new file mode 100644 index 00000000..7b0641ad --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cyPm.h @@ -0,0 +1,302 @@ +/***************************************************************************//** +* \file cyPm.h +* \version 5.70 +* +* \brief Provides the function definitions for the power management API. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2011-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPM_H) +#define CY_BOOT_CYPM_H + +#include "cytypes.h" +#include "cypins.h" + + +/** +* \addtogroup group_power_management Power Management API +* @{ + +\brief PSoC 4 devices support the following power modes (in order of high to low power consumption): Active, Sleep, +Deep Sleep, Hibernate, and Stop. Active, Sleep and Deep-Sleep are standard ARM defined power modes, supported by the +ARM CPUs. Hibernate/Stop are even lower power modes that are entered from firmware just like Deep-Sleep, but on wakeup +the CPU (and all peripherals) goes through a full reset. + +There is a full range of power modes supported by PSoC devices to control power consumption and the amount of available +resources. See the following table for the supported power modes. + +Mode | PSoC 4000 | Rest Devices | +----------- | ---------------------- | ---------------------- | +Active | Y | Y | +Sleep | Y | Y | +Deep Sleep | Y | Y | +Hibernate | Y | Y | +Stop | | Y | + +For the ARM-based devices (PSoC 4), an interrupt is required for the CPU to wake up. The Power Management implementation +assumes that wakeup time is configured with a separate component (component-based wakeup time configuration) for an +interrupt to be issued on terminal count. + +All pending interrupts should be cleared before the device is put into low power mode, even if they are masked. + +The Power Management API is provided in the CyPm.c and CyPm.h files. + + +\section group_power_management_implementation Implementation +For PSoC 4100, PSoC 4000U and PSoC 4200 devices, the software should set EXT_VCCD bit in the PWR_CONTROL register when +Vccd is shorted to Vddd on the board. This impacts the chip internal state transitions where it is necessary to know +whether Vccd is connected or floating to achieve minimum current in low power modes. Note Setting this bit turns off +the active regulator and will lead to a system reset unless both Vddd and Vccd pins are supplied externally. Refer to +the device TRM for more information. + +It is safe to call PM APIs from the ISR. The wakeup conditions for Sleep and DeepSleep low power modes are illustrated +in the following table. + +Interrupts State | Condition | Wakeup | ISR Execution | +------------------|---------------------------------|-----------|------------------ | +Unmasked | IRQ priority > current level | Yes | Yes | +Unmasked | IRQ priority 鈮 current level | No | No | +Masked | IRQ priority > current level | Yes | No | +Masked | IRQ priority 鈮 current level | No | No | + + +\section group_power_management_clocks Clock Configuration +For PSoC 4100 BLE and PSoC 4200 BLE devices, the HFCLK source should be set to IMO before switching the device into low +power mode. The IMO should be enabled (by calling CySysClkImoStart(), if it is not) and HFCLK source should be changed +to IMO by calling CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_IMO). + +If the System clock frequency is increased by switching to the IMO, the CySysFlashSetWaitCycles() function with an +appropriate parameter should be called beforehand. Also, it can optionally be called after lowering the System clock +frequency in order to improve CPU performance. See CySysFlashSetWaitCycles() description for the details. + + + + + +*/ +void CySysPmSleep(void); +void CySysPmDeepSleep(void); + +#if(CY_IP_SRSSV2) + void CySysPmHibernate(void); + void CySysPmFreezeIo(void); + void CySysPmUnfreezeIo(void); + uint32 CySysPmGetResetReason(void); + void CySysPmStop(void); + void CySysPmSetWakeupPolarity(uint32 polarity); +#else + void CySysPmSetWakeupHoldoff(uint32 hfclkFrequencyMhz); +#endif /* (CY_IP_SRSSV2) */ + +/** @} group_power_management */ + + +/******************************************************************************* +* The ARM compilers have the __wfi() intrinsic that inserts a WFI instruction +* into the instruction stream generated by the compiler. The GCC compiler has to +* execute assembly language instruction. +*******************************************************************************/ +#if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */ + #define CY_PM_WFI __wfi() +#else /* ASM for GCC & IAR */ + #define CY_PM_WFI __asm volatile ("WFI \n") +#endif /* __ARMCC_VERSION */ + +#if(CY_IP_SRSSV2) + + /* CySysPmSetWakeupPolarity() */ + #define CY_PM_STOP_WAKEUP_ACTIVE_LOW ((uint32)(0x0u)) /**< Logical zero will wakeup the chip */ + #define CY_PM_STOP_WAKEUP_ACTIVE_HIGH ((uint32)(0x1u)) /**< Logical one will wakeup the chip */ + #define CY_PM_STOP_WAKEUP_POLARITY (CY_PM_STOP_WAKEUP_ACTIVE_LOW) + + /* CySysPmGetResetReason() */ + #define CY_PM_RESET_REASON_UNKN (0u) /**< Unknown reset reason. */ + #define CY_PM_RESET_REASON_XRES (1u) /**< Transition from OFF/XRES to RESET */ + #define CY_PM_RESET_REASON_WAKEUP_HIB (2u) /**< Transition/wakeup from HIBERNATE to RESET */ + #define CY_PM_RESET_REASON_WAKEUP_STOP (3u) /**< Transition/wakeup from STOP to RESET */ + +#endif /* (CY_IP_SRSSV2) */ + + +/*************************************** +* Registers +***************************************/ + +/* Power Mode Control */ +#define CY_PM_PWR_CONTROL_REG (*(reg32 *) CYREG_PWR_CONTROL) +#define CY_PM_PWR_CONTROL_PTR ( (reg32 *) CYREG_PWR_CONTROL) + +/* CPU System Control Register */ +#if (CY_IP_CPUSS_CM0) + #define CY_PM_CPU_SCR_REG (*(reg32 *) CYREG_CM0_SCR) + #define CY_PM_CPU_SCR_PTR ( (reg32 *) CYREG_CM0_SCR) +#else /* CY_IP_CPUSS_CM0PLUS */ + #define CY_PM_CPU_SCR_REG (*(reg32 *) CYREG_CM0P_SCR) + #define CY_PM_CPU_SCR_PTR ( (reg32 *) CYREG_CM0P_SCR) +#endif /* (CY_IP_CPUSS_CM0) */ + +/* Power System Key & Delay Register */ +#define CY_PM_PWR_KEY_DELAY_REG (*(reg32 *) CYREG_PWR_KEY_DELAY) +#define CY_PM_PWR_KEY_DELAY_PTR ( (reg32 *) CYREG_PWR_KEY_DELAY) + + +#if(CY_IP_SRSSV2) + /* Hibernate wakeup value for PWR_KEY_DELAY */ + #define CY_SFLASH_HIB_KEY_DELAY_REG (*(reg16 *) CYREG_SFLASH_HIB_KEY_DELAY) + #define CY_SFLASH_HIB_KEY_DELAY_PTR ( (reg16 *) CYREG_SFLASH_HIB_KEY_DELAY) +#endif /* (CY_IP_SRSSV2) */ + +/* Deep Sleep wakeup value for PWR_KEY_DELAY */ +#define CY_SFLASH_DPSLP_KEY_DELAY_REG (*(reg16 *) CYREG_SFLASH_DPSLP_KEY_DELAY) +#define CY_SFLASH_DPSLP_KEY_DELAY_PTR ( (reg16 *) CYREG_SFLASH_DPSLP_KEY_DELAY) + +/* Power Stop Mode Register */ +#if(CY_IP_SRSSV2) + #define CY_PM_PWR_STOP_REG (*(reg32 *) CYREG_PWR_STOP) + #define CY_PM_PWR_STOP_PTR ( (reg32 *) CYREG_PWR_STOP) +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + /* CPU Subsystem Configuration */ + #define CY_PM_CPUSS_CONFIG_REG (*(reg32 *) CYREG_CPUSS_CONFIG) + #define CY_PM_CPUSS_CONFIG_PTR ( (reg32 *) CYREG_CPUSS_CONFIG) +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) */ + + +/*************************************** +* Register Constants +***************************************/ + +/* CM0 System Control Register Constants */ +#define CY_PM_CPU_SCR_SLEEPDEEP ((uint32)(0x04u)) + +#if(CY_IP_SRSSV2) + /* Power Mode Control Constants */ + #define CY_PM_PWR_CONTROL_HIBERNATE (0x80000000u) + + /* Power Mode Stop Constants */ + #define CY_PM_PWR_STOP_POLARITY_SHIFT (16u) + #define CY_PM_PWR_STOP_POLARITY ((uint32)((uint32)1u << CY_PM_PWR_STOP_POLARITY_SHIFT)) + #define CY_PM_PWR_STOP_FREEZE_SHIFT (17u) + #define CY_PM_PWR_STOP_FREEZE ((uint32)((uint32)1u << CY_PM_PWR_STOP_FREEZE_SHIFT)) + #define CY_PM_PWR_STOP_UNLOCK_SHIFT (8u) + #define CY_PM_PWR_STOP_UNLOCK_MASK ((uint32)((uint32)0xFFu << CY_PM_PWR_STOP_UNLOCK_SHIFT)) + #define CY_PM_PWR_STOP_UNLOCK ((uint32)((uint32)0x3Au << CY_PM_PWR_STOP_UNLOCK_SHIFT)) + #define CY_PM_PWR_STOP_STOP_SHIFT (31u) + #define CY_PM_PWR_STOP_STOP ((uint32)((uint32)1u << CY_PM_PWR_STOP_STOP_SHIFT)) + #define CY_PM_PWR_STOP_TOKEN_MASK ((uint32)(0xFFu)) + #define CY_PM_PWR_STOP_TOKEN_XRES ((uint32)(0x00u)) + #define CY_PM_PWR_STOP_TOKEN_HIB ((uint32)(0xF1u)) + #define CY_PM_PWR_STOP_TOKEN_STOP ((uint32)(0xF2u)) +#else + #define CY_PM_PWR_KEY_DELAY_REG_DEFAULT ((uint32) 248u) + #define CY_PM_PWR_KEY_DELAY_FREQ_DEFAULT (48u) +#endif /* (CY_IP_SRSSV2) */ + +#if (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) + /* 0 - normal operation, 1 - Flash Accelerator in bypass mode */ + #define CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS ((uint32) 0x02u) +#endif /* (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) */ + + +#if (CY_IP_SRSSV2) + #if (CY_IP_HOBTO_DEVICE) + /******************************************************************************* + * Function Name: CySysPmHibPinsDisableInputBuf + ****************************************************************************//** + * + * Disable the input buffer for all the port. This is required before Hibernate + * mode entry as the operation of the input buffer is not guaranteed if VCCD + * drops down to 1.0 V. + * + *******************************************************************************/ + static CY_INLINE void CySysPmHibPinsDisableInputBuf(void) + { + #ifdef CYREG_GPIO_PRT0_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT0_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT0_PC */ + + #ifdef CYREG_GPIO_PRT1_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT1_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT1_PC */ + + #ifdef CYREG_GPIO_PRT2_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT2_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT2_PC */ + + #ifdef CYREG_GPIO_PRT3_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT3_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT3_PC */ + + #ifdef CYREG_GPIO_PRT4_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT4_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT4_PC */ + + #ifdef CYREG_GPIO_PRT5_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT5_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT5_PC */ + + #ifdef CYREG_GPIO_PRT6_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT6_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT6_PC */ + + #ifdef CYREG_GPIO_PRT7_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT7_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT7_PC */ + + #ifdef CYREG_GPIO_PRT8_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT8_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT8_PC */ + + #ifdef CYREG_GPIO_PRT9_PC + CY_CLEAR_REG32_FIELD( CYREG_GPIO_PRT9_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT9_PC */ + + #ifdef CYREG_GPIO_PRT10_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT10_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT10_PC */ + + #ifdef CYREG_GPIO_PRT11_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT11_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT11_PC */ + + #ifdef CYREG_GPIO_PRT12_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT12_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT12_PC */ + + #ifdef CYREG_GPIO_PRT13_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT13_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT13_PC */ + + #ifdef CYREG_GPIO_PRT14_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT14_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT14_PC */ + + #ifdef CYREG_GPIO_PRT15_PC + CY_CLEAR_REG32_FIELD(CYREG_GPIO_PRT15_PC, CYFLD_GPIO_PRT_PORT_IB_MODE_SEL); + #endif /* CYREG_GPIO_PRT15_PC */ + } + #endif /* (CY_IP_HOBTO_DEVICE) */ +#endif /* (CY_IP_SRSSV2) */ + + +#if (CY_IP_CPUSS_CM0) + #define CY_PM_CM0_SCR_REG (CY_PM_CPU_SCR_REG) + #define CY_PM_CM0_SCR_PTR (CY_PM_CPU_SCR_PTR) + #define CY_PM_CM0_SCR_SLEEPDEEP (CY_PM_CPU_SCR_SLEEPDEEP) +#endif /* (CY_IP_CPUSS_CM0) */ + + +#endif /* CY_BOOT_CYPM_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/cy_em_eeprom.c b/cores/asr650x/projects/PSoC4/cy_em_eeprom.c new file mode 100644 index 00000000..ce94d9c0 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cy_em_eeprom.c @@ -0,0 +1,1416 @@ +/***************************************************************************//** +* \file cy_em_eeprom.c +* \version 2.0 +* +* \brief +* This file provides source code of the API for the Emulated EEPROM library. +* The Emulated EEPROM API allows creating of an emulated EEPROM in flash that +* has the ability to do wear leveling and restore corrupted data from a +* redundant copy. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include "cytypes.h" +#include + +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include "em_eeprom/cy_em_eeprom.h" +#else + #include "cy_em_eeprom.h" +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* Private Function Prototypes +***************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context); +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context); +static uint8 CalcChecksum(uint8 rowData[], uint32 len); +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config); +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, uint32 *rowData, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, uint32 ramBuffAddr, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context); +static uint32 GetAddresses(uint32 *startAddr, uint32 *endAddr, uint32 *offset, uint32 rowNum, uint32 addr, uint32 len); +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context); + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Init +****************************************************************************//** +* +* Initializes the Emulated EEPROM library by filling the context structure. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \param context +* The pointer to the EEPROM context structure to be filled by the function. +* \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* The context structure should not be modified by the user after it is filled +* with this function. Modification of context structure may cause the +* unexpected behavior of the Cy_Em_EEPROM API functions which rely on it. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* If the "Redundant Copy" option is used, the function performs a number of +* write operations to the EEPROM to initialize flash rows checksums. Therefore, +* Cy_Em_EEPROM_NumWrites(), when it is called right after Cy_Em_EEPROM_Init(), +* will return a non-zero value that identifies the number of writes performed +* by Cy_Em_EEPROM_Init(). +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + if((NULL != context) && (NULL != config) && (NULL != ((uint32 *)config->userFlashStartAddr)) && + (config->wearLevelingFactor <= CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR) && (config->eepromSize != 0u)) + { + ret = CheckRanges(config); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Copy the user config structure fields into context */ + context->eepromSize = config->eepromSize; + context->wearLevelingFactor = config->wearLevelingFactor; + context->redundantCopy = config->redundantCopy; + context->blockingWrite = config->blockingWrite; + context->userFlashStartAddr = config->userFlashStartAddr; + /* Store frequently used data for internal use */ + context->numberOfRows = CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(config->eepromSize); + context->wlEndAddr = ((CY_EM_EEPROM_GET_EEPROM_SIZE(context->numberOfRows) * config->wearLevelingFactor) + + config->userFlashStartAddr); + /* Find last written EEPROM row and store it for quick access */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + + if((0u == CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)) && (0u != context->redundantCopy)) + { + /* Call the function only after device reprogramming in case + * if redundant copy is enabled. + */ + ret = FillChecksum(context); + + /* Update the last written EEPROM row for Cy_Em_EEPROM_NumWrites() */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Read +****************************************************************************//** +* +* This function takes the logical EEPROM address, converts it to the actual +* physical address where the data is stored and returns the data to the user. +* +* \param addr +* The logical start address in EEPROM to start reading data from. +* +* \param eepromData +* The pointer to a user array to write data to. +* +* \param size +* The amount of data to read. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \note +* In case if redundant copy option is enabled the function may perform writes +* to EEPROM. This is done in case if the data in the EEPPROM is corrupted and +* the data in redundant copy is valid based on CRC-8 data integrity check. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 numBytesToRead; + uint32 curEepromBaseAddr; + uint32 curRowOffset; + uint32 startRowAddr; + uint32 actEepromRowNum; + uint32 curRdEepromRowNum = 0u; + uint32 dataStartEepromRowNum = 0u; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Validate input parameters */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 rdAddr = addr; + uint32 rdSize = size; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr); + uint32 updateAddrFlag = 0u; + + /* Calculate the number of the row read operations. Currently this only concerns + * the reads from the EEPROM data locations. + */ + uint32 numRowReads = ((((rdAddr + rdSize) - 1u) / CY_EM_EEPROM_EEPROM_DATA_LEN) - + (rdAddr / CY_EM_EEPROM_EEPROM_DATA_LEN)) + 1u; + + /* Get the address of the first row of the currently active EEPROM sector. If + * no wear leveling is used - the EEPROM has only one sector, so use the base + * addr stored in "context->userFlashStartAddr". + */ + curEepromBaseAddr = (((context->lastWrRowAddr - context->userFlashStartAddr) / + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) * + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) + + context->userFlashStartAddr; + + /* Find the number of the row that contains the start address of the data */ + for(i = 0u; i < context->numberOfRows; i++) + { + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(rdAddr, i)) + { + dataStartEepromRowNum = i; + curRdEepromRowNum = dataStartEepromRowNum; + break; + } + } + + /* Find the row number of the last written row */ + actEepromRowNum = (context->lastWrRowAddr - curEepromBaseAddr) / CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + /* Check if wear leveling is used */ + if(context->wearLevelingFactor > 1u) + { + uint32 dataEndEepromRowNum = dataStartEepromRowNum + (numRowReads - 1u); + + /* Check if the future validation of the read address is required. */ + updateAddrFlag = (dataStartEepromRowNum > actEepromRowNum) ? 1u : + ((dataEndEepromRowNum > actEepromRowNum) ? 1u : 0u); + } + + /* Copy data from the EEPROM data locations to the user buffer */ + for(i = 0u; i < numRowReads; i++) + { + startRowAddr = curEepromBaseAddr + (curRdEepromRowNum * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + curRowOffset = CY_EM_EEPROM_EEPROM_DATA_LEN + (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Check if there are more reads pending and update the number of the + * remaining bytes to read respectively. + */ + if((i + 1u) < numRowReads) + { + numBytesToRead = CY_EM_EEPROM_EEPROM_DATA_LEN - (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + } + else + { + numBytesToRead = rdSize; + } + + /* Check if the read address needs to be updated to point to the correct + * EEPROM sector. + */ + if((0u != updateAddrFlag) && (curRdEepromRowNum > actEepromRowNum)) + { + startRowAddr -= context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if(startRowAddr < context->userFlashStartAddr) + { + startRowAddr = context->wlEndAddr - + ((context->numberOfRows - curRdEepromRowNum) * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + + if(0u != context->redundantCopy) + { + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in + * the corresponding row in redundant copy, otherwise return failure. + */ + ret = CheckCrcAndCopy(startRowAddr, eeData, curRowOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + /* Copy the data to the user buffer */ + (void)memcpy((void *)(eeData), + (void *)(startRowAddr + curRowOffset), + numBytesToRead); + + /* Indicate success to be able to execute next code block */ + ret = CY_EM_EEPROM_SUCCESS; + } + + /* Update variables anticipated in the read operation */ + rdAddr += numBytesToRead; + rdSize -= numBytesToRead; + eeData += numBytesToRead; + curRdEepromRowNum++; + } + + /* This code block will copy the latest data from the EEPROM headers into the + * user buffer. The data previously copied into the user buffer may be updated + * as the EEPROM headers contain more recent data. + * The code block is executed when two following conditions are true: + * 1) The reads from "historic" data locations were successful; + * 2) The user performed at least one write operation to Em_EEPROM (0u != + * seqNum). + */ + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != seqNum)) + { + numRowReads = (context->numberOfRows <= seqNum) ? (context->numberOfRows) : (seqNum); + numRowReads--; + + for(i = (seqNum - numRowReads); i <= seqNum; i++) + { + startRowAddr = GetRowAddrBySeqNum(i, context); + + if (0u != startRowAddr) + { + /* The following variables are introduced to increase code readability. */ + uint32 startAddr = *(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET); + uint32 endAddr = startAddr + (*(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + + /* Check if the current row EEPROM header contains the data requested for read */ + if(0u != CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr, endAddr, addr, addr + size)) + { + uint32 srcOffset = (startAddr > addr) ? (0u) : (addr - startAddr); + uint32 dstOffset = (startAddr > addr) ? (startAddr - addr): (0u); + rdAddr = (startAddr > addr) ? (startAddr) : (addr); + + srcOffset += CY_EM_EEPROM_HEADER_DATA_OFFSET; + + /* Calculate the number of bytes to be read from the current row's EEPROM header */ + numBytesToRead = ((endAddr < (addr + size)) ? endAddr : (addr + size)) - rdAddr; + + /* Calculate the offset in the user buffer from which the data will be updated. */ + eeData = ((uint32)eepromData) + dstOffset; + + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in the + * corresponding row in redundant copy, otherwise return failure. Copy the data + * from the recent EEPROM headers to the user buffer. This will overwrite the + * data copied form EEPROM data locations as the data in EEPROM headers is newer. + */ + if(0u != context->redundantCopy) + { + ret = CheckCrcAndCopy(startRowAddr, eeData, srcOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + (void)memcpy((void *)(eeData), (void *)(startRowAddr + srcOffset), numBytesToRead); + } + } + } + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Write +****************************************************************************//** +* +* This function takes the logical EEPROM address and converts it to the actual +* physical address and writes data there. If wear leveling is implemented, the +* writing process will use the wear leveling techniques. This is a blocking +* function and it does not return until the write operation is completed. The +* user firmware should not enter Hibernate mode until write is completed. The +* write operation is allowed in Sleep and Deep-Sleep modes. During the flash +* operation, the device should not be reset, including the XRES pin, a software +* reset, and watchdog reset sources. Also, low-voltage detect circuits should +* be configured to generate an interrupt instead of a reset. Otherwise, portions +* of flash may undergo unexpected changes. +* +* \param addr +* The logical start address in EEPROM to start writing data from. +* +* \param eepromData +* Data to write to EEPROM. +* +* \param size +* The amount of data to write to EEPROM. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform write +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM write is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 wrCnt; + uint32 actEmEepromRowNum; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 startAddr = 0u; + uint32 endAddr = 0u; + uint32 tmpRowAddr; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + void * tmpData; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Check if the EEPROM data does not exceed the EEPROM capacity */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 numWrites = ((size - 1u) / CY_EM_EEPROM_HEADER_DATA_LEN) + 1u; + uint32 eeHeaderDataOffset = 0u; + + for(wrCnt = 0u; wrCnt < numWrites; wrCnt++) + { + uint32 skipOperation = 0u; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* Get the address of the row to be written. The "emEepromRowAddr" may be + * updated with the proper address (if wear leveling is used). The + * "emEepromRowRdAddr" will point to the row address from which the historic + * data will be read into the RAM buffer. + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + + /* Clear the RAM buffer so to not put junk into flash */ + (void)memset(writeRamBuffer, 0, CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Fill the EM_EEPROM header info for the row in the RAM buffer */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + writeRamBuffer[CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32] = addr; + tmpData = (void *) eeData; + + /* Check if this is the last row to write */ + if(wrCnt == (numWrites - 1u)) + { + /* Fill in the remaining size value to the EEPROM header. */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = size; + } + else + { + /* This is not the last row to write in the current EEPROM write operation. + * Write the maximum possible data size to the EEPROM header. Update the + * size, eeData and addr respectively. + */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = CY_EM_EEPROM_HEADER_DATA_LEN; + size -= CY_EM_EEPROM_HEADER_DATA_LEN; + addr += CY_EM_EEPROM_HEADER_DATA_LEN; + eeData += CY_EM_EEPROM_HEADER_DATA_LEN; + } + + /* Write the data to the EEPROM header */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_HEADER_DATA_OFFSET_U32], + tmpData, + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32]); + + if(emEepromRowRdAddr != 0UL) + { + /* Copy the EEPROM historic data for this row from flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + (void *)(emEepromRowRdAddr + CY_EM_EEPROM_EEPROM_DATA_LEN), + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + /* Check if there is data for this location in other EEPROM headers: + * find out the row with the lowest possible sequence number which + * may contain the data for the current row. + */ + i = (seqNum > context->numberOfRows) ? ((seqNum - (context->numberOfRows)) + 1u) : 1u; + + for(; i <= seqNum; i++) + { + if(i == seqNum) + { + /* The code reached the row that is about to be written. Analyze the recently + * created EEPROM header (stored in the RAM buffer currently): if it contains + * the data for EEPROM data locations in the row that is about to be written. + */ + tmpRowAddr = (uint32) writeRamBuffer; + } + else + { + /* Retrieve the address of the previously written row by its sequence number. + * The pointer will be used to get data from the respective EEPROM header. + */ + tmpRowAddr = GetRowAddrBySeqNum(i, context); + } + + actEmEepromRowNum = CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(emEepromRowAddr, + context->numberOfRows, + context->userFlashStartAddr); + if(0UL != tmpRowAddr) + { + /* Calculate the required addressed for the later EEPROM historic data update */ + skipOperation = GetAddresses( + &startAddr, + &endAddr, + &eeHeaderDataOffset, + actEmEepromRowNum, + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET), + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + } + else + { + /* Skip writes to the RAM buffer */ + skipOperation++; + } + + /* Write data to the RAM buffer */ + if(0u == skipOperation) + { + uint32 dataAddr = ((uint32)((uint8 *)&writeRamBuffer)) + startAddr; + + /* Update the address to point to the EEPROM header data and not to + * the start of the row. + */ + tmpRowAddr = tmpRowAddr + CY_EM_EEPROM_HEADER_DATA_OFFSET + eeHeaderDataOffset; + (void)memcpy((void *)(dataAddr), (void *)(tmpRowAddr), endAddr - startAddr); + } + + /* Calculate the checksum if redundant copy is enabled */ + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + } + + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, writeRamBuffer, context); + tmpRowAddr = emEepromRowAddr; + + /* Check if redundant copy is used */ + if((0u != context->redundantCopy) && (CY_EM_EEPROM_SUCCESS == ret)) + { + /* Update the row address to point to the row in the redundant EEPROM's copy */ + tmpRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Store last written row address only when EEPROM and redundant + * copy writes were successful. + */ + context->lastWrRowAddr = emEepromRowAddr; + } + else + { + break; + } + } + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Erase +****************************************************************************//** +* +* This function erases the entire contents of the EEPROM. Erased values are all +* zeros. This is a blocking function and it does not return until the write +* operation is completed. The user firmware should not enter Hibernate mode until +* erase is completed. The erase operation is allowed in Sleep and Deep-Sleep modes. +* During the flash operation, the device should not be reset, including the +* XRES pin, a software reset, and watchdog reset sources. Also, low-voltage +* detect circuits should be configured to generate an interrupt instead of a +* reset. Otherwise, portions of flash may undergo unexpected changes. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* For all non PSoC 6 devices the erase operation is performed by clearing +* the EEPROM data using flash write. This affects the flash durability. +* So it is recommended to use this function in utmost case to prolongate +* flash life. +* +* \note +* This function uses a buffer of the flash row size to perform erase +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM erase is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 seqNum; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV] = {0u}; +#if (CY_PSOC6) + uint32 emEepromStoredRowAddr = context->lastWrRowAddr; + uint32 storedSeqNum; +#endif /* (!CY_PSOC6) */ + + /* Get the sequence number of the last written row */ + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* If there were no writes to EEPROM - nothing to erase */ + if(0u != seqNum) + { + /* Calculate the number of row erase operations required */ + uint32 numWrites = context->numberOfRows * context->wearLevelingFactor; + + #if (CY_PSOC6) + GetNextRowToWrite(seqNum, &emEepromStoredRowAddr, &emEepromRowRdAddr, context); + storedSeqNum = seqNum + 1u; + #endif /* (CY_PSOC6) */ + + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + for(i = 0u; i < numWrites; i++) + { + #if (CY_PSOC6) + /* For PSoC 6 the erase operation moves backwards. From last written row + * identified by "seqNum" down to "seqNum" - "numWrites". If "emEepromRowAddr" + * is zero this means that the row identified by "seqNum" was previously + * erased. + */ + if(0u != emEepromRowAddr) + { + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + } + + seqNum--; + + if(0u == seqNum) + { + /* Exit the loop as there is no more row is EEPROM to be erased */ + break; + } + emEepromRowAddr = GetRowAddrBySeqNum(seqNum, context); + #else + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + /* Get the address of the row to be erased. "emEepromRowAddr" may be updated + * with the proper address (if wear leveling is used). + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + seqNum++; + writeRamBuffer[0u] = seqNum; + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + #endif /* (CY_PSOC6) */ + } + + #if (CY_PSOC6) + if(CY_EM_EEPROM_SUCCESS == ret) + { + writeRamBuffer[0u] = storedSeqNum; + + /* Write the previously stored sequence number to the flash row which would be + * written next if the erase wouldn't happen. In this case the write to + * redundant copy can be skipped as it does not add any value. + */ + ret = WriteRow(emEepromStoredRowAddr, writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = emEepromStoredRowAddr; + } + } + #endif /* (CY_PSOC6) */ + + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_NumWrites +****************************************************************************//** +* +* Returns the number of the EEPROM writes completed so far. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* The number of writes performed to the EEPROM. +* +*******************************************************************************/ +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context) +{ + return(CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)); +} + +/** \} */ + +/** \cond INTERNAL */ + + +/******************************************************************************* +* Function Name: FindLastWrittenRow +****************************************************************************//** +* +* Performs a search of the last written row address of the EEPROM associated +* with the context structure. If there were no writes to the EEPROM the +* function returns the start address of the EEPROM. The row address is returned +* in the input parameter. +* +* \param lastWrRowPtr +* The pointer to a memory where the last written row will be returned. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context) +{ + uint32 seqNum = 0u; + uint32 prevSeqNum = 0u; + uint32 numRows; + uint32 emEepromAddr = context->userFlashStartAddr; + + *lastWrRowPtr = emEepromAddr; + + for(numRows = 0u; numRows < (context->numberOfRows * context->wearLevelingFactor); numRows++) + { + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr); + if((0u != seqNum) && (seqNum > prevSeqNum)) + { + /* Some record in EEPROM was found. Store found sequence + * number and row address. + */ + prevSeqNum = seqNum; + *lastWrRowPtr = emEepromAddr; + } + + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } +} + + +/******************************************************************************* +* Function Name: GetRowAddrBySeqNum +****************************************************************************//** +* +* Returns the address of the row in EEPROM using its sequence number. +* +* \param seqNum +* The sequence number of the row. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* The address of the row or zero if the row with the sequence number was not +* found. +* +*******************************************************************************/ +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context) +{ + uint32 emEepromAddr = context->userFlashStartAddr; + + while(CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr) != seqNum) + { + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if (CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(emEepromAddr, context->wlEndAddr)) + { + emEepromAddr = 0u; + /* Exit the loop as we reached the end of EEPROM */ + break; + } + } + + return (emEepromAddr); +} + + +/******************************************************************************* +* Function Name: GetNextRowToWrite +****************************************************************************//** +* +* Performs a range check of the row that should be written and updates the +* address to the row respectively. The similar actions are done for the read +* address. +* +* \param seqNum +* The sequence number of the last written row. +* +* \param rowToWrPtr +* The address of the last written row (input). The address of the row to be +* written (output). +* +* \param rowToRdPtr +* The address of the row from which the data should be read into the RAM buffer +* in a later write operation. Out parameter. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context) +{ + /* Switch to the next row to be written if the current sequence number is + * not zero. + */ + if(0u != seqNum) + { + *rowToWrPtr = (*rowToWrPtr + CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + + /* If the resulting row address is out of EEPROM, then switch to the base + * EEPROM address (Row#0). + */ + if(CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(*rowToWrPtr, context->wlEndAddr)) + { + *rowToWrPtr = context->userFlashStartAddr; + } + + *rowToRdPtr = 0u; + + /* Check if the sequence number is larger than the number of rows in the EEPROM. + * If not, do not update the row read address because there is no historic + * data to be read. + */ + if(context->numberOfRows <= seqNum) + { + /* Check if wear leveling is used in EEPROM */ + if(context->wearLevelingFactor > 1u) + { + /* The read row address should be taken from an EEPROM copy that became + * inactive recently. This condition check handles that. + */ + if((*rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW)) < + context->userFlashStartAddr) + { + *rowToRdPtr = context->userFlashStartAddr + + (context->numberOfRows * (context->wearLevelingFactor - 1u) * + CY_EM_EEPROM_FLASH_SIZEOF_ROW) + (*rowToWrPtr - context->userFlashStartAddr); + } + else + { + *rowToRdPtr = *rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + else + { + /* If no wear leveling, always read from the same flash row that + * should be written. + */ + *rowToRdPtr = *rowToWrPtr; + } + } +} + + +/******************************************************************************* +* Function Name: CalcChecksum +****************************************************************************//** +* +* Implements CRC-8 that is used in checksum calculation for the redundant copy +* algorithm. +* +* \param rowData +* The row data to be used to calculate the checksum. +* +* \param len +* The length of rowData. +* +* \return +* The calculated value of CRC-8. +* +*******************************************************************************/ +static uint8 CalcChecksum(uint8 rowData[], uint32 len) +{ + uint8 crc = CY_EM_EEPROM_CRC8_SEED; + uint8 i; + uint16 cnt = 0u; + + while(cnt != len) + { + crc ^= rowData[cnt]; + for (i = 0u; i < CY_EM_EEPROM_CRC8_POLYNOM_LEN; i++) + { + crc = CY_EM_EEPROM_CALCULATE_CRC8(crc); + } + cnt++; + } + + return (crc); +} + + +/******************************************************************************* +* Function Name: CheckRanges +****************************************************************************//** +* +* Checks if the EEPROM of the requested size can be placed in flash. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_DATA; + uint32 startAddr = config->userFlashStartAddr; + uint32 endAddr = startAddr + CY_EM_EEPROM_GET_PHYSICAL_SIZE(config->eepromSize, + config->wearLevelingFactor, config->redundantCopy); + + /* Range check if there is enough flash for EEPROM */ + if (CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + return (ret); +} + + +/******************************************************************************* +* Function Name: WriteRow +****************************************************************************//** +* +* Writes one flash row starting from the specified row address. +* +* \param rowAdd +* The address of the flash row. +* +* \param rowData +* The pointer to the data to be written to the row. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, + uint32 *rowData, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (!CY_PSOC6) + cystatus rc; + uint32 rowId; + #if ((CY_PSOC3) || (CY_PSOC5)) + uint32 arrayId; + #endif /* (CY_PSOC3) */ + + #if (CY_PSOC3) + rowAddr &= CY_EM_EEPROM_CODE_ADDR_MASK; + context = context; /* To avoid compiler warning generation */ + #else + (void)context; /* To avoid compiler warning generation */ + #endif /* ((CY_PSOC3) */ + + /* For non-PSoC 6 devices, the Array ID and Row ID needed to write the row */ + rowId = (rowAddr / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % CY_EM_EEPROM_ROWS_IN_ARRAY; + + /* Write the flash row */ + #if (CY_PSOC4) + rc = CySysFlashWriteRow(rowId, (uint8 *)rowData); + #else + + #ifndef CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT + (void)CySetTemp(); + #endif /* (CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT) */ + + arrayId = rowAddr / CY_FLASH_SIZEOF_ARRAY; + rc = CyWriteRowData((uint8)arrayId, (uint16)rowId, (uint8 *)rowData); + + #if (CY_PSOC5) + CyFlushCache(); + #endif /* (CY_PSOC5) */ + #endif /* (CY_PSOC4) */ + + if(CYRET_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } +#else /* PSoC 6 */ + if(0u != context->blockingWrite) + { + /* Do blocking write */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_WriteRow(rowAddr, (const uint32 *)rowData)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate write */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartWrite(rowAddr, (const uint32 *)rowData)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if write completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } +#endif /* (CY_PSOC6) */ + + return (ret); +} + + +/******************************************************************************* +* Function Name: EraseRow +****************************************************************************//** +* +* Erases one flash row starting from the specified row address. If the redundant +* copy option is enabled the corresponding row in the redundant copy will also +* be erased. +* +* \param rowAdd +* The address of the flash row. +* +* \param ramBuffAddr +* The address of the RAM buffer that contains zeroed data (used only for +* non-PSoC 6 devices). +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, + uint32 ramBuffAddr, + cy_stc_eeprom_context_t * context) +{ + uint32 emEepromRowAddr = rowAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (CY_PSOC6) + uint32 i = 1u; + + (void)ramBuffAddr; /* To avoid compiler warning */ + + if(0u != context->redundantCopy) + { + i++; + } + + do + { + if(0u != context->blockingWrite) + { + /* Erase the flash row */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_EraseRow(emEepromRowAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate erase */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartErase(emEepromRowAddr)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if erase completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + } + else + { + break; + } + i--; + } while (0u != i); +#else + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != context->redundantCopy)) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = rowAddr; + } +#endif /* (CY_PSOC6) */ + + return(ret); +} + + +/******************************************************************************* +* Function Name: CheckCrcAndCopy +****************************************************************************//** +* +* Checks the checksum of the specific row in EEPROM. If the CRC matches - copies +* the data to the "datAddr" from EEPROM. f the CRC does not match checks the +* CRC of the corresponding row in the EEPROM's redundant copy. If the CRC +* matches - copies the data to the "datAddr" from EEPROM redundant copy. If the +* CRC of the redundant copy does not match - returns bad checksum. +* +* \param startAddr +* The address that points to the start of the specified row. +* +* \param datAddr +* The start address of where the row data will be copied if the CRC check +* will succeed. +* +* \param rowOffset +* The offset in the row from which the data should be copied. +* +* \param numBytes +* The number of bytes to be copied. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + + /* Calculate the row address in the EEPROM's redundant copy */ + uint32 rcStartRowAddr = (startAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Check the row data CRC in the EEPROM */ + if((*(uint32 *)(startAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(startAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + (void)memcpy((void *)(dstAddr), (void *)(startAddr + rowOffset), numBytes); + + ret = CY_EM_EEPROM_SUCCESS; + } + /* Check the row data CRC in the EEPROM's redundant copy */ + else if((*(uint32 *)(rcStartRowAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(rcStartRowAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + /* Copy the redundant copy row to RAM buffer to avoid read while write (RWW) + * flash exception. The RWW occurs while trying to write and read the data from + * same flash macro. + */ + (void)memcpy((void *)(writeRamBuffer), (void *)(rcStartRowAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Restore bad row data from the RAM buffer */ + ret = WriteRow(startAddr, (uint32 *)writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + (void)memcpy((void *)(dstAddr), (void *)(writeRamBuffer + rowOffset), numBytes); + } + } + else + { + ret = CY_EM_EEPROM_BAD_CHECKSUM; + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: GetAddresses +****************************************************************************//** +* +* Calculates the start and end address of the row's EEPROM data to be updated. +* The start and end are not absolute addresses but a relative addresses in a +* flash row. +* +* \param startAddr +* The pointer the address where the EEPROM data start address will be returned. +* +* \param endAddr +* The pointer the address where the EEPROM data end address will be returned. +* +* \param offset +* The pointer the address where the calculated offset of the EEPROM header data +* will be returned. +* +* \param rowNum +* The row number that is about to be written. +* +* \param addr +* The address of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \param len +* The length of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \return +* Zero indicates that the currently analyzed row has the data to be written to +* the active EEPROM row data locations. Non zero value indicates that there is +* no data to be written +* +*******************************************************************************/ +static uint32 GetAddresses(uint32 *startAddr, + uint32 *endAddr, + uint32 *offset, + uint32 rowNum, + uint32 addr, + uint32 len) +{ + uint32 skip = 0u; + + *offset =0u; + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN + (addr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *endAddr = *startAddr + len; + } + else + { + *endAddr = CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } + } + else + { + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN; + *endAddr = (*startAddr + len) - (*startAddr - (addr % CY_EM_EEPROM_EEPROM_DATA_LEN)); + *offset = len - (*endAddr - *startAddr); + } + else + { + skip++; + } + } + + return (skip); +} + + +/******************************************************************************* +* Function Name: FillChecksum +****************************************************************************//** +* +* Performs calculation of the checksum on each row in the Em_EEPROM and fills +* the Em_EEPROM headers checksum field with the calculated checksums. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \theory +* In case if redundant copy option is used the Em_EEPROM would return bad +* checksum while trying to read the EEPROM rows which were not yet written by +* the user. E.g. any read after device reprogramming without previous Write() +* operation to the EEPROM would fail. This would happen because the Em_EEPROM +* headers checksum field values (which is zero at the moment) would not be +* equal to the actual data checksum. This function allows to avoid read failure +* after device reprogramming. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 rdAddr; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 wrAddr = context->lastWrRowAddr; + uint32 tmpRowAddr; + /* Get the sequence number (number of writes) */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(wrAddr); + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + for(i = 0u; i < (context->numberOfRows * context->wearLevelingFactor); i++) + { + /* Copy the EEPROM row from Flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[0u], (void *)(wrAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Increment the sequence number */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + + /* Calculate and fill the checksum to the Em_EEPROM header */ + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Write the data to the specified flash row */ + ret = WriteRow(wrAddr, writeRamBuffer, context); + + /* Update the row address to point to the relevant row in the redundant + * EEPROM's copy. + */ + tmpRowAddr = (wrAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + + /* Get the address of the next row to be written. + * "rdAddr" is not used in this function but provided to prevent NULL + * pointer exception in GetNextRowToWrite(). + */ + GetNextRowToWrite(seqNum, &wrAddr, &rdAddr, context); + } + + return(ret); +} + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/cy_em_eeprom.h b/cores/asr650x/projects/PSoC4/cy_em_eeprom.h new file mode 100644 index 00000000..4aef67b0 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cy_em_eeprom.h @@ -0,0 +1,556 @@ +/******************************************************************************* +* \file cy_em_eeprom.h +* \version 2.0 +* +* \brief +* This file provides the function prototypes and constants for the Emulated +* EEPROM middleware library. +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** + * \mainpage Cypress Em_EEPROM Middleware Library + * + * The Emulated EEPROM provides an API that allows creating an emulated + * EEPROM in flash that has the ability to do wear leveling and restore + * corrupted data from a redundant copy. The Emulated EEPROM library is designed + * to be used with the Em_EEPROM component. + * + * The Cy_Em_EEPROM API is described in the following sections: + * - \ref group_em_eeprom_macros + * - \ref group_em_eeprom_data_structures + * - \ref group_em_eeprom_enums + * - \ref group_em_eeprom_functions + * + * Features: + * * EEPROM-Like Non-Volatile Storage + * * Easy to use Read and Write API + * * Optional Wear Leveling + * * Optional Redundant Data storage + * + * \section group_em_eeprom_configuration Configuration Considerations + * + * The Em_EEPROM operates on the top of the flash driver. The flash driver has + * some prerequisites for proper operation. Refer to the "Flash System + * Routine (Flash)" section of the PDL API Reference Manual. + * + * Initializing Emulated EEPROM in User flash + * + * To initialize an Emulated EEPROM in the User flash, the EEPROM storage should + * be declared by the user. For the proper operation, the EEPROM storage should + * be aligned to the size of the flash row. An example of the EEPROM storage + * declaration is below (applicable for GCC and MDK compilers): + * + * CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * Note that the name "emEeprom" is shown for reference. Any other name can be + * used instead. Also, note that the Em_EEPROM_PHYSICAL_SIZE constant is + * generated by the PSoC Creator Em_EEPROM component and so it is instance name + * dependent and its prefix should be changed when the name of the component + * changes. If the The Cy_Em_EEPROM middleware library is used without the + * Em_EEPROM component, the user has to provide a proper size for the EEPROM + * storage instead of Em_EEPROM_PHYSICAL_SIZE. The size of the EEPROM storage + * can be calculated using the following equation: + * + * Physical size = EEPROM data size * 2 * wear leveling * (1 + redundant copy) + * + * where, + * "EEPROM data size" - the size of data the user wants to store in the + * EEPROM. The data size must divide evenly to the half of the flash row size. + * "wear leveling" - the wear leveling factor (1-10). + * "redundant copy" - "zero" if a redundant copy is not used, and "one" + * otherwise. + * + * The start address of the storage should be filled to the Emulated EEPROM + * configuration structure and then passed to the Cy_Em_EEPROM_Init(). + * If the Em_EEPROM component is used, the config (Em_EEPROM_config) and + * context structures (Em_EEPROM_context) are defined by the component, so the + * user may just use that structures otherwise both of the structures need to + * be provided by the user. Note that if the "Config Data in Flash" + * option is selected in the component, then the configuration structure should + * be copied to RAM to allow EEPROM storage start address update. The following + * code demonstrates utilization of "Em_EEPROM_config" and "Em_EEPROM_context" + * Em_EEPROM component structures for Cy_Em_EEPROM middleware library + * initialization: + * + * cy_en_em_eeprom_status_t retValue; + * cy_stc_eeprom_config_t config; + * + * memcpy((void *)&config, + (void *)&Em_EEPROM_config, + sizeof(cy_stc_eeprom_config_t)); + * config.userFlashStartAddr = (uint32)emEeprom; + * retValue = Cy_Em_EEPROM_Init(&config, &Em_EEPROM_context); + * + * Initializing EEPROM in Emulated EEPROM flash area + * + * Initializing of the EEPROM storage in the Emulated EEPROM flash area is + * identical to initializing of the EEPROM storage in the User flash with one + * difference. The location of the Emulated EEPROM storage should be specified + * somewhere in the EmulatedEEPROM flash area. If the Em_EEPROM component is + * utilized in the project, then the respective storage + * (Em_EEPROM_em_EepromStorage[]) is automatically declared by the component + * if the "Use Emulated EEPROM" option is set to "Yes". The user just needs to + * fill the start address of the storage to the config structure. If the + * Em_EEPROM component is not used, the user needs to declare the storage + * in the Emulated EEPROM flash area. An example of such declaration is + * following (applicable for GCC and MDK compilers): + * + * CY_SECTION(".cy_em_eeprom") CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8_t emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma location = ".cy_em_eeprom" + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * where, + * Em_EEPROM_PHYSICAL_SIZE - is a constant that is generated by the Em_EEPROM + * component when the component is utilized in the project or it should be + * provided by the user. The equation for the calculation of the constant is + * shown above. + * + * Note that the size of the Emulated EEPROM flash area is limited. Refer to the + * specific device datasheet for the value of the available EEPROM Emulation + * area. + * + * \section group_em_eeprom_more_information More Information + * See the Em_EEPROM Component datasheet. + * + * + * \section group_em_eeprom_MISRA MISRA-C Compliance + * + * The Cy_Em_EEPROM library has the following specific deviations: + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AThe cast should not be performed between a pointer to the object type + * and a different pointer to the object type.The cast from the object type and a different pointer to the object + * was used intentionally because of the performance reasons.
14.2RAll non-null statements shall either have at least one side-effect, + * however executed, or cause control flow to change.To maintain common codebase, some variables, unused for a specific + * device, are casted to void to prevent generation of an unused variable + * compiler warning.
16.7AThe object addressed by the pointer parameter is not modified and so + * the pointer could be of type 'pointer to const'.The warning is generated because of the pointer dereferencing to + * address which makes the MISRA checker think the data is not + * modified.
17.4RThe array indexing shall be the only allowed form of pointer + * arithmetic.The pointer arithmetic used in several places on the Cy_Em_EEPROM + * implementation is safe and preferred because it increases the code + * flexibility.
19.7AA function shall be used in preference to a function-like macro.Macro is used because of performance reasons.
+ * + * \section group_em_eeprom_changelog Changelog + * + * + * + * + * + * + * + *
VersionChangesReason for Change
1.0Initial Version
+ * + * \defgroup group_em_eeprom_macros Macros + * \brief + * This section describes the Emulated EEPROM Macros. + * + * \defgroup group_em_eeprom_functions Functions + * \brief + * This section describes the Emulated EEPROM Function Prototypes. + * + * \defgroup group_em_eeprom_data_structures Data Structures + * \brief + * Describes the data structures defined by the Emulated EEPROM. + * + * \defgroup group_em_eeprom_enums Enumerated types + * \brief + * Describes the enumeration types defined by the Emulated EEPROM. + * + */ + + +#if !defined(CY_EM_EEPROM_H) +#define CY_EM_EEPROM_H + +#include "cytypes.h" +#include +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include + #include "syslib/cy_syslib.h" + #include "flash/cy_flash.h" +#else + #include "CyFlash.h" + #include +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + +/* The C binding of definitions if building with the C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ +#define CY_PSOC6 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + + +/*************************************** +* Data Structure definitions +***************************************/ +/** +* \addtogroup group_em_eeprom_data_structures +* \{ +*/ + +/** EEPROM configuration structure */ +typedef struct +{ + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_config_t; + +/** \} group_em_eeprom_data_structures */ + +/** The EEPROM context data structure. It is used to store the specific +* EEPROM context data. +*/ +typedef struct +{ + /** The pointer to the end address of EEPROM including wear leveling overhead + * and excluding redundant copy overhead. + */ + uint32 wlEndAddr; + + /** The number of flash rows allocated for the EEPROM excluding the number of + * rows allocated for wear leveling and redundant copy overhead. + */ + uint32 numberOfRows; + + /** The address of the last written EEPROM row */ + uint32 lastWrRowAddr; + + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_context_t; + +#if (CY_PSOC6) + + #define CY_EM_EEPROM_ID (CY_PDL_DRV_ID(0x1BuL)) /**< Em_EEPROM PDL ID */ + /** + * \addtogroup group_em_eeprom_enums + * \{ + * Specifies return values meaning. + */ + /** A prefix for EEPROM function error return-values */ + #define CY_EM_EEPROM_ID_ERROR (uint32_t)(CY_EM_EEPROM_ID | CY_PDL_STATUS_ERROR) + +#else + + /** A prefix for EEPROM function status codes. For non-PSoC6 devices, + * prefix is zero. + */ + #define CY_EM_EEPROM_ID_ERROR (0uL) + +#endif /* (CY_PSOC6) */ + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/** EEPROM return enumeration type */ +typedef enum +{ + CY_EM_EEPROM_SUCCESS = 0x00uL, /**< The function executed successfully */ + CY_EM_EEPROM_BAD_PARAM = (CY_EM_EEPROM_ID_ERROR + 1uL), /**< The input parameter is invalid */ + CY_EM_EEPROM_BAD_CHECKSUM = (CY_EM_EEPROM_ID_ERROR + 2uL), /**< The data in EEPROM is corrupted */ + CY_EM_EEPROM_BAD_DATA = (CY_EM_EEPROM_ID_ERROR + 3uL), /**< Failed to place the EEPROM in flash */ + CY_EM_EEPROM_WRITE_FAIL = (CY_EM_EEPROM_ID_ERROR + 4uL) /**< Write to EEPROM failed */ +} cy_en_em_eeprom_status_t; + +/** \} group_em_eeprom_enums */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context); +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context); +/** \} group_em_eeprom_functions */ + + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ +/** Library major version */ +#define CY_EM_EEPROM_VERSION_MAJOR (2) + +/** Library minor version */ +#define CY_EM_EEPROM_VERSION_MINOR (0) + +/** Defines the maximum data length that can be stored in one flash row */ +#define CY_EM_EEPROM_EEPROM_DATA_LEN (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) + +/** \} group_em_eeprom_macros */ + + +/*************************************** +* Macro definitions +***************************************/ +/** \cond INTERNAL */ + +/* Defines the size of flash row */ +#define CY_EM_EEPROM_FLASH_SIZEOF_ROW (CY_FLASH_SIZEOF_ROW) + +/* Device specific flash constants */ +#if (!CY_PSOC6) + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CYDEV_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CYDEV_FLASH_SIZE) + #define CY_EM_EEPROM_ROWS_IN_ARRAY (CY_FLASH_SIZEOF_ARRAY / CY_EM_EEPROM_FLASH_SIZEOF_ROW) + #if (CY_PSOC3) + #define CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX (0xff0000uL) + #define CY_EM_EEPROM_CODE_ADDR_END \ + (CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX + (CY_EM_EEPROM_FLASH_SIZE - 1u)) + #define CY_EM_EEPROM_CODE_ADDR_MASK (0xffffu) + /* Checks if the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX) && \ + ((endAddr) <= CY_EM_EEPROM_CODE_ADDR_END)) + #else + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) + #endif /* (CY_PSOC3) */ +#else + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CY_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CY_FLASH_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_BASE_ADDR (CY_EM_EEPROM_BASE) + #define CY_EM_EEPROM_EM_EEPROM_SIZE (CY_EM_EEPROM_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_END_ADDR (CY_EM_EEPROM_EM_EEPROM_BASE_ADDR + CY_EM_EEPROM_EM_EEPROM_SIZE) + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) || \ + (((startAddr) >= CY_EM_EEPROM_EM_EEPROM_BASE_ADDR) && \ + ((endAddr) <= CY_EM_EEPROM_EM_EEPROM_END_ADDR)))) +#endif /* (!CY_PSOC6) */ + +#define CY_EM_EEPROM_FLASH_END_ADDR (CY_EM_EEPROM_FLASH_BASE_ADDR + CY_EM_EEPROM_FLASH_SIZE) + +/* Defines the length of EEPROM data that can be stored in Em_EEPROM header */ +#define CY_EM_EEPROM_HEADER_DATA_LEN ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) - 16u) + +#define CY_EM_EEPROM_ADDR_IN_RANGE (1u) + +/* Return CY_EM_EEPROM_ADDR_IN_RANGE if addr exceeded the upper range of +* EEPROM. The wear leveling overhead is included in the range but redundant copy +* is excluded. +*/ +#define CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(addr, endEepromAddr) \ + (((addr) >= (endEepromAddr)) ? (0u) : (CY_EM_EEPROM_ADDR_IN_RANGE)) + +/* Check to see if the specified address is present in the EEPROM */ +#define CY_EM_EEPROM_IS_ADDR_IN_RANGE(addr, startEepromAddr, endEepromAddr) \ + (((addr) > (startEepromAddr)) ? \ + (((addr) < (endEepromAddr)) ? (CY_EM_EEPROM_ADDR_IN_RANGE) : (0u)) : (0u)) + +/* Check if the EEPROM address locations from startAddr1 to endAddr1 +* are crossed with EEPROM address locations from startAddr2 to endAddr2. +*/ +#define CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr1, endAddr1 , startAddr2, endAddr2) \ + (((startAddr1) > (startAddr2)) ? (((startAddr1) >= (endAddr2)) ? (0u) : (1u) ) : \ + (((startAddr2) >= (endAddr1)) ? (0u) : (1u))) + +/* Return the pointer to the start of the redundant copy of the EEPROM */ +#define CY_EM_EEPROM_GET_REDNT_COPY_ADDR_BASE(numRows, wearLeveling, eepromStartAddr) \ + ((((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) * (wearLeveling)) + (eepromStartAddr)) + +/* Return the number of the row in EM_EEPROM which contains an address defined by +* rowAddr. + */ +#define CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(rowAddr, maxRows, eepromStartAddr) \ + ((((rowAddr) - (eepromStartAddr)) / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % (maxRows)) + + +/** Returns the size allocated for the EEPROM excluding wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_EEPROM_SIZE(numRows) ((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) + +/* Check if the given address belongs to the EEPROM address of the row +* specified by rowNum. +*/ +#define CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum) \ + (((addr) < ((rowNum) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u))) ? (0u) : \ + (((addr) > ((((rowNum) + 1u) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)) - 1u)) ? \ + (0u) : (1u))) + +/* CRC-8 constants */ +#define CY_EM_EEPROM_CRC8_POLYNOM ((uint8)(0x31u)) +#define CY_EM_EEPROM_CRC8_POLYNOM_LEN (8u) +#define CY_EM_EEPROM_CRC8_SEED (0xFFu) +#define CY_EM_EEPROM_CRC8_XOR_VAL ((uint8) (0x80u)) + +#define CY_EM_EEPROM_CALCULATE_CRC8(crc) \ + ((CY_EM_EEPROM_CRC8_XOR_VAL == ((crc) & CY_EM_EEPROM_CRC8_XOR_VAL)) ? \ + ((uint8)(((uint8)((uint8)((crc) << 1u))) ^ CY_EM_EEPROM_CRC8_POLYNOM)) : ((uint8)((crc) << 1u))) + +#define CY_EM_EEPROM_GET_SEQ_NUM(addr) (*(uint32*)(addr)) + +/** \endcond */ + +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ + +/** Calculate the number of flash rows required to create an Em_EEPROM of +* dataSize. +*/ +#define CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) \ + (((dataSize) / (CY_EM_EEPROM_EEPROM_DATA_LEN)) + \ + ((((dataSize) % (CY_EM_EEPROM_EEPROM_DATA_LEN)) != 0u) ? 1U : 0U)) + +/** Returns the size of flash allocated for EEPROM including wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_PHYSICAL_SIZE(dataSize, wearLeveling, redundantCopy) \ + (((CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) * \ + CY_EM_EEPROM_FLASH_SIZEOF_ROW) * \ + (wearLeveling)) * (1uL + (redundantCopy))) + +/** \} group_em_eeprom_macros */ + + +/****************************************************************************** +* Local definitions +*******************************************************************************/ +/** \cond INTERNAL */ + +/* Offsets for 32-bit RAM buffer addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) / 4u) +#define CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32 (0u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32 (1u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET_U32 (2u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET_U32 (3u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32 (CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 - 1u) + +/* The same offsets as above used for direct memory addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET (4u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET (8u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET (12u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET (CY_EM_EEPROM_EEPROM_DATA_OFFSET - 4u) + +#define CY_EM_EEPROM_U32_DIV (4u) + +/* Maximum wear leveling value */ +#define CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR (10u) + +/* Maximum allowed flash row write/erase operation duration */ +#define CY_EM_EEPROM_MAX_WRITE_DURATION_MS (50u) + +/** \endcond */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* CY_EM_EEPROM_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/cybootloader.c b/cores/asr650x/projects/PSoC4/cybootloader.c new file mode 100644 index 00000000..3f07eceb --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cybootloader.c @@ -0,0 +1,1259 @@ +/* GENERATED CODE -- CHANGES WILL BE OVERWRITTEN */ + +#include "cytypes.h" + +#if (!CYDEV_BOOTLOADER_ENABLE) + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cyloadermeta"), used)) +#elif defined(__ICCARM__) +#pragma location=".cyloadermeta" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_loader[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; +#endif /* (!CYDEV_BOOTLOADER_ENABLE) */ + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cybootloader"), used)) +#elif defined(__ICCARM__) +#pragma location=".cybootloader" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_bootloader[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 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+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cymeta"), used)) +#elif defined(__ICCARM__) +#pragma location=".cymeta" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_metadata[] = { + 0x00u, 0x02u, 0x25u, 0x6Au, 0x11u, 0xB5u, 0x00u, 0x00u, + 0x25u, 0x74u, 0xDBu, 0x59u}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cyflashprotect"), used)) +#elif defined(__ICCARM__) +#pragma location=".cyflashprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_flashprotect[] = { + 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cychipprotect"), used)) +#elif defined(__ICCARM__) +#pragma location=".cychipprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_chipprotect[] = { + 0x02u}; diff --git a/cores/asr650x/projects/PSoC4/cybootloader.icf b/cores/asr650x/projects/PSoC4/cybootloader.icf new file mode 100644 index 00000000..614ba8f7 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cybootloader.icf @@ -0,0 +1,3 @@ +/* GENERATED CODE -- CHANGES WILL BE OVERWRITTEN */ + +define symbol CYDEV_BTLDR_SIZE = 0x00002200; diff --git a/cores/asr650x/projects/PSoC4/cycodeshareexport.ld b/cores/asr650x/projects/PSoC4/cycodeshareexport.ld new file mode 100644 index 00000000..e69de29b diff --git a/cores/asr650x/projects/PSoC4/cycodeshareimport.ld b/cores/asr650x/projects/PSoC4/cycodeshareimport.ld new file mode 100644 index 00000000..e69de29b diff --git a/cores/asr650x/projects/PSoC4/cycodeshareimport.scat b/cores/asr650x/projects/PSoC4/cycodeshareimport.scat new file mode 100644 index 00000000..e69de29b diff --git a/cores/asr650x/projects/PSoC4/cydevice_trm.h b/cores/asr650x/projects/PSoC4/cydevice_trm.h new file mode 100644 index 00000000..307e93bb --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cydevice_trm.h @@ -0,0 +1,5498 @@ +/******************************************************************************* +* File Name: cydevice_trm.h +* +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_TRM_H) +#define CYDEVICE_TRM_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00020000u +#define CYREG_FLASH_DATA_MBASE 0x00000000u +#define CYREG_FLASH_DATA_MSIZE 0x00020000u +#define CYDEV_SFLASH_BASE 0x0ffff000u +#define CYDEV_SFLASH_SIZE 0x00000800u +#define CYREG_SFLASH_PROT_ROW0 0x0ffff000u +#define CYFLD_SFLASH_DATA8__OFFSET 0x00000000u +#define CYFLD_SFLASH_DATA8__SIZE 0x00000008u +#define CYREG_SFLASH_PROT_ROW1 0x0ffff001u +#define CYREG_SFLASH_PROT_ROW2 0x0ffff002u +#define CYREG_SFLASH_PROT_ROW3 0x0ffff003u +#define CYREG_SFLASH_PROT_ROW4 0x0ffff004u +#define CYREG_SFLASH_PROT_ROW5 0x0ffff005u +#define CYREG_SFLASH_PROT_ROW6 0x0ffff006u +#define CYREG_SFLASH_PROT_ROW7 0x0ffff007u +#define CYREG_SFLASH_PROT_ROW8 0x0ffff008u +#define CYREG_SFLASH_PROT_ROW9 0x0ffff009u +#define CYREG_SFLASH_PROT_ROW10 0x0ffff00au +#define CYREG_SFLASH_PROT_ROW11 0x0ffff00bu +#define CYREG_SFLASH_PROT_ROW12 0x0ffff00cu +#define CYREG_SFLASH_PROT_ROW13 0x0ffff00du +#define CYREG_SFLASH_PROT_ROW14 0x0ffff00eu +#define CYREG_SFLASH_PROT_ROW15 0x0ffff00fu +#define CYREG_SFLASH_PROT_ROW16 0x0ffff010u +#define CYREG_SFLASH_PROT_ROW17 0x0ffff011u +#define CYREG_SFLASH_PROT_ROW18 0x0ffff012u +#define CYREG_SFLASH_PROT_ROW19 0x0ffff013u +#define CYREG_SFLASH_PROT_ROW20 0x0ffff014u +#define CYREG_SFLASH_PROT_ROW21 0x0ffff015u +#define CYREG_SFLASH_PROT_ROW22 0x0ffff016u +#define CYREG_SFLASH_PROT_ROW23 0x0ffff017u +#define CYREG_SFLASH_PROT_ROW24 0x0ffff018u +#define CYREG_SFLASH_PROT_ROW25 0x0ffff019u +#define CYREG_SFLASH_PROT_ROW26 0x0ffff01au +#define CYREG_SFLASH_PROT_ROW27 0x0ffff01bu +#define CYREG_SFLASH_PROT_ROW28 0x0ffff01cu +#define CYREG_SFLASH_PROT_ROW29 0x0ffff01du +#define CYREG_SFLASH_PROT_ROW30 0x0ffff01eu +#define CYREG_SFLASH_PROT_ROW31 0x0ffff01fu +#define CYREG_SFLASH_PROT_ROW32 0x0ffff020u +#define CYREG_SFLASH_PROT_ROW33 0x0ffff021u +#define CYREG_SFLASH_PROT_ROW34 0x0ffff022u +#define CYREG_SFLASH_PROT_ROW35 0x0ffff023u +#define CYREG_SFLASH_PROT_ROW36 0x0ffff024u +#define CYREG_SFLASH_PROT_ROW37 0x0ffff025u +#define CYREG_SFLASH_PROT_ROW38 0x0ffff026u +#define CYREG_SFLASH_PROT_ROW39 0x0ffff027u +#define CYREG_SFLASH_PROT_ROW40 0x0ffff028u +#define CYREG_SFLASH_PROT_ROW41 0x0ffff029u +#define CYREG_SFLASH_PROT_ROW42 0x0ffff02au +#define CYREG_SFLASH_PROT_ROW43 0x0ffff02bu +#define CYREG_SFLASH_PROT_ROW44 0x0ffff02cu +#define CYREG_SFLASH_PROT_ROW45 0x0ffff02du +#define CYREG_SFLASH_PROT_ROW46 0x0ffff02eu +#define CYREG_SFLASH_PROT_ROW47 0x0ffff02fu +#define CYREG_SFLASH_PROT_ROW48 0x0ffff030u +#define CYREG_SFLASH_PROT_ROW49 0x0ffff031u +#define CYREG_SFLASH_PROT_ROW50 0x0ffff032u +#define CYREG_SFLASH_PROT_ROW51 0x0ffff033u +#define CYREG_SFLASH_PROT_ROW52 0x0ffff034u +#define CYREG_SFLASH_PROT_ROW53 0x0ffff035u +#define CYREG_SFLASH_PROT_ROW54 0x0ffff036u +#define CYREG_SFLASH_PROT_ROW55 0x0ffff037u +#define CYREG_SFLASH_PROT_ROW56 0x0ffff038u +#define CYREG_SFLASH_PROT_ROW57 0x0ffff039u +#define CYREG_SFLASH_PROT_ROW58 0x0ffff03au +#define CYREG_SFLASH_PROT_ROW59 0x0ffff03bu +#define CYREG_SFLASH_PROT_ROW60 0x0ffff03cu +#define CYREG_SFLASH_PROT_ROW61 0x0ffff03du +#define CYREG_SFLASH_PROT_ROW62 0x0ffff03eu +#define CYREG_SFLASH_PROT_ROW63 0x0ffff03fu +#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff0ffu +#define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000u +#define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002u +#define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001u +#define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000u +#define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002u +#define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003u +#define CYREG_SFLASH_AV_PAIRS_8B0 0x0ffff100u +#define CYREG_SFLASH_AV_PAIRS_8B1 0x0ffff101u +#define CYREG_SFLASH_AV_PAIRS_8B2 0x0ffff102u +#define CYREG_SFLASH_AV_PAIRS_8B3 0x0ffff103u +#define CYREG_SFLASH_AV_PAIRS_8B4 0x0ffff104u +#define CYREG_SFLASH_AV_PAIRS_8B5 0x0ffff105u +#define CYREG_SFLASH_AV_PAIRS_8B6 0x0ffff106u +#define CYREG_SFLASH_AV_PAIRS_8B7 0x0ffff107u +#define CYREG_SFLASH_AV_PAIRS_8B8 0x0ffff108u +#define CYREG_SFLASH_AV_PAIRS_8B9 0x0ffff109u +#define CYREG_SFLASH_AV_PAIRS_8B10 0x0ffff10au +#define CYREG_SFLASH_AV_PAIRS_8B11 0x0ffff10bu +#define CYREG_SFLASH_AV_PAIRS_8B12 0x0ffff10cu +#define CYREG_SFLASH_AV_PAIRS_8B13 0x0ffff10du +#define CYREG_SFLASH_AV_PAIRS_8B14 0x0ffff10eu +#define CYREG_SFLASH_AV_PAIRS_8B15 0x0ffff10fu +#define CYREG_SFLASH_AV_PAIRS_8B16 0x0ffff110u +#define CYREG_SFLASH_AV_PAIRS_8B17 0x0ffff111u +#define CYREG_SFLASH_AV_PAIRS_8B18 0x0ffff112u +#define CYREG_SFLASH_AV_PAIRS_8B19 0x0ffff113u +#define CYREG_SFLASH_AV_PAIRS_8B20 0x0ffff114u +#define CYREG_SFLASH_AV_PAIRS_8B21 0x0ffff115u +#define CYREG_SFLASH_AV_PAIRS_8B22 0x0ffff116u +#define CYREG_SFLASH_AV_PAIRS_8B23 0x0ffff117u +#define CYREG_SFLASH_AV_PAIRS_8B24 0x0ffff118u +#define CYREG_SFLASH_AV_PAIRS_8B25 0x0ffff119u +#define CYREG_SFLASH_AV_PAIRS_8B26 0x0ffff11au +#define CYREG_SFLASH_AV_PAIRS_8B27 0x0ffff11bu +#define CYREG_SFLASH_AV_PAIRS_8B28 0x0ffff11cu +#define CYREG_SFLASH_AV_PAIRS_8B29 0x0ffff11du +#define CYREG_SFLASH_AV_PAIRS_8B30 0x0ffff11eu +#define CYREG_SFLASH_AV_PAIRS_8B31 0x0ffff11fu +#define CYREG_SFLASH_AV_PAIRS_8B32 0x0ffff120u +#define CYREG_SFLASH_AV_PAIRS_8B33 0x0ffff121u +#define CYREG_SFLASH_AV_PAIRS_8B34 0x0ffff122u +#define CYREG_SFLASH_AV_PAIRS_8B35 0x0ffff123u +#define CYREG_SFLASH_AV_PAIRS_8B36 0x0ffff124u +#define CYREG_SFLASH_AV_PAIRS_8B37 0x0ffff125u +#define CYREG_SFLASH_AV_PAIRS_8B38 0x0ffff126u +#define CYREG_SFLASH_AV_PAIRS_8B39 0x0ffff127u +#define CYREG_SFLASH_AV_PAIRS_8B40 0x0ffff128u +#define CYREG_SFLASH_AV_PAIRS_8B41 0x0ffff129u +#define CYREG_SFLASH_AV_PAIRS_8B42 0x0ffff12au +#define CYREG_SFLASH_AV_PAIRS_8B43 0x0ffff12bu +#define CYREG_SFLASH_AV_PAIRS_8B44 0x0ffff12cu +#define CYREG_SFLASH_AV_PAIRS_8B45 0x0ffff12du +#define CYREG_SFLASH_AV_PAIRS_8B46 0x0ffff12eu +#define CYREG_SFLASH_AV_PAIRS_8B47 0x0ffff12fu +#define CYREG_SFLASH_AV_PAIRS_8B48 0x0ffff130u +#define CYREG_SFLASH_AV_PAIRS_8B49 0x0ffff131u +#define CYREG_SFLASH_AV_PAIRS_8B50 0x0ffff132u +#define CYREG_SFLASH_AV_PAIRS_8B51 0x0ffff133u +#define CYREG_SFLASH_AV_PAIRS_8B52 0x0ffff134u +#define CYREG_SFLASH_AV_PAIRS_8B53 0x0ffff135u +#define CYREG_SFLASH_AV_PAIRS_8B54 0x0ffff136u +#define CYREG_SFLASH_AV_PAIRS_8B55 0x0ffff137u +#define CYREG_SFLASH_AV_PAIRS_8B56 0x0ffff138u +#define CYREG_SFLASH_AV_PAIRS_8B57 0x0ffff139u +#define CYREG_SFLASH_AV_PAIRS_8B58 0x0ffff13au +#define CYREG_SFLASH_AV_PAIRS_8B59 0x0ffff13bu +#define CYREG_SFLASH_AV_PAIRS_8B60 0x0ffff13cu +#define CYREG_SFLASH_AV_PAIRS_8B61 0x0ffff13du +#define CYREG_SFLASH_AV_PAIRS_8B62 0x0ffff13eu +#define CYREG_SFLASH_AV_PAIRS_8B63 0x0ffff13fu +#define CYREG_SFLASH_AV_PAIRS_8B64 0x0ffff140u +#define CYREG_SFLASH_AV_PAIRS_8B65 0x0ffff141u +#define CYREG_SFLASH_AV_PAIRS_8B66 0x0ffff142u +#define CYREG_SFLASH_AV_PAIRS_8B67 0x0ffff143u +#define CYREG_SFLASH_AV_PAIRS_8B68 0x0ffff144u +#define CYREG_SFLASH_AV_PAIRS_8B69 0x0ffff145u +#define CYREG_SFLASH_AV_PAIRS_8B70 0x0ffff146u +#define CYREG_SFLASH_AV_PAIRS_8B71 0x0ffff147u +#define CYREG_SFLASH_AV_PAIRS_8B72 0x0ffff148u +#define CYREG_SFLASH_AV_PAIRS_8B73 0x0ffff149u +#define CYREG_SFLASH_AV_PAIRS_8B74 0x0ffff14au +#define CYREG_SFLASH_AV_PAIRS_8B75 0x0ffff14bu +#define CYREG_SFLASH_AV_PAIRS_8B76 0x0ffff14cu +#define CYREG_SFLASH_AV_PAIRS_8B77 0x0ffff14du +#define CYREG_SFLASH_AV_PAIRS_8B78 0x0ffff14eu +#define CYREG_SFLASH_AV_PAIRS_8B79 0x0ffff14fu +#define CYREG_SFLASH_AV_PAIRS_8B80 0x0ffff150u +#define CYREG_SFLASH_AV_PAIRS_8B81 0x0ffff151u +#define CYREG_SFLASH_AV_PAIRS_8B82 0x0ffff152u +#define CYREG_SFLASH_AV_PAIRS_8B83 0x0ffff153u +#define CYREG_SFLASH_AV_PAIRS_8B84 0x0ffff154u +#define CYREG_SFLASH_AV_PAIRS_8B85 0x0ffff155u +#define CYREG_SFLASH_AV_PAIRS_8B86 0x0ffff156u +#define CYREG_SFLASH_AV_PAIRS_8B87 0x0ffff157u +#define CYREG_SFLASH_AV_PAIRS_8B88 0x0ffff158u +#define CYREG_SFLASH_AV_PAIRS_8B89 0x0ffff159u +#define CYREG_SFLASH_AV_PAIRS_8B90 0x0ffff15au +#define CYREG_SFLASH_AV_PAIRS_8B91 0x0ffff15bu +#define CYREG_SFLASH_AV_PAIRS_8B92 0x0ffff15cu +#define CYREG_SFLASH_AV_PAIRS_8B93 0x0ffff15du +#define CYREG_SFLASH_AV_PAIRS_8B94 0x0ffff15eu +#define CYREG_SFLASH_AV_PAIRS_8B95 0x0ffff15fu +#define CYREG_SFLASH_AV_PAIRS_8B96 0x0ffff160u +#define CYREG_SFLASH_AV_PAIRS_8B97 0x0ffff161u +#define CYREG_SFLASH_AV_PAIRS_8B98 0x0ffff162u +#define CYREG_SFLASH_AV_PAIRS_8B99 0x0ffff163u +#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff164u +#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff165u +#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff166u +#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff167u +#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff168u +#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff169u +#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff16au +#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff16bu +#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff16cu +#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff16du +#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff16eu +#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff16fu +#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff170u +#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff171u +#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff172u +#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff173u +#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff174u +#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff175u +#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff176u +#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff177u +#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff178u +#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff179u +#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff17au +#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff17bu +#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff17cu +#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff17du +#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff17eu +#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff17fu +#define CYREG_SFLASH_AV_PAIRS_32B0 0x0ffff200u +#define CYFLD_SFLASH_DATA32__OFFSET 0x00000000u +#define CYFLD_SFLASH_DATA32__SIZE 0x00000020u +#define CYREG_SFLASH_AV_PAIRS_32B1 0x0ffff204u +#define CYREG_SFLASH_AV_PAIRS_32B2 0x0ffff208u +#define CYREG_SFLASH_AV_PAIRS_32B3 0x0ffff20cu +#define CYREG_SFLASH_AV_PAIRS_32B4 0x0ffff210u +#define CYREG_SFLASH_AV_PAIRS_32B5 0x0ffff214u +#define CYREG_SFLASH_AV_PAIRS_32B6 0x0ffff218u +#define CYREG_SFLASH_AV_PAIRS_32B7 0x0ffff21cu +#define CYREG_SFLASH_AV_PAIRS_32B8 0x0ffff220u +#define CYREG_SFLASH_AV_PAIRS_32B9 0x0ffff224u +#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff228u +#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff22cu +#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff230u +#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff234u +#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff238u +#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff23cu +#define CYREG_SFLASH_SILICON_ID 0x0ffff244u +#define CYFLD_SFLASH_ID__OFFSET 0x00000000u +#define CYFLD_SFLASH_ID__SIZE 0x00000010u +#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff250u +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000u +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000au +#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff252u +#define CYREG_SFLASH_SWD_CONFIG 0x0ffff254u +#define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000u +#define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001u +#define CYREG_SFLASH_SWD_LISTEN 0x0ffff258u +#define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000u +#define CYFLD_SFLASH_CYCLES__SIZE 0x00000020u +#define CYREG_SFLASH_FLASH_START 0x0ffff25cu +#define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000u +#define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020u +#define CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM1 0x0ffff260u +#define CYFLD_SFLASH_CSD_ADC_CAL_LSB__OFFSET 0x00000000u +#define CYFLD_SFLASH_CSD_ADC_CAL_LSB__SIZE 0x00000008u +#define CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM2 0x0ffff261u +#define CYFLD_SFLASH_CSD_ADC_CAL_MSB__OFFSET 0x00000000u +#define CYFLD_SFLASH_CSD_ADC_CAL_MSB__SIZE 0x00000008u +#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff264u +#define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000u +#define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010u +#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff266u +#define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000u +#define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010u +#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff270u +#define CYFLD_SFLASH_KEY8__OFFSET 0x00000000u +#define CYFLD_SFLASH_KEY8__SIZE 0x00000008u +#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff271u +#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff272u +#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff273u +#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff274u +#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff275u +#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff276u +#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff277u +#define CYREG_SFLASH_DIE_LOT0 0x0ffff278u +#define CYFLD_SFLASH_LOT__OFFSET 0x00000000u +#define CYFLD_SFLASH_LOT__SIZE 0x00000008u +#define CYREG_SFLASH_DIE_LOT1 0x0ffff279u +#define CYREG_SFLASH_DIE_LOT2 0x0ffff27au +#define CYREG_SFLASH_DIE_WAFER 0x0ffff27bu +#define CYFLD_SFLASH_WAFER__OFFSET 0x00000000u +#define CYFLD_SFLASH_WAFER__SIZE 0x00000008u +#define CYREG_SFLASH_DIE_X 0x0ffff27cu +#define CYFLD_SFLASH_X__OFFSET 0x00000000u +#define CYFLD_SFLASH_X__SIZE 0x00000008u +#define CYREG_SFLASH_DIE_Y 0x0ffff27du +#define CYFLD_SFLASH_Y__OFFSET 0x00000000u +#define CYFLD_SFLASH_Y__SIZE 0x00000008u +#define CYREG_SFLASH_DIE_SORT 0x0ffff27eu +#define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000u +#define CYFLD_SFLASH_S1_PASS__SIZE 0x00000001u +#define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000001u +#define CYFLD_SFLASH_S2_PASS__SIZE 0x00000001u +#define CYFLD_SFLASH_S3_PASS__OFFSET 0x00000002u +#define CYFLD_SFLASH_S3_PASS__SIZE 0x00000001u +#define CYFLD_SFLASH_CRI_PASS__OFFSET 0x00000003u +#define CYFLD_SFLASH_CRI_PASS__SIZE 0x00000001u +#define CYFLD_SFLASH_CHI_PASS__OFFSET 0x00000004u +#define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000001u +#define CYFLD_SFLASH_ENG_PASS__OFFSET 0x00000005u +#define CYFLD_SFLASH_ENG_PASS__SIZE 0x00000001u +#define CYREG_SFLASH_DIE_MINOR 0x0ffff27fu +#define CYFLD_SFLASH_MINOR__OFFSET 0x00000000u +#define CYFLD_SFLASH_MINOR__SIZE 0x00000008u +#define CYREG_SFLASH_IMO_TRIM_USBMODE_24 0x0ffff33eu +#define CYFLD_SFLASH_TRIM_24__OFFSET 0x00000000u +#define CYFLD_SFLASH_TRIM_24__SIZE 0x00000008u +#define CYREG_SFLASH_IMO_TRIM_USBMODE_48 0x0ffff33fu +#define CYREG_SFLASH_IMO_TCTRIM_LT0 0x0ffff34cu +#define CYFLD_SFLASH_STEPSIZE__OFFSET 0x00000000u +#define CYFLD_SFLASH_STEPSIZE__SIZE 0x00000005u +#define CYFLD_SFLASH_TCTRIM__OFFSET 0x00000005u +#define CYFLD_SFLASH_TCTRIM__SIZE 0x00000002u +#define CYREG_SFLASH_IMO_TCTRIM_LT1 0x0ffff34du +#define CYREG_SFLASH_IMO_TCTRIM_LT2 0x0ffff34eu +#define CYREG_SFLASH_IMO_TCTRIM_LT3 0x0ffff34fu +#define CYREG_SFLASH_IMO_TCTRIM_LT4 0x0ffff350u +#define CYREG_SFLASH_IMO_TCTRIM_LT5 0x0ffff351u +#define CYREG_SFLASH_IMO_TCTRIM_LT6 0x0ffff352u +#define CYREG_SFLASH_IMO_TCTRIM_LT7 0x0ffff353u +#define CYREG_SFLASH_IMO_TCTRIM_LT8 0x0ffff354u +#define CYREG_SFLASH_IMO_TCTRIM_LT9 0x0ffff355u +#define CYREG_SFLASH_IMO_TCTRIM_LT10 0x0ffff356u +#define CYREG_SFLASH_IMO_TCTRIM_LT11 0x0ffff357u +#define CYREG_SFLASH_IMO_TCTRIM_LT12 0x0ffff358u +#define CYREG_SFLASH_IMO_TCTRIM_LT13 0x0ffff359u +#define CYREG_SFLASH_IMO_TCTRIM_LT14 0x0ffff35au +#define CYREG_SFLASH_IMO_TCTRIM_LT15 0x0ffff35bu +#define CYREG_SFLASH_IMO_TCTRIM_LT16 0x0ffff35cu +#define CYREG_SFLASH_IMO_TCTRIM_LT17 0x0ffff35du +#define CYREG_SFLASH_IMO_TCTRIM_LT18 0x0ffff35eu +#define CYREG_SFLASH_IMO_TCTRIM_LT19 0x0ffff35fu +#define CYREG_SFLASH_IMO_TCTRIM_LT20 0x0ffff360u +#define CYREG_SFLASH_IMO_TCTRIM_LT21 0x0ffff361u +#define CYREG_SFLASH_IMO_TCTRIM_LT22 0x0ffff362u +#define CYREG_SFLASH_IMO_TCTRIM_LT23 0x0ffff363u +#define CYREG_SFLASH_IMO_TCTRIM_LT24 0x0ffff364u +#define CYREG_SFLASH_IMO_TRIM_LT0 0x0ffff365u +#define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000u +#define CYFLD_SFLASH_OFFSET__SIZE 0x00000008u +#define CYREG_SFLASH_IMO_TRIM_LT1 0x0ffff366u +#define CYREG_SFLASH_IMO_TRIM_LT2 0x0ffff367u +#define CYREG_SFLASH_IMO_TRIM_LT3 0x0ffff368u +#define CYREG_SFLASH_IMO_TRIM_LT4 0x0ffff369u +#define CYREG_SFLASH_IMO_TRIM_LT5 0x0ffff36au +#define CYREG_SFLASH_IMO_TRIM_LT6 0x0ffff36bu +#define CYREG_SFLASH_IMO_TRIM_LT7 0x0ffff36cu +#define CYREG_SFLASH_IMO_TRIM_LT8 0x0ffff36du +#define CYREG_SFLASH_IMO_TRIM_LT9 0x0ffff36eu +#define CYREG_SFLASH_IMO_TRIM_LT10 0x0ffff36fu +#define CYREG_SFLASH_IMO_TRIM_LT11 0x0ffff370u +#define CYREG_SFLASH_IMO_TRIM_LT12 0x0ffff371u +#define CYREG_SFLASH_IMO_TRIM_LT13 0x0ffff372u +#define CYREG_SFLASH_IMO_TRIM_LT14 0x0ffff373u +#define CYREG_SFLASH_IMO_TRIM_LT15 0x0ffff374u +#define CYREG_SFLASH_IMO_TRIM_LT16 0x0ffff375u +#define CYREG_SFLASH_IMO_TRIM_LT17 0x0ffff376u +#define CYREG_SFLASH_IMO_TRIM_LT18 0x0ffff377u +#define CYREG_SFLASH_IMO_TRIM_LT19 0x0ffff378u +#define CYREG_SFLASH_IMO_TRIM_LT20 0x0ffff379u +#define CYREG_SFLASH_IMO_TRIM_LT21 0x0ffff37au +#define CYREG_SFLASH_IMO_TRIM_LT22 0x0ffff37bu +#define CYREG_SFLASH_IMO_TRIM_LT23 0x0ffff37cu +#define CYREG_SFLASH_IMO_TRIM_LT24 0x0ffff37du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH0 0x0ffff400u +#define CYFLD_SFLASH_BYTE_MEM__OFFSET 0x00000000u +#define CYFLD_SFLASH_BYTE_MEM__SIZE 0x00000008u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1 0x0ffff401u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH2 0x0ffff402u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH3 0x0ffff403u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH4 0x0ffff404u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH5 0x0ffff405u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH6 0x0ffff406u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH7 0x0ffff407u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH8 0x0ffff408u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH9 0x0ffff409u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH10 0x0ffff40au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH11 0x0ffff40bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH12 0x0ffff40cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH13 0x0ffff40du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH14 0x0ffff40eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH15 0x0ffff40fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH16 0x0ffff410u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH17 0x0ffff411u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH18 0x0ffff412u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH19 0x0ffff413u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH20 0x0ffff414u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH21 0x0ffff415u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH22 0x0ffff416u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH23 0x0ffff417u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH24 0x0ffff418u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH25 0x0ffff419u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH26 0x0ffff41au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH27 0x0ffff41bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH28 0x0ffff41cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH29 0x0ffff41du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH30 0x0ffff41eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH31 0x0ffff41fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH32 0x0ffff420u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH33 0x0ffff421u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH34 0x0ffff422u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH35 0x0ffff423u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH36 0x0ffff424u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH37 0x0ffff425u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH38 0x0ffff426u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH39 0x0ffff427u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH40 0x0ffff428u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH41 0x0ffff429u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH42 0x0ffff42au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH43 0x0ffff42bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH44 0x0ffff42cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH45 0x0ffff42du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH46 0x0ffff42eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH47 0x0ffff42fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH48 0x0ffff430u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH49 0x0ffff431u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH50 0x0ffff432u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH51 0x0ffff433u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH52 0x0ffff434u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH53 0x0ffff435u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH54 0x0ffff436u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH55 0x0ffff437u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH56 0x0ffff438u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH57 0x0ffff439u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH58 0x0ffff43au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH59 0x0ffff43bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH60 0x0ffff43cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH61 0x0ffff43du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH62 0x0ffff43eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH63 0x0ffff43fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH64 0x0ffff440u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH65 0x0ffff441u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH66 0x0ffff442u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH67 0x0ffff443u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH68 0x0ffff444u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH69 0x0ffff445u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH70 0x0ffff446u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH71 0x0ffff447u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH72 0x0ffff448u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH73 0x0ffff449u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH74 0x0ffff44au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH75 0x0ffff44bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH76 0x0ffff44cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH77 0x0ffff44du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH78 0x0ffff44eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH79 0x0ffff44fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH80 0x0ffff450u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH81 0x0ffff451u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH82 0x0ffff452u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH83 0x0ffff453u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH84 0x0ffff454u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH85 0x0ffff455u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH86 0x0ffff456u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH87 0x0ffff457u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH88 0x0ffff458u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH89 0x0ffff459u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH90 0x0ffff45au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH91 0x0ffff45bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH92 0x0ffff45cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH93 0x0ffff45du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH94 0x0ffff45eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH95 0x0ffff45fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH96 0x0ffff460u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH97 0x0ffff461u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH98 0x0ffff462u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH99 0x0ffff463u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH100 0x0ffff464u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH101 0x0ffff465u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH102 0x0ffff466u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH103 0x0ffff467u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH104 0x0ffff468u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH105 0x0ffff469u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH106 0x0ffff46au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH107 0x0ffff46bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH108 0x0ffff46cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH109 0x0ffff46du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH110 0x0ffff46eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH111 0x0ffff46fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH112 0x0ffff470u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH113 0x0ffff471u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH114 0x0ffff472u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH115 0x0ffff473u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH116 0x0ffff474u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH117 0x0ffff475u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH118 0x0ffff476u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH119 0x0ffff477u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH120 0x0ffff478u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH121 0x0ffff479u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH122 0x0ffff47au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH123 0x0ffff47bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH124 0x0ffff47cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH125 0x0ffff47du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH126 0x0ffff47eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH127 0x0ffff47fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH128 0x0ffff480u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH129 0x0ffff481u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH130 0x0ffff482u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH131 0x0ffff483u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH132 0x0ffff484u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH133 0x0ffff485u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH134 0x0ffff486u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH135 0x0ffff487u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH136 0x0ffff488u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH137 0x0ffff489u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH138 0x0ffff48au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH139 0x0ffff48bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH140 0x0ffff48cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH141 0x0ffff48du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH142 0x0ffff48eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH143 0x0ffff48fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH144 0x0ffff490u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH145 0x0ffff491u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH146 0x0ffff492u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH147 0x0ffff493u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH148 0x0ffff494u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH149 0x0ffff495u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH150 0x0ffff496u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH151 0x0ffff497u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH152 0x0ffff498u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH153 0x0ffff499u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH154 0x0ffff49au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH155 0x0ffff49bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH156 0x0ffff49cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH157 0x0ffff49du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH158 0x0ffff49eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH159 0x0ffff49fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH160 0x0ffff4a0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH161 0x0ffff4a1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH162 0x0ffff4a2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH163 0x0ffff4a3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH164 0x0ffff4a4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH165 0x0ffff4a5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH166 0x0ffff4a6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH167 0x0ffff4a7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH168 0x0ffff4a8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH169 0x0ffff4a9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH170 0x0ffff4aau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH171 0x0ffff4abu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH172 0x0ffff4acu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH173 0x0ffff4adu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH174 0x0ffff4aeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH175 0x0ffff4afu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH176 0x0ffff4b0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH177 0x0ffff4b1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH178 0x0ffff4b2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH179 0x0ffff4b3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH180 0x0ffff4b4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH181 0x0ffff4b5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH182 0x0ffff4b6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH183 0x0ffff4b7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH184 0x0ffff4b8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH185 0x0ffff4b9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH186 0x0ffff4bau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH187 0x0ffff4bbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH188 0x0ffff4bcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH189 0x0ffff4bdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH190 0x0ffff4beu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH191 0x0ffff4bfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH192 0x0ffff4c0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH193 0x0ffff4c1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH194 0x0ffff4c2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH195 0x0ffff4c3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH196 0x0ffff4c4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH197 0x0ffff4c5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH198 0x0ffff4c6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH199 0x0ffff4c7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH200 0x0ffff4c8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH201 0x0ffff4c9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH202 0x0ffff4cau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH203 0x0ffff4cbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH204 0x0ffff4ccu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH205 0x0ffff4cdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH206 0x0ffff4ceu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH207 0x0ffff4cfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH208 0x0ffff4d0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH209 0x0ffff4d1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH210 0x0ffff4d2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH211 0x0ffff4d3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH212 0x0ffff4d4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH213 0x0ffff4d5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH214 0x0ffff4d6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH215 0x0ffff4d7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH216 0x0ffff4d8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH217 0x0ffff4d9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH218 0x0ffff4dau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH219 0x0ffff4dbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH220 0x0ffff4dcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH221 0x0ffff4ddu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH222 0x0ffff4deu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH223 0x0ffff4dfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH224 0x0ffff4e0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH225 0x0ffff4e1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH226 0x0ffff4e2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH227 0x0ffff4e3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH228 0x0ffff4e4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH229 0x0ffff4e5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH230 0x0ffff4e6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH231 0x0ffff4e7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH232 0x0ffff4e8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH233 0x0ffff4e9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH234 0x0ffff4eau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH235 0x0ffff4ebu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH236 0x0ffff4ecu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH237 0x0ffff4edu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH238 0x0ffff4eeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH239 0x0ffff4efu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH240 0x0ffff4f0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH241 0x0ffff4f1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH242 0x0ffff4f2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH243 0x0ffff4f3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH244 0x0ffff4f4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH245 0x0ffff4f5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH246 0x0ffff4f6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH247 0x0ffff4f7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH248 0x0ffff4f8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH249 0x0ffff4f9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH250 0x0ffff4fau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH251 0x0ffff4fbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH252 0x0ffff4fcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH253 0x0ffff4fdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH254 0x0ffff4feu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH255 0x0ffff4ffu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH256 0x0ffff500u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH257 0x0ffff501u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH258 0x0ffff502u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH259 0x0ffff503u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH260 0x0ffff504u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH261 0x0ffff505u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH262 0x0ffff506u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH263 0x0ffff507u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH264 0x0ffff508u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH265 0x0ffff509u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH266 0x0ffff50au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH267 0x0ffff50bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH268 0x0ffff50cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH269 0x0ffff50du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH270 0x0ffff50eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH271 0x0ffff50fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH272 0x0ffff510u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH273 0x0ffff511u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH274 0x0ffff512u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH275 0x0ffff513u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH276 0x0ffff514u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH277 0x0ffff515u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH278 0x0ffff516u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH279 0x0ffff517u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH280 0x0ffff518u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH281 0x0ffff519u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH282 0x0ffff51au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH283 0x0ffff51bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH284 0x0ffff51cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH285 0x0ffff51du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH286 0x0ffff51eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH287 0x0ffff51fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH288 0x0ffff520u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH289 0x0ffff521u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH290 0x0ffff522u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH291 0x0ffff523u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH292 0x0ffff524u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH293 0x0ffff525u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH294 0x0ffff526u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH295 0x0ffff527u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH296 0x0ffff528u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH297 0x0ffff529u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH298 0x0ffff52au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH299 0x0ffff52bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH300 0x0ffff52cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH301 0x0ffff52du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH302 0x0ffff52eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH303 0x0ffff52fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH304 0x0ffff530u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH305 0x0ffff531u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH306 0x0ffff532u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH307 0x0ffff533u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH308 0x0ffff534u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH309 0x0ffff535u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH310 0x0ffff536u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH311 0x0ffff537u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH312 0x0ffff538u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH313 0x0ffff539u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH314 0x0ffff53au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH315 0x0ffff53bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH316 0x0ffff53cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH317 0x0ffff53du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH318 0x0ffff53eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH319 0x0ffff53fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH320 0x0ffff540u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH321 0x0ffff541u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH322 0x0ffff542u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH323 0x0ffff543u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH324 0x0ffff544u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH325 0x0ffff545u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH326 0x0ffff546u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH327 0x0ffff547u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH328 0x0ffff548u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH329 0x0ffff549u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH330 0x0ffff54au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH331 0x0ffff54bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH332 0x0ffff54cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH333 0x0ffff54du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH334 0x0ffff54eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH335 0x0ffff54fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH336 0x0ffff550u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH337 0x0ffff551u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH338 0x0ffff552u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH339 0x0ffff553u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH340 0x0ffff554u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH341 0x0ffff555u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH342 0x0ffff556u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH343 0x0ffff557u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH344 0x0ffff558u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH345 0x0ffff559u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH346 0x0ffff55au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH347 0x0ffff55bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH348 0x0ffff55cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH349 0x0ffff55du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH350 0x0ffff55eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH351 0x0ffff55fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH352 0x0ffff560u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH353 0x0ffff561u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH354 0x0ffff562u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH355 0x0ffff563u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH356 0x0ffff564u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH357 0x0ffff565u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH358 0x0ffff566u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH359 0x0ffff567u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH360 0x0ffff568u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH361 0x0ffff569u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH362 0x0ffff56au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH363 0x0ffff56bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH364 0x0ffff56cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH365 0x0ffff56du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH366 0x0ffff56eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH367 0x0ffff56fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH368 0x0ffff570u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH369 0x0ffff571u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH370 0x0ffff572u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH371 0x0ffff573u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH372 0x0ffff574u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH373 0x0ffff575u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH374 0x0ffff576u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH375 0x0ffff577u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH376 0x0ffff578u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH377 0x0ffff579u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH378 0x0ffff57au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH379 0x0ffff57bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH380 0x0ffff57cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH381 0x0ffff57du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH382 0x0ffff57eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH383 0x0ffff57fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH384 0x0ffff580u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH385 0x0ffff581u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH386 0x0ffff582u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH387 0x0ffff583u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH388 0x0ffff584u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH389 0x0ffff585u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH390 0x0ffff586u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH391 0x0ffff587u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH392 0x0ffff588u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH393 0x0ffff589u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH394 0x0ffff58au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH395 0x0ffff58bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH396 0x0ffff58cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH397 0x0ffff58du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH398 0x0ffff58eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH399 0x0ffff58fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH400 0x0ffff590u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH401 0x0ffff591u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH402 0x0ffff592u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH403 0x0ffff593u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH404 0x0ffff594u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH405 0x0ffff595u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH406 0x0ffff596u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH407 0x0ffff597u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH408 0x0ffff598u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH409 0x0ffff599u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH410 0x0ffff59au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH411 0x0ffff59bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH412 0x0ffff59cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH413 0x0ffff59du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH414 0x0ffff59eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH415 0x0ffff59fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH416 0x0ffff5a0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH417 0x0ffff5a1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH418 0x0ffff5a2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH419 0x0ffff5a3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH420 0x0ffff5a4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH421 0x0ffff5a5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH422 0x0ffff5a6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH423 0x0ffff5a7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH424 0x0ffff5a8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH425 0x0ffff5a9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH426 0x0ffff5aau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH427 0x0ffff5abu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH428 0x0ffff5acu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH429 0x0ffff5adu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH430 0x0ffff5aeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH431 0x0ffff5afu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH432 0x0ffff5b0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH433 0x0ffff5b1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH434 0x0ffff5b2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH435 0x0ffff5b3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH436 0x0ffff5b4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH437 0x0ffff5b5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH438 0x0ffff5b6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH439 0x0ffff5b7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH440 0x0ffff5b8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH441 0x0ffff5b9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH442 0x0ffff5bau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH443 0x0ffff5bbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH444 0x0ffff5bcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH445 0x0ffff5bdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH446 0x0ffff5beu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH447 0x0ffff5bfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH448 0x0ffff5c0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH449 0x0ffff5c1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH450 0x0ffff5c2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH451 0x0ffff5c3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH452 0x0ffff5c4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH453 0x0ffff5c5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH454 0x0ffff5c6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH455 0x0ffff5c7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH456 0x0ffff5c8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH457 0x0ffff5c9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH458 0x0ffff5cau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH459 0x0ffff5cbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH460 0x0ffff5ccu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH461 0x0ffff5cdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH462 0x0ffff5ceu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH463 0x0ffff5cfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH464 0x0ffff5d0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH465 0x0ffff5d1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH466 0x0ffff5d2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH467 0x0ffff5d3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH468 0x0ffff5d4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH469 0x0ffff5d5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH470 0x0ffff5d6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH471 0x0ffff5d7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH472 0x0ffff5d8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH473 0x0ffff5d9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH474 0x0ffff5dau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH475 0x0ffff5dbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH476 0x0ffff5dcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH477 0x0ffff5ddu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH478 0x0ffff5deu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH479 0x0ffff5dfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH480 0x0ffff5e0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH481 0x0ffff5e1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH482 0x0ffff5e2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH483 0x0ffff5e3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH484 0x0ffff5e4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH485 0x0ffff5e5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH486 0x0ffff5e6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH487 0x0ffff5e7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH488 0x0ffff5e8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH489 0x0ffff5e9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH490 0x0ffff5eau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH491 0x0ffff5ebu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH492 0x0ffff5ecu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH493 0x0ffff5edu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH494 0x0ffff5eeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH495 0x0ffff5efu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH496 0x0ffff5f0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH497 0x0ffff5f1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH498 0x0ffff5f2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH499 0x0ffff5f3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH500 0x0ffff5f4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH501 0x0ffff5f5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH502 0x0ffff5f6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH503 0x0ffff5f7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH504 0x0ffff5f8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH505 0x0ffff5f9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH506 0x0ffff5fau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH507 0x0ffff5fbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH508 0x0ffff5fcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH509 0x0ffff5fdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH510 0x0ffff5feu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH511 0x0ffff5ffu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH512 0x0ffff600u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH513 0x0ffff601u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH514 0x0ffff602u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH515 0x0ffff603u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH516 0x0ffff604u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH517 0x0ffff605u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH518 0x0ffff606u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH519 0x0ffff607u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH520 0x0ffff608u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH521 0x0ffff609u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH522 0x0ffff60au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH523 0x0ffff60bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH524 0x0ffff60cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH525 0x0ffff60du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH526 0x0ffff60eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH527 0x0ffff60fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH528 0x0ffff610u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH529 0x0ffff611u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH530 0x0ffff612u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH531 0x0ffff613u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH532 0x0ffff614u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH533 0x0ffff615u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH534 0x0ffff616u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH535 0x0ffff617u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH536 0x0ffff618u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH537 0x0ffff619u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH538 0x0ffff61au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH539 0x0ffff61bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH540 0x0ffff61cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH541 0x0ffff61du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH542 0x0ffff61eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH543 0x0ffff61fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH544 0x0ffff620u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH545 0x0ffff621u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH546 0x0ffff622u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH547 0x0ffff623u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH548 0x0ffff624u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH549 0x0ffff625u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH550 0x0ffff626u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH551 0x0ffff627u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH552 0x0ffff628u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH553 0x0ffff629u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH554 0x0ffff62au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH555 0x0ffff62bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH556 0x0ffff62cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH557 0x0ffff62du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH558 0x0ffff62eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH559 0x0ffff62fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH560 0x0ffff630u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH561 0x0ffff631u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH562 0x0ffff632u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH563 0x0ffff633u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH564 0x0ffff634u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH565 0x0ffff635u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH566 0x0ffff636u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH567 0x0ffff637u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH568 0x0ffff638u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH569 0x0ffff639u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH570 0x0ffff63au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH571 0x0ffff63bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH572 0x0ffff63cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH573 0x0ffff63du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH574 0x0ffff63eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH575 0x0ffff63fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH576 0x0ffff640u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH577 0x0ffff641u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH578 0x0ffff642u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH579 0x0ffff643u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH580 0x0ffff644u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH581 0x0ffff645u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH582 0x0ffff646u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH583 0x0ffff647u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH584 0x0ffff648u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH585 0x0ffff649u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH586 0x0ffff64au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH587 0x0ffff64bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH588 0x0ffff64cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH589 0x0ffff64du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH590 0x0ffff64eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH591 0x0ffff64fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH592 0x0ffff650u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH593 0x0ffff651u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH594 0x0ffff652u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH595 0x0ffff653u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH596 0x0ffff654u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH597 0x0ffff655u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH598 0x0ffff656u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH599 0x0ffff657u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH600 0x0ffff658u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH601 0x0ffff659u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH602 0x0ffff65au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH603 0x0ffff65bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH604 0x0ffff65cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH605 0x0ffff65du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH606 0x0ffff65eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH607 0x0ffff65fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH608 0x0ffff660u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH609 0x0ffff661u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH610 0x0ffff662u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH611 0x0ffff663u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH612 0x0ffff664u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH613 0x0ffff665u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH614 0x0ffff666u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH615 0x0ffff667u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH616 0x0ffff668u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH617 0x0ffff669u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH618 0x0ffff66au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH619 0x0ffff66bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH620 0x0ffff66cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH621 0x0ffff66du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH622 0x0ffff66eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH623 0x0ffff66fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH624 0x0ffff670u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH625 0x0ffff671u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH626 0x0ffff672u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH627 0x0ffff673u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH628 0x0ffff674u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH629 0x0ffff675u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH630 0x0ffff676u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH631 0x0ffff677u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH632 0x0ffff678u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH633 0x0ffff679u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH634 0x0ffff67au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH635 0x0ffff67bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH636 0x0ffff67cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH637 0x0ffff67du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH638 0x0ffff67eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH639 0x0ffff67fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH640 0x0ffff680u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH641 0x0ffff681u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH642 0x0ffff682u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH643 0x0ffff683u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH644 0x0ffff684u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH645 0x0ffff685u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH646 0x0ffff686u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH647 0x0ffff687u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH648 0x0ffff688u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH649 0x0ffff689u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH650 0x0ffff68au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH651 0x0ffff68bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH652 0x0ffff68cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH653 0x0ffff68du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH654 0x0ffff68eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH655 0x0ffff68fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH656 0x0ffff690u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH657 0x0ffff691u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH658 0x0ffff692u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH659 0x0ffff693u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH660 0x0ffff694u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH661 0x0ffff695u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH662 0x0ffff696u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH663 0x0ffff697u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH664 0x0ffff698u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH665 0x0ffff699u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH666 0x0ffff69au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH667 0x0ffff69bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH668 0x0ffff69cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH669 0x0ffff69du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH670 0x0ffff69eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH671 0x0ffff69fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH672 0x0ffff6a0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH673 0x0ffff6a1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH674 0x0ffff6a2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH675 0x0ffff6a3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH676 0x0ffff6a4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH677 0x0ffff6a5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH678 0x0ffff6a6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH679 0x0ffff6a7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH680 0x0ffff6a8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH681 0x0ffff6a9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH682 0x0ffff6aau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH683 0x0ffff6abu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH684 0x0ffff6acu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH685 0x0ffff6adu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH686 0x0ffff6aeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH687 0x0ffff6afu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH688 0x0ffff6b0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH689 0x0ffff6b1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH690 0x0ffff6b2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH691 0x0ffff6b3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH692 0x0ffff6b4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH693 0x0ffff6b5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH694 0x0ffff6b6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH695 0x0ffff6b7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH696 0x0ffff6b8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH697 0x0ffff6b9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH698 0x0ffff6bau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH699 0x0ffff6bbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH700 0x0ffff6bcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH701 0x0ffff6bdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH702 0x0ffff6beu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH703 0x0ffff6bfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH704 0x0ffff6c0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH705 0x0ffff6c1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH706 0x0ffff6c2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH707 0x0ffff6c3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH708 0x0ffff6c4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH709 0x0ffff6c5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH710 0x0ffff6c6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH711 0x0ffff6c7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH712 0x0ffff6c8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH713 0x0ffff6c9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH714 0x0ffff6cau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH715 0x0ffff6cbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH716 0x0ffff6ccu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH717 0x0ffff6cdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH718 0x0ffff6ceu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH719 0x0ffff6cfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH720 0x0ffff6d0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH721 0x0ffff6d1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH722 0x0ffff6d2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH723 0x0ffff6d3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH724 0x0ffff6d4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH725 0x0ffff6d5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH726 0x0ffff6d6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH727 0x0ffff6d7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH728 0x0ffff6d8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH729 0x0ffff6d9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH730 0x0ffff6dau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH731 0x0ffff6dbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH732 0x0ffff6dcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH733 0x0ffff6ddu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH734 0x0ffff6deu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH735 0x0ffff6dfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH736 0x0ffff6e0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH737 0x0ffff6e1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH738 0x0ffff6e2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH739 0x0ffff6e3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH740 0x0ffff6e4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH741 0x0ffff6e5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH742 0x0ffff6e6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH743 0x0ffff6e7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH744 0x0ffff6e8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH745 0x0ffff6e9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH746 0x0ffff6eau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH747 0x0ffff6ebu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH748 0x0ffff6ecu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH749 0x0ffff6edu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH750 0x0ffff6eeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH751 0x0ffff6efu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH752 0x0ffff6f0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH753 0x0ffff6f1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH754 0x0ffff6f2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH755 0x0ffff6f3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH756 0x0ffff6f4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH757 0x0ffff6f5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH758 0x0ffff6f6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH759 0x0ffff6f7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH760 0x0ffff6f8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH761 0x0ffff6f9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH762 0x0ffff6fau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH763 0x0ffff6fbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH764 0x0ffff6fcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH765 0x0ffff6fdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH766 0x0ffff6feu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH767 0x0ffff6ffu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH768 0x0ffff700u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH769 0x0ffff701u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH770 0x0ffff702u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH771 0x0ffff703u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH772 0x0ffff704u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH773 0x0ffff705u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH774 0x0ffff706u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH775 0x0ffff707u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH776 0x0ffff708u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH777 0x0ffff709u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH778 0x0ffff70au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH779 0x0ffff70bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH780 0x0ffff70cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH781 0x0ffff70du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH782 0x0ffff70eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH783 0x0ffff70fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH784 0x0ffff710u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH785 0x0ffff711u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH786 0x0ffff712u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH787 0x0ffff713u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH788 0x0ffff714u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH789 0x0ffff715u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH790 0x0ffff716u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH791 0x0ffff717u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH792 0x0ffff718u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH793 0x0ffff719u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH794 0x0ffff71au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH795 0x0ffff71bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH796 0x0ffff71cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH797 0x0ffff71du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH798 0x0ffff71eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH799 0x0ffff71fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH800 0x0ffff720u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH801 0x0ffff721u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH802 0x0ffff722u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH803 0x0ffff723u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH804 0x0ffff724u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH805 0x0ffff725u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH806 0x0ffff726u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH807 0x0ffff727u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH808 0x0ffff728u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH809 0x0ffff729u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH810 0x0ffff72au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH811 0x0ffff72bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH812 0x0ffff72cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH813 0x0ffff72du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH814 0x0ffff72eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH815 0x0ffff72fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH816 0x0ffff730u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH817 0x0ffff731u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH818 0x0ffff732u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH819 0x0ffff733u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH820 0x0ffff734u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH821 0x0ffff735u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH822 0x0ffff736u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH823 0x0ffff737u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH824 0x0ffff738u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH825 0x0ffff739u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH826 0x0ffff73au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH827 0x0ffff73bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH828 0x0ffff73cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH829 0x0ffff73du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH830 0x0ffff73eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH831 0x0ffff73fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH832 0x0ffff740u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH833 0x0ffff741u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH834 0x0ffff742u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH835 0x0ffff743u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH836 0x0ffff744u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH837 0x0ffff745u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH838 0x0ffff746u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH839 0x0ffff747u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH840 0x0ffff748u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH841 0x0ffff749u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH842 0x0ffff74au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH843 0x0ffff74bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH844 0x0ffff74cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH845 0x0ffff74du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH846 0x0ffff74eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH847 0x0ffff74fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH848 0x0ffff750u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH849 0x0ffff751u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH850 0x0ffff752u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH851 0x0ffff753u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH852 0x0ffff754u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH853 0x0ffff755u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH854 0x0ffff756u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH855 0x0ffff757u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH856 0x0ffff758u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH857 0x0ffff759u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH858 0x0ffff75au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH859 0x0ffff75bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH860 0x0ffff75cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH861 0x0ffff75du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH862 0x0ffff75eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH863 0x0ffff75fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH864 0x0ffff760u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH865 0x0ffff761u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH866 0x0ffff762u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH867 0x0ffff763u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH868 0x0ffff764u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH869 0x0ffff765u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH870 0x0ffff766u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH871 0x0ffff767u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH872 0x0ffff768u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH873 0x0ffff769u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH874 0x0ffff76au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH875 0x0ffff76bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH876 0x0ffff76cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH877 0x0ffff76du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH878 0x0ffff76eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH879 0x0ffff76fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH880 0x0ffff770u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH881 0x0ffff771u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH882 0x0ffff772u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH883 0x0ffff773u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH884 0x0ffff774u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH885 0x0ffff775u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH886 0x0ffff776u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH887 0x0ffff777u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH888 0x0ffff778u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH889 0x0ffff779u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH890 0x0ffff77au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH891 0x0ffff77bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH892 0x0ffff77cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH893 0x0ffff77du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH894 0x0ffff77eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH895 0x0ffff77fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH896 0x0ffff780u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH897 0x0ffff781u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH898 0x0ffff782u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH899 0x0ffff783u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH900 0x0ffff784u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH901 0x0ffff785u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH902 0x0ffff786u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH903 0x0ffff787u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH904 0x0ffff788u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH905 0x0ffff789u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH906 0x0ffff78au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH907 0x0ffff78bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH908 0x0ffff78cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH909 0x0ffff78du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH910 0x0ffff78eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH911 0x0ffff78fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH912 0x0ffff790u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH913 0x0ffff791u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH914 0x0ffff792u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH915 0x0ffff793u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH916 0x0ffff794u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH917 0x0ffff795u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH918 0x0ffff796u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH919 0x0ffff797u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH920 0x0ffff798u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH921 0x0ffff799u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH922 0x0ffff79au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH923 0x0ffff79bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH924 0x0ffff79cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH925 0x0ffff79du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH926 0x0ffff79eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH927 0x0ffff79fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH928 0x0ffff7a0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH929 0x0ffff7a1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH930 0x0ffff7a2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH931 0x0ffff7a3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH932 0x0ffff7a4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH933 0x0ffff7a5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH934 0x0ffff7a6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH935 0x0ffff7a7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH936 0x0ffff7a8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH937 0x0ffff7a9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH938 0x0ffff7aau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH939 0x0ffff7abu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH940 0x0ffff7acu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH941 0x0ffff7adu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH942 0x0ffff7aeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH943 0x0ffff7afu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH944 0x0ffff7b0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH945 0x0ffff7b1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH946 0x0ffff7b2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH947 0x0ffff7b3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH948 0x0ffff7b4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH949 0x0ffff7b5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH950 0x0ffff7b6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH951 0x0ffff7b7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH952 0x0ffff7b8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH953 0x0ffff7b9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH954 0x0ffff7bau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH955 0x0ffff7bbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH956 0x0ffff7bcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH957 0x0ffff7bdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH958 0x0ffff7beu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH959 0x0ffff7bfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH960 0x0ffff7c0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH961 0x0ffff7c1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH962 0x0ffff7c2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH963 0x0ffff7c3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH964 0x0ffff7c4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH965 0x0ffff7c5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH966 0x0ffff7c6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH967 0x0ffff7c7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH968 0x0ffff7c8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH969 0x0ffff7c9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH970 0x0ffff7cau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH971 0x0ffff7cbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH972 0x0ffff7ccu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH973 0x0ffff7cdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH974 0x0ffff7ceu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH975 0x0ffff7cfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH976 0x0ffff7d0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH977 0x0ffff7d1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH978 0x0ffff7d2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH979 0x0ffff7d3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH980 0x0ffff7d4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH981 0x0ffff7d5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH982 0x0ffff7d6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH983 0x0ffff7d7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH984 0x0ffff7d8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH985 0x0ffff7d9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH986 0x0ffff7dau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH987 0x0ffff7dbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH988 0x0ffff7dcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH989 0x0ffff7ddu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH990 0x0ffff7deu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH991 0x0ffff7dfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH992 0x0ffff7e0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH993 0x0ffff7e1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH994 0x0ffff7e2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH995 0x0ffff7e3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH996 0x0ffff7e4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH997 0x0ffff7e5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH998 0x0ffff7e6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH999 0x0ffff7e7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1000 0x0ffff7e8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1001 0x0ffff7e9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1002 0x0ffff7eau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1003 0x0ffff7ebu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1004 0x0ffff7ecu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1005 0x0ffff7edu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1006 0x0ffff7eeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1007 0x0ffff7efu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1008 0x0ffff7f0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1009 0x0ffff7f1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1010 0x0ffff7f2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1011 0x0ffff7f3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1012 0x0ffff7f4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1013 0x0ffff7f5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1014 0x0ffff7f6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1015 0x0ffff7f7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1016 0x0ffff7f8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1017 0x0ffff7f9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1018 0x0ffff7fau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1019 0x0ffff7fbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1020 0x0ffff7fcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1021 0x0ffff7fdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1022 0x0ffff7feu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1023 0x0ffff7ffu +#define CYDEV_ROM_BASE 0x10000000u +#define CYDEV_ROM_SIZE 0x00002000u +#define CYREG_ROM_DATA_MBASE 0x10000000u +#define CYREG_ROM_DATA_MSIZE 0x00002000u +#define CYDEV_SRAM_BASE 0x20000000u +#define CYDEV_SRAM_SIZE 0x00004000u +#define CYREG_SRAM_DATA_MBASE 0x20000000u +#define CYREG_SRAM_DATA_MSIZE 0x00004000u +#define CYDEV_PERI_BASE 0x40010000u +#define CYDEV_PERI_SIZE 0x00010000u +#define CYREG_PERI_DIV_CMD 0x40010000u +#define CYFLD_PERI_SEL_DIV__OFFSET 0x00000000u +#define CYFLD_PERI_SEL_DIV__SIZE 0x00000006u +#define CYFLD_PERI_SEL_TYPE__OFFSET 0x00000006u +#define CYFLD_PERI_SEL_TYPE__SIZE 0x00000002u +#define CYFLD_PERI_PA_SEL_DIV__OFFSET 0x00000008u +#define CYFLD_PERI_PA_SEL_DIV__SIZE 0x00000006u +#define CYFLD_PERI_PA_SEL_TYPE__OFFSET 0x0000000eu +#define CYFLD_PERI_PA_SEL_TYPE__SIZE 0x00000002u +#define CYFLD_PERI_DISABLE__OFFSET 0x0000001eu +#define CYFLD_PERI_DISABLE__SIZE 0x00000001u +#define CYFLD_PERI_ENABLE__OFFSET 0x0000001fu +#define CYFLD_PERI_ENABLE__SIZE 0x00000001u +#define CYREG_PERI_PCLK_CTL0 0x40010100u +/* Duplicate field name in PERI: SEL_DIV [3:0] (previous: [5:0]) */ +#define CYREG_PERI_PCLK_CTL1 0x40010104u +#define CYREG_PERI_PCLK_CTL2 0x40010108u +#define CYREG_PERI_PCLK_CTL3 0x4001010cu +#define CYREG_PERI_PCLK_CTL4 0x40010110u +#define CYREG_PERI_PCLK_CTL5 0x40010114u +#define CYREG_PERI_PCLK_CTL6 0x40010118u +#define CYREG_PERI_PCLK_CTL7 0x4001011cu +#define CYREG_PERI_PCLK_CTL8 0x40010120u +#define CYREG_PERI_PCLK_CTL9 0x40010124u +#define CYREG_PERI_PCLK_CTL10 0x40010128u +#define CYREG_PERI_PCLK_CTL11 0x4001012cu +#define CYREG_PERI_PCLK_CTL12 0x40010130u +#define CYREG_PERI_PCLK_CTL13 0x40010134u +#define CYREG_PERI_PCLK_CTL14 0x40010138u +#define CYREG_PERI_PCLK_CTL15 0x4001013cu +#define CYREG_PERI_PCLK_CTL16 0x40010140u +#define CYREG_PERI_PCLK_CTL17 0x40010144u +#define CYREG_PERI_PCLK_CTL18 0x40010148u +#define CYREG_PERI_DIV_16_CTL0 0x40010300u +#define CYFLD_PERI_EN__OFFSET 0x00000000u +#define CYFLD_PERI_EN__SIZE 0x00000001u +#define CYFLD_PERI_INT16_DIV__OFFSET 0x00000008u +#define CYFLD_PERI_INT16_DIV__SIZE 0x00000010u +#define CYREG_PERI_DIV_16_CTL1 0x40010304u +#define CYREG_PERI_DIV_16_CTL2 0x40010308u +#define CYREG_PERI_DIV_16_CTL3 0x4001030cu +#define CYREG_PERI_DIV_16_CTL4 0x40010310u +#define CYREG_PERI_DIV_16_CTL5 0x40010314u +#define CYREG_PERI_DIV_16_CTL6 0x40010318u +#define CYREG_PERI_DIV_16_CTL7 0x4001031cu +#define CYREG_PERI_DIV_16_CTL8 0x40010320u +#define CYREG_PERI_DIV_16_CTL9 0x40010324u +#define CYREG_PERI_DIV_16_CTL10 0x40010328u +#define CYREG_PERI_DIV_16_CTL11 0x4001032cu +#define CYREG_PERI_DIV_16_5_CTL0 0x40010400u +#define CYFLD_PERI_FRAC5_DIV__OFFSET 0x00000003u +#define CYFLD_PERI_FRAC5_DIV__SIZE 0x00000005u +#define CYREG_PERI_DIV_16_5_CTL1 0x40010404u +#define CYREG_PERI_DIV_16_5_CTL2 0x40010408u +#define CYREG_PERI_DIV_16_5_CTL3 0x4001040cu +#define CYREG_PERI_DIV_16_5_CTL4 0x40010410u +#define CYREG_PERI_DIV_24_5_CTL 0x40010500u +#define CYFLD_PERI_INT24_DIV__OFFSET 0x00000008u +#define CYFLD_PERI_INT24_DIV__SIZE 0x00000018u +#define CYREG_PERI_TR_CTL 0x40010600u +#define CYFLD_PERI_TR_SEL__OFFSET 0x00000000u +#define CYFLD_PERI_TR_SEL__SIZE 0x00000007u +#define CYFLD_PERI_TR_GROUP__OFFSET 0x00000008u +#define CYFLD_PERI_TR_GROUP__SIZE 0x00000004u +#define CYFLD_PERI_TR_COUNT__OFFSET 0x00000010u +#define CYFLD_PERI_TR_COUNT__SIZE 0x00000008u +#define CYFLD_PERI_TR_OUT__OFFSET 0x0000001eu +#define CYFLD_PERI_TR_OUT__SIZE 0x00000001u +#define CYFLD_PERI_TR_ACT__OFFSET 0x0000001fu +#define CYFLD_PERI_TR_ACT__SIZE 0x00000001u +#define CYDEV_PERI_TR_GROUP0_BASE 0x40012000u +#define CYDEV_PERI_TR_GROUP0_SIZE 0x00000200u +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL0 0x40012000u +#define CYFLD_PERI_TR_GROUP_SEL__OFFSET 0x00000000u +#define CYFLD_PERI_TR_GROUP_SEL__SIZE 0x00000006u +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL1 0x40012004u +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL2 0x40012008u +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL3 0x4001200cu +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL4 0x40012010u +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL5 0x40012014u +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL6 0x40012018u +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL7 0x4001201cu +#define CYDEV_PERI_TR_GROUP1_BASE 0x40012200u +#define CYDEV_PERI_TR_GROUP1_SIZE 0x00000200u +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL0 0x40012200u +/* Duplicate field name in PERI_TR_GROUP: SEL [4:0] (previous: [5:0]) */ +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL1 0x40012204u +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL2 0x40012208u +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL3 0x4001220cu +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL4 0x40012210u +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL5 0x40012214u +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL6 0x40012218u +#define CYDEV_PERI_TR_GROUP2_BASE 0x40012400u +#define CYDEV_PERI_TR_GROUP2_SIZE 0x00000200u +#define CYREG_PERI_TR_GROUP2_TR_OUT_CTL 0x40012400u +/* Duplicate field name in PERI_TR_GROUP: SEL [5:0] (previous: [4:0]) */ +#define CYDEV_PERI_TR_GROUP3_BASE 0x40012600u +#define CYDEV_PERI_TR_GROUP3_SIZE 0x00000200u +#define CYREG_PERI_TR_GROUP3_TR_OUT_CTL 0x40012600u +/* Duplicate field name in PERI_TR_GROUP: SEL [3:0] (previous: [5:0]) */ +#define CYDEV_HSIOM_BASE 0x40020000u +#define CYDEV_HSIOM_SIZE 0x00004000u +#define CYREG_HSIOM_PORT_SEL0 0x40020000u +#define CYFLD_HSIOM_IO0_SEL__OFFSET 0x00000000u +#define CYFLD_HSIOM_IO0_SEL__SIZE 0x00000004u +#define CYVAL_HSIOM_IO0_SEL_GPIO 0x00000000u +#define CYVAL_HSIOM_IO0_SEL_GPIO_DSI 0x00000001u +#define CYVAL_HSIOM_IO0_SEL_DSI_DSI 0x00000002u +#define CYVAL_HSIOM_IO0_SEL_DSI_GPIO 0x00000003u +#define CYVAL_HSIOM_IO0_SEL_CSD_SENSE 0x00000004u +#define CYVAL_HSIOM_IO0_SEL_CSD_SHIELD 0x00000005u +#define CYVAL_HSIOM_IO0_SEL_AMUXA 0x00000006u +#define CYVAL_HSIOM_IO0_SEL_AMUXB 0x00000007u +#define CYVAL_HSIOM_IO0_SEL_ACT_0 0x00000008u +#define CYVAL_HSIOM_IO0_SEL_ACT_1 0x00000009u +#define CYVAL_HSIOM_IO0_SEL_ACT_2 0x0000000au +#define CYVAL_HSIOM_IO0_SEL_ACT_3 0x0000000bu +#define CYVAL_HSIOM_IO0_SEL_LCD_COM 0x0000000cu +#define CYVAL_HSIOM_IO0_SEL_LCD_SEG 0x0000000du +#define CYVAL_HSIOM_IO0_SEL_DS_0 0x0000000cu +#define CYVAL_HSIOM_IO0_SEL_DS_1 0x0000000du +#define CYVAL_HSIOM_IO0_SEL_DS_2 0x0000000eu +#define CYVAL_HSIOM_IO0_SEL_DS_3 0x0000000fu +#define CYFLD_HSIOM_IO1_SEL__OFFSET 0x00000004u +#define CYFLD_HSIOM_IO1_SEL__SIZE 0x00000004u +#define CYFLD_HSIOM_IO2_SEL__OFFSET 0x00000008u +#define CYFLD_HSIOM_IO2_SEL__SIZE 0x00000004u +#define CYFLD_HSIOM_IO3_SEL__OFFSET 0x0000000cu +#define CYFLD_HSIOM_IO3_SEL__SIZE 0x00000004u +#define CYFLD_HSIOM_IO4_SEL__OFFSET 0x00000010u +#define CYFLD_HSIOM_IO4_SEL__SIZE 0x00000004u +#define CYFLD_HSIOM_IO5_SEL__OFFSET 0x00000014u +#define CYFLD_HSIOM_IO5_SEL__SIZE 0x00000004u +#define CYFLD_HSIOM_IO6_SEL__OFFSET 0x00000018u +#define CYFLD_HSIOM_IO6_SEL__SIZE 0x00000004u +#define CYFLD_HSIOM_IO7_SEL__OFFSET 0x0000001cu +#define CYFLD_HSIOM_IO7_SEL__SIZE 0x00000004u +#define CYREG_HSIOM_PORT_SEL1 0x40020100u +#define CYREG_HSIOM_PORT_SEL2 0x40020200u +#define CYREG_HSIOM_PORT_SEL3 0x40020300u +#define CYREG_HSIOM_PORT_SEL4 0x40020400u +#define CYREG_HSIOM_PORT_SEL5 0x40020500u +#define CYREG_HSIOM_PORT_SEL6 0x40020600u +#define CYREG_HSIOM_PORT_SEL7 0x40020700u +#define CYREG_HSIOM_AMUX_SPLIT_CTL0 0x40022100u +#define CYFLD_HSIOM_SWITCH_AA_SL__OFFSET 0x00000000u +#define CYFLD_HSIOM_SWITCH_AA_SL__SIZE 0x00000001u +#define CYFLD_HSIOM_SWITCH_AA_SR__OFFSET 0x00000001u +#define CYFLD_HSIOM_SWITCH_AA_SR__SIZE 0x00000001u +#define CYFLD_HSIOM_SWITCH_AA_S0__OFFSET 0x00000002u +#define CYFLD_HSIOM_SWITCH_AA_S0__SIZE 0x00000001u +#define CYFLD_HSIOM_SWITCH_BB_SL__OFFSET 0x00000004u +#define CYFLD_HSIOM_SWITCH_BB_SL__SIZE 0x00000001u +#define CYFLD_HSIOM_SWITCH_BB_SR__OFFSET 0x00000005u +#define CYFLD_HSIOM_SWITCH_BB_SR__SIZE 0x00000001u +#define CYFLD_HSIOM_SWITCH_BB_S0__OFFSET 0x00000006u +#define CYFLD_HSIOM_SWITCH_BB_S0__SIZE 0x00000001u +#define CYREG_HSIOM_AMUX_SPLIT_CTL1 0x40022104u +#define CYREG_PWR_CONTROL 0x40030000u +#define CYFLD__POWER_MODE__OFFSET 0x00000000u +#define CYFLD__POWER_MODE__SIZE 0x00000004u +#define CYVAL__POWER_MODE_RESET 0x00000000u +#define CYVAL__POWER_MODE_ACTIVE 0x00000001u +#define CYVAL__POWER_MODE_SLEEP 0x00000002u +#define CYVAL__POWER_MODE_DEEP_SLEEP 0x00000003u +#define CYFLD__DEBUG_SESSION__OFFSET 0x00000004u +#define CYFLD__DEBUG_SESSION__SIZE 0x00000001u +#define CYVAL__DEBUG_SESSION_NO_SESSION 0x00000000u +#define CYVAL__DEBUG_SESSION_SESSION_ACTIVE 0x00000001u +#define CYFLD__LPM_READY__OFFSET 0x00000005u +#define CYFLD__LPM_READY__SIZE 0x00000001u +#define CYFLD__OVER_TEMP_EN__OFFSET 0x00000010u +#define CYFLD__OVER_TEMP_EN__SIZE 0x00000001u +#define CYFLD__OVER_TEMP_THRESH__OFFSET 0x00000011u +#define CYFLD__OVER_TEMP_THRESH__SIZE 0x00000001u +#define CYFLD__SPARE__OFFSET 0x00000012u +#define CYFLD__SPARE__SIZE 0x00000002u +#define CYFLD__EXT_VCCD__OFFSET 0x00000017u +#define CYFLD__EXT_VCCD__SIZE 0x00000001u +#define CYREG_PWR_KEY_DELAY 0x40030004u +#define CYFLD__WAKEUP_HOLDOFF__OFFSET 0x00000000u +#define CYFLD__WAKEUP_HOLDOFF__SIZE 0x0000000au +#define CYREG_PWR_DDFT_SELECT 0x4003000cu +#define CYFLD__DDFT0_SEL__OFFSET 0x00000000u +#define CYFLD__DDFT0_SEL__SIZE 0x00000004u +#define CYVAL__DDFT0_SEL_WAKEUP 0x00000000u +#define CYVAL__DDFT0_SEL_AWAKE 0x00000001u +#define CYVAL__DDFT0_SEL_ACT_POWER_EN 0x00000002u +#define CYVAL__DDFT0_SEL_ACT_POWER_UP 0x00000003u +#define CYVAL__DDFT0_SEL_ACT_POWER_GOOD 0x00000004u +#define CYVAL__DDFT0_SEL_ACT_REF_EN 0x00000005u +#define CYVAL__DDFT0_SEL_ACT_COMP_EN 0x00000006u +#define CYVAL__DDFT0_SEL_DPSLP_REF_EN 0x00000007u +#define CYVAL__DDFT0_SEL_DPSLP_REG_EN 0x00000008u +#define CYVAL__DDFT0_SEL_DPSLP_COMP_EN 0x00000009u +#define CYVAL__DDFT0_SEL_OVER_TEMP_EN 0x0000000au +#define CYVAL__DDFT0_SEL_SLEEPHOLDREQ_N 0x0000000bu +#define CYVAL__DDFT0_SEL_ADFT_BUF_EN 0x0000000cu +#define CYVAL__DDFT0_SEL_ATPG_OBSERVE 0x0000000du +#define CYVAL__DDFT0_SEL_GND 0x0000000eu +#define CYVAL__DDFT0_SEL_PWR 0x0000000fu +#define CYFLD__DDFT1_SEL__OFFSET 0x00000004u +#define CYFLD__DDFT1_SEL__SIZE 0x00000004u +#define CYVAL__DDFT1_SEL_WAKEUP 0x00000000u +#define CYVAL__DDFT1_SEL_AWAKE 0x00000001u +#define CYVAL__DDFT1_SEL_ACT_POWER_EN 0x00000002u +#define CYVAL__DDFT1_SEL_ACT_POWER_UP 0x00000003u +#define CYVAL__DDFT1_SEL_ACT_POWER_GOOD 0x00000004u +#define CYVAL__DDFT1_SEL_ACT_REF_VALID 0x00000005u +#define CYVAL__DDFT1_SEL_ACT_REG_VALID 0x00000006u +#define CYVAL__DDFT1_SEL_ACT_COMP_OUT 0x00000007u +#define CYVAL__DDFT1_SEL_ACT_TEMP_HIGH 0x00000008u +#define CYVAL__DDFT1_SEL_DPSLP_COMP_OUT 0x00000009u +#define CYVAL__DDFT1_SEL_DPSLP_POWER_UP 0x0000000au +#define CYVAL__DDFT1_SEL_AWAKE_DELAYED 0x0000000bu +#define CYVAL__DDFT1_SEL_LPM_READY 0x0000000cu +#define CYVAL__DDFT1_SEL_SLEEPHOLDACK_N 0x0000000du +#define CYVAL__DDFT1_SEL_GND 0x0000000eu +#define CYVAL__DDFT1_SEL_PWR 0x0000000fu +#define CYREG_TST_MODE 0x40030014u +#define CYFLD__SWD_CONNECTED__OFFSET 0x00000002u +#define CYFLD__SWD_CONNECTED__SIZE 0x00000001u +#define CYFLD__BLOCK_ALT_XRES__OFFSET 0x0000001cu +#define CYFLD__BLOCK_ALT_XRES__SIZE 0x00000001u +#define CYFLD__TEST_KEY_DFT_EN__OFFSET 0x0000001eu +#define CYFLD__TEST_KEY_DFT_EN__SIZE 0x00000001u +#define CYFLD__TEST_MODE__OFFSET 0x0000001fu +#define CYFLD__TEST_MODE__SIZE 0x00000001u +#define CYREG_TST_DDFT_CTRL 0x40030018u +#define CYFLD__DFT_SEL0__OFFSET 0x00000000u +#define CYFLD__DFT_SEL0__SIZE 0x00000004u +#define CYVAL__DFT_SEL0_SRC0 0x00000000u +#define CYVAL__DFT_SEL0_SRC1 0x00000001u +#define CYVAL__DFT_SEL0_SRC2 0x00000002u +#define CYVAL__DFT_SEL0_SRC3 0x00000003u +#define CYVAL__DFT_SEL0_SRC4 0x00000004u +#define CYVAL__DFT_SEL0_SRC5 0x00000005u +#define CYVAL__DFT_SEL0_SRC6 0x00000006u +#define CYVAL__DFT_SEL0_SRC7 0x00000007u +#define CYVAL__DFT_SEL0_CLK0 0x00000008u +#define CYVAL__DFT_SEL0_CLK1 0x00000009u +#define CYVAL__DFT_SEL0_PWR0 0x0000000au +#define CYVAL__DFT_SEL0_PWR1 0x0000000bu +#define CYVAL__DFT_SEL0_RES0 0x0000000cu +#define CYVAL__DFT_SEL0_RES1 0x0000000du +#define CYVAL__DFT_SEL0_ADFT_COMP 0x0000000eu +#define CYVAL__DFT_SEL0_VSS 0x0000000fu +#define CYFLD__DFT_SEL1__OFFSET 0x00000008u +#define CYFLD__DFT_SEL1__SIZE 0x00000004u +#define CYVAL__DFT_SEL1_SRC0 0x00000000u +#define CYVAL__DFT_SEL1_SRC1 0x00000001u +#define CYVAL__DFT_SEL1_SRC2 0x00000002u +#define CYVAL__DFT_SEL1_SRC3 0x00000003u +#define CYVAL__DFT_SEL1_SRC4 0x00000004u +#define CYVAL__DFT_SEL1_SRC5 0x00000005u +#define CYVAL__DFT_SEL1_SRC6 0x00000006u +#define CYVAL__DFT_SEL1_SRC7 0x00000007u +#define CYVAL__DFT_SEL1_CLK0 0x00000008u +#define CYVAL__DFT_SEL1_CLK1 0x00000009u +#define CYVAL__DFT_SEL1_PWR0 0x0000000au +#define CYVAL__DFT_SEL1_PWR1 0x0000000bu +#define CYVAL__DFT_SEL1_RES0 0x0000000cu +#define CYVAL__DFT_SEL1_RES1 0x0000000du +#define CYVAL__DFT_SEL1_ADFT_COMP 0x0000000eu +#define CYVAL__DFT_SEL1_VSS 0x0000000fu +#define CYFLD__ENABLE__OFFSET 0x0000001fu +#define CYFLD__ENABLE__SIZE 0x00000001u +#define CYREG_TST_TRIM_CNTR1 0x4003001cu +#define CYFLD__COUNTER__OFFSET 0x00000000u +#define CYFLD__COUNTER__SIZE 0x00000010u +#define CYFLD__COUNTER_DONE__OFFSET 0x0000001fu +#define CYFLD__COUNTER_DONE__SIZE 0x00000001u +#define CYREG_TST_TRIM_CNTR2 0x40030020u +#define CYREG_TST_ADFT_CTRL 0x40030024u +#define CYFLD__BUF_AUTO_ZERO__OFFSET 0x00000000u +#define CYFLD__BUF_AUTO_ZERO__SIZE 0x00000001u +#define CYFLD__BUF_MODE__OFFSET 0x00000008u +#define CYFLD__BUF_MODE__SIZE 0x00000002u +#define CYFLD__BUF_COMP_OUT__OFFSET 0x00000010u +#define CYFLD__BUF_COMP_OUT__SIZE 0x00000001u +#define CYFLD__BUF_EN__OFFSET 0x0000001fu +#define CYFLD__BUF_EN__SIZE 0x00000001u +#define CYREG_CLK_SELECT 0x40030028u +#define CYFLD__HFCLK_SEL__OFFSET 0x00000000u +#define CYFLD__HFCLK_SEL__SIZE 0x00000002u +#define CYVAL__HFCLK_SEL_IMO 0x00000000u +#define CYVAL__HFCLK_SEL_EXTCLK 0x00000001u +#define CYVAL__HFCLK_SEL_ECO 0x00000002u +#define CYFLD__HFCLK_DIV__OFFSET 0x00000002u +#define CYFLD__HFCLK_DIV__SIZE 0x00000002u +#define CYVAL__HFCLK_DIV_NO_DIV 0x00000000u +#define CYVAL__HFCLK_DIV_DIV_BY_2 0x00000001u +#define CYVAL__HFCLK_DIV_DIV_BY_4 0x00000002u +#define CYVAL__HFCLK_DIV_DIV_BY_8 0x00000003u +#define CYFLD__PUMP_SEL__OFFSET 0x00000004u +#define CYFLD__PUMP_SEL__SIZE 0x00000002u +#define CYVAL__PUMP_SEL_GND 0x00000000u +#define CYVAL__PUMP_SEL_IMO 0x00000001u +#define CYVAL__PUMP_SEL_HFCLK 0x00000002u +#define CYFLD__SYSCLK_DIV__OFFSET 0x00000006u +#define CYFLD__SYSCLK_DIV__SIZE 0x00000002u +#define CYVAL__SYSCLK_DIV_NO_DIV 0x00000000u +#define CYVAL__SYSCLK_DIV_DIV_BY_2 0x00000001u +#define CYVAL__SYSCLK_DIV_DIV_BY_4 0x00000002u +#define CYVAL__SYSCLK_DIV_DIV_BY_8 0x00000003u +#define CYREG_CLK_ILO_CONFIG 0x4003002cu +#define CYREG_CLK_IMO_CONFIG 0x40030030u +#define CYREG_CLK_DFT_SELECT 0x40030034u +#define CYFLD__DFT_DIV0__OFFSET 0x00000004u +#define CYFLD__DFT_DIV0__SIZE 0x00000002u +#define CYVAL__DFT_DIV0_NO_DIV 0x00000000u +#define CYVAL__DFT_DIV0_DIV_BY_2 0x00000001u +#define CYVAL__DFT_DIV0_DIV_BY_4 0x00000002u +#define CYVAL__DFT_DIV0_DIV_BY_8 0x00000003u +#define CYFLD__DFT_EDGE0__OFFSET 0x00000006u +#define CYFLD__DFT_EDGE0__SIZE 0x00000001u +#define CYVAL__DFT_EDGE0_POSEDGE 0x00000000u +#define CYVAL__DFT_EDGE0_NEGEDGE 0x00000001u +#define CYFLD__DFT_DIV1__OFFSET 0x0000000cu +#define CYFLD__DFT_DIV1__SIZE 0x00000002u +#define CYVAL__DFT_DIV1_NO_DIV 0x00000000u +#define CYVAL__DFT_DIV1_DIV_BY_2 0x00000001u +#define CYVAL__DFT_DIV1_DIV_BY_4 0x00000002u +#define CYVAL__DFT_DIV1_DIV_BY_8 0x00000003u +#define CYFLD__DFT_EDGE1__OFFSET 0x0000000eu +#define CYFLD__DFT_EDGE1__SIZE 0x00000001u +#define CYVAL__DFT_EDGE1_POSEDGE 0x00000000u +#define CYVAL__DFT_EDGE1_NEGEDGE 0x00000001u +#define CYREG_WDT_DISABLE_KEY 0x40030038u +#define CYFLD__KEY__OFFSET 0x00000000u +#define CYFLD__KEY__SIZE 0x00000020u +#define CYREG_WDT_COUNTER 0x4003003cu +#define CYREG_WDT_MATCH 0x40030040u +#define CYFLD__MATCH__OFFSET 0x00000000u +#define CYFLD__MATCH__SIZE 0x00000010u +#define CYFLD__IGNORE_BITS__OFFSET 0x00000010u +#define CYFLD__IGNORE_BITS__SIZE 0x00000004u +#define CYREG_SRSS_INTR 0x40030044u +#define CYFLD__WDT_MATCH__OFFSET 0x00000000u +#define CYFLD__WDT_MATCH__SIZE 0x00000001u +#define CYFLD__TEMP_HIGH__OFFSET 0x00000001u +#define CYFLD__TEMP_HIGH__SIZE 0x00000001u +#define CYREG_SRSS_INTR_SET 0x40030048u +#define CYREG_SRSS_INTR_MASK 0x4003004cu +#define CYREG_RES_CAUSE 0x40030054u +#define CYFLD__RESET_WDT__OFFSET 0x00000000u +#define CYFLD__RESET_WDT__SIZE 0x00000001u +#define CYFLD__RESET_PROT_FAULT__OFFSET 0x00000003u +#define CYFLD__RESET_PROT_FAULT__SIZE 0x00000001u +#define CYFLD__RESET_SOFT__OFFSET 0x00000004u +#define CYFLD__RESET_SOFT__SIZE 0x00000001u +#define CYREG_PWR_BG_TRIM1 0x40030f00u +#define CYFLD__REF_VTRIM__OFFSET 0x00000000u +#define CYFLD__REF_VTRIM__SIZE 0x00000006u +#define CYREG_PWR_BG_TRIM2 0x40030f04u +#define CYFLD__REF_ITRIM__OFFSET 0x00000000u +#define CYFLD__REF_ITRIM__SIZE 0x00000006u +#define CYREG_CLK_IMO_SELECT 0x40030f08u +#define CYFLD__FREQ__OFFSET 0x00000000u +#define CYFLD__FREQ__SIZE 0x00000003u +#define CYVAL__FREQ_24_MHZ 0x00000000u +#define CYVAL__FREQ_28_MHZ 0x00000001u +#define CYVAL__FREQ_32_MHZ 0x00000002u +#define CYVAL__FREQ_36_MHZ 0x00000003u +#define CYVAL__FREQ_40_MHZ 0x00000004u +#define CYVAL__FREQ_44_MHZ 0x00000005u +#define CYVAL__FREQ_48_MHZ 0x00000006u +#define CYREG_CLK_IMO_TRIM1 0x40030f0cu +#define CYFLD__OFFSET__OFFSET 0x00000000u +#define CYFLD__OFFSET__SIZE 0x00000008u +#define CYREG_CLK_IMO_TRIM2 0x40030f10u +#define CYFLD__FSOFFSET__OFFSET 0x00000000u +#define CYFLD__FSOFFSET__SIZE 0x00000003u +#define CYREG_PWR_PWRSYS_TRIM1 0x40030f14u +#define CYFLD__DPSLP_REF_TRIM__OFFSET 0x00000000u +#define CYFLD__DPSLP_REF_TRIM__SIZE 0x00000004u +#define CYFLD__SPARE_TRIM__OFFSET 0x00000004u +#define CYFLD__SPARE_TRIM__SIZE 0x00000004u +#define CYREG_CLK_IMO_TRIM3 0x40030f18u +#define CYFLD__STEPSIZE__OFFSET 0x00000000u +#define CYFLD__STEPSIZE__SIZE 0x00000005u +#define CYFLD__TCTRIM__OFFSET 0x00000005u +#define CYFLD__TCTRIM__SIZE 0x00000002u +#define CYDEV_GPIO_BASE 0x40040000u +#define CYDEV_GPIO_SIZE 0x00004000u +#define CYDEV_GPIO_PRT0_BASE 0x40040000u +#define CYDEV_GPIO_PRT0_SIZE 0x00000100u +#define CYREG_GPIO_PRT0_DR 0x40040000u +#define CYFLD_GPIO_PRT_DATA0__OFFSET 0x00000000u +#define CYFLD_GPIO_PRT_DATA0__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_DATA1__OFFSET 0x00000001u +#define CYFLD_GPIO_PRT_DATA1__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_DATA2__OFFSET 0x00000002u +#define CYFLD_GPIO_PRT_DATA2__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_DATA3__OFFSET 0x00000003u +#define CYFLD_GPIO_PRT_DATA3__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_DATA4__OFFSET 0x00000004u +#define CYFLD_GPIO_PRT_DATA4__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_DATA5__OFFSET 0x00000005u +#define CYFLD_GPIO_PRT_DATA5__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_DATA6__OFFSET 0x00000006u +#define CYFLD_GPIO_PRT_DATA6__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_DATA7__OFFSET 0x00000007u +#define CYFLD_GPIO_PRT_DATA7__SIZE 0x00000001u +#define CYREG_GPIO_PRT0_PS 0x40040004u +#define CYFLD_GPIO_PRT_FLT_DATA__OFFSET 0x00000008u +#define CYFLD_GPIO_PRT_FLT_DATA__SIZE 0x00000001u +#define CYREG_GPIO_PRT0_PC 0x40040008u +#define CYFLD_GPIO_PRT_DM0__OFFSET 0x00000000u +#define CYFLD_GPIO_PRT_DM0__SIZE 0x00000003u +#define CYVAL_GPIO_PRT_DM0_OFF 0x00000000u +#define CYVAL_GPIO_PRT_DM0_INPUT 0x00000001u +#define CYVAL_GPIO_PRT_DM0_0_PU 0x00000002u +#define CYVAL_GPIO_PRT_DM0_PD_1 0x00000003u +#define CYVAL_GPIO_PRT_DM0_0_Z 0x00000004u +#define CYVAL_GPIO_PRT_DM0_Z_1 0x00000005u +#define CYVAL_GPIO_PRT_DM0_0_1 0x00000006u +#define CYVAL_GPIO_PRT_DM0_PD_PU 0x00000007u +#define CYFLD_GPIO_PRT_DM1__OFFSET 0x00000003u +#define CYFLD_GPIO_PRT_DM1__SIZE 0x00000003u +#define CYFLD_GPIO_PRT_DM2__OFFSET 0x00000006u +#define CYFLD_GPIO_PRT_DM2__SIZE 0x00000003u +#define CYFLD_GPIO_PRT_DM3__OFFSET 0x00000009u +#define CYFLD_GPIO_PRT_DM3__SIZE 0x00000003u +#define CYFLD_GPIO_PRT_DM4__OFFSET 0x0000000cu +#define CYFLD_GPIO_PRT_DM4__SIZE 0x00000003u +#define CYFLD_GPIO_PRT_DM5__OFFSET 0x0000000fu +#define CYFLD_GPIO_PRT_DM5__SIZE 0x00000003u +#define CYFLD_GPIO_PRT_DM6__OFFSET 0x00000012u +#define CYFLD_GPIO_PRT_DM6__SIZE 0x00000003u +#define CYFLD_GPIO_PRT_DM7__OFFSET 0x00000015u +#define CYFLD_GPIO_PRT_DM7__SIZE 0x00000003u +#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__OFFSET 0x00000018u +#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_PORT_SLOW__OFFSET 0x00000019u +#define CYFLD_GPIO_PRT_PORT_SLOW__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__OFFSET 0x0000001eu +#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__SIZE 0x00000002u +#define CYREG_GPIO_PRT0_INTR_CFG 0x4004000cu +#define CYFLD_GPIO_PRT_EDGE0_SEL__OFFSET 0x00000000u +#define CYFLD_GPIO_PRT_EDGE0_SEL__SIZE 0x00000002u +#define CYVAL_GPIO_PRT_EDGE0_SEL_DISABLE 0x00000000u +#define CYVAL_GPIO_PRT_EDGE0_SEL_RISING 0x00000001u +#define CYVAL_GPIO_PRT_EDGE0_SEL_FALLING 0x00000002u +#define CYVAL_GPIO_PRT_EDGE0_SEL_BOTH 0x00000003u +#define CYFLD_GPIO_PRT_EDGE1_SEL__OFFSET 0x00000002u +#define CYFLD_GPIO_PRT_EDGE1_SEL__SIZE 0x00000002u +#define CYFLD_GPIO_PRT_EDGE2_SEL__OFFSET 0x00000004u +#define CYFLD_GPIO_PRT_EDGE2_SEL__SIZE 0x00000002u +#define CYFLD_GPIO_PRT_EDGE3_SEL__OFFSET 0x00000006u +#define CYFLD_GPIO_PRT_EDGE3_SEL__SIZE 0x00000002u +#define CYFLD_GPIO_PRT_EDGE4_SEL__OFFSET 0x00000008u +#define CYFLD_GPIO_PRT_EDGE4_SEL__SIZE 0x00000002u +#define CYFLD_GPIO_PRT_EDGE5_SEL__OFFSET 0x0000000au +#define CYFLD_GPIO_PRT_EDGE5_SEL__SIZE 0x00000002u +#define CYFLD_GPIO_PRT_EDGE6_SEL__OFFSET 0x0000000cu +#define CYFLD_GPIO_PRT_EDGE6_SEL__SIZE 0x00000002u +#define CYFLD_GPIO_PRT_EDGE7_SEL__OFFSET 0x0000000eu +#define CYFLD_GPIO_PRT_EDGE7_SEL__SIZE 0x00000002u +#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__OFFSET 0x00000010u +#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__SIZE 0x00000002u +#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_DISABLE 0x00000000u +#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_RISING 0x00000001u +#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_FALLING 0x00000002u +#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_BOTH 0x00000003u +#define CYFLD_GPIO_PRT_FLT_SEL__OFFSET 0x00000012u +#define CYFLD_GPIO_PRT_FLT_SEL__SIZE 0x00000003u +#define CYREG_GPIO_PRT0_INTR 0x40040010u +#define CYFLD_GPIO_PRT_PS_DATA0__OFFSET 0x00000010u +#define CYFLD_GPIO_PRT_PS_DATA0__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_PS_DATA1__OFFSET 0x00000011u +#define CYFLD_GPIO_PRT_PS_DATA1__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_PS_DATA2__OFFSET 0x00000012u +#define CYFLD_GPIO_PRT_PS_DATA2__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_PS_DATA3__OFFSET 0x00000013u +#define CYFLD_GPIO_PRT_PS_DATA3__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_PS_DATA4__OFFSET 0x00000014u +#define CYFLD_GPIO_PRT_PS_DATA4__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_PS_DATA5__OFFSET 0x00000015u +#define CYFLD_GPIO_PRT_PS_DATA5__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_PS_DATA6__OFFSET 0x00000016u +#define CYFLD_GPIO_PRT_PS_DATA6__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_PS_DATA7__OFFSET 0x00000017u +#define CYFLD_GPIO_PRT_PS_DATA7__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_PS_FLT_DATA__OFFSET 0x00000018u +#define CYFLD_GPIO_PRT_PS_FLT_DATA__SIZE 0x00000001u +#define CYREG_GPIO_PRT0_PC2 0x40040018u +#define CYFLD_GPIO_PRT_INP_DIS0__OFFSET 0x00000000u +#define CYFLD_GPIO_PRT_INP_DIS0__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_INP_DIS1__OFFSET 0x00000001u +#define CYFLD_GPIO_PRT_INP_DIS1__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_INP_DIS2__OFFSET 0x00000002u +#define CYFLD_GPIO_PRT_INP_DIS2__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_INP_DIS3__OFFSET 0x00000003u +#define CYFLD_GPIO_PRT_INP_DIS3__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_INP_DIS4__OFFSET 0x00000004u +#define CYFLD_GPIO_PRT_INP_DIS4__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_INP_DIS5__OFFSET 0x00000005u +#define CYFLD_GPIO_PRT_INP_DIS5__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_INP_DIS6__OFFSET 0x00000006u +#define CYFLD_GPIO_PRT_INP_DIS6__SIZE 0x00000001u +#define CYFLD_GPIO_PRT_INP_DIS7__OFFSET 0x00000007u +#define CYFLD_GPIO_PRT_INP_DIS7__SIZE 0x00000001u +#define CYREG_GPIO_PRT0_DR_SET 0x40040040u +#define CYFLD_GPIO_PRT_DATA__OFFSET 0x00000000u +#define CYFLD_GPIO_PRT_DATA__SIZE 0x00000008u +#define CYREG_GPIO_PRT0_DR_CLR 0x40040044u +#define CYREG_GPIO_PRT0_DR_INV 0x40040048u +#define CYDEV_GPIO_PRT1_BASE 0x40040100u +#define CYDEV_GPIO_PRT1_SIZE 0x00000100u +#define CYREG_GPIO_PRT1_DR 0x40040100u +#define CYREG_GPIO_PRT1_PS 0x40040104u +#define CYREG_GPIO_PRT1_PC 0x40040108u +#define CYREG_GPIO_PRT1_INTR_CFG 0x4004010cu +#define CYREG_GPIO_PRT1_INTR 0x40040110u +#define CYREG_GPIO_PRT1_PC2 0x40040118u +#define CYREG_GPIO_PRT1_DR_SET 0x40040140u +#define CYREG_GPIO_PRT1_DR_CLR 0x40040144u +#define CYREG_GPIO_PRT1_DR_INV 0x40040148u +#define CYDEV_GPIO_PRT2_BASE 0x40040200u +#define CYDEV_GPIO_PRT2_SIZE 0x00000100u +#define CYREG_GPIO_PRT2_DR 0x40040200u +#define CYREG_GPIO_PRT2_PS 0x40040204u +#define CYREG_GPIO_PRT2_PC 0x40040208u +#define CYREG_GPIO_PRT2_INTR_CFG 0x4004020cu +#define CYREG_GPIO_PRT2_INTR 0x40040210u +#define CYREG_GPIO_PRT2_PC2 0x40040218u +#define CYREG_GPIO_PRT2_DR_SET 0x40040240u +#define CYREG_GPIO_PRT2_DR_CLR 0x40040244u +#define CYREG_GPIO_PRT2_DR_INV 0x40040248u +#define CYDEV_GPIO_PRT3_BASE 0x40040300u +#define CYDEV_GPIO_PRT3_SIZE 0x00000100u +#define CYREG_GPIO_PRT3_DR 0x40040300u +#define CYREG_GPIO_PRT3_PS 0x40040304u +#define CYREG_GPIO_PRT3_PC 0x40040308u +#define CYREG_GPIO_PRT3_INTR_CFG 0x4004030cu +#define CYREG_GPIO_PRT3_INTR 0x40040310u +#define CYREG_GPIO_PRT3_PC2 0x40040318u +#define CYREG_GPIO_PRT3_DR_SET 0x40040340u +#define CYREG_GPIO_PRT3_DR_CLR 0x40040344u +#define CYREG_GPIO_PRT3_DR_INV 0x40040348u +#define CYDEV_GPIO_PRT4_BASE 0x40040400u +#define CYDEV_GPIO_PRT4_SIZE 0x00000100u +#define CYREG_GPIO_PRT4_DR 0x40040400u +#define CYREG_GPIO_PRT4_PS 0x40040404u +#define CYREG_GPIO_PRT4_PC 0x40040408u +#define CYREG_GPIO_PRT4_INTR_CFG 0x4004040cu +#define CYREG_GPIO_PRT4_INTR 0x40040410u +#define CYREG_GPIO_PRT4_PC2 0x40040418u +#define CYREG_GPIO_PRT4_DR_SET 0x40040440u +#define CYREG_GPIO_PRT4_DR_CLR 0x40040444u +#define CYREG_GPIO_PRT4_DR_INV 0x40040448u +#define CYDEV_GPIO_PRT5_BASE 0x40040500u +#define CYDEV_GPIO_PRT5_SIZE 0x00000100u +#define CYREG_GPIO_PRT5_DR 0x40040500u +#define CYREG_GPIO_PRT5_PS 0x40040504u +#define CYREG_GPIO_PRT5_PC 0x40040508u +#define CYREG_GPIO_PRT5_INTR_CFG 0x4004050cu +#define CYREG_GPIO_PRT5_INTR 0x40040510u +#define CYREG_GPIO_PRT5_PC2 0x40040518u +#define CYREG_GPIO_PRT5_DR_SET 0x40040540u +#define CYREG_GPIO_PRT5_DR_CLR 0x40040544u +#define CYREG_GPIO_PRT5_DR_INV 0x40040548u +#define CYDEV_GPIO_PRT6_BASE 0x40040600u +#define CYDEV_GPIO_PRT6_SIZE 0x00000100u +#define CYREG_GPIO_PRT6_DR 0x40040600u +#define CYREG_GPIO_PRT6_PS 0x40040604u +#define CYREG_GPIO_PRT6_PC 0x40040608u +#define CYREG_GPIO_PRT6_INTR_CFG 0x4004060cu +#define CYREG_GPIO_PRT6_INTR 0x40040610u +#define CYREG_GPIO_PRT6_PC2 0x40040618u +#define CYREG_GPIO_PRT6_DR_SET 0x40040640u +#define CYREG_GPIO_PRT6_DR_CLR 0x40040644u +#define CYREG_GPIO_PRT6_DR_INV 0x40040648u +#define CYDEV_GPIO_PRT7_BASE 0x40040700u +#define CYDEV_GPIO_PRT7_SIZE 0x00000100u +#define CYREG_GPIO_PRT7_DR 0x40040700u +#define CYREG_GPIO_PRT7_PS 0x40040704u +#define CYREG_GPIO_PRT7_PC 0x40040708u +#define CYREG_GPIO_PRT7_INTR_CFG 0x4004070cu +#define CYREG_GPIO_PRT7_INTR 0x40040710u +#define CYREG_GPIO_PRT7_PC2 0x40040718u +#define CYREG_GPIO_PRT7_DR_SET 0x40040740u +#define CYREG_GPIO_PRT7_DR_CLR 0x40040744u +#define CYREG_GPIO_PRT7_DR_INV 0x40040748u +#define CYREG_GPIO_INTR_CAUSE 0x40041000u +#define CYFLD_GPIO_PORT_INT__OFFSET 0x00000000u +#define CYFLD_GPIO_PORT_INT__SIZE 0x00000008u +#define CYDEV_PRGIO_BASE 0x40050000u +#define CYDEV_PRGIO_SIZE 0x00001000u +#define CYDEV_PRGIO_PRT0_BASE 0x40050000u +#define CYDEV_PRGIO_PRT0_SIZE 0x00000100u +#define CYREG_PRGIO_PRT0_CTL 0x40050000u +#define CYFLD_PRGIO_PRT_BYPASS__OFFSET 0x00000000u +#define CYFLD_PRGIO_PRT_BYPASS__SIZE 0x00000008u +#define CYFLD_PRGIO_PRT_CLOCK_SRC__OFFSET 0x00000008u +#define CYFLD_PRGIO_PRT_CLOCK_SRC__SIZE 0x00000005u +#define CYFLD_PRGIO_PRT_HLD_OVR__OFFSET 0x00000018u +#define CYFLD_PRGIO_PRT_HLD_OVR__SIZE 0x00000001u +#define CYFLD_PRGIO_PRT_PIPELINE_EN__OFFSET 0x00000019u +#define CYFLD_PRGIO_PRT_PIPELINE_EN__SIZE 0x00000001u +#define CYFLD_PRGIO_PRT_ENABLED__OFFSET 0x0000001fu +#define CYFLD_PRGIO_PRT_ENABLED__SIZE 0x00000001u +#define CYREG_PRGIO_PRT0_SYNC_CTL 0x40050010u +#define CYFLD_PRGIO_PRT_IO_SYNC_EN__OFFSET 0x00000000u +#define CYFLD_PRGIO_PRT_IO_SYNC_EN__SIZE 0x00000008u +#define CYFLD_PRGIO_PRT_CHIP_SYNC_EN__OFFSET 0x00000008u +#define CYFLD_PRGIO_PRT_CHIP_SYNC_EN__SIZE 0x00000008u +#define CYREG_PRGIO_PRT0_LUT_SEL0 0x40050020u +#define CYFLD_PRGIO_PRT_LUT_TR0_SEL__OFFSET 0x00000000u +#define CYFLD_PRGIO_PRT_LUT_TR0_SEL__SIZE 0x00000004u +#define CYFLD_PRGIO_PRT_LUT_TR1_SEL__OFFSET 0x00000008u +#define CYFLD_PRGIO_PRT_LUT_TR1_SEL__SIZE 0x00000004u +#define CYFLD_PRGIO_PRT_LUT_TR2_SEL__OFFSET 0x00000010u +#define CYFLD_PRGIO_PRT_LUT_TR2_SEL__SIZE 0x00000004u +#define CYREG_PRGIO_PRT0_LUT_SEL1 0x40050024u +#define CYREG_PRGIO_PRT0_LUT_SEL2 0x40050028u +#define CYREG_PRGIO_PRT0_LUT_SEL3 0x4005002cu +#define CYREG_PRGIO_PRT0_LUT_SEL4 0x40050030u +#define CYREG_PRGIO_PRT0_LUT_SEL5 0x40050034u +#define CYREG_PRGIO_PRT0_LUT_SEL6 0x40050038u +#define CYREG_PRGIO_PRT0_LUT_SEL7 0x4005003cu +#define CYREG_PRGIO_PRT0_LUT_CTL0 0x40050040u +#define CYFLD_PRGIO_PRT_LUT__OFFSET 0x00000000u +#define CYFLD_PRGIO_PRT_LUT__SIZE 0x00000008u +#define CYFLD_PRGIO_PRT_LUT_OPC__OFFSET 0x00000008u +#define CYFLD_PRGIO_PRT_LUT_OPC__SIZE 0x00000002u +#define CYREG_PRGIO_PRT0_LUT_CTL1 0x40050044u +#define CYREG_PRGIO_PRT0_LUT_CTL2 0x40050048u +#define CYREG_PRGIO_PRT0_LUT_CTL3 0x4005004cu +#define CYREG_PRGIO_PRT0_LUT_CTL4 0x40050050u +#define CYREG_PRGIO_PRT0_LUT_CTL5 0x40050054u +#define CYREG_PRGIO_PRT0_LUT_CTL6 0x40050058u +#define CYREG_PRGIO_PRT0_LUT_CTL7 0x4005005cu +#define CYREG_PRGIO_PRT0_DU_SEL 0x400500c0u +#define CYFLD_PRGIO_PRT_DU_TR0_SEL__OFFSET 0x00000000u +#define CYFLD_PRGIO_PRT_DU_TR0_SEL__SIZE 0x00000004u +#define CYFLD_PRGIO_PRT_DU_TR1_SEL__OFFSET 0x00000008u +#define CYFLD_PRGIO_PRT_DU_TR1_SEL__SIZE 0x00000004u +#define CYFLD_PRGIO_PRT_DU_TR2_SEL__OFFSET 0x00000010u +#define CYFLD_PRGIO_PRT_DU_TR2_SEL__SIZE 0x00000004u +#define CYFLD_PRGIO_PRT_DU_DATA0_SEL__OFFSET 0x00000018u +#define CYFLD_PRGIO_PRT_DU_DATA0_SEL__SIZE 0x00000002u +#define CYFLD_PRGIO_PRT_DU_DATA1_SEL__OFFSET 0x0000001cu +#define CYFLD_PRGIO_PRT_DU_DATA1_SEL__SIZE 0x00000002u +#define CYREG_PRGIO_PRT0_DU_CTL 0x400500c4u +#define CYFLD_PRGIO_PRT_DU_SIZE__OFFSET 0x00000000u +#define CYFLD_PRGIO_PRT_DU_SIZE__SIZE 0x00000003u +#define CYFLD_PRGIO_PRT_DU_OPC__OFFSET 0x00000008u +#define CYFLD_PRGIO_PRT_DU_OPC__SIZE 0x00000004u +#define CYREG_PRGIO_PRT0_DATA 0x400500f0u +#define CYFLD_PRGIO_PRT_DATA__OFFSET 0x00000000u +#define CYFLD_PRGIO_PRT_DATA__SIZE 0x00000008u +#define CYDEV_PRGIO_PRT1_BASE 0x40050100u +#define CYDEV_PRGIO_PRT1_SIZE 0x00000100u +#define CYREG_PRGIO_PRT1_CTL 0x40050100u +#define CYREG_PRGIO_PRT1_SYNC_CTL 0x40050110u +#define CYREG_PRGIO_PRT1_LUT_SEL0 0x40050120u +#define CYREG_PRGIO_PRT1_LUT_SEL1 0x40050124u +#define CYREG_PRGIO_PRT1_LUT_SEL2 0x40050128u +#define CYREG_PRGIO_PRT1_LUT_SEL3 0x4005012cu +#define CYREG_PRGIO_PRT1_LUT_SEL4 0x40050130u +#define CYREG_PRGIO_PRT1_LUT_SEL5 0x40050134u +#define CYREG_PRGIO_PRT1_LUT_SEL6 0x40050138u +#define CYREG_PRGIO_PRT1_LUT_SEL7 0x4005013cu +#define CYREG_PRGIO_PRT1_LUT_CTL0 0x40050140u +#define CYREG_PRGIO_PRT1_LUT_CTL1 0x40050144u +#define CYREG_PRGIO_PRT1_LUT_CTL2 0x40050148u +#define CYREG_PRGIO_PRT1_LUT_CTL3 0x4005014cu +#define CYREG_PRGIO_PRT1_LUT_CTL4 0x40050150u +#define CYREG_PRGIO_PRT1_LUT_CTL5 0x40050154u +#define CYREG_PRGIO_PRT1_LUT_CTL6 0x40050158u +#define CYREG_PRGIO_PRT1_LUT_CTL7 0x4005015cu +#define CYREG_PRGIO_PRT1_DU_SEL 0x400501c0u +#define CYREG_PRGIO_PRT1_DU_CTL 0x400501c4u +#define CYREG_PRGIO_PRT1_DATA 0x400501f0u +#define CYDEV_PRGIO_PRT2_BASE 0x40050200u +#define CYDEV_PRGIO_PRT2_SIZE 0x00000100u +#define CYREG_PRGIO_PRT2_CTL 0x40050200u +#define CYREG_PRGIO_PRT2_SYNC_CTL 0x40050210u +#define CYREG_PRGIO_PRT2_LUT_SEL0 0x40050220u +#define CYREG_PRGIO_PRT2_LUT_SEL1 0x40050224u +#define CYREG_PRGIO_PRT2_LUT_SEL2 0x40050228u +#define CYREG_PRGIO_PRT2_LUT_SEL3 0x4005022cu +#define CYREG_PRGIO_PRT2_LUT_SEL4 0x40050230u +#define CYREG_PRGIO_PRT2_LUT_SEL5 0x40050234u +#define CYREG_PRGIO_PRT2_LUT_SEL6 0x40050238u +#define CYREG_PRGIO_PRT2_LUT_SEL7 0x4005023cu +#define CYREG_PRGIO_PRT2_LUT_CTL0 0x40050240u +#define CYREG_PRGIO_PRT2_LUT_CTL1 0x40050244u +#define CYREG_PRGIO_PRT2_LUT_CTL2 0x40050248u +#define CYREG_PRGIO_PRT2_LUT_CTL3 0x4005024cu +#define CYREG_PRGIO_PRT2_LUT_CTL4 0x40050250u +#define CYREG_PRGIO_PRT2_LUT_CTL5 0x40050254u +#define CYREG_PRGIO_PRT2_LUT_CTL6 0x40050258u +#define CYREG_PRGIO_PRT2_LUT_CTL7 0x4005025cu +#define CYREG_PRGIO_PRT2_DU_SEL 0x400502c0u +#define CYREG_PRGIO_PRT2_DU_CTL 0x400502c4u +#define CYREG_PRGIO_PRT2_DATA 0x400502f0u +#define CYDEV_CPUSS_BASE 0x40100000u +#define CYDEV_CPUSS_SIZE 0x00001000u +#define CYREG_CPUSS_SYSREQ 0x40100004u +#define CYFLD_CPUSS_SYSCALL_COMMAND__OFFSET 0x00000000u +#define CYFLD_CPUSS_SYSCALL_COMMAND__SIZE 0x00000010u +#define CYFLD_CPUSS_DIS_RESET_VECT_REL__OFFSET 0x0000001bu +#define CYFLD_CPUSS_DIS_RESET_VECT_REL__SIZE 0x00000001u +#define CYFLD_CPUSS_PRIVILEGED__OFFSET 0x0000001cu +#define CYFLD_CPUSS_PRIVILEGED__SIZE 0x00000001u +#define CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET 0x0000001du +#define CYFLD_CPUSS_ROM_ACCESS_EN__SIZE 0x00000001u +#define CYFLD_CPUSS_HMASTER_0__OFFSET 0x0000001eu +#define CYFLD_CPUSS_HMASTER_0__SIZE 0x00000001u +#define CYFLD_CPUSS_SYSCALL_REQ__OFFSET 0x0000001fu +#define CYFLD_CPUSS_SYSCALL_REQ__SIZE 0x00000001u +#define CYREG_CPUSS_SYSARG 0x40100008u +#define CYFLD_CPUSS_SYSCALL_ARG__OFFSET 0x00000000u +#define CYFLD_CPUSS_SYSCALL_ARG__SIZE 0x00000020u +#define CYREG_CPUSS_PROTECTION 0x4010000cu +#define CYFLD_CPUSS_PROTECTION_MODE__OFFSET 0x00000000u +#define CYFLD_CPUSS_PROTECTION_MODE__SIZE 0x00000004u +#define CYFLD_CPUSS_FLASH_LOCK__OFFSET 0x0000001eu +#define CYFLD_CPUSS_FLASH_LOCK__SIZE 0x00000001u +#define CYFLD_CPUSS_PROTECTION_LOCK__OFFSET 0x0000001fu +#define CYFLD_CPUSS_PROTECTION_LOCK__SIZE 0x00000001u +#define CYREG_CPUSS_PRIV_ROM 0x40100010u +#define CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET 0x00000000u +#define CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE 0x00000008u +#define CYREG_CPUSS_PRIV_RAM 0x40100014u +#define CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET 0x00000000u +#define CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE 0x00000009u +#define CYREG_CPUSS_PRIV_FLASH 0x40100018u +#define CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET 0x00000000u +#define CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE 0x0000000cu +#define CYREG_CPUSS_WOUNDING 0x4010001cu +#define CYFLD_CPUSS_RAM_WOUND__OFFSET 0x00000010u +#define CYFLD_CPUSS_RAM_WOUND__SIZE 0x00000003u +#define CYFLD_CPUSS_FLASH_WOUND__OFFSET 0x00000014u +#define CYFLD_CPUSS_FLASH_WOUND__SIZE 0x00000003u +#define CYREG_CPUSS_FLASH_CTL 0x40100030u +#define CYFLD_CPUSS_FLASH_WS__OFFSET 0x00000000u +#define CYFLD_CPUSS_FLASH_WS__SIZE 0x00000002u +#define CYFLD_CPUSS_PREF_EN__OFFSET 0x00000004u +#define CYFLD_CPUSS_PREF_EN__SIZE 0x00000001u +#define CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET 0x00000008u +#define CYFLD_CPUSS_FLASH_INVALIDATE__SIZE 0x00000001u +#define CYFLD_CPUSS_ARB__OFFSET 0x00000010u +#define CYFLD_CPUSS_ARB__SIZE 0x00000002u +#define CYREG_CPUSS_ROM_CTL 0x40100034u +#define CYFLD_CPUSS_ROM_WS__OFFSET 0x00000000u +#define CYFLD_CPUSS_ROM_WS__SIZE 0x00000001u +#define CYREG_CPUSS_RAM_CTL 0x40100038u +#define CYREG_CPUSS_DMAC_CTL 0x4010003cu +#define CYREG_CPUSS_SL_CTL0 0x40100100u +#define CYREG_CPUSS_SL_CTL1 0x40100104u +#define CYREG_CPUSS_SL_CTL2 0x40100108u +#define CYDEV_DMAC_BASE 0x40101000u +#define CYDEV_DMAC_SIZE 0x00001000u +#define CYREG_DMAC_CTL 0x40101000u +#define CYFLD_DMAC_ENABLED__OFFSET 0x0000001fu +#define CYFLD_DMAC_ENABLED__SIZE 0x00000001u +#define CYREG_DMAC_STATUS 0x40101010u +#define CYFLD_DMAC_DATA_NR__OFFSET 0x00000000u +#define CYFLD_DMAC_DATA_NR__SIZE 0x00000010u +#define CYFLD_DMAC_CH_ADDR__OFFSET 0x00000010u +#define CYFLD_DMAC_CH_ADDR__SIZE 0x00000003u +#define CYFLD_DMAC_STATE__OFFSET 0x00000018u +#define CYFLD_DMAC_STATE__SIZE 0x00000003u +#define CYFLD_DMAC_PRIO__OFFSET 0x0000001cu +#define CYFLD_DMAC_PRIO__SIZE 0x00000002u +#define CYFLD_DMAC_PING_PONG__OFFSET 0x0000001eu +#define CYFLD_DMAC_PING_PONG__SIZE 0x00000001u +#define CYFLD_DMAC_ACTIVE__OFFSET 0x0000001fu +#define CYFLD_DMAC_ACTIVE__SIZE 0x00000001u +#define CYREG_DMAC_STATUS_SRC_ADDR 0x40101014u +#define CYFLD_DMAC_ADDR__OFFSET 0x00000000u +#define CYFLD_DMAC_ADDR__SIZE 0x00000020u +#define CYREG_DMAC_STATUS_DST_ADDR 0x40101018u +#define CYREG_DMAC_STATUS_CH_ACT 0x4010101cu +#define CYFLD_DMAC_CH__OFFSET 0x00000000u +#define CYFLD_DMAC_CH__SIZE 0x00000008u +#define CYREG_DMAC_CH_CTL0 0x40101080u +#define CYREG_DMAC_CH_CTL1 0x40101084u +#define CYREG_DMAC_CH_CTL2 0x40101088u +#define CYREG_DMAC_CH_CTL3 0x4010108cu +#define CYREG_DMAC_CH_CTL4 0x40101090u +#define CYREG_DMAC_CH_CTL5 0x40101094u +#define CYREG_DMAC_CH_CTL6 0x40101098u +#define CYREG_DMAC_CH_CTL7 0x4010109cu +#define CYREG_DMAC_INTR 0x401017f0u +#define CYREG_DMAC_INTR_SET 0x401017f4u +#define CYREG_DMAC_INTR_MASK 0x401017f8u +#define CYREG_DMAC_INTR_MASKED 0x401017fcu +#define CYDEV_DMAC_DESCR0_BASE 0x40101800u +#define CYDEV_DMAC_DESCR0_SIZE 0x00000020u +#define CYREG_DMAC_DESCR0_PING_SRC 0x40101800u +#define CYFLD_DMAC_DESCR_ADDR__OFFSET 0x00000000u +#define CYFLD_DMAC_DESCR_ADDR__SIZE 0x00000020u +#define CYREG_DMAC_DESCR0_PING_DST 0x40101804u +#define CYREG_DMAC_DESCR0_PING_CTL 0x40101808u +#define CYFLD_DMAC_DESCR_DATA_NR__OFFSET 0x00000000u +#define CYFLD_DMAC_DESCR_DATA_NR__SIZE 0x00000010u +#define CYFLD_DMAC_DESCR_DATA_SIZE__OFFSET 0x00000010u +#define CYFLD_DMAC_DESCR_DATA_SIZE__SIZE 0x00000002u +#define CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__OFFSET 0x00000014u +#define CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__SIZE 0x00000001u +#define CYFLD_DMAC_DESCR_DST_ADDR_INCR__OFFSET 0x00000015u +#define CYFLD_DMAC_DESCR_DST_ADDR_INCR__SIZE 0x00000001u +#define CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__OFFSET 0x00000016u +#define CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__SIZE 0x00000001u +#define CYFLD_DMAC_DESCR_SRC_ADDR_INCR__OFFSET 0x00000017u +#define CYFLD_DMAC_DESCR_SRC_ADDR_INCR__SIZE 0x00000001u +#define CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__OFFSET 0x00000018u +#define CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__SIZE 0x00000002u +#define CYFLD_DMAC_DESCR_INV_DESCR__OFFSET 0x0000001au +#define CYFLD_DMAC_DESCR_INV_DESCR__SIZE 0x00000001u +#define CYFLD_DMAC_DESCR_SET_CAUSE__OFFSET 0x0000001bu +#define CYFLD_DMAC_DESCR_SET_CAUSE__SIZE 0x00000001u +#define CYFLD_DMAC_DESCR_PREEMPTABLE__OFFSET 0x0000001cu +#define CYFLD_DMAC_DESCR_PREEMPTABLE__SIZE 0x00000001u +#define CYFLD_DMAC_DESCR_FLIPPING__OFFSET 0x0000001du +#define CYFLD_DMAC_DESCR_FLIPPING__SIZE 0x00000001u +#define CYFLD_DMAC_DESCR_OPCODE__OFFSET 0x0000001eu +#define CYFLD_DMAC_DESCR_OPCODE__SIZE 0x00000002u +#define CYREG_DMAC_DESCR0_PING_STATUS 0x4010180cu +#define CYFLD_DMAC_DESCR_CURR_DATA_NR__OFFSET 0x00000000u +#define CYFLD_DMAC_DESCR_CURR_DATA_NR__SIZE 0x00000010u +#define CYFLD_DMAC_DESCR_RESPONSE__OFFSET 0x00000010u +#define CYFLD_DMAC_DESCR_RESPONSE__SIZE 0x00000003u +#define CYFLD_DMAC_DESCR_VALID__OFFSET 0x0000001fu +#define CYFLD_DMAC_DESCR_VALID__SIZE 0x00000001u +#define CYREG_DMAC_DESCR0_PONG_SRC 0x40101810u +#define CYREG_DMAC_DESCR0_PONG_DST 0x40101814u +#define CYREG_DMAC_DESCR0_PONG_CTL 0x40101818u +#define CYREG_DMAC_DESCR0_PONG_STATUS 0x4010181cu +#define CYDEV_DMAC_DESCR1_BASE 0x40101820u +#define CYDEV_DMAC_DESCR1_SIZE 0x00000020u +#define CYREG_DMAC_DESCR1_PING_SRC 0x40101820u +#define CYREG_DMAC_DESCR1_PING_DST 0x40101824u +#define CYREG_DMAC_DESCR1_PING_CTL 0x40101828u +#define CYREG_DMAC_DESCR1_PING_STATUS 0x4010182cu +#define CYREG_DMAC_DESCR1_PONG_SRC 0x40101830u +#define CYREG_DMAC_DESCR1_PONG_DST 0x40101834u +#define CYREG_DMAC_DESCR1_PONG_CTL 0x40101838u +#define CYREG_DMAC_DESCR1_PONG_STATUS 0x4010183cu +#define CYDEV_DMAC_DESCR2_BASE 0x40101840u +#define CYDEV_DMAC_DESCR2_SIZE 0x00000020u +#define CYREG_DMAC_DESCR2_PING_SRC 0x40101840u +#define CYREG_DMAC_DESCR2_PING_DST 0x40101844u +#define CYREG_DMAC_DESCR2_PING_CTL 0x40101848u +#define CYREG_DMAC_DESCR2_PING_STATUS 0x4010184cu +#define CYREG_DMAC_DESCR2_PONG_SRC 0x40101850u +#define CYREG_DMAC_DESCR2_PONG_DST 0x40101854u +#define CYREG_DMAC_DESCR2_PONG_CTL 0x40101858u +#define CYREG_DMAC_DESCR2_PONG_STATUS 0x4010185cu +#define CYDEV_DMAC_DESCR3_BASE 0x40101860u +#define CYDEV_DMAC_DESCR3_SIZE 0x00000020u +#define CYREG_DMAC_DESCR3_PING_SRC 0x40101860u +#define CYREG_DMAC_DESCR3_PING_DST 0x40101864u +#define CYREG_DMAC_DESCR3_PING_CTL 0x40101868u +#define CYREG_DMAC_DESCR3_PING_STATUS 0x4010186cu +#define CYREG_DMAC_DESCR3_PONG_SRC 0x40101870u +#define CYREG_DMAC_DESCR3_PONG_DST 0x40101874u +#define CYREG_DMAC_DESCR3_PONG_CTL 0x40101878u +#define CYREG_DMAC_DESCR3_PONG_STATUS 0x4010187cu +#define CYDEV_DMAC_DESCR4_BASE 0x40101880u +#define CYDEV_DMAC_DESCR4_SIZE 0x00000020u +#define CYREG_DMAC_DESCR4_PING_SRC 0x40101880u +#define CYREG_DMAC_DESCR4_PING_DST 0x40101884u +#define CYREG_DMAC_DESCR4_PING_CTL 0x40101888u +#define CYREG_DMAC_DESCR4_PING_STATUS 0x4010188cu +#define CYREG_DMAC_DESCR4_PONG_SRC 0x40101890u +#define CYREG_DMAC_DESCR4_PONG_DST 0x40101894u +#define CYREG_DMAC_DESCR4_PONG_CTL 0x40101898u +#define CYREG_DMAC_DESCR4_PONG_STATUS 0x4010189cu +#define CYDEV_DMAC_DESCR5_BASE 0x401018a0u +#define CYDEV_DMAC_DESCR5_SIZE 0x00000020u +#define CYREG_DMAC_DESCR5_PING_SRC 0x401018a0u +#define CYREG_DMAC_DESCR5_PING_DST 0x401018a4u +#define CYREG_DMAC_DESCR5_PING_CTL 0x401018a8u +#define CYREG_DMAC_DESCR5_PING_STATUS 0x401018acu +#define CYREG_DMAC_DESCR5_PONG_SRC 0x401018b0u +#define CYREG_DMAC_DESCR5_PONG_DST 0x401018b4u +#define CYREG_DMAC_DESCR5_PONG_CTL 0x401018b8u +#define CYREG_DMAC_DESCR5_PONG_STATUS 0x401018bcu +#define CYDEV_DMAC_DESCR6_BASE 0x401018c0u +#define CYDEV_DMAC_DESCR6_SIZE 0x00000020u +#define CYREG_DMAC_DESCR6_PING_SRC 0x401018c0u +#define CYREG_DMAC_DESCR6_PING_DST 0x401018c4u +#define CYREG_DMAC_DESCR6_PING_CTL 0x401018c8u +#define CYREG_DMAC_DESCR6_PING_STATUS 0x401018ccu +#define CYREG_DMAC_DESCR6_PONG_SRC 0x401018d0u +#define CYREG_DMAC_DESCR6_PONG_DST 0x401018d4u +#define CYREG_DMAC_DESCR6_PONG_CTL 0x401018d8u +#define CYREG_DMAC_DESCR6_PONG_STATUS 0x401018dcu +#define CYDEV_DMAC_DESCR7_BASE 0x401018e0u +#define CYDEV_DMAC_DESCR7_SIZE 0x00000020u +#define CYREG_DMAC_DESCR7_PING_SRC 0x401018e0u +#define CYREG_DMAC_DESCR7_PING_DST 0x401018e4u +#define CYREG_DMAC_DESCR7_PING_CTL 0x401018e8u +#define CYREG_DMAC_DESCR7_PING_STATUS 0x401018ecu +#define CYREG_DMAC_DESCR7_PONG_SRC 0x401018f0u +#define CYREG_DMAC_DESCR7_PONG_DST 0x401018f4u +#define CYREG_DMAC_DESCR7_PONG_CTL 0x401018f8u +#define CYREG_DMAC_DESCR7_PONG_STATUS 0x401018fcu +#define CYDEV_SPCIF_BASE 0x40110000u +#define CYDEV_SPCIF_SIZE 0x00010000u +#define CYREG_SPCIF_GEOMETRY 0x40110000u +#define CYFLD_SPCIF_FLASH__OFFSET 0x00000000u +#define CYFLD_SPCIF_FLASH__SIZE 0x0000000eu +#define CYFLD_SPCIF_SFLASH__OFFSET 0x0000000eu +#define CYFLD_SPCIF_SFLASH__SIZE 0x00000006u +#define CYFLD_SPCIF_NUM_FLASH__OFFSET 0x00000014u +#define CYFLD_SPCIF_NUM_FLASH__SIZE 0x00000002u +#define CYFLD_SPCIF_FLASH_ROW__OFFSET 0x00000016u +#define CYFLD_SPCIF_FLASH_ROW__SIZE 0x00000002u +#define CYFLD_SPCIF_DE_CPD_LP__OFFSET 0x0000001fu +#define CYFLD_SPCIF_DE_CPD_LP__SIZE 0x00000001u +#define CYREG_SPCIF_INTR 0x401107f0u +#define CYFLD_SPCIF_TIMER__OFFSET 0x00000000u +#define CYFLD_SPCIF_TIMER__SIZE 0x00000001u +#define CYREG_SPCIF_INTR_SET 0x401107f4u +#define CYREG_SPCIF_INTR_MASK 0x401107f8u +#define CYREG_SPCIF_INTR_MASKED 0x401107fcu +#define CYDEV_TCPWM_BASE 0x40200000u +#define CYDEV_TCPWM_SIZE 0x00010000u +#define CYREG_TCPWM_CTRL 0x40200000u +#define CYFLD_TCPWM_COUNTER_ENABLED__OFFSET 0x00000000u +#define CYFLD_TCPWM_COUNTER_ENABLED__SIZE 0x00000008u +#define CYREG_TCPWM_CMD 0x40200008u +#define CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET 0x00000000u +#define CYFLD_TCPWM_COUNTER_CAPTURE__SIZE 0x00000008u +#define CYFLD_TCPWM_COUNTER_RELOAD__OFFSET 0x00000008u +#define CYFLD_TCPWM_COUNTER_RELOAD__SIZE 0x00000008u +#define CYFLD_TCPWM_COUNTER_STOP__OFFSET 0x00000010u +#define CYFLD_TCPWM_COUNTER_STOP__SIZE 0x00000008u +#define CYFLD_TCPWM_COUNTER_START__OFFSET 0x00000018u +#define CYFLD_TCPWM_COUNTER_START__SIZE 0x00000008u +#define CYREG_TCPWM_INTR_CAUSE 0x4020000cu +#define CYFLD_TCPWM_COUNTER_INT__OFFSET 0x00000000u +#define CYFLD_TCPWM_COUNTER_INT__SIZE 0x00000008u +#define CYDEV_TCPWM_CNT0_BASE 0x40200100u +#define CYDEV_TCPWM_CNT0_SIZE 0x00000040u +#define CYREG_TCPWM_CNT0_CTRL 0x40200100u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET 0x00000001u +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET 0x00000002u +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET 0x00000003u +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_GENERIC__OFFSET 0x00000008u +#define CYFLD_TCPWM_CNT_GENERIC__SIZE 0x00000008u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY1 0x00000000u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY2 0x00000001u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY4 0x00000002u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY8 0x00000003u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY16 0x00000004u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY32 0x00000005u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY64 0x00000006u +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY128 0x00000007u +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET 0x00000010u +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP 0x00000000u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN 0x00000001u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 0x00000002u +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 0x00000003u +#define CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET 0x00000012u +#define CYFLD_TCPWM_CNT_ONE_SHOT__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET 0x00000014u +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 0x00000000u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 0x00000001u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 0x00000002u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT 0x00000001u +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT 0x00000002u +#define CYFLD_TCPWM_CNT_MODE__OFFSET 0x00000018u +#define CYFLD_TCPWM_CNT_MODE__SIZE 0x00000003u +#define CYVAL_TCPWM_CNT_MODE_TIMER 0x00000000u +#define CYVAL_TCPWM_CNT_MODE_CAPTURE 0x00000002u +#define CYVAL_TCPWM_CNT_MODE_QUAD 0x00000003u +#define CYVAL_TCPWM_CNT_MODE_PWM 0x00000004u +#define CYVAL_TCPWM_CNT_MODE_PWM_DT 0x00000005u +#define CYVAL_TCPWM_CNT_MODE_PWM_PR 0x00000006u +#define CYREG_TCPWM_CNT0_STATUS 0x40200104u +#define CYFLD_TCPWM_CNT_DOWN__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_DOWN__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_RUNNING__OFFSET 0x0000001fu +#define CYFLD_TCPWM_CNT_RUNNING__SIZE 0x00000001u +#define CYREG_TCPWM_CNT0_COUNTER 0x40200108u +#define CYFLD_TCPWM_CNT_COUNTER__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_COUNTER__SIZE 0x00000010u +#define CYREG_TCPWM_CNT0_CC 0x4020010cu +#define CYFLD_TCPWM_CNT_CC__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CC__SIZE 0x00000010u +#define CYREG_TCPWM_CNT0_CC_BUFF 0x40200110u +#define CYREG_TCPWM_CNT0_PERIOD 0x40200114u +#define CYFLD_TCPWM_CNT_PERIOD__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_PERIOD__SIZE 0x00000010u +#define CYREG_TCPWM_CNT0_PERIOD_BUFF 0x40200118u +#define CYREG_TCPWM_CNT0_TR_CTRL0 0x40200120u +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET 0x00000004u +#define CYFLD_TCPWM_CNT_COUNT_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET 0x00000008u +#define CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_STOP_SEL__OFFSET 0x0000000cu +#define CYFLD_TCPWM_CNT_STOP_SEL__SIZE 0x00000004u +#define CYFLD_TCPWM_CNT_START_SEL__OFFSET 0x00000010u +#define CYFLD_TCPWM_CNT_START_SEL__SIZE 0x00000004u +#define CYREG_TCPWM_CNT0_TR_CTRL1 0x40200124u +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET 0x00000002u +#define CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET 0x00000004u +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET 0x00000006u +#define CYFLD_TCPWM_CNT_STOP_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET 0x00000003u +#define CYFLD_TCPWM_CNT_START_EDGE__OFFSET 0x00000008u +#define CYFLD_TCPWM_CNT_START_EDGE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE 0x00000000u +#define CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE 0x00000001u +#define CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES 0x00000002u +#define CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET 0x00000003u +#define CYREG_TCPWM_CNT0_TR_CTRL2 0x40200128u +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET 0x00000000u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR 0x00000001u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT 0x00000002u +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE 0x00000003u +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET 0x00000002u +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET 0x00000000u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR 0x00000001u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT 0x00000002u +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE 0x00000003u +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET 0x00000004u +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE 0x00000002u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET 0x00000000u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR 0x00000001u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT 0x00000002u +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE 0x00000003u +#define CYREG_TCPWM_CNT0_INTR 0x40200130u +#define CYFLD_TCPWM_CNT_TC__OFFSET 0x00000000u +#define CYFLD_TCPWM_CNT_TC__SIZE 0x00000001u +#define CYFLD_TCPWM_CNT_CC_MATCH__OFFSET 0x00000001u +#define CYFLD_TCPWM_CNT_CC_MATCH__SIZE 0x00000001u +#define CYREG_TCPWM_CNT0_INTR_SET 0x40200134u +#define CYREG_TCPWM_CNT0_INTR_MASK 0x40200138u +#define CYREG_TCPWM_CNT0_INTR_MASKED 0x4020013cu +#define CYDEV_TCPWM_CNT1_BASE 0x40200140u +#define CYDEV_TCPWM_CNT1_SIZE 0x00000040u +#define CYREG_TCPWM_CNT1_CTRL 0x40200140u +#define CYREG_TCPWM_CNT1_STATUS 0x40200144u +#define CYREG_TCPWM_CNT1_COUNTER 0x40200148u +#define CYREG_TCPWM_CNT1_CC 0x4020014cu +#define CYREG_TCPWM_CNT1_CC_BUFF 0x40200150u +#define CYREG_TCPWM_CNT1_PERIOD 0x40200154u +#define CYREG_TCPWM_CNT1_PERIOD_BUFF 0x40200158u +#define CYREG_TCPWM_CNT1_TR_CTRL0 0x40200160u +#define CYREG_TCPWM_CNT1_TR_CTRL1 0x40200164u +#define CYREG_TCPWM_CNT1_TR_CTRL2 0x40200168u +#define CYREG_TCPWM_CNT1_INTR 0x40200170u +#define CYREG_TCPWM_CNT1_INTR_SET 0x40200174u +#define CYREG_TCPWM_CNT1_INTR_MASK 0x40200178u +#define CYREG_TCPWM_CNT1_INTR_MASKED 0x4020017cu +#define CYDEV_TCPWM_CNT2_BASE 0x40200180u +#define CYDEV_TCPWM_CNT2_SIZE 0x00000040u +#define CYREG_TCPWM_CNT2_CTRL 0x40200180u +#define CYREG_TCPWM_CNT2_STATUS 0x40200184u +#define CYREG_TCPWM_CNT2_COUNTER 0x40200188u +#define CYREG_TCPWM_CNT2_CC 0x4020018cu +#define CYREG_TCPWM_CNT2_CC_BUFF 0x40200190u +#define CYREG_TCPWM_CNT2_PERIOD 0x40200194u +#define CYREG_TCPWM_CNT2_PERIOD_BUFF 0x40200198u +#define CYREG_TCPWM_CNT2_TR_CTRL0 0x402001a0u +#define CYREG_TCPWM_CNT2_TR_CTRL1 0x402001a4u +#define CYREG_TCPWM_CNT2_TR_CTRL2 0x402001a8u +#define CYREG_TCPWM_CNT2_INTR 0x402001b0u +#define CYREG_TCPWM_CNT2_INTR_SET 0x402001b4u +#define CYREG_TCPWM_CNT2_INTR_MASK 0x402001b8u +#define CYREG_TCPWM_CNT2_INTR_MASKED 0x402001bcu +#define CYDEV_TCPWM_CNT3_BASE 0x402001c0u +#define CYDEV_TCPWM_CNT3_SIZE 0x00000040u +#define CYREG_TCPWM_CNT3_CTRL 0x402001c0u +#define CYREG_TCPWM_CNT3_STATUS 0x402001c4u +#define CYREG_TCPWM_CNT3_COUNTER 0x402001c8u +#define CYREG_TCPWM_CNT3_CC 0x402001ccu +#define CYREG_TCPWM_CNT3_CC_BUFF 0x402001d0u +#define CYREG_TCPWM_CNT3_PERIOD 0x402001d4u +#define CYREG_TCPWM_CNT3_PERIOD_BUFF 0x402001d8u +#define CYREG_TCPWM_CNT3_TR_CTRL0 0x402001e0u +#define CYREG_TCPWM_CNT3_TR_CTRL1 0x402001e4u +#define CYREG_TCPWM_CNT3_TR_CTRL2 0x402001e8u +#define CYREG_TCPWM_CNT3_INTR 0x402001f0u +#define CYREG_TCPWM_CNT3_INTR_SET 0x402001f4u +#define CYREG_TCPWM_CNT3_INTR_MASK 0x402001f8u +#define CYREG_TCPWM_CNT3_INTR_MASKED 0x402001fcu +#define CYDEV_TCPWM_CNT4_BASE 0x40200200u +#define CYDEV_TCPWM_CNT4_SIZE 0x00000040u +#define CYREG_TCPWM_CNT4_CTRL 0x40200200u +#define CYREG_TCPWM_CNT4_STATUS 0x40200204u +#define CYREG_TCPWM_CNT4_COUNTER 0x40200208u +#define CYREG_TCPWM_CNT4_CC 0x4020020cu +#define CYREG_TCPWM_CNT4_CC_BUFF 0x40200210u +#define CYREG_TCPWM_CNT4_PERIOD 0x40200214u +#define CYREG_TCPWM_CNT4_PERIOD_BUFF 0x40200218u +#define CYREG_TCPWM_CNT4_TR_CTRL0 0x40200220u +#define CYREG_TCPWM_CNT4_TR_CTRL1 0x40200224u +#define CYREG_TCPWM_CNT4_TR_CTRL2 0x40200228u +#define CYREG_TCPWM_CNT4_INTR 0x40200230u +#define CYREG_TCPWM_CNT4_INTR_SET 0x40200234u +#define CYREG_TCPWM_CNT4_INTR_MASK 0x40200238u +#define CYREG_TCPWM_CNT4_INTR_MASKED 0x4020023cu +#define CYDEV_TCPWM_CNT5_BASE 0x40200240u +#define CYDEV_TCPWM_CNT5_SIZE 0x00000040u +#define CYREG_TCPWM_CNT5_CTRL 0x40200240u +#define CYREG_TCPWM_CNT5_STATUS 0x40200244u +#define CYREG_TCPWM_CNT5_COUNTER 0x40200248u +#define CYREG_TCPWM_CNT5_CC 0x4020024cu +#define CYREG_TCPWM_CNT5_CC_BUFF 0x40200250u +#define CYREG_TCPWM_CNT5_PERIOD 0x40200254u +#define CYREG_TCPWM_CNT5_PERIOD_BUFF 0x40200258u +#define CYREG_TCPWM_CNT5_TR_CTRL0 0x40200260u +#define CYREG_TCPWM_CNT5_TR_CTRL1 0x40200264u +#define CYREG_TCPWM_CNT5_TR_CTRL2 0x40200268u +#define CYREG_TCPWM_CNT5_INTR 0x40200270u +#define CYREG_TCPWM_CNT5_INTR_SET 0x40200274u +#define CYREG_TCPWM_CNT5_INTR_MASK 0x40200278u +#define CYREG_TCPWM_CNT5_INTR_MASKED 0x4020027cu +#define CYDEV_TCPWM_CNT6_BASE 0x40200280u +#define CYDEV_TCPWM_CNT6_SIZE 0x00000040u +#define CYREG_TCPWM_CNT6_CTRL 0x40200280u +#define CYREG_TCPWM_CNT6_STATUS 0x40200284u +#define CYREG_TCPWM_CNT6_COUNTER 0x40200288u +#define CYREG_TCPWM_CNT6_CC 0x4020028cu +#define CYREG_TCPWM_CNT6_CC_BUFF 0x40200290u +#define CYREG_TCPWM_CNT6_PERIOD 0x40200294u +#define CYREG_TCPWM_CNT6_PERIOD_BUFF 0x40200298u +#define CYREG_TCPWM_CNT6_TR_CTRL0 0x402002a0u +#define CYREG_TCPWM_CNT6_TR_CTRL1 0x402002a4u +#define CYREG_TCPWM_CNT6_TR_CTRL2 0x402002a8u +#define CYREG_TCPWM_CNT6_INTR 0x402002b0u +#define CYREG_TCPWM_CNT6_INTR_SET 0x402002b4u +#define CYREG_TCPWM_CNT6_INTR_MASK 0x402002b8u +#define CYREG_TCPWM_CNT6_INTR_MASKED 0x402002bcu +#define CYDEV_TCPWM_CNT7_BASE 0x402002c0u +#define CYDEV_TCPWM_CNT7_SIZE 0x00000040u +#define CYREG_TCPWM_CNT7_CTRL 0x402002c0u +#define CYREG_TCPWM_CNT7_STATUS 0x402002c4u +#define CYREG_TCPWM_CNT7_COUNTER 0x402002c8u +#define CYREG_TCPWM_CNT7_CC 0x402002ccu +#define CYREG_TCPWM_CNT7_CC_BUFF 0x402002d0u +#define CYREG_TCPWM_CNT7_PERIOD 0x402002d4u +#define CYREG_TCPWM_CNT7_PERIOD_BUFF 0x402002d8u +#define CYREG_TCPWM_CNT7_TR_CTRL0 0x402002e0u +#define CYREG_TCPWM_CNT7_TR_CTRL1 0x402002e4u +#define CYREG_TCPWM_CNT7_TR_CTRL2 0x402002e8u +#define CYREG_TCPWM_CNT7_INTR 0x402002f0u +#define CYREG_TCPWM_CNT7_INTR_SET 0x402002f4u +#define CYREG_TCPWM_CNT7_INTR_MASK 0x402002f8u +#define CYREG_TCPWM_CNT7_INTR_MASKED 0x402002fcu +#define CYDEV_WCO_BASE 0x40220000u +#define CYDEV_WCO_SIZE 0x00010000u +#define CYREG_WCO_CONFIG 0x40220000u +#define CYFLD_WCO_LPM_EN__OFFSET 0x00000000u +#define CYFLD_WCO_LPM_EN__SIZE 0x00000001u +#define CYFLD_WCO_LPM_AUTO__OFFSET 0x00000001u +#define CYFLD_WCO_LPM_AUTO__SIZE 0x00000001u +#define CYFLD_WCO_EXT_INPUT_EN__OFFSET 0x00000002u +#define CYFLD_WCO_EXT_INPUT_EN__SIZE 0x00000001u +#define CYFLD_WCO_ENBUS__OFFSET 0x00000010u +#define CYFLD_WCO_ENBUS__SIZE 0x00000008u +#define CYFLD_WCO_DPLL_ENABLE__OFFSET 0x0000001eu +#define CYFLD_WCO_DPLL_ENABLE__SIZE 0x00000001u +#define CYFLD_WCO_IP_ENABLE__OFFSET 0x0000001fu +#define CYFLD_WCO_IP_ENABLE__SIZE 0x00000001u +#define CYREG_WCO_STATUS 0x40220004u +#define CYFLD_WCO_OUT_BLNK_A__OFFSET 0x00000000u +#define CYFLD_WCO_OUT_BLNK_A__SIZE 0x00000001u +#define CYREG_WCO_DPLL 0x40220008u +#define CYFLD_WCO_DPLL_MULT__OFFSET 0x00000000u +#define CYFLD_WCO_DPLL_MULT__SIZE 0x0000000bu +#define CYFLD_WCO_DPLL_LF_IGAIN__OFFSET 0x00000010u +#define CYFLD_WCO_DPLL_LF_IGAIN__SIZE 0x00000003u +#define CYFLD_WCO_DPLL_LF_PGAIN__OFFSET 0x00000013u +#define CYFLD_WCO_DPLL_LF_PGAIN__SIZE 0x00000003u +#define CYFLD_WCO_DPLL_LF_LIMIT__OFFSET 0x00000016u +#define CYFLD_WCO_DPLL_LF_LIMIT__SIZE 0x00000008u +#define CYREG_WCO_WDT_CTRLOW 0x40220200u +#define CYFLD_WCO_WDT_CTR0__OFFSET 0x00000000u +#define CYFLD_WCO_WDT_CTR0__SIZE 0x00000010u +#define CYFLD_WCO_WDT_CTR1__OFFSET 0x00000010u +#define CYFLD_WCO_WDT_CTR1__SIZE 0x00000010u +#define CYREG_WCO_WDT_CTRHIGH 0x40220204u +#define CYFLD_WCO_WDT_CTR2__OFFSET 0x00000000u +#define CYFLD_WCO_WDT_CTR2__SIZE 0x00000020u +#define CYREG_WCO_WDT_MATCH 0x40220208u +#define CYFLD_WCO_WDT_MATCH0__OFFSET 0x00000000u +#define CYFLD_WCO_WDT_MATCH0__SIZE 0x00000010u +#define CYFLD_WCO_WDT_MATCH1__OFFSET 0x00000010u +#define CYFLD_WCO_WDT_MATCH1__SIZE 0x00000010u +#define CYREG_WCO_WDT_CONFIG 0x4022020cu +#define CYFLD_WCO_WDT_MODE0__OFFSET 0x00000000u +#define CYFLD_WCO_WDT_MODE0__SIZE 0x00000002u +#define CYVAL_WCO_WDT_MODE0_NOTHING 0x00000000u +#define CYVAL_WCO_WDT_MODE0_INT 0x00000001u +#define CYVAL_WCO_WDT_MODE0_RESET 0x00000002u +#define CYVAL_WCO_WDT_MODE0_INT_THEN_RESET 0x00000003u +#define CYFLD_WCO_WDT_CLEAR0__OFFSET 0x00000002u +#define CYFLD_WCO_WDT_CLEAR0__SIZE 0x00000001u +#define CYFLD_WCO_WDT_CASCADE0_1__OFFSET 0x00000003u +#define CYFLD_WCO_WDT_CASCADE0_1__SIZE 0x00000001u +#define CYFLD_WCO_WDT_MODE1__OFFSET 0x00000008u +#define CYFLD_WCO_WDT_MODE1__SIZE 0x00000002u +#define CYVAL_WCO_WDT_MODE1_NOTHING 0x00000000u +#define CYVAL_WCO_WDT_MODE1_INT 0x00000001u +#define CYVAL_WCO_WDT_MODE1_RESET 0x00000002u +#define CYVAL_WCO_WDT_MODE1_INT_THEN_RESET 0x00000003u +#define CYFLD_WCO_WDT_CLEAR1__OFFSET 0x0000000au +#define CYFLD_WCO_WDT_CLEAR1__SIZE 0x00000001u +#define CYFLD_WCO_WDT_CASCADE1_2__OFFSET 0x0000000bu +#define CYFLD_WCO_WDT_CASCADE1_2__SIZE 0x00000001u +#define CYFLD_WCO_WDT_MODE2__OFFSET 0x00000010u +#define CYFLD_WCO_WDT_MODE2__SIZE 0x00000001u +#define CYVAL_WCO_WDT_MODE2_NOTHING 0x00000000u +#define CYVAL_WCO_WDT_MODE2_INT 0x00000001u +#define CYFLD_WCO_WDT_BITS2__OFFSET 0x00000018u +#define CYFLD_WCO_WDT_BITS2__SIZE 0x00000005u +#define CYFLD_WCO_LFCLK_SEL__OFFSET 0x0000001eu +#define CYFLD_WCO_LFCLK_SEL__SIZE 0x00000002u +#define CYREG_WCO_WDT_CONTROL 0x40220210u +#define CYFLD_WCO_WDT_ENABLE0__OFFSET 0x00000000u +#define CYFLD_WCO_WDT_ENABLE0__SIZE 0x00000001u +#define CYFLD_WCO_WDT_ENABLED0__OFFSET 0x00000001u +#define CYFLD_WCO_WDT_ENABLED0__SIZE 0x00000001u +#define CYFLD_WCO_WDT_INT0__OFFSET 0x00000002u +#define CYFLD_WCO_WDT_INT0__SIZE 0x00000001u +#define CYFLD_WCO_WDT_RESET0__OFFSET 0x00000003u +#define CYFLD_WCO_WDT_RESET0__SIZE 0x00000001u +#define CYFLD_WCO_WDT_ENABLE1__OFFSET 0x00000008u +#define CYFLD_WCO_WDT_ENABLE1__SIZE 0x00000001u +#define CYFLD_WCO_WDT_ENABLED1__OFFSET 0x00000009u +#define CYFLD_WCO_WDT_ENABLED1__SIZE 0x00000001u +#define CYFLD_WCO_WDT_INT1__OFFSET 0x0000000au +#define CYFLD_WCO_WDT_INT1__SIZE 0x00000001u +#define CYFLD_WCO_WDT_RESET1__OFFSET 0x0000000bu +#define CYFLD_WCO_WDT_RESET1__SIZE 0x00000001u +#define CYFLD_WCO_WDT_ENABLE2__OFFSET 0x00000010u +#define CYFLD_WCO_WDT_ENABLE2__SIZE 0x00000001u +#define CYFLD_WCO_WDT_ENABLED2__OFFSET 0x00000011u +#define CYFLD_WCO_WDT_ENABLED2__SIZE 0x00000001u +#define CYFLD_WCO_WDT_INT2__OFFSET 0x00000012u +#define CYFLD_WCO_WDT_INT2__SIZE 0x00000001u +#define CYFLD_WCO_WDT_RESET2__OFFSET 0x00000013u +#define CYFLD_WCO_WDT_RESET2__SIZE 0x00000001u +#define CYREG_WCO_WDT_CLKEN 0x40220214u +#define CYFLD_WCO_CLK_WCO_EN_FOR_WDT__OFFSET 0x00000000u +#define CYFLD_WCO_CLK_WCO_EN_FOR_WDT__SIZE 0x00000001u +#define CYFLD_WCO_CLK_ILO_EN_FOR_WDT__OFFSET 0x00000001u +#define CYFLD_WCO_CLK_ILO_EN_FOR_WDT__SIZE 0x00000001u +#define CYREG_WCO_TRIM 0x40220f00u +#define CYFLD_WCO_XGM__OFFSET 0x00000000u +#define CYFLD_WCO_XGM__SIZE 0x00000003u +#define CYFLD_WCO_LPM_GM__OFFSET 0x00000004u +#define CYFLD_WCO_LPM_GM__SIZE 0x00000002u +#define CYDEV_SCB0_BASE 0x40240000u +#define CYDEV_SCB0_SIZE 0x00010000u +#define CYREG_SCB0_CTRL 0x40240000u +#define CYFLD_SCB_OVS__OFFSET 0x00000000u +#define CYFLD_SCB_OVS__SIZE 0x00000004u +#define CYFLD_SCB_EC_AM_MODE__OFFSET 0x00000008u +#define CYFLD_SCB_EC_AM_MODE__SIZE 0x00000001u +#define CYFLD_SCB_EC_OP_MODE__OFFSET 0x00000009u +#define CYFLD_SCB_EC_OP_MODE__SIZE 0x00000001u +#define CYFLD_SCB_EZ_MODE__OFFSET 0x0000000au +#define CYFLD_SCB_EZ_MODE__SIZE 0x00000001u +#define CYFLD_SCB_BYTE_MODE__OFFSET 0x0000000bu +#define CYFLD_SCB_BYTE_MODE__SIZE 0x00000001u +#define CYFLD_SCB_ADDR_ACCEPT__OFFSET 0x00000010u +#define CYFLD_SCB_ADDR_ACCEPT__SIZE 0x00000001u +#define CYFLD_SCB_BLOCK__OFFSET 0x00000011u +#define CYFLD_SCB_BLOCK__SIZE 0x00000001u +#define CYFLD_SCB_MODE__OFFSET 0x00000018u +#define CYFLD_SCB_MODE__SIZE 0x00000002u +#define CYVAL_SCB_MODE_I2C 0x00000000u +#define CYVAL_SCB_MODE_SPI 0x00000001u +#define CYVAL_SCB_MODE_UART 0x00000002u +#define CYFLD_SCB_ENABLED__OFFSET 0x0000001fu +#define CYFLD_SCB_ENABLED__SIZE 0x00000001u +#define CYREG_SCB0_STATUS 0x40240004u +#define CYFLD_SCB_EC_BUSY__OFFSET 0x00000000u +#define CYFLD_SCB_EC_BUSY__SIZE 0x00000001u +#define CYREG_SCB0_SPI_CTRL 0x40240020u +#define CYFLD_SCB_CONTINUOUS__OFFSET 0x00000000u +#define CYFLD_SCB_CONTINUOUS__SIZE 0x00000001u +#define CYFLD_SCB_SELECT_PRECEDE__OFFSET 0x00000001u +#define CYFLD_SCB_SELECT_PRECEDE__SIZE 0x00000001u +#define CYFLD_SCB_CPHA__OFFSET 0x00000002u +#define CYFLD_SCB_CPHA__SIZE 0x00000001u +#define CYFLD_SCB_CPOL__OFFSET 0x00000003u +#define CYFLD_SCB_CPOL__SIZE 0x00000001u +#define CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET 0x00000004u +#define CYFLD_SCB_LATE_MISO_SAMPLE__SIZE 0x00000001u +#define CYFLD_SCB_SCLK_CONTINUOUS__OFFSET 0x00000005u +#define CYFLD_SCB_SCLK_CONTINUOUS__SIZE 0x00000001u +#define CYFLD_SCB_SSEL_POLARITY0__OFFSET 0x00000008u +#define CYFLD_SCB_SSEL_POLARITY0__SIZE 0x00000001u +#define CYFLD_SCB_SSEL_POLARITY1__OFFSET 0x00000009u +#define CYFLD_SCB_SSEL_POLARITY1__SIZE 0x00000001u +#define CYFLD_SCB_SSEL_POLARITY2__OFFSET 0x0000000au +#define CYFLD_SCB_SSEL_POLARITY2__SIZE 0x00000001u +#define CYFLD_SCB_SSEL_POLARITY3__OFFSET 0x0000000bu +#define CYFLD_SCB_SSEL_POLARITY3__SIZE 0x00000001u +#define CYFLD_SCB_LOOPBACK__OFFSET 0x00000010u +#define CYFLD_SCB_LOOPBACK__SIZE 0x00000001u +#define CYFLD_SCB_SLAVE_SELECT__OFFSET 0x0000001au +#define CYFLD_SCB_SLAVE_SELECT__SIZE 0x00000002u +#define CYFLD_SCB_MASTER_MODE__OFFSET 0x0000001fu +#define CYFLD_SCB_MASTER_MODE__SIZE 0x00000001u +#define CYREG_SCB0_SPI_STATUS 0x40240024u +#define CYFLD_SCB_BUS_BUSY__OFFSET 0x00000000u +#define CYFLD_SCB_BUS_BUSY__SIZE 0x00000001u +#define CYFLD_SCB_SPI_EC_BUSY__OFFSET 0x00000001u +#define CYFLD_SCB_SPI_EC_BUSY__SIZE 0x00000001u +#define CYFLD_SCB_CURR_EZ_ADDR__OFFSET 0x00000008u +#define CYFLD_SCB_CURR_EZ_ADDR__SIZE 0x00000008u +#define CYFLD_SCB_BASE_EZ_ADDR__OFFSET 0x00000010u +#define CYFLD_SCB_BASE_EZ_ADDR__SIZE 0x00000008u +#define CYREG_SCB0_UART_CTRL 0x40240040u +#define CYREG_SCB0_UART_TX_CTRL 0x40240044u +#define CYFLD_SCB_STOP_BITS__OFFSET 0x00000000u +#define CYFLD_SCB_STOP_BITS__SIZE 0x00000003u +#define CYFLD_SCB_PARITY__OFFSET 0x00000004u +#define CYFLD_SCB_PARITY__SIZE 0x00000001u +#define CYFLD_SCB_PARITY_ENABLED__OFFSET 0x00000005u +#define CYFLD_SCB_PARITY_ENABLED__SIZE 0x00000001u +#define CYFLD_SCB_RETRY_ON_NACK__OFFSET 0x00000008u +#define CYFLD_SCB_RETRY_ON_NACK__SIZE 0x00000001u +#define CYREG_SCB0_UART_RX_CTRL 0x40240048u +#define CYFLD_SCB_POLARITY__OFFSET 0x00000006u +#define CYFLD_SCB_POLARITY__SIZE 0x00000001u +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET 0x00000008u +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET 0x00000009u +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_MP_MODE__OFFSET 0x0000000au +#define CYFLD_SCB_MP_MODE__SIZE 0x00000001u +#define CYFLD_SCB_LIN_MODE__OFFSET 0x0000000cu +#define CYFLD_SCB_LIN_MODE__SIZE 0x00000001u +#define CYFLD_SCB_SKIP_START__OFFSET 0x0000000du +#define CYFLD_SCB_SKIP_START__SIZE 0x00000001u +#define CYFLD_SCB_BREAK_WIDTH__OFFSET 0x00000010u +#define CYFLD_SCB_BREAK_WIDTH__SIZE 0x00000004u +#define CYREG_SCB0_UART_RX_STATUS 0x4024004cu +#define CYFLD_SCB_BR_COUNTER__OFFSET 0x00000000u +#define CYFLD_SCB_BR_COUNTER__SIZE 0x0000000cu +#define CYREG_SCB0_UART_FLOW_CTRL 0x40240050u +#define CYFLD_SCB_TRIGGER_LEVEL__OFFSET 0x00000000u +#define CYFLD_SCB_TRIGGER_LEVEL__SIZE 0x00000004u +#define CYFLD_SCB_RTS_POLARITY__OFFSET 0x00000010u +#define CYFLD_SCB_RTS_POLARITY__SIZE 0x00000001u +#define CYFLD_SCB_CTS_POLARITY__OFFSET 0x00000018u +#define CYFLD_SCB_CTS_POLARITY__SIZE 0x00000001u +#define CYFLD_SCB_CTS_ENABLED__OFFSET 0x00000019u +#define CYFLD_SCB_CTS_ENABLED__SIZE 0x00000001u +#define CYREG_SCB0_I2C_CTRL 0x40240060u +#define CYFLD_SCB_HIGH_PHASE_OVS__OFFSET 0x00000000u +#define CYFLD_SCB_HIGH_PHASE_OVS__SIZE 0x00000004u +#define CYFLD_SCB_LOW_PHASE_OVS__OFFSET 0x00000004u +#define CYFLD_SCB_LOW_PHASE_OVS__SIZE 0x00000004u +#define CYFLD_SCB_M_READY_DATA_ACK__OFFSET 0x00000008u +#define CYFLD_SCB_M_READY_DATA_ACK__SIZE 0x00000001u +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET 0x00000009u +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE 0x00000001u +#define CYFLD_SCB_S_GENERAL_IGNORE__OFFSET 0x0000000bu +#define CYFLD_SCB_S_GENERAL_IGNORE__SIZE 0x00000001u +#define CYFLD_SCB_S_READY_ADDR_ACK__OFFSET 0x0000000cu +#define CYFLD_SCB_S_READY_ADDR_ACK__SIZE 0x00000001u +#define CYFLD_SCB_S_READY_DATA_ACK__OFFSET 0x0000000du +#define CYFLD_SCB_S_READY_DATA_ACK__SIZE 0x00000001u +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET 0x0000000eu +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE 0x00000001u +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET 0x0000000fu +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE 0x00000001u +#define CYFLD_SCB_SLAVE_MODE__OFFSET 0x0000001eu +#define CYFLD_SCB_SLAVE_MODE__SIZE 0x00000001u +#define CYREG_SCB0_I2C_STATUS 0x40240064u +#define CYFLD_SCB_I2C_EC_BUSY__OFFSET 0x00000001u +#define CYFLD_SCB_I2C_EC_BUSY__SIZE 0x00000001u +#define CYFLD_SCB_S_READ__OFFSET 0x00000004u +#define CYFLD_SCB_S_READ__SIZE 0x00000001u +#define CYFLD_SCB_M_READ__OFFSET 0x00000005u +#define CYFLD_SCB_M_READ__SIZE 0x00000001u +#define CYREG_SCB0_I2C_M_CMD 0x40240068u +#define CYFLD_SCB_M_START__OFFSET 0x00000000u +#define CYFLD_SCB_M_START__SIZE 0x00000001u +#define CYFLD_SCB_M_START_ON_IDLE__OFFSET 0x00000001u +#define CYFLD_SCB_M_START_ON_IDLE__SIZE 0x00000001u +#define CYFLD_SCB_M_ACK__OFFSET 0x00000002u +#define CYFLD_SCB_M_ACK__SIZE 0x00000001u +#define CYFLD_SCB_M_NACK__OFFSET 0x00000003u +#define CYFLD_SCB_M_NACK__SIZE 0x00000001u +#define CYFLD_SCB_M_STOP__OFFSET 0x00000004u +#define CYFLD_SCB_M_STOP__SIZE 0x00000001u +#define CYREG_SCB0_I2C_S_CMD 0x4024006cu +#define CYFLD_SCB_S_ACK__OFFSET 0x00000000u +#define CYFLD_SCB_S_ACK__SIZE 0x00000001u +#define CYFLD_SCB_S_NACK__OFFSET 0x00000001u +#define CYFLD_SCB_S_NACK__SIZE 0x00000001u +#define CYREG_SCB0_I2C_CFG 0x40240070u +#define CYFLD_SCB_SDA_IN_FILT_TRIM__OFFSET 0x00000000u +#define CYFLD_SCB_SDA_IN_FILT_TRIM__SIZE 0x00000002u +#define CYFLD_SCB_SDA_IN_FILT_SEL__OFFSET 0x00000004u +#define CYFLD_SCB_SDA_IN_FILT_SEL__SIZE 0x00000001u +#define CYFLD_SCB_SCL_IN_FILT_TRIM__OFFSET 0x00000008u +#define CYFLD_SCB_SCL_IN_FILT_TRIM__SIZE 0x00000002u +#define CYFLD_SCB_SCL_IN_FILT_SEL__OFFSET 0x0000000cu +#define CYFLD_SCB_SCL_IN_FILT_SEL__SIZE 0x00000001u +#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__OFFSET 0x00000010u +#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__SIZE 0x00000002u +#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__OFFSET 0x00000012u +#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__SIZE 0x00000002u +#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__OFFSET 0x00000014u +#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__SIZE 0x00000002u +#define CYFLD_SCB_SDA_OUT_FILT_SEL__OFFSET 0x0000001cu +#define CYFLD_SCB_SDA_OUT_FILT_SEL__SIZE 0x00000002u +#define CYREG_SCB0_TX_CTRL 0x40240200u +#define CYFLD_SCB_DATA_WIDTH__OFFSET 0x00000000u +#define CYFLD_SCB_DATA_WIDTH__SIZE 0x00000004u +#define CYFLD_SCB_MSB_FIRST__OFFSET 0x00000008u +#define CYFLD_SCB_MSB_FIRST__SIZE 0x00000001u +#define CYREG_SCB0_TX_FIFO_CTRL 0x40240204u +#define CYFLD_SCB_CLEAR__OFFSET 0x00000010u +#define CYFLD_SCB_CLEAR__SIZE 0x00000001u +#define CYFLD_SCB_FREEZE__OFFSET 0x00000011u +#define CYFLD_SCB_FREEZE__SIZE 0x00000001u +#define CYREG_SCB0_TX_FIFO_STATUS 0x40240208u +#define CYFLD_SCB_USED__OFFSET 0x00000000u +#define CYFLD_SCB_USED__SIZE 0x00000005u +#define CYFLD_SCB_SR_VALID__OFFSET 0x0000000fu +#define CYFLD_SCB_SR_VALID__SIZE 0x00000001u +#define CYFLD_SCB_RD_PTR__OFFSET 0x00000010u +#define CYFLD_SCB_RD_PTR__SIZE 0x00000004u +#define CYFLD_SCB_WR_PTR__OFFSET 0x00000018u +#define CYFLD_SCB_WR_PTR__SIZE 0x00000004u +#define CYREG_SCB0_TX_FIFO_WR 0x40240240u +#define CYFLD_SCB_DATA__OFFSET 0x00000000u +#define CYFLD_SCB_DATA__SIZE 0x00000010u +#define CYREG_SCB0_RX_CTRL 0x40240300u +#define CYFLD_SCB_MEDIAN__OFFSET 0x00000009u +#define CYFLD_SCB_MEDIAN__SIZE 0x00000001u +#define CYREG_SCB0_RX_FIFO_CTRL 0x40240304u +#define CYREG_SCB0_RX_FIFO_STATUS 0x40240308u +#define CYREG_SCB0_RX_MATCH 0x40240310u +#define CYFLD_SCB_ADDR__OFFSET 0x00000000u +#define CYFLD_SCB_ADDR__SIZE 0x00000008u +#define CYFLD_SCB_MASK__OFFSET 0x00000010u +#define CYFLD_SCB_MASK__SIZE 0x00000008u +#define CYREG_SCB0_RX_FIFO_RD 0x40240340u +#define CYREG_SCB0_RX_FIFO_RD_SILENT 0x40240344u +#define CYREG_SCB0_EZ_DATA0 0x40240400u +#define CYFLD_SCB_EZ_DATA__OFFSET 0x00000000u +#define CYFLD_SCB_EZ_DATA__SIZE 0x00000008u +#define CYREG_SCB0_EZ_DATA1 0x40240404u +#define CYREG_SCB0_EZ_DATA2 0x40240408u +#define CYREG_SCB0_EZ_DATA3 0x4024040cu +#define CYREG_SCB0_EZ_DATA4 0x40240410u +#define CYREG_SCB0_EZ_DATA5 0x40240414u +#define CYREG_SCB0_EZ_DATA6 0x40240418u +#define CYREG_SCB0_EZ_DATA7 0x4024041cu +#define CYREG_SCB0_EZ_DATA8 0x40240420u +#define CYREG_SCB0_EZ_DATA9 0x40240424u +#define CYREG_SCB0_EZ_DATA10 0x40240428u +#define CYREG_SCB0_EZ_DATA11 0x4024042cu +#define CYREG_SCB0_EZ_DATA12 0x40240430u +#define CYREG_SCB0_EZ_DATA13 0x40240434u +#define CYREG_SCB0_EZ_DATA14 0x40240438u +#define CYREG_SCB0_EZ_DATA15 0x4024043cu +#define CYREG_SCB0_EZ_DATA16 0x40240440u +#define CYREG_SCB0_EZ_DATA17 0x40240444u +#define CYREG_SCB0_EZ_DATA18 0x40240448u +#define CYREG_SCB0_EZ_DATA19 0x4024044cu +#define CYREG_SCB0_EZ_DATA20 0x40240450u +#define CYREG_SCB0_EZ_DATA21 0x40240454u +#define CYREG_SCB0_EZ_DATA22 0x40240458u +#define CYREG_SCB0_EZ_DATA23 0x4024045cu +#define CYREG_SCB0_EZ_DATA24 0x40240460u +#define CYREG_SCB0_EZ_DATA25 0x40240464u +#define CYREG_SCB0_EZ_DATA26 0x40240468u +#define CYREG_SCB0_EZ_DATA27 0x4024046cu +#define CYREG_SCB0_EZ_DATA28 0x40240470u +#define CYREG_SCB0_EZ_DATA29 0x40240474u +#define CYREG_SCB0_EZ_DATA30 0x40240478u +#define CYREG_SCB0_EZ_DATA31 0x4024047cu +#define CYREG_SCB0_INTR_CAUSE 0x40240e00u +#define CYFLD_SCB_M__OFFSET 0x00000000u +#define CYFLD_SCB_M__SIZE 0x00000001u +#define CYFLD_SCB_S__OFFSET 0x00000001u +#define CYFLD_SCB_S__SIZE 0x00000001u +#define CYFLD_SCB_TX__OFFSET 0x00000002u +#define CYFLD_SCB_TX__SIZE 0x00000001u +#define CYFLD_SCB_RX__OFFSET 0x00000003u +#define CYFLD_SCB_RX__SIZE 0x00000001u +#define CYFLD_SCB_I2C_EC__OFFSET 0x00000004u +#define CYFLD_SCB_I2C_EC__SIZE 0x00000001u +#define CYFLD_SCB_SPI_EC__OFFSET 0x00000005u +#define CYFLD_SCB_SPI_EC__SIZE 0x00000001u +#define CYREG_SCB0_INTR_I2C_EC 0x40240e80u +#define CYFLD_SCB_WAKE_UP__OFFSET 0x00000000u +#define CYFLD_SCB_WAKE_UP__SIZE 0x00000001u +#define CYFLD_SCB_EZ_STOP__OFFSET 0x00000001u +#define CYFLD_SCB_EZ_STOP__SIZE 0x00000001u +#define CYFLD_SCB_EZ_WRITE_STOP__OFFSET 0x00000002u +#define CYFLD_SCB_EZ_WRITE_STOP__SIZE 0x00000001u +#define CYFLD_SCB_EZ_READ_STOP__OFFSET 0x00000003u +#define CYFLD_SCB_EZ_READ_STOP__SIZE 0x00000001u +#define CYREG_SCB0_INTR_I2C_EC_MASK 0x40240e88u +#define CYREG_SCB0_INTR_I2C_EC_MASKED 0x40240e8cu +#define CYREG_SCB0_INTR_SPI_EC 0x40240ec0u +#define CYREG_SCB0_INTR_SPI_EC_MASK 0x40240ec8u +#define CYREG_SCB0_INTR_SPI_EC_MASKED 0x40240eccu +#define CYREG_SCB0_INTR_M 0x40240f00u +#define CYFLD_SCB_I2C_ARB_LOST__OFFSET 0x00000000u +#define CYFLD_SCB_I2C_ARB_LOST__SIZE 0x00000001u +#define CYFLD_SCB_I2C_NACK__OFFSET 0x00000001u +#define CYFLD_SCB_I2C_NACK__SIZE 0x00000001u +#define CYFLD_SCB_I2C_ACK__OFFSET 0x00000002u +#define CYFLD_SCB_I2C_ACK__SIZE 0x00000001u +#define CYFLD_SCB_I2C_STOP__OFFSET 0x00000004u +#define CYFLD_SCB_I2C_STOP__SIZE 0x00000001u +#define CYFLD_SCB_I2C_BUS_ERROR__OFFSET 0x00000008u +#define CYFLD_SCB_I2C_BUS_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_SPI_DONE__OFFSET 0x00000009u +#define CYFLD_SCB_SPI_DONE__SIZE 0x00000001u +#define CYREG_SCB0_INTR_M_SET 0x40240f04u +#define CYREG_SCB0_INTR_M_MASK 0x40240f08u +#define CYREG_SCB0_INTR_M_MASKED 0x40240f0cu +#define CYREG_SCB0_INTR_S 0x40240f40u +#define CYFLD_SCB_I2C_WRITE_STOP__OFFSET 0x00000003u +#define CYFLD_SCB_I2C_WRITE_STOP__SIZE 0x00000001u +#define CYFLD_SCB_I2C_START__OFFSET 0x00000005u +#define CYFLD_SCB_I2C_START__SIZE 0x00000001u +#define CYFLD_SCB_I2C_ADDR_MATCH__OFFSET 0x00000006u +#define CYFLD_SCB_I2C_ADDR_MATCH__SIZE 0x00000001u +#define CYFLD_SCB_I2C_GENERAL__OFFSET 0x00000007u +#define CYFLD_SCB_I2C_GENERAL__SIZE 0x00000001u +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET 0x00000009u +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE 0x00000001u +#define CYFLD_SCB_SPI_EZ_STOP__OFFSET 0x0000000au +#define CYFLD_SCB_SPI_EZ_STOP__SIZE 0x00000001u +#define CYFLD_SCB_SPI_BUS_ERROR__OFFSET 0x0000000bu +#define CYFLD_SCB_SPI_BUS_ERROR__SIZE 0x00000001u +#define CYREG_SCB0_INTR_S_SET 0x40240f44u +#define CYREG_SCB0_INTR_S_MASK 0x40240f48u +#define CYREG_SCB0_INTR_S_MASKED 0x40240f4cu +#define CYREG_SCB0_INTR_TX 0x40240f80u +#define CYFLD_SCB_TRIGGER__OFFSET 0x00000000u +#define CYFLD_SCB_TRIGGER__SIZE 0x00000001u +#define CYFLD_SCB_NOT_FULL__OFFSET 0x00000001u +#define CYFLD_SCB_NOT_FULL__SIZE 0x00000001u +#define CYFLD_SCB_EMPTY__OFFSET 0x00000004u +#define CYFLD_SCB_EMPTY__SIZE 0x00000001u +#define CYFLD_SCB_OVERFLOW__OFFSET 0x00000005u +#define CYFLD_SCB_OVERFLOW__SIZE 0x00000001u +#define CYFLD_SCB_UNDERFLOW__OFFSET 0x00000006u +#define CYFLD_SCB_UNDERFLOW__SIZE 0x00000001u +#define CYFLD_SCB_BLOCKED__OFFSET 0x00000007u +#define CYFLD_SCB_BLOCKED__SIZE 0x00000001u +#define CYFLD_SCB_UART_NACK__OFFSET 0x00000008u +#define CYFLD_SCB_UART_NACK__SIZE 0x00000001u +#define CYFLD_SCB_UART_DONE__OFFSET 0x00000009u +#define CYFLD_SCB_UART_DONE__SIZE 0x00000001u +#define CYFLD_SCB_UART_ARB_LOST__OFFSET 0x0000000au +#define CYFLD_SCB_UART_ARB_LOST__SIZE 0x00000001u +#define CYREG_SCB0_INTR_TX_SET 0x40240f84u +#define CYREG_SCB0_INTR_TX_MASK 0x40240f88u +#define CYREG_SCB0_INTR_TX_MASKED 0x40240f8cu +#define CYREG_SCB0_INTR_RX 0x40240fc0u +#define CYFLD_SCB_NOT_EMPTY__OFFSET 0x00000002u +#define CYFLD_SCB_NOT_EMPTY__SIZE 0x00000001u +#define CYFLD_SCB_FULL__OFFSET 0x00000003u +#define CYFLD_SCB_FULL__SIZE 0x00000001u +#define CYFLD_SCB_FRAME_ERROR__OFFSET 0x00000008u +#define CYFLD_SCB_FRAME_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_PARITY_ERROR__OFFSET 0x00000009u +#define CYFLD_SCB_PARITY_ERROR__SIZE 0x00000001u +#define CYFLD_SCB_BAUD_DETECT__OFFSET 0x0000000au +#define CYFLD_SCB_BAUD_DETECT__SIZE 0x00000001u +#define CYFLD_SCB_BREAK_DETECT__OFFSET 0x0000000bu +#define CYFLD_SCB_BREAK_DETECT__SIZE 0x00000001u +#define CYREG_SCB0_INTR_RX_SET 0x40240fc4u +#define CYREG_SCB0_INTR_RX_MASK 0x40240fc8u +#define CYREG_SCB0_INTR_RX_MASKED 0x40240fccu +#define CYDEV_SCB1_BASE 0x40250000u +#define CYDEV_SCB1_SIZE 0x00010000u +#define CYREG_SCB1_CTRL 0x40250000u +#define CYREG_SCB1_STATUS 0x40250004u +#define CYREG_SCB1_SPI_CTRL 0x40250020u +#define CYREG_SCB1_SPI_STATUS 0x40250024u +#define CYREG_SCB1_UART_CTRL 0x40250040u +#define CYREG_SCB1_UART_TX_CTRL 0x40250044u +#define CYREG_SCB1_UART_RX_CTRL 0x40250048u +#define CYREG_SCB1_UART_RX_STATUS 0x4025004cu +#define CYREG_SCB1_UART_FLOW_CTRL 0x40250050u +#define CYREG_SCB1_I2C_CTRL 0x40250060u +#define CYREG_SCB1_I2C_STATUS 0x40250064u +#define CYREG_SCB1_I2C_M_CMD 0x40250068u +#define CYREG_SCB1_I2C_S_CMD 0x4025006cu +#define CYREG_SCB1_I2C_CFG 0x40250070u +#define CYREG_SCB1_TX_CTRL 0x40250200u +#define CYREG_SCB1_TX_FIFO_CTRL 0x40250204u +#define CYREG_SCB1_TX_FIFO_STATUS 0x40250208u +#define CYREG_SCB1_TX_FIFO_WR 0x40250240u +#define CYREG_SCB1_RX_CTRL 0x40250300u +#define CYREG_SCB1_RX_FIFO_CTRL 0x40250304u +#define CYREG_SCB1_RX_FIFO_STATUS 0x40250308u +#define CYREG_SCB1_RX_MATCH 0x40250310u +#define CYREG_SCB1_RX_FIFO_RD 0x40250340u +#define CYREG_SCB1_RX_FIFO_RD_SILENT 0x40250344u +#define CYREG_SCB1_EZ_DATA0 0x40250400u +#define CYREG_SCB1_EZ_DATA1 0x40250404u +#define CYREG_SCB1_EZ_DATA2 0x40250408u +#define CYREG_SCB1_EZ_DATA3 0x4025040cu +#define CYREG_SCB1_EZ_DATA4 0x40250410u +#define CYREG_SCB1_EZ_DATA5 0x40250414u +#define CYREG_SCB1_EZ_DATA6 0x40250418u +#define CYREG_SCB1_EZ_DATA7 0x4025041cu +#define CYREG_SCB1_EZ_DATA8 0x40250420u +#define CYREG_SCB1_EZ_DATA9 0x40250424u +#define CYREG_SCB1_EZ_DATA10 0x40250428u +#define CYREG_SCB1_EZ_DATA11 0x4025042cu +#define CYREG_SCB1_EZ_DATA12 0x40250430u +#define CYREG_SCB1_EZ_DATA13 0x40250434u +#define CYREG_SCB1_EZ_DATA14 0x40250438u +#define CYREG_SCB1_EZ_DATA15 0x4025043cu +#define CYREG_SCB1_EZ_DATA16 0x40250440u +#define CYREG_SCB1_EZ_DATA17 0x40250444u +#define CYREG_SCB1_EZ_DATA18 0x40250448u +#define CYREG_SCB1_EZ_DATA19 0x4025044cu +#define CYREG_SCB1_EZ_DATA20 0x40250450u +#define CYREG_SCB1_EZ_DATA21 0x40250454u +#define CYREG_SCB1_EZ_DATA22 0x40250458u +#define CYREG_SCB1_EZ_DATA23 0x4025045cu +#define CYREG_SCB1_EZ_DATA24 0x40250460u +#define CYREG_SCB1_EZ_DATA25 0x40250464u +#define CYREG_SCB1_EZ_DATA26 0x40250468u +#define CYREG_SCB1_EZ_DATA27 0x4025046cu +#define CYREG_SCB1_EZ_DATA28 0x40250470u +#define CYREG_SCB1_EZ_DATA29 0x40250474u +#define CYREG_SCB1_EZ_DATA30 0x40250478u +#define CYREG_SCB1_EZ_DATA31 0x4025047cu +#define CYREG_SCB1_INTR_CAUSE 0x40250e00u +#define CYREG_SCB1_INTR_I2C_EC 0x40250e80u +#define CYREG_SCB1_INTR_I2C_EC_MASK 0x40250e88u +#define CYREG_SCB1_INTR_I2C_EC_MASKED 0x40250e8cu +#define CYREG_SCB1_INTR_SPI_EC 0x40250ec0u +#define CYREG_SCB1_INTR_SPI_EC_MASK 0x40250ec8u +#define CYREG_SCB1_INTR_SPI_EC_MASKED 0x40250eccu +#define CYREG_SCB1_INTR_M 0x40250f00u +#define CYREG_SCB1_INTR_M_SET 0x40250f04u +#define CYREG_SCB1_INTR_M_MASK 0x40250f08u +#define CYREG_SCB1_INTR_M_MASKED 0x40250f0cu +#define CYREG_SCB1_INTR_S 0x40250f40u +#define CYREG_SCB1_INTR_S_SET 0x40250f44u +#define CYREG_SCB1_INTR_S_MASK 0x40250f48u +#define CYREG_SCB1_INTR_S_MASKED 0x40250f4cu +#define CYREG_SCB1_INTR_TX 0x40250f80u +#define CYREG_SCB1_INTR_TX_SET 0x40250f84u +#define CYREG_SCB1_INTR_TX_MASK 0x40250f88u +#define CYREG_SCB1_INTR_TX_MASKED 0x40250f8cu +#define CYREG_SCB1_INTR_RX 0x40250fc0u +#define CYREG_SCB1_INTR_RX_SET 0x40250fc4u +#define CYREG_SCB1_INTR_RX_MASK 0x40250fc8u +#define CYREG_SCB1_INTR_RX_MASKED 0x40250fccu +#define CYDEV_SCB2_BASE 0x40260000u +#define CYDEV_SCB2_SIZE 0x00010000u +#define CYREG_SCB2_CTRL 0x40260000u +#define CYREG_SCB2_STATUS 0x40260004u +#define CYREG_SCB2_SPI_CTRL 0x40260020u +#define CYREG_SCB2_SPI_STATUS 0x40260024u +#define CYREG_SCB2_UART_CTRL 0x40260040u +#define CYREG_SCB2_UART_TX_CTRL 0x40260044u +#define CYREG_SCB2_UART_RX_CTRL 0x40260048u +#define CYREG_SCB2_UART_RX_STATUS 0x4026004cu +#define CYREG_SCB2_UART_FLOW_CTRL 0x40260050u +#define CYREG_SCB2_I2C_CTRL 0x40260060u +#define CYREG_SCB2_I2C_STATUS 0x40260064u +#define CYREG_SCB2_I2C_M_CMD 0x40260068u +#define CYREG_SCB2_I2C_S_CMD 0x4026006cu +#define CYREG_SCB2_I2C_CFG 0x40260070u +#define CYREG_SCB2_TX_CTRL 0x40260200u +#define CYREG_SCB2_TX_FIFO_CTRL 0x40260204u +#define CYREG_SCB2_TX_FIFO_STATUS 0x40260208u +#define CYREG_SCB2_TX_FIFO_WR 0x40260240u +#define CYREG_SCB2_RX_CTRL 0x40260300u +#define CYREG_SCB2_RX_FIFO_CTRL 0x40260304u +#define CYREG_SCB2_RX_FIFO_STATUS 0x40260308u +#define CYREG_SCB2_RX_MATCH 0x40260310u +#define CYREG_SCB2_RX_FIFO_RD 0x40260340u +#define CYREG_SCB2_RX_FIFO_RD_SILENT 0x40260344u +#define CYREG_SCB2_EZ_DATA0 0x40260400u +#define CYREG_SCB2_EZ_DATA1 0x40260404u +#define CYREG_SCB2_EZ_DATA2 0x40260408u +#define CYREG_SCB2_EZ_DATA3 0x4026040cu +#define CYREG_SCB2_EZ_DATA4 0x40260410u +#define CYREG_SCB2_EZ_DATA5 0x40260414u +#define CYREG_SCB2_EZ_DATA6 0x40260418u +#define CYREG_SCB2_EZ_DATA7 0x4026041cu +#define CYREG_SCB2_EZ_DATA8 0x40260420u +#define CYREG_SCB2_EZ_DATA9 0x40260424u +#define CYREG_SCB2_EZ_DATA10 0x40260428u +#define CYREG_SCB2_EZ_DATA11 0x4026042cu +#define CYREG_SCB2_EZ_DATA12 0x40260430u +#define CYREG_SCB2_EZ_DATA13 0x40260434u +#define CYREG_SCB2_EZ_DATA14 0x40260438u +#define CYREG_SCB2_EZ_DATA15 0x4026043cu +#define CYREG_SCB2_EZ_DATA16 0x40260440u +#define CYREG_SCB2_EZ_DATA17 0x40260444u +#define CYREG_SCB2_EZ_DATA18 0x40260448u +#define CYREG_SCB2_EZ_DATA19 0x4026044cu +#define CYREG_SCB2_EZ_DATA20 0x40260450u +#define CYREG_SCB2_EZ_DATA21 0x40260454u +#define CYREG_SCB2_EZ_DATA22 0x40260458u +#define CYREG_SCB2_EZ_DATA23 0x4026045cu +#define CYREG_SCB2_EZ_DATA24 0x40260460u +#define CYREG_SCB2_EZ_DATA25 0x40260464u +#define CYREG_SCB2_EZ_DATA26 0x40260468u +#define CYREG_SCB2_EZ_DATA27 0x4026046cu +#define CYREG_SCB2_EZ_DATA28 0x40260470u +#define CYREG_SCB2_EZ_DATA29 0x40260474u +#define CYREG_SCB2_EZ_DATA30 0x40260478u +#define CYREG_SCB2_EZ_DATA31 0x4026047cu +#define CYREG_SCB2_INTR_CAUSE 0x40260e00u +#define CYREG_SCB2_INTR_I2C_EC 0x40260e80u +#define CYREG_SCB2_INTR_I2C_EC_MASK 0x40260e88u +#define CYREG_SCB2_INTR_I2C_EC_MASKED 0x40260e8cu +#define CYREG_SCB2_INTR_SPI_EC 0x40260ec0u +#define CYREG_SCB2_INTR_SPI_EC_MASK 0x40260ec8u +#define CYREG_SCB2_INTR_SPI_EC_MASKED 0x40260eccu +#define CYREG_SCB2_INTR_M 0x40260f00u +#define CYREG_SCB2_INTR_M_SET 0x40260f04u +#define CYREG_SCB2_INTR_M_MASK 0x40260f08u +#define CYREG_SCB2_INTR_M_MASKED 0x40260f0cu +#define CYREG_SCB2_INTR_S 0x40260f40u +#define CYREG_SCB2_INTR_S_SET 0x40260f44u +#define CYREG_SCB2_INTR_S_MASK 0x40260f48u +#define CYREG_SCB2_INTR_S_MASKED 0x40260f4cu +#define CYREG_SCB2_INTR_TX 0x40260f80u +#define CYREG_SCB2_INTR_TX_SET 0x40260f84u +#define CYREG_SCB2_INTR_TX_MASK 0x40260f88u +#define CYREG_SCB2_INTR_TX_MASKED 0x40260f8cu +#define CYREG_SCB2_INTR_RX 0x40260fc0u +#define CYREG_SCB2_INTR_RX_SET 0x40260fc4u +#define CYREG_SCB2_INTR_RX_MASK 0x40260fc8u +#define CYREG_SCB2_INTR_RX_MASKED 0x40260fccu +#define CYDEV_SCB3_BASE 0x40270000u +#define CYDEV_SCB3_SIZE 0x00010000u +#define CYREG_SCB3_CTRL 0x40270000u +#define CYREG_SCB3_STATUS 0x40270004u +#define CYREG_SCB3_SPI_CTRL 0x40270020u +#define CYREG_SCB3_SPI_STATUS 0x40270024u +#define CYREG_SCB3_UART_CTRL 0x40270040u +#define CYREG_SCB3_UART_TX_CTRL 0x40270044u +#define CYREG_SCB3_UART_RX_CTRL 0x40270048u +#define CYREG_SCB3_UART_RX_STATUS 0x4027004cu +#define CYREG_SCB3_UART_FLOW_CTRL 0x40270050u +#define CYREG_SCB3_I2C_CTRL 0x40270060u +#define CYREG_SCB3_I2C_STATUS 0x40270064u +#define CYREG_SCB3_I2C_M_CMD 0x40270068u +#define CYREG_SCB3_I2C_S_CMD 0x4027006cu +#define CYREG_SCB3_I2C_CFG 0x40270070u +#define CYREG_SCB3_TX_CTRL 0x40270200u +#define CYREG_SCB3_TX_FIFO_CTRL 0x40270204u +#define CYREG_SCB3_TX_FIFO_STATUS 0x40270208u +#define CYREG_SCB3_TX_FIFO_WR 0x40270240u +#define CYREG_SCB3_RX_CTRL 0x40270300u +#define CYREG_SCB3_RX_FIFO_CTRL 0x40270304u +#define CYREG_SCB3_RX_FIFO_STATUS 0x40270308u +#define CYREG_SCB3_RX_MATCH 0x40270310u +#define CYREG_SCB3_RX_FIFO_RD 0x40270340u +#define CYREG_SCB3_RX_FIFO_RD_SILENT 0x40270344u +#define CYREG_SCB3_EZ_DATA0 0x40270400u +#define CYREG_SCB3_EZ_DATA1 0x40270404u +#define CYREG_SCB3_EZ_DATA2 0x40270408u +#define CYREG_SCB3_EZ_DATA3 0x4027040cu +#define CYREG_SCB3_EZ_DATA4 0x40270410u +#define CYREG_SCB3_EZ_DATA5 0x40270414u +#define CYREG_SCB3_EZ_DATA6 0x40270418u +#define CYREG_SCB3_EZ_DATA7 0x4027041cu +#define CYREG_SCB3_EZ_DATA8 0x40270420u +#define CYREG_SCB3_EZ_DATA9 0x40270424u +#define CYREG_SCB3_EZ_DATA10 0x40270428u +#define CYREG_SCB3_EZ_DATA11 0x4027042cu +#define CYREG_SCB3_EZ_DATA12 0x40270430u +#define CYREG_SCB3_EZ_DATA13 0x40270434u +#define CYREG_SCB3_EZ_DATA14 0x40270438u +#define CYREG_SCB3_EZ_DATA15 0x4027043cu +#define CYREG_SCB3_EZ_DATA16 0x40270440u +#define CYREG_SCB3_EZ_DATA17 0x40270444u +#define CYREG_SCB3_EZ_DATA18 0x40270448u +#define CYREG_SCB3_EZ_DATA19 0x4027044cu +#define CYREG_SCB3_EZ_DATA20 0x40270450u +#define CYREG_SCB3_EZ_DATA21 0x40270454u +#define CYREG_SCB3_EZ_DATA22 0x40270458u +#define CYREG_SCB3_EZ_DATA23 0x4027045cu +#define CYREG_SCB3_EZ_DATA24 0x40270460u +#define CYREG_SCB3_EZ_DATA25 0x40270464u +#define CYREG_SCB3_EZ_DATA26 0x40270468u +#define CYREG_SCB3_EZ_DATA27 0x4027046cu +#define CYREG_SCB3_EZ_DATA28 0x40270470u +#define CYREG_SCB3_EZ_DATA29 0x40270474u +#define CYREG_SCB3_EZ_DATA30 0x40270478u +#define CYREG_SCB3_EZ_DATA31 0x4027047cu +#define CYREG_SCB3_INTR_CAUSE 0x40270e00u +#define CYREG_SCB3_INTR_I2C_EC 0x40270e80u +#define CYREG_SCB3_INTR_I2C_EC_MASK 0x40270e88u +#define CYREG_SCB3_INTR_I2C_EC_MASKED 0x40270e8cu +#define CYREG_SCB3_INTR_SPI_EC 0x40270ec0u +#define CYREG_SCB3_INTR_SPI_EC_MASK 0x40270ec8u +#define CYREG_SCB3_INTR_SPI_EC_MASKED 0x40270eccu +#define CYREG_SCB3_INTR_M 0x40270f00u +#define CYREG_SCB3_INTR_M_SET 0x40270f04u +#define CYREG_SCB3_INTR_M_MASK 0x40270f08u +#define CYREG_SCB3_INTR_M_MASKED 0x40270f0cu +#define CYREG_SCB3_INTR_S 0x40270f40u +#define CYREG_SCB3_INTR_S_SET 0x40270f44u +#define CYREG_SCB3_INTR_S_MASK 0x40270f48u +#define CYREG_SCB3_INTR_S_MASKED 0x40270f4cu +#define CYREG_SCB3_INTR_TX 0x40270f80u +#define CYREG_SCB3_INTR_TX_SET 0x40270f84u +#define CYREG_SCB3_INTR_TX_MASK 0x40270f88u +#define CYREG_SCB3_INTR_TX_MASKED 0x40270f8cu +#define CYREG_SCB3_INTR_RX 0x40270fc0u +#define CYREG_SCB3_INTR_RX_SET 0x40270fc4u +#define CYREG_SCB3_INTR_RX_MASK 0x40270fc8u +#define CYREG_SCB3_INTR_RX_MASKED 0x40270fccu +#define CYDEV_SCB4_BASE 0x40280000u +#define CYDEV_SCB4_SIZE 0x00010000u +#define CYREG_SCB4_CTRL 0x40280000u +#define CYREG_SCB4_STATUS 0x40280004u +#define CYREG_SCB4_SPI_CTRL 0x40280020u +#define CYREG_SCB4_SPI_STATUS 0x40280024u +#define CYREG_SCB4_UART_CTRL 0x40280040u +#define CYREG_SCB4_UART_TX_CTRL 0x40280044u +#define CYREG_SCB4_UART_RX_CTRL 0x40280048u +#define CYREG_SCB4_UART_RX_STATUS 0x4028004cu +#define CYREG_SCB4_UART_FLOW_CTRL 0x40280050u +#define CYREG_SCB4_I2C_CTRL 0x40280060u +#define CYREG_SCB4_I2C_STATUS 0x40280064u +#define CYREG_SCB4_I2C_M_CMD 0x40280068u +#define CYREG_SCB4_I2C_S_CMD 0x4028006cu +#define CYREG_SCB4_I2C_CFG 0x40280070u +#define CYREG_SCB4_TX_CTRL 0x40280200u +#define CYREG_SCB4_TX_FIFO_CTRL 0x40280204u +#define CYREG_SCB4_TX_FIFO_STATUS 0x40280208u +#define CYREG_SCB4_TX_FIFO_WR 0x40280240u +#define CYREG_SCB4_RX_CTRL 0x40280300u +#define CYREG_SCB4_RX_FIFO_CTRL 0x40280304u +#define CYREG_SCB4_RX_FIFO_STATUS 0x40280308u +#define CYREG_SCB4_RX_MATCH 0x40280310u +#define CYREG_SCB4_RX_FIFO_RD 0x40280340u +#define CYREG_SCB4_RX_FIFO_RD_SILENT 0x40280344u +#define CYREG_SCB4_EZ_DATA0 0x40280400u +#define CYREG_SCB4_EZ_DATA1 0x40280404u +#define CYREG_SCB4_EZ_DATA2 0x40280408u +#define CYREG_SCB4_EZ_DATA3 0x4028040cu +#define CYREG_SCB4_EZ_DATA4 0x40280410u +#define CYREG_SCB4_EZ_DATA5 0x40280414u +#define CYREG_SCB4_EZ_DATA6 0x40280418u +#define CYREG_SCB4_EZ_DATA7 0x4028041cu +#define CYREG_SCB4_EZ_DATA8 0x40280420u +#define CYREG_SCB4_EZ_DATA9 0x40280424u +#define CYREG_SCB4_EZ_DATA10 0x40280428u +#define CYREG_SCB4_EZ_DATA11 0x4028042cu +#define CYREG_SCB4_EZ_DATA12 0x40280430u +#define CYREG_SCB4_EZ_DATA13 0x40280434u +#define CYREG_SCB4_EZ_DATA14 0x40280438u +#define CYREG_SCB4_EZ_DATA15 0x4028043cu +#define CYREG_SCB4_EZ_DATA16 0x40280440u +#define CYREG_SCB4_EZ_DATA17 0x40280444u +#define CYREG_SCB4_EZ_DATA18 0x40280448u +#define CYREG_SCB4_EZ_DATA19 0x4028044cu +#define CYREG_SCB4_EZ_DATA20 0x40280450u +#define CYREG_SCB4_EZ_DATA21 0x40280454u +#define CYREG_SCB4_EZ_DATA22 0x40280458u +#define CYREG_SCB4_EZ_DATA23 0x4028045cu +#define CYREG_SCB4_EZ_DATA24 0x40280460u +#define CYREG_SCB4_EZ_DATA25 0x40280464u +#define CYREG_SCB4_EZ_DATA26 0x40280468u +#define CYREG_SCB4_EZ_DATA27 0x4028046cu +#define CYREG_SCB4_EZ_DATA28 0x40280470u +#define CYREG_SCB4_EZ_DATA29 0x40280474u +#define CYREG_SCB4_EZ_DATA30 0x40280478u +#define CYREG_SCB4_EZ_DATA31 0x4028047cu +#define CYREG_SCB4_INTR_CAUSE 0x40280e00u +#define CYREG_SCB4_INTR_I2C_EC 0x40280e80u +#define CYREG_SCB4_INTR_I2C_EC_MASK 0x40280e88u +#define CYREG_SCB4_INTR_I2C_EC_MASKED 0x40280e8cu +#define CYREG_SCB4_INTR_SPI_EC 0x40280ec0u +#define CYREG_SCB4_INTR_SPI_EC_MASK 0x40280ec8u +#define CYREG_SCB4_INTR_SPI_EC_MASKED 0x40280eccu +#define CYREG_SCB4_INTR_M 0x40280f00u +#define CYREG_SCB4_INTR_M_SET 0x40280f04u +#define CYREG_SCB4_INTR_M_MASK 0x40280f08u +#define CYREG_SCB4_INTR_M_MASKED 0x40280f0cu +#define CYREG_SCB4_INTR_S 0x40280f40u +#define CYREG_SCB4_INTR_S_SET 0x40280f44u +#define CYREG_SCB4_INTR_S_MASK 0x40280f48u +#define CYREG_SCB4_INTR_S_MASKED 0x40280f4cu +#define CYREG_SCB4_INTR_TX 0x40280f80u +#define CYREG_SCB4_INTR_TX_SET 0x40280f84u +#define CYREG_SCB4_INTR_TX_MASK 0x40280f88u +#define CYREG_SCB4_INTR_TX_MASKED 0x40280f8cu +#define CYREG_SCB4_INTR_RX 0x40280fc0u +#define CYREG_SCB4_INTR_RX_SET 0x40280fc4u +#define CYREG_SCB4_INTR_RX_MASK 0x40280fc8u +#define CYREG_SCB4_INTR_RX_MASKED 0x40280fccu +#define CYDEV_CSD_BASE 0x40290000u +#define CYDEV_CSD_SIZE 0x00001000u +#define CYREG_CSD_CONFIG 0x40290000u +#define CYFLD_CSD_LOW_VDDA__OFFSET 0x00000003u +#define CYFLD_CSD_LOW_VDDA__SIZE 0x00000001u +#define CYFLD_CSD_FILTER_DELAY__OFFSET 0x00000004u +#define CYFLD_CSD_FILTER_DELAY__SIZE 0x00000003u +#define CYFLD_CSD_SHIELD_DELAY__OFFSET 0x00000008u +#define CYFLD_CSD_SHIELD_DELAY__SIZE 0x00000002u +#define CYVAL_CSD_SHIELD_DELAY_OFF 0x00000000u +#define CYVAL_CSD_SHIELD_DELAY_D5NS 0x00000001u +#define CYVAL_CSD_SHIELD_DELAY_D10NS 0x00000002u +#define CYVAL_CSD_SHIELD_DELAY_D20NS 0x00000003u +#define CYFLD_CSD_SENSE_EN__OFFSET 0x0000000cu +#define CYFLD_CSD_SENSE_EN__SIZE 0x00000001u +#define CYFLD_CSD_CHARGE_MODE__OFFSET 0x0000000eu +#define CYFLD_CSD_CHARGE_MODE__SIZE 0x00000001u +#define CYVAL_CSD_CHARGE_MODE_CHARGE_OFF 0x00000000u +#define CYVAL_CSD_CHARGE_MODE_CHARGE_IO 0x00000001u +#define CYFLD_CSD_FULL_WAVE__OFFSET 0x00000011u +#define CYFLD_CSD_FULL_WAVE__SIZE 0x00000001u +#define CYVAL_CSD_FULL_WAVE_HALFWAVE 0x00000000u +#define CYVAL_CSD_FULL_WAVE_FULLWAVE 0x00000001u +#define CYFLD_CSD_MUTUAL_CAP__OFFSET 0x00000012u +#define CYFLD_CSD_MUTUAL_CAP__SIZE 0x00000001u +#define CYVAL_CSD_MUTUAL_CAP_SELFCAP 0x00000000u +#define CYVAL_CSD_MUTUAL_CAP_MUTUALCAP 0x00000001u +#define CYFLD_CSD_CSX_DUAL_CNT__OFFSET 0x00000013u +#define CYFLD_CSD_CSX_DUAL_CNT__SIZE 0x00000001u +#define CYVAL_CSD_CSX_DUAL_CNT_ONE 0x00000000u +#define CYVAL_CSD_CSX_DUAL_CNT_TWO 0x00000001u +#define CYFLD_CSD_DSI_COUNT_SEL__OFFSET 0x00000018u +#define CYFLD_CSD_DSI_COUNT_SEL__SIZE 0x00000001u +#define CYVAL_CSD_DSI_COUNT_SEL_CSD_RESULT 0x00000000u +#define CYVAL_CSD_DSI_COUNT_SEL_ADC_RESULT 0x00000001u +#define CYFLD_CSD_DSI_SAMPLE_EN__OFFSET 0x00000019u +#define CYFLD_CSD_DSI_SAMPLE_EN__SIZE 0x00000001u +#define CYFLD_CSD_SAMPLE_SYNC__OFFSET 0x0000001au +#define CYFLD_CSD_SAMPLE_SYNC__SIZE 0x00000001u +#define CYFLD_CSD_DSI_SENSE_EN__OFFSET 0x0000001bu +#define CYFLD_CSD_DSI_SENSE_EN__SIZE 0x00000001u +#define CYFLD_CSD_LP_MODE__OFFSET 0x0000001eu +#define CYFLD_CSD_LP_MODE__SIZE 0x00000001u +#define CYFLD_CSD_ENABLE__OFFSET 0x0000001fu +#define CYFLD_CSD_ENABLE__SIZE 0x00000001u +#define CYREG_CSD_SPARE 0x40290004u +#define CYFLD_CSD_SPARE__OFFSET 0x00000000u +#define CYFLD_CSD_SPARE__SIZE 0x00000004u +#define CYREG_CSD_STATUS 0x40290080u +#define CYFLD_CSD_CSD_CHARGE__OFFSET 0x00000000u +#define CYFLD_CSD_CSD_CHARGE__SIZE 0x00000001u +#define CYFLD_CSD_CSD_SENSE__OFFSET 0x00000001u +#define CYFLD_CSD_CSD_SENSE__SIZE 0x00000001u +#define CYFLD_CSD_HSCMP_OUT__OFFSET 0x00000002u +#define CYFLD_CSD_HSCMP_OUT__SIZE 0x00000001u +#define CYVAL_CSD_HSCMP_OUT_C_LT_VREF 0x00000000u +#define CYVAL_CSD_HSCMP_OUT_C_GT_VREF 0x00000001u +#define CYFLD_CSD_CSDCMP_OUT__OFFSET 0x00000003u +#define CYFLD_CSD_CSDCMP_OUT__SIZE 0x00000001u +#define CYREG_CSD_STAT_SEQ 0x40290084u +#define CYFLD_CSD_SEQ_STATE__OFFSET 0x00000000u +#define CYFLD_CSD_SEQ_STATE__SIZE 0x00000003u +#define CYFLD_CSD_ADC_STATE__OFFSET 0x00000010u +#define CYFLD_CSD_ADC_STATE__SIZE 0x00000003u +#define CYREG_CSD_STAT_CNTS 0x40290088u +#define CYFLD_CSD_NUM_CONV__OFFSET 0x00000000u +#define CYFLD_CSD_NUM_CONV__SIZE 0x00000010u +#define CYREG_CSD_STAT_HCNT 0x4029008cu +#define CYFLD_CSD_CNT__OFFSET 0x00000000u +#define CYFLD_CSD_CNT__SIZE 0x00000010u +#define CYREG_CSD_RESULT_VAL1 0x402900d0u +#define CYFLD_CSD_VALUE__OFFSET 0x00000000u +#define CYFLD_CSD_VALUE__SIZE 0x00000010u +#define CYFLD_CSD_BAD_CONVS__OFFSET 0x00000010u +#define CYFLD_CSD_BAD_CONVS__SIZE 0x00000008u +#define CYREG_CSD_RESULT_VAL2 0x402900d4u +#define CYREG_CSD_ADC_RES 0x402900e0u +#define CYFLD_CSD_VIN_CNT__OFFSET 0x00000000u +#define CYFLD_CSD_VIN_CNT__SIZE 0x00000010u +#define CYFLD_CSD_HSCMP_POL__OFFSET 0x00000010u +#define CYFLD_CSD_HSCMP_POL__SIZE 0x00000001u +#define CYFLD_CSD_ADC_OVERFLOW__OFFSET 0x0000001eu +#define CYFLD_CSD_ADC_OVERFLOW__SIZE 0x00000001u +#define CYFLD_CSD_ADC_ABORT__OFFSET 0x0000001fu +#define CYFLD_CSD_ADC_ABORT__SIZE 0x00000001u +#define CYREG_CSD_INTR 0x402900f0u +#define CYFLD_CSD_SAMPLE__OFFSET 0x00000001u +#define CYFLD_CSD_SAMPLE__SIZE 0x00000001u +#define CYFLD_CSD_INIT__OFFSET 0x00000002u +#define CYFLD_CSD_INIT__SIZE 0x00000001u +#define CYFLD_CSD_ADC_RES__OFFSET 0x00000008u +#define CYFLD_CSD_ADC_RES__SIZE 0x00000001u +#define CYREG_CSD_INTR_SET 0x402900f4u +#define CYREG_CSD_INTR_MASK 0x402900f8u +#define CYREG_CSD_INTR_MASKED 0x402900fcu +#define CYREG_CSD_HSCMP 0x40290180u +#define CYFLD_CSD_HSCMP_EN__OFFSET 0x00000000u +#define CYFLD_CSD_HSCMP_EN__SIZE 0x00000001u +#define CYVAL_CSD_HSCMP_EN_OFF 0x00000000u +#define CYVAL_CSD_HSCMP_EN_ON 0x00000001u +#define CYFLD_CSD_HSCMP_INVERT__OFFSET 0x00000004u +#define CYFLD_CSD_HSCMP_INVERT__SIZE 0x00000001u +#define CYFLD_CSD_AZ_EN__OFFSET 0x0000001fu +#define CYFLD_CSD_AZ_EN__SIZE 0x00000001u +#define CYREG_CSD_AMBUF 0x40290184u +#define CYFLD_CSD_PWR_MODE__OFFSET 0x00000000u +#define CYFLD_CSD_PWR_MODE__SIZE 0x00000002u +#define CYVAL_CSD_PWR_MODE_OFF 0x00000000u +#define CYVAL_CSD_PWR_MODE_NORM 0x00000001u +#define CYVAL_CSD_PWR_MODE_HI 0x00000002u +#define CYREG_CSD_REFGEN 0x40290188u +#define CYFLD_CSD_REFGEN_EN__OFFSET 0x00000000u +#define CYFLD_CSD_REFGEN_EN__SIZE 0x00000001u +#define CYVAL_CSD_REFGEN_EN_OFF 0x00000000u +#define CYVAL_CSD_REFGEN_EN_ON 0x00000001u +#define CYFLD_CSD_BYPASS__OFFSET 0x00000004u +#define CYFLD_CSD_BYPASS__SIZE 0x00000001u +#define CYFLD_CSD_VDDA_EN__OFFSET 0x00000005u +#define CYFLD_CSD_VDDA_EN__SIZE 0x00000001u +#define CYFLD_CSD_RES_EN__OFFSET 0x00000006u +#define CYFLD_CSD_RES_EN__SIZE 0x00000001u +#define CYFLD_CSD_GAIN__OFFSET 0x00000008u +#define CYFLD_CSD_GAIN__SIZE 0x00000005u +#define CYFLD_CSD_VREFLO_SEL__OFFSET 0x00000010u +#define CYFLD_CSD_VREFLO_SEL__SIZE 0x00000005u +#define CYFLD_CSD_VREFLO_INT__OFFSET 0x00000017u +#define CYFLD_CSD_VREFLO_INT__SIZE 0x00000001u +#define CYREG_CSD_CSDCMP 0x4029018cu +#define CYFLD_CSD_CSDCMP_EN__OFFSET 0x00000000u +#define CYFLD_CSD_CSDCMP_EN__SIZE 0x00000001u +#define CYVAL_CSD_CSDCMP_EN_OFF 0x00000000u +#define CYVAL_CSD_CSDCMP_EN_ON 0x00000001u +#define CYFLD_CSD_POLARITY_SEL__OFFSET 0x00000004u +#define CYFLD_CSD_POLARITY_SEL__SIZE 0x00000002u +#define CYVAL_CSD_POLARITY_SEL_IDACA_POL 0x00000000u +#define CYVAL_CSD_POLARITY_SEL_IDACB_POL 0x00000001u +#define CYVAL_CSD_POLARITY_SEL_DUAL_POL 0x00000002u +#define CYFLD_CSD_CMP_PHASE__OFFSET 0x00000008u +#define CYFLD_CSD_CMP_PHASE__SIZE 0x00000002u +#define CYVAL_CSD_CMP_PHASE_FULL 0x00000000u +#define CYVAL_CSD_CMP_PHASE_PHI1 0x00000001u +#define CYVAL_CSD_CMP_PHASE_PHI2 0x00000002u +#define CYVAL_CSD_CMP_PHASE_PHI1_2 0x00000003u +#define CYFLD_CSD_CMP_MODE__OFFSET 0x0000001cu +#define CYFLD_CSD_CMP_MODE__SIZE 0x00000001u +#define CYVAL_CSD_CMP_MODE_CSD 0x00000000u +#define CYVAL_CSD_CMP_MODE_GP 0x00000001u +#define CYFLD_CSD_FEEDBACK_MODE__OFFSET 0x0000001du +#define CYFLD_CSD_FEEDBACK_MODE__SIZE 0x00000001u +#define CYVAL_CSD_FEEDBACK_MODE_FLOP 0x00000000u +#define CYVAL_CSD_FEEDBACK_MODE_COMP 0x00000001u +#define CYREG_CSD_IDACA 0x402901c0u +#define CYFLD_CSD_VAL__OFFSET 0x00000000u +#define CYFLD_CSD_VAL__SIZE 0x00000007u +#define CYFLD_CSD_POL_DYN__OFFSET 0x00000007u +#define CYFLD_CSD_POL_DYN__SIZE 0x00000001u +#define CYVAL_CSD_POL_DYN_STATIC 0x00000000u +#define CYVAL_CSD_POL_DYN_DYNAMIC 0x00000001u +#define CYFLD_CSD_POLARITY__OFFSET 0x00000008u +#define CYFLD_CSD_POLARITY__SIZE 0x00000002u +#define CYVAL_CSD_POLARITY_VSSA_SRC 0x00000000u +#define CYVAL_CSD_POLARITY_VDDA_SNK 0x00000001u +#define CYVAL_CSD_POLARITY_SENSE 0x00000002u +#define CYVAL_CSD_POLARITY_SENSE_INV 0x00000003u +#define CYFLD_CSD_BAL_MODE__OFFSET 0x0000000au +#define CYFLD_CSD_BAL_MODE__SIZE 0x00000002u +#define CYVAL_CSD_BAL_MODE_FULL 0x00000000u +#define CYVAL_CSD_BAL_MODE_PHI1 0x00000001u +#define CYVAL_CSD_BAL_MODE_PHI2 0x00000002u +#define CYVAL_CSD_BAL_MODE_PHI1_2 0x00000003u +#define CYFLD_CSD_LEG1_MODE__OFFSET 0x00000010u +#define CYFLD_CSD_LEG1_MODE__SIZE 0x00000002u +#define CYVAL_CSD_LEG1_MODE_GP_STATIC 0x00000000u +#define CYVAL_CSD_LEG1_MODE_GP 0x00000001u +#define CYVAL_CSD_LEG1_MODE_CSD_STATIC 0x00000002u +#define CYVAL_CSD_LEG1_MODE_CSD 0x00000003u +#define CYFLD_CSD_LEG2_MODE__OFFSET 0x00000012u +#define CYFLD_CSD_LEG2_MODE__SIZE 0x00000002u +#define CYVAL_CSD_LEG2_MODE_GP_STATIC 0x00000000u +#define CYVAL_CSD_LEG2_MODE_GP 0x00000001u +#define CYVAL_CSD_LEG2_MODE_CSD_STATIC 0x00000002u +#define CYVAL_CSD_LEG2_MODE_CSD 0x00000003u +#define CYFLD_CSD_DSI_CTRL_EN__OFFSET 0x00000015u +#define CYFLD_CSD_DSI_CTRL_EN__SIZE 0x00000001u +#define CYFLD_CSD_RANGE__OFFSET 0x00000016u +#define CYFLD_CSD_RANGE__SIZE 0x00000002u +#define CYVAL_CSD_RANGE_IDAC_LO 0x00000000u +#define CYVAL_CSD_RANGE_IDAC_MED 0x00000001u +#define CYVAL_CSD_RANGE_IDAC_HI 0x00000002u +#define CYVAL_CSD_RANGE_IDAC_MED2 0x00000003u +#define CYFLD_CSD_LEG1_EN__OFFSET 0x00000018u +#define CYFLD_CSD_LEG1_EN__SIZE 0x00000001u +#define CYFLD_CSD_LEG2_EN__OFFSET 0x00000019u +#define CYFLD_CSD_LEG2_EN__SIZE 0x00000001u +#define CYREG_CSD_IDACB 0x402901c4u +#define CYFLD_CSD_LEG3_EN__OFFSET 0x0000001au +#define CYFLD_CSD_LEG3_EN__SIZE 0x00000001u +#define CYREG_CSD_SW_RES 0x402901f0u +#define CYFLD_CSD_RES_HCAV__OFFSET 0x00000000u +#define CYFLD_CSD_RES_HCAV__SIZE 0x00000002u +#define CYVAL_CSD_RES_HCAV_LOW 0x00000000u +#define CYVAL_CSD_RES_HCAV_MED 0x00000001u +#define CYVAL_CSD_RES_HCAV_HIGH 0x00000002u +#define CYVAL_CSD_RES_HCAV_LOWEMI 0x00000003u +#define CYFLD_CSD_RES_HCAG__OFFSET 0x00000002u +#define CYFLD_CSD_RES_HCAG__SIZE 0x00000002u +#define CYFLD_CSD_RES_HCBV__OFFSET 0x00000004u +#define CYFLD_CSD_RES_HCBV__SIZE 0x00000002u +#define CYFLD_CSD_RES_HCBG__OFFSET 0x00000006u +#define CYFLD_CSD_RES_HCBG__SIZE 0x00000002u +#define CYFLD_CSD_RES_F1PM__OFFSET 0x00000010u +#define CYFLD_CSD_RES_F1PM__SIZE 0x00000002u +#define CYVAL_CSD_RES_F1PM_LOW 0x00000000u +#define CYVAL_CSD_RES_F1PM_MED 0x00000001u +#define CYVAL_CSD_RES_F1PM_HIGH 0x00000002u +#define CYVAL_CSD_RES_F1PM_RESERVED 0x00000003u +#define CYFLD_CSD_RES_F2PT__OFFSET 0x00000012u +#define CYFLD_CSD_RES_F2PT__SIZE 0x00000002u +#define CYREG_CSD_SENSE_PERIOD 0x40290200u +#define CYFLD_CSD_SENSE_DIV__OFFSET 0x00000000u +#define CYFLD_CSD_SENSE_DIV__SIZE 0x0000000cu +#define CYFLD_CSD_LFSR_SIZE__OFFSET 0x00000010u +#define CYFLD_CSD_LFSR_SIZE__SIZE 0x00000003u +#define CYVAL_CSD_LFSR_SIZE_OFF 0x00000000u +#define CYVAL_CSD_LFSR_SIZE_6B 0x00000001u +#define CYVAL_CSD_LFSR_SIZE_7B 0x00000002u +#define CYVAL_CSD_LFSR_SIZE_9B 0x00000003u +#define CYVAL_CSD_LFSR_SIZE_10B 0x00000004u +#define CYVAL_CSD_LFSR_SIZE_8B 0x00000005u +#define CYVAL_CSD_LFSR_SIZE_12B 0x00000006u +#define CYFLD_CSD_LFSR_SCALE__OFFSET 0x00000014u +#define CYFLD_CSD_LFSR_SCALE__SIZE 0x00000004u +#define CYFLD_CSD_LFSR_CLEAR__OFFSET 0x00000018u +#define CYFLD_CSD_LFSR_CLEAR__SIZE 0x00000001u +#define CYFLD_CSD_SEL_LFSR_MSB__OFFSET 0x00000019u +#define CYFLD_CSD_SEL_LFSR_MSB__SIZE 0x00000001u +#define CYFLD_CSD_LFSR_BITS__OFFSET 0x0000001au +#define CYFLD_CSD_LFSR_BITS__SIZE 0x00000002u +#define CYVAL_CSD_LFSR_BITS_2B 0x00000000u +#define CYVAL_CSD_LFSR_BITS_3B 0x00000001u +#define CYVAL_CSD_LFSR_BITS_4B 0x00000002u +#define CYVAL_CSD_LFSR_BITS_5B 0x00000003u +#define CYREG_CSD_SENSE_DUTY 0x40290204u +#define CYFLD_CSD_SENSE_WIDTH__OFFSET 0x00000000u +#define CYFLD_CSD_SENSE_WIDTH__SIZE 0x0000000cu +#define CYFLD_CSD_SENSE_POL__OFFSET 0x00000010u +#define CYFLD_CSD_SENSE_POL__SIZE 0x00000001u +#define CYFLD_CSD_OVERLAP_PHI1__OFFSET 0x00000012u +#define CYFLD_CSD_OVERLAP_PHI1__SIZE 0x00000001u +#define CYFLD_CSD_OVERLAP_PHI2__OFFSET 0x00000013u +#define CYFLD_CSD_OVERLAP_PHI2__SIZE 0x00000001u +#define CYREG_CSD_SW_HS_P_SEL 0x40290280u +#define CYFLD_CSD_SW_HMPM__OFFSET 0x00000000u +#define CYFLD_CSD_SW_HMPM__SIZE 0x00000001u +#define CYFLD_CSD_SW_HMPT__OFFSET 0x00000004u +#define CYFLD_CSD_SW_HMPT__SIZE 0x00000001u +#define CYFLD_CSD_SW_HMPS__OFFSET 0x00000008u +#define CYFLD_CSD_SW_HMPS__SIZE 0x00000001u +#define CYFLD_CSD_SW_HMMA__OFFSET 0x0000000cu +#define CYFLD_CSD_SW_HMMA__SIZE 0x00000001u +#define CYFLD_CSD_SW_HMMB__OFFSET 0x00000010u +#define CYFLD_CSD_SW_HMMB__SIZE 0x00000001u +#define CYFLD_CSD_SW_HMCA__OFFSET 0x00000014u +#define CYFLD_CSD_SW_HMCA__SIZE 0x00000001u +#define CYFLD_CSD_SW_HMCB__OFFSET 0x00000018u +#define CYFLD_CSD_SW_HMCB__SIZE 0x00000001u +#define CYFLD_CSD_SW_HMRH__OFFSET 0x0000001cu +#define CYFLD_CSD_SW_HMRH__SIZE 0x00000001u +#define CYREG_CSD_SW_HS_N_SEL 0x40290284u +#define CYFLD_CSD_SW_HCCC__OFFSET 0x00000010u +#define CYFLD_CSD_SW_HCCC__SIZE 0x00000001u +#define CYFLD_CSD_SW_HCCD__OFFSET 0x00000014u +#define CYFLD_CSD_SW_HCCD__SIZE 0x00000001u +#define CYFLD_CSD_SW_HCRH__OFFSET 0x00000018u +#define CYFLD_CSD_SW_HCRH__SIZE 0x00000003u +#define CYFLD_CSD_SW_HCRL__OFFSET 0x0000001cu +#define CYFLD_CSD_SW_HCRL__SIZE 0x00000003u +#define CYREG_CSD_SW_SHIELD_SEL 0x40290288u +#define CYFLD_CSD_SW_HCAV__OFFSET 0x00000000u +#define CYFLD_CSD_SW_HCAV__SIZE 0x00000003u +#define CYFLD_CSD_SW_HCAG__OFFSET 0x00000004u +#define CYFLD_CSD_SW_HCAG__SIZE 0x00000003u +#define CYFLD_CSD_SW_HCBV__OFFSET 0x00000008u +#define CYFLD_CSD_SW_HCBV__SIZE 0x00000003u +#define CYFLD_CSD_SW_HCBG__OFFSET 0x0000000cu +#define CYFLD_CSD_SW_HCBG__SIZE 0x00000003u +#define CYFLD_CSD_SW_HCCV__OFFSET 0x00000010u +#define CYFLD_CSD_SW_HCCV__SIZE 0x00000001u +#define CYFLD_CSD_SW_HCCG__OFFSET 0x00000014u +#define CYFLD_CSD_SW_HCCG__SIZE 0x00000001u +#define CYREG_CSD_SW_HS_P_SEL1 0x4029028cu +#define CYFLD_CSD_SW_HMRE__OFFSET 0x00000000u +#define CYFLD_CSD_SW_HMRE__SIZE 0x00000001u +#define CYREG_CSD_SW_AMUXBUF_SEL 0x40290290u +#define CYFLD_CSD_SW_IRBY__OFFSET 0x00000004u +#define CYFLD_CSD_SW_IRBY__SIZE 0x00000001u +#define CYFLD_CSD_SW_IRLB__OFFSET 0x00000008u +#define CYFLD_CSD_SW_IRLB__SIZE 0x00000001u +#define CYFLD_CSD_SW_ICA__OFFSET 0x0000000cu +#define CYFLD_CSD_SW_ICA__SIZE 0x00000001u +#define CYFLD_CSD_SW_ICB__OFFSET 0x00000010u +#define CYFLD_CSD_SW_ICB__SIZE 0x00000003u +#define CYFLD_CSD_SW_IRLI__OFFSET 0x00000014u +#define CYFLD_CSD_SW_IRLI__SIZE 0x00000001u +#define CYFLD_CSD_SW_IRH__OFFSET 0x00000018u +#define CYFLD_CSD_SW_IRH__SIZE 0x00000001u +#define CYFLD_CSD_SW_IRL__OFFSET 0x0000001cu +#define CYFLD_CSD_SW_IRL__SIZE 0x00000001u +#define CYREG_CSD_SW_BYP_SEL 0x40290294u +#define CYFLD_CSD_SW_BYA__OFFSET 0x0000000cu +#define CYFLD_CSD_SW_BYA__SIZE 0x00000001u +#define CYFLD_CSD_SW_BYB__OFFSET 0x00000010u +#define CYFLD_CSD_SW_BYB__SIZE 0x00000001u +#define CYFLD_CSD_SW_CBCC__OFFSET 0x00000014u +#define CYFLD_CSD_SW_CBCC__SIZE 0x00000001u +#define CYREG_CSD_SW_CMP_P_SEL 0x402902a0u +#define CYFLD_CSD_SW_SFPM__OFFSET 0x00000000u +#define CYFLD_CSD_SW_SFPM__SIZE 0x00000003u +#define CYFLD_CSD_SW_SFPT__OFFSET 0x00000004u +#define CYFLD_CSD_SW_SFPT__SIZE 0x00000003u +#define CYFLD_CSD_SW_SFPS__OFFSET 0x00000008u +#define CYFLD_CSD_SW_SFPS__SIZE 0x00000003u +#define CYFLD_CSD_SW_SFMA__OFFSET 0x0000000cu +#define CYFLD_CSD_SW_SFMA__SIZE 0x00000001u +#define CYFLD_CSD_SW_SFMB__OFFSET 0x00000010u +#define CYFLD_CSD_SW_SFMB__SIZE 0x00000001u +#define CYFLD_CSD_SW_SFCA__OFFSET 0x00000014u +#define CYFLD_CSD_SW_SFCA__SIZE 0x00000001u +#define CYFLD_CSD_SW_SFCB__OFFSET 0x00000018u +#define CYFLD_CSD_SW_SFCB__SIZE 0x00000001u +#define CYREG_CSD_SW_CMP_N_SEL 0x402902a4u +#define CYFLD_CSD_SW_SCRH__OFFSET 0x00000018u +#define CYFLD_CSD_SW_SCRH__SIZE 0x00000003u +#define CYFLD_CSD_SW_SCRL__OFFSET 0x0000001cu +#define CYFLD_CSD_SW_SCRL__SIZE 0x00000003u +#define CYREG_CSD_SW_REFGEN_SEL 0x402902a8u +#define CYFLD_CSD_SW_IAIB__OFFSET 0x00000000u +#define CYFLD_CSD_SW_IAIB__SIZE 0x00000001u +#define CYFLD_CSD_SW_IBCB__OFFSET 0x00000004u +#define CYFLD_CSD_SW_IBCB__SIZE 0x00000001u +#define CYFLD_CSD_SW_SGMB__OFFSET 0x00000010u +#define CYFLD_CSD_SW_SGMB__SIZE 0x00000001u +#define CYFLD_CSD_SW_SGRE__OFFSET 0x00000018u +#define CYFLD_CSD_SW_SGRE__SIZE 0x00000001u +#define CYFLD_CSD_SW_SGR__OFFSET 0x0000001cu +#define CYFLD_CSD_SW_SGR__SIZE 0x00000001u +#define CYREG_CSD_SW_FW_MOD_SEL 0x402902b0u +#define CYFLD_CSD_SW_F1PM__OFFSET 0x00000000u +#define CYFLD_CSD_SW_F1PM__SIZE 0x00000001u +#define CYFLD_CSD_SW_F1MA__OFFSET 0x00000008u +#define CYFLD_CSD_SW_F1MA__SIZE 0x00000003u +#define CYFLD_CSD_SW_F1CA__OFFSET 0x00000010u +#define CYFLD_CSD_SW_F1CA__SIZE 0x00000003u +#define CYFLD_CSD_SW_C1CC__OFFSET 0x00000014u +#define CYFLD_CSD_SW_C1CC__SIZE 0x00000001u +#define CYFLD_CSD_SW_C1CD__OFFSET 0x00000018u +#define CYFLD_CSD_SW_C1CD__SIZE 0x00000001u +#define CYFLD_CSD_SW_C1F1__OFFSET 0x0000001cu +#define CYFLD_CSD_SW_C1F1__SIZE 0x00000001u +#define CYREG_CSD_SW_FW_TANK_SEL 0x402902b4u +#define CYFLD_CSD_SW_F2PT__OFFSET 0x00000004u +#define CYFLD_CSD_SW_F2PT__SIZE 0x00000001u +#define CYFLD_CSD_SW_F2MA__OFFSET 0x00000008u +#define CYFLD_CSD_SW_F2MA__SIZE 0x00000003u +#define CYFLD_CSD_SW_F2CA__OFFSET 0x0000000cu +#define CYFLD_CSD_SW_F2CA__SIZE 0x00000003u +#define CYFLD_CSD_SW_F2CB__OFFSET 0x00000010u +#define CYFLD_CSD_SW_F2CB__SIZE 0x00000003u +#define CYFLD_CSD_SW_C2CC__OFFSET 0x00000014u +#define CYFLD_CSD_SW_C2CC__SIZE 0x00000001u +#define CYFLD_CSD_SW_C2CD__OFFSET 0x00000018u +#define CYFLD_CSD_SW_C2CD__SIZE 0x00000001u +#define CYFLD_CSD_SW_C2F2__OFFSET 0x0000001cu +#define CYFLD_CSD_SW_C2F2__SIZE 0x00000001u +#define CYREG_CSD_SW_DSI_SEL 0x402902c0u +#define CYFLD_CSD_DSI_CSH_TANK__OFFSET 0x00000000u +#define CYFLD_CSD_DSI_CSH_TANK__SIZE 0x00000003u +#define CYFLD_CSD_DSI_CMOD__OFFSET 0x00000004u +#define CYFLD_CSD_DSI_CMOD__SIZE 0x00000003u +#define CYREG_CSD_SEQ_TIME 0x40290300u +#define CYFLD_CSD_AZ_TIME__OFFSET 0x00000000u +#define CYFLD_CSD_AZ_TIME__SIZE 0x00000008u +#define CYREG_CSD_SEQ_INIT_CNT 0x40290310u +#define CYFLD_CSD_CONV_CNT__OFFSET 0x00000000u +#define CYFLD_CSD_CONV_CNT__SIZE 0x00000010u +#define CYREG_CSD_SEQ_NORM_CNT 0x40290314u +#define CYREG_CSD_ADC_CTL 0x40290320u +#define CYFLD_CSD_ADC_TIME__OFFSET 0x00000000u +#define CYFLD_CSD_ADC_TIME__SIZE 0x00000008u +#define CYFLD_CSD_ADC_MODE__OFFSET 0x00000010u +#define CYFLD_CSD_ADC_MODE__SIZE 0x00000002u +#define CYVAL_CSD_ADC_MODE_OFF 0x00000000u +#define CYVAL_CSD_ADC_MODE_VREF_CNT 0x00000001u +#define CYVAL_CSD_ADC_MODE_VREF_BY2_CNT 0x00000002u +#define CYVAL_CSD_ADC_MODE_VIN_CNT 0x00000003u +#define CYREG_CSD_SEQ_START 0x40290340u +#define CYFLD_CSD_START__OFFSET 0x00000000u +#define CYFLD_CSD_START__SIZE 0x00000001u +#define CYFLD_CSD_SEQ_MODE__OFFSET 0x00000001u +#define CYFLD_CSD_SEQ_MODE__SIZE 0x00000001u +#define CYFLD_CSD_ABORT__OFFSET 0x00000003u +#define CYFLD_CSD_ABORT__SIZE 0x00000001u +#define CYFLD_CSD_DSI_START_EN__OFFSET 0x00000004u +#define CYFLD_CSD_DSI_START_EN__SIZE 0x00000001u +#define CYFLD_CSD_AZ0_SKIP__OFFSET 0x00000008u +#define CYFLD_CSD_AZ0_SKIP__SIZE 0x00000001u +#define CYFLD_CSD_AZ1_SKIP__OFFSET 0x00000009u +#define CYFLD_CSD_AZ1_SKIP__SIZE 0x00000001u +#define CYDEV_LCD_BASE 0x402a0000u +#define CYDEV_LCD_SIZE 0x00010000u +#define CYREG_LCD_ID 0x402a0000u +#define CYFLD_LCD_ID__OFFSET 0x00000000u +#define CYFLD_LCD_ID__SIZE 0x00000010u +#define CYFLD_LCD_REVISION__OFFSET 0x00000010u +#define CYFLD_LCD_REVISION__SIZE 0x00000010u +#define CYREG_LCD_DIVIDER 0x402a0004u +#define CYFLD_LCD_SUBFR_DIV__OFFSET 0x00000000u +#define CYFLD_LCD_SUBFR_DIV__SIZE 0x00000010u +#define CYFLD_LCD_DEAD_DIV__OFFSET 0x00000010u +#define CYFLD_LCD_DEAD_DIV__SIZE 0x00000010u +#define CYREG_LCD_CONTROL 0x402a0008u +#define CYFLD_LCD_LS_EN__OFFSET 0x00000000u +#define CYFLD_LCD_LS_EN__SIZE 0x00000001u +#define CYFLD_LCD_HS_EN__OFFSET 0x00000001u +#define CYFLD_LCD_HS_EN__SIZE 0x00000001u +#define CYFLD_LCD_LCD_MODE__OFFSET 0x00000002u +#define CYFLD_LCD_LCD_MODE__SIZE 0x00000001u +#define CYVAL_LCD_LCD_MODE_LS 0x00000000u +#define CYVAL_LCD_LCD_MODE_HS 0x00000001u +#define CYFLD_LCD_TYPE__OFFSET 0x00000003u +#define CYFLD_LCD_TYPE__SIZE 0x00000001u +#define CYVAL_LCD_TYPE_TYPE_A 0x00000000u +#define CYVAL_LCD_TYPE_TYPE_B 0x00000001u +#define CYFLD_LCD_OP_MODE__OFFSET 0x00000004u +#define CYFLD_LCD_OP_MODE__SIZE 0x00000001u +#define CYVAL_LCD_OP_MODE_PWM 0x00000000u +#define CYVAL_LCD_OP_MODE_CORRELATION 0x00000001u +#define CYFLD_LCD_BIAS__OFFSET 0x00000005u +#define CYFLD_LCD_BIAS__SIZE 0x00000002u +#define CYVAL_LCD_BIAS_HALF 0x00000000u +#define CYVAL_LCD_BIAS_THIRD 0x00000001u +#define CYVAL_LCD_BIAS_FOURTH 0x00000002u +#define CYVAL_LCD_BIAS_FIFTH 0x00000003u +#define CYFLD_LCD_COM_NUM__OFFSET 0x00000008u +#define CYFLD_LCD_COM_NUM__SIZE 0x00000004u +#define CYFLD_LCD_LS_EN_STAT__OFFSET 0x0000001fu +#define CYFLD_LCD_LS_EN_STAT__SIZE 0x00000001u +#define CYREG_LCD_DATA00 0x402a0100u +#define CYFLD_LCD_DATA__OFFSET 0x00000000u +#define CYFLD_LCD_DATA__SIZE 0x00000020u +#define CYREG_LCD_DATA01 0x402a0104u +#define CYREG_LCD_DATA02 0x402a0108u +#define CYREG_LCD_DATA03 0x402a010cu +#define CYREG_LCD_DATA04 0x402a0110u +#define CYREG_LCD_DATA05 0x402a0114u +#define CYREG_LCD_DATA06 0x402a0118u +#define CYREG_LCD_DATA07 0x402a011cu +#define CYREG_LCD_DATA10 0x402a0200u +#define CYREG_LCD_DATA11 0x402a0204u +#define CYREG_LCD_DATA12 0x402a0208u +#define CYREG_LCD_DATA13 0x402a020cu +#define CYREG_LCD_DATA14 0x402a0210u +#define CYREG_LCD_DATA15 0x402a0214u +#define CYREG_LCD_DATA16 0x402a0218u +#define CYREG_LCD_DATA17 0x402a021cu +#define CYDEV_LPCOMP_BASE 0x402b0000u +#define CYDEV_LPCOMP_SIZE 0x00010000u +#define CYREG_LPCOMP_ID 0x402b0000u +#define CYFLD_LPCOMP_ID__OFFSET 0x00000000u +#define CYFLD_LPCOMP_ID__SIZE 0x00000010u +#define CYFLD_LPCOMP_REVISION__OFFSET 0x00000010u +#define CYFLD_LPCOMP_REVISION__SIZE 0x00000010u +#define CYREG_LPCOMP_CONFIG 0x402b0004u +#define CYFLD_LPCOMP_MODE1__OFFSET 0x00000000u +#define CYFLD_LPCOMP_MODE1__SIZE 0x00000002u +#define CYVAL_LPCOMP_MODE1_SLOW 0x00000000u +#define CYVAL_LPCOMP_MODE1_FAST 0x00000001u +#define CYVAL_LPCOMP_MODE1_ULP 0x00000002u +#define CYFLD_LPCOMP_HYST1__OFFSET 0x00000002u +#define CYFLD_LPCOMP_HYST1__SIZE 0x00000001u +#define CYFLD_LPCOMP_FILTER1__OFFSET 0x00000003u +#define CYFLD_LPCOMP_FILTER1__SIZE 0x00000001u +#define CYFLD_LPCOMP_INTTYPE1__OFFSET 0x00000004u +#define CYFLD_LPCOMP_INTTYPE1__SIZE 0x00000002u +#define CYVAL_LPCOMP_INTTYPE1_DISABLE 0x00000000u +#define CYVAL_LPCOMP_INTTYPE1_RISING 0x00000001u +#define CYVAL_LPCOMP_INTTYPE1_FALLING 0x00000002u +#define CYVAL_LPCOMP_INTTYPE1_BOTH 0x00000003u +#define CYFLD_LPCOMP_OUT1__OFFSET 0x00000006u +#define CYFLD_LPCOMP_OUT1__SIZE 0x00000001u +#define CYFLD_LPCOMP_ENABLE1__OFFSET 0x00000007u +#define CYFLD_LPCOMP_ENABLE1__SIZE 0x00000001u +#define CYFLD_LPCOMP_MODE2__OFFSET 0x00000008u +#define CYFLD_LPCOMP_MODE2__SIZE 0x00000002u +#define CYVAL_LPCOMP_MODE2_SLOW 0x00000000u +#define CYVAL_LPCOMP_MODE2_FAST 0x00000001u +#define CYVAL_LPCOMP_MODE2_ULP 0x00000002u +#define CYFLD_LPCOMP_HYST2__OFFSET 0x0000000au +#define CYFLD_LPCOMP_HYST2__SIZE 0x00000001u +#define CYFLD_LPCOMP_FILTER2__OFFSET 0x0000000bu +#define CYFLD_LPCOMP_FILTER2__SIZE 0x00000001u +#define CYFLD_LPCOMP_INTTYPE2__OFFSET 0x0000000cu +#define CYFLD_LPCOMP_INTTYPE2__SIZE 0x00000002u +#define CYVAL_LPCOMP_INTTYPE2_DISABLE 0x00000000u +#define CYVAL_LPCOMP_INTTYPE2_RISING 0x00000001u +#define CYVAL_LPCOMP_INTTYPE2_FALLING 0x00000002u +#define CYVAL_LPCOMP_INTTYPE2_BOTH 0x00000003u +#define CYFLD_LPCOMP_OUT2__OFFSET 0x0000000eu +#define CYFLD_LPCOMP_OUT2__SIZE 0x00000001u +#define CYFLD_LPCOMP_ENABLE2__OFFSET 0x0000000fu +#define CYFLD_LPCOMP_ENABLE2__SIZE 0x00000001u +#define CYFLD_LPCOMP_DSI_BYPASS1__OFFSET 0x00000010u +#define CYFLD_LPCOMP_DSI_BYPASS1__SIZE 0x00000001u +#define CYFLD_LPCOMP_DSI_LEVEL1__OFFSET 0x00000011u +#define CYFLD_LPCOMP_DSI_LEVEL1__SIZE 0x00000001u +#define CYFLD_LPCOMP_DSI_BYPASS2__OFFSET 0x00000014u +#define CYFLD_LPCOMP_DSI_BYPASS2__SIZE 0x00000001u +#define CYFLD_LPCOMP_DSI_LEVEL2__OFFSET 0x00000015u +#define CYFLD_LPCOMP_DSI_LEVEL2__SIZE 0x00000001u +#define CYREG_LPCOMP_DFT 0x402b0008u +#define CYFLD_LPCOMP_CAL_EN__OFFSET 0x00000000u +#define CYFLD_LPCOMP_CAL_EN__SIZE 0x00000001u +#define CYFLD_LPCOMP_BYPASS__OFFSET 0x00000001u +#define CYFLD_LPCOMP_BYPASS__SIZE 0x00000001u +#define CYREG_LPCOMP_INTR 0x402b0010u +#define CYFLD_LPCOMP_COMP1__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP1__SIZE 0x00000001u +#define CYFLD_LPCOMP_COMP2__OFFSET 0x00000001u +#define CYFLD_LPCOMP_COMP2__SIZE 0x00000001u +#define CYREG_LPCOMP_INTR_SET 0x402b0014u +#define CYREG_LPCOMP_INTR_MASK 0x402b0018u +#define CYFLD_LPCOMP_COMP1_MASK__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP1_MASK__SIZE 0x00000001u +#define CYFLD_LPCOMP_COMP2_MASK__OFFSET 0x00000001u +#define CYFLD_LPCOMP_COMP2_MASK__SIZE 0x00000001u +#define CYREG_LPCOMP_INTR_MASKED 0x402b001cu +#define CYFLD_LPCOMP_COMP1_MASKED__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP1_MASKED__SIZE 0x00000001u +#define CYFLD_LPCOMP_COMP2_MASKED__OFFSET 0x00000001u +#define CYFLD_LPCOMP_COMP2_MASKED__SIZE 0x00000001u +#define CYREG_LPCOMP_TRIM1 0x402bff00u +#define CYFLD_LPCOMP_COMP1_TRIMA__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP1_TRIMA__SIZE 0x00000005u +#define CYREG_LPCOMP_TRIM2 0x402bff04u +#define CYFLD_LPCOMP_COMP1_TRIMB__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP1_TRIMB__SIZE 0x00000005u +#define CYREG_LPCOMP_TRIM3 0x402bff08u +#define CYFLD_LPCOMP_COMP2_TRIMA__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP2_TRIMA__SIZE 0x00000005u +#define CYREG_LPCOMP_TRIM4 0x402bff0cu +#define CYFLD_LPCOMP_COMP2_TRIMB__OFFSET 0x00000000u +#define CYFLD_LPCOMP_COMP2_TRIMB__SIZE 0x00000005u +#define CYDEV_CRYPTO_BASE 0x402c0000u +#define CYDEV_CRYPTO_SIZE 0x00010000u +#define CYREG_CRYPTO_CTL 0x402c0000u +#define CYFLD_CRYPTO_OPCODE__OFFSET 0x00000000u +#define CYFLD_CRYPTO_OPCODE__SIZE 0x00000005u +#define CYVAL_CRYPTO_OPCODE_AES_FORWARD 0x00000000u +#define CYVAL_CRYPTO_OPCODE_AES_INVERSE 0x00000001u +#define CYVAL_CRYPTO_OPCODE_SHA 0x00000010u +#define CYVAL_CRYPTO_OPCODE_CRC 0x00000018u +#define CYFLD_CRYPTO_ENABLED__OFFSET 0x0000001fu +#define CYFLD_CRYPTO_ENABLED__SIZE 0x00000001u +#define CYREG_CRYPTO_STATUS 0x402c0004u +#define CYFLD_CRYPTO_BUSY__OFFSET 0x00000000u +#define CYFLD_CRYPTO_BUSY__SIZE 0x00000001u +#define CYREG_CRYPTO_CMD 0x402c0008u +#define CYFLD_CRYPTO_START__OFFSET 0x00000000u +#define CYFLD_CRYPTO_START__SIZE 0x00000001u +#define CYREG_CRYPTO_TR_CTL0 0x402c0280u +#define CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__OFFSET 0x00000000u +#define CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__SIZE 0x00000008u +#define CYFLD_CRYPTO_RED_CLOCK_DIV__OFFSET 0x00000008u +#define CYFLD_CRYPTO_RED_CLOCK_DIV__SIZE 0x00000008u +#define CYFLD_CRYPTO_INIT_DELAY__OFFSET 0x00000010u +#define CYFLD_CRYPTO_INIT_DELAY__SIZE 0x00000008u +#define CYFLD_CRYPTO_VON_NEUMANN_CORR__OFFSET 0x00000018u +#define CYFLD_CRYPTO_VON_NEUMANN_CORR__SIZE 0x00000001u +#define CYFLD_CRYPTO_STOP_ON_AP_DETECT__OFFSET 0x0000001cu +#define CYFLD_CRYPTO_STOP_ON_AP_DETECT__SIZE 0x00000001u +#define CYFLD_CRYPTO_STOP_ON_RC_DETECT__OFFSET 0x0000001du +#define CYFLD_CRYPTO_STOP_ON_RC_DETECT__SIZE 0x00000001u +#define CYREG_CRYPTO_TR_CTL1 0x402c0284u +#define CYFLD_CRYPTO_DATA_BIT_SIZE__OFFSET 0x00000000u +#define CYFLD_CRYPTO_DATA_BIT_SIZE__SIZE 0x00000006u +#define CYREG_CRYPTO_TR_RESULT0 0x402c0288u +#define CYFLD_CRYPTO_DATA32__OFFSET 0x00000000u +#define CYFLD_CRYPTO_DATA32__SIZE 0x00000020u +#define CYREG_CRYPTO_TR_RESULT1 0x402c028cu +#define CYREG_CRYPTO_TR_CMD 0x402c0290u +#define CYFLD_CRYPTO_START_RO11__OFFSET 0x00000000u +#define CYFLD_CRYPTO_START_RO11__SIZE 0x00000001u +#define CYFLD_CRYPTO_START_RO15__OFFSET 0x00000001u +#define CYFLD_CRYPTO_START_RO15__SIZE 0x00000001u +#define CYFLD_CRYPTO_START_GARO15__OFFSET 0x00000002u +#define CYFLD_CRYPTO_START_GARO15__SIZE 0x00000001u +#define CYFLD_CRYPTO_START_GARO31__OFFSET 0x00000003u +#define CYFLD_CRYPTO_START_GARO31__SIZE 0x00000001u +#define CYFLD_CRYPTO_START_FIRO15__OFFSET 0x00000004u +#define CYFLD_CRYPTO_START_FIRO15__SIZE 0x00000001u +#define CYFLD_CRYPTO_START_FIRO31__OFFSET 0x00000005u +#define CYFLD_CRYPTO_START_FIRO31__SIZE 0x00000001u +#define CYREG_CRYPTO_TR_GARO_CTL 0x402c02a0u +#define CYFLD_CRYPTO_POLYNOMIAL31__OFFSET 0x00000000u +#define CYFLD_CRYPTO_POLYNOMIAL31__SIZE 0x0000001fu +#define CYREG_CRYPTO_TR_FIRO_CTL 0x402c02a4u +#define CYREG_CRYPTO_TR_MON_CTL 0x402c02c0u +#define CYFLD_CRYPTO_BITSTREAM_SEL__OFFSET 0x00000000u +#define CYFLD_CRYPTO_BITSTREAM_SEL__SIZE 0x00000002u +#define CYREG_CRYPTO_TR_MON_CMD 0x402c02c8u +#define CYFLD_CRYPTO_START_AP__OFFSET 0x00000000u +#define CYFLD_CRYPTO_START_AP__SIZE 0x00000001u +#define CYFLD_CRYPTO_START_RC__OFFSET 0x00000001u +#define CYFLD_CRYPTO_START_RC__SIZE 0x00000001u +#define CYREG_CRYPTO_TR_MON_RC_CTL 0x402c02d0u +#define CYFLD_CRYPTO_CUTOFF_COUNT8__OFFSET 0x00000000u +#define CYFLD_CRYPTO_CUTOFF_COUNT8__SIZE 0x00000008u +#define CYREG_CRYPTO_TR_MON_RC_STATUS0 0x402c02d8u +#define CYFLD_CRYPTO_BIT__OFFSET 0x00000000u +#define CYFLD_CRYPTO_BIT__SIZE 0x00000001u +#define CYREG_CRYPTO_TR_MON_RC_STATUS1 0x402c02dcu +#define CYFLD_CRYPTO_REP_COUNT__OFFSET 0x00000000u +#define CYFLD_CRYPTO_REP_COUNT__SIZE 0x00000008u +#define CYREG_CRYPTO_TR_MON_AP_CTL 0x402c02e0u +#define CYFLD_CRYPTO_CUTOFF_COUNT16__OFFSET 0x00000000u +#define CYFLD_CRYPTO_CUTOFF_COUNT16__SIZE 0x00000010u +#define CYFLD_CRYPTO_WINDOW_SIZE__OFFSET 0x00000010u +#define CYFLD_CRYPTO_WINDOW_SIZE__SIZE 0x00000010u +#define CYREG_CRYPTO_TR_MON_AP_STATUS0 0x402c02e8u +#define CYREG_CRYPTO_TR_MON_AP_STATUS1 0x402c02ecu +#define CYFLD_CRYPTO_OCC_COUNT__OFFSET 0x00000000u +#define CYFLD_CRYPTO_OCC_COUNT__SIZE 0x00000010u +#define CYFLD_CRYPTO_WINDOW_INDEX__OFFSET 0x00000010u +#define CYFLD_CRYPTO_WINDOW_INDEX__SIZE 0x00000010u +#define CYREG_CRYPTO_INTR 0x402c07c0u +#define CYFLD_CRYPTO_DONE__OFFSET 0x00000000u +#define CYFLD_CRYPTO_DONE__SIZE 0x00000001u +#define CYFLD_CRYPTO_ACCESS_ERROR__OFFSET 0x00000001u +#define CYFLD_CRYPTO_ACCESS_ERROR__SIZE 0x00000001u +#define CYFLD_CRYPTO_TR_INITIALIZED__OFFSET 0x00000006u +#define CYFLD_CRYPTO_TR_INITIALIZED__SIZE 0x00000001u +#define CYFLD_CRYPTO_TR_DATA_AVAILABLE__OFFSET 0x00000007u +#define CYFLD_CRYPTO_TR_DATA_AVAILABLE__SIZE 0x00000001u +#define CYFLD_CRYPTO_TR_AP_DETECT__OFFSET 0x00000008u +#define CYFLD_CRYPTO_TR_AP_DETECT__SIZE 0x00000001u +#define CYFLD_CRYPTO_TR_RC_DETECT__OFFSET 0x00000009u +#define CYFLD_CRYPTO_TR_RC_DETECT__SIZE 0x00000001u +#define CYREG_CRYPTO_INTR_SET 0x402c07c4u +#define CYREG_CRYPTO_INTR_MASK 0x402c07c8u +#define CYREG_CRYPTO_INTR_MASKED 0x402c07ccu +#define CYREG_CRYPTO_MEM_BUFF0 0x402c0800u +#define CYREG_CRYPTO_MEM_BUFF1 0x402c0804u +#define CYREG_CRYPTO_MEM_BUFF2 0x402c0808u +#define CYREG_CRYPTO_MEM_BUFF3 0x402c080cu +#define CYREG_CRYPTO_MEM_BUFF4 0x402c0810u +#define CYREG_CRYPTO_MEM_BUFF5 0x402c0814u +#define CYREG_CRYPTO_MEM_BUFF6 0x402c0818u +#define CYREG_CRYPTO_MEM_BUFF7 0x402c081cu +#define CYREG_CRYPTO_MEM_BUFF8 0x402c0820u +#define CYREG_CRYPTO_MEM_BUFF9 0x402c0824u +#define CYREG_CRYPTO_MEM_BUFF10 0x402c0828u +#define CYREG_CRYPTO_MEM_BUFF11 0x402c082cu +#define CYREG_CRYPTO_MEM_BUFF12 0x402c0830u +#define CYREG_CRYPTO_MEM_BUFF13 0x402c0834u +#define CYREG_CRYPTO_MEM_BUFF14 0x402c0838u +#define CYREG_CRYPTO_MEM_BUFF15 0x402c083cu +#define CYREG_CRYPTO_MEM_BUFF16 0x402c0840u +#define CYREG_CRYPTO_MEM_BUFF17 0x402c0844u +#define CYREG_CRYPTO_MEM_BUFF18 0x402c0848u +#define CYREG_CRYPTO_MEM_BUFF19 0x402c084cu +#define CYREG_CRYPTO_MEM_BUFF20 0x402c0850u +#define CYREG_CRYPTO_MEM_BUFF21 0x402c0854u +#define CYREG_CRYPTO_MEM_BUFF22 0x402c0858u +#define CYREG_CRYPTO_MEM_BUFF23 0x402c085cu +#define CYREG_CRYPTO_MEM_BUFF24 0x402c0860u +#define CYREG_CRYPTO_MEM_BUFF25 0x402c0864u +#define CYREG_CRYPTO_MEM_BUFF26 0x402c0868u +#define CYREG_CRYPTO_MEM_BUFF27 0x402c086cu +#define CYREG_CRYPTO_MEM_BUFF28 0x402c0870u +#define CYREG_CRYPTO_MEM_BUFF29 0x402c0874u +#define CYREG_CRYPTO_MEM_BUFF30 0x402c0878u +#define CYREG_CRYPTO_MEM_BUFF31 0x402c087cu +#define CYREG_CRYPTO_MEM_BUFF32 0x402c0880u +#define CYREG_CRYPTO_MEM_BUFF33 0x402c0884u +#define CYREG_CRYPTO_MEM_BUFF34 0x402c0888u +#define CYREG_CRYPTO_MEM_BUFF35 0x402c088cu +#define CYREG_CRYPTO_MEM_BUFF36 0x402c0890u +#define CYREG_CRYPTO_MEM_BUFF37 0x402c0894u +#define CYREG_CRYPTO_MEM_BUFF38 0x402c0898u +#define CYREG_CRYPTO_MEM_BUFF39 0x402c089cu +#define CYREG_CRYPTO_MEM_BUFF40 0x402c08a0u +#define CYREG_CRYPTO_MEM_BUFF41 0x402c08a4u +#define CYREG_CRYPTO_MEM_BUFF42 0x402c08a8u +#define CYREG_CRYPTO_MEM_BUFF43 0x402c08acu +#define CYREG_CRYPTO_MEM_BUFF44 0x402c08b0u +#define CYREG_CRYPTO_MEM_BUFF45 0x402c08b4u +#define CYREG_CRYPTO_MEM_BUFF46 0x402c08b8u +#define CYREG_CRYPTO_MEM_BUFF47 0x402c08bcu +#define CYREG_CRYPTO_MEM_BUFF48 0x402c08c0u +#define CYREG_CRYPTO_MEM_BUFF49 0x402c08c4u +#define CYREG_CRYPTO_MEM_BUFF50 0x402c08c8u +#define CYREG_CRYPTO_MEM_BUFF51 0x402c08ccu +#define CYREG_CRYPTO_MEM_BUFF52 0x402c08d0u +#define CYREG_CRYPTO_MEM_BUFF53 0x402c08d4u +#define CYREG_CRYPTO_MEM_BUFF54 0x402c08d8u +#define CYREG_CRYPTO_MEM_BUFF55 0x402c08dcu +#define CYREG_CRYPTO_MEM_BUFF56 0x402c08e0u +#define CYREG_CRYPTO_MEM_BUFF57 0x402c08e4u +#define CYREG_CRYPTO_MEM_BUFF58 0x402c08e8u +#define CYREG_CRYPTO_MEM_BUFF59 0x402c08ecu +#define CYREG_CRYPTO_MEM_BUFF60 0x402c08f0u +#define CYREG_CRYPTO_MEM_BUFF61 0x402c08f4u +#define CYREG_CRYPTO_MEM_BUFF62 0x402c08f8u +#define CYREG_CRYPTO_MEM_BUFF63 0x402c08fcu +#define CYREG_CRYPTO_PRIV_BUF 0x402cff00u +#define CYFLD_CRYPTO_BUF_PRIV_LIMIT__OFFSET 0x00000000u +#define CYFLD_CRYPTO_BUF_PRIV_LIMIT__SIZE 0x00000003u +#define CYDEV_CAN_BASE 0x402e0000u +#define CYDEV_CAN_SIZE 0x00010000u +#define CYREG_CAN_INT_STATUS 0x402e0000u +#define CYFLD_CAN_ARB_LOSS__OFFSET 0x00000002u +#define CYFLD_CAN_ARB_LOSS__SIZE 0x00000001u +#define CYFLD_CAN_OVR_LOAD__OFFSET 0x00000003u +#define CYFLD_CAN_OVR_LOAD__SIZE 0x00000001u +#define CYFLD_CAN_BIT_ERR__OFFSET 0x00000004u +#define CYFLD_CAN_BIT_ERR__SIZE 0x00000001u +#define CYFLD_CAN_STUFF_ERR__OFFSET 0x00000005u +#define CYFLD_CAN_STUFF_ERR__SIZE 0x00000001u +#define CYFLD_CAN_ACK_ERR__OFFSET 0x00000006u +#define CYFLD_CAN_ACK_ERR__SIZE 0x00000001u +#define CYFLD_CAN_FORM_ERR__OFFSET 0x00000007u +#define CYFLD_CAN_FORM_ERR__SIZE 0x00000001u +#define CYFLD_CAN_CRC_ERR__OFFSET 0x00000008u +#define CYFLD_CAN_CRC_ERR__SIZE 0x00000001u +#define CYFLD_CAN_BUS_OFF__OFFSET 0x00000009u +#define CYFLD_CAN_BUS_OFF__SIZE 0x00000001u +#define CYFLD_CAN_RX_MSG_LOSS__OFFSET 0x0000000au +#define CYFLD_CAN_RX_MSG_LOSS__SIZE 0x00000001u +#define CYFLD_CAN_TX_MSG__OFFSET 0x0000000bu +#define CYFLD_CAN_TX_MSG__SIZE 0x00000001u +#define CYFLD_CAN_RX_MSG__OFFSET 0x0000000cu +#define CYFLD_CAN_RX_MSG__SIZE 0x00000001u +#define CYFLD_CAN_RTR_MSG__OFFSET 0x0000000du +#define CYFLD_CAN_RTR_MSG__SIZE 0x00000001u +#define CYFLD_CAN_STUCK_AT_0__OFFSET 0x0000000eu +#define CYFLD_CAN_STUCK_AT_0__SIZE 0x00000001u +#define CYFLD_CAN_SST_FAILURE__OFFSET 0x0000000fu +#define CYFLD_CAN_SST_FAILURE__SIZE 0x00000001u +#define CYREG_CAN_INT_EBL 0x402e0004u +#define CYFLD_CAN_GLOBAL_INT_ENBL__OFFSET 0x00000000u +#define CYFLD_CAN_GLOBAL_INT_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_ARB_LOSS_ENBL__OFFSET 0x00000002u +#define CYFLD_CAN_ARB_LOSS_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_OVR_LOAD_ENBL__OFFSET 0x00000003u +#define CYFLD_CAN_OVR_LOAD_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_BIT_ERR_ENBL__OFFSET 0x00000004u +#define CYFLD_CAN_BIT_ERR_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_STUFF_ERR_ENBL__OFFSET 0x00000005u +#define CYFLD_CAN_STUFF_ERR_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_ACK_ERR_ENBL__OFFSET 0x00000006u +#define CYFLD_CAN_ACK_ERR_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_FORM_ERR_ENBL__OFFSET 0x00000007u +#define CYFLD_CAN_FORM_ERR_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_CRC_ERR_ENBL__OFFSET 0x00000008u +#define CYFLD_CAN_CRC_ERR_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_BUS_OFF_ENBL__OFFSET 0x00000009u +#define CYFLD_CAN_BUS_OFF_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_TX_MSG_ENBL__OFFSET 0x0000000bu +#define CYFLD_CAN_TX_MSG_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_RX_MSG_ENBl__OFFSET 0x0000000cu +#define CYFLD_CAN_RX_MSG_ENBl__SIZE 0x00000001u +#define CYFLD_CAN_RTR_MSG_ENBL__OFFSET 0x0000000du +#define CYFLD_CAN_RTR_MSG_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_STUCK_AT_0_ENBL__OFFSET 0x0000000eu +#define CYFLD_CAN_STUCK_AT_0_ENBL__SIZE 0x00000001u +#define CYFLD_CAN_SST_FAILURE_ENBL__OFFSET 0x0000000fu +#define CYFLD_CAN_SST_FAILURE_ENBL__SIZE 0x00000001u +#define CYREG_CAN_BUFFER_STATUS 0x402e0008u +#define CYFLD_CAN_RX0_MSG_AV__OFFSET 0x00000000u +#define CYFLD_CAN_RX0_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX1_MSG_AV__OFFSET 0x00000001u +#define CYFLD_CAN_RX1_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX2_MSG_AV__OFFSET 0x00000002u +#define CYFLD_CAN_RX2_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX3_MSG_AV__OFFSET 0x00000003u +#define CYFLD_CAN_RX3_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX4_MSG_AV__OFFSET 0x00000004u +#define CYFLD_CAN_RX4_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX5_MSG_AV__OFFSET 0x00000005u +#define CYFLD_CAN_RX5_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX6_MSG_AV__OFFSET 0x00000006u +#define CYFLD_CAN_RX6_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX7_MSG_AV__OFFSET 0x00000007u +#define CYFLD_CAN_RX7_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX8_MSG_AV__OFFSET 0x00000008u +#define CYFLD_CAN_RX8_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX9_MSG_AV__OFFSET 0x00000009u +#define CYFLD_CAN_RX9_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX10_MSG_AV__OFFSET 0x0000000au +#define CYFLD_CAN_RX10_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX11_MSG_AV__OFFSET 0x0000000bu +#define CYFLD_CAN_RX11_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX12_MSG_AV__OFFSET 0x0000000cu +#define CYFLD_CAN_RX12_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX13_MSG_AV__OFFSET 0x0000000du +#define CYFLD_CAN_RX13_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX14_MSG_AV__OFFSET 0x0000000eu +#define CYFLD_CAN_RX14_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_RX15_MSG_AV__OFFSET 0x0000000fu +#define CYFLD_CAN_RX15_MSG_AV__SIZE 0x00000001u +#define CYFLD_CAN_TX0_REQ_PEND__OFFSET 0x00000010u +#define CYFLD_CAN_TX0_REQ_PEND__SIZE 0x00000001u +#define CYFLD_CAN_TX1_REQ_PEND__OFFSET 0x00000011u +#define CYFLD_CAN_TX1_REQ_PEND__SIZE 0x00000001u +#define CYFLD_CAN_TX2_REQ_PEND__OFFSET 0x00000012u +#define CYFLD_CAN_TX2_REQ_PEND__SIZE 0x00000001u +#define CYFLD_CAN_TX3_REQ_PEND__OFFSET 0x00000013u +#define CYFLD_CAN_TX3_REQ_PEND__SIZE 0x00000001u +#define CYFLD_CAN_TX4_REQ_PEND__OFFSET 0x00000014u +#define CYFLD_CAN_TX4_REQ_PEND__SIZE 0x00000001u +#define CYFLD_CAN_TX5_REQ_PEND__OFFSET 0x00000015u +#define CYFLD_CAN_TX5_REQ_PEND__SIZE 0x00000001u +#define CYFLD_CAN_TX6_REQ_PEND__OFFSET 0x00000016u +#define CYFLD_CAN_TX6_REQ_PEND__SIZE 0x00000001u +#define CYFLD_CAN_TX7_REQ_PEND__OFFSET 0x00000017u +#define CYFLD_CAN_TX7_REQ_PEND__SIZE 0x00000001u +#define CYREG_CAN_ERROR_STATUS 0x402e000cu +#define CYFLD_CAN_TX_ERR_CNT__OFFSET 0x00000000u +#define CYFLD_CAN_TX_ERR_CNT__SIZE 0x00000008u +#define CYFLD_CAN_RX_ERR_CNT__OFFSET 0x00000008u +#define CYFLD_CAN_RX_ERR_CNT__SIZE 0x00000008u +#define CYFLD_CAN_ERROR_STATE__OFFSET 0x00000010u +#define CYFLD_CAN_ERROR_STATE__SIZE 0x00000002u +#define CYFLD_CAN_TXGTE96__OFFSET 0x00000012u +#define CYFLD_CAN_TXGTE96__SIZE 0x00000001u +#define CYFLD_CAN_RXGTE96__OFFSET 0x00000013u +#define CYFLD_CAN_RXGTE96__SIZE 0x00000001u +#define CYREG_CAN_COMMAND 0x402e0010u +#define CYFLD_CAN_RUN__OFFSET 0x00000000u +#define CYFLD_CAN_RUN__SIZE 0x00000001u +#define CYFLD_CAN_LISTEN__OFFSET 0x00000001u +#define CYFLD_CAN_LISTEN__SIZE 0x00000001u +#define CYFLD_CAN_LOOPBACK_TEST__OFFSET 0x00000002u +#define CYFLD_CAN_LOOPBACK_TEST__SIZE 0x00000001u +#define CYFLD_CAN_SRAM_TEST__OFFSET 0x00000003u +#define CYFLD_CAN_SRAM_TEST__SIZE 0x00000001u +#define CYFLD_CAN_IP_REV_NUMBER__OFFSET 0x00000010u +#define CYFLD_CAN_IP_REV_NUMBER__SIZE 0x00000008u +#define CYFLD_CAN_IP_MINOR_VERSION__OFFSET 0x00000018u +#define CYFLD_CAN_IP_MINOR_VERSION__SIZE 0x00000004u +#define CYFLD_CAN_IP_MAJOR_VERSION__OFFSET 0x0000001cu +#define CYFLD_CAN_IP_MAJOR_VERSION__SIZE 0x00000004u +#define CYREG_CAN_CONFIG 0x402e0014u +#define CYFLD_CAN_EDGE_MODE__OFFSET 0x00000000u +#define CYFLD_CAN_EDGE_MODE__SIZE 0x00000001u +#define CYFLD_CAN_SAMPLING_MODE__OFFSET 0x00000001u +#define CYFLD_CAN_SAMPLING_MODE__SIZE 0x00000001u +#define CYFLD_CAN_CFG_SJW__OFFSET 0x00000002u +#define CYFLD_CAN_CFG_SJW__SIZE 0x00000002u +#define CYFLD_CAN_AUTO_RESTART__OFFSET 0x00000004u +#define CYFLD_CAN_AUTO_RESTART__SIZE 0x00000001u +#define CYFLD_CAN_CFG_TSEG2__OFFSET 0x00000005u +#define CYFLD_CAN_CFG_TSEG2__SIZE 0x00000003u +#define CYFLD_CAN_CFG_TSEG1__OFFSET 0x00000008u +#define CYFLD_CAN_CFG_TSEG1__SIZE 0x00000004u +#define CYFLD_CAN_CFG_ARBITER__OFFSET 0x0000000cu +#define CYFLD_CAN_CFG_ARBITER__SIZE 0x00000001u +#define CYFLD_CAN_SWAP_ENDIAN__OFFSET 0x0000000du +#define CYFLD_CAN_SWAP_ENDIAN__SIZE 0x00000001u +#define CYFLD_CAN_ECR_MODE__OFFSET 0x0000000eu +#define CYFLD_CAN_ECR_MODE__SIZE 0x00000001u +#define CYFLD_CAN_CFG_BITRATE__OFFSET 0x00000010u +#define CYFLD_CAN_CFG_BITRATE__SIZE 0x0000000fu +#define CYREG_CAN_ECR 0x402e0018u +#define CYFLD_CAN_ECR_STATUS__OFFSET 0x00000000u +#define CYFLD_CAN_ECR_STATUS__SIZE 0x00000001u +#define CYFLD_CAN_ERROR_TYPE__OFFSET 0x00000001u +#define CYFLD_CAN_ERROR_TYPE__SIZE 0x00000003u +#define CYFLD_CAN_RX_MODE__OFFSET 0x00000004u +#define CYFLD_CAN_RX_MODE__SIZE 0x00000001u +#define CYFLD_CAN_TX_MODE__OFFSET 0x00000005u +#define CYFLD_CAN_TX_MODE__SIZE 0x00000001u +#define CYFLD_CAN_BIT__OFFSET 0x00000006u +#define CYFLD_CAN_BIT__SIZE 0x00000006u +#define CYFLD_CAN_Field__OFFSET 0x0000000cu +#define CYFLD_CAN_Field__SIZE 0x00000005u +#define CYDEV_CAN_CAN_TX0_BASE 0x402e0020u +#define CYDEV_CAN_CAN_TX0_SIZE 0x00000010u +#define CYREG_CAN_CAN_TX0_CONTROL 0x402e0020u +#define CYFLD_CAN_CAN_TX_TX_REQ__OFFSET 0x00000000u +#define CYFLD_CAN_CAN_TX_TX_REQ__SIZE 0x00000001u +#define CYFLD_CAN_CAN_TX_TX_ABORT__OFFSET 0x00000001u +#define CYFLD_CAN_CAN_TX_TX_ABORT__SIZE 0x00000001u +#define CYFLD_CAN_CAN_TX_TX_INT_EBL__OFFSET 0x00000002u +#define CYFLD_CAN_CAN_TX_TX_INT_EBL__SIZE 0x00000001u +#define CYFLD_CAN_CAN_TX_WPNL__OFFSET 0x00000003u +#define CYFLD_CAN_CAN_TX_WPNL__SIZE 0x00000001u +#define CYFLD_CAN_CAN_TX_DLC__OFFSET 0x00000010u +#define CYFLD_CAN_CAN_TX_DLC__SIZE 0x00000004u +#define CYFLD_CAN_CAN_TX_IDE__OFFSET 0x00000014u +#define CYFLD_CAN_CAN_TX_IDE__SIZE 0x00000001u +#define CYFLD_CAN_CAN_TX_RTR__OFFSET 0x00000015u +#define CYFLD_CAN_CAN_TX_RTR__SIZE 0x00000001u +#define CYFLD_CAN_CAN_TX_WPNH__OFFSET 0x00000017u +#define CYFLD_CAN_CAN_TX_WPNH__SIZE 0x00000001u +#define CYREG_CAN_CAN_TX0_ID 0x402e0024u +#define CYFLD_CAN_CAN_TX_ID__OFFSET 0x00000003u +#define CYFLD_CAN_CAN_TX_ID__SIZE 0x0000001du +#define CYREG_CAN_CAN_TX0_DATA_HIGH 0x402e0028u +#define CYFLD_CAN_CAN_TX_DATA__OFFSET 0x00000000u +#define CYFLD_CAN_CAN_TX_DATA__SIZE 0x00000020u +#define CYREG_CAN_CAN_TX0_DATA_LOW 0x402e002cu +#define CYDEV_CAN_CAN_TX1_BASE 0x402e0030u +#define CYDEV_CAN_CAN_TX1_SIZE 0x00000010u +#define CYREG_CAN_CAN_TX1_CONTROL 0x402e0030u +#define CYREG_CAN_CAN_TX1_ID 0x402e0034u +#define CYREG_CAN_CAN_TX1_DATA_HIGH 0x402e0038u +#define CYREG_CAN_CAN_TX1_DATA_LOW 0x402e003cu +#define CYDEV_CAN_CAN_TX2_BASE 0x402e0040u +#define CYDEV_CAN_CAN_TX2_SIZE 0x00000010u +#define CYREG_CAN_CAN_TX2_CONTROL 0x402e0040u +#define CYREG_CAN_CAN_TX2_ID 0x402e0044u +#define CYREG_CAN_CAN_TX2_DATA_HIGH 0x402e0048u +#define CYREG_CAN_CAN_TX2_DATA_LOW 0x402e004cu +#define CYDEV_CAN_CAN_TX3_BASE 0x402e0050u +#define CYDEV_CAN_CAN_TX3_SIZE 0x00000010u +#define CYREG_CAN_CAN_TX3_CONTROL 0x402e0050u +#define CYREG_CAN_CAN_TX3_ID 0x402e0054u +#define CYREG_CAN_CAN_TX3_DATA_HIGH 0x402e0058u +#define CYREG_CAN_CAN_TX3_DATA_LOW 0x402e005cu +#define CYDEV_CAN_CAN_TX4_BASE 0x402e0060u +#define CYDEV_CAN_CAN_TX4_SIZE 0x00000010u +#define CYREG_CAN_CAN_TX4_CONTROL 0x402e0060u +#define CYREG_CAN_CAN_TX4_ID 0x402e0064u +#define CYREG_CAN_CAN_TX4_DATA_HIGH 0x402e0068u +#define CYREG_CAN_CAN_TX4_DATA_LOW 0x402e006cu +#define CYDEV_CAN_CAN_TX5_BASE 0x402e0070u +#define CYDEV_CAN_CAN_TX5_SIZE 0x00000010u +#define CYREG_CAN_CAN_TX5_CONTROL 0x402e0070u +#define CYREG_CAN_CAN_TX5_ID 0x402e0074u +#define CYREG_CAN_CAN_TX5_DATA_HIGH 0x402e0078u +#define CYREG_CAN_CAN_TX5_DATA_LOW 0x402e007cu +#define CYDEV_CAN_CAN_TX6_BASE 0x402e0080u +#define CYDEV_CAN_CAN_TX6_SIZE 0x00000010u +#define CYREG_CAN_CAN_TX6_CONTROL 0x402e0080u +#define CYREG_CAN_CAN_TX6_ID 0x402e0084u +#define CYREG_CAN_CAN_TX6_DATA_HIGH 0x402e0088u +#define CYREG_CAN_CAN_TX6_DATA_LOW 0x402e008cu +#define CYDEV_CAN_CAN_TX7_BASE 0x402e0090u +#define CYDEV_CAN_CAN_TX7_SIZE 0x00000010u +#define CYREG_CAN_CAN_TX7_CONTROL 0x402e0090u +#define CYREG_CAN_CAN_TX7_ID 0x402e0094u +#define CYREG_CAN_CAN_TX7_DATA_HIGH 0x402e0098u +#define CYREG_CAN_CAN_TX7_DATA_LOW 0x402e009cu +#define CYDEV_CAN_CAN_RX0_BASE 0x402e00a0u +#define CYDEV_CAN_CAN_RX0_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX0_CONTROL 0x402e00a0u +#define CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__OFFSET 0x00000000u +#define CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__SIZE 0x00000001u +#define CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__OFFSET 0x00000001u +#define CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__SIZE 0x00000001u +#define CYFLD_CAN_CAN_RX_RTR_ABORT__OFFSET 0x00000002u +#define CYFLD_CAN_CAN_RX_RTR_ABORT__SIZE 0x00000001u +#define CYFLD_CAN_CAN_RX_BUFFER_EN__OFFSET 0x00000003u +#define CYFLD_CAN_CAN_RX_BUFFER_EN__SIZE 0x00000001u +#define CYFLD_CAN_CAN_RX_RTR_REPLY__OFFSET 0x00000004u +#define CYFLD_CAN_CAN_RX_RTR_REPLY__SIZE 0x00000001u +#define CYFLD_CAN_CAN_RX_RX_INT_EBL__OFFSET 0x00000005u +#define CYFLD_CAN_CAN_RX_RX_INT_EBL__SIZE 0x00000001u +#define CYFLD_CAN_CAN_RX_LINK_FLAG__OFFSET 0x00000006u +#define CYFLD_CAN_CAN_RX_LINK_FLAG__SIZE 0x00000001u +#define CYFLD_CAN_CAN_RX_WPNL__OFFSET 0x00000007u +#define CYFLD_CAN_CAN_RX_WPNL__SIZE 0x00000001u +#define CYFLD_CAN_CAN_RX_DLC__OFFSET 0x00000010u +#define CYFLD_CAN_CAN_RX_DLC__SIZE 0x00000004u +#define CYFLD_CAN_CAN_RX_IDE_FMT__OFFSET 0x00000014u +#define CYFLD_CAN_CAN_RX_IDE_FMT__SIZE 0x00000001u +#define CYFLD_CAN_CAN_RX_RTR_MSG__OFFSET 0x00000015u +#define CYFLD_CAN_CAN_RX_RTR_MSG__SIZE 0x00000001u +#define CYFLD_CAN_CAN_RX_WPNH__OFFSET 0x00000017u +#define CYFLD_CAN_CAN_RX_WPNH__SIZE 0x00000001u +#define CYREG_CAN_CAN_RX0_ID 0x402e00a4u +#define CYFLD_CAN_CAN_RX_ID__OFFSET 0x00000003u +#define CYFLD_CAN_CAN_RX_ID__SIZE 0x0000001du +#define CYREG_CAN_CAN_RX0_DATA_HIGH 0x402e00a8u +#define CYFLD_CAN_CAN_RX_DATA__OFFSET 0x00000000u +#define CYFLD_CAN_CAN_RX_DATA__SIZE 0x00000020u +#define CYREG_CAN_CAN_RX0_DATA_LOW 0x402e00acu +#define CYREG_CAN_CAN_RX0_AMR 0x402e00b0u +#define CYFLD_CAN_CAN_RX_RTR__OFFSET 0x00000001u +#define CYFLD_CAN_CAN_RX_RTR__SIZE 0x00000001u +#define CYFLD_CAN_CAN_RX_IDE__OFFSET 0x00000002u +#define CYFLD_CAN_CAN_RX_IDE__SIZE 0x00000001u +#define CYREG_CAN_CAN_RX0_ACR 0x402e00b4u +#define CYREG_CAN_CAN_RX0_AMR_DATA 0x402e00b8u +#define CYFLD_CAN_CAN_RX_DATAL__OFFSET 0x00000000u +#define CYFLD_CAN_CAN_RX_DATAL__SIZE 0x00000010u +#define CYREG_CAN_CAN_RX0_ACR_DATA 0x402e00bcu +#define CYDEV_CAN_CAN_RX1_BASE 0x402e00c0u +#define CYDEV_CAN_CAN_RX1_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX1_CONTROL 0x402e00c0u +#define CYREG_CAN_CAN_RX1_ID 0x402e00c4u +#define CYREG_CAN_CAN_RX1_DATA_HIGH 0x402e00c8u +#define CYREG_CAN_CAN_RX1_DATA_LOW 0x402e00ccu +#define CYREG_CAN_CAN_RX1_AMR 0x402e00d0u +#define CYREG_CAN_CAN_RX1_ACR 0x402e00d4u +#define CYREG_CAN_CAN_RX1_AMR_DATA 0x402e00d8u +#define CYREG_CAN_CAN_RX1_ACR_DATA 0x402e00dcu +#define CYDEV_CAN_CAN_RX2_BASE 0x402e00e0u +#define CYDEV_CAN_CAN_RX2_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX2_CONTROL 0x402e00e0u +#define CYREG_CAN_CAN_RX2_ID 0x402e00e4u +#define CYREG_CAN_CAN_RX2_DATA_HIGH 0x402e00e8u +#define CYREG_CAN_CAN_RX2_DATA_LOW 0x402e00ecu +#define CYREG_CAN_CAN_RX2_AMR 0x402e00f0u +#define CYREG_CAN_CAN_RX2_ACR 0x402e00f4u +#define CYREG_CAN_CAN_RX2_AMR_DATA 0x402e00f8u +#define CYREG_CAN_CAN_RX2_ACR_DATA 0x402e00fcu +#define CYDEV_CAN_CAN_RX3_BASE 0x402e0100u +#define CYDEV_CAN_CAN_RX3_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX3_CONTROL 0x402e0100u +#define CYREG_CAN_CAN_RX3_ID 0x402e0104u +#define CYREG_CAN_CAN_RX3_DATA_HIGH 0x402e0108u +#define CYREG_CAN_CAN_RX3_DATA_LOW 0x402e010cu +#define CYREG_CAN_CAN_RX3_AMR 0x402e0110u +#define CYREG_CAN_CAN_RX3_ACR 0x402e0114u +#define CYREG_CAN_CAN_RX3_AMR_DATA 0x402e0118u +#define CYREG_CAN_CAN_RX3_ACR_DATA 0x402e011cu +#define CYDEV_CAN_CAN_RX4_BASE 0x402e0120u +#define CYDEV_CAN_CAN_RX4_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX4_CONTROL 0x402e0120u +#define CYREG_CAN_CAN_RX4_ID 0x402e0124u +#define CYREG_CAN_CAN_RX4_DATA_HIGH 0x402e0128u +#define CYREG_CAN_CAN_RX4_DATA_LOW 0x402e012cu +#define CYREG_CAN_CAN_RX4_AMR 0x402e0130u +#define CYREG_CAN_CAN_RX4_ACR 0x402e0134u +#define CYREG_CAN_CAN_RX4_AMR_DATA 0x402e0138u +#define CYREG_CAN_CAN_RX4_ACR_DATA 0x402e013cu +#define CYDEV_CAN_CAN_RX5_BASE 0x402e0140u +#define CYDEV_CAN_CAN_RX5_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX5_CONTROL 0x402e0140u +#define CYREG_CAN_CAN_RX5_ID 0x402e0144u +#define CYREG_CAN_CAN_RX5_DATA_HIGH 0x402e0148u +#define CYREG_CAN_CAN_RX5_DATA_LOW 0x402e014cu +#define CYREG_CAN_CAN_RX5_AMR 0x402e0150u +#define CYREG_CAN_CAN_RX5_ACR 0x402e0154u +#define CYREG_CAN_CAN_RX5_AMR_DATA 0x402e0158u +#define CYREG_CAN_CAN_RX5_ACR_DATA 0x402e015cu +#define CYDEV_CAN_CAN_RX6_BASE 0x402e0160u +#define CYDEV_CAN_CAN_RX6_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX6_CONTROL 0x402e0160u +#define CYREG_CAN_CAN_RX6_ID 0x402e0164u +#define CYREG_CAN_CAN_RX6_DATA_HIGH 0x402e0168u +#define CYREG_CAN_CAN_RX6_DATA_LOW 0x402e016cu +#define CYREG_CAN_CAN_RX6_AMR 0x402e0170u +#define CYREG_CAN_CAN_RX6_ACR 0x402e0174u +#define CYREG_CAN_CAN_RX6_AMR_DATA 0x402e0178u +#define CYREG_CAN_CAN_RX6_ACR_DATA 0x402e017cu +#define CYDEV_CAN_CAN_RX7_BASE 0x402e0180u +#define CYDEV_CAN_CAN_RX7_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX7_CONTROL 0x402e0180u +#define CYREG_CAN_CAN_RX7_ID 0x402e0184u +#define CYREG_CAN_CAN_RX7_DATA_HIGH 0x402e0188u +#define CYREG_CAN_CAN_RX7_DATA_LOW 0x402e018cu +#define CYREG_CAN_CAN_RX7_AMR 0x402e0190u +#define CYREG_CAN_CAN_RX7_ACR 0x402e0194u +#define CYREG_CAN_CAN_RX7_AMR_DATA 0x402e0198u +#define CYREG_CAN_CAN_RX7_ACR_DATA 0x402e019cu +#define CYDEV_CAN_CAN_RX8_BASE 0x402e01a0u +#define CYDEV_CAN_CAN_RX8_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX8_CONTROL 0x402e01a0u +#define CYREG_CAN_CAN_RX8_ID 0x402e01a4u +#define CYREG_CAN_CAN_RX8_DATA_HIGH 0x402e01a8u +#define CYREG_CAN_CAN_RX8_DATA_LOW 0x402e01acu +#define CYREG_CAN_CAN_RX8_AMR 0x402e01b0u +#define CYREG_CAN_CAN_RX8_ACR 0x402e01b4u +#define CYREG_CAN_CAN_RX8_AMR_DATA 0x402e01b8u +#define CYREG_CAN_CAN_RX8_ACR_DATA 0x402e01bcu +#define CYDEV_CAN_CAN_RX9_BASE 0x402e01c0u +#define CYDEV_CAN_CAN_RX9_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX9_CONTROL 0x402e01c0u +#define CYREG_CAN_CAN_RX9_ID 0x402e01c4u +#define CYREG_CAN_CAN_RX9_DATA_HIGH 0x402e01c8u +#define CYREG_CAN_CAN_RX9_DATA_LOW 0x402e01ccu +#define CYREG_CAN_CAN_RX9_AMR 0x402e01d0u +#define CYREG_CAN_CAN_RX9_ACR 0x402e01d4u +#define CYREG_CAN_CAN_RX9_AMR_DATA 0x402e01d8u +#define CYREG_CAN_CAN_RX9_ACR_DATA 0x402e01dcu +#define CYDEV_CAN_CAN_RX10_BASE 0x402e01e0u +#define CYDEV_CAN_CAN_RX10_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX10_CONTROL 0x402e01e0u +#define CYREG_CAN_CAN_RX10_ID 0x402e01e4u +#define CYREG_CAN_CAN_RX10_DATA_HIGH 0x402e01e8u +#define CYREG_CAN_CAN_RX10_DATA_LOW 0x402e01ecu +#define CYREG_CAN_CAN_RX10_AMR 0x402e01f0u +#define CYREG_CAN_CAN_RX10_ACR 0x402e01f4u +#define CYREG_CAN_CAN_RX10_AMR_DATA 0x402e01f8u +#define CYREG_CAN_CAN_RX10_ACR_DATA 0x402e01fcu +#define CYDEV_CAN_CAN_RX11_BASE 0x402e0200u +#define CYDEV_CAN_CAN_RX11_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX11_CONTROL 0x402e0200u +#define CYREG_CAN_CAN_RX11_ID 0x402e0204u +#define CYREG_CAN_CAN_RX11_DATA_HIGH 0x402e0208u +#define CYREG_CAN_CAN_RX11_DATA_LOW 0x402e020cu +#define CYREG_CAN_CAN_RX11_AMR 0x402e0210u +#define CYREG_CAN_CAN_RX11_ACR 0x402e0214u +#define CYREG_CAN_CAN_RX11_AMR_DATA 0x402e0218u +#define CYREG_CAN_CAN_RX11_ACR_DATA 0x402e021cu +#define CYDEV_CAN_CAN_RX12_BASE 0x402e0220u +#define CYDEV_CAN_CAN_RX12_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX12_CONTROL 0x402e0220u +#define CYREG_CAN_CAN_RX12_ID 0x402e0224u +#define CYREG_CAN_CAN_RX12_DATA_HIGH 0x402e0228u +#define CYREG_CAN_CAN_RX12_DATA_LOW 0x402e022cu +#define CYREG_CAN_CAN_RX12_AMR 0x402e0230u +#define CYREG_CAN_CAN_RX12_ACR 0x402e0234u +#define CYREG_CAN_CAN_RX12_AMR_DATA 0x402e0238u +#define CYREG_CAN_CAN_RX12_ACR_DATA 0x402e023cu +#define CYDEV_CAN_CAN_RX13_BASE 0x402e0240u +#define CYDEV_CAN_CAN_RX13_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX13_CONTROL 0x402e0240u +#define CYREG_CAN_CAN_RX13_ID 0x402e0244u +#define CYREG_CAN_CAN_RX13_DATA_HIGH 0x402e0248u +#define CYREG_CAN_CAN_RX13_DATA_LOW 0x402e024cu +#define CYREG_CAN_CAN_RX13_AMR 0x402e0250u +#define CYREG_CAN_CAN_RX13_ACR 0x402e0254u +#define CYREG_CAN_CAN_RX13_AMR_DATA 0x402e0258u +#define CYREG_CAN_CAN_RX13_ACR_DATA 0x402e025cu +#define CYDEV_CAN_CAN_RX14_BASE 0x402e0260u +#define CYDEV_CAN_CAN_RX14_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX14_CONTROL 0x402e0260u +#define CYREG_CAN_CAN_RX14_ID 0x402e0264u +#define CYREG_CAN_CAN_RX14_DATA_HIGH 0x402e0268u +#define CYREG_CAN_CAN_RX14_DATA_LOW 0x402e026cu +#define CYREG_CAN_CAN_RX14_AMR 0x402e0270u +#define CYREG_CAN_CAN_RX14_ACR 0x402e0274u +#define CYREG_CAN_CAN_RX14_AMR_DATA 0x402e0278u +#define CYREG_CAN_CAN_RX14_ACR_DATA 0x402e027cu +#define CYDEV_CAN_CAN_RX15_BASE 0x402e0280u +#define CYDEV_CAN_CAN_RX15_SIZE 0x00000020u +#define CYREG_CAN_CAN_RX15_CONTROL 0x402e0280u +#define CYREG_CAN_CAN_RX15_ID 0x402e0284u +#define CYREG_CAN_CAN_RX15_DATA_HIGH 0x402e0288u +#define CYREG_CAN_CAN_RX15_DATA_LOW 0x402e028cu +#define CYREG_CAN_CAN_RX15_AMR 0x402e0290u +#define CYREG_CAN_CAN_RX15_ACR 0x402e0294u +#define CYREG_CAN_CAN_RX15_AMR_DATA 0x402e0298u +#define CYREG_CAN_CAN_RX15_ACR_DATA 0x402e029cu +#define CYREG_CAN_CNTL 0x402e0400u +#define CYFLD_CAN_TT_ENABLE__OFFSET 0x00000000u +#define CYFLD_CAN_TT_ENABLE__SIZE 0x00000001u +#define CYFLD_CAN_IP_ENABLE__OFFSET 0x0000001fu +#define CYFLD_CAN_IP_ENABLE__SIZE 0x00000001u +#define CYREG_CAN_TTCAN_COUNTER 0x402e0404u +#define CYFLD_CAN_LOCAL_TIME__OFFSET 0x00000010u +#define CYFLD_CAN_LOCAL_TIME__SIZE 0x00000010u +#define CYREG_CAN_TTCAN_COMPARE 0x402e0408u +#define CYFLD_CAN_TIME_MARK__OFFSET 0x00000010u +#define CYFLD_CAN_TIME_MARK__SIZE 0x00000010u +#define CYREG_CAN_TTCAN_CAPTURE 0x402e040cu +#define CYFLD_CAN_SYNC_MARK__OFFSET 0x00000010u +#define CYFLD_CAN_SYNC_MARK__SIZE 0x00000010u +#define CYREG_CAN_TTCAN_TIMING 0x402e0410u +#define CYREG_CAN_INTR_CAN 0x402e0414u +#define CYFLD_CAN_INT_STATUS__OFFSET 0x00000000u +#define CYFLD_CAN_INT_STATUS__SIZE 0x00000001u +#define CYFLD_CAN_TT_COMPARE__OFFSET 0x00000001u +#define CYFLD_CAN_TT_COMPARE__SIZE 0x00000001u +#define CYFLD_CAN_TT_CAPTURE__OFFSET 0x00000002u +#define CYFLD_CAN_TT_CAPTURE__SIZE 0x00000001u +#define CYREG_CAN_INTR_CAN_SET 0x402e0418u +#define CYREG_CAN_INTR_CAN_MASK 0x402e041cu +#define CYREG_CAN_INTR_CAN_MASKED 0x402e0420u +#define CYDEV_EXCO_BASE 0x402f0000u +#define CYDEV_EXCO_SIZE 0x00010000u +#define CYREG_EXCO_CLK_SELECT 0x402f0000u +#define CYFLD_EXCO_CLK_SELECT__OFFSET 0x00000000u +#define CYFLD_EXCO_CLK_SELECT__SIZE 0x00000001u +#define CYFLD_EXCO_REF_SEL__OFFSET 0x00000001u +#define CYFLD_EXCO_REF_SEL__SIZE 0x00000001u +#define CYREG_EXCO_ECO_CONFIG 0x402f0008u +#define CYFLD_EXCO_CLK_EN__OFFSET 0x00000000u +#define CYFLD_EXCO_CLK_EN__SIZE 0x00000001u +#define CYFLD_EXCO_AGC_EN__OFFSET 0x00000001u +#define CYFLD_EXCO_AGC_EN__SIZE 0x00000001u +#define CYFLD_EXCO_ENABLE__OFFSET 0x0000001fu +#define CYFLD_EXCO_ENABLE__SIZE 0x00000001u +#define CYREG_EXCO_ECO_STATUS 0x402f000cu +#define CYFLD_EXCO_WATCHDOG_ERROR__OFFSET 0x00000000u +#define CYFLD_EXCO_WATCHDOG_ERROR__SIZE 0x00000001u +#define CYREG_EXCO_PLL_CONFIG 0x402f0014u +#define CYFLD_EXCO_FEEDBACK_DIV__OFFSET 0x00000000u +#define CYFLD_EXCO_FEEDBACK_DIV__SIZE 0x00000008u +#define CYFLD_EXCO_REFERENCE_DIV__OFFSET 0x00000008u +#define CYFLD_EXCO_REFERENCE_DIV__SIZE 0x00000006u +#define CYFLD_EXCO_OUTPUT_DIV__OFFSET 0x0000000eu +#define CYFLD_EXCO_OUTPUT_DIV__SIZE 0x00000002u +#define CYVAL_EXCO_OUTPUT_DIV_PASS 0x00000000u +#define CYVAL_EXCO_OUTPUT_DIV_DIV2 0x00000001u +#define CYVAL_EXCO_OUTPUT_DIV_DIV4 0x00000002u +#define CYVAL_EXCO_OUTPUT_DIV_DIV8 0x00000003u +#define CYFLD_EXCO_ICP_SEL__OFFSET 0x00000010u +#define CYFLD_EXCO_ICP_SEL__SIZE 0x00000003u +#define CYFLD_EXCO_BYPASS_SEL__OFFSET 0x00000014u +#define CYFLD_EXCO_BYPASS_SEL__SIZE 0x00000002u +#define CYVAL_EXCO_BYPASS_SEL_AUTO 0x00000000u +#define CYVAL_EXCO_BYPASS_SEL_AUTO1 0x00000001u +#define CYVAL_EXCO_BYPASS_SEL_PLL_REF 0x00000002u +#define CYVAL_EXCO_BYPASS_SEL_PLL_OUT 0x00000003u +#define CYFLD_EXCO_ISOLATE_N__OFFSET 0x0000001eu +#define CYFLD_EXCO_ISOLATE_N__SIZE 0x00000001u +#define CYREG_EXCO_PLL_STATUS 0x402f0018u +#define CYFLD_EXCO_LOCKED__OFFSET 0x00000000u +#define CYFLD_EXCO_LOCKED__SIZE 0x00000001u +#define CYREG_EXCO_PLL_TEST 0x402f001cu +#define CYFLD_EXCO_TEST_MODE__OFFSET 0x00000000u +#define CYFLD_EXCO_TEST_MODE__SIZE 0x00000003u +#define CYVAL_EXCO_TEST_MODE_NORMAL 0x00000000u +#define CYVAL_EXCO_TEST_MODE_TEST_VC_LKG 0x00000001u +#define CYVAL_EXCO_TEST_MODE_TEST_CP_DN 0x00000002u +#define CYVAL_EXCO_TEST_MODE_TEST_CP_UP 0x00000003u +#define CYVAL_EXCO_TEST_MODE_USER_EXT_FL 0x00000004u +#define CYVAL_EXCO_TEST_MODE_TEST_CTR_PQ 0x00000005u +#define CYVAL_EXCO_TEST_MODE_TEST_LD_DLY 0x00000006u +#define CYVAL_EXCO_TEST_MODE_TEST_CTR_ALT 0x00000007u +#define CYFLD_EXCO_FAST_LOCK_EN__OFFSET 0x00000003u +#define CYFLD_EXCO_FAST_LOCK_EN__SIZE 0x00000001u +#define CYFLD_EXCO_UNLOCK_OCCURRED__OFFSET 0x00000004u +#define CYFLD_EXCO_UNLOCK_OCCURRED__SIZE 0x00000001u +#define CYREG_EXCO_EXCO_PGM_CLK 0x402f0020u +#define CYFLD_EXCO_CLK_ECO__OFFSET 0x00000001u +#define CYFLD_EXCO_CLK_ECO__SIZE 0x00000001u +#define CYFLD_EXCO_CLK_PLL0_IN__OFFSET 0x00000002u +#define CYFLD_EXCO_CLK_PLL0_IN__SIZE 0x00000001u +#define CYFLD_EXCO_CLK_PLL0_OUT__OFFSET 0x00000003u +#define CYFLD_EXCO_CLK_PLL0_OUT__SIZE 0x00000001u +#define CYFLD_EXCO_EN_CLK_PLL0__OFFSET 0x00000004u +#define CYFLD_EXCO_EN_CLK_PLL0__SIZE 0x00000001u +#define CYREG_EXCO_ECO_TRIM0 0x402fff00u +#define CYFLD_EXCO_WDTRIM__OFFSET 0x00000000u +#define CYFLD_EXCO_WDTRIM__SIZE 0x00000002u +#define CYFLD_EXCO_ATRIM__OFFSET 0x00000002u +#define CYFLD_EXCO_ATRIM__SIZE 0x00000003u +#define CYREG_EXCO_ECO_TRIM1 0x402fff04u +#define CYFLD_EXCO_FTRIM__OFFSET 0x00000000u +#define CYFLD_EXCO_FTRIM__SIZE 0x00000002u +#define CYFLD_EXCO_RTRIM__OFFSET 0x00000002u +#define CYFLD_EXCO_RTRIM__SIZE 0x00000002u +#define CYFLD_EXCO_GTRIM__OFFSET 0x00000004u +#define CYFLD_EXCO_GTRIM__SIZE 0x00000002u +#define CYREG_EXCO_ECO_TRIM2 0x402fff08u +#define CYFLD_EXCO_ITRIM__OFFSET 0x00000000u +#define CYFLD_EXCO_ITRIM__SIZE 0x00000006u +#define CYREG_EXCO_PLL_TRIM 0x402fff0cu +#define CYFLD_EXCO_VCO_GAIN__OFFSET 0x00000000u +#define CYFLD_EXCO_VCO_GAIN__SIZE 0x00000002u +#define CYFLD_EXCO_LOCK_WINDOW__OFFSET 0x00000002u +#define CYFLD_EXCO_LOCK_WINDOW__SIZE 0x00000002u +#define CYVAL_EXCO_LOCK_WINDOW_DELAY_25NS 0x00000000u +#define CYVAL_EXCO_LOCK_WINDOW_DELAY_50NS 0x00000001u +#define CYVAL_EXCO_LOCK_WINDOW_DELAY_75NS 0x00000002u +#define CYVAL_EXCO_LOCK_WINDOW_DELAY_100NS 0x00000003u +#define CYFLD_EXCO_LOCK_DELAY__OFFSET 0x00000004u +#define CYFLD_EXCO_LOCK_DELAY__SIZE 0x00000002u +#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_16 0x00000000u +#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_32 0x00000001u +#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_48 0x00000002u +#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_64 0x00000003u +#define CYDEV_CTBM0_BASE 0x40300000u +#define CYDEV_CTBM0_SIZE 0x00010000u +#define CYREG_CTBM0_CTB_CTRL 0x40300000u +#define CYFLD_CTBM_DEEPSLEEP_ON__OFFSET 0x0000001eu +#define CYFLD_CTBM_DEEPSLEEP_ON__SIZE 0x00000001u +#define CYFLD_CTBM_ENABLED__OFFSET 0x0000001fu +#define CYFLD_CTBM_ENABLED__SIZE 0x00000001u +#define CYREG_CTBM0_OA_RES0_CTRL 0x40300004u +#define CYFLD_CTBM_OA0_PWR_MODE__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_PWR_MODE__SIZE 0x00000002u +#define CYVAL_CTBM_OA0_PWR_MODE_OFF 0x00000000u +#define CYVAL_CTBM_OA0_PWR_MODE_LOW 0x00000001u +#define CYVAL_CTBM_OA0_PWR_MODE_MEDIUM 0x00000002u +#define CYVAL_CTBM_OA0_PWR_MODE_HIGH 0x00000003u +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET 0x00000002u +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_COMP_EN__OFFSET 0x00000004u +#define CYFLD_CTBM_OA0_COMP_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_HYST_EN__OFFSET 0x00000005u +#define CYFLD_CTBM_OA0_HYST_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET 0x00000006u +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_DSI_LEVEL__OFFSET 0x00000007u +#define CYFLD_CTBM_OA0_DSI_LEVEL__SIZE 0x00000001u +#define CYFLD_CTBM_OA0_COMPINT__OFFSET 0x00000008u +#define CYFLD_CTBM_OA0_COMPINT__SIZE 0x00000002u +#define CYVAL_CTBM_OA0_COMPINT_DISABLE 0x00000000u +#define CYVAL_CTBM_OA0_COMPINT_RISING 0x00000001u +#define CYVAL_CTBM_OA0_COMPINT_FALLING 0x00000002u +#define CYVAL_CTBM_OA0_COMPINT_BOTH 0x00000003u +#define CYFLD_CTBM_OA0_PUMP_EN__OFFSET 0x0000000bu +#define CYFLD_CTBM_OA0_PUMP_EN__SIZE 0x00000001u +#define CYREG_CTBM0_OA_RES1_CTRL 0x40300008u +#define CYFLD_CTBM_OA1_PWR_MODE__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_PWR_MODE__SIZE 0x00000002u +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET 0x00000002u +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_COMP_EN__OFFSET 0x00000004u +#define CYFLD_CTBM_OA1_COMP_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_HYST_EN__OFFSET 0x00000005u +#define CYFLD_CTBM_OA1_HYST_EN__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET 0x00000006u +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_DSI_LEVEL__OFFSET 0x00000007u +#define CYFLD_CTBM_OA1_DSI_LEVEL__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_COMPINT__OFFSET 0x00000008u +#define CYFLD_CTBM_OA1_COMPINT__SIZE 0x00000002u +#define CYVAL_CTBM_OA1_COMPINT_DISABLE 0x00000000u +#define CYVAL_CTBM_OA1_COMPINT_RISING 0x00000001u +#define CYVAL_CTBM_OA1_COMPINT_FALLING 0x00000002u +#define CYVAL_CTBM_OA1_COMPINT_BOTH 0x00000003u +#define CYFLD_CTBM_OA1_PUMP_EN__OFFSET 0x0000000bu +#define CYFLD_CTBM_OA1_PUMP_EN__SIZE 0x00000001u +#define CYREG_CTBM0_COMP_STAT 0x4030000cu +#define CYFLD_CTBM_OA0_COMP__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_COMP__SIZE 0x00000001u +#define CYFLD_CTBM_OA1_COMP__OFFSET 0x00000010u +#define CYFLD_CTBM_OA1_COMP__SIZE 0x00000001u +#define CYREG_CTBM0_INTR 0x40300020u +#define CYFLD_CTBM_COMP0__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1__SIZE 0x00000001u +#define CYREG_CTBM0_INTR_SET 0x40300024u +#define CYFLD_CTBM_COMP0_SET__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0_SET__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1_SET__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1_SET__SIZE 0x00000001u +#define CYREG_CTBM0_INTR_MASK 0x40300028u +#define CYFLD_CTBM_COMP0_MASK__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0_MASK__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1_MASK__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1_MASK__SIZE 0x00000001u +#define CYREG_CTBM0_INTR_MASKED 0x4030002cu +#define CYFLD_CTBM_COMP0_MASKED__OFFSET 0x00000000u +#define CYFLD_CTBM_COMP0_MASKED__SIZE 0x00000001u +#define CYFLD_CTBM_COMP1_MASKED__OFFSET 0x00000001u +#define CYFLD_CTBM_COMP1_MASKED__SIZE 0x00000001u +#define CYREG_CTBM0_DFT_CTRL 0x40300030u +#define CYFLD_CTBM_DFT_MODE__OFFSET 0x00000000u +#define CYFLD_CTBM_DFT_MODE__SIZE 0x00000003u +#define CYFLD_CTBM_DFT_EN__OFFSET 0x0000001fu +#define CYFLD_CTBM_DFT_EN__SIZE 0x00000001u +#define CYREG_CTBM0_OA0_SW 0x40300080u +#define CYFLD_CTBM_OA0P_A00__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0P_A00__SIZE 0x00000001u +#define CYFLD_CTBM_OA0P_A20__OFFSET 0x00000002u +#define CYFLD_CTBM_OA0P_A20__SIZE 0x00000001u +#define CYFLD_CTBM_OA0P_A30__OFFSET 0x00000003u +#define CYFLD_CTBM_OA0P_A30__SIZE 0x00000001u +#define CYFLD_CTBM_OA0M_A11__OFFSET 0x00000008u +#define CYFLD_CTBM_OA0M_A11__SIZE 0x00000001u +#define CYFLD_CTBM_OA0M_A81__OFFSET 0x0000000eu +#define CYFLD_CTBM_OA0M_A81__SIZE 0x00000001u +#define CYFLD_CTBM_OA0O_D51__OFFSET 0x00000012u +#define CYFLD_CTBM_OA0O_D51__SIZE 0x00000001u +#define CYFLD_CTBM_OA0O_D81__OFFSET 0x00000015u +#define CYFLD_CTBM_OA0O_D81__SIZE 0x00000001u +#define CYREG_CTBM0_OA0_SW_CLEAR 0x40300084u +#define CYREG_CTBM0_OA1_SW 0x40300088u +#define CYFLD_CTBM_OA1P_A03__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1P_A03__SIZE 0x00000001u +#define CYFLD_CTBM_OA1P_A13__OFFSET 0x00000001u +#define CYFLD_CTBM_OA1P_A13__SIZE 0x00000001u +#define CYFLD_CTBM_OA1P_A43__OFFSET 0x00000004u +#define CYFLD_CTBM_OA1P_A43__SIZE 0x00000001u +#define CYFLD_CTBM_OA1M_A22__OFFSET 0x00000008u +#define CYFLD_CTBM_OA1M_A22__SIZE 0x00000001u +#define CYFLD_CTBM_OA1M_A82__OFFSET 0x0000000eu +#define CYFLD_CTBM_OA1M_A82__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D52__OFFSET 0x00000012u +#define CYFLD_CTBM_OA1O_D52__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D62__OFFSET 0x00000013u +#define CYFLD_CTBM_OA1O_D62__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D82__OFFSET 0x00000015u +#define CYFLD_CTBM_OA1O_D82__SIZE 0x00000001u +#define CYREG_CTBM0_OA1_SW_CLEAR 0x4030008cu +#define CYREG_CTBM0_CTB_SW_HW_CTRL 0x403000c0u +#define CYFLD_CTBM_P2_HW_CTRL__OFFSET 0x00000002u +#define CYFLD_CTBM_P2_HW_CTRL__SIZE 0x00000001u +#define CYFLD_CTBM_P3_HW_CTRL__OFFSET 0x00000003u +#define CYFLD_CTBM_P3_HW_CTRL__SIZE 0x00000001u +#define CYREG_CTBM0_CTB_SW_STATUS 0x403000c4u +#define CYFLD_CTBM_OA0O_D51_STAT__OFFSET 0x0000001cu +#define CYFLD_CTBM_OA0O_D51_STAT__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D52_STAT__OFFSET 0x0000001du +#define CYFLD_CTBM_OA1O_D52_STAT__SIZE 0x00000001u +#define CYFLD_CTBM_OA1O_D62_STAT__OFFSET 0x0000001eu +#define CYFLD_CTBM_OA1O_D62_STAT__SIZE 0x00000001u +#define CYREG_CTBM0_OA0_OFFSET_TRIM 0x40300f00u +#define CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM0_OA0_SLOPE_OFFSET_TRIM 0x40300f04u +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM0_OA0_COMP_TRIM 0x40300f08u +#define CYFLD_CTBM_OA0_COMP_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA0_COMP_TRIM__SIZE 0x00000002u +#define CYREG_CTBM0_OA1_OFFSET_TRIM 0x40300f0cu +#define CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM0_OA1_SLOPE_OFFSET_TRIM 0x40300f10u +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE 0x00000006u +#define CYREG_CTBM0_OA1_COMP_TRIM 0x40300f14u +#define CYFLD_CTBM_OA1_COMP_TRIM__OFFSET 0x00000000u +#define CYFLD_CTBM_OA1_COMP_TRIM__SIZE 0x00000002u +#define CYDEV_SAR_BASE 0x403a0000u +#define CYDEV_SAR_SIZE 0x00010000u +#define CYREG_SAR_CTRL 0x403a0000u +#define CYFLD_SAR_VREF_SEL__OFFSET 0x00000004u +#define CYFLD_SAR_VREF_SEL__SIZE 0x00000003u +#define CYVAL_SAR_VREF_SEL_VREF0 0x00000000u +#define CYVAL_SAR_VREF_SEL_VREF1 0x00000001u +#define CYVAL_SAR_VREF_SEL_VREF2 0x00000002u +#define CYVAL_SAR_VREF_SEL_VREF_AROUTE 0x00000003u +#define CYVAL_SAR_VREF_SEL_VBGR 0x00000004u +#define CYVAL_SAR_VREF_SEL_VREF_EXT 0x00000005u +#define CYVAL_SAR_VREF_SEL_VDDA_DIV_2 0x00000006u +#define CYVAL_SAR_VREF_SEL_VDDA 0x00000007u +#define CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET 0x00000007u +#define CYFLD_SAR_VREF_BYP_CAP_EN__SIZE 0x00000001u +#define CYFLD_SAR_NEG_SEL__OFFSET 0x00000009u +#define CYFLD_SAR_NEG_SEL__SIZE 0x00000003u +#define CYVAL_SAR_NEG_SEL_VSSA_KELVIN 0x00000000u +#define CYVAL_SAR_NEG_SEL_ART_VSSA 0x00000001u +#define CYVAL_SAR_NEG_SEL_P1 0x00000002u +#define CYVAL_SAR_NEG_SEL_P3 0x00000003u +#define CYVAL_SAR_NEG_SEL_P5 0x00000004u +#define CYVAL_SAR_NEG_SEL_P7 0x00000005u +#define CYVAL_SAR_NEG_SEL_ACORE 0x00000006u +#define CYVAL_SAR_NEG_SEL_VREF 0x00000007u +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET 0x0000000du +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE 0x00000001u +#define CYFLD_SAR_PWR_CTRL_VREF__OFFSET 0x0000000eu +#define CYFLD_SAR_PWR_CTRL_VREF__SIZE 0x00000002u +#define CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR 0x00000000u +#define CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR 0x00000001u +#define CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR 0x00000002u +#define CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR 0x00000003u +#define CYFLD_SAR_SPARE__OFFSET 0x00000010u +#define CYFLD_SAR_SPARE__SIZE 0x00000004u +#define CYFLD_SAR_BOOSTPUMP_EN__OFFSET 0x00000014u +#define CYFLD_SAR_BOOSTPUMP_EN__SIZE 0x00000001u +#define CYFLD_SAR_ICONT_LV__OFFSET 0x00000018u +#define CYFLD_SAR_ICONT_LV__SIZE 0x00000002u +#define CYVAL_SAR_ICONT_LV_NORMAL_PWR 0x00000000u +#define CYVAL_SAR_ICONT_LV_HALF_PWR 0x00000001u +#define CYVAL_SAR_ICONT_LV_MORE_PWR 0x00000002u +#define CYVAL_SAR_ICONT_LV_QUARTER_PWR 0x00000003u +#define CYFLD_SAR_DEEPSLEEP_ON__OFFSET 0x0000001bu +#define CYFLD_SAR_DEEPSLEEP_ON__SIZE 0x00000001u +#define CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET 0x0000001cu +#define CYFLD_SAR_DSI_SYNC_CONFIG__SIZE 0x00000001u +#define CYFLD_SAR_DSI_MODE__OFFSET 0x0000001du +#define CYFLD_SAR_DSI_MODE__SIZE 0x00000001u +#define CYFLD_SAR_SWITCH_DISABLE__OFFSET 0x0000001eu +#define CYFLD_SAR_SWITCH_DISABLE__SIZE 0x00000001u +#define CYFLD_SAR_ENABLED__OFFSET 0x0000001fu +#define CYFLD_SAR_ENABLED__SIZE 0x00000001u +#define CYREG_SAR_SAMPLE_CTRL 0x403a0004u +#define CYFLD_SAR_SUB_RESOLUTION__OFFSET 0x00000000u +#define CYFLD_SAR_SUB_RESOLUTION__SIZE 0x00000001u +#define CYVAL_SAR_SUB_RESOLUTION_8B 0x00000000u +#define CYVAL_SAR_SUB_RESOLUTION_10B 0x00000001u +#define CYFLD_SAR_LEFT_ALIGN__OFFSET 0x00000001u +#define CYFLD_SAR_LEFT_ALIGN__SIZE 0x00000001u +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET 0x00000002u +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE 0x00000001u +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED 0x00000000u +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED 0x00000001u +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET 0x00000003u +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE 0x00000001u +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED 0x00000000u +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED 0x00000001u +#define CYFLD_SAR_AVG_CNT__OFFSET 0x00000004u +#define CYFLD_SAR_AVG_CNT__SIZE 0x00000003u +#define CYFLD_SAR_AVG_SHIFT__OFFSET 0x00000007u +#define CYFLD_SAR_AVG_SHIFT__SIZE 0x00000001u +#define CYFLD_SAR_CONTINUOUS__OFFSET 0x00000010u +#define CYFLD_SAR_CONTINUOUS__SIZE 0x00000001u +#define CYFLD_SAR_DSI_TRIGGER_EN__OFFSET 0x00000011u +#define CYFLD_SAR_DSI_TRIGGER_EN__SIZE 0x00000001u +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET 0x00000012u +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE 0x00000001u +#define CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET 0x00000013u +#define CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE 0x00000001u +#define CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET 0x0000001fu +#define CYFLD_SAR_EOS_DSI_OUT_EN__SIZE 0x00000001u +#define CYREG_SAR_SAMPLE_TIME01 0x403a0010u +#define CYFLD_SAR_SAMPLE_TIME0__OFFSET 0x00000000u +#define CYFLD_SAR_SAMPLE_TIME0__SIZE 0x0000000au +#define CYFLD_SAR_SAMPLE_TIME1__OFFSET 0x00000010u +#define CYFLD_SAR_SAMPLE_TIME1__SIZE 0x0000000au +#define CYREG_SAR_SAMPLE_TIME23 0x403a0014u +#define CYFLD_SAR_SAMPLE_TIME2__OFFSET 0x00000000u +#define CYFLD_SAR_SAMPLE_TIME2__SIZE 0x0000000au +#define CYFLD_SAR_SAMPLE_TIME3__OFFSET 0x00000010u +#define CYFLD_SAR_SAMPLE_TIME3__SIZE 0x0000000au +#define CYREG_SAR_RANGE_THRES 0x403a0018u +#define CYFLD_SAR_RANGE_LOW__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_LOW__SIZE 0x00000010u +#define CYFLD_SAR_RANGE_HIGH__OFFSET 0x00000010u +#define CYFLD_SAR_RANGE_HIGH__SIZE 0x00000010u +#define CYREG_SAR_RANGE_COND 0x403a001cu +#define CYFLD_SAR_RANGE_COND__OFFSET 0x0000001eu +#define CYFLD_SAR_RANGE_COND__SIZE 0x00000002u +#define CYVAL_SAR_RANGE_COND_BELOW 0x00000000u +#define CYVAL_SAR_RANGE_COND_INSIDE 0x00000001u +#define CYVAL_SAR_RANGE_COND_ABOVE 0x00000002u +#define CYVAL_SAR_RANGE_COND_OUTSIDE 0x00000003u +#define CYREG_SAR_CHAN_EN 0x403a0020u +#define CYFLD_SAR_CHAN_EN__OFFSET 0x00000000u +#define CYFLD_SAR_CHAN_EN__SIZE 0x00000010u +#define CYREG_SAR_START_CTRL 0x403a0024u +#define CYFLD_SAR_FW_TRIGGER__OFFSET 0x00000000u +#define CYFLD_SAR_FW_TRIGGER__SIZE 0x00000001u +#define CYREG_SAR_DFT_CTRL 0x403a0030u +#define CYFLD_SAR_DLY_INC__OFFSET 0x00000000u +#define CYFLD_SAR_DLY_INC__SIZE 0x00000001u +#define CYFLD_SAR_HIZ__OFFSET 0x00000001u +#define CYFLD_SAR_HIZ__SIZE 0x00000001u +#define CYFLD_SAR_DFT_INC__OFFSET 0x00000010u +#define CYFLD_SAR_DFT_INC__SIZE 0x00000004u +#define CYFLD_SAR_DFT_OUTC__OFFSET 0x00000014u +#define CYFLD_SAR_DFT_OUTC__SIZE 0x00000003u +#define CYFLD_SAR_SEL_CSEL_DFT__OFFSET 0x00000018u +#define CYFLD_SAR_SEL_CSEL_DFT__SIZE 0x00000004u +#define CYFLD_SAR_EN_CSEL_DFT__OFFSET 0x0000001cu +#define CYFLD_SAR_EN_CSEL_DFT__SIZE 0x00000001u +#define CYFLD_SAR_DCEN__OFFSET 0x0000001du +#define CYFLD_SAR_DCEN__SIZE 0x00000001u +#define CYFLD_SAR_ADFT_OVERRIDE__OFFSET 0x0000001fu +#define CYFLD_SAR_ADFT_OVERRIDE__SIZE 0x00000001u +#define CYREG_SAR_CHAN_CONFIG0 0x403a0080u +#define CYFLD_SAR_PIN_ADDR__OFFSET 0x00000000u +#define CYFLD_SAR_PIN_ADDR__SIZE 0x00000003u +#define CYFLD_SAR_PORT_ADDR__OFFSET 0x00000004u +#define CYFLD_SAR_PORT_ADDR__SIZE 0x00000003u +#define CYVAL_SAR_PORT_ADDR_SARMUX 0x00000000u +#define CYVAL_SAR_PORT_ADDR_CTB0 0x00000001u +#define CYVAL_SAR_PORT_ADDR_CTB1 0x00000002u +#define CYVAL_SAR_PORT_ADDR_CTB2 0x00000003u +#define CYVAL_SAR_PORT_ADDR_CTB3 0x00000004u +#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT2 0x00000005u +#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT1 0x00000006u +#define CYVAL_SAR_PORT_ADDR_SARMUX_VIRT 0x00000007u +#define CYFLD_SAR_DIFFERENTIAL_EN__OFFSET 0x00000008u +#define CYFLD_SAR_DIFFERENTIAL_EN__SIZE 0x00000001u +#define CYFLD_SAR_RESOLUTION__OFFSET 0x00000009u +#define CYFLD_SAR_RESOLUTION__SIZE 0x00000001u +#define CYVAL_SAR_RESOLUTION_MAXRES 0x00000000u +#define CYVAL_SAR_RESOLUTION_SUBRES 0x00000001u +#define CYFLD_SAR_AVG_EN__OFFSET 0x0000000au +#define CYFLD_SAR_AVG_EN__SIZE 0x00000001u +#define CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET 0x0000000cu +#define CYFLD_SAR_SAMPLE_TIME_SEL__SIZE 0x00000002u +#define CYFLD_SAR_DSI_OUT_EN__OFFSET 0x0000001fu +#define CYFLD_SAR_DSI_OUT_EN__SIZE 0x00000001u +#define CYREG_SAR_CHAN_CONFIG1 0x403a0084u +#define CYREG_SAR_CHAN_CONFIG2 0x403a0088u +#define CYREG_SAR_CHAN_CONFIG3 0x403a008cu +#define CYREG_SAR_CHAN_CONFIG4 0x403a0090u +#define CYREG_SAR_CHAN_CONFIG5 0x403a0094u +#define CYREG_SAR_CHAN_CONFIG6 0x403a0098u +#define CYREG_SAR_CHAN_CONFIG7 0x403a009cu +#define CYREG_SAR_CHAN_CONFIG8 0x403a00a0u +#define CYREG_SAR_CHAN_CONFIG9 0x403a00a4u +#define CYREG_SAR_CHAN_CONFIG10 0x403a00a8u +#define CYREG_SAR_CHAN_CONFIG11 0x403a00acu +#define CYREG_SAR_CHAN_CONFIG12 0x403a00b0u +#define CYREG_SAR_CHAN_CONFIG13 0x403a00b4u +#define CYREG_SAR_CHAN_CONFIG14 0x403a00b8u +#define CYREG_SAR_CHAN_CONFIG15 0x403a00bcu +#define CYREG_SAR_CHAN_WORK0 0x403a0100u +#define CYFLD_SAR_WORK__OFFSET 0x00000000u +#define CYFLD_SAR_WORK__SIZE 0x00000010u +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET 0x0000001fu +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE 0x00000001u +#define CYREG_SAR_CHAN_WORK1 0x403a0104u +#define CYREG_SAR_CHAN_WORK2 0x403a0108u +#define CYREG_SAR_CHAN_WORK3 0x403a010cu +#define CYREG_SAR_CHAN_WORK4 0x403a0110u +#define CYREG_SAR_CHAN_WORK5 0x403a0114u +#define CYREG_SAR_CHAN_WORK6 0x403a0118u +#define CYREG_SAR_CHAN_WORK7 0x403a011cu +#define CYREG_SAR_CHAN_WORK8 0x403a0120u +#define CYREG_SAR_CHAN_WORK9 0x403a0124u +#define CYREG_SAR_CHAN_WORK10 0x403a0128u +#define CYREG_SAR_CHAN_WORK11 0x403a012cu +#define CYREG_SAR_CHAN_WORK12 0x403a0130u +#define CYREG_SAR_CHAN_WORK13 0x403a0134u +#define CYREG_SAR_CHAN_WORK14 0x403a0138u +#define CYREG_SAR_CHAN_WORK15 0x403a013cu +#define CYREG_SAR_CHAN_RESULT0 0x403a0180u +#define CYFLD_SAR_RESULT__OFFSET 0x00000000u +#define CYFLD_SAR_RESULT__SIZE 0x00000010u +#define CYFLD_SAR_SATURATE_INTR_MIR__OFFSET 0x0000001du +#define CYFLD_SAR_SATURATE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_RANGE_INTR_MIR__OFFSET 0x0000001eu +#define CYFLD_SAR_RANGE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET 0x0000001fu +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE 0x00000001u +#define CYREG_SAR_CHAN_RESULT1 0x403a0184u +#define CYREG_SAR_CHAN_RESULT2 0x403a0188u +#define CYREG_SAR_CHAN_RESULT3 0x403a018cu +#define CYREG_SAR_CHAN_RESULT4 0x403a0190u +#define CYREG_SAR_CHAN_RESULT5 0x403a0194u +#define CYREG_SAR_CHAN_RESULT6 0x403a0198u +#define CYREG_SAR_CHAN_RESULT7 0x403a019cu +#define CYREG_SAR_CHAN_RESULT8 0x403a01a0u +#define CYREG_SAR_CHAN_RESULT9 0x403a01a4u +#define CYREG_SAR_CHAN_RESULT10 0x403a01a8u +#define CYREG_SAR_CHAN_RESULT11 0x403a01acu +#define CYREG_SAR_CHAN_RESULT12 0x403a01b0u +#define CYREG_SAR_CHAN_RESULT13 0x403a01b4u +#define CYREG_SAR_CHAN_RESULT14 0x403a01b8u +#define CYREG_SAR_CHAN_RESULT15 0x403a01bcu +#define CYREG_SAR_CHAN_WORK_VALID 0x403a0200u +#define CYFLD_SAR_CHAN_WORK_VALID__OFFSET 0x00000000u +#define CYFLD_SAR_CHAN_WORK_VALID__SIZE 0x00000010u +#define CYREG_SAR_CHAN_RESULT_VALID 0x403a0204u +#define CYFLD_SAR_CHAN_RESULT_VALID__OFFSET 0x00000000u +#define CYFLD_SAR_CHAN_RESULT_VALID__SIZE 0x00000010u +#define CYREG_SAR_STATUS 0x403a0208u +#define CYFLD_SAR_CUR_CHAN__OFFSET 0x00000000u +#define CYFLD_SAR_CUR_CHAN__SIZE 0x00000005u +#define CYFLD_SAR_SW_VREF_NEG__OFFSET 0x0000001eu +#define CYFLD_SAR_SW_VREF_NEG__SIZE 0x00000001u +#define CYFLD_SAR_BUSY__OFFSET 0x0000001fu +#define CYFLD_SAR_BUSY__SIZE 0x00000001u +#define CYREG_SAR_AVG_STAT 0x403a020cu +#define CYFLD_SAR_CUR_AVG_ACCU__OFFSET 0x00000000u +#define CYFLD_SAR_CUR_AVG_ACCU__SIZE 0x00000014u +#define CYFLD_SAR_CUR_AVG_CNT__OFFSET 0x00000018u +#define CYFLD_SAR_CUR_AVG_CNT__SIZE 0x00000008u +#define CYREG_SAR_INTR 0x403a0210u +#define CYFLD_SAR_EOS_INTR__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_INTR__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_INTR__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_INTR__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_INTR__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_INTR__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_INTR__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_INTR__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_INTR__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_INTR__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_INTR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_INTR__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_INTR__SIZE 0x00000001u +#define CYREG_SAR_INTR_SET 0x403a0214u +#define CYFLD_SAR_EOS_SET__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_SET__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_SET__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_SET__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_SET__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_SET__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_SET__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_SET__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_SET__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_SET__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_SET__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_SET__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_SET__SIZE 0x00000001u +#define CYREG_SAR_INTR_MASK 0x403a0218u +#define CYFLD_SAR_EOS_MASK__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_MASK__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASK__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASK__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_MASK__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_MASK__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_MASK__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_MASK__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_MASK__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_MASK__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_MASK__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_MASK__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_MASK__SIZE 0x00000001u +#define CYREG_SAR_INTR_MASKED 0x403a021cu +#define CYFLD_SAR_EOS_MASKED__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_MASKED__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_MASKED__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_MASKED__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_MASKED__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_MASKED__SIZE 0x00000001u +#define CYREG_SAR_SATURATE_INTR 0x403a0220u +#define CYFLD_SAR_SATURATE_INTR__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_INTR__SIZE 0x00000010u +#define CYREG_SAR_SATURATE_INTR_SET 0x403a0224u +#define CYFLD_SAR_SATURATE_SET__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_SET__SIZE 0x00000010u +#define CYREG_SAR_SATURATE_INTR_MASK 0x403a0228u +#define CYFLD_SAR_SATURATE_MASK__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_MASK__SIZE 0x00000010u +#define CYREG_SAR_SATURATE_INTR_MASKED 0x403a022cu +#define CYFLD_SAR_SATURATE_MASKED__OFFSET 0x00000000u +#define CYFLD_SAR_SATURATE_MASKED__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR 0x403a0230u +#define CYFLD_SAR_RANGE_INTR__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_INTR__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR_SET 0x403a0234u +#define CYFLD_SAR_RANGE_SET__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_SET__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR_MASK 0x403a0238u +#define CYFLD_SAR_RANGE_MASK__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_MASK__SIZE 0x00000010u +#define CYREG_SAR_RANGE_INTR_MASKED 0x403a023cu +#define CYFLD_SAR_RANGE_MASKED__OFFSET 0x00000000u +#define CYFLD_SAR_RANGE_MASKED__SIZE 0x00000010u +#define CYREG_SAR_INTR_CAUSE 0x403a0240u +#define CYFLD_SAR_EOS_MASKED_MIR__OFFSET 0x00000000u +#define CYFLD_SAR_EOS_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET 0x00000001u +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET 0x00000002u +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET 0x00000003u +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET 0x00000005u +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET 0x00000006u +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET 0x00000007u +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE 0x00000001u +#define CYFLD_SAR_SATURATE_MASKED_RED__OFFSET 0x0000001eu +#define CYFLD_SAR_SATURATE_MASKED_RED__SIZE 0x00000001u +#define CYFLD_SAR_RANGE_MASKED_RED__OFFSET 0x0000001fu +#define CYFLD_SAR_RANGE_MASKED_RED__SIZE 0x00000001u +#define CYREG_SAR_INJ_CHAN_CONFIG 0x403a0280u +#define CYFLD_SAR_INJ_PIN_ADDR__OFFSET 0x00000000u +#define CYFLD_SAR_INJ_PIN_ADDR__SIZE 0x00000003u +#define CYFLD_SAR_INJ_PORT_ADDR__OFFSET 0x00000004u +#define CYFLD_SAR_INJ_PORT_ADDR__SIZE 0x00000003u +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX 0x00000000u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB0 0x00000001u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB1 0x00000002u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB2 0x00000003u +#define CYVAL_SAR_INJ_PORT_ADDR_CTB3 0x00000004u +#define CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT 0x00000006u +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT 0x00000007u +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET 0x00000008u +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RESOLUTION__OFFSET 0x00000009u +#define CYFLD_SAR_INJ_RESOLUTION__SIZE 0x00000001u +#define CYVAL_SAR_INJ_RESOLUTION_12B 0x00000000u +#define CYVAL_SAR_INJ_RESOLUTION_SUBRES 0x00000001u +#define CYFLD_SAR_INJ_AVG_EN__OFFSET 0x0000000au +#define CYFLD_SAR_INJ_AVG_EN__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET 0x0000000cu +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE 0x00000002u +#define CYFLD_SAR_INJ_TAILGATING__OFFSET 0x0000001eu +#define CYFLD_SAR_INJ_TAILGATING__SIZE 0x00000001u +#define CYFLD_SAR_INJ_START_EN__OFFSET 0x0000001fu +#define CYFLD_SAR_INJ_START_EN__SIZE 0x00000001u +#define CYREG_SAR_INJ_RESULT 0x403a0290u +#define CYFLD_SAR_INJ_RESULT__OFFSET 0x00000000u +#define CYFLD_SAR_INJ_RESULT__SIZE 0x00000010u +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET 0x0000001cu +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET 0x0000001du +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET 0x0000001eu +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE 0x00000001u +#define CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET 0x0000001fu +#define CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH0 0x403a0300u +#define CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET 0x00000000u +#define CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET 0x00000001u +#define CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET 0x00000002u +#define CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET 0x00000003u +#define CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET 0x00000004u +#define CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET 0x00000005u +#define CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET 0x00000006u +#define CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET 0x00000007u +#define CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET 0x00000008u +#define CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET 0x00000009u +#define CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET 0x0000000au +#define CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET 0x0000000bu +#define CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET 0x0000000cu +#define CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET 0x0000000du +#define CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET 0x0000000eu +#define CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET 0x0000000fu +#define CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET 0x00000010u +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET 0x00000011u +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET 0x00000012u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET 0x00000013u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET 0x00000014u +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET 0x00000015u +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET 0x00000016u +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET 0x00000017u +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET 0x00000018u +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET 0x00000019u +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET 0x0000001au +#define CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET 0x0000001bu +#define CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET 0x0000001cu +#define CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET 0x0000001du +#define CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH_CLEAR0 0x403a0304u +#define CYREG_SAR_MUX_SWITCH1 0x403a0308u +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET 0x00000000u +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET 0x00000001u +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET 0x00000002u +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET 0x00000003u +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH_CLEAR1 0x403a030cu +#define CYREG_SAR_MUX_SWITCH_HW_CTRL 0x403a0340u +#define CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET 0x00000000u +#define CYFLD_SAR_MUX_HW_CTRL_P0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P1__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET 0x00000002u +#define CYFLD_SAR_MUX_HW_CTRL_P2__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET 0x00000003u +#define CYFLD_SAR_MUX_HW_CTRL_P3__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET 0x00000004u +#define CYFLD_SAR_MUX_HW_CTRL_P4__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET 0x00000005u +#define CYFLD_SAR_MUX_HW_CTRL_P5__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET 0x00000006u +#define CYFLD_SAR_MUX_HW_CTRL_P6__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET 0x00000007u +#define CYFLD_SAR_MUX_HW_CTRL_P7__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET 0x00000010u +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET 0x00000011u +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET 0x00000012u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET 0x00000013u +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET 0x00000016u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE 0x00000001u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET 0x00000017u +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE 0x00000001u +#define CYREG_SAR_MUX_SWITCH_STATUS 0x403a0348u +#define CYREG_SAR_PUMP_CTRL 0x403a0380u +#define CYFLD_SAR_CLOCK_SEL__OFFSET 0x00000000u +#define CYFLD_SAR_CLOCK_SEL__SIZE 0x00000001u +#define CYREG_SAR_ANA_TRIM 0x403a0f00u +#define CYFLD_SAR_CAP_TRIM__OFFSET 0x00000000u +#define CYFLD_SAR_CAP_TRIM__SIZE 0x00000003u +#define CYFLD_SAR_TRIMUNIT__OFFSET 0x00000003u +#define CYFLD_SAR_TRIMUNIT__SIZE 0x00000001u +#define CYREG_SAR_WOUNDING 0x403a0f04u +#define CYFLD_SAR_WOUND_RESOLUTION__OFFSET 0x00000000u +#define CYFLD_SAR_WOUND_RESOLUTION__SIZE 0x00000002u +#define CYVAL_SAR_WOUND_RESOLUTION_12BIT 0x00000000u +#define CYVAL_SAR_WOUND_RESOLUTION_10BIT 0x00000001u +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT 0x00000002u +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO 0x00000003u +#define CYDEV_PASS_BASE 0x403f0000u +#define CYDEV_PASS_SIZE 0x00010000u +#define CYREG_PASS_INTR_CAUSE 0x403f0000u +#define CYFLD_PASS_CTB0_INT__OFFSET 0x00000000u +#define CYFLD_PASS_CTB0_INT__SIZE 0x00000001u +#define CYREG_PASS_DFT_CTRL 0x403f0030u +#define CYFLD_PASS_DSAB_ADFT_RES_EN__OFFSET 0x00000000u +#define CYFLD_PASS_DSAB_ADFT_RES_EN__SIZE 0x00000001u +#define CYREG_PASS_PASS_CTRL 0x403f0108u +#define CYFLD_PASS_PMPCLK_BYP__OFFSET 0x00000000u +#define CYFLD_PASS_PMPCLK_BYP__SIZE 0x00000001u +#define CYFLD_PASS_PMPCLK_SRC__OFFSET 0x00000001u +#define CYFLD_PASS_PMPCLK_SRC__SIZE 0x00000001u +#define CYFLD_PASS_RMB_BITS__OFFSET 0x00000008u +#define CYFLD_PASS_RMB_BITS__SIZE 0x00000008u +#define CYDEV_PASS_DSAB_BASE 0x403f0e00u +#define CYDEV_PASS_DSAB_SIZE 0x00000100u +#define CYREG_PASS_DSAB_DSAB_CTRL 0x403f0e00u +#define CYFLD_PASS_DSAB_CURRENT_SEL__OFFSET 0x00000000u +#define CYFLD_PASS_DSAB_CURRENT_SEL__SIZE 0x00000006u +#define CYFLD_PASS_DSAB_SEL_OUT__OFFSET 0x00000008u +#define CYFLD_PASS_DSAB_SEL_OUT__SIZE 0x00000004u +#define CYFLD_PASS_DSAB_REF_SWAP_EN__OFFSET 0x00000010u +#define CYFLD_PASS_DSAB_REF_SWAP_EN__SIZE 0x00000004u +#define CYFLD_PASS_DSAB_BYPASS_MODE_EN__OFFSET 0x00000018u +#define CYFLD_PASS_DSAB_BYPASS_MODE_EN__SIZE 0x00000001u +#define CYFLD_PASS_DSAB_STARTUP_RM__OFFSET 0x0000001cu +#define CYFLD_PASS_DSAB_STARTUP_RM__SIZE 0x00000001u +#define CYFLD_PASS_DSAB_ENABLED__OFFSET 0x0000001fu +#define CYFLD_PASS_DSAB_ENABLED__SIZE 0x00000001u +#define CYREG_PASS_DSAB_DSAB_DFT 0x403f0e04u +#define CYFLD_PASS_DSAB_EN_DFT__OFFSET 0x00000000u +#define CYFLD_PASS_DSAB_EN_DFT__SIZE 0x00000004u +#define CYREG_PASS_DSAB_TRIM 0x403f0f00u +#define CYFLD_PASS_IBIAS_TRIM__OFFSET 0x00000000u +#define CYFLD_PASS_IBIAS_TRIM__SIZE 0x00000004u +#define CYFLD_PASS_DSAB_RMB_BITS__OFFSET 0x00000004u +#define CYFLD_PASS_DSAB_RMB_BITS__SIZE 0x00000002u +#define CYDEV_CM0P_BASE 0xe0000000u +#define CYDEV_CM0P_SIZE 0x00100000u +#define CYREG_CM0P_DWT_PID4 0xe0001fd0u +#define CYFLD_CM0P_VALUE__OFFSET 0x00000000u +#define CYFLD_CM0P_VALUE__SIZE 0x00000020u +#define CYREG_CM0P_DWT_PID0 0xe0001fe0u +#define CYREG_CM0P_DWT_PID1 0xe0001fe4u +#define CYREG_CM0P_DWT_PID2 0xe0001fe8u +#define CYREG_CM0P_DWT_PID3 0xe0001fecu +#define CYREG_CM0P_DWT_CID0 0xe0001ff0u +#define CYREG_CM0P_DWT_CID1 0xe0001ff4u +#define CYREG_CM0P_DWT_CID2 0xe0001ff8u +#define CYREG_CM0P_DWT_CID3 0xe0001ffcu +#define CYREG_CM0P_BP_PID4 0xe0002fd0u +#define CYREG_CM0P_BP_PID0 0xe0002fe0u +#define CYREG_CM0P_BP_PID1 0xe0002fe4u +#define CYREG_CM0P_BP_PID2 0xe0002fe8u +#define CYREG_CM0P_BP_PID3 0xe0002fecu +#define CYREG_CM0P_BP_CID0 0xe0002ff0u +#define CYREG_CM0P_BP_CID1 0xe0002ff4u +#define CYREG_CM0P_BP_CID2 0xe0002ff8u +#define CYREG_CM0P_BP_CID3 0xe0002ffcu +#define CYREG_CM0P_SYST_CSR 0xe000e010u +#define CYFLD_CM0P_ENABLE__OFFSET 0x00000000u +#define CYFLD_CM0P_ENABLE__SIZE 0x00000001u +#define CYFLD_CM0P_TICKINT__OFFSET 0x00000001u +#define CYFLD_CM0P_TICKINT__SIZE 0x00000001u +#define CYFLD_CM0P_CLKSOURCE__OFFSET 0x00000002u +#define CYFLD_CM0P_CLKSOURCE__SIZE 0x00000001u +#define CYFLD_CM0P_COUNTFLAG__OFFSET 0x00000010u +#define CYFLD_CM0P_COUNTFLAG__SIZE 0x00000001u +#define CYREG_CM0P_SYST_RVR 0xe000e014u +#define CYFLD_CM0P_RELOAD__OFFSET 0x00000000u +#define CYFLD_CM0P_RELOAD__SIZE 0x00000018u +#define CYREG_CM0P_SYST_CVR 0xe000e018u +#define CYFLD_CM0P_CURRENT__OFFSET 0x00000000u +#define CYFLD_CM0P_CURRENT__SIZE 0x00000018u +#define CYREG_CM0P_SYST_CALIB 0xe000e01cu +#define CYFLD_CM0P_TENMS__OFFSET 0x00000000u +#define CYFLD_CM0P_TENMS__SIZE 0x00000018u +#define CYFLD_CM0P_SKEW__OFFSET 0x0000001eu +#define CYFLD_CM0P_SKEW__SIZE 0x00000001u +#define CYFLD_CM0P_NOREF__OFFSET 0x0000001fu +#define CYFLD_CM0P_NOREF__SIZE 0x00000001u +#define CYREG_CM0P_ISER 0xe000e100u +#define CYFLD_CM0P_SETENA__OFFSET 0x00000000u +#define CYFLD_CM0P_SETENA__SIZE 0x00000020u +#define CYREG_CM0P_ICER 0xe000e180u +#define CYFLD_CM0P_CLRENA__OFFSET 0x00000000u +#define CYFLD_CM0P_CLRENA__SIZE 0x00000020u +#define CYREG_CM0P_ISPR 0xe000e200u +#define CYFLD_CM0P_SETPEND__OFFSET 0x00000000u +#define CYFLD_CM0P_SETPEND__SIZE 0x00000020u +#define CYREG_CM0P_ICPR 0xe000e280u +#define CYFLD_CM0P_CLRPEND__OFFSET 0x00000000u +#define CYFLD_CM0P_CLRPEND__SIZE 0x00000020u +#define CYREG_CM0P_IPR0 0xe000e400u +#define CYFLD_CM0P_PRI_N0__OFFSET 0x00000006u +#define CYFLD_CM0P_PRI_N0__SIZE 0x00000002u +#define CYFLD_CM0P_PRI_N1__OFFSET 0x0000000eu +#define CYFLD_CM0P_PRI_N1__SIZE 0x00000002u +#define CYFLD_CM0P_PRI_N2__OFFSET 0x00000016u +#define CYFLD_CM0P_PRI_N2__SIZE 0x00000002u +#define CYFLD_CM0P_PRI_N3__OFFSET 0x0000001eu +#define CYFLD_CM0P_PRI_N3__SIZE 0x00000002u +#define CYREG_CM0P_IPR1 0xe000e404u +#define CYREG_CM0P_IPR2 0xe000e408u +#define CYREG_CM0P_IPR3 0xe000e40cu +#define CYREG_CM0P_IPR4 0xe000e410u +#define CYREG_CM0P_IPR5 0xe000e414u +#define CYREG_CM0P_IPR6 0xe000e418u +#define CYREG_CM0P_IPR7 0xe000e41cu +#define CYREG_CM0P_CPUID 0xe000ed00u +#define CYFLD_CM0P_REVISION__OFFSET 0x00000000u +#define CYFLD_CM0P_REVISION__SIZE 0x00000004u +#define CYFLD_CM0P_PARTNO__OFFSET 0x00000004u +#define CYFLD_CM0P_PARTNO__SIZE 0x0000000cu +#define CYFLD_CM0P_CONSTANT__OFFSET 0x00000010u +#define CYFLD_CM0P_CONSTANT__SIZE 0x00000004u +#define CYFLD_CM0P_VARIANT__OFFSET 0x00000014u +#define CYFLD_CM0P_VARIANT__SIZE 0x00000004u +#define CYFLD_CM0P_IMPLEMENTER__OFFSET 0x00000018u +#define CYFLD_CM0P_IMPLEMENTER__SIZE 0x00000008u +#define CYREG_CM0P_ICSR 0xe000ed04u +#define CYFLD_CM0P_VECTACTIVE__OFFSET 0x00000000u +#define CYFLD_CM0P_VECTACTIVE__SIZE 0x00000009u +#define CYFLD_CM0P_VECTPENDING__OFFSET 0x0000000cu +#define CYFLD_CM0P_VECTPENDING__SIZE 0x00000009u +#define CYFLD_CM0P_ISRPENDING__OFFSET 0x00000016u +#define CYFLD_CM0P_ISRPENDING__SIZE 0x00000001u +#define CYFLD_CM0P_ISRPREEMPT__OFFSET 0x00000017u +#define CYFLD_CM0P_ISRPREEMPT__SIZE 0x00000001u +#define CYFLD_CM0P_PENDSTCLR__OFFSET 0x00000019u +#define CYFLD_CM0P_PENDSTCLR__SIZE 0x00000001u +#define CYFLD_CM0P_PENDSTSETb__OFFSET 0x0000001au +#define CYFLD_CM0P_PENDSTSETb__SIZE 0x00000001u +#define CYFLD_CM0P_PENDSVCLR__OFFSET 0x0000001bu +#define CYFLD_CM0P_PENDSVCLR__SIZE 0x00000001u +#define CYFLD_CM0P_PENDSVSET__OFFSET 0x0000001cu +#define CYFLD_CM0P_PENDSVSET__SIZE 0x00000001u +#define CYFLD_CM0P_NMIPENDSET__OFFSET 0x0000001fu +#define CYFLD_CM0P_NMIPENDSET__SIZE 0x00000001u +#define CYREG_CM0P_VTOR 0xe000ed08u +#define CYFLD_CM0P_TBLOFF__OFFSET 0x00000008u +#define CYFLD_CM0P_TBLOFF__SIZE 0x00000018u +#define CYREG_CM0P_AIRCR 0xe000ed0cu +#define CYFLD_CM0P_VECTCLRACTIVE__OFFSET 0x00000001u +#define CYFLD_CM0P_VECTCLRACTIVE__SIZE 0x00000001u +#define CYFLD_CM0P_SYSRESETREQ__OFFSET 0x00000002u +#define CYFLD_CM0P_SYSRESETREQ__SIZE 0x00000001u +#define CYFLD_CM0P_ENDIANNESS__OFFSET 0x0000000fu +#define CYFLD_CM0P_ENDIANNESS__SIZE 0x00000001u +#define CYFLD_CM0P_VECTKEY__OFFSET 0x00000010u +#define CYFLD_CM0P_VECTKEY__SIZE 0x00000010u +#define CYREG_CM0P_SCR 0xe000ed10u +#define CYFLD_CM0P_SLEEPONEXIT__OFFSET 0x00000001u +#define CYFLD_CM0P_SLEEPONEXIT__SIZE 0x00000001u +#define CYFLD_CM0P_SLEEPDEEP__OFFSET 0x00000002u +#define CYFLD_CM0P_SLEEPDEEP__SIZE 0x00000001u +#define CYFLD_CM0P_SEVONPEND__OFFSET 0x00000004u +#define CYFLD_CM0P_SEVONPEND__SIZE 0x00000001u +#define CYREG_CM0P_CCR 0xe000ed14u +#define CYFLD_CM0P_UNALIGN_TRP__OFFSET 0x00000003u +#define CYFLD_CM0P_UNALIGN_TRP__SIZE 0x00000001u +#define CYFLD_CM0P_STKALIGN__OFFSET 0x00000009u +#define CYFLD_CM0P_STKALIGN__SIZE 0x00000001u +#define CYREG_CM0P_SHPR2 0xe000ed1cu +#define CYFLD_CM0P_PRI_11__OFFSET 0x0000001eu +#define CYFLD_CM0P_PRI_11__SIZE 0x00000002u +#define CYREG_CM0P_SHPR3 0xe000ed20u +#define CYFLD_CM0P_PRI_14__OFFSET 0x00000016u +#define CYFLD_CM0P_PRI_14__SIZE 0x00000002u +#define CYFLD_CM0P_PRI_15__OFFSET 0x0000001eu +#define CYFLD_CM0P_PRI_15__SIZE 0x00000002u +#define CYREG_CM0P_SHCSR 0xe000ed24u +#define CYFLD_CM0P_SVCALLPENDED__OFFSET 0x0000000fu +#define CYFLD_CM0P_SVCALLPENDED__SIZE 0x00000001u +#define CYREG_CM0P_SCS_PID4 0xe000efd0u +#define CYREG_CM0P_SCS_PID0 0xe000efe0u +#define CYREG_CM0P_SCS_PID1 0xe000efe4u +#define CYREG_CM0P_SCS_PID2 0xe000efe8u +#define CYREG_CM0P_SCS_PID3 0xe000efecu +#define CYREG_CM0P_SCS_CID0 0xe000eff0u +#define CYREG_CM0P_SCS_CID1 0xe000eff4u +#define CYREG_CM0P_SCS_CID2 0xe000eff8u +#define CYREG_CM0P_SCS_CID3 0xe000effcu +#define CYREG_CM0P_ROM_SCS 0xe00ff000u +#define CYREG_CM0P_ROM_DWT 0xe00ff004u +#define CYREG_CM0P_ROM_BPU 0xe00ff008u +#define CYREG_CM0P_ROM_END 0xe00ff00cu +#define CYREG_CM0P_ROM_CSMT 0xe00fffccu +#define CYREG_CM0P_ROM_PID4 0xe00fffd0u +#define CYREG_CM0P_ROM_PID0 0xe00fffe0u +#define CYREG_CM0P_ROM_PID1 0xe00fffe4u +#define CYREG_CM0P_ROM_PID2 0xe00fffe8u +#define CYREG_CM0P_ROM_PID3 0xe00fffecu +#define CYREG_CM0P_ROM_CID0 0xe00ffff0u +#define CYREG_CM0P_ROM_CID1 0xe00ffff4u +#define CYREG_CM0P_ROM_CID2 0xe00ffff8u +#define CYREG_CM0P_ROM_CID3 0xe00ffffcu +#define CYDEV_ROMTABLE_BASE 0xf0000000u +#define CYDEV_ROMTABLE_SIZE 0x00001000u +#define CYREG_ROMTABLE_ADDR 0xf0000000u +#define CYFLD_ROMTABLE_PRESENT__OFFSET 0x00000000u +#define CYFLD_ROMTABLE_PRESENT__SIZE 0x00000001u +#define CYFLD_ROMTABLE_FORMAT_32BIT__OFFSET 0x00000001u +#define CYFLD_ROMTABLE_FORMAT_32BIT__SIZE 0x00000001u +#define CYFLD_ROMTABLE_ADDR_OFFSET__OFFSET 0x0000000cu +#define CYFLD_ROMTABLE_ADDR_OFFSET__SIZE 0x00000014u +#define CYREG_ROMTABLE_DID 0xf0000fccu +#define CYFLD_ROMTABLE_VALUE__OFFSET 0x00000000u +#define CYFLD_ROMTABLE_VALUE__SIZE 0x00000020u +#define CYREG_ROMTABLE_PID4 0xf0000fd0u +#define CYFLD_ROMTABLE_JEP_CONTINUATION__OFFSET 0x00000000u +#define CYFLD_ROMTABLE_JEP_CONTINUATION__SIZE 0x00000004u +#define CYFLD_ROMTABLE_COUNT__OFFSET 0x00000004u +#define CYFLD_ROMTABLE_COUNT__SIZE 0x00000004u +#define CYREG_ROMTABLE_PID5 0xf0000fd4u +#define CYREG_ROMTABLE_PID6 0xf0000fd8u +#define CYREG_ROMTABLE_PID7 0xf0000fdcu +#define CYREG_ROMTABLE_PID0 0xf0000fe0u +#define CYFLD_ROMTABLE_PN_MIN__OFFSET 0x00000000u +#define CYFLD_ROMTABLE_PN_MIN__SIZE 0x00000008u +#define CYREG_ROMTABLE_PID1 0xf0000fe4u +#define CYFLD_ROMTABLE_PN_MAJ__OFFSET 0x00000000u +#define CYFLD_ROMTABLE_PN_MAJ__SIZE 0x00000004u +#define CYFLD_ROMTABLE_JEPID_MIN__OFFSET 0x00000004u +#define CYFLD_ROMTABLE_JEPID_MIN__SIZE 0x00000004u +#define CYREG_ROMTABLE_PID2 0xf0000fe8u +#define CYFLD_ROMTABLE_JEPID_MAJ__OFFSET 0x00000000u +#define CYFLD_ROMTABLE_JEPID_MAJ__SIZE 0x00000003u +#define CYFLD_ROMTABLE_REV__OFFSET 0x00000004u +#define CYFLD_ROMTABLE_REV__SIZE 0x00000004u +#define CYREG_ROMTABLE_PID3 0xf0000fecu +#define CYFLD_ROMTABLE_CM__OFFSET 0x00000000u +#define CYFLD_ROMTABLE_CM__SIZE 0x00000004u +#define CYFLD_ROMTABLE_REV_AND__OFFSET 0x00000004u +#define CYFLD_ROMTABLE_REV_AND__SIZE 0x00000004u +#define CYREG_ROMTABLE_CID0 0xf0000ff0u +#define CYREG_ROMTABLE_CID1 0xf0000ff4u +#define CYREG_ROMTABLE_CID2 0xf0000ff8u +#define CYREG_ROMTABLE_CID3 0xf0000ffcu +#define CYDEV_FLS_SECTOR_SIZE 0x00020000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#endif /* CYDEVICE_TRM_H */ diff --git a/cores/asr650x/projects/PSoC4/cydevicegnu_trm.inc b/cores/asr650x/projects/PSoC4/cydevicegnu_trm.inc new file mode 100644 index 00000000..bed290f8 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cydevicegnu_trm.inc @@ -0,0 +1,5491 @@ +/******************************************************************************* +* File Name: cydevicegnu_trm.inc +* +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00020000 +.set CYREG_FLASH_DATA_MBASE, 0x00000000 +.set CYREG_FLASH_DATA_MSIZE, 0x00020000 +.set CYDEV_SFLASH_BASE, 0x0ffff000 +.set CYDEV_SFLASH_SIZE, 0x00000800 +.set CYREG_SFLASH_PROT_ROW0, 0x0ffff000 +.set CYFLD_SFLASH_DATA8__OFFSET, 0x00000000 +.set CYFLD_SFLASH_DATA8__SIZE, 0x00000008 +.set CYREG_SFLASH_PROT_ROW1, 0x0ffff001 +.set CYREG_SFLASH_PROT_ROW2, 0x0ffff002 +.set CYREG_SFLASH_PROT_ROW3, 0x0ffff003 +.set CYREG_SFLASH_PROT_ROW4, 0x0ffff004 +.set CYREG_SFLASH_PROT_ROW5, 0x0ffff005 +.set CYREG_SFLASH_PROT_ROW6, 0x0ffff006 +.set CYREG_SFLASH_PROT_ROW7, 0x0ffff007 +.set CYREG_SFLASH_PROT_ROW8, 0x0ffff008 +.set CYREG_SFLASH_PROT_ROW9, 0x0ffff009 +.set CYREG_SFLASH_PROT_ROW10, 0x0ffff00a +.set CYREG_SFLASH_PROT_ROW11, 0x0ffff00b +.set CYREG_SFLASH_PROT_ROW12, 0x0ffff00c +.set CYREG_SFLASH_PROT_ROW13, 0x0ffff00d +.set CYREG_SFLASH_PROT_ROW14, 0x0ffff00e +.set CYREG_SFLASH_PROT_ROW15, 0x0ffff00f +.set CYREG_SFLASH_PROT_ROW16, 0x0ffff010 +.set CYREG_SFLASH_PROT_ROW17, 0x0ffff011 +.set CYREG_SFLASH_PROT_ROW18, 0x0ffff012 +.set CYREG_SFLASH_PROT_ROW19, 0x0ffff013 +.set CYREG_SFLASH_PROT_ROW20, 0x0ffff014 +.set CYREG_SFLASH_PROT_ROW21, 0x0ffff015 +.set CYREG_SFLASH_PROT_ROW22, 0x0ffff016 +.set CYREG_SFLASH_PROT_ROW23, 0x0ffff017 +.set CYREG_SFLASH_PROT_ROW24, 0x0ffff018 +.set CYREG_SFLASH_PROT_ROW25, 0x0ffff019 +.set CYREG_SFLASH_PROT_ROW26, 0x0ffff01a +.set CYREG_SFLASH_PROT_ROW27, 0x0ffff01b +.set CYREG_SFLASH_PROT_ROW28, 0x0ffff01c +.set CYREG_SFLASH_PROT_ROW29, 0x0ffff01d +.set CYREG_SFLASH_PROT_ROW30, 0x0ffff01e +.set CYREG_SFLASH_PROT_ROW31, 0x0ffff01f +.set CYREG_SFLASH_PROT_ROW32, 0x0ffff020 +.set CYREG_SFLASH_PROT_ROW33, 0x0ffff021 +.set CYREG_SFLASH_PROT_ROW34, 0x0ffff022 +.set CYREG_SFLASH_PROT_ROW35, 0x0ffff023 +.set CYREG_SFLASH_PROT_ROW36, 0x0ffff024 +.set CYREG_SFLASH_PROT_ROW37, 0x0ffff025 +.set CYREG_SFLASH_PROT_ROW38, 0x0ffff026 +.set CYREG_SFLASH_PROT_ROW39, 0x0ffff027 +.set CYREG_SFLASH_PROT_ROW40, 0x0ffff028 +.set CYREG_SFLASH_PROT_ROW41, 0x0ffff029 +.set CYREG_SFLASH_PROT_ROW42, 0x0ffff02a +.set CYREG_SFLASH_PROT_ROW43, 0x0ffff02b +.set CYREG_SFLASH_PROT_ROW44, 0x0ffff02c +.set CYREG_SFLASH_PROT_ROW45, 0x0ffff02d +.set CYREG_SFLASH_PROT_ROW46, 0x0ffff02e +.set CYREG_SFLASH_PROT_ROW47, 0x0ffff02f +.set CYREG_SFLASH_PROT_ROW48, 0x0ffff030 +.set CYREG_SFLASH_PROT_ROW49, 0x0ffff031 +.set CYREG_SFLASH_PROT_ROW50, 0x0ffff032 +.set CYREG_SFLASH_PROT_ROW51, 0x0ffff033 +.set CYREG_SFLASH_PROT_ROW52, 0x0ffff034 +.set CYREG_SFLASH_PROT_ROW53, 0x0ffff035 +.set CYREG_SFLASH_PROT_ROW54, 0x0ffff036 +.set CYREG_SFLASH_PROT_ROW55, 0x0ffff037 +.set CYREG_SFLASH_PROT_ROW56, 0x0ffff038 +.set CYREG_SFLASH_PROT_ROW57, 0x0ffff039 +.set CYREG_SFLASH_PROT_ROW58, 0x0ffff03a +.set CYREG_SFLASH_PROT_ROW59, 0x0ffff03b +.set CYREG_SFLASH_PROT_ROW60, 0x0ffff03c +.set CYREG_SFLASH_PROT_ROW61, 0x0ffff03d +.set CYREG_SFLASH_PROT_ROW62, 0x0ffff03e +.set CYREG_SFLASH_PROT_ROW63, 0x0ffff03f +.set CYREG_SFLASH_PROT_PROTECTION, 0x0ffff0ff +.set CYFLD_SFLASH_PROT_LEVEL__OFFSET, 0x00000000 +.set CYFLD_SFLASH_PROT_LEVEL__SIZE, 0x00000002 +.set CYVAL_SFLASH_PROT_LEVEL_VIRGIN, 0x00000001 +.set CYVAL_SFLASH_PROT_LEVEL_OPEN, 0x00000000 +.set CYVAL_SFLASH_PROT_LEVEL_PROTECTED, 0x00000002 +.set CYVAL_SFLASH_PROT_LEVEL_KILL, 0x00000003 +.set CYREG_SFLASH_AV_PAIRS_8B0, 0x0ffff100 +.set CYREG_SFLASH_AV_PAIRS_8B1, 0x0ffff101 +.set CYREG_SFLASH_AV_PAIRS_8B2, 0x0ffff102 +.set CYREG_SFLASH_AV_PAIRS_8B3, 0x0ffff103 +.set CYREG_SFLASH_AV_PAIRS_8B4, 0x0ffff104 +.set CYREG_SFLASH_AV_PAIRS_8B5, 0x0ffff105 +.set CYREG_SFLASH_AV_PAIRS_8B6, 0x0ffff106 +.set CYREG_SFLASH_AV_PAIRS_8B7, 0x0ffff107 +.set CYREG_SFLASH_AV_PAIRS_8B8, 0x0ffff108 +.set CYREG_SFLASH_AV_PAIRS_8B9, 0x0ffff109 +.set CYREG_SFLASH_AV_PAIRS_8B10, 0x0ffff10a +.set CYREG_SFLASH_AV_PAIRS_8B11, 0x0ffff10b +.set CYREG_SFLASH_AV_PAIRS_8B12, 0x0ffff10c +.set CYREG_SFLASH_AV_PAIRS_8B13, 0x0ffff10d +.set CYREG_SFLASH_AV_PAIRS_8B14, 0x0ffff10e +.set CYREG_SFLASH_AV_PAIRS_8B15, 0x0ffff10f +.set CYREG_SFLASH_AV_PAIRS_8B16, 0x0ffff110 +.set CYREG_SFLASH_AV_PAIRS_8B17, 0x0ffff111 +.set CYREG_SFLASH_AV_PAIRS_8B18, 0x0ffff112 +.set CYREG_SFLASH_AV_PAIRS_8B19, 0x0ffff113 +.set CYREG_SFLASH_AV_PAIRS_8B20, 0x0ffff114 +.set CYREG_SFLASH_AV_PAIRS_8B21, 0x0ffff115 +.set CYREG_SFLASH_AV_PAIRS_8B22, 0x0ffff116 +.set CYREG_SFLASH_AV_PAIRS_8B23, 0x0ffff117 +.set CYREG_SFLASH_AV_PAIRS_8B24, 0x0ffff118 +.set CYREG_SFLASH_AV_PAIRS_8B25, 0x0ffff119 +.set CYREG_SFLASH_AV_PAIRS_8B26, 0x0ffff11a +.set CYREG_SFLASH_AV_PAIRS_8B27, 0x0ffff11b +.set CYREG_SFLASH_AV_PAIRS_8B28, 0x0ffff11c +.set CYREG_SFLASH_AV_PAIRS_8B29, 0x0ffff11d +.set CYREG_SFLASH_AV_PAIRS_8B30, 0x0ffff11e +.set CYREG_SFLASH_AV_PAIRS_8B31, 0x0ffff11f +.set CYREG_SFLASH_AV_PAIRS_8B32, 0x0ffff120 +.set CYREG_SFLASH_AV_PAIRS_8B33, 0x0ffff121 +.set CYREG_SFLASH_AV_PAIRS_8B34, 0x0ffff122 +.set CYREG_SFLASH_AV_PAIRS_8B35, 0x0ffff123 +.set CYREG_SFLASH_AV_PAIRS_8B36, 0x0ffff124 +.set CYREG_SFLASH_AV_PAIRS_8B37, 0x0ffff125 +.set CYREG_SFLASH_AV_PAIRS_8B38, 0x0ffff126 +.set CYREG_SFLASH_AV_PAIRS_8B39, 0x0ffff127 +.set CYREG_SFLASH_AV_PAIRS_8B40, 0x0ffff128 +.set CYREG_SFLASH_AV_PAIRS_8B41, 0x0ffff129 +.set CYREG_SFLASH_AV_PAIRS_8B42, 0x0ffff12a +.set CYREG_SFLASH_AV_PAIRS_8B43, 0x0ffff12b +.set CYREG_SFLASH_AV_PAIRS_8B44, 0x0ffff12c +.set CYREG_SFLASH_AV_PAIRS_8B45, 0x0ffff12d +.set CYREG_SFLASH_AV_PAIRS_8B46, 0x0ffff12e +.set CYREG_SFLASH_AV_PAIRS_8B47, 0x0ffff12f +.set CYREG_SFLASH_AV_PAIRS_8B48, 0x0ffff130 +.set CYREG_SFLASH_AV_PAIRS_8B49, 0x0ffff131 +.set CYREG_SFLASH_AV_PAIRS_8B50, 0x0ffff132 +.set CYREG_SFLASH_AV_PAIRS_8B51, 0x0ffff133 +.set CYREG_SFLASH_AV_PAIRS_8B52, 0x0ffff134 +.set CYREG_SFLASH_AV_PAIRS_8B53, 0x0ffff135 +.set CYREG_SFLASH_AV_PAIRS_8B54, 0x0ffff136 +.set CYREG_SFLASH_AV_PAIRS_8B55, 0x0ffff137 +.set CYREG_SFLASH_AV_PAIRS_8B56, 0x0ffff138 +.set CYREG_SFLASH_AV_PAIRS_8B57, 0x0ffff139 +.set CYREG_SFLASH_AV_PAIRS_8B58, 0x0ffff13a +.set CYREG_SFLASH_AV_PAIRS_8B59, 0x0ffff13b +.set CYREG_SFLASH_AV_PAIRS_8B60, 0x0ffff13c +.set CYREG_SFLASH_AV_PAIRS_8B61, 0x0ffff13d +.set CYREG_SFLASH_AV_PAIRS_8B62, 0x0ffff13e +.set CYREG_SFLASH_AV_PAIRS_8B63, 0x0ffff13f +.set CYREG_SFLASH_AV_PAIRS_8B64, 0x0ffff140 +.set CYREG_SFLASH_AV_PAIRS_8B65, 0x0ffff141 +.set CYREG_SFLASH_AV_PAIRS_8B66, 0x0ffff142 +.set CYREG_SFLASH_AV_PAIRS_8B67, 0x0ffff143 +.set CYREG_SFLASH_AV_PAIRS_8B68, 0x0ffff144 +.set CYREG_SFLASH_AV_PAIRS_8B69, 0x0ffff145 +.set CYREG_SFLASH_AV_PAIRS_8B70, 0x0ffff146 +.set CYREG_SFLASH_AV_PAIRS_8B71, 0x0ffff147 +.set CYREG_SFLASH_AV_PAIRS_8B72, 0x0ffff148 +.set CYREG_SFLASH_AV_PAIRS_8B73, 0x0ffff149 +.set CYREG_SFLASH_AV_PAIRS_8B74, 0x0ffff14a +.set CYREG_SFLASH_AV_PAIRS_8B75, 0x0ffff14b +.set CYREG_SFLASH_AV_PAIRS_8B76, 0x0ffff14c +.set CYREG_SFLASH_AV_PAIRS_8B77, 0x0ffff14d +.set CYREG_SFLASH_AV_PAIRS_8B78, 0x0ffff14e +.set CYREG_SFLASH_AV_PAIRS_8B79, 0x0ffff14f +.set CYREG_SFLASH_AV_PAIRS_8B80, 0x0ffff150 +.set CYREG_SFLASH_AV_PAIRS_8B81, 0x0ffff151 +.set CYREG_SFLASH_AV_PAIRS_8B82, 0x0ffff152 +.set CYREG_SFLASH_AV_PAIRS_8B83, 0x0ffff153 +.set CYREG_SFLASH_AV_PAIRS_8B84, 0x0ffff154 +.set CYREG_SFLASH_AV_PAIRS_8B85, 0x0ffff155 +.set CYREG_SFLASH_AV_PAIRS_8B86, 0x0ffff156 +.set CYREG_SFLASH_AV_PAIRS_8B87, 0x0ffff157 +.set CYREG_SFLASH_AV_PAIRS_8B88, 0x0ffff158 +.set CYREG_SFLASH_AV_PAIRS_8B89, 0x0ffff159 +.set CYREG_SFLASH_AV_PAIRS_8B90, 0x0ffff15a +.set CYREG_SFLASH_AV_PAIRS_8B91, 0x0ffff15b +.set CYREG_SFLASH_AV_PAIRS_8B92, 0x0ffff15c +.set CYREG_SFLASH_AV_PAIRS_8B93, 0x0ffff15d +.set CYREG_SFLASH_AV_PAIRS_8B94, 0x0ffff15e +.set CYREG_SFLASH_AV_PAIRS_8B95, 0x0ffff15f +.set CYREG_SFLASH_AV_PAIRS_8B96, 0x0ffff160 +.set CYREG_SFLASH_AV_PAIRS_8B97, 0x0ffff161 +.set CYREG_SFLASH_AV_PAIRS_8B98, 0x0ffff162 +.set CYREG_SFLASH_AV_PAIRS_8B99, 0x0ffff163 +.set CYREG_SFLASH_AV_PAIRS_8B100, 0x0ffff164 +.set CYREG_SFLASH_AV_PAIRS_8B101, 0x0ffff165 +.set CYREG_SFLASH_AV_PAIRS_8B102, 0x0ffff166 +.set CYREG_SFLASH_AV_PAIRS_8B103, 0x0ffff167 +.set CYREG_SFLASH_AV_PAIRS_8B104, 0x0ffff168 +.set CYREG_SFLASH_AV_PAIRS_8B105, 0x0ffff169 +.set CYREG_SFLASH_AV_PAIRS_8B106, 0x0ffff16a +.set CYREG_SFLASH_AV_PAIRS_8B107, 0x0ffff16b +.set CYREG_SFLASH_AV_PAIRS_8B108, 0x0ffff16c +.set CYREG_SFLASH_AV_PAIRS_8B109, 0x0ffff16d +.set CYREG_SFLASH_AV_PAIRS_8B110, 0x0ffff16e +.set CYREG_SFLASH_AV_PAIRS_8B111, 0x0ffff16f +.set CYREG_SFLASH_AV_PAIRS_8B112, 0x0ffff170 +.set CYREG_SFLASH_AV_PAIRS_8B113, 0x0ffff171 +.set CYREG_SFLASH_AV_PAIRS_8B114, 0x0ffff172 +.set CYREG_SFLASH_AV_PAIRS_8B115, 0x0ffff173 +.set CYREG_SFLASH_AV_PAIRS_8B116, 0x0ffff174 +.set CYREG_SFLASH_AV_PAIRS_8B117, 0x0ffff175 +.set CYREG_SFLASH_AV_PAIRS_8B118, 0x0ffff176 +.set CYREG_SFLASH_AV_PAIRS_8B119, 0x0ffff177 +.set CYREG_SFLASH_AV_PAIRS_8B120, 0x0ffff178 +.set CYREG_SFLASH_AV_PAIRS_8B121, 0x0ffff179 +.set CYREG_SFLASH_AV_PAIRS_8B122, 0x0ffff17a +.set CYREG_SFLASH_AV_PAIRS_8B123, 0x0ffff17b +.set CYREG_SFLASH_AV_PAIRS_8B124, 0x0ffff17c +.set CYREG_SFLASH_AV_PAIRS_8B125, 0x0ffff17d +.set CYREG_SFLASH_AV_PAIRS_8B126, 0x0ffff17e +.set CYREG_SFLASH_AV_PAIRS_8B127, 0x0ffff17f +.set CYREG_SFLASH_AV_PAIRS_32B0, 0x0ffff200 +.set CYFLD_SFLASH_DATA32__OFFSET, 0x00000000 +.set CYFLD_SFLASH_DATA32__SIZE, 0x00000020 +.set CYREG_SFLASH_AV_PAIRS_32B1, 0x0ffff204 +.set CYREG_SFLASH_AV_PAIRS_32B2, 0x0ffff208 +.set CYREG_SFLASH_AV_PAIRS_32B3, 0x0ffff20c +.set CYREG_SFLASH_AV_PAIRS_32B4, 0x0ffff210 +.set CYREG_SFLASH_AV_PAIRS_32B5, 0x0ffff214 +.set CYREG_SFLASH_AV_PAIRS_32B6, 0x0ffff218 +.set CYREG_SFLASH_AV_PAIRS_32B7, 0x0ffff21c +.set CYREG_SFLASH_AV_PAIRS_32B8, 0x0ffff220 +.set CYREG_SFLASH_AV_PAIRS_32B9, 0x0ffff224 +.set CYREG_SFLASH_AV_PAIRS_32B10, 0x0ffff228 +.set CYREG_SFLASH_AV_PAIRS_32B11, 0x0ffff22c +.set CYREG_SFLASH_AV_PAIRS_32B12, 0x0ffff230 +.set CYREG_SFLASH_AV_PAIRS_32B13, 0x0ffff234 +.set CYREG_SFLASH_AV_PAIRS_32B14, 0x0ffff238 +.set CYREG_SFLASH_AV_PAIRS_32B15, 0x0ffff23c +.set CYREG_SFLASH_SILICON_ID, 0x0ffff244 +.set CYFLD_SFLASH_ID__OFFSET, 0x00000000 +.set CYFLD_SFLASH_ID__SIZE, 0x00000010 +.set CYREG_SFLASH_HIB_KEY_DELAY, 0x0ffff250 +.set CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET, 0x00000000 +.set CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE, 0x0000000a +.set CYREG_SFLASH_DPSLP_KEY_DELAY, 0x0ffff252 +.set CYREG_SFLASH_SWD_CONFIG, 0x0ffff254 +.set CYFLD_SFLASH_SWD_SELECT__OFFSET, 0x00000000 +.set CYFLD_SFLASH_SWD_SELECT__SIZE, 0x00000001 +.set CYREG_SFLASH_SWD_LISTEN, 0x0ffff258 +.set CYFLD_SFLASH_CYCLES__OFFSET, 0x00000000 +.set CYFLD_SFLASH_CYCLES__SIZE, 0x00000020 +.set CYREG_SFLASH_FLASH_START, 0x0ffff25c +.set CYFLD_SFLASH_ADDRESS__OFFSET, 0x00000000 +.set CYFLD_SFLASH_ADDRESS__SIZE, 0x00000020 +.set CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM1, 0x0ffff260 +.set CYFLD_SFLASH_CSD_ADC_CAL_LSB__OFFSET, 0x00000000 +.set CYFLD_SFLASH_CSD_ADC_CAL_LSB__SIZE, 0x00000008 +.set CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM2, 0x0ffff261 +.set CYFLD_SFLASH_CSD_ADC_CAL_MSB__OFFSET, 0x00000000 +.set CYFLD_SFLASH_CSD_ADC_CAL_MSB__SIZE, 0x00000008 +.set CYREG_SFLASH_SAR_TEMP_MULTIPLIER, 0x0ffff264 +.set CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET, 0x00000000 +.set CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE, 0x00000010 +.set CYREG_SFLASH_SAR_TEMP_OFFSET, 0x0ffff266 +.set CYFLD_SFLASH_TEMP_OFFSET__OFFSET, 0x00000000 +.set CYFLD_SFLASH_TEMP_OFFSET__SIZE, 0x00000010 +.set CYREG_SFLASH_PROT_VIRGINKEY0, 0x0ffff270 +.set CYFLD_SFLASH_KEY8__OFFSET, 0x00000000 +.set CYFLD_SFLASH_KEY8__SIZE, 0x00000008 +.set CYREG_SFLASH_PROT_VIRGINKEY1, 0x0ffff271 +.set CYREG_SFLASH_PROT_VIRGINKEY2, 0x0ffff272 +.set CYREG_SFLASH_PROT_VIRGINKEY3, 0x0ffff273 +.set CYREG_SFLASH_PROT_VIRGINKEY4, 0x0ffff274 +.set CYREG_SFLASH_PROT_VIRGINKEY5, 0x0ffff275 +.set CYREG_SFLASH_PROT_VIRGINKEY6, 0x0ffff276 +.set CYREG_SFLASH_PROT_VIRGINKEY7, 0x0ffff277 +.set CYREG_SFLASH_DIE_LOT0, 0x0ffff278 +.set CYFLD_SFLASH_LOT__OFFSET, 0x00000000 +.set CYFLD_SFLASH_LOT__SIZE, 0x00000008 +.set CYREG_SFLASH_DIE_LOT1, 0x0ffff279 +.set CYREG_SFLASH_DIE_LOT2, 0x0ffff27a +.set CYREG_SFLASH_DIE_WAFER, 0x0ffff27b +.set CYFLD_SFLASH_WAFER__OFFSET, 0x00000000 +.set CYFLD_SFLASH_WAFER__SIZE, 0x00000008 +.set CYREG_SFLASH_DIE_X, 0x0ffff27c +.set CYFLD_SFLASH_X__OFFSET, 0x00000000 +.set CYFLD_SFLASH_X__SIZE, 0x00000008 +.set CYREG_SFLASH_DIE_Y, 0x0ffff27d +.set CYFLD_SFLASH_Y__OFFSET, 0x00000000 +.set CYFLD_SFLASH_Y__SIZE, 0x00000008 +.set CYREG_SFLASH_DIE_SORT, 0x0ffff27e +.set CYFLD_SFLASH_S1_PASS__OFFSET, 0x00000000 +.set CYFLD_SFLASH_S1_PASS__SIZE, 0x00000001 +.set CYFLD_SFLASH_S2_PASS__OFFSET, 0x00000001 +.set CYFLD_SFLASH_S2_PASS__SIZE, 0x00000001 +.set CYFLD_SFLASH_S3_PASS__OFFSET, 0x00000002 +.set CYFLD_SFLASH_S3_PASS__SIZE, 0x00000001 +.set CYFLD_SFLASH_CRI_PASS__OFFSET, 0x00000003 +.set CYFLD_SFLASH_CRI_PASS__SIZE, 0x00000001 +.set CYFLD_SFLASH_CHI_PASS__OFFSET, 0x00000004 +.set CYFLD_SFLASH_CHI_PASS__SIZE, 0x00000001 +.set CYFLD_SFLASH_ENG_PASS__OFFSET, 0x00000005 +.set CYFLD_SFLASH_ENG_PASS__SIZE, 0x00000001 +.set CYREG_SFLASH_DIE_MINOR, 0x0ffff27f +.set CYFLD_SFLASH_MINOR__OFFSET, 0x00000000 +.set CYFLD_SFLASH_MINOR__SIZE, 0x00000008 +.set CYREG_SFLASH_IMO_TRIM_USBMODE_24, 0x0ffff33e +.set CYFLD_SFLASH_TRIM_24__OFFSET, 0x00000000 +.set CYFLD_SFLASH_TRIM_24__SIZE, 0x00000008 +.set CYREG_SFLASH_IMO_TRIM_USBMODE_48, 0x0ffff33f +.set CYREG_SFLASH_IMO_TCTRIM_LT0, 0x0ffff34c +.set CYFLD_SFLASH_STEPSIZE__OFFSET, 0x00000000 +.set CYFLD_SFLASH_STEPSIZE__SIZE, 0x00000005 +.set CYFLD_SFLASH_TCTRIM__OFFSET, 0x00000005 +.set CYFLD_SFLASH_TCTRIM__SIZE, 0x00000002 +.set CYREG_SFLASH_IMO_TCTRIM_LT1, 0x0ffff34d +.set CYREG_SFLASH_IMO_TCTRIM_LT2, 0x0ffff34e +.set CYREG_SFLASH_IMO_TCTRIM_LT3, 0x0ffff34f +.set CYREG_SFLASH_IMO_TCTRIM_LT4, 0x0ffff350 +.set CYREG_SFLASH_IMO_TCTRIM_LT5, 0x0ffff351 +.set CYREG_SFLASH_IMO_TCTRIM_LT6, 0x0ffff352 +.set CYREG_SFLASH_IMO_TCTRIM_LT7, 0x0ffff353 +.set CYREG_SFLASH_IMO_TCTRIM_LT8, 0x0ffff354 +.set CYREG_SFLASH_IMO_TCTRIM_LT9, 0x0ffff355 +.set CYREG_SFLASH_IMO_TCTRIM_LT10, 0x0ffff356 +.set CYREG_SFLASH_IMO_TCTRIM_LT11, 0x0ffff357 +.set CYREG_SFLASH_IMO_TCTRIM_LT12, 0x0ffff358 +.set CYREG_SFLASH_IMO_TCTRIM_LT13, 0x0ffff359 +.set CYREG_SFLASH_IMO_TCTRIM_LT14, 0x0ffff35a +.set CYREG_SFLASH_IMO_TCTRIM_LT15, 0x0ffff35b +.set CYREG_SFLASH_IMO_TCTRIM_LT16, 0x0ffff35c +.set CYREG_SFLASH_IMO_TCTRIM_LT17, 0x0ffff35d +.set CYREG_SFLASH_IMO_TCTRIM_LT18, 0x0ffff35e +.set CYREG_SFLASH_IMO_TCTRIM_LT19, 0x0ffff35f +.set CYREG_SFLASH_IMO_TCTRIM_LT20, 0x0ffff360 +.set CYREG_SFLASH_IMO_TCTRIM_LT21, 0x0ffff361 +.set CYREG_SFLASH_IMO_TCTRIM_LT22, 0x0ffff362 +.set CYREG_SFLASH_IMO_TCTRIM_LT23, 0x0ffff363 +.set CYREG_SFLASH_IMO_TCTRIM_LT24, 0x0ffff364 +.set CYREG_SFLASH_IMO_TRIM_LT0, 0x0ffff365 +.set CYFLD_SFLASH_OFFSET__OFFSET, 0x00000000 +.set CYFLD_SFLASH_OFFSET__SIZE, 0x00000008 +.set CYREG_SFLASH_IMO_TRIM_LT1, 0x0ffff366 +.set CYREG_SFLASH_IMO_TRIM_LT2, 0x0ffff367 +.set CYREG_SFLASH_IMO_TRIM_LT3, 0x0ffff368 +.set CYREG_SFLASH_IMO_TRIM_LT4, 0x0ffff369 +.set CYREG_SFLASH_IMO_TRIM_LT5, 0x0ffff36a +.set CYREG_SFLASH_IMO_TRIM_LT6, 0x0ffff36b +.set CYREG_SFLASH_IMO_TRIM_LT7, 0x0ffff36c +.set CYREG_SFLASH_IMO_TRIM_LT8, 0x0ffff36d +.set CYREG_SFLASH_IMO_TRIM_LT9, 0x0ffff36e +.set CYREG_SFLASH_IMO_TRIM_LT10, 0x0ffff36f +.set CYREG_SFLASH_IMO_TRIM_LT11, 0x0ffff370 +.set CYREG_SFLASH_IMO_TRIM_LT12, 0x0ffff371 +.set CYREG_SFLASH_IMO_TRIM_LT13, 0x0ffff372 +.set CYREG_SFLASH_IMO_TRIM_LT14, 0x0ffff373 +.set CYREG_SFLASH_IMO_TRIM_LT15, 0x0ffff374 +.set CYREG_SFLASH_IMO_TRIM_LT16, 0x0ffff375 +.set CYREG_SFLASH_IMO_TRIM_LT17, 0x0ffff376 +.set CYREG_SFLASH_IMO_TRIM_LT18, 0x0ffff377 +.set CYREG_SFLASH_IMO_TRIM_LT19, 0x0ffff378 +.set CYREG_SFLASH_IMO_TRIM_LT20, 0x0ffff379 +.set CYREG_SFLASH_IMO_TRIM_LT21, 0x0ffff37a +.set CYREG_SFLASH_IMO_TRIM_LT22, 0x0ffff37b +.set CYREG_SFLASH_IMO_TRIM_LT23, 0x0ffff37c +.set CYREG_SFLASH_IMO_TRIM_LT24, 0x0ffff37d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH0, 0x0ffff400 +.set CYFLD_SFLASH_BYTE_MEM__OFFSET, 0x00000000 +.set CYFLD_SFLASH_BYTE_MEM__SIZE, 0x00000008 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1, 0x0ffff401 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH2, 0x0ffff402 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH3, 0x0ffff403 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH4, 0x0ffff404 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH5, 0x0ffff405 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH6, 0x0ffff406 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH7, 0x0ffff407 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH8, 0x0ffff408 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH9, 0x0ffff409 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH10, 0x0ffff40a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH11, 0x0ffff40b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH12, 0x0ffff40c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH13, 0x0ffff40d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH14, 0x0ffff40e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH15, 0x0ffff40f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH16, 0x0ffff410 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH17, 0x0ffff411 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH18, 0x0ffff412 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH19, 0x0ffff413 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH20, 0x0ffff414 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH21, 0x0ffff415 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH22, 0x0ffff416 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH23, 0x0ffff417 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH24, 0x0ffff418 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH25, 0x0ffff419 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH26, 0x0ffff41a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH27, 0x0ffff41b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH28, 0x0ffff41c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH29, 0x0ffff41d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH30, 0x0ffff41e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH31, 0x0ffff41f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH32, 0x0ffff420 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH33, 0x0ffff421 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH34, 0x0ffff422 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH35, 0x0ffff423 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH36, 0x0ffff424 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH37, 0x0ffff425 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH38, 0x0ffff426 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH39, 0x0ffff427 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH40, 0x0ffff428 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH41, 0x0ffff429 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH42, 0x0ffff42a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH43, 0x0ffff42b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH44, 0x0ffff42c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH45, 0x0ffff42d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH46, 0x0ffff42e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH47, 0x0ffff42f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH48, 0x0ffff430 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH49, 0x0ffff431 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH50, 0x0ffff432 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH51, 0x0ffff433 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH52, 0x0ffff434 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH53, 0x0ffff435 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH54, 0x0ffff436 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH55, 0x0ffff437 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH56, 0x0ffff438 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH57, 0x0ffff439 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH58, 0x0ffff43a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH59, 0x0ffff43b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH60, 0x0ffff43c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH61, 0x0ffff43d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH62, 0x0ffff43e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH63, 0x0ffff43f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH64, 0x0ffff440 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH65, 0x0ffff441 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH66, 0x0ffff442 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH67, 0x0ffff443 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH68, 0x0ffff444 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH69, 0x0ffff445 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH70, 0x0ffff446 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH71, 0x0ffff447 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH72, 0x0ffff448 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH73, 0x0ffff449 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH74, 0x0ffff44a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH75, 0x0ffff44b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH76, 0x0ffff44c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH77, 0x0ffff44d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH78, 0x0ffff44e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH79, 0x0ffff44f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH80, 0x0ffff450 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH81, 0x0ffff451 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH82, 0x0ffff452 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH83, 0x0ffff453 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH84, 0x0ffff454 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH85, 0x0ffff455 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH86, 0x0ffff456 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH87, 0x0ffff457 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH88, 0x0ffff458 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH89, 0x0ffff459 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH90, 0x0ffff45a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH91, 0x0ffff45b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH92, 0x0ffff45c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH93, 0x0ffff45d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH94, 0x0ffff45e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH95, 0x0ffff45f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH96, 0x0ffff460 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH97, 0x0ffff461 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH98, 0x0ffff462 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH99, 0x0ffff463 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH100, 0x0ffff464 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH101, 0x0ffff465 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH102, 0x0ffff466 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH103, 0x0ffff467 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH104, 0x0ffff468 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH105, 0x0ffff469 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH106, 0x0ffff46a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH107, 0x0ffff46b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH108, 0x0ffff46c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH109, 0x0ffff46d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH110, 0x0ffff46e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH111, 0x0ffff46f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH112, 0x0ffff470 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH113, 0x0ffff471 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH114, 0x0ffff472 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH115, 0x0ffff473 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH116, 0x0ffff474 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH117, 0x0ffff475 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH118, 0x0ffff476 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH119, 0x0ffff477 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH120, 0x0ffff478 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH121, 0x0ffff479 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH122, 0x0ffff47a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH123, 0x0ffff47b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH124, 0x0ffff47c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH125, 0x0ffff47d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH126, 0x0ffff47e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH127, 0x0ffff47f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH128, 0x0ffff480 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH129, 0x0ffff481 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH130, 0x0ffff482 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH131, 0x0ffff483 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH132, 0x0ffff484 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH133, 0x0ffff485 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH134, 0x0ffff486 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH135, 0x0ffff487 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH136, 0x0ffff488 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH137, 0x0ffff489 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH138, 0x0ffff48a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH139, 0x0ffff48b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH140, 0x0ffff48c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH141, 0x0ffff48d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH142, 0x0ffff48e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH143, 0x0ffff48f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH144, 0x0ffff490 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH145, 0x0ffff491 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH146, 0x0ffff492 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH147, 0x0ffff493 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH148, 0x0ffff494 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH149, 0x0ffff495 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH150, 0x0ffff496 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH151, 0x0ffff497 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH152, 0x0ffff498 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH153, 0x0ffff499 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH154, 0x0ffff49a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH155, 0x0ffff49b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH156, 0x0ffff49c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH157, 0x0ffff49d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH158, 0x0ffff49e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH159, 0x0ffff49f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH160, 0x0ffff4a0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH161, 0x0ffff4a1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH162, 0x0ffff4a2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH163, 0x0ffff4a3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH164, 0x0ffff4a4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH165, 0x0ffff4a5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH166, 0x0ffff4a6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH167, 0x0ffff4a7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH168, 0x0ffff4a8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH169, 0x0ffff4a9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH170, 0x0ffff4aa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH171, 0x0ffff4ab +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH172, 0x0ffff4ac +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH173, 0x0ffff4ad +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH174, 0x0ffff4ae +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH175, 0x0ffff4af +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH176, 0x0ffff4b0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH177, 0x0ffff4b1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH178, 0x0ffff4b2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH179, 0x0ffff4b3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH180, 0x0ffff4b4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH181, 0x0ffff4b5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH182, 0x0ffff4b6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH183, 0x0ffff4b7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH184, 0x0ffff4b8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH185, 0x0ffff4b9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH186, 0x0ffff4ba +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH187, 0x0ffff4bb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH188, 0x0ffff4bc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH189, 0x0ffff4bd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH190, 0x0ffff4be +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH191, 0x0ffff4bf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH192, 0x0ffff4c0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH193, 0x0ffff4c1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH194, 0x0ffff4c2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH195, 0x0ffff4c3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH196, 0x0ffff4c4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH197, 0x0ffff4c5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH198, 0x0ffff4c6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH199, 0x0ffff4c7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH200, 0x0ffff4c8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH201, 0x0ffff4c9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH202, 0x0ffff4ca +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH203, 0x0ffff4cb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH204, 0x0ffff4cc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH205, 0x0ffff4cd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH206, 0x0ffff4ce +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH207, 0x0ffff4cf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH208, 0x0ffff4d0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH209, 0x0ffff4d1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH210, 0x0ffff4d2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH211, 0x0ffff4d3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH212, 0x0ffff4d4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH213, 0x0ffff4d5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH214, 0x0ffff4d6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH215, 0x0ffff4d7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH216, 0x0ffff4d8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH217, 0x0ffff4d9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH218, 0x0ffff4da +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH219, 0x0ffff4db +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH220, 0x0ffff4dc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH221, 0x0ffff4dd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH222, 0x0ffff4de +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH223, 0x0ffff4df +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH224, 0x0ffff4e0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH225, 0x0ffff4e1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH226, 0x0ffff4e2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH227, 0x0ffff4e3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH228, 0x0ffff4e4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH229, 0x0ffff4e5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH230, 0x0ffff4e6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH231, 0x0ffff4e7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH232, 0x0ffff4e8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH233, 0x0ffff4e9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH234, 0x0ffff4ea +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH235, 0x0ffff4eb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH236, 0x0ffff4ec +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH237, 0x0ffff4ed +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH238, 0x0ffff4ee +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH239, 0x0ffff4ef +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH240, 0x0ffff4f0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH241, 0x0ffff4f1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH242, 0x0ffff4f2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH243, 0x0ffff4f3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH244, 0x0ffff4f4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH245, 0x0ffff4f5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH246, 0x0ffff4f6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH247, 0x0ffff4f7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH248, 0x0ffff4f8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH249, 0x0ffff4f9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH250, 0x0ffff4fa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH251, 0x0ffff4fb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH252, 0x0ffff4fc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH253, 0x0ffff4fd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH254, 0x0ffff4fe +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH255, 0x0ffff4ff +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH256, 0x0ffff500 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH257, 0x0ffff501 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH258, 0x0ffff502 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH259, 0x0ffff503 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH260, 0x0ffff504 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH261, 0x0ffff505 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH262, 0x0ffff506 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH263, 0x0ffff507 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH264, 0x0ffff508 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH265, 0x0ffff509 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH266, 0x0ffff50a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH267, 0x0ffff50b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH268, 0x0ffff50c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH269, 0x0ffff50d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH270, 0x0ffff50e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH271, 0x0ffff50f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH272, 0x0ffff510 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH273, 0x0ffff511 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH274, 0x0ffff512 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH275, 0x0ffff513 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH276, 0x0ffff514 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH277, 0x0ffff515 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH278, 0x0ffff516 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH279, 0x0ffff517 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH280, 0x0ffff518 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH281, 0x0ffff519 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH282, 0x0ffff51a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH283, 0x0ffff51b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH284, 0x0ffff51c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH285, 0x0ffff51d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH286, 0x0ffff51e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH287, 0x0ffff51f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH288, 0x0ffff520 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH289, 0x0ffff521 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH290, 0x0ffff522 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH291, 0x0ffff523 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH292, 0x0ffff524 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH293, 0x0ffff525 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH294, 0x0ffff526 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH295, 0x0ffff527 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH296, 0x0ffff528 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH297, 0x0ffff529 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH298, 0x0ffff52a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH299, 0x0ffff52b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH300, 0x0ffff52c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH301, 0x0ffff52d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH302, 0x0ffff52e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH303, 0x0ffff52f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH304, 0x0ffff530 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH305, 0x0ffff531 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH306, 0x0ffff532 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH307, 0x0ffff533 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH308, 0x0ffff534 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH309, 0x0ffff535 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH310, 0x0ffff536 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH311, 0x0ffff537 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH312, 0x0ffff538 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH313, 0x0ffff539 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH314, 0x0ffff53a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH315, 0x0ffff53b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH316, 0x0ffff53c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH317, 0x0ffff53d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH318, 0x0ffff53e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH319, 0x0ffff53f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH320, 0x0ffff540 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH321, 0x0ffff541 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH322, 0x0ffff542 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH323, 0x0ffff543 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH324, 0x0ffff544 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH325, 0x0ffff545 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH326, 0x0ffff546 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH327, 0x0ffff547 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH328, 0x0ffff548 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH329, 0x0ffff549 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH330, 0x0ffff54a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH331, 0x0ffff54b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH332, 0x0ffff54c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH333, 0x0ffff54d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH334, 0x0ffff54e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH335, 0x0ffff54f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH336, 0x0ffff550 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH337, 0x0ffff551 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH338, 0x0ffff552 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH339, 0x0ffff553 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH340, 0x0ffff554 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH341, 0x0ffff555 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH342, 0x0ffff556 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH343, 0x0ffff557 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH344, 0x0ffff558 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH345, 0x0ffff559 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH346, 0x0ffff55a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH347, 0x0ffff55b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH348, 0x0ffff55c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH349, 0x0ffff55d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH350, 0x0ffff55e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH351, 0x0ffff55f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH352, 0x0ffff560 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH353, 0x0ffff561 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH354, 0x0ffff562 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH355, 0x0ffff563 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH356, 0x0ffff564 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH357, 0x0ffff565 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH358, 0x0ffff566 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH359, 0x0ffff567 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH360, 0x0ffff568 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH361, 0x0ffff569 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH362, 0x0ffff56a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH363, 0x0ffff56b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH364, 0x0ffff56c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH365, 0x0ffff56d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH366, 0x0ffff56e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH367, 0x0ffff56f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH368, 0x0ffff570 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH369, 0x0ffff571 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH370, 0x0ffff572 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH371, 0x0ffff573 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH372, 0x0ffff574 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH373, 0x0ffff575 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH374, 0x0ffff576 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH375, 0x0ffff577 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH376, 0x0ffff578 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH377, 0x0ffff579 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH378, 0x0ffff57a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH379, 0x0ffff57b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH380, 0x0ffff57c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH381, 0x0ffff57d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH382, 0x0ffff57e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH383, 0x0ffff57f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH384, 0x0ffff580 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH385, 0x0ffff581 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH386, 0x0ffff582 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH387, 0x0ffff583 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH388, 0x0ffff584 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH389, 0x0ffff585 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH390, 0x0ffff586 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH391, 0x0ffff587 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH392, 0x0ffff588 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH393, 0x0ffff589 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH394, 0x0ffff58a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH395, 0x0ffff58b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH396, 0x0ffff58c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH397, 0x0ffff58d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH398, 0x0ffff58e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH399, 0x0ffff58f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH400, 0x0ffff590 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH401, 0x0ffff591 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH402, 0x0ffff592 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH403, 0x0ffff593 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH404, 0x0ffff594 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH405, 0x0ffff595 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH406, 0x0ffff596 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH407, 0x0ffff597 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH408, 0x0ffff598 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH409, 0x0ffff599 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH410, 0x0ffff59a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH411, 0x0ffff59b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH412, 0x0ffff59c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH413, 0x0ffff59d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH414, 0x0ffff59e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH415, 0x0ffff59f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH416, 0x0ffff5a0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH417, 0x0ffff5a1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH418, 0x0ffff5a2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH419, 0x0ffff5a3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH420, 0x0ffff5a4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH421, 0x0ffff5a5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH422, 0x0ffff5a6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH423, 0x0ffff5a7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH424, 0x0ffff5a8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH425, 0x0ffff5a9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH426, 0x0ffff5aa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH427, 0x0ffff5ab +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH428, 0x0ffff5ac +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH429, 0x0ffff5ad +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH430, 0x0ffff5ae +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH431, 0x0ffff5af +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH432, 0x0ffff5b0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH433, 0x0ffff5b1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH434, 0x0ffff5b2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH435, 0x0ffff5b3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH436, 0x0ffff5b4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH437, 0x0ffff5b5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH438, 0x0ffff5b6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH439, 0x0ffff5b7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH440, 0x0ffff5b8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH441, 0x0ffff5b9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH442, 0x0ffff5ba +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH443, 0x0ffff5bb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH444, 0x0ffff5bc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH445, 0x0ffff5bd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH446, 0x0ffff5be +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH447, 0x0ffff5bf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH448, 0x0ffff5c0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH449, 0x0ffff5c1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH450, 0x0ffff5c2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH451, 0x0ffff5c3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH452, 0x0ffff5c4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH453, 0x0ffff5c5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH454, 0x0ffff5c6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH455, 0x0ffff5c7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH456, 0x0ffff5c8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH457, 0x0ffff5c9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH458, 0x0ffff5ca +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH459, 0x0ffff5cb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH460, 0x0ffff5cc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH461, 0x0ffff5cd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH462, 0x0ffff5ce +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH463, 0x0ffff5cf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH464, 0x0ffff5d0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH465, 0x0ffff5d1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH466, 0x0ffff5d2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH467, 0x0ffff5d3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH468, 0x0ffff5d4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH469, 0x0ffff5d5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH470, 0x0ffff5d6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH471, 0x0ffff5d7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH472, 0x0ffff5d8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH473, 0x0ffff5d9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH474, 0x0ffff5da +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH475, 0x0ffff5db +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH476, 0x0ffff5dc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH477, 0x0ffff5dd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH478, 0x0ffff5de +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH479, 0x0ffff5df +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH480, 0x0ffff5e0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH481, 0x0ffff5e1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH482, 0x0ffff5e2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH483, 0x0ffff5e3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH484, 0x0ffff5e4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH485, 0x0ffff5e5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH486, 0x0ffff5e6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH487, 0x0ffff5e7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH488, 0x0ffff5e8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH489, 0x0ffff5e9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH490, 0x0ffff5ea +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH491, 0x0ffff5eb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH492, 0x0ffff5ec +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH493, 0x0ffff5ed +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH494, 0x0ffff5ee +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH495, 0x0ffff5ef +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH496, 0x0ffff5f0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH497, 0x0ffff5f1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH498, 0x0ffff5f2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH499, 0x0ffff5f3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH500, 0x0ffff5f4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH501, 0x0ffff5f5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH502, 0x0ffff5f6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH503, 0x0ffff5f7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH504, 0x0ffff5f8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH505, 0x0ffff5f9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH506, 0x0ffff5fa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH507, 0x0ffff5fb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH508, 0x0ffff5fc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH509, 0x0ffff5fd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH510, 0x0ffff5fe +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH511, 0x0ffff5ff +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH512, 0x0ffff600 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH513, 0x0ffff601 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH514, 0x0ffff602 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH515, 0x0ffff603 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH516, 0x0ffff604 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH517, 0x0ffff605 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH518, 0x0ffff606 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH519, 0x0ffff607 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH520, 0x0ffff608 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH521, 0x0ffff609 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH522, 0x0ffff60a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH523, 0x0ffff60b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH524, 0x0ffff60c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH525, 0x0ffff60d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH526, 0x0ffff60e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH527, 0x0ffff60f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH528, 0x0ffff610 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH529, 0x0ffff611 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH530, 0x0ffff612 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH531, 0x0ffff613 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH532, 0x0ffff614 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH533, 0x0ffff615 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH534, 0x0ffff616 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH535, 0x0ffff617 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH536, 0x0ffff618 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH537, 0x0ffff619 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH538, 0x0ffff61a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH539, 0x0ffff61b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH540, 0x0ffff61c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH541, 0x0ffff61d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH542, 0x0ffff61e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH543, 0x0ffff61f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH544, 0x0ffff620 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH545, 0x0ffff621 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH546, 0x0ffff622 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH547, 0x0ffff623 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH548, 0x0ffff624 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH549, 0x0ffff625 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH550, 0x0ffff626 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH551, 0x0ffff627 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH552, 0x0ffff628 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH553, 0x0ffff629 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH554, 0x0ffff62a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH555, 0x0ffff62b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH556, 0x0ffff62c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH557, 0x0ffff62d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH558, 0x0ffff62e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH559, 0x0ffff62f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH560, 0x0ffff630 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH561, 0x0ffff631 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH562, 0x0ffff632 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH563, 0x0ffff633 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH564, 0x0ffff634 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH565, 0x0ffff635 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH566, 0x0ffff636 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH567, 0x0ffff637 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH568, 0x0ffff638 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH569, 0x0ffff639 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH570, 0x0ffff63a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH571, 0x0ffff63b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH572, 0x0ffff63c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH573, 0x0ffff63d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH574, 0x0ffff63e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH575, 0x0ffff63f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH576, 0x0ffff640 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH577, 0x0ffff641 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH578, 0x0ffff642 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH579, 0x0ffff643 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH580, 0x0ffff644 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH581, 0x0ffff645 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH582, 0x0ffff646 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH583, 0x0ffff647 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH584, 0x0ffff648 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH585, 0x0ffff649 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH586, 0x0ffff64a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH587, 0x0ffff64b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH588, 0x0ffff64c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH589, 0x0ffff64d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH590, 0x0ffff64e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH591, 0x0ffff64f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH592, 0x0ffff650 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH593, 0x0ffff651 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH594, 0x0ffff652 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH595, 0x0ffff653 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH596, 0x0ffff654 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH597, 0x0ffff655 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH598, 0x0ffff656 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH599, 0x0ffff657 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH600, 0x0ffff658 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH601, 0x0ffff659 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH602, 0x0ffff65a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH603, 0x0ffff65b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH604, 0x0ffff65c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH605, 0x0ffff65d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH606, 0x0ffff65e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH607, 0x0ffff65f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH608, 0x0ffff660 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH609, 0x0ffff661 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH610, 0x0ffff662 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH611, 0x0ffff663 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH612, 0x0ffff664 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH613, 0x0ffff665 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH614, 0x0ffff666 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH615, 0x0ffff667 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH616, 0x0ffff668 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH617, 0x0ffff669 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH618, 0x0ffff66a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH619, 0x0ffff66b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH620, 0x0ffff66c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH621, 0x0ffff66d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH622, 0x0ffff66e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH623, 0x0ffff66f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH624, 0x0ffff670 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH625, 0x0ffff671 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH626, 0x0ffff672 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH627, 0x0ffff673 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH628, 0x0ffff674 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH629, 0x0ffff675 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH630, 0x0ffff676 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH631, 0x0ffff677 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH632, 0x0ffff678 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH633, 0x0ffff679 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH634, 0x0ffff67a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH635, 0x0ffff67b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH636, 0x0ffff67c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH637, 0x0ffff67d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH638, 0x0ffff67e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH639, 0x0ffff67f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH640, 0x0ffff680 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH641, 0x0ffff681 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH642, 0x0ffff682 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH643, 0x0ffff683 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH644, 0x0ffff684 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH645, 0x0ffff685 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH646, 0x0ffff686 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH647, 0x0ffff687 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH648, 0x0ffff688 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH649, 0x0ffff689 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH650, 0x0ffff68a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH651, 0x0ffff68b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH652, 0x0ffff68c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH653, 0x0ffff68d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH654, 0x0ffff68e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH655, 0x0ffff68f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH656, 0x0ffff690 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH657, 0x0ffff691 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH658, 0x0ffff692 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH659, 0x0ffff693 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH660, 0x0ffff694 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH661, 0x0ffff695 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH662, 0x0ffff696 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH663, 0x0ffff697 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH664, 0x0ffff698 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH665, 0x0ffff699 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH666, 0x0ffff69a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH667, 0x0ffff69b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH668, 0x0ffff69c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH669, 0x0ffff69d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH670, 0x0ffff69e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH671, 0x0ffff69f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH672, 0x0ffff6a0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH673, 0x0ffff6a1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH674, 0x0ffff6a2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH675, 0x0ffff6a3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH676, 0x0ffff6a4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH677, 0x0ffff6a5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH678, 0x0ffff6a6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH679, 0x0ffff6a7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH680, 0x0ffff6a8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH681, 0x0ffff6a9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH682, 0x0ffff6aa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH683, 0x0ffff6ab +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH684, 0x0ffff6ac +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH685, 0x0ffff6ad +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH686, 0x0ffff6ae +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH687, 0x0ffff6af +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH688, 0x0ffff6b0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH689, 0x0ffff6b1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH690, 0x0ffff6b2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH691, 0x0ffff6b3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH692, 0x0ffff6b4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH693, 0x0ffff6b5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH694, 0x0ffff6b6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH695, 0x0ffff6b7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH696, 0x0ffff6b8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH697, 0x0ffff6b9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH698, 0x0ffff6ba +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH699, 0x0ffff6bb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH700, 0x0ffff6bc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH701, 0x0ffff6bd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH702, 0x0ffff6be +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH703, 0x0ffff6bf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH704, 0x0ffff6c0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH705, 0x0ffff6c1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH706, 0x0ffff6c2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH707, 0x0ffff6c3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH708, 0x0ffff6c4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH709, 0x0ffff6c5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH710, 0x0ffff6c6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH711, 0x0ffff6c7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH712, 0x0ffff6c8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH713, 0x0ffff6c9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH714, 0x0ffff6ca +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH715, 0x0ffff6cb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH716, 0x0ffff6cc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH717, 0x0ffff6cd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH718, 0x0ffff6ce +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH719, 0x0ffff6cf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH720, 0x0ffff6d0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH721, 0x0ffff6d1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH722, 0x0ffff6d2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH723, 0x0ffff6d3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH724, 0x0ffff6d4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH725, 0x0ffff6d5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH726, 0x0ffff6d6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH727, 0x0ffff6d7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH728, 0x0ffff6d8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH729, 0x0ffff6d9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH730, 0x0ffff6da +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH731, 0x0ffff6db +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH732, 0x0ffff6dc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH733, 0x0ffff6dd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH734, 0x0ffff6de +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH735, 0x0ffff6df +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH736, 0x0ffff6e0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH737, 0x0ffff6e1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH738, 0x0ffff6e2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH739, 0x0ffff6e3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH740, 0x0ffff6e4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH741, 0x0ffff6e5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH742, 0x0ffff6e6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH743, 0x0ffff6e7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH744, 0x0ffff6e8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH745, 0x0ffff6e9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH746, 0x0ffff6ea +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH747, 0x0ffff6eb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH748, 0x0ffff6ec +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH749, 0x0ffff6ed +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH750, 0x0ffff6ee +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH751, 0x0ffff6ef +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH752, 0x0ffff6f0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH753, 0x0ffff6f1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH754, 0x0ffff6f2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH755, 0x0ffff6f3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH756, 0x0ffff6f4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH757, 0x0ffff6f5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH758, 0x0ffff6f6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH759, 0x0ffff6f7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH760, 0x0ffff6f8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH761, 0x0ffff6f9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH762, 0x0ffff6fa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH763, 0x0ffff6fb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH764, 0x0ffff6fc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH765, 0x0ffff6fd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH766, 0x0ffff6fe +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH767, 0x0ffff6ff +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH768, 0x0ffff700 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH769, 0x0ffff701 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH770, 0x0ffff702 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH771, 0x0ffff703 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH772, 0x0ffff704 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH773, 0x0ffff705 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH774, 0x0ffff706 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH775, 0x0ffff707 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH776, 0x0ffff708 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH777, 0x0ffff709 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH778, 0x0ffff70a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH779, 0x0ffff70b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH780, 0x0ffff70c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH781, 0x0ffff70d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH782, 0x0ffff70e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH783, 0x0ffff70f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH784, 0x0ffff710 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH785, 0x0ffff711 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH786, 0x0ffff712 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH787, 0x0ffff713 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH788, 0x0ffff714 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH789, 0x0ffff715 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH790, 0x0ffff716 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH791, 0x0ffff717 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH792, 0x0ffff718 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH793, 0x0ffff719 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH794, 0x0ffff71a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH795, 0x0ffff71b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH796, 0x0ffff71c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH797, 0x0ffff71d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH798, 0x0ffff71e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH799, 0x0ffff71f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH800, 0x0ffff720 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH801, 0x0ffff721 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH802, 0x0ffff722 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH803, 0x0ffff723 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH804, 0x0ffff724 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH805, 0x0ffff725 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH806, 0x0ffff726 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH807, 0x0ffff727 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH808, 0x0ffff728 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH809, 0x0ffff729 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH810, 0x0ffff72a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH811, 0x0ffff72b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH812, 0x0ffff72c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH813, 0x0ffff72d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH814, 0x0ffff72e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH815, 0x0ffff72f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH816, 0x0ffff730 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH817, 0x0ffff731 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH818, 0x0ffff732 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH819, 0x0ffff733 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH820, 0x0ffff734 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH821, 0x0ffff735 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH822, 0x0ffff736 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH823, 0x0ffff737 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH824, 0x0ffff738 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH825, 0x0ffff739 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH826, 0x0ffff73a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH827, 0x0ffff73b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH828, 0x0ffff73c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH829, 0x0ffff73d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH830, 0x0ffff73e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH831, 0x0ffff73f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH832, 0x0ffff740 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH833, 0x0ffff741 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH834, 0x0ffff742 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH835, 0x0ffff743 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH836, 0x0ffff744 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH837, 0x0ffff745 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH838, 0x0ffff746 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH839, 0x0ffff747 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH840, 0x0ffff748 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH841, 0x0ffff749 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH842, 0x0ffff74a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH843, 0x0ffff74b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH844, 0x0ffff74c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH845, 0x0ffff74d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH846, 0x0ffff74e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH847, 0x0ffff74f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH848, 0x0ffff750 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH849, 0x0ffff751 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH850, 0x0ffff752 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH851, 0x0ffff753 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH852, 0x0ffff754 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH853, 0x0ffff755 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH854, 0x0ffff756 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH855, 0x0ffff757 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH856, 0x0ffff758 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH857, 0x0ffff759 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH858, 0x0ffff75a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH859, 0x0ffff75b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH860, 0x0ffff75c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH861, 0x0ffff75d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH862, 0x0ffff75e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH863, 0x0ffff75f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH864, 0x0ffff760 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH865, 0x0ffff761 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH866, 0x0ffff762 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH867, 0x0ffff763 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH868, 0x0ffff764 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH869, 0x0ffff765 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH870, 0x0ffff766 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH871, 0x0ffff767 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH872, 0x0ffff768 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH873, 0x0ffff769 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH874, 0x0ffff76a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH875, 0x0ffff76b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH876, 0x0ffff76c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH877, 0x0ffff76d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH878, 0x0ffff76e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH879, 0x0ffff76f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH880, 0x0ffff770 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH881, 0x0ffff771 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH882, 0x0ffff772 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH883, 0x0ffff773 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH884, 0x0ffff774 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH885, 0x0ffff775 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH886, 0x0ffff776 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH887, 0x0ffff777 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH888, 0x0ffff778 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH889, 0x0ffff779 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH890, 0x0ffff77a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH891, 0x0ffff77b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH892, 0x0ffff77c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH893, 0x0ffff77d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH894, 0x0ffff77e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH895, 0x0ffff77f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH896, 0x0ffff780 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH897, 0x0ffff781 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH898, 0x0ffff782 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH899, 0x0ffff783 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH900, 0x0ffff784 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH901, 0x0ffff785 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH902, 0x0ffff786 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH903, 0x0ffff787 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH904, 0x0ffff788 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH905, 0x0ffff789 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH906, 0x0ffff78a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH907, 0x0ffff78b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH908, 0x0ffff78c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH909, 0x0ffff78d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH910, 0x0ffff78e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH911, 0x0ffff78f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH912, 0x0ffff790 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH913, 0x0ffff791 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH914, 0x0ffff792 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH915, 0x0ffff793 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH916, 0x0ffff794 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH917, 0x0ffff795 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH918, 0x0ffff796 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH919, 0x0ffff797 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH920, 0x0ffff798 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH921, 0x0ffff799 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH922, 0x0ffff79a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH923, 0x0ffff79b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH924, 0x0ffff79c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH925, 0x0ffff79d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH926, 0x0ffff79e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH927, 0x0ffff79f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH928, 0x0ffff7a0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH929, 0x0ffff7a1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH930, 0x0ffff7a2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH931, 0x0ffff7a3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH932, 0x0ffff7a4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH933, 0x0ffff7a5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH934, 0x0ffff7a6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH935, 0x0ffff7a7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH936, 0x0ffff7a8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH937, 0x0ffff7a9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH938, 0x0ffff7aa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH939, 0x0ffff7ab +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH940, 0x0ffff7ac +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH941, 0x0ffff7ad +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH942, 0x0ffff7ae +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH943, 0x0ffff7af +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH944, 0x0ffff7b0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH945, 0x0ffff7b1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH946, 0x0ffff7b2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH947, 0x0ffff7b3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH948, 0x0ffff7b4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH949, 0x0ffff7b5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH950, 0x0ffff7b6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH951, 0x0ffff7b7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH952, 0x0ffff7b8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH953, 0x0ffff7b9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH954, 0x0ffff7ba +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH955, 0x0ffff7bb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH956, 0x0ffff7bc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH957, 0x0ffff7bd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH958, 0x0ffff7be +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH959, 0x0ffff7bf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH960, 0x0ffff7c0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH961, 0x0ffff7c1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH962, 0x0ffff7c2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH963, 0x0ffff7c3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH964, 0x0ffff7c4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH965, 0x0ffff7c5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH966, 0x0ffff7c6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH967, 0x0ffff7c7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH968, 0x0ffff7c8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH969, 0x0ffff7c9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH970, 0x0ffff7ca +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH971, 0x0ffff7cb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH972, 0x0ffff7cc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH973, 0x0ffff7cd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH974, 0x0ffff7ce +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH975, 0x0ffff7cf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH976, 0x0ffff7d0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH977, 0x0ffff7d1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH978, 0x0ffff7d2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH979, 0x0ffff7d3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH980, 0x0ffff7d4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH981, 0x0ffff7d5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH982, 0x0ffff7d6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH983, 0x0ffff7d7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH984, 0x0ffff7d8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH985, 0x0ffff7d9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH986, 0x0ffff7da +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH987, 0x0ffff7db +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH988, 0x0ffff7dc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH989, 0x0ffff7dd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH990, 0x0ffff7de +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH991, 0x0ffff7df +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH992, 0x0ffff7e0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH993, 0x0ffff7e1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH994, 0x0ffff7e2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH995, 0x0ffff7e3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH996, 0x0ffff7e4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH997, 0x0ffff7e5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH998, 0x0ffff7e6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH999, 0x0ffff7e7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1000, 0x0ffff7e8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1001, 0x0ffff7e9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1002, 0x0ffff7ea +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1003, 0x0ffff7eb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1004, 0x0ffff7ec +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1005, 0x0ffff7ed +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1006, 0x0ffff7ee +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1007, 0x0ffff7ef +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1008, 0x0ffff7f0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1009, 0x0ffff7f1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1010, 0x0ffff7f2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1011, 0x0ffff7f3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1012, 0x0ffff7f4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1013, 0x0ffff7f5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1014, 0x0ffff7f6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1015, 0x0ffff7f7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1016, 0x0ffff7f8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1017, 0x0ffff7f9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1018, 0x0ffff7fa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1019, 0x0ffff7fb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1020, 0x0ffff7fc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1021, 0x0ffff7fd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1022, 0x0ffff7fe +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1023, 0x0ffff7ff +.set CYDEV_ROM_BASE, 0x10000000 +.set CYDEV_ROM_SIZE, 0x00002000 +.set CYREG_ROM_DATA_MBASE, 0x10000000 +.set CYREG_ROM_DATA_MSIZE, 0x00002000 +.set CYDEV_SRAM_BASE, 0x20000000 +.set CYDEV_SRAM_SIZE, 0x00004000 +.set CYREG_SRAM_DATA_MBASE, 0x20000000 +.set CYREG_SRAM_DATA_MSIZE, 0x00004000 +.set CYDEV_PERI_BASE, 0x40010000 +.set CYDEV_PERI_SIZE, 0x00010000 +.set CYREG_PERI_DIV_CMD, 0x40010000 +.set CYFLD_PERI_SEL_DIV__OFFSET, 0x00000000 +.set CYFLD_PERI_SEL_DIV__SIZE, 0x00000006 +.set CYFLD_PERI_SEL_TYPE__OFFSET, 0x00000006 +.set CYFLD_PERI_SEL_TYPE__SIZE, 0x00000002 +.set CYFLD_PERI_PA_SEL_DIV__OFFSET, 0x00000008 +.set CYFLD_PERI_PA_SEL_DIV__SIZE, 0x00000006 +.set CYFLD_PERI_PA_SEL_TYPE__OFFSET, 0x0000000e +.set CYFLD_PERI_PA_SEL_TYPE__SIZE, 0x00000002 +.set CYFLD_PERI_DISABLE__OFFSET, 0x0000001e +.set CYFLD_PERI_DISABLE__SIZE, 0x00000001 +.set CYFLD_PERI_ENABLE__OFFSET, 0x0000001f +.set CYFLD_PERI_ENABLE__SIZE, 0x00000001 +.set CYREG_PERI_PCLK_CTL0, 0x40010100 +.set CYREG_PERI_PCLK_CTL1, 0x40010104 +.set CYREG_PERI_PCLK_CTL2, 0x40010108 +.set CYREG_PERI_PCLK_CTL3, 0x4001010c +.set CYREG_PERI_PCLK_CTL4, 0x40010110 +.set CYREG_PERI_PCLK_CTL5, 0x40010114 +.set CYREG_PERI_PCLK_CTL6, 0x40010118 +.set CYREG_PERI_PCLK_CTL7, 0x4001011c +.set CYREG_PERI_PCLK_CTL8, 0x40010120 +.set CYREG_PERI_PCLK_CTL9, 0x40010124 +.set CYREG_PERI_PCLK_CTL10, 0x40010128 +.set CYREG_PERI_PCLK_CTL11, 0x4001012c +.set CYREG_PERI_PCLK_CTL12, 0x40010130 +.set CYREG_PERI_PCLK_CTL13, 0x40010134 +.set CYREG_PERI_PCLK_CTL14, 0x40010138 +.set CYREG_PERI_PCLK_CTL15, 0x4001013c +.set CYREG_PERI_PCLK_CTL16, 0x40010140 +.set CYREG_PERI_PCLK_CTL17, 0x40010144 +.set CYREG_PERI_PCLK_CTL18, 0x40010148 +.set CYREG_PERI_DIV_16_CTL0, 0x40010300 +.set CYFLD_PERI_EN__OFFSET, 0x00000000 +.set CYFLD_PERI_EN__SIZE, 0x00000001 +.set CYFLD_PERI_INT16_DIV__OFFSET, 0x00000008 +.set CYFLD_PERI_INT16_DIV__SIZE, 0x00000010 +.set CYREG_PERI_DIV_16_CTL1, 0x40010304 +.set CYREG_PERI_DIV_16_CTL2, 0x40010308 +.set CYREG_PERI_DIV_16_CTL3, 0x4001030c +.set CYREG_PERI_DIV_16_CTL4, 0x40010310 +.set CYREG_PERI_DIV_16_CTL5, 0x40010314 +.set CYREG_PERI_DIV_16_CTL6, 0x40010318 +.set CYREG_PERI_DIV_16_CTL7, 0x4001031c +.set CYREG_PERI_DIV_16_CTL8, 0x40010320 +.set CYREG_PERI_DIV_16_CTL9, 0x40010324 +.set CYREG_PERI_DIV_16_CTL10, 0x40010328 +.set CYREG_PERI_DIV_16_CTL11, 0x4001032c +.set CYREG_PERI_DIV_16_5_CTL0, 0x40010400 +.set CYFLD_PERI_FRAC5_DIV__OFFSET, 0x00000003 +.set CYFLD_PERI_FRAC5_DIV__SIZE, 0x00000005 +.set CYREG_PERI_DIV_16_5_CTL1, 0x40010404 +.set CYREG_PERI_DIV_16_5_CTL2, 0x40010408 +.set CYREG_PERI_DIV_16_5_CTL3, 0x4001040c +.set CYREG_PERI_DIV_16_5_CTL4, 0x40010410 +.set CYREG_PERI_DIV_24_5_CTL, 0x40010500 +.set CYFLD_PERI_INT24_DIV__OFFSET, 0x00000008 +.set CYFLD_PERI_INT24_DIV__SIZE, 0x00000018 +.set CYREG_PERI_TR_CTL, 0x40010600 +.set CYFLD_PERI_TR_SEL__OFFSET, 0x00000000 +.set CYFLD_PERI_TR_SEL__SIZE, 0x00000007 +.set CYFLD_PERI_TR_GROUP__OFFSET, 0x00000008 +.set CYFLD_PERI_TR_GROUP__SIZE, 0x00000004 +.set CYFLD_PERI_TR_COUNT__OFFSET, 0x00000010 +.set CYFLD_PERI_TR_COUNT__SIZE, 0x00000008 +.set CYFLD_PERI_TR_OUT__OFFSET, 0x0000001e +.set CYFLD_PERI_TR_OUT__SIZE, 0x00000001 +.set CYFLD_PERI_TR_ACT__OFFSET, 0x0000001f +.set CYFLD_PERI_TR_ACT__SIZE, 0x00000001 +.set CYDEV_PERI_TR_GROUP0_BASE, 0x40012000 +.set CYDEV_PERI_TR_GROUP0_SIZE, 0x00000200 +.set CYREG_PERI_TR_GROUP0_TR_OUT_CTL0, 0x40012000 +.set CYFLD_PERI_TR_GROUP_SEL__OFFSET, 0x00000000 +.set CYFLD_PERI_TR_GROUP_SEL__SIZE, 0x00000006 +.set CYREG_PERI_TR_GROUP0_TR_OUT_CTL1, 0x40012004 +.set CYREG_PERI_TR_GROUP0_TR_OUT_CTL2, 0x40012008 +.set CYREG_PERI_TR_GROUP0_TR_OUT_CTL3, 0x4001200c +.set CYREG_PERI_TR_GROUP0_TR_OUT_CTL4, 0x40012010 +.set CYREG_PERI_TR_GROUP0_TR_OUT_CTL5, 0x40012014 +.set CYREG_PERI_TR_GROUP0_TR_OUT_CTL6, 0x40012018 +.set CYREG_PERI_TR_GROUP0_TR_OUT_CTL7, 0x4001201c +.set CYDEV_PERI_TR_GROUP1_BASE, 0x40012200 +.set CYDEV_PERI_TR_GROUP1_SIZE, 0x00000200 +.set CYREG_PERI_TR_GROUP1_TR_OUT_CTL0, 0x40012200 +.set CYREG_PERI_TR_GROUP1_TR_OUT_CTL1, 0x40012204 +.set CYREG_PERI_TR_GROUP1_TR_OUT_CTL2, 0x40012208 +.set CYREG_PERI_TR_GROUP1_TR_OUT_CTL3, 0x4001220c +.set CYREG_PERI_TR_GROUP1_TR_OUT_CTL4, 0x40012210 +.set CYREG_PERI_TR_GROUP1_TR_OUT_CTL5, 0x40012214 +.set CYREG_PERI_TR_GROUP1_TR_OUT_CTL6, 0x40012218 +.set CYDEV_PERI_TR_GROUP2_BASE, 0x40012400 +.set CYDEV_PERI_TR_GROUP2_SIZE, 0x00000200 +.set CYREG_PERI_TR_GROUP2_TR_OUT_CTL, 0x40012400 +.set CYDEV_PERI_TR_GROUP3_BASE, 0x40012600 +.set CYDEV_PERI_TR_GROUP3_SIZE, 0x00000200 +.set CYREG_PERI_TR_GROUP3_TR_OUT_CTL, 0x40012600 +.set CYDEV_HSIOM_BASE, 0x40020000 +.set CYDEV_HSIOM_SIZE, 0x00004000 +.set CYREG_HSIOM_PORT_SEL0, 0x40020000 +.set CYFLD_HSIOM_IO0_SEL__OFFSET, 0x00000000 +.set CYFLD_HSIOM_IO0_SEL__SIZE, 0x00000004 +.set CYVAL_HSIOM_IO0_SEL_GPIO, 0x00000000 +.set CYVAL_HSIOM_IO0_SEL_GPIO_DSI, 0x00000001 +.set CYVAL_HSIOM_IO0_SEL_DSI_DSI, 0x00000002 +.set CYVAL_HSIOM_IO0_SEL_DSI_GPIO, 0x00000003 +.set CYVAL_HSIOM_IO0_SEL_CSD_SENSE, 0x00000004 +.set CYVAL_HSIOM_IO0_SEL_CSD_SHIELD, 0x00000005 +.set CYVAL_HSIOM_IO0_SEL_AMUXA, 0x00000006 +.set CYVAL_HSIOM_IO0_SEL_AMUXB, 0x00000007 +.set CYVAL_HSIOM_IO0_SEL_ACT_0, 0x00000008 +.set CYVAL_HSIOM_IO0_SEL_ACT_1, 0x00000009 +.set CYVAL_HSIOM_IO0_SEL_ACT_2, 0x0000000a +.set CYVAL_HSIOM_IO0_SEL_ACT_3, 0x0000000b +.set CYVAL_HSIOM_IO0_SEL_LCD_COM, 0x0000000c +.set CYVAL_HSIOM_IO0_SEL_LCD_SEG, 0x0000000d +.set CYVAL_HSIOM_IO0_SEL_DS_0, 0x0000000c +.set CYVAL_HSIOM_IO0_SEL_DS_1, 0x0000000d +.set CYVAL_HSIOM_IO0_SEL_DS_2, 0x0000000e +.set CYVAL_HSIOM_IO0_SEL_DS_3, 0x0000000f +.set CYFLD_HSIOM_IO1_SEL__OFFSET, 0x00000004 +.set CYFLD_HSIOM_IO1_SEL__SIZE, 0x00000004 +.set CYFLD_HSIOM_IO2_SEL__OFFSET, 0x00000008 +.set CYFLD_HSIOM_IO2_SEL__SIZE, 0x00000004 +.set CYFLD_HSIOM_IO3_SEL__OFFSET, 0x0000000c +.set CYFLD_HSIOM_IO3_SEL__SIZE, 0x00000004 +.set CYFLD_HSIOM_IO4_SEL__OFFSET, 0x00000010 +.set CYFLD_HSIOM_IO4_SEL__SIZE, 0x00000004 +.set CYFLD_HSIOM_IO5_SEL__OFFSET, 0x00000014 +.set CYFLD_HSIOM_IO5_SEL__SIZE, 0x00000004 +.set CYFLD_HSIOM_IO6_SEL__OFFSET, 0x00000018 +.set CYFLD_HSIOM_IO6_SEL__SIZE, 0x00000004 +.set CYFLD_HSIOM_IO7_SEL__OFFSET, 0x0000001c +.set CYFLD_HSIOM_IO7_SEL__SIZE, 0x00000004 +.set CYREG_HSIOM_PORT_SEL1, 0x40020100 +.set CYREG_HSIOM_PORT_SEL2, 0x40020200 +.set CYREG_HSIOM_PORT_SEL3, 0x40020300 +.set CYREG_HSIOM_PORT_SEL4, 0x40020400 +.set CYREG_HSIOM_PORT_SEL5, 0x40020500 +.set CYREG_HSIOM_PORT_SEL6, 0x40020600 +.set CYREG_HSIOM_PORT_SEL7, 0x40020700 +.set CYREG_HSIOM_AMUX_SPLIT_CTL0, 0x40022100 +.set CYFLD_HSIOM_SWITCH_AA_SL__OFFSET, 0x00000000 +.set CYFLD_HSIOM_SWITCH_AA_SL__SIZE, 0x00000001 +.set CYFLD_HSIOM_SWITCH_AA_SR__OFFSET, 0x00000001 +.set CYFLD_HSIOM_SWITCH_AA_SR__SIZE, 0x00000001 +.set CYFLD_HSIOM_SWITCH_AA_S0__OFFSET, 0x00000002 +.set CYFLD_HSIOM_SWITCH_AA_S0__SIZE, 0x00000001 +.set CYFLD_HSIOM_SWITCH_BB_SL__OFFSET, 0x00000004 +.set CYFLD_HSIOM_SWITCH_BB_SL__SIZE, 0x00000001 +.set CYFLD_HSIOM_SWITCH_BB_SR__OFFSET, 0x00000005 +.set CYFLD_HSIOM_SWITCH_BB_SR__SIZE, 0x00000001 +.set CYFLD_HSIOM_SWITCH_BB_S0__OFFSET, 0x00000006 +.set CYFLD_HSIOM_SWITCH_BB_S0__SIZE, 0x00000001 +.set CYREG_HSIOM_AMUX_SPLIT_CTL1, 0x40022104 +.set CYREG_PWR_CONTROL, 0x40030000 +.set CYFLD__POWER_MODE__OFFSET, 0x00000000 +.set CYFLD__POWER_MODE__SIZE, 0x00000004 +.set CYVAL__POWER_MODE_RESET, 0x00000000 +.set CYVAL__POWER_MODE_ACTIVE, 0x00000001 +.set CYVAL__POWER_MODE_SLEEP, 0x00000002 +.set CYVAL__POWER_MODE_DEEP_SLEEP, 0x00000003 +.set CYFLD__DEBUG_SESSION__OFFSET, 0x00000004 +.set CYFLD__DEBUG_SESSION__SIZE, 0x00000001 +.set CYVAL__DEBUG_SESSION_NO_SESSION, 0x00000000 +.set CYVAL__DEBUG_SESSION_SESSION_ACTIVE, 0x00000001 +.set CYFLD__LPM_READY__OFFSET, 0x00000005 +.set CYFLD__LPM_READY__SIZE, 0x00000001 +.set CYFLD__OVER_TEMP_EN__OFFSET, 0x00000010 +.set CYFLD__OVER_TEMP_EN__SIZE, 0x00000001 +.set CYFLD__OVER_TEMP_THRESH__OFFSET, 0x00000011 +.set CYFLD__OVER_TEMP_THRESH__SIZE, 0x00000001 +.set CYFLD__SPARE__OFFSET, 0x00000012 +.set CYFLD__SPARE__SIZE, 0x00000002 +.set CYFLD__EXT_VCCD__OFFSET, 0x00000017 +.set CYFLD__EXT_VCCD__SIZE, 0x00000001 +.set CYREG_PWR_KEY_DELAY, 0x40030004 +.set CYFLD__WAKEUP_HOLDOFF__OFFSET, 0x00000000 +.set CYFLD__WAKEUP_HOLDOFF__SIZE, 0x0000000a +.set CYREG_PWR_DDFT_SELECT, 0x4003000c +.set CYFLD__DDFT0_SEL__OFFSET, 0x00000000 +.set CYFLD__DDFT0_SEL__SIZE, 0x00000004 +.set CYVAL__DDFT0_SEL_WAKEUP, 0x00000000 +.set CYVAL__DDFT0_SEL_AWAKE, 0x00000001 +.set CYVAL__DDFT0_SEL_ACT_POWER_EN, 0x00000002 +.set CYVAL__DDFT0_SEL_ACT_POWER_UP, 0x00000003 +.set CYVAL__DDFT0_SEL_ACT_POWER_GOOD, 0x00000004 +.set CYVAL__DDFT0_SEL_ACT_REF_EN, 0x00000005 +.set CYVAL__DDFT0_SEL_ACT_COMP_EN, 0x00000006 +.set CYVAL__DDFT0_SEL_DPSLP_REF_EN, 0x00000007 +.set CYVAL__DDFT0_SEL_DPSLP_REG_EN, 0x00000008 +.set CYVAL__DDFT0_SEL_DPSLP_COMP_EN, 0x00000009 +.set CYVAL__DDFT0_SEL_OVER_TEMP_EN, 0x0000000a +.set CYVAL__DDFT0_SEL_SLEEPHOLDREQ_N, 0x0000000b +.set CYVAL__DDFT0_SEL_ADFT_BUF_EN, 0x0000000c +.set CYVAL__DDFT0_SEL_ATPG_OBSERVE, 0x0000000d +.set CYVAL__DDFT0_SEL_GND, 0x0000000e +.set CYVAL__DDFT0_SEL_PWR, 0x0000000f +.set CYFLD__DDFT1_SEL__OFFSET, 0x00000004 +.set CYFLD__DDFT1_SEL__SIZE, 0x00000004 +.set CYVAL__DDFT1_SEL_WAKEUP, 0x00000000 +.set CYVAL__DDFT1_SEL_AWAKE, 0x00000001 +.set CYVAL__DDFT1_SEL_ACT_POWER_EN, 0x00000002 +.set CYVAL__DDFT1_SEL_ACT_POWER_UP, 0x00000003 +.set CYVAL__DDFT1_SEL_ACT_POWER_GOOD, 0x00000004 +.set CYVAL__DDFT1_SEL_ACT_REF_VALID, 0x00000005 +.set CYVAL__DDFT1_SEL_ACT_REG_VALID, 0x00000006 +.set CYVAL__DDFT1_SEL_ACT_COMP_OUT, 0x00000007 +.set CYVAL__DDFT1_SEL_ACT_TEMP_HIGH, 0x00000008 +.set CYVAL__DDFT1_SEL_DPSLP_COMP_OUT, 0x00000009 +.set CYVAL__DDFT1_SEL_DPSLP_POWER_UP, 0x0000000a +.set CYVAL__DDFT1_SEL_AWAKE_DELAYED, 0x0000000b +.set CYVAL__DDFT1_SEL_LPM_READY, 0x0000000c +.set CYVAL__DDFT1_SEL_SLEEPHOLDACK_N, 0x0000000d +.set CYVAL__DDFT1_SEL_GND, 0x0000000e +.set CYVAL__DDFT1_SEL_PWR, 0x0000000f +.set CYREG_TST_MODE, 0x40030014 +.set CYFLD__SWD_CONNECTED__OFFSET, 0x00000002 +.set CYFLD__SWD_CONNECTED__SIZE, 0x00000001 +.set CYFLD__BLOCK_ALT_XRES__OFFSET, 0x0000001c +.set CYFLD__BLOCK_ALT_XRES__SIZE, 0x00000001 +.set CYFLD__TEST_KEY_DFT_EN__OFFSET, 0x0000001e +.set CYFLD__TEST_KEY_DFT_EN__SIZE, 0x00000001 +.set CYFLD__TEST_MODE__OFFSET, 0x0000001f +.set CYFLD__TEST_MODE__SIZE, 0x00000001 +.set CYREG_TST_DDFT_CTRL, 0x40030018 +.set CYFLD__DFT_SEL0__OFFSET, 0x00000000 +.set CYFLD__DFT_SEL0__SIZE, 0x00000004 +.set CYVAL__DFT_SEL0_SRC0, 0x00000000 +.set CYVAL__DFT_SEL0_SRC1, 0x00000001 +.set CYVAL__DFT_SEL0_SRC2, 0x00000002 +.set CYVAL__DFT_SEL0_SRC3, 0x00000003 +.set CYVAL__DFT_SEL0_SRC4, 0x00000004 +.set CYVAL__DFT_SEL0_SRC5, 0x00000005 +.set CYVAL__DFT_SEL0_SRC6, 0x00000006 +.set CYVAL__DFT_SEL0_SRC7, 0x00000007 +.set CYVAL__DFT_SEL0_CLK0, 0x00000008 +.set CYVAL__DFT_SEL0_CLK1, 0x00000009 +.set CYVAL__DFT_SEL0_PWR0, 0x0000000a +.set CYVAL__DFT_SEL0_PWR1, 0x0000000b +.set CYVAL__DFT_SEL0_RES0, 0x0000000c +.set CYVAL__DFT_SEL0_RES1, 0x0000000d +.set CYVAL__DFT_SEL0_ADFT_COMP, 0x0000000e +.set CYVAL__DFT_SEL0_VSS, 0x0000000f +.set CYFLD__DFT_SEL1__OFFSET, 0x00000008 +.set CYFLD__DFT_SEL1__SIZE, 0x00000004 +.set CYVAL__DFT_SEL1_SRC0, 0x00000000 +.set CYVAL__DFT_SEL1_SRC1, 0x00000001 +.set CYVAL__DFT_SEL1_SRC2, 0x00000002 +.set CYVAL__DFT_SEL1_SRC3, 0x00000003 +.set CYVAL__DFT_SEL1_SRC4, 0x00000004 +.set CYVAL__DFT_SEL1_SRC5, 0x00000005 +.set CYVAL__DFT_SEL1_SRC6, 0x00000006 +.set CYVAL__DFT_SEL1_SRC7, 0x00000007 +.set CYVAL__DFT_SEL1_CLK0, 0x00000008 +.set CYVAL__DFT_SEL1_CLK1, 0x00000009 +.set CYVAL__DFT_SEL1_PWR0, 0x0000000a +.set CYVAL__DFT_SEL1_PWR1, 0x0000000b +.set CYVAL__DFT_SEL1_RES0, 0x0000000c +.set CYVAL__DFT_SEL1_RES1, 0x0000000d +.set CYVAL__DFT_SEL1_ADFT_COMP, 0x0000000e +.set CYVAL__DFT_SEL1_VSS, 0x0000000f +.set CYFLD__ENABLE__OFFSET, 0x0000001f +.set CYFLD__ENABLE__SIZE, 0x00000001 +.set CYREG_TST_TRIM_CNTR1, 0x4003001c +.set CYFLD__COUNTER__OFFSET, 0x00000000 +.set CYFLD__COUNTER__SIZE, 0x00000010 +.set CYFLD__COUNTER_DONE__OFFSET, 0x0000001f +.set CYFLD__COUNTER_DONE__SIZE, 0x00000001 +.set CYREG_TST_TRIM_CNTR2, 0x40030020 +.set CYREG_TST_ADFT_CTRL, 0x40030024 +.set CYFLD__BUF_AUTO_ZERO__OFFSET, 0x00000000 +.set CYFLD__BUF_AUTO_ZERO__SIZE, 0x00000001 +.set CYFLD__BUF_MODE__OFFSET, 0x00000008 +.set CYFLD__BUF_MODE__SIZE, 0x00000002 +.set CYFLD__BUF_COMP_OUT__OFFSET, 0x00000010 +.set CYFLD__BUF_COMP_OUT__SIZE, 0x00000001 +.set CYFLD__BUF_EN__OFFSET, 0x0000001f +.set CYFLD__BUF_EN__SIZE, 0x00000001 +.set CYREG_CLK_SELECT, 0x40030028 +.set CYFLD__HFCLK_SEL__OFFSET, 0x00000000 +.set CYFLD__HFCLK_SEL__SIZE, 0x00000002 +.set CYVAL__HFCLK_SEL_IMO, 0x00000000 +.set CYVAL__HFCLK_SEL_EXTCLK, 0x00000001 +.set CYVAL__HFCLK_SEL_ECO, 0x00000002 +.set CYFLD__HFCLK_DIV__OFFSET, 0x00000002 +.set CYFLD__HFCLK_DIV__SIZE, 0x00000002 +.set CYVAL__HFCLK_DIV_NO_DIV, 0x00000000 +.set CYVAL__HFCLK_DIV_DIV_BY_2, 0x00000001 +.set CYVAL__HFCLK_DIV_DIV_BY_4, 0x00000002 +.set CYVAL__HFCLK_DIV_DIV_BY_8, 0x00000003 +.set CYFLD__PUMP_SEL__OFFSET, 0x00000004 +.set CYFLD__PUMP_SEL__SIZE, 0x00000002 +.set CYVAL__PUMP_SEL_GND, 0x00000000 +.set CYVAL__PUMP_SEL_IMO, 0x00000001 +.set CYVAL__PUMP_SEL_HFCLK, 0x00000002 +.set CYFLD__SYSCLK_DIV__OFFSET, 0x00000006 +.set CYFLD__SYSCLK_DIV__SIZE, 0x00000002 +.set CYVAL__SYSCLK_DIV_NO_DIV, 0x00000000 +.set CYVAL__SYSCLK_DIV_DIV_BY_2, 0x00000001 +.set CYVAL__SYSCLK_DIV_DIV_BY_4, 0x00000002 +.set CYVAL__SYSCLK_DIV_DIV_BY_8, 0x00000003 +.set CYREG_CLK_ILO_CONFIG, 0x4003002c +.set CYREG_CLK_IMO_CONFIG, 0x40030030 +.set CYREG_CLK_DFT_SELECT, 0x40030034 +.set CYFLD__DFT_DIV0__OFFSET, 0x00000004 +.set CYFLD__DFT_DIV0__SIZE, 0x00000002 +.set CYVAL__DFT_DIV0_NO_DIV, 0x00000000 +.set CYVAL__DFT_DIV0_DIV_BY_2, 0x00000001 +.set CYVAL__DFT_DIV0_DIV_BY_4, 0x00000002 +.set CYVAL__DFT_DIV0_DIV_BY_8, 0x00000003 +.set CYFLD__DFT_EDGE0__OFFSET, 0x00000006 +.set CYFLD__DFT_EDGE0__SIZE, 0x00000001 +.set CYVAL__DFT_EDGE0_POSEDGE, 0x00000000 +.set CYVAL__DFT_EDGE0_NEGEDGE, 0x00000001 +.set CYFLD__DFT_DIV1__OFFSET, 0x0000000c +.set CYFLD__DFT_DIV1__SIZE, 0x00000002 +.set CYVAL__DFT_DIV1_NO_DIV, 0x00000000 +.set CYVAL__DFT_DIV1_DIV_BY_2, 0x00000001 +.set CYVAL__DFT_DIV1_DIV_BY_4, 0x00000002 +.set CYVAL__DFT_DIV1_DIV_BY_8, 0x00000003 +.set CYFLD__DFT_EDGE1__OFFSET, 0x0000000e +.set CYFLD__DFT_EDGE1__SIZE, 0x00000001 +.set CYVAL__DFT_EDGE1_POSEDGE, 0x00000000 +.set CYVAL__DFT_EDGE1_NEGEDGE, 0x00000001 +.set CYREG_WDT_DISABLE_KEY, 0x40030038 +.set CYFLD__KEY__OFFSET, 0x00000000 +.set CYFLD__KEY__SIZE, 0x00000020 +.set CYREG_WDT_COUNTER, 0x4003003c +.set CYREG_WDT_MATCH, 0x40030040 +.set CYFLD__MATCH__OFFSET, 0x00000000 +.set CYFLD__MATCH__SIZE, 0x00000010 +.set CYFLD__IGNORE_BITS__OFFSET, 0x00000010 +.set CYFLD__IGNORE_BITS__SIZE, 0x00000004 +.set CYREG_SRSS_INTR, 0x40030044 +.set CYFLD__WDT_MATCH__OFFSET, 0x00000000 +.set CYFLD__WDT_MATCH__SIZE, 0x00000001 +.set CYFLD__TEMP_HIGH__OFFSET, 0x00000001 +.set CYFLD__TEMP_HIGH__SIZE, 0x00000001 +.set CYREG_SRSS_INTR_SET, 0x40030048 +.set CYREG_SRSS_INTR_MASK, 0x4003004c +.set CYREG_RES_CAUSE, 0x40030054 +.set CYFLD__RESET_WDT__OFFSET, 0x00000000 +.set CYFLD__RESET_WDT__SIZE, 0x00000001 +.set CYFLD__RESET_PROT_FAULT__OFFSET, 0x00000003 +.set CYFLD__RESET_PROT_FAULT__SIZE, 0x00000001 +.set CYFLD__RESET_SOFT__OFFSET, 0x00000004 +.set CYFLD__RESET_SOFT__SIZE, 0x00000001 +.set CYREG_PWR_BG_TRIM1, 0x40030f00 +.set CYFLD__REF_VTRIM__OFFSET, 0x00000000 +.set CYFLD__REF_VTRIM__SIZE, 0x00000006 +.set CYREG_PWR_BG_TRIM2, 0x40030f04 +.set CYFLD__REF_ITRIM__OFFSET, 0x00000000 +.set CYFLD__REF_ITRIM__SIZE, 0x00000006 +.set CYREG_CLK_IMO_SELECT, 0x40030f08 +.set CYFLD__FREQ__OFFSET, 0x00000000 +.set CYFLD__FREQ__SIZE, 0x00000003 +.set CYVAL__FREQ_24_MHZ, 0x00000000 +.set CYVAL__FREQ_28_MHZ, 0x00000001 +.set CYVAL__FREQ_32_MHZ, 0x00000002 +.set CYVAL__FREQ_36_MHZ, 0x00000003 +.set CYVAL__FREQ_40_MHZ, 0x00000004 +.set CYVAL__FREQ_44_MHZ, 0x00000005 +.set CYVAL__FREQ_48_MHZ, 0x00000006 +.set CYREG_CLK_IMO_TRIM1, 0x40030f0c +.set CYFLD__OFFSET__OFFSET, 0x00000000 +.set CYFLD__OFFSET__SIZE, 0x00000008 +.set CYREG_CLK_IMO_TRIM2, 0x40030f10 +.set CYFLD__FSOFFSET__OFFSET, 0x00000000 +.set CYFLD__FSOFFSET__SIZE, 0x00000003 +.set CYREG_PWR_PWRSYS_TRIM1, 0x40030f14 +.set CYFLD__DPSLP_REF_TRIM__OFFSET, 0x00000000 +.set CYFLD__DPSLP_REF_TRIM__SIZE, 0x00000004 +.set CYFLD__SPARE_TRIM__OFFSET, 0x00000004 +.set CYFLD__SPARE_TRIM__SIZE, 0x00000004 +.set CYREG_CLK_IMO_TRIM3, 0x40030f18 +.set CYFLD__STEPSIZE__OFFSET, 0x00000000 +.set CYFLD__STEPSIZE__SIZE, 0x00000005 +.set CYFLD__TCTRIM__OFFSET, 0x00000005 +.set CYFLD__TCTRIM__SIZE, 0x00000002 +.set CYDEV_GPIO_BASE, 0x40040000 +.set CYDEV_GPIO_SIZE, 0x00004000 +.set CYDEV_GPIO_PRT0_BASE, 0x40040000 +.set CYDEV_GPIO_PRT0_SIZE, 0x00000100 +.set CYREG_GPIO_PRT0_DR, 0x40040000 +.set CYFLD_GPIO_PRT_DATA0__OFFSET, 0x00000000 +.set CYFLD_GPIO_PRT_DATA0__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_DATA1__OFFSET, 0x00000001 +.set CYFLD_GPIO_PRT_DATA1__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_DATA2__OFFSET, 0x00000002 +.set CYFLD_GPIO_PRT_DATA2__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_DATA3__OFFSET, 0x00000003 +.set CYFLD_GPIO_PRT_DATA3__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_DATA4__OFFSET, 0x00000004 +.set CYFLD_GPIO_PRT_DATA4__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_DATA5__OFFSET, 0x00000005 +.set CYFLD_GPIO_PRT_DATA5__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_DATA6__OFFSET, 0x00000006 +.set CYFLD_GPIO_PRT_DATA6__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_DATA7__OFFSET, 0x00000007 +.set CYFLD_GPIO_PRT_DATA7__SIZE, 0x00000001 +.set CYREG_GPIO_PRT0_PS, 0x40040004 +.set CYFLD_GPIO_PRT_FLT_DATA__OFFSET, 0x00000008 +.set CYFLD_GPIO_PRT_FLT_DATA__SIZE, 0x00000001 +.set CYREG_GPIO_PRT0_PC, 0x40040008 +.set CYFLD_GPIO_PRT_DM0__OFFSET, 0x00000000 +.set CYFLD_GPIO_PRT_DM0__SIZE, 0x00000003 +.set CYVAL_GPIO_PRT_DM0_OFF, 0x00000000 +.set CYVAL_GPIO_PRT_DM0_INPUT, 0x00000001 +.set CYVAL_GPIO_PRT_DM0_0_PU, 0x00000002 +.set CYVAL_GPIO_PRT_DM0_PD_1, 0x00000003 +.set CYVAL_GPIO_PRT_DM0_0_Z, 0x00000004 +.set CYVAL_GPIO_PRT_DM0_Z_1, 0x00000005 +.set CYVAL_GPIO_PRT_DM0_0_1, 0x00000006 +.set CYVAL_GPIO_PRT_DM0_PD_PU, 0x00000007 +.set CYFLD_GPIO_PRT_DM1__OFFSET, 0x00000003 +.set CYFLD_GPIO_PRT_DM1__SIZE, 0x00000003 +.set CYFLD_GPIO_PRT_DM2__OFFSET, 0x00000006 +.set CYFLD_GPIO_PRT_DM2__SIZE, 0x00000003 +.set CYFLD_GPIO_PRT_DM3__OFFSET, 0x00000009 +.set CYFLD_GPIO_PRT_DM3__SIZE, 0x00000003 +.set CYFLD_GPIO_PRT_DM4__OFFSET, 0x0000000c +.set CYFLD_GPIO_PRT_DM4__SIZE, 0x00000003 +.set CYFLD_GPIO_PRT_DM5__OFFSET, 0x0000000f +.set CYFLD_GPIO_PRT_DM5__SIZE, 0x00000003 +.set CYFLD_GPIO_PRT_DM6__OFFSET, 0x00000012 +.set CYFLD_GPIO_PRT_DM6__SIZE, 0x00000003 +.set CYFLD_GPIO_PRT_DM7__OFFSET, 0x00000015 +.set CYFLD_GPIO_PRT_DM7__SIZE, 0x00000003 +.set CYFLD_GPIO_PRT_PORT_VTRIP_SEL__OFFSET, 0x00000018 +.set CYFLD_GPIO_PRT_PORT_VTRIP_SEL__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_PORT_SLOW__OFFSET, 0x00000019 +.set CYFLD_GPIO_PRT_PORT_SLOW__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__OFFSET, 0x0000001e +.set CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__SIZE, 0x00000002 +.set CYREG_GPIO_PRT0_INTR_CFG, 0x4004000c +.set CYFLD_GPIO_PRT_EDGE0_SEL__OFFSET, 0x00000000 +.set CYFLD_GPIO_PRT_EDGE0_SEL__SIZE, 0x00000002 +.set CYVAL_GPIO_PRT_EDGE0_SEL_DISABLE, 0x00000000 +.set CYVAL_GPIO_PRT_EDGE0_SEL_RISING, 0x00000001 +.set CYVAL_GPIO_PRT_EDGE0_SEL_FALLING, 0x00000002 +.set CYVAL_GPIO_PRT_EDGE0_SEL_BOTH, 0x00000003 +.set CYFLD_GPIO_PRT_EDGE1_SEL__OFFSET, 0x00000002 +.set CYFLD_GPIO_PRT_EDGE1_SEL__SIZE, 0x00000002 +.set CYFLD_GPIO_PRT_EDGE2_SEL__OFFSET, 0x00000004 +.set CYFLD_GPIO_PRT_EDGE2_SEL__SIZE, 0x00000002 +.set CYFLD_GPIO_PRT_EDGE3_SEL__OFFSET, 0x00000006 +.set CYFLD_GPIO_PRT_EDGE3_SEL__SIZE, 0x00000002 +.set CYFLD_GPIO_PRT_EDGE4_SEL__OFFSET, 0x00000008 +.set CYFLD_GPIO_PRT_EDGE4_SEL__SIZE, 0x00000002 +.set CYFLD_GPIO_PRT_EDGE5_SEL__OFFSET, 0x0000000a +.set CYFLD_GPIO_PRT_EDGE5_SEL__SIZE, 0x00000002 +.set CYFLD_GPIO_PRT_EDGE6_SEL__OFFSET, 0x0000000c +.set CYFLD_GPIO_PRT_EDGE6_SEL__SIZE, 0x00000002 +.set CYFLD_GPIO_PRT_EDGE7_SEL__OFFSET, 0x0000000e +.set CYFLD_GPIO_PRT_EDGE7_SEL__SIZE, 0x00000002 +.set CYFLD_GPIO_PRT_FLT_EDGE_SEL__OFFSET, 0x00000010 +.set CYFLD_GPIO_PRT_FLT_EDGE_SEL__SIZE, 0x00000002 +.set CYVAL_GPIO_PRT_FLT_EDGE_SEL_DISABLE, 0x00000000 +.set CYVAL_GPIO_PRT_FLT_EDGE_SEL_RISING, 0x00000001 +.set CYVAL_GPIO_PRT_FLT_EDGE_SEL_FALLING, 0x00000002 +.set CYVAL_GPIO_PRT_FLT_EDGE_SEL_BOTH, 0x00000003 +.set CYFLD_GPIO_PRT_FLT_SEL__OFFSET, 0x00000012 +.set CYFLD_GPIO_PRT_FLT_SEL__SIZE, 0x00000003 +.set CYREG_GPIO_PRT0_INTR, 0x40040010 +.set CYFLD_GPIO_PRT_PS_DATA0__OFFSET, 0x00000010 +.set CYFLD_GPIO_PRT_PS_DATA0__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_PS_DATA1__OFFSET, 0x00000011 +.set CYFLD_GPIO_PRT_PS_DATA1__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_PS_DATA2__OFFSET, 0x00000012 +.set CYFLD_GPIO_PRT_PS_DATA2__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_PS_DATA3__OFFSET, 0x00000013 +.set CYFLD_GPIO_PRT_PS_DATA3__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_PS_DATA4__OFFSET, 0x00000014 +.set CYFLD_GPIO_PRT_PS_DATA4__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_PS_DATA5__OFFSET, 0x00000015 +.set CYFLD_GPIO_PRT_PS_DATA5__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_PS_DATA6__OFFSET, 0x00000016 +.set CYFLD_GPIO_PRT_PS_DATA6__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_PS_DATA7__OFFSET, 0x00000017 +.set CYFLD_GPIO_PRT_PS_DATA7__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_PS_FLT_DATA__OFFSET, 0x00000018 +.set CYFLD_GPIO_PRT_PS_FLT_DATA__SIZE, 0x00000001 +.set CYREG_GPIO_PRT0_PC2, 0x40040018 +.set CYFLD_GPIO_PRT_INP_DIS0__OFFSET, 0x00000000 +.set CYFLD_GPIO_PRT_INP_DIS0__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_INP_DIS1__OFFSET, 0x00000001 +.set CYFLD_GPIO_PRT_INP_DIS1__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_INP_DIS2__OFFSET, 0x00000002 +.set CYFLD_GPIO_PRT_INP_DIS2__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_INP_DIS3__OFFSET, 0x00000003 +.set CYFLD_GPIO_PRT_INP_DIS3__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_INP_DIS4__OFFSET, 0x00000004 +.set CYFLD_GPIO_PRT_INP_DIS4__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_INP_DIS5__OFFSET, 0x00000005 +.set CYFLD_GPIO_PRT_INP_DIS5__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_INP_DIS6__OFFSET, 0x00000006 +.set CYFLD_GPIO_PRT_INP_DIS6__SIZE, 0x00000001 +.set CYFLD_GPIO_PRT_INP_DIS7__OFFSET, 0x00000007 +.set CYFLD_GPIO_PRT_INP_DIS7__SIZE, 0x00000001 +.set CYREG_GPIO_PRT0_DR_SET, 0x40040040 +.set CYFLD_GPIO_PRT_DATA__OFFSET, 0x00000000 +.set CYFLD_GPIO_PRT_DATA__SIZE, 0x00000008 +.set CYREG_GPIO_PRT0_DR_CLR, 0x40040044 +.set CYREG_GPIO_PRT0_DR_INV, 0x40040048 +.set CYDEV_GPIO_PRT1_BASE, 0x40040100 +.set CYDEV_GPIO_PRT1_SIZE, 0x00000100 +.set CYREG_GPIO_PRT1_DR, 0x40040100 +.set CYREG_GPIO_PRT1_PS, 0x40040104 +.set CYREG_GPIO_PRT1_PC, 0x40040108 +.set CYREG_GPIO_PRT1_INTR_CFG, 0x4004010c +.set CYREG_GPIO_PRT1_INTR, 0x40040110 +.set CYREG_GPIO_PRT1_PC2, 0x40040118 +.set CYREG_GPIO_PRT1_DR_SET, 0x40040140 +.set CYREG_GPIO_PRT1_DR_CLR, 0x40040144 +.set CYREG_GPIO_PRT1_DR_INV, 0x40040148 +.set CYDEV_GPIO_PRT2_BASE, 0x40040200 +.set CYDEV_GPIO_PRT2_SIZE, 0x00000100 +.set CYREG_GPIO_PRT2_DR, 0x40040200 +.set CYREG_GPIO_PRT2_PS, 0x40040204 +.set CYREG_GPIO_PRT2_PC, 0x40040208 +.set CYREG_GPIO_PRT2_INTR_CFG, 0x4004020c +.set CYREG_GPIO_PRT2_INTR, 0x40040210 +.set CYREG_GPIO_PRT2_PC2, 0x40040218 +.set CYREG_GPIO_PRT2_DR_SET, 0x40040240 +.set CYREG_GPIO_PRT2_DR_CLR, 0x40040244 +.set CYREG_GPIO_PRT2_DR_INV, 0x40040248 +.set CYDEV_GPIO_PRT3_BASE, 0x40040300 +.set CYDEV_GPIO_PRT3_SIZE, 0x00000100 +.set CYREG_GPIO_PRT3_DR, 0x40040300 +.set CYREG_GPIO_PRT3_PS, 0x40040304 +.set CYREG_GPIO_PRT3_PC, 0x40040308 +.set CYREG_GPIO_PRT3_INTR_CFG, 0x4004030c +.set CYREG_GPIO_PRT3_INTR, 0x40040310 +.set CYREG_GPIO_PRT3_PC2, 0x40040318 +.set CYREG_GPIO_PRT3_DR_SET, 0x40040340 +.set CYREG_GPIO_PRT3_DR_CLR, 0x40040344 +.set CYREG_GPIO_PRT3_DR_INV, 0x40040348 +.set CYDEV_GPIO_PRT4_BASE, 0x40040400 +.set CYDEV_GPIO_PRT4_SIZE, 0x00000100 +.set CYREG_GPIO_PRT4_DR, 0x40040400 +.set CYREG_GPIO_PRT4_PS, 0x40040404 +.set CYREG_GPIO_PRT4_PC, 0x40040408 +.set CYREG_GPIO_PRT4_INTR_CFG, 0x4004040c +.set CYREG_GPIO_PRT4_INTR, 0x40040410 +.set CYREG_GPIO_PRT4_PC2, 0x40040418 +.set CYREG_GPIO_PRT4_DR_SET, 0x40040440 +.set CYREG_GPIO_PRT4_DR_CLR, 0x40040444 +.set CYREG_GPIO_PRT4_DR_INV, 0x40040448 +.set CYDEV_GPIO_PRT5_BASE, 0x40040500 +.set CYDEV_GPIO_PRT5_SIZE, 0x00000100 +.set CYREG_GPIO_PRT5_DR, 0x40040500 +.set CYREG_GPIO_PRT5_PS, 0x40040504 +.set CYREG_GPIO_PRT5_PC, 0x40040508 +.set CYREG_GPIO_PRT5_INTR_CFG, 0x4004050c +.set CYREG_GPIO_PRT5_INTR, 0x40040510 +.set CYREG_GPIO_PRT5_PC2, 0x40040518 +.set CYREG_GPIO_PRT5_DR_SET, 0x40040540 +.set CYREG_GPIO_PRT5_DR_CLR, 0x40040544 +.set CYREG_GPIO_PRT5_DR_INV, 0x40040548 +.set CYDEV_GPIO_PRT6_BASE, 0x40040600 +.set CYDEV_GPIO_PRT6_SIZE, 0x00000100 +.set CYREG_GPIO_PRT6_DR, 0x40040600 +.set CYREG_GPIO_PRT6_PS, 0x40040604 +.set CYREG_GPIO_PRT6_PC, 0x40040608 +.set CYREG_GPIO_PRT6_INTR_CFG, 0x4004060c +.set CYREG_GPIO_PRT6_INTR, 0x40040610 +.set CYREG_GPIO_PRT6_PC2, 0x40040618 +.set CYREG_GPIO_PRT6_DR_SET, 0x40040640 +.set CYREG_GPIO_PRT6_DR_CLR, 0x40040644 +.set CYREG_GPIO_PRT6_DR_INV, 0x40040648 +.set CYDEV_GPIO_PRT7_BASE, 0x40040700 +.set CYDEV_GPIO_PRT7_SIZE, 0x00000100 +.set CYREG_GPIO_PRT7_DR, 0x40040700 +.set CYREG_GPIO_PRT7_PS, 0x40040704 +.set CYREG_GPIO_PRT7_PC, 0x40040708 +.set CYREG_GPIO_PRT7_INTR_CFG, 0x4004070c +.set CYREG_GPIO_PRT7_INTR, 0x40040710 +.set CYREG_GPIO_PRT7_PC2, 0x40040718 +.set CYREG_GPIO_PRT7_DR_SET, 0x40040740 +.set CYREG_GPIO_PRT7_DR_CLR, 0x40040744 +.set CYREG_GPIO_PRT7_DR_INV, 0x40040748 +.set CYREG_GPIO_INTR_CAUSE, 0x40041000 +.set CYFLD_GPIO_PORT_INT__OFFSET, 0x00000000 +.set CYFLD_GPIO_PORT_INT__SIZE, 0x00000008 +.set CYDEV_PRGIO_BASE, 0x40050000 +.set CYDEV_PRGIO_SIZE, 0x00001000 +.set CYDEV_PRGIO_PRT0_BASE, 0x40050000 +.set CYDEV_PRGIO_PRT0_SIZE, 0x00000100 +.set CYREG_PRGIO_PRT0_CTL, 0x40050000 +.set CYFLD_PRGIO_PRT_BYPASS__OFFSET, 0x00000000 +.set CYFLD_PRGIO_PRT_BYPASS__SIZE, 0x00000008 +.set CYFLD_PRGIO_PRT_CLOCK_SRC__OFFSET, 0x00000008 +.set CYFLD_PRGIO_PRT_CLOCK_SRC__SIZE, 0x00000005 +.set CYFLD_PRGIO_PRT_HLD_OVR__OFFSET, 0x00000018 +.set CYFLD_PRGIO_PRT_HLD_OVR__SIZE, 0x00000001 +.set CYFLD_PRGIO_PRT_PIPELINE_EN__OFFSET, 0x00000019 +.set CYFLD_PRGIO_PRT_PIPELINE_EN__SIZE, 0x00000001 +.set CYFLD_PRGIO_PRT_ENABLED__OFFSET, 0x0000001f +.set CYFLD_PRGIO_PRT_ENABLED__SIZE, 0x00000001 +.set CYREG_PRGIO_PRT0_SYNC_CTL, 0x40050010 +.set CYFLD_PRGIO_PRT_IO_SYNC_EN__OFFSET, 0x00000000 +.set CYFLD_PRGIO_PRT_IO_SYNC_EN__SIZE, 0x00000008 +.set CYFLD_PRGIO_PRT_CHIP_SYNC_EN__OFFSET, 0x00000008 +.set CYFLD_PRGIO_PRT_CHIP_SYNC_EN__SIZE, 0x00000008 +.set CYREG_PRGIO_PRT0_LUT_SEL0, 0x40050020 +.set CYFLD_PRGIO_PRT_LUT_TR0_SEL__OFFSET, 0x00000000 +.set CYFLD_PRGIO_PRT_LUT_TR0_SEL__SIZE, 0x00000004 +.set CYFLD_PRGIO_PRT_LUT_TR1_SEL__OFFSET, 0x00000008 +.set CYFLD_PRGIO_PRT_LUT_TR1_SEL__SIZE, 0x00000004 +.set CYFLD_PRGIO_PRT_LUT_TR2_SEL__OFFSET, 0x00000010 +.set CYFLD_PRGIO_PRT_LUT_TR2_SEL__SIZE, 0x00000004 +.set CYREG_PRGIO_PRT0_LUT_SEL1, 0x40050024 +.set CYREG_PRGIO_PRT0_LUT_SEL2, 0x40050028 +.set CYREG_PRGIO_PRT0_LUT_SEL3, 0x4005002c +.set CYREG_PRGIO_PRT0_LUT_SEL4, 0x40050030 +.set CYREG_PRGIO_PRT0_LUT_SEL5, 0x40050034 +.set CYREG_PRGIO_PRT0_LUT_SEL6, 0x40050038 +.set CYREG_PRGIO_PRT0_LUT_SEL7, 0x4005003c +.set CYREG_PRGIO_PRT0_LUT_CTL0, 0x40050040 +.set CYFLD_PRGIO_PRT_LUT__OFFSET, 0x00000000 +.set CYFLD_PRGIO_PRT_LUT__SIZE, 0x00000008 +.set CYFLD_PRGIO_PRT_LUT_OPC__OFFSET, 0x00000008 +.set CYFLD_PRGIO_PRT_LUT_OPC__SIZE, 0x00000002 +.set CYREG_PRGIO_PRT0_LUT_CTL1, 0x40050044 +.set CYREG_PRGIO_PRT0_LUT_CTL2, 0x40050048 +.set CYREG_PRGIO_PRT0_LUT_CTL3, 0x4005004c +.set CYREG_PRGIO_PRT0_LUT_CTL4, 0x40050050 +.set CYREG_PRGIO_PRT0_LUT_CTL5, 0x40050054 +.set CYREG_PRGIO_PRT0_LUT_CTL6, 0x40050058 +.set CYREG_PRGIO_PRT0_LUT_CTL7, 0x4005005c +.set CYREG_PRGIO_PRT0_DU_SEL, 0x400500c0 +.set CYFLD_PRGIO_PRT_DU_TR0_SEL__OFFSET, 0x00000000 +.set CYFLD_PRGIO_PRT_DU_TR0_SEL__SIZE, 0x00000004 +.set CYFLD_PRGIO_PRT_DU_TR1_SEL__OFFSET, 0x00000008 +.set CYFLD_PRGIO_PRT_DU_TR1_SEL__SIZE, 0x00000004 +.set CYFLD_PRGIO_PRT_DU_TR2_SEL__OFFSET, 0x00000010 +.set CYFLD_PRGIO_PRT_DU_TR2_SEL__SIZE, 0x00000004 +.set CYFLD_PRGIO_PRT_DU_DATA0_SEL__OFFSET, 0x00000018 +.set CYFLD_PRGIO_PRT_DU_DATA0_SEL__SIZE, 0x00000002 +.set CYFLD_PRGIO_PRT_DU_DATA1_SEL__OFFSET, 0x0000001c +.set CYFLD_PRGIO_PRT_DU_DATA1_SEL__SIZE, 0x00000002 +.set CYREG_PRGIO_PRT0_DU_CTL, 0x400500c4 +.set CYFLD_PRGIO_PRT_DU_SIZE__OFFSET, 0x00000000 +.set CYFLD_PRGIO_PRT_DU_SIZE__SIZE, 0x00000003 +.set CYFLD_PRGIO_PRT_DU_OPC__OFFSET, 0x00000008 +.set CYFLD_PRGIO_PRT_DU_OPC__SIZE, 0x00000004 +.set CYREG_PRGIO_PRT0_DATA, 0x400500f0 +.set CYFLD_PRGIO_PRT_DATA__OFFSET, 0x00000000 +.set CYFLD_PRGIO_PRT_DATA__SIZE, 0x00000008 +.set CYDEV_PRGIO_PRT1_BASE, 0x40050100 +.set CYDEV_PRGIO_PRT1_SIZE, 0x00000100 +.set CYREG_PRGIO_PRT1_CTL, 0x40050100 +.set CYREG_PRGIO_PRT1_SYNC_CTL, 0x40050110 +.set CYREG_PRGIO_PRT1_LUT_SEL0, 0x40050120 +.set CYREG_PRGIO_PRT1_LUT_SEL1, 0x40050124 +.set CYREG_PRGIO_PRT1_LUT_SEL2, 0x40050128 +.set CYREG_PRGIO_PRT1_LUT_SEL3, 0x4005012c +.set CYREG_PRGIO_PRT1_LUT_SEL4, 0x40050130 +.set CYREG_PRGIO_PRT1_LUT_SEL5, 0x40050134 +.set CYREG_PRGIO_PRT1_LUT_SEL6, 0x40050138 +.set CYREG_PRGIO_PRT1_LUT_SEL7, 0x4005013c +.set CYREG_PRGIO_PRT1_LUT_CTL0, 0x40050140 +.set CYREG_PRGIO_PRT1_LUT_CTL1, 0x40050144 +.set CYREG_PRGIO_PRT1_LUT_CTL2, 0x40050148 +.set CYREG_PRGIO_PRT1_LUT_CTL3, 0x4005014c +.set CYREG_PRGIO_PRT1_LUT_CTL4, 0x40050150 +.set CYREG_PRGIO_PRT1_LUT_CTL5, 0x40050154 +.set CYREG_PRGIO_PRT1_LUT_CTL6, 0x40050158 +.set CYREG_PRGIO_PRT1_LUT_CTL7, 0x4005015c +.set CYREG_PRGIO_PRT1_DU_SEL, 0x400501c0 +.set CYREG_PRGIO_PRT1_DU_CTL, 0x400501c4 +.set CYREG_PRGIO_PRT1_DATA, 0x400501f0 +.set CYDEV_PRGIO_PRT2_BASE, 0x40050200 +.set CYDEV_PRGIO_PRT2_SIZE, 0x00000100 +.set CYREG_PRGIO_PRT2_CTL, 0x40050200 +.set CYREG_PRGIO_PRT2_SYNC_CTL, 0x40050210 +.set CYREG_PRGIO_PRT2_LUT_SEL0, 0x40050220 +.set CYREG_PRGIO_PRT2_LUT_SEL1, 0x40050224 +.set CYREG_PRGIO_PRT2_LUT_SEL2, 0x40050228 +.set CYREG_PRGIO_PRT2_LUT_SEL3, 0x4005022c +.set CYREG_PRGIO_PRT2_LUT_SEL4, 0x40050230 +.set CYREG_PRGIO_PRT2_LUT_SEL5, 0x40050234 +.set CYREG_PRGIO_PRT2_LUT_SEL6, 0x40050238 +.set CYREG_PRGIO_PRT2_LUT_SEL7, 0x4005023c +.set CYREG_PRGIO_PRT2_LUT_CTL0, 0x40050240 +.set CYREG_PRGIO_PRT2_LUT_CTL1, 0x40050244 +.set CYREG_PRGIO_PRT2_LUT_CTL2, 0x40050248 +.set CYREG_PRGIO_PRT2_LUT_CTL3, 0x4005024c +.set CYREG_PRGIO_PRT2_LUT_CTL4, 0x40050250 +.set CYREG_PRGIO_PRT2_LUT_CTL5, 0x40050254 +.set CYREG_PRGIO_PRT2_LUT_CTL6, 0x40050258 +.set CYREG_PRGIO_PRT2_LUT_CTL7, 0x4005025c +.set CYREG_PRGIO_PRT2_DU_SEL, 0x400502c0 +.set CYREG_PRGIO_PRT2_DU_CTL, 0x400502c4 +.set CYREG_PRGIO_PRT2_DATA, 0x400502f0 +.set CYDEV_CPUSS_BASE, 0x40100000 +.set CYDEV_CPUSS_SIZE, 0x00001000 +.set CYREG_CPUSS_SYSREQ, 0x40100004 +.set CYFLD_CPUSS_SYSCALL_COMMAND__OFFSET, 0x00000000 +.set CYFLD_CPUSS_SYSCALL_COMMAND__SIZE, 0x00000010 +.set CYFLD_CPUSS_DIS_RESET_VECT_REL__OFFSET, 0x0000001b +.set CYFLD_CPUSS_DIS_RESET_VECT_REL__SIZE, 0x00000001 +.set CYFLD_CPUSS_PRIVILEGED__OFFSET, 0x0000001c +.set CYFLD_CPUSS_PRIVILEGED__SIZE, 0x00000001 +.set CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET, 0x0000001d +.set CYFLD_CPUSS_ROM_ACCESS_EN__SIZE, 0x00000001 +.set CYFLD_CPUSS_HMASTER_0__OFFSET, 0x0000001e +.set CYFLD_CPUSS_HMASTER_0__SIZE, 0x00000001 +.set CYFLD_CPUSS_SYSCALL_REQ__OFFSET, 0x0000001f +.set CYFLD_CPUSS_SYSCALL_REQ__SIZE, 0x00000001 +.set CYREG_CPUSS_SYSARG, 0x40100008 +.set CYFLD_CPUSS_SYSCALL_ARG__OFFSET, 0x00000000 +.set CYFLD_CPUSS_SYSCALL_ARG__SIZE, 0x00000020 +.set CYREG_CPUSS_PROTECTION, 0x4010000c +.set CYFLD_CPUSS_PROTECTION_MODE__OFFSET, 0x00000000 +.set CYFLD_CPUSS_PROTECTION_MODE__SIZE, 0x00000004 +.set CYFLD_CPUSS_FLASH_LOCK__OFFSET, 0x0000001e +.set CYFLD_CPUSS_FLASH_LOCK__SIZE, 0x00000001 +.set CYFLD_CPUSS_PROTECTION_LOCK__OFFSET, 0x0000001f +.set CYFLD_CPUSS_PROTECTION_LOCK__SIZE, 0x00000001 +.set CYREG_CPUSS_PRIV_ROM, 0x40100010 +.set CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET, 0x00000000 +.set CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE, 0x00000008 +.set CYREG_CPUSS_PRIV_RAM, 0x40100014 +.set CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET, 0x00000000 +.set CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE, 0x00000009 +.set CYREG_CPUSS_PRIV_FLASH, 0x40100018 +.set CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET, 0x00000000 +.set CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE, 0x0000000c +.set CYREG_CPUSS_WOUNDING, 0x4010001c +.set CYFLD_CPUSS_RAM_WOUND__OFFSET, 0x00000010 +.set CYFLD_CPUSS_RAM_WOUND__SIZE, 0x00000003 +.set CYFLD_CPUSS_FLASH_WOUND__OFFSET, 0x00000014 +.set CYFLD_CPUSS_FLASH_WOUND__SIZE, 0x00000003 +.set CYREG_CPUSS_FLASH_CTL, 0x40100030 +.set CYFLD_CPUSS_FLASH_WS__OFFSET, 0x00000000 +.set CYFLD_CPUSS_FLASH_WS__SIZE, 0x00000002 +.set CYFLD_CPUSS_PREF_EN__OFFSET, 0x00000004 +.set CYFLD_CPUSS_PREF_EN__SIZE, 0x00000001 +.set CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET, 0x00000008 +.set CYFLD_CPUSS_FLASH_INVALIDATE__SIZE, 0x00000001 +.set CYFLD_CPUSS_ARB__OFFSET, 0x00000010 +.set CYFLD_CPUSS_ARB__SIZE, 0x00000002 +.set CYREG_CPUSS_ROM_CTL, 0x40100034 +.set CYFLD_CPUSS_ROM_WS__OFFSET, 0x00000000 +.set CYFLD_CPUSS_ROM_WS__SIZE, 0x00000001 +.set CYREG_CPUSS_RAM_CTL, 0x40100038 +.set CYREG_CPUSS_DMAC_CTL, 0x4010003c +.set CYREG_CPUSS_SL_CTL0, 0x40100100 +.set CYREG_CPUSS_SL_CTL1, 0x40100104 +.set CYREG_CPUSS_SL_CTL2, 0x40100108 +.set CYDEV_DMAC_BASE, 0x40101000 +.set CYDEV_DMAC_SIZE, 0x00001000 +.set CYREG_DMAC_CTL, 0x40101000 +.set CYFLD_DMAC_ENABLED__OFFSET, 0x0000001f +.set CYFLD_DMAC_ENABLED__SIZE, 0x00000001 +.set CYREG_DMAC_STATUS, 0x40101010 +.set CYFLD_DMAC_DATA_NR__OFFSET, 0x00000000 +.set CYFLD_DMAC_DATA_NR__SIZE, 0x00000010 +.set CYFLD_DMAC_CH_ADDR__OFFSET, 0x00000010 +.set CYFLD_DMAC_CH_ADDR__SIZE, 0x00000003 +.set CYFLD_DMAC_STATE__OFFSET, 0x00000018 +.set CYFLD_DMAC_STATE__SIZE, 0x00000003 +.set CYFLD_DMAC_PRIO__OFFSET, 0x0000001c +.set CYFLD_DMAC_PRIO__SIZE, 0x00000002 +.set CYFLD_DMAC_PING_PONG__OFFSET, 0x0000001e +.set CYFLD_DMAC_PING_PONG__SIZE, 0x00000001 +.set CYFLD_DMAC_ACTIVE__OFFSET, 0x0000001f +.set CYFLD_DMAC_ACTIVE__SIZE, 0x00000001 +.set CYREG_DMAC_STATUS_SRC_ADDR, 0x40101014 +.set CYFLD_DMAC_ADDR__OFFSET, 0x00000000 +.set CYFLD_DMAC_ADDR__SIZE, 0x00000020 +.set CYREG_DMAC_STATUS_DST_ADDR, 0x40101018 +.set CYREG_DMAC_STATUS_CH_ACT, 0x4010101c +.set CYFLD_DMAC_CH__OFFSET, 0x00000000 +.set CYFLD_DMAC_CH__SIZE, 0x00000008 +.set CYREG_DMAC_CH_CTL0, 0x40101080 +.set CYREG_DMAC_CH_CTL1, 0x40101084 +.set CYREG_DMAC_CH_CTL2, 0x40101088 +.set CYREG_DMAC_CH_CTL3, 0x4010108c +.set CYREG_DMAC_CH_CTL4, 0x40101090 +.set CYREG_DMAC_CH_CTL5, 0x40101094 +.set CYREG_DMAC_CH_CTL6, 0x40101098 +.set CYREG_DMAC_CH_CTL7, 0x4010109c +.set CYREG_DMAC_INTR, 0x401017f0 +.set CYREG_DMAC_INTR_SET, 0x401017f4 +.set CYREG_DMAC_INTR_MASK, 0x401017f8 +.set CYREG_DMAC_INTR_MASKED, 0x401017fc +.set CYDEV_DMAC_DESCR0_BASE, 0x40101800 +.set CYDEV_DMAC_DESCR0_SIZE, 0x00000020 +.set CYREG_DMAC_DESCR0_PING_SRC, 0x40101800 +.set CYFLD_DMAC_DESCR_ADDR__OFFSET, 0x00000000 +.set CYFLD_DMAC_DESCR_ADDR__SIZE, 0x00000020 +.set CYREG_DMAC_DESCR0_PING_DST, 0x40101804 +.set CYREG_DMAC_DESCR0_PING_CTL, 0x40101808 +.set CYFLD_DMAC_DESCR_DATA_NR__OFFSET, 0x00000000 +.set CYFLD_DMAC_DESCR_DATA_NR__SIZE, 0x00000010 +.set CYFLD_DMAC_DESCR_DATA_SIZE__OFFSET, 0x00000010 +.set CYFLD_DMAC_DESCR_DATA_SIZE__SIZE, 0x00000002 +.set CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__OFFSET, 0x00000014 +.set CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__SIZE, 0x00000001 +.set CYFLD_DMAC_DESCR_DST_ADDR_INCR__OFFSET, 0x00000015 +.set CYFLD_DMAC_DESCR_DST_ADDR_INCR__SIZE, 0x00000001 +.set CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__OFFSET, 0x00000016 +.set CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__SIZE, 0x00000001 +.set CYFLD_DMAC_DESCR_SRC_ADDR_INCR__OFFSET, 0x00000017 +.set CYFLD_DMAC_DESCR_SRC_ADDR_INCR__SIZE, 0x00000001 +.set CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__OFFSET, 0x00000018 +.set CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__SIZE, 0x00000002 +.set CYFLD_DMAC_DESCR_INV_DESCR__OFFSET, 0x0000001a +.set CYFLD_DMAC_DESCR_INV_DESCR__SIZE, 0x00000001 +.set CYFLD_DMAC_DESCR_SET_CAUSE__OFFSET, 0x0000001b +.set CYFLD_DMAC_DESCR_SET_CAUSE__SIZE, 0x00000001 +.set CYFLD_DMAC_DESCR_PREEMPTABLE__OFFSET, 0x0000001c +.set CYFLD_DMAC_DESCR_PREEMPTABLE__SIZE, 0x00000001 +.set CYFLD_DMAC_DESCR_FLIPPING__OFFSET, 0x0000001d +.set CYFLD_DMAC_DESCR_FLIPPING__SIZE, 0x00000001 +.set CYFLD_DMAC_DESCR_OPCODE__OFFSET, 0x0000001e +.set CYFLD_DMAC_DESCR_OPCODE__SIZE, 0x00000002 +.set CYREG_DMAC_DESCR0_PING_STATUS, 0x4010180c +.set CYFLD_DMAC_DESCR_CURR_DATA_NR__OFFSET, 0x00000000 +.set CYFLD_DMAC_DESCR_CURR_DATA_NR__SIZE, 0x00000010 +.set CYFLD_DMAC_DESCR_RESPONSE__OFFSET, 0x00000010 +.set CYFLD_DMAC_DESCR_RESPONSE__SIZE, 0x00000003 +.set CYFLD_DMAC_DESCR_VALID__OFFSET, 0x0000001f +.set CYFLD_DMAC_DESCR_VALID__SIZE, 0x00000001 +.set CYREG_DMAC_DESCR0_PONG_SRC, 0x40101810 +.set CYREG_DMAC_DESCR0_PONG_DST, 0x40101814 +.set CYREG_DMAC_DESCR0_PONG_CTL, 0x40101818 +.set CYREG_DMAC_DESCR0_PONG_STATUS, 0x4010181c +.set CYDEV_DMAC_DESCR1_BASE, 0x40101820 +.set CYDEV_DMAC_DESCR1_SIZE, 0x00000020 +.set CYREG_DMAC_DESCR1_PING_SRC, 0x40101820 +.set CYREG_DMAC_DESCR1_PING_DST, 0x40101824 +.set CYREG_DMAC_DESCR1_PING_CTL, 0x40101828 +.set CYREG_DMAC_DESCR1_PING_STATUS, 0x4010182c +.set CYREG_DMAC_DESCR1_PONG_SRC, 0x40101830 +.set CYREG_DMAC_DESCR1_PONG_DST, 0x40101834 +.set CYREG_DMAC_DESCR1_PONG_CTL, 0x40101838 +.set CYREG_DMAC_DESCR1_PONG_STATUS, 0x4010183c +.set CYDEV_DMAC_DESCR2_BASE, 0x40101840 +.set CYDEV_DMAC_DESCR2_SIZE, 0x00000020 +.set CYREG_DMAC_DESCR2_PING_SRC, 0x40101840 +.set CYREG_DMAC_DESCR2_PING_DST, 0x40101844 +.set CYREG_DMAC_DESCR2_PING_CTL, 0x40101848 +.set CYREG_DMAC_DESCR2_PING_STATUS, 0x4010184c +.set CYREG_DMAC_DESCR2_PONG_SRC, 0x40101850 +.set CYREG_DMAC_DESCR2_PONG_DST, 0x40101854 +.set CYREG_DMAC_DESCR2_PONG_CTL, 0x40101858 +.set CYREG_DMAC_DESCR2_PONG_STATUS, 0x4010185c +.set CYDEV_DMAC_DESCR3_BASE, 0x40101860 +.set CYDEV_DMAC_DESCR3_SIZE, 0x00000020 +.set CYREG_DMAC_DESCR3_PING_SRC, 0x40101860 +.set CYREG_DMAC_DESCR3_PING_DST, 0x40101864 +.set CYREG_DMAC_DESCR3_PING_CTL, 0x40101868 +.set CYREG_DMAC_DESCR3_PING_STATUS, 0x4010186c +.set CYREG_DMAC_DESCR3_PONG_SRC, 0x40101870 +.set CYREG_DMAC_DESCR3_PONG_DST, 0x40101874 +.set CYREG_DMAC_DESCR3_PONG_CTL, 0x40101878 +.set CYREG_DMAC_DESCR3_PONG_STATUS, 0x4010187c +.set CYDEV_DMAC_DESCR4_BASE, 0x40101880 +.set CYDEV_DMAC_DESCR4_SIZE, 0x00000020 +.set CYREG_DMAC_DESCR4_PING_SRC, 0x40101880 +.set CYREG_DMAC_DESCR4_PING_DST, 0x40101884 +.set CYREG_DMAC_DESCR4_PING_CTL, 0x40101888 +.set CYREG_DMAC_DESCR4_PING_STATUS, 0x4010188c +.set CYREG_DMAC_DESCR4_PONG_SRC, 0x40101890 +.set CYREG_DMAC_DESCR4_PONG_DST, 0x40101894 +.set CYREG_DMAC_DESCR4_PONG_CTL, 0x40101898 +.set CYREG_DMAC_DESCR4_PONG_STATUS, 0x4010189c +.set CYDEV_DMAC_DESCR5_BASE, 0x401018a0 +.set CYDEV_DMAC_DESCR5_SIZE, 0x00000020 +.set CYREG_DMAC_DESCR5_PING_SRC, 0x401018a0 +.set CYREG_DMAC_DESCR5_PING_DST, 0x401018a4 +.set CYREG_DMAC_DESCR5_PING_CTL, 0x401018a8 +.set CYREG_DMAC_DESCR5_PING_STATUS, 0x401018ac +.set CYREG_DMAC_DESCR5_PONG_SRC, 0x401018b0 +.set CYREG_DMAC_DESCR5_PONG_DST, 0x401018b4 +.set CYREG_DMAC_DESCR5_PONG_CTL, 0x401018b8 +.set CYREG_DMAC_DESCR5_PONG_STATUS, 0x401018bc +.set CYDEV_DMAC_DESCR6_BASE, 0x401018c0 +.set CYDEV_DMAC_DESCR6_SIZE, 0x00000020 +.set CYREG_DMAC_DESCR6_PING_SRC, 0x401018c0 +.set CYREG_DMAC_DESCR6_PING_DST, 0x401018c4 +.set CYREG_DMAC_DESCR6_PING_CTL, 0x401018c8 +.set CYREG_DMAC_DESCR6_PING_STATUS, 0x401018cc +.set CYREG_DMAC_DESCR6_PONG_SRC, 0x401018d0 +.set CYREG_DMAC_DESCR6_PONG_DST, 0x401018d4 +.set CYREG_DMAC_DESCR6_PONG_CTL, 0x401018d8 +.set CYREG_DMAC_DESCR6_PONG_STATUS, 0x401018dc +.set CYDEV_DMAC_DESCR7_BASE, 0x401018e0 +.set CYDEV_DMAC_DESCR7_SIZE, 0x00000020 +.set CYREG_DMAC_DESCR7_PING_SRC, 0x401018e0 +.set CYREG_DMAC_DESCR7_PING_DST, 0x401018e4 +.set CYREG_DMAC_DESCR7_PING_CTL, 0x401018e8 +.set CYREG_DMAC_DESCR7_PING_STATUS, 0x401018ec +.set CYREG_DMAC_DESCR7_PONG_SRC, 0x401018f0 +.set CYREG_DMAC_DESCR7_PONG_DST, 0x401018f4 +.set CYREG_DMAC_DESCR7_PONG_CTL, 0x401018f8 +.set CYREG_DMAC_DESCR7_PONG_STATUS, 0x401018fc +.set CYDEV_SPCIF_BASE, 0x40110000 +.set CYDEV_SPCIF_SIZE, 0x00010000 +.set CYREG_SPCIF_GEOMETRY, 0x40110000 +.set CYFLD_SPCIF_FLASH__OFFSET, 0x00000000 +.set CYFLD_SPCIF_FLASH__SIZE, 0x0000000e +.set CYFLD_SPCIF_SFLASH__OFFSET, 0x0000000e +.set CYFLD_SPCIF_SFLASH__SIZE, 0x00000006 +.set CYFLD_SPCIF_NUM_FLASH__OFFSET, 0x00000014 +.set CYFLD_SPCIF_NUM_FLASH__SIZE, 0x00000002 +.set CYFLD_SPCIF_FLASH_ROW__OFFSET, 0x00000016 +.set CYFLD_SPCIF_FLASH_ROW__SIZE, 0x00000002 +.set CYFLD_SPCIF_DE_CPD_LP__OFFSET, 0x0000001f +.set CYFLD_SPCIF_DE_CPD_LP__SIZE, 0x00000001 +.set CYREG_SPCIF_INTR, 0x401107f0 +.set CYFLD_SPCIF_TIMER__OFFSET, 0x00000000 +.set CYFLD_SPCIF_TIMER__SIZE, 0x00000001 +.set CYREG_SPCIF_INTR_SET, 0x401107f4 +.set CYREG_SPCIF_INTR_MASK, 0x401107f8 +.set CYREG_SPCIF_INTR_MASKED, 0x401107fc +.set CYDEV_TCPWM_BASE, 0x40200000 +.set CYDEV_TCPWM_SIZE, 0x00010000 +.set CYREG_TCPWM_CTRL, 0x40200000 +.set CYFLD_TCPWM_COUNTER_ENABLED__OFFSET, 0x00000000 +.set CYFLD_TCPWM_COUNTER_ENABLED__SIZE, 0x00000008 +.set CYREG_TCPWM_CMD, 0x40200008 +.set CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET, 0x00000000 +.set CYFLD_TCPWM_COUNTER_CAPTURE__SIZE, 0x00000008 +.set CYFLD_TCPWM_COUNTER_RELOAD__OFFSET, 0x00000008 +.set CYFLD_TCPWM_COUNTER_RELOAD__SIZE, 0x00000008 +.set CYFLD_TCPWM_COUNTER_STOP__OFFSET, 0x00000010 +.set CYFLD_TCPWM_COUNTER_STOP__SIZE, 0x00000008 +.set CYFLD_TCPWM_COUNTER_START__OFFSET, 0x00000018 +.set CYFLD_TCPWM_COUNTER_START__SIZE, 0x00000008 +.set CYREG_TCPWM_INTR_CAUSE, 0x4020000c +.set CYFLD_TCPWM_COUNTER_INT__OFFSET, 0x00000000 +.set CYFLD_TCPWM_COUNTER_INT__SIZE, 0x00000008 +.set CYDEV_TCPWM_CNT0_BASE, 0x40200100 +.set CYDEV_TCPWM_CNT0_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT0_CTRL, 0x40200100 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET, 0x00000001 +.set CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET, 0x00000002 +.set CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET, 0x00000003 +.set CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_GENERIC__OFFSET, 0x00000008 +.set CYFLD_TCPWM_CNT_GENERIC__SIZE, 0x00000008 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY1, 0x00000000 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY2, 0x00000001 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY4, 0x00000002 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY8, 0x00000003 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY16, 0x00000004 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY32, 0x00000005 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY64, 0x00000006 +.set CYVAL_TCPWM_CNT_GENERIC_DIVBY128, 0x00000007 +.set CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET, 0x00000010 +.set CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP, 0x00000000 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN, 0x00000001 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1, 0x00000002 +.set CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2, 0x00000003 +.set CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET, 0x00000012 +.set CYFLD_TCPWM_CNT_ONE_SHOT__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET, 0x00000014 +.set CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1, 0x00000000 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2, 0x00000001 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4, 0x00000002 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT, 0x00000001 +.set CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT, 0x00000002 +.set CYFLD_TCPWM_CNT_MODE__OFFSET, 0x00000018 +.set CYFLD_TCPWM_CNT_MODE__SIZE, 0x00000003 +.set CYVAL_TCPWM_CNT_MODE_TIMER, 0x00000000 +.set CYVAL_TCPWM_CNT_MODE_CAPTURE, 0x00000002 +.set CYVAL_TCPWM_CNT_MODE_QUAD, 0x00000003 +.set CYVAL_TCPWM_CNT_MODE_PWM, 0x00000004 +.set CYVAL_TCPWM_CNT_MODE_PWM_DT, 0x00000005 +.set CYVAL_TCPWM_CNT_MODE_PWM_PR, 0x00000006 +.set CYREG_TCPWM_CNT0_STATUS, 0x40200104 +.set CYFLD_TCPWM_CNT_DOWN__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_DOWN__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_RUNNING__OFFSET, 0x0000001f +.set CYFLD_TCPWM_CNT_RUNNING__SIZE, 0x00000001 +.set CYREG_TCPWM_CNT0_COUNTER, 0x40200108 +.set CYFLD_TCPWM_CNT_COUNTER__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_COUNTER__SIZE, 0x00000010 +.set CYREG_TCPWM_CNT0_CC, 0x4020010c +.set CYFLD_TCPWM_CNT_CC__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CC__SIZE, 0x00000010 +.set CYREG_TCPWM_CNT0_CC_BUFF, 0x40200110 +.set CYREG_TCPWM_CNT0_PERIOD, 0x40200114 +.set CYFLD_TCPWM_CNT_PERIOD__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_PERIOD__SIZE, 0x00000010 +.set CYREG_TCPWM_CNT0_PERIOD_BUFF, 0x40200118 +.set CYREG_TCPWM_CNT0_TR_CTRL0, 0x40200120 +.set CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET, 0x00000004 +.set CYFLD_TCPWM_CNT_COUNT_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET, 0x00000008 +.set CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_STOP_SEL__OFFSET, 0x0000000c +.set CYFLD_TCPWM_CNT_STOP_SEL__SIZE, 0x00000004 +.set CYFLD_TCPWM_CNT_START_SEL__OFFSET, 0x00000010 +.set CYFLD_TCPWM_CNT_START_SEL__SIZE, 0x00000004 +.set CYREG_TCPWM_CNT0_TR_CTRL1, 0x40200124 +.set CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET, 0x00000002 +.set CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET, 0x00000004 +.set CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET, 0x00000006 +.set CYFLD_TCPWM_CNT_STOP_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET, 0x00000003 +.set CYFLD_TCPWM_CNT_START_EDGE__OFFSET, 0x00000008 +.set CYFLD_TCPWM_CNT_START_EDGE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE, 0x00000000 +.set CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE, 0x00000001 +.set CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES, 0x00000002 +.set CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET, 0x00000003 +.set CYREG_TCPWM_CNT0_TR_CTRL2, 0x40200128 +.set CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET, 0x00000000 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR, 0x00000001 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT, 0x00000002 +.set CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE, 0x00000003 +.set CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET, 0x00000002 +.set CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET, 0x00000000 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR, 0x00000001 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT, 0x00000002 +.set CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE, 0x00000003 +.set CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET, 0x00000004 +.set CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE, 0x00000002 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET, 0x00000000 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR, 0x00000001 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT, 0x00000002 +.set CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE, 0x00000003 +.set CYREG_TCPWM_CNT0_INTR, 0x40200130 +.set CYFLD_TCPWM_CNT_TC__OFFSET, 0x00000000 +.set CYFLD_TCPWM_CNT_TC__SIZE, 0x00000001 +.set CYFLD_TCPWM_CNT_CC_MATCH__OFFSET, 0x00000001 +.set CYFLD_TCPWM_CNT_CC_MATCH__SIZE, 0x00000001 +.set CYREG_TCPWM_CNT0_INTR_SET, 0x40200134 +.set CYREG_TCPWM_CNT0_INTR_MASK, 0x40200138 +.set CYREG_TCPWM_CNT0_INTR_MASKED, 0x4020013c +.set CYDEV_TCPWM_CNT1_BASE, 0x40200140 +.set CYDEV_TCPWM_CNT1_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT1_CTRL, 0x40200140 +.set CYREG_TCPWM_CNT1_STATUS, 0x40200144 +.set CYREG_TCPWM_CNT1_COUNTER, 0x40200148 +.set CYREG_TCPWM_CNT1_CC, 0x4020014c +.set CYREG_TCPWM_CNT1_CC_BUFF, 0x40200150 +.set CYREG_TCPWM_CNT1_PERIOD, 0x40200154 +.set CYREG_TCPWM_CNT1_PERIOD_BUFF, 0x40200158 +.set CYREG_TCPWM_CNT1_TR_CTRL0, 0x40200160 +.set CYREG_TCPWM_CNT1_TR_CTRL1, 0x40200164 +.set CYREG_TCPWM_CNT1_TR_CTRL2, 0x40200168 +.set CYREG_TCPWM_CNT1_INTR, 0x40200170 +.set CYREG_TCPWM_CNT1_INTR_SET, 0x40200174 +.set CYREG_TCPWM_CNT1_INTR_MASK, 0x40200178 +.set CYREG_TCPWM_CNT1_INTR_MASKED, 0x4020017c +.set CYDEV_TCPWM_CNT2_BASE, 0x40200180 +.set CYDEV_TCPWM_CNT2_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT2_CTRL, 0x40200180 +.set CYREG_TCPWM_CNT2_STATUS, 0x40200184 +.set CYREG_TCPWM_CNT2_COUNTER, 0x40200188 +.set CYREG_TCPWM_CNT2_CC, 0x4020018c +.set CYREG_TCPWM_CNT2_CC_BUFF, 0x40200190 +.set CYREG_TCPWM_CNT2_PERIOD, 0x40200194 +.set CYREG_TCPWM_CNT2_PERIOD_BUFF, 0x40200198 +.set CYREG_TCPWM_CNT2_TR_CTRL0, 0x402001a0 +.set CYREG_TCPWM_CNT2_TR_CTRL1, 0x402001a4 +.set CYREG_TCPWM_CNT2_TR_CTRL2, 0x402001a8 +.set CYREG_TCPWM_CNT2_INTR, 0x402001b0 +.set CYREG_TCPWM_CNT2_INTR_SET, 0x402001b4 +.set CYREG_TCPWM_CNT2_INTR_MASK, 0x402001b8 +.set CYREG_TCPWM_CNT2_INTR_MASKED, 0x402001bc +.set CYDEV_TCPWM_CNT3_BASE, 0x402001c0 +.set CYDEV_TCPWM_CNT3_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT3_CTRL, 0x402001c0 +.set CYREG_TCPWM_CNT3_STATUS, 0x402001c4 +.set CYREG_TCPWM_CNT3_COUNTER, 0x402001c8 +.set CYREG_TCPWM_CNT3_CC, 0x402001cc +.set CYREG_TCPWM_CNT3_CC_BUFF, 0x402001d0 +.set CYREG_TCPWM_CNT3_PERIOD, 0x402001d4 +.set CYREG_TCPWM_CNT3_PERIOD_BUFF, 0x402001d8 +.set CYREG_TCPWM_CNT3_TR_CTRL0, 0x402001e0 +.set CYREG_TCPWM_CNT3_TR_CTRL1, 0x402001e4 +.set CYREG_TCPWM_CNT3_TR_CTRL2, 0x402001e8 +.set CYREG_TCPWM_CNT3_INTR, 0x402001f0 +.set CYREG_TCPWM_CNT3_INTR_SET, 0x402001f4 +.set CYREG_TCPWM_CNT3_INTR_MASK, 0x402001f8 +.set CYREG_TCPWM_CNT3_INTR_MASKED, 0x402001fc +.set CYDEV_TCPWM_CNT4_BASE, 0x40200200 +.set CYDEV_TCPWM_CNT4_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT4_CTRL, 0x40200200 +.set CYREG_TCPWM_CNT4_STATUS, 0x40200204 +.set CYREG_TCPWM_CNT4_COUNTER, 0x40200208 +.set CYREG_TCPWM_CNT4_CC, 0x4020020c +.set CYREG_TCPWM_CNT4_CC_BUFF, 0x40200210 +.set CYREG_TCPWM_CNT4_PERIOD, 0x40200214 +.set CYREG_TCPWM_CNT4_PERIOD_BUFF, 0x40200218 +.set CYREG_TCPWM_CNT4_TR_CTRL0, 0x40200220 +.set CYREG_TCPWM_CNT4_TR_CTRL1, 0x40200224 +.set CYREG_TCPWM_CNT4_TR_CTRL2, 0x40200228 +.set CYREG_TCPWM_CNT4_INTR, 0x40200230 +.set CYREG_TCPWM_CNT4_INTR_SET, 0x40200234 +.set CYREG_TCPWM_CNT4_INTR_MASK, 0x40200238 +.set CYREG_TCPWM_CNT4_INTR_MASKED, 0x4020023c +.set CYDEV_TCPWM_CNT5_BASE, 0x40200240 +.set CYDEV_TCPWM_CNT5_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT5_CTRL, 0x40200240 +.set CYREG_TCPWM_CNT5_STATUS, 0x40200244 +.set CYREG_TCPWM_CNT5_COUNTER, 0x40200248 +.set CYREG_TCPWM_CNT5_CC, 0x4020024c +.set CYREG_TCPWM_CNT5_CC_BUFF, 0x40200250 +.set CYREG_TCPWM_CNT5_PERIOD, 0x40200254 +.set CYREG_TCPWM_CNT5_PERIOD_BUFF, 0x40200258 +.set CYREG_TCPWM_CNT5_TR_CTRL0, 0x40200260 +.set CYREG_TCPWM_CNT5_TR_CTRL1, 0x40200264 +.set CYREG_TCPWM_CNT5_TR_CTRL2, 0x40200268 +.set CYREG_TCPWM_CNT5_INTR, 0x40200270 +.set CYREG_TCPWM_CNT5_INTR_SET, 0x40200274 +.set CYREG_TCPWM_CNT5_INTR_MASK, 0x40200278 +.set CYREG_TCPWM_CNT5_INTR_MASKED, 0x4020027c +.set CYDEV_TCPWM_CNT6_BASE, 0x40200280 +.set CYDEV_TCPWM_CNT6_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT6_CTRL, 0x40200280 +.set CYREG_TCPWM_CNT6_STATUS, 0x40200284 +.set CYREG_TCPWM_CNT6_COUNTER, 0x40200288 +.set CYREG_TCPWM_CNT6_CC, 0x4020028c +.set CYREG_TCPWM_CNT6_CC_BUFF, 0x40200290 +.set CYREG_TCPWM_CNT6_PERIOD, 0x40200294 +.set CYREG_TCPWM_CNT6_PERIOD_BUFF, 0x40200298 +.set CYREG_TCPWM_CNT6_TR_CTRL0, 0x402002a0 +.set CYREG_TCPWM_CNT6_TR_CTRL1, 0x402002a4 +.set CYREG_TCPWM_CNT6_TR_CTRL2, 0x402002a8 +.set CYREG_TCPWM_CNT6_INTR, 0x402002b0 +.set CYREG_TCPWM_CNT6_INTR_SET, 0x402002b4 +.set CYREG_TCPWM_CNT6_INTR_MASK, 0x402002b8 +.set CYREG_TCPWM_CNT6_INTR_MASKED, 0x402002bc +.set CYDEV_TCPWM_CNT7_BASE, 0x402002c0 +.set CYDEV_TCPWM_CNT7_SIZE, 0x00000040 +.set CYREG_TCPWM_CNT7_CTRL, 0x402002c0 +.set CYREG_TCPWM_CNT7_STATUS, 0x402002c4 +.set CYREG_TCPWM_CNT7_COUNTER, 0x402002c8 +.set CYREG_TCPWM_CNT7_CC, 0x402002cc +.set CYREG_TCPWM_CNT7_CC_BUFF, 0x402002d0 +.set CYREG_TCPWM_CNT7_PERIOD, 0x402002d4 +.set CYREG_TCPWM_CNT7_PERIOD_BUFF, 0x402002d8 +.set CYREG_TCPWM_CNT7_TR_CTRL0, 0x402002e0 +.set CYREG_TCPWM_CNT7_TR_CTRL1, 0x402002e4 +.set CYREG_TCPWM_CNT7_TR_CTRL2, 0x402002e8 +.set CYREG_TCPWM_CNT7_INTR, 0x402002f0 +.set CYREG_TCPWM_CNT7_INTR_SET, 0x402002f4 +.set CYREG_TCPWM_CNT7_INTR_MASK, 0x402002f8 +.set CYREG_TCPWM_CNT7_INTR_MASKED, 0x402002fc +.set CYDEV_WCO_BASE, 0x40220000 +.set CYDEV_WCO_SIZE, 0x00010000 +.set CYREG_WCO_CONFIG, 0x40220000 +.set CYFLD_WCO_LPM_EN__OFFSET, 0x00000000 +.set CYFLD_WCO_LPM_EN__SIZE, 0x00000001 +.set CYFLD_WCO_LPM_AUTO__OFFSET, 0x00000001 +.set CYFLD_WCO_LPM_AUTO__SIZE, 0x00000001 +.set CYFLD_WCO_EXT_INPUT_EN__OFFSET, 0x00000002 +.set CYFLD_WCO_EXT_INPUT_EN__SIZE, 0x00000001 +.set CYFLD_WCO_ENBUS__OFFSET, 0x00000010 +.set CYFLD_WCO_ENBUS__SIZE, 0x00000008 +.set CYFLD_WCO_DPLL_ENABLE__OFFSET, 0x0000001e +.set CYFLD_WCO_DPLL_ENABLE__SIZE, 0x00000001 +.set CYFLD_WCO_IP_ENABLE__OFFSET, 0x0000001f +.set CYFLD_WCO_IP_ENABLE__SIZE, 0x00000001 +.set CYREG_WCO_STATUS, 0x40220004 +.set CYFLD_WCO_OUT_BLNK_A__OFFSET, 0x00000000 +.set CYFLD_WCO_OUT_BLNK_A__SIZE, 0x00000001 +.set CYREG_WCO_DPLL, 0x40220008 +.set CYFLD_WCO_DPLL_MULT__OFFSET, 0x00000000 +.set CYFLD_WCO_DPLL_MULT__SIZE, 0x0000000b +.set CYFLD_WCO_DPLL_LF_IGAIN__OFFSET, 0x00000010 +.set CYFLD_WCO_DPLL_LF_IGAIN__SIZE, 0x00000003 +.set CYFLD_WCO_DPLL_LF_PGAIN__OFFSET, 0x00000013 +.set CYFLD_WCO_DPLL_LF_PGAIN__SIZE, 0x00000003 +.set CYFLD_WCO_DPLL_LF_LIMIT__OFFSET, 0x00000016 +.set CYFLD_WCO_DPLL_LF_LIMIT__SIZE, 0x00000008 +.set CYREG_WCO_WDT_CTRLOW, 0x40220200 +.set CYFLD_WCO_WDT_CTR0__OFFSET, 0x00000000 +.set CYFLD_WCO_WDT_CTR0__SIZE, 0x00000010 +.set CYFLD_WCO_WDT_CTR1__OFFSET, 0x00000010 +.set CYFLD_WCO_WDT_CTR1__SIZE, 0x00000010 +.set CYREG_WCO_WDT_CTRHIGH, 0x40220204 +.set CYFLD_WCO_WDT_CTR2__OFFSET, 0x00000000 +.set CYFLD_WCO_WDT_CTR2__SIZE, 0x00000020 +.set CYREG_WCO_WDT_MATCH, 0x40220208 +.set CYFLD_WCO_WDT_MATCH0__OFFSET, 0x00000000 +.set CYFLD_WCO_WDT_MATCH0__SIZE, 0x00000010 +.set CYFLD_WCO_WDT_MATCH1__OFFSET, 0x00000010 +.set CYFLD_WCO_WDT_MATCH1__SIZE, 0x00000010 +.set CYREG_WCO_WDT_CONFIG, 0x4022020c +.set CYFLD_WCO_WDT_MODE0__OFFSET, 0x00000000 +.set CYFLD_WCO_WDT_MODE0__SIZE, 0x00000002 +.set CYVAL_WCO_WDT_MODE0_NOTHING, 0x00000000 +.set CYVAL_WCO_WDT_MODE0_INT, 0x00000001 +.set CYVAL_WCO_WDT_MODE0_RESET, 0x00000002 +.set CYVAL_WCO_WDT_MODE0_INT_THEN_RESET, 0x00000003 +.set CYFLD_WCO_WDT_CLEAR0__OFFSET, 0x00000002 +.set CYFLD_WCO_WDT_CLEAR0__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_CASCADE0_1__OFFSET, 0x00000003 +.set CYFLD_WCO_WDT_CASCADE0_1__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_MODE1__OFFSET, 0x00000008 +.set CYFLD_WCO_WDT_MODE1__SIZE, 0x00000002 +.set CYVAL_WCO_WDT_MODE1_NOTHING, 0x00000000 +.set CYVAL_WCO_WDT_MODE1_INT, 0x00000001 +.set CYVAL_WCO_WDT_MODE1_RESET, 0x00000002 +.set CYVAL_WCO_WDT_MODE1_INT_THEN_RESET, 0x00000003 +.set CYFLD_WCO_WDT_CLEAR1__OFFSET, 0x0000000a +.set CYFLD_WCO_WDT_CLEAR1__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_CASCADE1_2__OFFSET, 0x0000000b +.set CYFLD_WCO_WDT_CASCADE1_2__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_MODE2__OFFSET, 0x00000010 +.set CYFLD_WCO_WDT_MODE2__SIZE, 0x00000001 +.set CYVAL_WCO_WDT_MODE2_NOTHING, 0x00000000 +.set CYVAL_WCO_WDT_MODE2_INT, 0x00000001 +.set CYFLD_WCO_WDT_BITS2__OFFSET, 0x00000018 +.set CYFLD_WCO_WDT_BITS2__SIZE, 0x00000005 +.set CYFLD_WCO_LFCLK_SEL__OFFSET, 0x0000001e +.set CYFLD_WCO_LFCLK_SEL__SIZE, 0x00000002 +.set CYREG_WCO_WDT_CONTROL, 0x40220210 +.set CYFLD_WCO_WDT_ENABLE0__OFFSET, 0x00000000 +.set CYFLD_WCO_WDT_ENABLE0__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_ENABLED0__OFFSET, 0x00000001 +.set CYFLD_WCO_WDT_ENABLED0__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_INT0__OFFSET, 0x00000002 +.set CYFLD_WCO_WDT_INT0__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_RESET0__OFFSET, 0x00000003 +.set CYFLD_WCO_WDT_RESET0__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_ENABLE1__OFFSET, 0x00000008 +.set CYFLD_WCO_WDT_ENABLE1__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_ENABLED1__OFFSET, 0x00000009 +.set CYFLD_WCO_WDT_ENABLED1__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_INT1__OFFSET, 0x0000000a +.set CYFLD_WCO_WDT_INT1__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_RESET1__OFFSET, 0x0000000b +.set CYFLD_WCO_WDT_RESET1__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_ENABLE2__OFFSET, 0x00000010 +.set CYFLD_WCO_WDT_ENABLE2__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_ENABLED2__OFFSET, 0x00000011 +.set CYFLD_WCO_WDT_ENABLED2__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_INT2__OFFSET, 0x00000012 +.set CYFLD_WCO_WDT_INT2__SIZE, 0x00000001 +.set CYFLD_WCO_WDT_RESET2__OFFSET, 0x00000013 +.set CYFLD_WCO_WDT_RESET2__SIZE, 0x00000001 +.set CYREG_WCO_WDT_CLKEN, 0x40220214 +.set CYFLD_WCO_CLK_WCO_EN_FOR_WDT__OFFSET, 0x00000000 +.set CYFLD_WCO_CLK_WCO_EN_FOR_WDT__SIZE, 0x00000001 +.set CYFLD_WCO_CLK_ILO_EN_FOR_WDT__OFFSET, 0x00000001 +.set CYFLD_WCO_CLK_ILO_EN_FOR_WDT__SIZE, 0x00000001 +.set CYREG_WCO_TRIM, 0x40220f00 +.set CYFLD_WCO_XGM__OFFSET, 0x00000000 +.set CYFLD_WCO_XGM__SIZE, 0x00000003 +.set CYFLD_WCO_LPM_GM__OFFSET, 0x00000004 +.set CYFLD_WCO_LPM_GM__SIZE, 0x00000002 +.set CYDEV_SCB0_BASE, 0x40240000 +.set CYDEV_SCB0_SIZE, 0x00010000 +.set CYREG_SCB0_CTRL, 0x40240000 +.set CYFLD_SCB_OVS__OFFSET, 0x00000000 +.set CYFLD_SCB_OVS__SIZE, 0x00000004 +.set CYFLD_SCB_EC_AM_MODE__OFFSET, 0x00000008 +.set CYFLD_SCB_EC_AM_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_EC_OP_MODE__OFFSET, 0x00000009 +.set CYFLD_SCB_EC_OP_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_MODE__OFFSET, 0x0000000a +.set CYFLD_SCB_EZ_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_BYTE_MODE__OFFSET, 0x0000000b +.set CYFLD_SCB_BYTE_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_ADDR_ACCEPT__OFFSET, 0x00000010 +.set CYFLD_SCB_ADDR_ACCEPT__SIZE, 0x00000001 +.set CYFLD_SCB_BLOCK__OFFSET, 0x00000011 +.set CYFLD_SCB_BLOCK__SIZE, 0x00000001 +.set CYFLD_SCB_MODE__OFFSET, 0x00000018 +.set CYFLD_SCB_MODE__SIZE, 0x00000002 +.set CYVAL_SCB_MODE_I2C, 0x00000000 +.set CYVAL_SCB_MODE_SPI, 0x00000001 +.set CYVAL_SCB_MODE_UART, 0x00000002 +.set CYFLD_SCB_ENABLED__OFFSET, 0x0000001f +.set CYFLD_SCB_ENABLED__SIZE, 0x00000001 +.set CYREG_SCB0_STATUS, 0x40240004 +.set CYFLD_SCB_EC_BUSY__OFFSET, 0x00000000 +.set CYFLD_SCB_EC_BUSY__SIZE, 0x00000001 +.set CYREG_SCB0_SPI_CTRL, 0x40240020 +.set CYFLD_SCB_CONTINUOUS__OFFSET, 0x00000000 +.set CYFLD_SCB_CONTINUOUS__SIZE, 0x00000001 +.set CYFLD_SCB_SELECT_PRECEDE__OFFSET, 0x00000001 +.set CYFLD_SCB_SELECT_PRECEDE__SIZE, 0x00000001 +.set CYFLD_SCB_CPHA__OFFSET, 0x00000002 +.set CYFLD_SCB_CPHA__SIZE, 0x00000001 +.set CYFLD_SCB_CPOL__OFFSET, 0x00000003 +.set CYFLD_SCB_CPOL__SIZE, 0x00000001 +.set CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET, 0x00000004 +.set CYFLD_SCB_LATE_MISO_SAMPLE__SIZE, 0x00000001 +.set CYFLD_SCB_SCLK_CONTINUOUS__OFFSET, 0x00000005 +.set CYFLD_SCB_SCLK_CONTINUOUS__SIZE, 0x00000001 +.set CYFLD_SCB_SSEL_POLARITY0__OFFSET, 0x00000008 +.set CYFLD_SCB_SSEL_POLARITY0__SIZE, 0x00000001 +.set CYFLD_SCB_SSEL_POLARITY1__OFFSET, 0x00000009 +.set CYFLD_SCB_SSEL_POLARITY1__SIZE, 0x00000001 +.set CYFLD_SCB_SSEL_POLARITY2__OFFSET, 0x0000000a +.set CYFLD_SCB_SSEL_POLARITY2__SIZE, 0x00000001 +.set CYFLD_SCB_SSEL_POLARITY3__OFFSET, 0x0000000b +.set CYFLD_SCB_SSEL_POLARITY3__SIZE, 0x00000001 +.set CYFLD_SCB_LOOPBACK__OFFSET, 0x00000010 +.set CYFLD_SCB_LOOPBACK__SIZE, 0x00000001 +.set CYFLD_SCB_SLAVE_SELECT__OFFSET, 0x0000001a +.set CYFLD_SCB_SLAVE_SELECT__SIZE, 0x00000002 +.set CYFLD_SCB_MASTER_MODE__OFFSET, 0x0000001f +.set CYFLD_SCB_MASTER_MODE__SIZE, 0x00000001 +.set CYREG_SCB0_SPI_STATUS, 0x40240024 +.set CYFLD_SCB_BUS_BUSY__OFFSET, 0x00000000 +.set CYFLD_SCB_BUS_BUSY__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_EC_BUSY__OFFSET, 0x00000001 +.set CYFLD_SCB_SPI_EC_BUSY__SIZE, 0x00000001 +.set CYFLD_SCB_CURR_EZ_ADDR__OFFSET, 0x00000008 +.set CYFLD_SCB_CURR_EZ_ADDR__SIZE, 0x00000008 +.set CYFLD_SCB_BASE_EZ_ADDR__OFFSET, 0x00000010 +.set CYFLD_SCB_BASE_EZ_ADDR__SIZE, 0x00000008 +.set CYREG_SCB0_UART_CTRL, 0x40240040 +.set CYREG_SCB0_UART_TX_CTRL, 0x40240044 +.set CYFLD_SCB_STOP_BITS__OFFSET, 0x00000000 +.set CYFLD_SCB_STOP_BITS__SIZE, 0x00000003 +.set CYFLD_SCB_PARITY__OFFSET, 0x00000004 +.set CYFLD_SCB_PARITY__SIZE, 0x00000001 +.set CYFLD_SCB_PARITY_ENABLED__OFFSET, 0x00000005 +.set CYFLD_SCB_PARITY_ENABLED__SIZE, 0x00000001 +.set CYFLD_SCB_RETRY_ON_NACK__OFFSET, 0x00000008 +.set CYFLD_SCB_RETRY_ON_NACK__SIZE, 0x00000001 +.set CYREG_SCB0_UART_RX_CTRL, 0x40240048 +.set CYFLD_SCB_POLARITY__OFFSET, 0x00000006 +.set CYFLD_SCB_POLARITY__SIZE, 0x00000001 +.set CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET, 0x00000008 +.set CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET, 0x00000009 +.set CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_MP_MODE__OFFSET, 0x0000000a +.set CYFLD_SCB_MP_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_LIN_MODE__OFFSET, 0x0000000c +.set CYFLD_SCB_LIN_MODE__SIZE, 0x00000001 +.set CYFLD_SCB_SKIP_START__OFFSET, 0x0000000d +.set CYFLD_SCB_SKIP_START__SIZE, 0x00000001 +.set CYFLD_SCB_BREAK_WIDTH__OFFSET, 0x00000010 +.set CYFLD_SCB_BREAK_WIDTH__SIZE, 0x00000004 +.set CYREG_SCB0_UART_RX_STATUS, 0x4024004c +.set CYFLD_SCB_BR_COUNTER__OFFSET, 0x00000000 +.set CYFLD_SCB_BR_COUNTER__SIZE, 0x0000000c +.set CYREG_SCB0_UART_FLOW_CTRL, 0x40240050 +.set CYFLD_SCB_TRIGGER_LEVEL__OFFSET, 0x00000000 +.set CYFLD_SCB_TRIGGER_LEVEL__SIZE, 0x00000004 +.set CYFLD_SCB_RTS_POLARITY__OFFSET, 0x00000010 +.set CYFLD_SCB_RTS_POLARITY__SIZE, 0x00000001 +.set CYFLD_SCB_CTS_POLARITY__OFFSET, 0x00000018 +.set CYFLD_SCB_CTS_POLARITY__SIZE, 0x00000001 +.set CYFLD_SCB_CTS_ENABLED__OFFSET, 0x00000019 +.set CYFLD_SCB_CTS_ENABLED__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_CTRL, 0x40240060 +.set CYFLD_SCB_HIGH_PHASE_OVS__OFFSET, 0x00000000 +.set CYFLD_SCB_HIGH_PHASE_OVS__SIZE, 0x00000004 +.set CYFLD_SCB_LOW_PHASE_OVS__OFFSET, 0x00000004 +.set CYFLD_SCB_LOW_PHASE_OVS__SIZE, 0x00000004 +.set CYFLD_SCB_M_READY_DATA_ACK__OFFSET, 0x00000008 +.set CYFLD_SCB_M_READY_DATA_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET, 0x00000009 +.set CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_GENERAL_IGNORE__OFFSET, 0x0000000b +.set CYFLD_SCB_S_GENERAL_IGNORE__SIZE, 0x00000001 +.set CYFLD_SCB_S_READY_ADDR_ACK__OFFSET, 0x0000000c +.set CYFLD_SCB_S_READY_ADDR_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_READY_DATA_ACK__OFFSET, 0x0000000d +.set CYFLD_SCB_S_READY_DATA_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET, 0x0000000e +.set CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET, 0x0000000f +.set CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_SLAVE_MODE__OFFSET, 0x0000001e +.set CYFLD_SCB_SLAVE_MODE__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_STATUS, 0x40240064 +.set CYFLD_SCB_I2C_EC_BUSY__OFFSET, 0x00000001 +.set CYFLD_SCB_I2C_EC_BUSY__SIZE, 0x00000001 +.set CYFLD_SCB_S_READ__OFFSET, 0x00000004 +.set CYFLD_SCB_S_READ__SIZE, 0x00000001 +.set CYFLD_SCB_M_READ__OFFSET, 0x00000005 +.set CYFLD_SCB_M_READ__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_M_CMD, 0x40240068 +.set CYFLD_SCB_M_START__OFFSET, 0x00000000 +.set CYFLD_SCB_M_START__SIZE, 0x00000001 +.set CYFLD_SCB_M_START_ON_IDLE__OFFSET, 0x00000001 +.set CYFLD_SCB_M_START_ON_IDLE__SIZE, 0x00000001 +.set CYFLD_SCB_M_ACK__OFFSET, 0x00000002 +.set CYFLD_SCB_M_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_M_NACK__OFFSET, 0x00000003 +.set CYFLD_SCB_M_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_M_STOP__OFFSET, 0x00000004 +.set CYFLD_SCB_M_STOP__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_S_CMD, 0x4024006c +.set CYFLD_SCB_S_ACK__OFFSET, 0x00000000 +.set CYFLD_SCB_S_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_S_NACK__OFFSET, 0x00000001 +.set CYFLD_SCB_S_NACK__SIZE, 0x00000001 +.set CYREG_SCB0_I2C_CFG, 0x40240070 +.set CYFLD_SCB_SDA_IN_FILT_TRIM__OFFSET, 0x00000000 +.set CYFLD_SCB_SDA_IN_FILT_TRIM__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_IN_FILT_SEL__OFFSET, 0x00000004 +.set CYFLD_SCB_SDA_IN_FILT_SEL__SIZE, 0x00000001 +.set CYFLD_SCB_SCL_IN_FILT_TRIM__OFFSET, 0x00000008 +.set CYFLD_SCB_SCL_IN_FILT_TRIM__SIZE, 0x00000002 +.set CYFLD_SCB_SCL_IN_FILT_SEL__OFFSET, 0x0000000c +.set CYFLD_SCB_SCL_IN_FILT_SEL__SIZE, 0x00000001 +.set CYFLD_SCB_SDA_OUT_FILT0_TRIM__OFFSET, 0x00000010 +.set CYFLD_SCB_SDA_OUT_FILT0_TRIM__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_OUT_FILT1_TRIM__OFFSET, 0x00000012 +.set CYFLD_SCB_SDA_OUT_FILT1_TRIM__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_OUT_FILT2_TRIM__OFFSET, 0x00000014 +.set CYFLD_SCB_SDA_OUT_FILT2_TRIM__SIZE, 0x00000002 +.set CYFLD_SCB_SDA_OUT_FILT_SEL__OFFSET, 0x0000001c +.set CYFLD_SCB_SDA_OUT_FILT_SEL__SIZE, 0x00000002 +.set CYREG_SCB0_TX_CTRL, 0x40240200 +.set CYFLD_SCB_DATA_WIDTH__OFFSET, 0x00000000 +.set CYFLD_SCB_DATA_WIDTH__SIZE, 0x00000004 +.set CYFLD_SCB_MSB_FIRST__OFFSET, 0x00000008 +.set CYFLD_SCB_MSB_FIRST__SIZE, 0x00000001 +.set CYREG_SCB0_TX_FIFO_CTRL, 0x40240204 +.set CYFLD_SCB_CLEAR__OFFSET, 0x00000010 +.set CYFLD_SCB_CLEAR__SIZE, 0x00000001 +.set CYFLD_SCB_FREEZE__OFFSET, 0x00000011 +.set CYFLD_SCB_FREEZE__SIZE, 0x00000001 +.set CYREG_SCB0_TX_FIFO_STATUS, 0x40240208 +.set CYFLD_SCB_USED__OFFSET, 0x00000000 +.set CYFLD_SCB_USED__SIZE, 0x00000005 +.set CYFLD_SCB_SR_VALID__OFFSET, 0x0000000f +.set CYFLD_SCB_SR_VALID__SIZE, 0x00000001 +.set CYFLD_SCB_RD_PTR__OFFSET, 0x00000010 +.set CYFLD_SCB_RD_PTR__SIZE, 0x00000004 +.set CYFLD_SCB_WR_PTR__OFFSET, 0x00000018 +.set CYFLD_SCB_WR_PTR__SIZE, 0x00000004 +.set CYREG_SCB0_TX_FIFO_WR, 0x40240240 +.set CYFLD_SCB_DATA__OFFSET, 0x00000000 +.set CYFLD_SCB_DATA__SIZE, 0x00000010 +.set CYREG_SCB0_RX_CTRL, 0x40240300 +.set CYFLD_SCB_MEDIAN__OFFSET, 0x00000009 +.set CYFLD_SCB_MEDIAN__SIZE, 0x00000001 +.set CYREG_SCB0_RX_FIFO_CTRL, 0x40240304 +.set CYREG_SCB0_RX_FIFO_STATUS, 0x40240308 +.set CYREG_SCB0_RX_MATCH, 0x40240310 +.set CYFLD_SCB_ADDR__OFFSET, 0x00000000 +.set CYFLD_SCB_ADDR__SIZE, 0x00000008 +.set CYFLD_SCB_MASK__OFFSET, 0x00000010 +.set CYFLD_SCB_MASK__SIZE, 0x00000008 +.set CYREG_SCB0_RX_FIFO_RD, 0x40240340 +.set CYREG_SCB0_RX_FIFO_RD_SILENT, 0x40240344 +.set CYREG_SCB0_EZ_DATA0, 0x40240400 +.set CYFLD_SCB_EZ_DATA__OFFSET, 0x00000000 +.set CYFLD_SCB_EZ_DATA__SIZE, 0x00000008 +.set CYREG_SCB0_EZ_DATA1, 0x40240404 +.set CYREG_SCB0_EZ_DATA2, 0x40240408 +.set CYREG_SCB0_EZ_DATA3, 0x4024040c +.set CYREG_SCB0_EZ_DATA4, 0x40240410 +.set CYREG_SCB0_EZ_DATA5, 0x40240414 +.set CYREG_SCB0_EZ_DATA6, 0x40240418 +.set CYREG_SCB0_EZ_DATA7, 0x4024041c +.set CYREG_SCB0_EZ_DATA8, 0x40240420 +.set CYREG_SCB0_EZ_DATA9, 0x40240424 +.set CYREG_SCB0_EZ_DATA10, 0x40240428 +.set CYREG_SCB0_EZ_DATA11, 0x4024042c +.set CYREG_SCB0_EZ_DATA12, 0x40240430 +.set CYREG_SCB0_EZ_DATA13, 0x40240434 +.set CYREG_SCB0_EZ_DATA14, 0x40240438 +.set CYREG_SCB0_EZ_DATA15, 0x4024043c +.set CYREG_SCB0_EZ_DATA16, 0x40240440 +.set CYREG_SCB0_EZ_DATA17, 0x40240444 +.set CYREG_SCB0_EZ_DATA18, 0x40240448 +.set CYREG_SCB0_EZ_DATA19, 0x4024044c +.set CYREG_SCB0_EZ_DATA20, 0x40240450 +.set CYREG_SCB0_EZ_DATA21, 0x40240454 +.set CYREG_SCB0_EZ_DATA22, 0x40240458 +.set CYREG_SCB0_EZ_DATA23, 0x4024045c +.set CYREG_SCB0_EZ_DATA24, 0x40240460 +.set CYREG_SCB0_EZ_DATA25, 0x40240464 +.set CYREG_SCB0_EZ_DATA26, 0x40240468 +.set CYREG_SCB0_EZ_DATA27, 0x4024046c +.set CYREG_SCB0_EZ_DATA28, 0x40240470 +.set CYREG_SCB0_EZ_DATA29, 0x40240474 +.set CYREG_SCB0_EZ_DATA30, 0x40240478 +.set CYREG_SCB0_EZ_DATA31, 0x4024047c +.set CYREG_SCB0_INTR_CAUSE, 0x40240e00 +.set CYFLD_SCB_M__OFFSET, 0x00000000 +.set CYFLD_SCB_M__SIZE, 0x00000001 +.set CYFLD_SCB_S__OFFSET, 0x00000001 +.set CYFLD_SCB_S__SIZE, 0x00000001 +.set CYFLD_SCB_TX__OFFSET, 0x00000002 +.set CYFLD_SCB_TX__SIZE, 0x00000001 +.set CYFLD_SCB_RX__OFFSET, 0x00000003 +.set CYFLD_SCB_RX__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_EC__OFFSET, 0x00000004 +.set CYFLD_SCB_I2C_EC__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_EC__OFFSET, 0x00000005 +.set CYFLD_SCB_SPI_EC__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_I2C_EC, 0x40240e80 +.set CYFLD_SCB_WAKE_UP__OFFSET, 0x00000000 +.set CYFLD_SCB_WAKE_UP__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_STOP__OFFSET, 0x00000001 +.set CYFLD_SCB_EZ_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_WRITE_STOP__OFFSET, 0x00000002 +.set CYFLD_SCB_EZ_WRITE_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_EZ_READ_STOP__OFFSET, 0x00000003 +.set CYFLD_SCB_EZ_READ_STOP__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_I2C_EC_MASK, 0x40240e88 +.set CYREG_SCB0_INTR_I2C_EC_MASKED, 0x40240e8c +.set CYREG_SCB0_INTR_SPI_EC, 0x40240ec0 +.set CYREG_SCB0_INTR_SPI_EC_MASK, 0x40240ec8 +.set CYREG_SCB0_INTR_SPI_EC_MASKED, 0x40240ecc +.set CYREG_SCB0_INTR_M, 0x40240f00 +.set CYFLD_SCB_I2C_ARB_LOST__OFFSET, 0x00000000 +.set CYFLD_SCB_I2C_ARB_LOST__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_NACK__OFFSET, 0x00000001 +.set CYFLD_SCB_I2C_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_ACK__OFFSET, 0x00000002 +.set CYFLD_SCB_I2C_ACK__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_STOP__OFFSET, 0x00000004 +.set CYFLD_SCB_I2C_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_BUS_ERROR__OFFSET, 0x00000008 +.set CYFLD_SCB_I2C_BUS_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_DONE__OFFSET, 0x00000009 +.set CYFLD_SCB_SPI_DONE__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_M_SET, 0x40240f04 +.set CYREG_SCB0_INTR_M_MASK, 0x40240f08 +.set CYREG_SCB0_INTR_M_MASKED, 0x40240f0c +.set CYREG_SCB0_INTR_S, 0x40240f40 +.set CYFLD_SCB_I2C_WRITE_STOP__OFFSET, 0x00000003 +.set CYFLD_SCB_I2C_WRITE_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_START__OFFSET, 0x00000005 +.set CYFLD_SCB_I2C_START__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_ADDR_MATCH__OFFSET, 0x00000006 +.set CYFLD_SCB_I2C_ADDR_MATCH__SIZE, 0x00000001 +.set CYFLD_SCB_I2C_GENERAL__OFFSET, 0x00000007 +.set CYFLD_SCB_I2C_GENERAL__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET, 0x00000009 +.set CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_EZ_STOP__OFFSET, 0x0000000a +.set CYFLD_SCB_SPI_EZ_STOP__SIZE, 0x00000001 +.set CYFLD_SCB_SPI_BUS_ERROR__OFFSET, 0x0000000b +.set CYFLD_SCB_SPI_BUS_ERROR__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_S_SET, 0x40240f44 +.set CYREG_SCB0_INTR_S_MASK, 0x40240f48 +.set CYREG_SCB0_INTR_S_MASKED, 0x40240f4c +.set CYREG_SCB0_INTR_TX, 0x40240f80 +.set CYFLD_SCB_TRIGGER__OFFSET, 0x00000000 +.set CYFLD_SCB_TRIGGER__SIZE, 0x00000001 +.set CYFLD_SCB_NOT_FULL__OFFSET, 0x00000001 +.set CYFLD_SCB_NOT_FULL__SIZE, 0x00000001 +.set CYFLD_SCB_EMPTY__OFFSET, 0x00000004 +.set CYFLD_SCB_EMPTY__SIZE, 0x00000001 +.set CYFLD_SCB_OVERFLOW__OFFSET, 0x00000005 +.set CYFLD_SCB_OVERFLOW__SIZE, 0x00000001 +.set CYFLD_SCB_UNDERFLOW__OFFSET, 0x00000006 +.set CYFLD_SCB_UNDERFLOW__SIZE, 0x00000001 +.set CYFLD_SCB_BLOCKED__OFFSET, 0x00000007 +.set CYFLD_SCB_BLOCKED__SIZE, 0x00000001 +.set CYFLD_SCB_UART_NACK__OFFSET, 0x00000008 +.set CYFLD_SCB_UART_NACK__SIZE, 0x00000001 +.set CYFLD_SCB_UART_DONE__OFFSET, 0x00000009 +.set CYFLD_SCB_UART_DONE__SIZE, 0x00000001 +.set CYFLD_SCB_UART_ARB_LOST__OFFSET, 0x0000000a +.set CYFLD_SCB_UART_ARB_LOST__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_TX_SET, 0x40240f84 +.set CYREG_SCB0_INTR_TX_MASK, 0x40240f88 +.set CYREG_SCB0_INTR_TX_MASKED, 0x40240f8c +.set CYREG_SCB0_INTR_RX, 0x40240fc0 +.set CYFLD_SCB_NOT_EMPTY__OFFSET, 0x00000002 +.set CYFLD_SCB_NOT_EMPTY__SIZE, 0x00000001 +.set CYFLD_SCB_FULL__OFFSET, 0x00000003 +.set CYFLD_SCB_FULL__SIZE, 0x00000001 +.set CYFLD_SCB_FRAME_ERROR__OFFSET, 0x00000008 +.set CYFLD_SCB_FRAME_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_PARITY_ERROR__OFFSET, 0x00000009 +.set CYFLD_SCB_PARITY_ERROR__SIZE, 0x00000001 +.set CYFLD_SCB_BAUD_DETECT__OFFSET, 0x0000000a +.set CYFLD_SCB_BAUD_DETECT__SIZE, 0x00000001 +.set CYFLD_SCB_BREAK_DETECT__OFFSET, 0x0000000b +.set CYFLD_SCB_BREAK_DETECT__SIZE, 0x00000001 +.set CYREG_SCB0_INTR_RX_SET, 0x40240fc4 +.set CYREG_SCB0_INTR_RX_MASK, 0x40240fc8 +.set CYREG_SCB0_INTR_RX_MASKED, 0x40240fcc +.set CYDEV_SCB1_BASE, 0x40250000 +.set CYDEV_SCB1_SIZE, 0x00010000 +.set CYREG_SCB1_CTRL, 0x40250000 +.set CYREG_SCB1_STATUS, 0x40250004 +.set CYREG_SCB1_SPI_CTRL, 0x40250020 +.set CYREG_SCB1_SPI_STATUS, 0x40250024 +.set CYREG_SCB1_UART_CTRL, 0x40250040 +.set CYREG_SCB1_UART_TX_CTRL, 0x40250044 +.set CYREG_SCB1_UART_RX_CTRL, 0x40250048 +.set CYREG_SCB1_UART_RX_STATUS, 0x4025004c +.set CYREG_SCB1_UART_FLOW_CTRL, 0x40250050 +.set CYREG_SCB1_I2C_CTRL, 0x40250060 +.set CYREG_SCB1_I2C_STATUS, 0x40250064 +.set CYREG_SCB1_I2C_M_CMD, 0x40250068 +.set CYREG_SCB1_I2C_S_CMD, 0x4025006c +.set CYREG_SCB1_I2C_CFG, 0x40250070 +.set CYREG_SCB1_TX_CTRL, 0x40250200 +.set CYREG_SCB1_TX_FIFO_CTRL, 0x40250204 +.set CYREG_SCB1_TX_FIFO_STATUS, 0x40250208 +.set CYREG_SCB1_TX_FIFO_WR, 0x40250240 +.set CYREG_SCB1_RX_CTRL, 0x40250300 +.set CYREG_SCB1_RX_FIFO_CTRL, 0x40250304 +.set CYREG_SCB1_RX_FIFO_STATUS, 0x40250308 +.set CYREG_SCB1_RX_MATCH, 0x40250310 +.set CYREG_SCB1_RX_FIFO_RD, 0x40250340 +.set CYREG_SCB1_RX_FIFO_RD_SILENT, 0x40250344 +.set CYREG_SCB1_EZ_DATA0, 0x40250400 +.set CYREG_SCB1_EZ_DATA1, 0x40250404 +.set CYREG_SCB1_EZ_DATA2, 0x40250408 +.set CYREG_SCB1_EZ_DATA3, 0x4025040c +.set CYREG_SCB1_EZ_DATA4, 0x40250410 +.set CYREG_SCB1_EZ_DATA5, 0x40250414 +.set CYREG_SCB1_EZ_DATA6, 0x40250418 +.set CYREG_SCB1_EZ_DATA7, 0x4025041c +.set CYREG_SCB1_EZ_DATA8, 0x40250420 +.set CYREG_SCB1_EZ_DATA9, 0x40250424 +.set CYREG_SCB1_EZ_DATA10, 0x40250428 +.set CYREG_SCB1_EZ_DATA11, 0x4025042c +.set CYREG_SCB1_EZ_DATA12, 0x40250430 +.set CYREG_SCB1_EZ_DATA13, 0x40250434 +.set CYREG_SCB1_EZ_DATA14, 0x40250438 +.set CYREG_SCB1_EZ_DATA15, 0x4025043c +.set CYREG_SCB1_EZ_DATA16, 0x40250440 +.set CYREG_SCB1_EZ_DATA17, 0x40250444 +.set CYREG_SCB1_EZ_DATA18, 0x40250448 +.set CYREG_SCB1_EZ_DATA19, 0x4025044c +.set CYREG_SCB1_EZ_DATA20, 0x40250450 +.set CYREG_SCB1_EZ_DATA21, 0x40250454 +.set CYREG_SCB1_EZ_DATA22, 0x40250458 +.set CYREG_SCB1_EZ_DATA23, 0x4025045c +.set CYREG_SCB1_EZ_DATA24, 0x40250460 +.set CYREG_SCB1_EZ_DATA25, 0x40250464 +.set CYREG_SCB1_EZ_DATA26, 0x40250468 +.set CYREG_SCB1_EZ_DATA27, 0x4025046c +.set CYREG_SCB1_EZ_DATA28, 0x40250470 +.set CYREG_SCB1_EZ_DATA29, 0x40250474 +.set CYREG_SCB1_EZ_DATA30, 0x40250478 +.set CYREG_SCB1_EZ_DATA31, 0x4025047c +.set CYREG_SCB1_INTR_CAUSE, 0x40250e00 +.set CYREG_SCB1_INTR_I2C_EC, 0x40250e80 +.set CYREG_SCB1_INTR_I2C_EC_MASK, 0x40250e88 +.set CYREG_SCB1_INTR_I2C_EC_MASKED, 0x40250e8c +.set CYREG_SCB1_INTR_SPI_EC, 0x40250ec0 +.set CYREG_SCB1_INTR_SPI_EC_MASK, 0x40250ec8 +.set CYREG_SCB1_INTR_SPI_EC_MASKED, 0x40250ecc +.set CYREG_SCB1_INTR_M, 0x40250f00 +.set CYREG_SCB1_INTR_M_SET, 0x40250f04 +.set CYREG_SCB1_INTR_M_MASK, 0x40250f08 +.set CYREG_SCB1_INTR_M_MASKED, 0x40250f0c +.set CYREG_SCB1_INTR_S, 0x40250f40 +.set CYREG_SCB1_INTR_S_SET, 0x40250f44 +.set CYREG_SCB1_INTR_S_MASK, 0x40250f48 +.set CYREG_SCB1_INTR_S_MASKED, 0x40250f4c +.set CYREG_SCB1_INTR_TX, 0x40250f80 +.set CYREG_SCB1_INTR_TX_SET, 0x40250f84 +.set CYREG_SCB1_INTR_TX_MASK, 0x40250f88 +.set CYREG_SCB1_INTR_TX_MASKED, 0x40250f8c +.set CYREG_SCB1_INTR_RX, 0x40250fc0 +.set CYREG_SCB1_INTR_RX_SET, 0x40250fc4 +.set CYREG_SCB1_INTR_RX_MASK, 0x40250fc8 +.set CYREG_SCB1_INTR_RX_MASKED, 0x40250fcc +.set CYDEV_SCB2_BASE, 0x40260000 +.set CYDEV_SCB2_SIZE, 0x00010000 +.set CYREG_SCB2_CTRL, 0x40260000 +.set CYREG_SCB2_STATUS, 0x40260004 +.set CYREG_SCB2_SPI_CTRL, 0x40260020 +.set CYREG_SCB2_SPI_STATUS, 0x40260024 +.set CYREG_SCB2_UART_CTRL, 0x40260040 +.set CYREG_SCB2_UART_TX_CTRL, 0x40260044 +.set CYREG_SCB2_UART_RX_CTRL, 0x40260048 +.set CYREG_SCB2_UART_RX_STATUS, 0x4026004c +.set CYREG_SCB2_UART_FLOW_CTRL, 0x40260050 +.set CYREG_SCB2_I2C_CTRL, 0x40260060 +.set CYREG_SCB2_I2C_STATUS, 0x40260064 +.set CYREG_SCB2_I2C_M_CMD, 0x40260068 +.set CYREG_SCB2_I2C_S_CMD, 0x4026006c +.set CYREG_SCB2_I2C_CFG, 0x40260070 +.set CYREG_SCB2_TX_CTRL, 0x40260200 +.set CYREG_SCB2_TX_FIFO_CTRL, 0x40260204 +.set CYREG_SCB2_TX_FIFO_STATUS, 0x40260208 +.set CYREG_SCB2_TX_FIFO_WR, 0x40260240 +.set CYREG_SCB2_RX_CTRL, 0x40260300 +.set CYREG_SCB2_RX_FIFO_CTRL, 0x40260304 +.set CYREG_SCB2_RX_FIFO_STATUS, 0x40260308 +.set CYREG_SCB2_RX_MATCH, 0x40260310 +.set CYREG_SCB2_RX_FIFO_RD, 0x40260340 +.set CYREG_SCB2_RX_FIFO_RD_SILENT, 0x40260344 +.set CYREG_SCB2_EZ_DATA0, 0x40260400 +.set CYREG_SCB2_EZ_DATA1, 0x40260404 +.set CYREG_SCB2_EZ_DATA2, 0x40260408 +.set CYREG_SCB2_EZ_DATA3, 0x4026040c +.set CYREG_SCB2_EZ_DATA4, 0x40260410 +.set CYREG_SCB2_EZ_DATA5, 0x40260414 +.set CYREG_SCB2_EZ_DATA6, 0x40260418 +.set CYREG_SCB2_EZ_DATA7, 0x4026041c +.set CYREG_SCB2_EZ_DATA8, 0x40260420 +.set CYREG_SCB2_EZ_DATA9, 0x40260424 +.set CYREG_SCB2_EZ_DATA10, 0x40260428 +.set CYREG_SCB2_EZ_DATA11, 0x4026042c +.set CYREG_SCB2_EZ_DATA12, 0x40260430 +.set CYREG_SCB2_EZ_DATA13, 0x40260434 +.set CYREG_SCB2_EZ_DATA14, 0x40260438 +.set CYREG_SCB2_EZ_DATA15, 0x4026043c +.set CYREG_SCB2_EZ_DATA16, 0x40260440 +.set CYREG_SCB2_EZ_DATA17, 0x40260444 +.set CYREG_SCB2_EZ_DATA18, 0x40260448 +.set CYREG_SCB2_EZ_DATA19, 0x4026044c +.set CYREG_SCB2_EZ_DATA20, 0x40260450 +.set CYREG_SCB2_EZ_DATA21, 0x40260454 +.set CYREG_SCB2_EZ_DATA22, 0x40260458 +.set CYREG_SCB2_EZ_DATA23, 0x4026045c +.set CYREG_SCB2_EZ_DATA24, 0x40260460 +.set CYREG_SCB2_EZ_DATA25, 0x40260464 +.set CYREG_SCB2_EZ_DATA26, 0x40260468 +.set CYREG_SCB2_EZ_DATA27, 0x4026046c +.set CYREG_SCB2_EZ_DATA28, 0x40260470 +.set CYREG_SCB2_EZ_DATA29, 0x40260474 +.set CYREG_SCB2_EZ_DATA30, 0x40260478 +.set CYREG_SCB2_EZ_DATA31, 0x4026047c +.set CYREG_SCB2_INTR_CAUSE, 0x40260e00 +.set CYREG_SCB2_INTR_I2C_EC, 0x40260e80 +.set CYREG_SCB2_INTR_I2C_EC_MASK, 0x40260e88 +.set CYREG_SCB2_INTR_I2C_EC_MASKED, 0x40260e8c +.set CYREG_SCB2_INTR_SPI_EC, 0x40260ec0 +.set CYREG_SCB2_INTR_SPI_EC_MASK, 0x40260ec8 +.set CYREG_SCB2_INTR_SPI_EC_MASKED, 0x40260ecc +.set CYREG_SCB2_INTR_M, 0x40260f00 +.set CYREG_SCB2_INTR_M_SET, 0x40260f04 +.set CYREG_SCB2_INTR_M_MASK, 0x40260f08 +.set CYREG_SCB2_INTR_M_MASKED, 0x40260f0c +.set CYREG_SCB2_INTR_S, 0x40260f40 +.set CYREG_SCB2_INTR_S_SET, 0x40260f44 +.set CYREG_SCB2_INTR_S_MASK, 0x40260f48 +.set CYREG_SCB2_INTR_S_MASKED, 0x40260f4c +.set CYREG_SCB2_INTR_TX, 0x40260f80 +.set CYREG_SCB2_INTR_TX_SET, 0x40260f84 +.set CYREG_SCB2_INTR_TX_MASK, 0x40260f88 +.set CYREG_SCB2_INTR_TX_MASKED, 0x40260f8c +.set CYREG_SCB2_INTR_RX, 0x40260fc0 +.set CYREG_SCB2_INTR_RX_SET, 0x40260fc4 +.set CYREG_SCB2_INTR_RX_MASK, 0x40260fc8 +.set CYREG_SCB2_INTR_RX_MASKED, 0x40260fcc +.set CYDEV_SCB3_BASE, 0x40270000 +.set CYDEV_SCB3_SIZE, 0x00010000 +.set CYREG_SCB3_CTRL, 0x40270000 +.set CYREG_SCB3_STATUS, 0x40270004 +.set CYREG_SCB3_SPI_CTRL, 0x40270020 +.set CYREG_SCB3_SPI_STATUS, 0x40270024 +.set CYREG_SCB3_UART_CTRL, 0x40270040 +.set CYREG_SCB3_UART_TX_CTRL, 0x40270044 +.set CYREG_SCB3_UART_RX_CTRL, 0x40270048 +.set CYREG_SCB3_UART_RX_STATUS, 0x4027004c +.set CYREG_SCB3_UART_FLOW_CTRL, 0x40270050 +.set CYREG_SCB3_I2C_CTRL, 0x40270060 +.set CYREG_SCB3_I2C_STATUS, 0x40270064 +.set CYREG_SCB3_I2C_M_CMD, 0x40270068 +.set CYREG_SCB3_I2C_S_CMD, 0x4027006c +.set CYREG_SCB3_I2C_CFG, 0x40270070 +.set CYREG_SCB3_TX_CTRL, 0x40270200 +.set CYREG_SCB3_TX_FIFO_CTRL, 0x40270204 +.set CYREG_SCB3_TX_FIFO_STATUS, 0x40270208 +.set CYREG_SCB3_TX_FIFO_WR, 0x40270240 +.set CYREG_SCB3_RX_CTRL, 0x40270300 +.set CYREG_SCB3_RX_FIFO_CTRL, 0x40270304 +.set CYREG_SCB3_RX_FIFO_STATUS, 0x40270308 +.set CYREG_SCB3_RX_MATCH, 0x40270310 +.set CYREG_SCB3_RX_FIFO_RD, 0x40270340 +.set CYREG_SCB3_RX_FIFO_RD_SILENT, 0x40270344 +.set CYREG_SCB3_EZ_DATA0, 0x40270400 +.set CYREG_SCB3_EZ_DATA1, 0x40270404 +.set CYREG_SCB3_EZ_DATA2, 0x40270408 +.set CYREG_SCB3_EZ_DATA3, 0x4027040c +.set CYREG_SCB3_EZ_DATA4, 0x40270410 +.set CYREG_SCB3_EZ_DATA5, 0x40270414 +.set CYREG_SCB3_EZ_DATA6, 0x40270418 +.set CYREG_SCB3_EZ_DATA7, 0x4027041c +.set CYREG_SCB3_EZ_DATA8, 0x40270420 +.set CYREG_SCB3_EZ_DATA9, 0x40270424 +.set CYREG_SCB3_EZ_DATA10, 0x40270428 +.set CYREG_SCB3_EZ_DATA11, 0x4027042c +.set CYREG_SCB3_EZ_DATA12, 0x40270430 +.set CYREG_SCB3_EZ_DATA13, 0x40270434 +.set CYREG_SCB3_EZ_DATA14, 0x40270438 +.set CYREG_SCB3_EZ_DATA15, 0x4027043c +.set CYREG_SCB3_EZ_DATA16, 0x40270440 +.set CYREG_SCB3_EZ_DATA17, 0x40270444 +.set CYREG_SCB3_EZ_DATA18, 0x40270448 +.set CYREG_SCB3_EZ_DATA19, 0x4027044c +.set CYREG_SCB3_EZ_DATA20, 0x40270450 +.set CYREG_SCB3_EZ_DATA21, 0x40270454 +.set CYREG_SCB3_EZ_DATA22, 0x40270458 +.set CYREG_SCB3_EZ_DATA23, 0x4027045c +.set CYREG_SCB3_EZ_DATA24, 0x40270460 +.set CYREG_SCB3_EZ_DATA25, 0x40270464 +.set CYREG_SCB3_EZ_DATA26, 0x40270468 +.set CYREG_SCB3_EZ_DATA27, 0x4027046c +.set CYREG_SCB3_EZ_DATA28, 0x40270470 +.set CYREG_SCB3_EZ_DATA29, 0x40270474 +.set CYREG_SCB3_EZ_DATA30, 0x40270478 +.set CYREG_SCB3_EZ_DATA31, 0x4027047c +.set CYREG_SCB3_INTR_CAUSE, 0x40270e00 +.set CYREG_SCB3_INTR_I2C_EC, 0x40270e80 +.set CYREG_SCB3_INTR_I2C_EC_MASK, 0x40270e88 +.set CYREG_SCB3_INTR_I2C_EC_MASKED, 0x40270e8c +.set CYREG_SCB3_INTR_SPI_EC, 0x40270ec0 +.set CYREG_SCB3_INTR_SPI_EC_MASK, 0x40270ec8 +.set CYREG_SCB3_INTR_SPI_EC_MASKED, 0x40270ecc +.set CYREG_SCB3_INTR_M, 0x40270f00 +.set CYREG_SCB3_INTR_M_SET, 0x40270f04 +.set CYREG_SCB3_INTR_M_MASK, 0x40270f08 +.set CYREG_SCB3_INTR_M_MASKED, 0x40270f0c +.set CYREG_SCB3_INTR_S, 0x40270f40 +.set CYREG_SCB3_INTR_S_SET, 0x40270f44 +.set CYREG_SCB3_INTR_S_MASK, 0x40270f48 +.set CYREG_SCB3_INTR_S_MASKED, 0x40270f4c +.set CYREG_SCB3_INTR_TX, 0x40270f80 +.set CYREG_SCB3_INTR_TX_SET, 0x40270f84 +.set CYREG_SCB3_INTR_TX_MASK, 0x40270f88 +.set CYREG_SCB3_INTR_TX_MASKED, 0x40270f8c +.set CYREG_SCB3_INTR_RX, 0x40270fc0 +.set CYREG_SCB3_INTR_RX_SET, 0x40270fc4 +.set CYREG_SCB3_INTR_RX_MASK, 0x40270fc8 +.set CYREG_SCB3_INTR_RX_MASKED, 0x40270fcc +.set CYDEV_SCB4_BASE, 0x40280000 +.set CYDEV_SCB4_SIZE, 0x00010000 +.set CYREG_SCB4_CTRL, 0x40280000 +.set CYREG_SCB4_STATUS, 0x40280004 +.set CYREG_SCB4_SPI_CTRL, 0x40280020 +.set CYREG_SCB4_SPI_STATUS, 0x40280024 +.set CYREG_SCB4_UART_CTRL, 0x40280040 +.set CYREG_SCB4_UART_TX_CTRL, 0x40280044 +.set CYREG_SCB4_UART_RX_CTRL, 0x40280048 +.set CYREG_SCB4_UART_RX_STATUS, 0x4028004c +.set CYREG_SCB4_UART_FLOW_CTRL, 0x40280050 +.set CYREG_SCB4_I2C_CTRL, 0x40280060 +.set CYREG_SCB4_I2C_STATUS, 0x40280064 +.set CYREG_SCB4_I2C_M_CMD, 0x40280068 +.set CYREG_SCB4_I2C_S_CMD, 0x4028006c +.set CYREG_SCB4_I2C_CFG, 0x40280070 +.set CYREG_SCB4_TX_CTRL, 0x40280200 +.set CYREG_SCB4_TX_FIFO_CTRL, 0x40280204 +.set CYREG_SCB4_TX_FIFO_STATUS, 0x40280208 +.set CYREG_SCB4_TX_FIFO_WR, 0x40280240 +.set CYREG_SCB4_RX_CTRL, 0x40280300 +.set CYREG_SCB4_RX_FIFO_CTRL, 0x40280304 +.set CYREG_SCB4_RX_FIFO_STATUS, 0x40280308 +.set CYREG_SCB4_RX_MATCH, 0x40280310 +.set CYREG_SCB4_RX_FIFO_RD, 0x40280340 +.set CYREG_SCB4_RX_FIFO_RD_SILENT, 0x40280344 +.set CYREG_SCB4_EZ_DATA0, 0x40280400 +.set CYREG_SCB4_EZ_DATA1, 0x40280404 +.set CYREG_SCB4_EZ_DATA2, 0x40280408 +.set CYREG_SCB4_EZ_DATA3, 0x4028040c +.set CYREG_SCB4_EZ_DATA4, 0x40280410 +.set CYREG_SCB4_EZ_DATA5, 0x40280414 +.set CYREG_SCB4_EZ_DATA6, 0x40280418 +.set CYREG_SCB4_EZ_DATA7, 0x4028041c +.set CYREG_SCB4_EZ_DATA8, 0x40280420 +.set CYREG_SCB4_EZ_DATA9, 0x40280424 +.set CYREG_SCB4_EZ_DATA10, 0x40280428 +.set CYREG_SCB4_EZ_DATA11, 0x4028042c +.set CYREG_SCB4_EZ_DATA12, 0x40280430 +.set CYREG_SCB4_EZ_DATA13, 0x40280434 +.set CYREG_SCB4_EZ_DATA14, 0x40280438 +.set CYREG_SCB4_EZ_DATA15, 0x4028043c +.set CYREG_SCB4_EZ_DATA16, 0x40280440 +.set CYREG_SCB4_EZ_DATA17, 0x40280444 +.set CYREG_SCB4_EZ_DATA18, 0x40280448 +.set CYREG_SCB4_EZ_DATA19, 0x4028044c +.set CYREG_SCB4_EZ_DATA20, 0x40280450 +.set CYREG_SCB4_EZ_DATA21, 0x40280454 +.set CYREG_SCB4_EZ_DATA22, 0x40280458 +.set CYREG_SCB4_EZ_DATA23, 0x4028045c +.set CYREG_SCB4_EZ_DATA24, 0x40280460 +.set CYREG_SCB4_EZ_DATA25, 0x40280464 +.set CYREG_SCB4_EZ_DATA26, 0x40280468 +.set CYREG_SCB4_EZ_DATA27, 0x4028046c +.set CYREG_SCB4_EZ_DATA28, 0x40280470 +.set CYREG_SCB4_EZ_DATA29, 0x40280474 +.set CYREG_SCB4_EZ_DATA30, 0x40280478 +.set CYREG_SCB4_EZ_DATA31, 0x4028047c +.set CYREG_SCB4_INTR_CAUSE, 0x40280e00 +.set CYREG_SCB4_INTR_I2C_EC, 0x40280e80 +.set CYREG_SCB4_INTR_I2C_EC_MASK, 0x40280e88 +.set CYREG_SCB4_INTR_I2C_EC_MASKED, 0x40280e8c +.set CYREG_SCB4_INTR_SPI_EC, 0x40280ec0 +.set CYREG_SCB4_INTR_SPI_EC_MASK, 0x40280ec8 +.set CYREG_SCB4_INTR_SPI_EC_MASKED, 0x40280ecc +.set CYREG_SCB4_INTR_M, 0x40280f00 +.set CYREG_SCB4_INTR_M_SET, 0x40280f04 +.set CYREG_SCB4_INTR_M_MASK, 0x40280f08 +.set CYREG_SCB4_INTR_M_MASKED, 0x40280f0c +.set CYREG_SCB4_INTR_S, 0x40280f40 +.set CYREG_SCB4_INTR_S_SET, 0x40280f44 +.set CYREG_SCB4_INTR_S_MASK, 0x40280f48 +.set CYREG_SCB4_INTR_S_MASKED, 0x40280f4c +.set CYREG_SCB4_INTR_TX, 0x40280f80 +.set CYREG_SCB4_INTR_TX_SET, 0x40280f84 +.set CYREG_SCB4_INTR_TX_MASK, 0x40280f88 +.set CYREG_SCB4_INTR_TX_MASKED, 0x40280f8c +.set CYREG_SCB4_INTR_RX, 0x40280fc0 +.set CYREG_SCB4_INTR_RX_SET, 0x40280fc4 +.set CYREG_SCB4_INTR_RX_MASK, 0x40280fc8 +.set CYREG_SCB4_INTR_RX_MASKED, 0x40280fcc +.set CYDEV_CSD_BASE, 0x40290000 +.set CYDEV_CSD_SIZE, 0x00001000 +.set CYREG_CSD_CONFIG, 0x40290000 +.set CYFLD_CSD_LOW_VDDA__OFFSET, 0x00000003 +.set CYFLD_CSD_LOW_VDDA__SIZE, 0x00000001 +.set CYFLD_CSD_FILTER_DELAY__OFFSET, 0x00000004 +.set CYFLD_CSD_FILTER_DELAY__SIZE, 0x00000003 +.set CYFLD_CSD_SHIELD_DELAY__OFFSET, 0x00000008 +.set CYFLD_CSD_SHIELD_DELAY__SIZE, 0x00000002 +.set CYVAL_CSD_SHIELD_DELAY_OFF, 0x00000000 +.set CYVAL_CSD_SHIELD_DELAY_D5NS, 0x00000001 +.set CYVAL_CSD_SHIELD_DELAY_D10NS, 0x00000002 +.set CYVAL_CSD_SHIELD_DELAY_D20NS, 0x00000003 +.set CYFLD_CSD_SENSE_EN__OFFSET, 0x0000000c +.set CYFLD_CSD_SENSE_EN__SIZE, 0x00000001 +.set CYFLD_CSD_CHARGE_MODE__OFFSET, 0x0000000e +.set CYFLD_CSD_CHARGE_MODE__SIZE, 0x00000001 +.set CYVAL_CSD_CHARGE_MODE_CHARGE_OFF, 0x00000000 +.set CYVAL_CSD_CHARGE_MODE_CHARGE_IO, 0x00000001 +.set CYFLD_CSD_FULL_WAVE__OFFSET, 0x00000011 +.set CYFLD_CSD_FULL_WAVE__SIZE, 0x00000001 +.set CYVAL_CSD_FULL_WAVE_HALFWAVE, 0x00000000 +.set CYVAL_CSD_FULL_WAVE_FULLWAVE, 0x00000001 +.set CYFLD_CSD_MUTUAL_CAP__OFFSET, 0x00000012 +.set CYFLD_CSD_MUTUAL_CAP__SIZE, 0x00000001 +.set CYVAL_CSD_MUTUAL_CAP_SELFCAP, 0x00000000 +.set CYVAL_CSD_MUTUAL_CAP_MUTUALCAP, 0x00000001 +.set CYFLD_CSD_CSX_DUAL_CNT__OFFSET, 0x00000013 +.set CYFLD_CSD_CSX_DUAL_CNT__SIZE, 0x00000001 +.set CYVAL_CSD_CSX_DUAL_CNT_ONE, 0x00000000 +.set CYVAL_CSD_CSX_DUAL_CNT_TWO, 0x00000001 +.set CYFLD_CSD_DSI_COUNT_SEL__OFFSET, 0x00000018 +.set CYFLD_CSD_DSI_COUNT_SEL__SIZE, 0x00000001 +.set CYVAL_CSD_DSI_COUNT_SEL_CSD_RESULT, 0x00000000 +.set CYVAL_CSD_DSI_COUNT_SEL_ADC_RESULT, 0x00000001 +.set CYFLD_CSD_DSI_SAMPLE_EN__OFFSET, 0x00000019 +.set CYFLD_CSD_DSI_SAMPLE_EN__SIZE, 0x00000001 +.set CYFLD_CSD_SAMPLE_SYNC__OFFSET, 0x0000001a +.set CYFLD_CSD_SAMPLE_SYNC__SIZE, 0x00000001 +.set CYFLD_CSD_DSI_SENSE_EN__OFFSET, 0x0000001b +.set CYFLD_CSD_DSI_SENSE_EN__SIZE, 0x00000001 +.set CYFLD_CSD_LP_MODE__OFFSET, 0x0000001e +.set CYFLD_CSD_LP_MODE__SIZE, 0x00000001 +.set CYFLD_CSD_ENABLE__OFFSET, 0x0000001f +.set CYFLD_CSD_ENABLE__SIZE, 0x00000001 +.set CYREG_CSD_SPARE, 0x40290004 +.set CYFLD_CSD_SPARE__OFFSET, 0x00000000 +.set CYFLD_CSD_SPARE__SIZE, 0x00000004 +.set CYREG_CSD_STATUS, 0x40290080 +.set CYFLD_CSD_CSD_CHARGE__OFFSET, 0x00000000 +.set CYFLD_CSD_CSD_CHARGE__SIZE, 0x00000001 +.set CYFLD_CSD_CSD_SENSE__OFFSET, 0x00000001 +.set CYFLD_CSD_CSD_SENSE__SIZE, 0x00000001 +.set CYFLD_CSD_HSCMP_OUT__OFFSET, 0x00000002 +.set CYFLD_CSD_HSCMP_OUT__SIZE, 0x00000001 +.set CYVAL_CSD_HSCMP_OUT_C_LT_VREF, 0x00000000 +.set CYVAL_CSD_HSCMP_OUT_C_GT_VREF, 0x00000001 +.set CYFLD_CSD_CSDCMP_OUT__OFFSET, 0x00000003 +.set CYFLD_CSD_CSDCMP_OUT__SIZE, 0x00000001 +.set CYREG_CSD_STAT_SEQ, 0x40290084 +.set CYFLD_CSD_SEQ_STATE__OFFSET, 0x00000000 +.set CYFLD_CSD_SEQ_STATE__SIZE, 0x00000003 +.set CYFLD_CSD_ADC_STATE__OFFSET, 0x00000010 +.set CYFLD_CSD_ADC_STATE__SIZE, 0x00000003 +.set CYREG_CSD_STAT_CNTS, 0x40290088 +.set CYFLD_CSD_NUM_CONV__OFFSET, 0x00000000 +.set CYFLD_CSD_NUM_CONV__SIZE, 0x00000010 +.set CYREG_CSD_STAT_HCNT, 0x4029008c +.set CYFLD_CSD_CNT__OFFSET, 0x00000000 +.set CYFLD_CSD_CNT__SIZE, 0x00000010 +.set CYREG_CSD_RESULT_VAL1, 0x402900d0 +.set CYFLD_CSD_VALUE__OFFSET, 0x00000000 +.set CYFLD_CSD_VALUE__SIZE, 0x00000010 +.set CYFLD_CSD_BAD_CONVS__OFFSET, 0x00000010 +.set CYFLD_CSD_BAD_CONVS__SIZE, 0x00000008 +.set CYREG_CSD_RESULT_VAL2, 0x402900d4 +.set CYREG_CSD_ADC_RES, 0x402900e0 +.set CYFLD_CSD_VIN_CNT__OFFSET, 0x00000000 +.set CYFLD_CSD_VIN_CNT__SIZE, 0x00000010 +.set CYFLD_CSD_HSCMP_POL__OFFSET, 0x00000010 +.set CYFLD_CSD_HSCMP_POL__SIZE, 0x00000001 +.set CYFLD_CSD_ADC_OVERFLOW__OFFSET, 0x0000001e +.set CYFLD_CSD_ADC_OVERFLOW__SIZE, 0x00000001 +.set CYFLD_CSD_ADC_ABORT__OFFSET, 0x0000001f +.set CYFLD_CSD_ADC_ABORT__SIZE, 0x00000001 +.set CYREG_CSD_INTR, 0x402900f0 +.set CYFLD_CSD_SAMPLE__OFFSET, 0x00000001 +.set CYFLD_CSD_SAMPLE__SIZE, 0x00000001 +.set CYFLD_CSD_INIT__OFFSET, 0x00000002 +.set CYFLD_CSD_INIT__SIZE, 0x00000001 +.set CYFLD_CSD_ADC_RES__OFFSET, 0x00000008 +.set CYFLD_CSD_ADC_RES__SIZE, 0x00000001 +.set CYREG_CSD_INTR_SET, 0x402900f4 +.set CYREG_CSD_INTR_MASK, 0x402900f8 +.set CYREG_CSD_INTR_MASKED, 0x402900fc +.set CYREG_CSD_HSCMP, 0x40290180 +.set CYFLD_CSD_HSCMP_EN__OFFSET, 0x00000000 +.set CYFLD_CSD_HSCMP_EN__SIZE, 0x00000001 +.set CYVAL_CSD_HSCMP_EN_OFF, 0x00000000 +.set CYVAL_CSD_HSCMP_EN_ON, 0x00000001 +.set CYFLD_CSD_HSCMP_INVERT__OFFSET, 0x00000004 +.set CYFLD_CSD_HSCMP_INVERT__SIZE, 0x00000001 +.set CYFLD_CSD_AZ_EN__OFFSET, 0x0000001f +.set CYFLD_CSD_AZ_EN__SIZE, 0x00000001 +.set CYREG_CSD_AMBUF, 0x40290184 +.set CYFLD_CSD_PWR_MODE__OFFSET, 0x00000000 +.set CYFLD_CSD_PWR_MODE__SIZE, 0x00000002 +.set CYVAL_CSD_PWR_MODE_OFF, 0x00000000 +.set CYVAL_CSD_PWR_MODE_NORM, 0x00000001 +.set CYVAL_CSD_PWR_MODE_HI, 0x00000002 +.set CYREG_CSD_REFGEN, 0x40290188 +.set CYFLD_CSD_REFGEN_EN__OFFSET, 0x00000000 +.set CYFLD_CSD_REFGEN_EN__SIZE, 0x00000001 +.set CYVAL_CSD_REFGEN_EN_OFF, 0x00000000 +.set CYVAL_CSD_REFGEN_EN_ON, 0x00000001 +.set CYFLD_CSD_BYPASS__OFFSET, 0x00000004 +.set CYFLD_CSD_BYPASS__SIZE, 0x00000001 +.set CYFLD_CSD_VDDA_EN__OFFSET, 0x00000005 +.set CYFLD_CSD_VDDA_EN__SIZE, 0x00000001 +.set CYFLD_CSD_RES_EN__OFFSET, 0x00000006 +.set CYFLD_CSD_RES_EN__SIZE, 0x00000001 +.set CYFLD_CSD_GAIN__OFFSET, 0x00000008 +.set CYFLD_CSD_GAIN__SIZE, 0x00000005 +.set CYFLD_CSD_VREFLO_SEL__OFFSET, 0x00000010 +.set CYFLD_CSD_VREFLO_SEL__SIZE, 0x00000005 +.set CYFLD_CSD_VREFLO_INT__OFFSET, 0x00000017 +.set CYFLD_CSD_VREFLO_INT__SIZE, 0x00000001 +.set CYREG_CSD_CSDCMP, 0x4029018c +.set CYFLD_CSD_CSDCMP_EN__OFFSET, 0x00000000 +.set CYFLD_CSD_CSDCMP_EN__SIZE, 0x00000001 +.set CYVAL_CSD_CSDCMP_EN_OFF, 0x00000000 +.set CYVAL_CSD_CSDCMP_EN_ON, 0x00000001 +.set CYFLD_CSD_POLARITY_SEL__OFFSET, 0x00000004 +.set CYFLD_CSD_POLARITY_SEL__SIZE, 0x00000002 +.set CYVAL_CSD_POLARITY_SEL_IDACA_POL, 0x00000000 +.set CYVAL_CSD_POLARITY_SEL_IDACB_POL, 0x00000001 +.set CYVAL_CSD_POLARITY_SEL_DUAL_POL, 0x00000002 +.set CYFLD_CSD_CMP_PHASE__OFFSET, 0x00000008 +.set CYFLD_CSD_CMP_PHASE__SIZE, 0x00000002 +.set CYVAL_CSD_CMP_PHASE_FULL, 0x00000000 +.set CYVAL_CSD_CMP_PHASE_PHI1, 0x00000001 +.set CYVAL_CSD_CMP_PHASE_PHI2, 0x00000002 +.set CYVAL_CSD_CMP_PHASE_PHI1_2, 0x00000003 +.set CYFLD_CSD_CMP_MODE__OFFSET, 0x0000001c +.set CYFLD_CSD_CMP_MODE__SIZE, 0x00000001 +.set CYVAL_CSD_CMP_MODE_CSD, 0x00000000 +.set CYVAL_CSD_CMP_MODE_GP, 0x00000001 +.set CYFLD_CSD_FEEDBACK_MODE__OFFSET, 0x0000001d +.set CYFLD_CSD_FEEDBACK_MODE__SIZE, 0x00000001 +.set CYVAL_CSD_FEEDBACK_MODE_FLOP, 0x00000000 +.set CYVAL_CSD_FEEDBACK_MODE_COMP, 0x00000001 +.set CYREG_CSD_IDACA, 0x402901c0 +.set CYFLD_CSD_VAL__OFFSET, 0x00000000 +.set CYFLD_CSD_VAL__SIZE, 0x00000007 +.set CYFLD_CSD_POL_DYN__OFFSET, 0x00000007 +.set CYFLD_CSD_POL_DYN__SIZE, 0x00000001 +.set CYVAL_CSD_POL_DYN_STATIC, 0x00000000 +.set CYVAL_CSD_POL_DYN_DYNAMIC, 0x00000001 +.set CYFLD_CSD_POLARITY__OFFSET, 0x00000008 +.set CYFLD_CSD_POLARITY__SIZE, 0x00000002 +.set CYVAL_CSD_POLARITY_VSSA_SRC, 0x00000000 +.set CYVAL_CSD_POLARITY_VDDA_SNK, 0x00000001 +.set CYVAL_CSD_POLARITY_SENSE, 0x00000002 +.set CYVAL_CSD_POLARITY_SENSE_INV, 0x00000003 +.set CYFLD_CSD_BAL_MODE__OFFSET, 0x0000000a +.set CYFLD_CSD_BAL_MODE__SIZE, 0x00000002 +.set CYVAL_CSD_BAL_MODE_FULL, 0x00000000 +.set CYVAL_CSD_BAL_MODE_PHI1, 0x00000001 +.set CYVAL_CSD_BAL_MODE_PHI2, 0x00000002 +.set CYVAL_CSD_BAL_MODE_PHI1_2, 0x00000003 +.set CYFLD_CSD_LEG1_MODE__OFFSET, 0x00000010 +.set CYFLD_CSD_LEG1_MODE__SIZE, 0x00000002 +.set CYVAL_CSD_LEG1_MODE_GP_STATIC, 0x00000000 +.set CYVAL_CSD_LEG1_MODE_GP, 0x00000001 +.set CYVAL_CSD_LEG1_MODE_CSD_STATIC, 0x00000002 +.set CYVAL_CSD_LEG1_MODE_CSD, 0x00000003 +.set CYFLD_CSD_LEG2_MODE__OFFSET, 0x00000012 +.set CYFLD_CSD_LEG2_MODE__SIZE, 0x00000002 +.set CYVAL_CSD_LEG2_MODE_GP_STATIC, 0x00000000 +.set CYVAL_CSD_LEG2_MODE_GP, 0x00000001 +.set CYVAL_CSD_LEG2_MODE_CSD_STATIC, 0x00000002 +.set CYVAL_CSD_LEG2_MODE_CSD, 0x00000003 +.set CYFLD_CSD_DSI_CTRL_EN__OFFSET, 0x00000015 +.set CYFLD_CSD_DSI_CTRL_EN__SIZE, 0x00000001 +.set CYFLD_CSD_RANGE__OFFSET, 0x00000016 +.set CYFLD_CSD_RANGE__SIZE, 0x00000002 +.set CYVAL_CSD_RANGE_IDAC_LO, 0x00000000 +.set CYVAL_CSD_RANGE_IDAC_MED, 0x00000001 +.set CYVAL_CSD_RANGE_IDAC_HI, 0x00000002 +.set CYVAL_CSD_RANGE_IDAC_MED2, 0x00000003 +.set CYFLD_CSD_LEG1_EN__OFFSET, 0x00000018 +.set CYFLD_CSD_LEG1_EN__SIZE, 0x00000001 +.set CYFLD_CSD_LEG2_EN__OFFSET, 0x00000019 +.set CYFLD_CSD_LEG2_EN__SIZE, 0x00000001 +.set CYREG_CSD_IDACB, 0x402901c4 +.set CYFLD_CSD_LEG3_EN__OFFSET, 0x0000001a +.set CYFLD_CSD_LEG3_EN__SIZE, 0x00000001 +.set CYREG_CSD_SW_RES, 0x402901f0 +.set CYFLD_CSD_RES_HCAV__OFFSET, 0x00000000 +.set CYFLD_CSD_RES_HCAV__SIZE, 0x00000002 +.set CYVAL_CSD_RES_HCAV_LOW, 0x00000000 +.set CYVAL_CSD_RES_HCAV_MED, 0x00000001 +.set CYVAL_CSD_RES_HCAV_HIGH, 0x00000002 +.set CYVAL_CSD_RES_HCAV_LOWEMI, 0x00000003 +.set CYFLD_CSD_RES_HCAG__OFFSET, 0x00000002 +.set CYFLD_CSD_RES_HCAG__SIZE, 0x00000002 +.set CYFLD_CSD_RES_HCBV__OFFSET, 0x00000004 +.set CYFLD_CSD_RES_HCBV__SIZE, 0x00000002 +.set CYFLD_CSD_RES_HCBG__OFFSET, 0x00000006 +.set CYFLD_CSD_RES_HCBG__SIZE, 0x00000002 +.set CYFLD_CSD_RES_F1PM__OFFSET, 0x00000010 +.set CYFLD_CSD_RES_F1PM__SIZE, 0x00000002 +.set CYVAL_CSD_RES_F1PM_LOW, 0x00000000 +.set CYVAL_CSD_RES_F1PM_MED, 0x00000001 +.set CYVAL_CSD_RES_F1PM_HIGH, 0x00000002 +.set CYVAL_CSD_RES_F1PM_RESERVED, 0x00000003 +.set CYFLD_CSD_RES_F2PT__OFFSET, 0x00000012 +.set CYFLD_CSD_RES_F2PT__SIZE, 0x00000002 +.set CYREG_CSD_SENSE_PERIOD, 0x40290200 +.set CYFLD_CSD_SENSE_DIV__OFFSET, 0x00000000 +.set CYFLD_CSD_SENSE_DIV__SIZE, 0x0000000c +.set CYFLD_CSD_LFSR_SIZE__OFFSET, 0x00000010 +.set CYFLD_CSD_LFSR_SIZE__SIZE, 0x00000003 +.set CYVAL_CSD_LFSR_SIZE_OFF, 0x00000000 +.set CYVAL_CSD_LFSR_SIZE_6B, 0x00000001 +.set CYVAL_CSD_LFSR_SIZE_7B, 0x00000002 +.set CYVAL_CSD_LFSR_SIZE_9B, 0x00000003 +.set CYVAL_CSD_LFSR_SIZE_10B, 0x00000004 +.set CYVAL_CSD_LFSR_SIZE_8B, 0x00000005 +.set CYVAL_CSD_LFSR_SIZE_12B, 0x00000006 +.set CYFLD_CSD_LFSR_SCALE__OFFSET, 0x00000014 +.set CYFLD_CSD_LFSR_SCALE__SIZE, 0x00000004 +.set CYFLD_CSD_LFSR_CLEAR__OFFSET, 0x00000018 +.set CYFLD_CSD_LFSR_CLEAR__SIZE, 0x00000001 +.set CYFLD_CSD_SEL_LFSR_MSB__OFFSET, 0x00000019 +.set CYFLD_CSD_SEL_LFSR_MSB__SIZE, 0x00000001 +.set CYFLD_CSD_LFSR_BITS__OFFSET, 0x0000001a +.set CYFLD_CSD_LFSR_BITS__SIZE, 0x00000002 +.set CYVAL_CSD_LFSR_BITS_2B, 0x00000000 +.set CYVAL_CSD_LFSR_BITS_3B, 0x00000001 +.set CYVAL_CSD_LFSR_BITS_4B, 0x00000002 +.set CYVAL_CSD_LFSR_BITS_5B, 0x00000003 +.set CYREG_CSD_SENSE_DUTY, 0x40290204 +.set CYFLD_CSD_SENSE_WIDTH__OFFSET, 0x00000000 +.set CYFLD_CSD_SENSE_WIDTH__SIZE, 0x0000000c +.set CYFLD_CSD_SENSE_POL__OFFSET, 0x00000010 +.set CYFLD_CSD_SENSE_POL__SIZE, 0x00000001 +.set CYFLD_CSD_OVERLAP_PHI1__OFFSET, 0x00000012 +.set CYFLD_CSD_OVERLAP_PHI1__SIZE, 0x00000001 +.set CYFLD_CSD_OVERLAP_PHI2__OFFSET, 0x00000013 +.set CYFLD_CSD_OVERLAP_PHI2__SIZE, 0x00000001 +.set CYREG_CSD_SW_HS_P_SEL, 0x40290280 +.set CYFLD_CSD_SW_HMPM__OFFSET, 0x00000000 +.set CYFLD_CSD_SW_HMPM__SIZE, 0x00000001 +.set CYFLD_CSD_SW_HMPT__OFFSET, 0x00000004 +.set CYFLD_CSD_SW_HMPT__SIZE, 0x00000001 +.set CYFLD_CSD_SW_HMPS__OFFSET, 0x00000008 +.set CYFLD_CSD_SW_HMPS__SIZE, 0x00000001 +.set CYFLD_CSD_SW_HMMA__OFFSET, 0x0000000c +.set CYFLD_CSD_SW_HMMA__SIZE, 0x00000001 +.set CYFLD_CSD_SW_HMMB__OFFSET, 0x00000010 +.set CYFLD_CSD_SW_HMMB__SIZE, 0x00000001 +.set CYFLD_CSD_SW_HMCA__OFFSET, 0x00000014 +.set CYFLD_CSD_SW_HMCA__SIZE, 0x00000001 +.set CYFLD_CSD_SW_HMCB__OFFSET, 0x00000018 +.set CYFLD_CSD_SW_HMCB__SIZE, 0x00000001 +.set CYFLD_CSD_SW_HMRH__OFFSET, 0x0000001c +.set CYFLD_CSD_SW_HMRH__SIZE, 0x00000001 +.set CYREG_CSD_SW_HS_N_SEL, 0x40290284 +.set CYFLD_CSD_SW_HCCC__OFFSET, 0x00000010 +.set CYFLD_CSD_SW_HCCC__SIZE, 0x00000001 +.set CYFLD_CSD_SW_HCCD__OFFSET, 0x00000014 +.set CYFLD_CSD_SW_HCCD__SIZE, 0x00000001 +.set CYFLD_CSD_SW_HCRH__OFFSET, 0x00000018 +.set CYFLD_CSD_SW_HCRH__SIZE, 0x00000003 +.set CYFLD_CSD_SW_HCRL__OFFSET, 0x0000001c +.set CYFLD_CSD_SW_HCRL__SIZE, 0x00000003 +.set CYREG_CSD_SW_SHIELD_SEL, 0x40290288 +.set CYFLD_CSD_SW_HCAV__OFFSET, 0x00000000 +.set CYFLD_CSD_SW_HCAV__SIZE, 0x00000003 +.set CYFLD_CSD_SW_HCAG__OFFSET, 0x00000004 +.set CYFLD_CSD_SW_HCAG__SIZE, 0x00000003 +.set CYFLD_CSD_SW_HCBV__OFFSET, 0x00000008 +.set CYFLD_CSD_SW_HCBV__SIZE, 0x00000003 +.set CYFLD_CSD_SW_HCBG__OFFSET, 0x0000000c +.set CYFLD_CSD_SW_HCBG__SIZE, 0x00000003 +.set CYFLD_CSD_SW_HCCV__OFFSET, 0x00000010 +.set CYFLD_CSD_SW_HCCV__SIZE, 0x00000001 +.set CYFLD_CSD_SW_HCCG__OFFSET, 0x00000014 +.set CYFLD_CSD_SW_HCCG__SIZE, 0x00000001 +.set CYREG_CSD_SW_HS_P_SEL1, 0x4029028c +.set CYFLD_CSD_SW_HMRE__OFFSET, 0x00000000 +.set CYFLD_CSD_SW_HMRE__SIZE, 0x00000001 +.set CYREG_CSD_SW_AMUXBUF_SEL, 0x40290290 +.set CYFLD_CSD_SW_IRBY__OFFSET, 0x00000004 +.set CYFLD_CSD_SW_IRBY__SIZE, 0x00000001 +.set CYFLD_CSD_SW_IRLB__OFFSET, 0x00000008 +.set CYFLD_CSD_SW_IRLB__SIZE, 0x00000001 +.set CYFLD_CSD_SW_ICA__OFFSET, 0x0000000c +.set CYFLD_CSD_SW_ICA__SIZE, 0x00000001 +.set CYFLD_CSD_SW_ICB__OFFSET, 0x00000010 +.set CYFLD_CSD_SW_ICB__SIZE, 0x00000003 +.set CYFLD_CSD_SW_IRLI__OFFSET, 0x00000014 +.set CYFLD_CSD_SW_IRLI__SIZE, 0x00000001 +.set CYFLD_CSD_SW_IRH__OFFSET, 0x00000018 +.set CYFLD_CSD_SW_IRH__SIZE, 0x00000001 +.set CYFLD_CSD_SW_IRL__OFFSET, 0x0000001c +.set CYFLD_CSD_SW_IRL__SIZE, 0x00000001 +.set CYREG_CSD_SW_BYP_SEL, 0x40290294 +.set CYFLD_CSD_SW_BYA__OFFSET, 0x0000000c +.set CYFLD_CSD_SW_BYA__SIZE, 0x00000001 +.set CYFLD_CSD_SW_BYB__OFFSET, 0x00000010 +.set CYFLD_CSD_SW_BYB__SIZE, 0x00000001 +.set CYFLD_CSD_SW_CBCC__OFFSET, 0x00000014 +.set CYFLD_CSD_SW_CBCC__SIZE, 0x00000001 +.set CYREG_CSD_SW_CMP_P_SEL, 0x402902a0 +.set CYFLD_CSD_SW_SFPM__OFFSET, 0x00000000 +.set CYFLD_CSD_SW_SFPM__SIZE, 0x00000003 +.set CYFLD_CSD_SW_SFPT__OFFSET, 0x00000004 +.set CYFLD_CSD_SW_SFPT__SIZE, 0x00000003 +.set CYFLD_CSD_SW_SFPS__OFFSET, 0x00000008 +.set CYFLD_CSD_SW_SFPS__SIZE, 0x00000003 +.set CYFLD_CSD_SW_SFMA__OFFSET, 0x0000000c +.set CYFLD_CSD_SW_SFMA__SIZE, 0x00000001 +.set CYFLD_CSD_SW_SFMB__OFFSET, 0x00000010 +.set CYFLD_CSD_SW_SFMB__SIZE, 0x00000001 +.set CYFLD_CSD_SW_SFCA__OFFSET, 0x00000014 +.set CYFLD_CSD_SW_SFCA__SIZE, 0x00000001 +.set CYFLD_CSD_SW_SFCB__OFFSET, 0x00000018 +.set CYFLD_CSD_SW_SFCB__SIZE, 0x00000001 +.set CYREG_CSD_SW_CMP_N_SEL, 0x402902a4 +.set CYFLD_CSD_SW_SCRH__OFFSET, 0x00000018 +.set CYFLD_CSD_SW_SCRH__SIZE, 0x00000003 +.set CYFLD_CSD_SW_SCRL__OFFSET, 0x0000001c +.set CYFLD_CSD_SW_SCRL__SIZE, 0x00000003 +.set CYREG_CSD_SW_REFGEN_SEL, 0x402902a8 +.set CYFLD_CSD_SW_IAIB__OFFSET, 0x00000000 +.set CYFLD_CSD_SW_IAIB__SIZE, 0x00000001 +.set CYFLD_CSD_SW_IBCB__OFFSET, 0x00000004 +.set CYFLD_CSD_SW_IBCB__SIZE, 0x00000001 +.set CYFLD_CSD_SW_SGMB__OFFSET, 0x00000010 +.set CYFLD_CSD_SW_SGMB__SIZE, 0x00000001 +.set CYFLD_CSD_SW_SGRE__OFFSET, 0x00000018 +.set CYFLD_CSD_SW_SGRE__SIZE, 0x00000001 +.set CYFLD_CSD_SW_SGR__OFFSET, 0x0000001c +.set CYFLD_CSD_SW_SGR__SIZE, 0x00000001 +.set CYREG_CSD_SW_FW_MOD_SEL, 0x402902b0 +.set CYFLD_CSD_SW_F1PM__OFFSET, 0x00000000 +.set CYFLD_CSD_SW_F1PM__SIZE, 0x00000001 +.set CYFLD_CSD_SW_F1MA__OFFSET, 0x00000008 +.set CYFLD_CSD_SW_F1MA__SIZE, 0x00000003 +.set CYFLD_CSD_SW_F1CA__OFFSET, 0x00000010 +.set CYFLD_CSD_SW_F1CA__SIZE, 0x00000003 +.set CYFLD_CSD_SW_C1CC__OFFSET, 0x00000014 +.set CYFLD_CSD_SW_C1CC__SIZE, 0x00000001 +.set CYFLD_CSD_SW_C1CD__OFFSET, 0x00000018 +.set CYFLD_CSD_SW_C1CD__SIZE, 0x00000001 +.set CYFLD_CSD_SW_C1F1__OFFSET, 0x0000001c +.set CYFLD_CSD_SW_C1F1__SIZE, 0x00000001 +.set CYREG_CSD_SW_FW_TANK_SEL, 0x402902b4 +.set CYFLD_CSD_SW_F2PT__OFFSET, 0x00000004 +.set CYFLD_CSD_SW_F2PT__SIZE, 0x00000001 +.set CYFLD_CSD_SW_F2MA__OFFSET, 0x00000008 +.set CYFLD_CSD_SW_F2MA__SIZE, 0x00000003 +.set CYFLD_CSD_SW_F2CA__OFFSET, 0x0000000c +.set CYFLD_CSD_SW_F2CA__SIZE, 0x00000003 +.set CYFLD_CSD_SW_F2CB__OFFSET, 0x00000010 +.set CYFLD_CSD_SW_F2CB__SIZE, 0x00000003 +.set CYFLD_CSD_SW_C2CC__OFFSET, 0x00000014 +.set CYFLD_CSD_SW_C2CC__SIZE, 0x00000001 +.set CYFLD_CSD_SW_C2CD__OFFSET, 0x00000018 +.set CYFLD_CSD_SW_C2CD__SIZE, 0x00000001 +.set CYFLD_CSD_SW_C2F2__OFFSET, 0x0000001c +.set CYFLD_CSD_SW_C2F2__SIZE, 0x00000001 +.set CYREG_CSD_SW_DSI_SEL, 0x402902c0 +.set CYFLD_CSD_DSI_CSH_TANK__OFFSET, 0x00000000 +.set CYFLD_CSD_DSI_CSH_TANK__SIZE, 0x00000003 +.set CYFLD_CSD_DSI_CMOD__OFFSET, 0x00000004 +.set CYFLD_CSD_DSI_CMOD__SIZE, 0x00000003 +.set CYREG_CSD_SEQ_TIME, 0x40290300 +.set CYFLD_CSD_AZ_TIME__OFFSET, 0x00000000 +.set CYFLD_CSD_AZ_TIME__SIZE, 0x00000008 +.set CYREG_CSD_SEQ_INIT_CNT, 0x40290310 +.set CYFLD_CSD_CONV_CNT__OFFSET, 0x00000000 +.set CYFLD_CSD_CONV_CNT__SIZE, 0x00000010 +.set CYREG_CSD_SEQ_NORM_CNT, 0x40290314 +.set CYREG_CSD_ADC_CTL, 0x40290320 +.set CYFLD_CSD_ADC_TIME__OFFSET, 0x00000000 +.set CYFLD_CSD_ADC_TIME__SIZE, 0x00000008 +.set CYFLD_CSD_ADC_MODE__OFFSET, 0x00000010 +.set CYFLD_CSD_ADC_MODE__SIZE, 0x00000002 +.set CYVAL_CSD_ADC_MODE_OFF, 0x00000000 +.set CYVAL_CSD_ADC_MODE_VREF_CNT, 0x00000001 +.set CYVAL_CSD_ADC_MODE_VREF_BY2_CNT, 0x00000002 +.set CYVAL_CSD_ADC_MODE_VIN_CNT, 0x00000003 +.set CYREG_CSD_SEQ_START, 0x40290340 +.set CYFLD_CSD_START__OFFSET, 0x00000000 +.set CYFLD_CSD_START__SIZE, 0x00000001 +.set CYFLD_CSD_SEQ_MODE__OFFSET, 0x00000001 +.set CYFLD_CSD_SEQ_MODE__SIZE, 0x00000001 +.set CYFLD_CSD_ABORT__OFFSET, 0x00000003 +.set CYFLD_CSD_ABORT__SIZE, 0x00000001 +.set CYFLD_CSD_DSI_START_EN__OFFSET, 0x00000004 +.set CYFLD_CSD_DSI_START_EN__SIZE, 0x00000001 +.set CYFLD_CSD_AZ0_SKIP__OFFSET, 0x00000008 +.set CYFLD_CSD_AZ0_SKIP__SIZE, 0x00000001 +.set CYFLD_CSD_AZ1_SKIP__OFFSET, 0x00000009 +.set CYFLD_CSD_AZ1_SKIP__SIZE, 0x00000001 +.set CYDEV_LCD_BASE, 0x402a0000 +.set CYDEV_LCD_SIZE, 0x00010000 +.set CYREG_LCD_ID, 0x402a0000 +.set CYFLD_LCD_ID__OFFSET, 0x00000000 +.set CYFLD_LCD_ID__SIZE, 0x00000010 +.set CYFLD_LCD_REVISION__OFFSET, 0x00000010 +.set CYFLD_LCD_REVISION__SIZE, 0x00000010 +.set CYREG_LCD_DIVIDER, 0x402a0004 +.set CYFLD_LCD_SUBFR_DIV__OFFSET, 0x00000000 +.set CYFLD_LCD_SUBFR_DIV__SIZE, 0x00000010 +.set CYFLD_LCD_DEAD_DIV__OFFSET, 0x00000010 +.set CYFLD_LCD_DEAD_DIV__SIZE, 0x00000010 +.set CYREG_LCD_CONTROL, 0x402a0008 +.set CYFLD_LCD_LS_EN__OFFSET, 0x00000000 +.set CYFLD_LCD_LS_EN__SIZE, 0x00000001 +.set CYFLD_LCD_HS_EN__OFFSET, 0x00000001 +.set CYFLD_LCD_HS_EN__SIZE, 0x00000001 +.set CYFLD_LCD_LCD_MODE__OFFSET, 0x00000002 +.set CYFLD_LCD_LCD_MODE__SIZE, 0x00000001 +.set CYVAL_LCD_LCD_MODE_LS, 0x00000000 +.set CYVAL_LCD_LCD_MODE_HS, 0x00000001 +.set CYFLD_LCD_TYPE__OFFSET, 0x00000003 +.set CYFLD_LCD_TYPE__SIZE, 0x00000001 +.set CYVAL_LCD_TYPE_TYPE_A, 0x00000000 +.set CYVAL_LCD_TYPE_TYPE_B, 0x00000001 +.set CYFLD_LCD_OP_MODE__OFFSET, 0x00000004 +.set CYFLD_LCD_OP_MODE__SIZE, 0x00000001 +.set CYVAL_LCD_OP_MODE_PWM, 0x00000000 +.set CYVAL_LCD_OP_MODE_CORRELATION, 0x00000001 +.set CYFLD_LCD_BIAS__OFFSET, 0x00000005 +.set CYFLD_LCD_BIAS__SIZE, 0x00000002 +.set CYVAL_LCD_BIAS_HALF, 0x00000000 +.set CYVAL_LCD_BIAS_THIRD, 0x00000001 +.set CYVAL_LCD_BIAS_FOURTH, 0x00000002 +.set CYVAL_LCD_BIAS_FIFTH, 0x00000003 +.set CYFLD_LCD_COM_NUM__OFFSET, 0x00000008 +.set CYFLD_LCD_COM_NUM__SIZE, 0x00000004 +.set CYFLD_LCD_LS_EN_STAT__OFFSET, 0x0000001f +.set CYFLD_LCD_LS_EN_STAT__SIZE, 0x00000001 +.set CYREG_LCD_DATA00, 0x402a0100 +.set CYFLD_LCD_DATA__OFFSET, 0x00000000 +.set CYFLD_LCD_DATA__SIZE, 0x00000020 +.set CYREG_LCD_DATA01, 0x402a0104 +.set CYREG_LCD_DATA02, 0x402a0108 +.set CYREG_LCD_DATA03, 0x402a010c +.set CYREG_LCD_DATA04, 0x402a0110 +.set CYREG_LCD_DATA05, 0x402a0114 +.set CYREG_LCD_DATA06, 0x402a0118 +.set CYREG_LCD_DATA07, 0x402a011c +.set CYREG_LCD_DATA10, 0x402a0200 +.set CYREG_LCD_DATA11, 0x402a0204 +.set CYREG_LCD_DATA12, 0x402a0208 +.set CYREG_LCD_DATA13, 0x402a020c +.set CYREG_LCD_DATA14, 0x402a0210 +.set CYREG_LCD_DATA15, 0x402a0214 +.set CYREG_LCD_DATA16, 0x402a0218 +.set CYREG_LCD_DATA17, 0x402a021c +.set CYDEV_LPCOMP_BASE, 0x402b0000 +.set CYDEV_LPCOMP_SIZE, 0x00010000 +.set CYREG_LPCOMP_ID, 0x402b0000 +.set CYFLD_LPCOMP_ID__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_ID__SIZE, 0x00000010 +.set CYFLD_LPCOMP_REVISION__OFFSET, 0x00000010 +.set CYFLD_LPCOMP_REVISION__SIZE, 0x00000010 +.set CYREG_LPCOMP_CONFIG, 0x402b0004 +.set CYFLD_LPCOMP_MODE1__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_MODE1__SIZE, 0x00000002 +.set CYVAL_LPCOMP_MODE1_SLOW, 0x00000000 +.set CYVAL_LPCOMP_MODE1_FAST, 0x00000001 +.set CYVAL_LPCOMP_MODE1_ULP, 0x00000002 +.set CYFLD_LPCOMP_HYST1__OFFSET, 0x00000002 +.set CYFLD_LPCOMP_HYST1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_FILTER1__OFFSET, 0x00000003 +.set CYFLD_LPCOMP_FILTER1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_INTTYPE1__OFFSET, 0x00000004 +.set CYFLD_LPCOMP_INTTYPE1__SIZE, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE1_DISABLE, 0x00000000 +.set CYVAL_LPCOMP_INTTYPE1_RISING, 0x00000001 +.set CYVAL_LPCOMP_INTTYPE1_FALLING, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE1_BOTH, 0x00000003 +.set CYFLD_LPCOMP_OUT1__OFFSET, 0x00000006 +.set CYFLD_LPCOMP_OUT1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_ENABLE1__OFFSET, 0x00000007 +.set CYFLD_LPCOMP_ENABLE1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_MODE2__OFFSET, 0x00000008 +.set CYFLD_LPCOMP_MODE2__SIZE, 0x00000002 +.set CYVAL_LPCOMP_MODE2_SLOW, 0x00000000 +.set CYVAL_LPCOMP_MODE2_FAST, 0x00000001 +.set CYVAL_LPCOMP_MODE2_ULP, 0x00000002 +.set CYFLD_LPCOMP_HYST2__OFFSET, 0x0000000a +.set CYFLD_LPCOMP_HYST2__SIZE, 0x00000001 +.set CYFLD_LPCOMP_FILTER2__OFFSET, 0x0000000b +.set CYFLD_LPCOMP_FILTER2__SIZE, 0x00000001 +.set CYFLD_LPCOMP_INTTYPE2__OFFSET, 0x0000000c +.set CYFLD_LPCOMP_INTTYPE2__SIZE, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE2_DISABLE, 0x00000000 +.set CYVAL_LPCOMP_INTTYPE2_RISING, 0x00000001 +.set CYVAL_LPCOMP_INTTYPE2_FALLING, 0x00000002 +.set CYVAL_LPCOMP_INTTYPE2_BOTH, 0x00000003 +.set CYFLD_LPCOMP_OUT2__OFFSET, 0x0000000e +.set CYFLD_LPCOMP_OUT2__SIZE, 0x00000001 +.set CYFLD_LPCOMP_ENABLE2__OFFSET, 0x0000000f +.set CYFLD_LPCOMP_ENABLE2__SIZE, 0x00000001 +.set CYFLD_LPCOMP_DSI_BYPASS1__OFFSET, 0x00000010 +.set CYFLD_LPCOMP_DSI_BYPASS1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_DSI_LEVEL1__OFFSET, 0x00000011 +.set CYFLD_LPCOMP_DSI_LEVEL1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_DSI_BYPASS2__OFFSET, 0x00000014 +.set CYFLD_LPCOMP_DSI_BYPASS2__SIZE, 0x00000001 +.set CYFLD_LPCOMP_DSI_LEVEL2__OFFSET, 0x00000015 +.set CYFLD_LPCOMP_DSI_LEVEL2__SIZE, 0x00000001 +.set CYREG_LPCOMP_DFT, 0x402b0008 +.set CYFLD_LPCOMP_CAL_EN__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_CAL_EN__SIZE, 0x00000001 +.set CYFLD_LPCOMP_BYPASS__OFFSET, 0x00000001 +.set CYFLD_LPCOMP_BYPASS__SIZE, 0x00000001 +.set CYREG_LPCOMP_INTR, 0x402b0010 +.set CYFLD_LPCOMP_COMP1__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP1__SIZE, 0x00000001 +.set CYFLD_LPCOMP_COMP2__OFFSET, 0x00000001 +.set CYFLD_LPCOMP_COMP2__SIZE, 0x00000001 +.set CYREG_LPCOMP_INTR_SET, 0x402b0014 +.set CYREG_LPCOMP_INTR_MASK, 0x402b0018 +.set CYFLD_LPCOMP_COMP1_MASK__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP1_MASK__SIZE, 0x00000001 +.set CYFLD_LPCOMP_COMP2_MASK__OFFSET, 0x00000001 +.set CYFLD_LPCOMP_COMP2_MASK__SIZE, 0x00000001 +.set CYREG_LPCOMP_INTR_MASKED, 0x402b001c +.set CYFLD_LPCOMP_COMP1_MASKED__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP1_MASKED__SIZE, 0x00000001 +.set CYFLD_LPCOMP_COMP2_MASKED__OFFSET, 0x00000001 +.set CYFLD_LPCOMP_COMP2_MASKED__SIZE, 0x00000001 +.set CYREG_LPCOMP_TRIM1, 0x402bff00 +.set CYFLD_LPCOMP_COMP1_TRIMA__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP1_TRIMA__SIZE, 0x00000005 +.set CYREG_LPCOMP_TRIM2, 0x402bff04 +.set CYFLD_LPCOMP_COMP1_TRIMB__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP1_TRIMB__SIZE, 0x00000005 +.set CYREG_LPCOMP_TRIM3, 0x402bff08 +.set CYFLD_LPCOMP_COMP2_TRIMA__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP2_TRIMA__SIZE, 0x00000005 +.set CYREG_LPCOMP_TRIM4, 0x402bff0c +.set CYFLD_LPCOMP_COMP2_TRIMB__OFFSET, 0x00000000 +.set CYFLD_LPCOMP_COMP2_TRIMB__SIZE, 0x00000005 +.set CYDEV_CRYPTO_BASE, 0x402c0000 +.set CYDEV_CRYPTO_SIZE, 0x00010000 +.set CYREG_CRYPTO_CTL, 0x402c0000 +.set CYFLD_CRYPTO_OPCODE__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_OPCODE__SIZE, 0x00000005 +.set CYVAL_CRYPTO_OPCODE_AES_FORWARD, 0x00000000 +.set CYVAL_CRYPTO_OPCODE_AES_INVERSE, 0x00000001 +.set CYVAL_CRYPTO_OPCODE_SHA, 0x00000010 +.set CYVAL_CRYPTO_OPCODE_CRC, 0x00000018 +.set CYFLD_CRYPTO_ENABLED__OFFSET, 0x0000001f +.set CYFLD_CRYPTO_ENABLED__SIZE, 0x00000001 +.set CYREG_CRYPTO_STATUS, 0x402c0004 +.set CYFLD_CRYPTO_BUSY__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_BUSY__SIZE, 0x00000001 +.set CYREG_CRYPTO_CMD, 0x402c0008 +.set CYFLD_CRYPTO_START__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_START__SIZE, 0x00000001 +.set CYREG_CRYPTO_TR_CTL0, 0x402c0280 +.set CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__SIZE, 0x00000008 +.set CYFLD_CRYPTO_RED_CLOCK_DIV__OFFSET, 0x00000008 +.set CYFLD_CRYPTO_RED_CLOCK_DIV__SIZE, 0x00000008 +.set CYFLD_CRYPTO_INIT_DELAY__OFFSET, 0x00000010 +.set CYFLD_CRYPTO_INIT_DELAY__SIZE, 0x00000008 +.set CYFLD_CRYPTO_VON_NEUMANN_CORR__OFFSET, 0x00000018 +.set CYFLD_CRYPTO_VON_NEUMANN_CORR__SIZE, 0x00000001 +.set CYFLD_CRYPTO_STOP_ON_AP_DETECT__OFFSET, 0x0000001c +.set CYFLD_CRYPTO_STOP_ON_AP_DETECT__SIZE, 0x00000001 +.set CYFLD_CRYPTO_STOP_ON_RC_DETECT__OFFSET, 0x0000001d +.set CYFLD_CRYPTO_STOP_ON_RC_DETECT__SIZE, 0x00000001 +.set CYREG_CRYPTO_TR_CTL1, 0x402c0284 +.set CYFLD_CRYPTO_DATA_BIT_SIZE__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_DATA_BIT_SIZE__SIZE, 0x00000006 +.set CYREG_CRYPTO_TR_RESULT0, 0x402c0288 +.set CYFLD_CRYPTO_DATA32__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_DATA32__SIZE, 0x00000020 +.set CYREG_CRYPTO_TR_RESULT1, 0x402c028c +.set CYREG_CRYPTO_TR_CMD, 0x402c0290 +.set CYFLD_CRYPTO_START_RO11__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_START_RO11__SIZE, 0x00000001 +.set CYFLD_CRYPTO_START_RO15__OFFSET, 0x00000001 +.set CYFLD_CRYPTO_START_RO15__SIZE, 0x00000001 +.set CYFLD_CRYPTO_START_GARO15__OFFSET, 0x00000002 +.set CYFLD_CRYPTO_START_GARO15__SIZE, 0x00000001 +.set CYFLD_CRYPTO_START_GARO31__OFFSET, 0x00000003 +.set CYFLD_CRYPTO_START_GARO31__SIZE, 0x00000001 +.set CYFLD_CRYPTO_START_FIRO15__OFFSET, 0x00000004 +.set CYFLD_CRYPTO_START_FIRO15__SIZE, 0x00000001 +.set CYFLD_CRYPTO_START_FIRO31__OFFSET, 0x00000005 +.set CYFLD_CRYPTO_START_FIRO31__SIZE, 0x00000001 +.set CYREG_CRYPTO_TR_GARO_CTL, 0x402c02a0 +.set CYFLD_CRYPTO_POLYNOMIAL31__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_POLYNOMIAL31__SIZE, 0x0000001f +.set CYREG_CRYPTO_TR_FIRO_CTL, 0x402c02a4 +.set CYREG_CRYPTO_TR_MON_CTL, 0x402c02c0 +.set CYFLD_CRYPTO_BITSTREAM_SEL__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_BITSTREAM_SEL__SIZE, 0x00000002 +.set CYREG_CRYPTO_TR_MON_CMD, 0x402c02c8 +.set CYFLD_CRYPTO_START_AP__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_START_AP__SIZE, 0x00000001 +.set CYFLD_CRYPTO_START_RC__OFFSET, 0x00000001 +.set CYFLD_CRYPTO_START_RC__SIZE, 0x00000001 +.set CYREG_CRYPTO_TR_MON_RC_CTL, 0x402c02d0 +.set CYFLD_CRYPTO_CUTOFF_COUNT8__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_CUTOFF_COUNT8__SIZE, 0x00000008 +.set CYREG_CRYPTO_TR_MON_RC_STATUS0, 0x402c02d8 +.set CYFLD_CRYPTO_BIT__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_BIT__SIZE, 0x00000001 +.set CYREG_CRYPTO_TR_MON_RC_STATUS1, 0x402c02dc +.set CYFLD_CRYPTO_REP_COUNT__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_REP_COUNT__SIZE, 0x00000008 +.set CYREG_CRYPTO_TR_MON_AP_CTL, 0x402c02e0 +.set CYFLD_CRYPTO_CUTOFF_COUNT16__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_CUTOFF_COUNT16__SIZE, 0x00000010 +.set CYFLD_CRYPTO_WINDOW_SIZE__OFFSET, 0x00000010 +.set CYFLD_CRYPTO_WINDOW_SIZE__SIZE, 0x00000010 +.set CYREG_CRYPTO_TR_MON_AP_STATUS0, 0x402c02e8 +.set CYREG_CRYPTO_TR_MON_AP_STATUS1, 0x402c02ec +.set CYFLD_CRYPTO_OCC_COUNT__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_OCC_COUNT__SIZE, 0x00000010 +.set CYFLD_CRYPTO_WINDOW_INDEX__OFFSET, 0x00000010 +.set CYFLD_CRYPTO_WINDOW_INDEX__SIZE, 0x00000010 +.set CYREG_CRYPTO_INTR, 0x402c07c0 +.set CYFLD_CRYPTO_DONE__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_DONE__SIZE, 0x00000001 +.set CYFLD_CRYPTO_ACCESS_ERROR__OFFSET, 0x00000001 +.set CYFLD_CRYPTO_ACCESS_ERROR__SIZE, 0x00000001 +.set CYFLD_CRYPTO_TR_INITIALIZED__OFFSET, 0x00000006 +.set CYFLD_CRYPTO_TR_INITIALIZED__SIZE, 0x00000001 +.set CYFLD_CRYPTO_TR_DATA_AVAILABLE__OFFSET, 0x00000007 +.set CYFLD_CRYPTO_TR_DATA_AVAILABLE__SIZE, 0x00000001 +.set CYFLD_CRYPTO_TR_AP_DETECT__OFFSET, 0x00000008 +.set CYFLD_CRYPTO_TR_AP_DETECT__SIZE, 0x00000001 +.set CYFLD_CRYPTO_TR_RC_DETECT__OFFSET, 0x00000009 +.set CYFLD_CRYPTO_TR_RC_DETECT__SIZE, 0x00000001 +.set CYREG_CRYPTO_INTR_SET, 0x402c07c4 +.set CYREG_CRYPTO_INTR_MASK, 0x402c07c8 +.set CYREG_CRYPTO_INTR_MASKED, 0x402c07cc +.set CYREG_CRYPTO_MEM_BUFF0, 0x402c0800 +.set CYREG_CRYPTO_MEM_BUFF1, 0x402c0804 +.set CYREG_CRYPTO_MEM_BUFF2, 0x402c0808 +.set CYREG_CRYPTO_MEM_BUFF3, 0x402c080c +.set CYREG_CRYPTO_MEM_BUFF4, 0x402c0810 +.set CYREG_CRYPTO_MEM_BUFF5, 0x402c0814 +.set CYREG_CRYPTO_MEM_BUFF6, 0x402c0818 +.set CYREG_CRYPTO_MEM_BUFF7, 0x402c081c +.set CYREG_CRYPTO_MEM_BUFF8, 0x402c0820 +.set CYREG_CRYPTO_MEM_BUFF9, 0x402c0824 +.set CYREG_CRYPTO_MEM_BUFF10, 0x402c0828 +.set CYREG_CRYPTO_MEM_BUFF11, 0x402c082c +.set CYREG_CRYPTO_MEM_BUFF12, 0x402c0830 +.set CYREG_CRYPTO_MEM_BUFF13, 0x402c0834 +.set CYREG_CRYPTO_MEM_BUFF14, 0x402c0838 +.set CYREG_CRYPTO_MEM_BUFF15, 0x402c083c +.set CYREG_CRYPTO_MEM_BUFF16, 0x402c0840 +.set CYREG_CRYPTO_MEM_BUFF17, 0x402c0844 +.set CYREG_CRYPTO_MEM_BUFF18, 0x402c0848 +.set CYREG_CRYPTO_MEM_BUFF19, 0x402c084c +.set CYREG_CRYPTO_MEM_BUFF20, 0x402c0850 +.set CYREG_CRYPTO_MEM_BUFF21, 0x402c0854 +.set CYREG_CRYPTO_MEM_BUFF22, 0x402c0858 +.set CYREG_CRYPTO_MEM_BUFF23, 0x402c085c +.set CYREG_CRYPTO_MEM_BUFF24, 0x402c0860 +.set CYREG_CRYPTO_MEM_BUFF25, 0x402c0864 +.set CYREG_CRYPTO_MEM_BUFF26, 0x402c0868 +.set CYREG_CRYPTO_MEM_BUFF27, 0x402c086c +.set CYREG_CRYPTO_MEM_BUFF28, 0x402c0870 +.set CYREG_CRYPTO_MEM_BUFF29, 0x402c0874 +.set CYREG_CRYPTO_MEM_BUFF30, 0x402c0878 +.set CYREG_CRYPTO_MEM_BUFF31, 0x402c087c +.set CYREG_CRYPTO_MEM_BUFF32, 0x402c0880 +.set CYREG_CRYPTO_MEM_BUFF33, 0x402c0884 +.set CYREG_CRYPTO_MEM_BUFF34, 0x402c0888 +.set CYREG_CRYPTO_MEM_BUFF35, 0x402c088c +.set CYREG_CRYPTO_MEM_BUFF36, 0x402c0890 +.set CYREG_CRYPTO_MEM_BUFF37, 0x402c0894 +.set CYREG_CRYPTO_MEM_BUFF38, 0x402c0898 +.set CYREG_CRYPTO_MEM_BUFF39, 0x402c089c +.set CYREG_CRYPTO_MEM_BUFF40, 0x402c08a0 +.set CYREG_CRYPTO_MEM_BUFF41, 0x402c08a4 +.set CYREG_CRYPTO_MEM_BUFF42, 0x402c08a8 +.set CYREG_CRYPTO_MEM_BUFF43, 0x402c08ac +.set CYREG_CRYPTO_MEM_BUFF44, 0x402c08b0 +.set CYREG_CRYPTO_MEM_BUFF45, 0x402c08b4 +.set CYREG_CRYPTO_MEM_BUFF46, 0x402c08b8 +.set CYREG_CRYPTO_MEM_BUFF47, 0x402c08bc +.set CYREG_CRYPTO_MEM_BUFF48, 0x402c08c0 +.set CYREG_CRYPTO_MEM_BUFF49, 0x402c08c4 +.set CYREG_CRYPTO_MEM_BUFF50, 0x402c08c8 +.set CYREG_CRYPTO_MEM_BUFF51, 0x402c08cc +.set CYREG_CRYPTO_MEM_BUFF52, 0x402c08d0 +.set CYREG_CRYPTO_MEM_BUFF53, 0x402c08d4 +.set CYREG_CRYPTO_MEM_BUFF54, 0x402c08d8 +.set CYREG_CRYPTO_MEM_BUFF55, 0x402c08dc +.set CYREG_CRYPTO_MEM_BUFF56, 0x402c08e0 +.set CYREG_CRYPTO_MEM_BUFF57, 0x402c08e4 +.set CYREG_CRYPTO_MEM_BUFF58, 0x402c08e8 +.set CYREG_CRYPTO_MEM_BUFF59, 0x402c08ec +.set CYREG_CRYPTO_MEM_BUFF60, 0x402c08f0 +.set CYREG_CRYPTO_MEM_BUFF61, 0x402c08f4 +.set CYREG_CRYPTO_MEM_BUFF62, 0x402c08f8 +.set CYREG_CRYPTO_MEM_BUFF63, 0x402c08fc +.set CYREG_CRYPTO_PRIV_BUF, 0x402cff00 +.set CYFLD_CRYPTO_BUF_PRIV_LIMIT__OFFSET, 0x00000000 +.set CYFLD_CRYPTO_BUF_PRIV_LIMIT__SIZE, 0x00000003 +.set CYDEV_CAN_BASE, 0x402e0000 +.set CYDEV_CAN_SIZE, 0x00010000 +.set CYREG_CAN_INT_STATUS, 0x402e0000 +.set CYFLD_CAN_ARB_LOSS__OFFSET, 0x00000002 +.set CYFLD_CAN_ARB_LOSS__SIZE, 0x00000001 +.set CYFLD_CAN_OVR_LOAD__OFFSET, 0x00000003 +.set CYFLD_CAN_OVR_LOAD__SIZE, 0x00000001 +.set CYFLD_CAN_BIT_ERR__OFFSET, 0x00000004 +.set CYFLD_CAN_BIT_ERR__SIZE, 0x00000001 +.set CYFLD_CAN_STUFF_ERR__OFFSET, 0x00000005 +.set CYFLD_CAN_STUFF_ERR__SIZE, 0x00000001 +.set CYFLD_CAN_ACK_ERR__OFFSET, 0x00000006 +.set CYFLD_CAN_ACK_ERR__SIZE, 0x00000001 +.set CYFLD_CAN_FORM_ERR__OFFSET, 0x00000007 +.set CYFLD_CAN_FORM_ERR__SIZE, 0x00000001 +.set CYFLD_CAN_CRC_ERR__OFFSET, 0x00000008 +.set CYFLD_CAN_CRC_ERR__SIZE, 0x00000001 +.set CYFLD_CAN_BUS_OFF__OFFSET, 0x00000009 +.set CYFLD_CAN_BUS_OFF__SIZE, 0x00000001 +.set CYFLD_CAN_RX_MSG_LOSS__OFFSET, 0x0000000a +.set CYFLD_CAN_RX_MSG_LOSS__SIZE, 0x00000001 +.set CYFLD_CAN_TX_MSG__OFFSET, 0x0000000b +.set CYFLD_CAN_TX_MSG__SIZE, 0x00000001 +.set CYFLD_CAN_RX_MSG__OFFSET, 0x0000000c +.set CYFLD_CAN_RX_MSG__SIZE, 0x00000001 +.set CYFLD_CAN_RTR_MSG__OFFSET, 0x0000000d +.set CYFLD_CAN_RTR_MSG__SIZE, 0x00000001 +.set CYFLD_CAN_STUCK_AT_0__OFFSET, 0x0000000e +.set CYFLD_CAN_STUCK_AT_0__SIZE, 0x00000001 +.set CYFLD_CAN_SST_FAILURE__OFFSET, 0x0000000f +.set CYFLD_CAN_SST_FAILURE__SIZE, 0x00000001 +.set CYREG_CAN_INT_EBL, 0x402e0004 +.set CYFLD_CAN_GLOBAL_INT_ENBL__OFFSET, 0x00000000 +.set CYFLD_CAN_GLOBAL_INT_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_ARB_LOSS_ENBL__OFFSET, 0x00000002 +.set CYFLD_CAN_ARB_LOSS_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_OVR_LOAD_ENBL__OFFSET, 0x00000003 +.set CYFLD_CAN_OVR_LOAD_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_BIT_ERR_ENBL__OFFSET, 0x00000004 +.set CYFLD_CAN_BIT_ERR_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_STUFF_ERR_ENBL__OFFSET, 0x00000005 +.set CYFLD_CAN_STUFF_ERR_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_ACK_ERR_ENBL__OFFSET, 0x00000006 +.set CYFLD_CAN_ACK_ERR_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_FORM_ERR_ENBL__OFFSET, 0x00000007 +.set CYFLD_CAN_FORM_ERR_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_CRC_ERR_ENBL__OFFSET, 0x00000008 +.set CYFLD_CAN_CRC_ERR_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_BUS_OFF_ENBL__OFFSET, 0x00000009 +.set CYFLD_CAN_BUS_OFF_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_TX_MSG_ENBL__OFFSET, 0x0000000b +.set CYFLD_CAN_TX_MSG_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_RX_MSG_ENBl__OFFSET, 0x0000000c +.set CYFLD_CAN_RX_MSG_ENBl__SIZE, 0x00000001 +.set CYFLD_CAN_RTR_MSG_ENBL__OFFSET, 0x0000000d +.set CYFLD_CAN_RTR_MSG_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_STUCK_AT_0_ENBL__OFFSET, 0x0000000e +.set CYFLD_CAN_STUCK_AT_0_ENBL__SIZE, 0x00000001 +.set CYFLD_CAN_SST_FAILURE_ENBL__OFFSET, 0x0000000f +.set CYFLD_CAN_SST_FAILURE_ENBL__SIZE, 0x00000001 +.set CYREG_CAN_BUFFER_STATUS, 0x402e0008 +.set CYFLD_CAN_RX0_MSG_AV__OFFSET, 0x00000000 +.set CYFLD_CAN_RX0_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX1_MSG_AV__OFFSET, 0x00000001 +.set CYFLD_CAN_RX1_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX2_MSG_AV__OFFSET, 0x00000002 +.set CYFLD_CAN_RX2_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX3_MSG_AV__OFFSET, 0x00000003 +.set CYFLD_CAN_RX3_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX4_MSG_AV__OFFSET, 0x00000004 +.set CYFLD_CAN_RX4_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX5_MSG_AV__OFFSET, 0x00000005 +.set CYFLD_CAN_RX5_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX6_MSG_AV__OFFSET, 0x00000006 +.set CYFLD_CAN_RX6_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX7_MSG_AV__OFFSET, 0x00000007 +.set CYFLD_CAN_RX7_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX8_MSG_AV__OFFSET, 0x00000008 +.set CYFLD_CAN_RX8_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX9_MSG_AV__OFFSET, 0x00000009 +.set CYFLD_CAN_RX9_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX10_MSG_AV__OFFSET, 0x0000000a +.set CYFLD_CAN_RX10_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX11_MSG_AV__OFFSET, 0x0000000b +.set CYFLD_CAN_RX11_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX12_MSG_AV__OFFSET, 0x0000000c +.set CYFLD_CAN_RX12_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX13_MSG_AV__OFFSET, 0x0000000d +.set CYFLD_CAN_RX13_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX14_MSG_AV__OFFSET, 0x0000000e +.set CYFLD_CAN_RX14_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_RX15_MSG_AV__OFFSET, 0x0000000f +.set CYFLD_CAN_RX15_MSG_AV__SIZE, 0x00000001 +.set CYFLD_CAN_TX0_REQ_PEND__OFFSET, 0x00000010 +.set CYFLD_CAN_TX0_REQ_PEND__SIZE, 0x00000001 +.set CYFLD_CAN_TX1_REQ_PEND__OFFSET, 0x00000011 +.set CYFLD_CAN_TX1_REQ_PEND__SIZE, 0x00000001 +.set CYFLD_CAN_TX2_REQ_PEND__OFFSET, 0x00000012 +.set CYFLD_CAN_TX2_REQ_PEND__SIZE, 0x00000001 +.set CYFLD_CAN_TX3_REQ_PEND__OFFSET, 0x00000013 +.set CYFLD_CAN_TX3_REQ_PEND__SIZE, 0x00000001 +.set CYFLD_CAN_TX4_REQ_PEND__OFFSET, 0x00000014 +.set CYFLD_CAN_TX4_REQ_PEND__SIZE, 0x00000001 +.set CYFLD_CAN_TX5_REQ_PEND__OFFSET, 0x00000015 +.set CYFLD_CAN_TX5_REQ_PEND__SIZE, 0x00000001 +.set CYFLD_CAN_TX6_REQ_PEND__OFFSET, 0x00000016 +.set CYFLD_CAN_TX6_REQ_PEND__SIZE, 0x00000001 +.set CYFLD_CAN_TX7_REQ_PEND__OFFSET, 0x00000017 +.set CYFLD_CAN_TX7_REQ_PEND__SIZE, 0x00000001 +.set CYREG_CAN_ERROR_STATUS, 0x402e000c +.set CYFLD_CAN_TX_ERR_CNT__OFFSET, 0x00000000 +.set CYFLD_CAN_TX_ERR_CNT__SIZE, 0x00000008 +.set CYFLD_CAN_RX_ERR_CNT__OFFSET, 0x00000008 +.set CYFLD_CAN_RX_ERR_CNT__SIZE, 0x00000008 +.set CYFLD_CAN_ERROR_STATE__OFFSET, 0x00000010 +.set CYFLD_CAN_ERROR_STATE__SIZE, 0x00000002 +.set CYFLD_CAN_TXGTE96__OFFSET, 0x00000012 +.set CYFLD_CAN_TXGTE96__SIZE, 0x00000001 +.set CYFLD_CAN_RXGTE96__OFFSET, 0x00000013 +.set CYFLD_CAN_RXGTE96__SIZE, 0x00000001 +.set CYREG_CAN_COMMAND, 0x402e0010 +.set CYFLD_CAN_RUN__OFFSET, 0x00000000 +.set CYFLD_CAN_RUN__SIZE, 0x00000001 +.set CYFLD_CAN_LISTEN__OFFSET, 0x00000001 +.set CYFLD_CAN_LISTEN__SIZE, 0x00000001 +.set CYFLD_CAN_LOOPBACK_TEST__OFFSET, 0x00000002 +.set CYFLD_CAN_LOOPBACK_TEST__SIZE, 0x00000001 +.set CYFLD_CAN_SRAM_TEST__OFFSET, 0x00000003 +.set CYFLD_CAN_SRAM_TEST__SIZE, 0x00000001 +.set CYFLD_CAN_IP_REV_NUMBER__OFFSET, 0x00000010 +.set CYFLD_CAN_IP_REV_NUMBER__SIZE, 0x00000008 +.set CYFLD_CAN_IP_MINOR_VERSION__OFFSET, 0x00000018 +.set CYFLD_CAN_IP_MINOR_VERSION__SIZE, 0x00000004 +.set CYFLD_CAN_IP_MAJOR_VERSION__OFFSET, 0x0000001c +.set CYFLD_CAN_IP_MAJOR_VERSION__SIZE, 0x00000004 +.set CYREG_CAN_CONFIG, 0x402e0014 +.set CYFLD_CAN_EDGE_MODE__OFFSET, 0x00000000 +.set CYFLD_CAN_EDGE_MODE__SIZE, 0x00000001 +.set CYFLD_CAN_SAMPLING_MODE__OFFSET, 0x00000001 +.set CYFLD_CAN_SAMPLING_MODE__SIZE, 0x00000001 +.set CYFLD_CAN_CFG_SJW__OFFSET, 0x00000002 +.set CYFLD_CAN_CFG_SJW__SIZE, 0x00000002 +.set CYFLD_CAN_AUTO_RESTART__OFFSET, 0x00000004 +.set CYFLD_CAN_AUTO_RESTART__SIZE, 0x00000001 +.set CYFLD_CAN_CFG_TSEG2__OFFSET, 0x00000005 +.set CYFLD_CAN_CFG_TSEG2__SIZE, 0x00000003 +.set CYFLD_CAN_CFG_TSEG1__OFFSET, 0x00000008 +.set CYFLD_CAN_CFG_TSEG1__SIZE, 0x00000004 +.set CYFLD_CAN_CFG_ARBITER__OFFSET, 0x0000000c +.set CYFLD_CAN_CFG_ARBITER__SIZE, 0x00000001 +.set CYFLD_CAN_SWAP_ENDIAN__OFFSET, 0x0000000d +.set CYFLD_CAN_SWAP_ENDIAN__SIZE, 0x00000001 +.set CYFLD_CAN_ECR_MODE__OFFSET, 0x0000000e +.set CYFLD_CAN_ECR_MODE__SIZE, 0x00000001 +.set CYFLD_CAN_CFG_BITRATE__OFFSET, 0x00000010 +.set CYFLD_CAN_CFG_BITRATE__SIZE, 0x0000000f +.set CYREG_CAN_ECR, 0x402e0018 +.set CYFLD_CAN_ECR_STATUS__OFFSET, 0x00000000 +.set CYFLD_CAN_ECR_STATUS__SIZE, 0x00000001 +.set CYFLD_CAN_ERROR_TYPE__OFFSET, 0x00000001 +.set CYFLD_CAN_ERROR_TYPE__SIZE, 0x00000003 +.set CYFLD_CAN_RX_MODE__OFFSET, 0x00000004 +.set CYFLD_CAN_RX_MODE__SIZE, 0x00000001 +.set CYFLD_CAN_TX_MODE__OFFSET, 0x00000005 +.set CYFLD_CAN_TX_MODE__SIZE, 0x00000001 +.set CYFLD_CAN_BIT__OFFSET, 0x00000006 +.set CYFLD_CAN_BIT__SIZE, 0x00000006 +.set CYFLD_CAN_Field__OFFSET, 0x0000000c +.set CYFLD_CAN_Field__SIZE, 0x00000005 +.set CYDEV_CAN_CAN_TX0_BASE, 0x402e0020 +.set CYDEV_CAN_CAN_TX0_SIZE, 0x00000010 +.set CYREG_CAN_CAN_TX0_CONTROL, 0x402e0020 +.set CYFLD_CAN_CAN_TX_TX_REQ__OFFSET, 0x00000000 +.set CYFLD_CAN_CAN_TX_TX_REQ__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_TX_TX_ABORT__OFFSET, 0x00000001 +.set CYFLD_CAN_CAN_TX_TX_ABORT__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_TX_TX_INT_EBL__OFFSET, 0x00000002 +.set CYFLD_CAN_CAN_TX_TX_INT_EBL__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_TX_WPNL__OFFSET, 0x00000003 +.set CYFLD_CAN_CAN_TX_WPNL__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_TX_DLC__OFFSET, 0x00000010 +.set CYFLD_CAN_CAN_TX_DLC__SIZE, 0x00000004 +.set CYFLD_CAN_CAN_TX_IDE__OFFSET, 0x00000014 +.set CYFLD_CAN_CAN_TX_IDE__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_TX_RTR__OFFSET, 0x00000015 +.set CYFLD_CAN_CAN_TX_RTR__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_TX_WPNH__OFFSET, 0x00000017 +.set CYFLD_CAN_CAN_TX_WPNH__SIZE, 0x00000001 +.set CYREG_CAN_CAN_TX0_ID, 0x402e0024 +.set CYFLD_CAN_CAN_TX_ID__OFFSET, 0x00000003 +.set CYFLD_CAN_CAN_TX_ID__SIZE, 0x0000001d +.set CYREG_CAN_CAN_TX0_DATA_HIGH, 0x402e0028 +.set CYFLD_CAN_CAN_TX_DATA__OFFSET, 0x00000000 +.set CYFLD_CAN_CAN_TX_DATA__SIZE, 0x00000020 +.set CYREG_CAN_CAN_TX0_DATA_LOW, 0x402e002c +.set CYDEV_CAN_CAN_TX1_BASE, 0x402e0030 +.set CYDEV_CAN_CAN_TX1_SIZE, 0x00000010 +.set CYREG_CAN_CAN_TX1_CONTROL, 0x402e0030 +.set CYREG_CAN_CAN_TX1_ID, 0x402e0034 +.set CYREG_CAN_CAN_TX1_DATA_HIGH, 0x402e0038 +.set CYREG_CAN_CAN_TX1_DATA_LOW, 0x402e003c +.set CYDEV_CAN_CAN_TX2_BASE, 0x402e0040 +.set CYDEV_CAN_CAN_TX2_SIZE, 0x00000010 +.set CYREG_CAN_CAN_TX2_CONTROL, 0x402e0040 +.set CYREG_CAN_CAN_TX2_ID, 0x402e0044 +.set CYREG_CAN_CAN_TX2_DATA_HIGH, 0x402e0048 +.set CYREG_CAN_CAN_TX2_DATA_LOW, 0x402e004c +.set CYDEV_CAN_CAN_TX3_BASE, 0x402e0050 +.set CYDEV_CAN_CAN_TX3_SIZE, 0x00000010 +.set CYREG_CAN_CAN_TX3_CONTROL, 0x402e0050 +.set CYREG_CAN_CAN_TX3_ID, 0x402e0054 +.set CYREG_CAN_CAN_TX3_DATA_HIGH, 0x402e0058 +.set CYREG_CAN_CAN_TX3_DATA_LOW, 0x402e005c +.set CYDEV_CAN_CAN_TX4_BASE, 0x402e0060 +.set CYDEV_CAN_CAN_TX4_SIZE, 0x00000010 +.set CYREG_CAN_CAN_TX4_CONTROL, 0x402e0060 +.set CYREG_CAN_CAN_TX4_ID, 0x402e0064 +.set CYREG_CAN_CAN_TX4_DATA_HIGH, 0x402e0068 +.set CYREG_CAN_CAN_TX4_DATA_LOW, 0x402e006c +.set CYDEV_CAN_CAN_TX5_BASE, 0x402e0070 +.set CYDEV_CAN_CAN_TX5_SIZE, 0x00000010 +.set CYREG_CAN_CAN_TX5_CONTROL, 0x402e0070 +.set CYREG_CAN_CAN_TX5_ID, 0x402e0074 +.set CYREG_CAN_CAN_TX5_DATA_HIGH, 0x402e0078 +.set CYREG_CAN_CAN_TX5_DATA_LOW, 0x402e007c +.set CYDEV_CAN_CAN_TX6_BASE, 0x402e0080 +.set CYDEV_CAN_CAN_TX6_SIZE, 0x00000010 +.set CYREG_CAN_CAN_TX6_CONTROL, 0x402e0080 +.set CYREG_CAN_CAN_TX6_ID, 0x402e0084 +.set CYREG_CAN_CAN_TX6_DATA_HIGH, 0x402e0088 +.set CYREG_CAN_CAN_TX6_DATA_LOW, 0x402e008c +.set CYDEV_CAN_CAN_TX7_BASE, 0x402e0090 +.set CYDEV_CAN_CAN_TX7_SIZE, 0x00000010 +.set CYREG_CAN_CAN_TX7_CONTROL, 0x402e0090 +.set CYREG_CAN_CAN_TX7_ID, 0x402e0094 +.set CYREG_CAN_CAN_TX7_DATA_HIGH, 0x402e0098 +.set CYREG_CAN_CAN_TX7_DATA_LOW, 0x402e009c +.set CYDEV_CAN_CAN_RX0_BASE, 0x402e00a0 +.set CYDEV_CAN_CAN_RX0_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX0_CONTROL, 0x402e00a0 +.set CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__OFFSET, 0x00000000 +.set CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__OFFSET, 0x00000001 +.set CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_RX_RTR_ABORT__OFFSET, 0x00000002 +.set CYFLD_CAN_CAN_RX_RTR_ABORT__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_RX_BUFFER_EN__OFFSET, 0x00000003 +.set CYFLD_CAN_CAN_RX_BUFFER_EN__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_RX_RTR_REPLY__OFFSET, 0x00000004 +.set CYFLD_CAN_CAN_RX_RTR_REPLY__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_RX_RX_INT_EBL__OFFSET, 0x00000005 +.set CYFLD_CAN_CAN_RX_RX_INT_EBL__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_RX_LINK_FLAG__OFFSET, 0x00000006 +.set CYFLD_CAN_CAN_RX_LINK_FLAG__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_RX_WPNL__OFFSET, 0x00000007 +.set CYFLD_CAN_CAN_RX_WPNL__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_RX_DLC__OFFSET, 0x00000010 +.set CYFLD_CAN_CAN_RX_DLC__SIZE, 0x00000004 +.set CYFLD_CAN_CAN_RX_IDE_FMT__OFFSET, 0x00000014 +.set CYFLD_CAN_CAN_RX_IDE_FMT__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_RX_RTR_MSG__OFFSET, 0x00000015 +.set CYFLD_CAN_CAN_RX_RTR_MSG__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_RX_WPNH__OFFSET, 0x00000017 +.set CYFLD_CAN_CAN_RX_WPNH__SIZE, 0x00000001 +.set CYREG_CAN_CAN_RX0_ID, 0x402e00a4 +.set CYFLD_CAN_CAN_RX_ID__OFFSET, 0x00000003 +.set CYFLD_CAN_CAN_RX_ID__SIZE, 0x0000001d +.set CYREG_CAN_CAN_RX0_DATA_HIGH, 0x402e00a8 +.set CYFLD_CAN_CAN_RX_DATA__OFFSET, 0x00000000 +.set CYFLD_CAN_CAN_RX_DATA__SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX0_DATA_LOW, 0x402e00ac +.set CYREG_CAN_CAN_RX0_AMR, 0x402e00b0 +.set CYFLD_CAN_CAN_RX_RTR__OFFSET, 0x00000001 +.set CYFLD_CAN_CAN_RX_RTR__SIZE, 0x00000001 +.set CYFLD_CAN_CAN_RX_IDE__OFFSET, 0x00000002 +.set CYFLD_CAN_CAN_RX_IDE__SIZE, 0x00000001 +.set CYREG_CAN_CAN_RX0_ACR, 0x402e00b4 +.set CYREG_CAN_CAN_RX0_AMR_DATA, 0x402e00b8 +.set CYFLD_CAN_CAN_RX_DATAL__OFFSET, 0x00000000 +.set CYFLD_CAN_CAN_RX_DATAL__SIZE, 0x00000010 +.set CYREG_CAN_CAN_RX0_ACR_DATA, 0x402e00bc +.set CYDEV_CAN_CAN_RX1_BASE, 0x402e00c0 +.set CYDEV_CAN_CAN_RX1_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX1_CONTROL, 0x402e00c0 +.set CYREG_CAN_CAN_RX1_ID, 0x402e00c4 +.set CYREG_CAN_CAN_RX1_DATA_HIGH, 0x402e00c8 +.set CYREG_CAN_CAN_RX1_DATA_LOW, 0x402e00cc +.set CYREG_CAN_CAN_RX1_AMR, 0x402e00d0 +.set CYREG_CAN_CAN_RX1_ACR, 0x402e00d4 +.set CYREG_CAN_CAN_RX1_AMR_DATA, 0x402e00d8 +.set CYREG_CAN_CAN_RX1_ACR_DATA, 0x402e00dc +.set CYDEV_CAN_CAN_RX2_BASE, 0x402e00e0 +.set CYDEV_CAN_CAN_RX2_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX2_CONTROL, 0x402e00e0 +.set CYREG_CAN_CAN_RX2_ID, 0x402e00e4 +.set CYREG_CAN_CAN_RX2_DATA_HIGH, 0x402e00e8 +.set CYREG_CAN_CAN_RX2_DATA_LOW, 0x402e00ec +.set CYREG_CAN_CAN_RX2_AMR, 0x402e00f0 +.set CYREG_CAN_CAN_RX2_ACR, 0x402e00f4 +.set CYREG_CAN_CAN_RX2_AMR_DATA, 0x402e00f8 +.set CYREG_CAN_CAN_RX2_ACR_DATA, 0x402e00fc +.set CYDEV_CAN_CAN_RX3_BASE, 0x402e0100 +.set CYDEV_CAN_CAN_RX3_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX3_CONTROL, 0x402e0100 +.set CYREG_CAN_CAN_RX3_ID, 0x402e0104 +.set CYREG_CAN_CAN_RX3_DATA_HIGH, 0x402e0108 +.set CYREG_CAN_CAN_RX3_DATA_LOW, 0x402e010c +.set CYREG_CAN_CAN_RX3_AMR, 0x402e0110 +.set CYREG_CAN_CAN_RX3_ACR, 0x402e0114 +.set CYREG_CAN_CAN_RX3_AMR_DATA, 0x402e0118 +.set CYREG_CAN_CAN_RX3_ACR_DATA, 0x402e011c +.set CYDEV_CAN_CAN_RX4_BASE, 0x402e0120 +.set CYDEV_CAN_CAN_RX4_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX4_CONTROL, 0x402e0120 +.set CYREG_CAN_CAN_RX4_ID, 0x402e0124 +.set CYREG_CAN_CAN_RX4_DATA_HIGH, 0x402e0128 +.set CYREG_CAN_CAN_RX4_DATA_LOW, 0x402e012c +.set CYREG_CAN_CAN_RX4_AMR, 0x402e0130 +.set CYREG_CAN_CAN_RX4_ACR, 0x402e0134 +.set CYREG_CAN_CAN_RX4_AMR_DATA, 0x402e0138 +.set CYREG_CAN_CAN_RX4_ACR_DATA, 0x402e013c +.set CYDEV_CAN_CAN_RX5_BASE, 0x402e0140 +.set CYDEV_CAN_CAN_RX5_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX5_CONTROL, 0x402e0140 +.set CYREG_CAN_CAN_RX5_ID, 0x402e0144 +.set CYREG_CAN_CAN_RX5_DATA_HIGH, 0x402e0148 +.set CYREG_CAN_CAN_RX5_DATA_LOW, 0x402e014c +.set CYREG_CAN_CAN_RX5_AMR, 0x402e0150 +.set CYREG_CAN_CAN_RX5_ACR, 0x402e0154 +.set CYREG_CAN_CAN_RX5_AMR_DATA, 0x402e0158 +.set CYREG_CAN_CAN_RX5_ACR_DATA, 0x402e015c +.set CYDEV_CAN_CAN_RX6_BASE, 0x402e0160 +.set CYDEV_CAN_CAN_RX6_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX6_CONTROL, 0x402e0160 +.set CYREG_CAN_CAN_RX6_ID, 0x402e0164 +.set CYREG_CAN_CAN_RX6_DATA_HIGH, 0x402e0168 +.set CYREG_CAN_CAN_RX6_DATA_LOW, 0x402e016c +.set CYREG_CAN_CAN_RX6_AMR, 0x402e0170 +.set CYREG_CAN_CAN_RX6_ACR, 0x402e0174 +.set CYREG_CAN_CAN_RX6_AMR_DATA, 0x402e0178 +.set CYREG_CAN_CAN_RX6_ACR_DATA, 0x402e017c +.set CYDEV_CAN_CAN_RX7_BASE, 0x402e0180 +.set CYDEV_CAN_CAN_RX7_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX7_CONTROL, 0x402e0180 +.set CYREG_CAN_CAN_RX7_ID, 0x402e0184 +.set CYREG_CAN_CAN_RX7_DATA_HIGH, 0x402e0188 +.set CYREG_CAN_CAN_RX7_DATA_LOW, 0x402e018c +.set CYREG_CAN_CAN_RX7_AMR, 0x402e0190 +.set CYREG_CAN_CAN_RX7_ACR, 0x402e0194 +.set CYREG_CAN_CAN_RX7_AMR_DATA, 0x402e0198 +.set CYREG_CAN_CAN_RX7_ACR_DATA, 0x402e019c +.set CYDEV_CAN_CAN_RX8_BASE, 0x402e01a0 +.set CYDEV_CAN_CAN_RX8_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX8_CONTROL, 0x402e01a0 +.set CYREG_CAN_CAN_RX8_ID, 0x402e01a4 +.set CYREG_CAN_CAN_RX8_DATA_HIGH, 0x402e01a8 +.set CYREG_CAN_CAN_RX8_DATA_LOW, 0x402e01ac +.set CYREG_CAN_CAN_RX8_AMR, 0x402e01b0 +.set CYREG_CAN_CAN_RX8_ACR, 0x402e01b4 +.set CYREG_CAN_CAN_RX8_AMR_DATA, 0x402e01b8 +.set CYREG_CAN_CAN_RX8_ACR_DATA, 0x402e01bc +.set CYDEV_CAN_CAN_RX9_BASE, 0x402e01c0 +.set CYDEV_CAN_CAN_RX9_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX9_CONTROL, 0x402e01c0 +.set CYREG_CAN_CAN_RX9_ID, 0x402e01c4 +.set CYREG_CAN_CAN_RX9_DATA_HIGH, 0x402e01c8 +.set CYREG_CAN_CAN_RX9_DATA_LOW, 0x402e01cc +.set CYREG_CAN_CAN_RX9_AMR, 0x402e01d0 +.set CYREG_CAN_CAN_RX9_ACR, 0x402e01d4 +.set CYREG_CAN_CAN_RX9_AMR_DATA, 0x402e01d8 +.set CYREG_CAN_CAN_RX9_ACR_DATA, 0x402e01dc +.set CYDEV_CAN_CAN_RX10_BASE, 0x402e01e0 +.set CYDEV_CAN_CAN_RX10_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX10_CONTROL, 0x402e01e0 +.set CYREG_CAN_CAN_RX10_ID, 0x402e01e4 +.set CYREG_CAN_CAN_RX10_DATA_HIGH, 0x402e01e8 +.set CYREG_CAN_CAN_RX10_DATA_LOW, 0x402e01ec +.set CYREG_CAN_CAN_RX10_AMR, 0x402e01f0 +.set CYREG_CAN_CAN_RX10_ACR, 0x402e01f4 +.set CYREG_CAN_CAN_RX10_AMR_DATA, 0x402e01f8 +.set CYREG_CAN_CAN_RX10_ACR_DATA, 0x402e01fc +.set CYDEV_CAN_CAN_RX11_BASE, 0x402e0200 +.set CYDEV_CAN_CAN_RX11_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX11_CONTROL, 0x402e0200 +.set CYREG_CAN_CAN_RX11_ID, 0x402e0204 +.set CYREG_CAN_CAN_RX11_DATA_HIGH, 0x402e0208 +.set CYREG_CAN_CAN_RX11_DATA_LOW, 0x402e020c +.set CYREG_CAN_CAN_RX11_AMR, 0x402e0210 +.set CYREG_CAN_CAN_RX11_ACR, 0x402e0214 +.set CYREG_CAN_CAN_RX11_AMR_DATA, 0x402e0218 +.set CYREG_CAN_CAN_RX11_ACR_DATA, 0x402e021c +.set CYDEV_CAN_CAN_RX12_BASE, 0x402e0220 +.set CYDEV_CAN_CAN_RX12_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX12_CONTROL, 0x402e0220 +.set CYREG_CAN_CAN_RX12_ID, 0x402e0224 +.set CYREG_CAN_CAN_RX12_DATA_HIGH, 0x402e0228 +.set CYREG_CAN_CAN_RX12_DATA_LOW, 0x402e022c +.set CYREG_CAN_CAN_RX12_AMR, 0x402e0230 +.set CYREG_CAN_CAN_RX12_ACR, 0x402e0234 +.set CYREG_CAN_CAN_RX12_AMR_DATA, 0x402e0238 +.set CYREG_CAN_CAN_RX12_ACR_DATA, 0x402e023c +.set CYDEV_CAN_CAN_RX13_BASE, 0x402e0240 +.set CYDEV_CAN_CAN_RX13_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX13_CONTROL, 0x402e0240 +.set CYREG_CAN_CAN_RX13_ID, 0x402e0244 +.set CYREG_CAN_CAN_RX13_DATA_HIGH, 0x402e0248 +.set CYREG_CAN_CAN_RX13_DATA_LOW, 0x402e024c +.set CYREG_CAN_CAN_RX13_AMR, 0x402e0250 +.set CYREG_CAN_CAN_RX13_ACR, 0x402e0254 +.set CYREG_CAN_CAN_RX13_AMR_DATA, 0x402e0258 +.set CYREG_CAN_CAN_RX13_ACR_DATA, 0x402e025c +.set CYDEV_CAN_CAN_RX14_BASE, 0x402e0260 +.set CYDEV_CAN_CAN_RX14_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX14_CONTROL, 0x402e0260 +.set CYREG_CAN_CAN_RX14_ID, 0x402e0264 +.set CYREG_CAN_CAN_RX14_DATA_HIGH, 0x402e0268 +.set CYREG_CAN_CAN_RX14_DATA_LOW, 0x402e026c +.set CYREG_CAN_CAN_RX14_AMR, 0x402e0270 +.set CYREG_CAN_CAN_RX14_ACR, 0x402e0274 +.set CYREG_CAN_CAN_RX14_AMR_DATA, 0x402e0278 +.set CYREG_CAN_CAN_RX14_ACR_DATA, 0x402e027c +.set CYDEV_CAN_CAN_RX15_BASE, 0x402e0280 +.set CYDEV_CAN_CAN_RX15_SIZE, 0x00000020 +.set CYREG_CAN_CAN_RX15_CONTROL, 0x402e0280 +.set CYREG_CAN_CAN_RX15_ID, 0x402e0284 +.set CYREG_CAN_CAN_RX15_DATA_HIGH, 0x402e0288 +.set CYREG_CAN_CAN_RX15_DATA_LOW, 0x402e028c +.set CYREG_CAN_CAN_RX15_AMR, 0x402e0290 +.set CYREG_CAN_CAN_RX15_ACR, 0x402e0294 +.set CYREG_CAN_CAN_RX15_AMR_DATA, 0x402e0298 +.set CYREG_CAN_CAN_RX15_ACR_DATA, 0x402e029c +.set CYREG_CAN_CNTL, 0x402e0400 +.set CYFLD_CAN_TT_ENABLE__OFFSET, 0x00000000 +.set CYFLD_CAN_TT_ENABLE__SIZE, 0x00000001 +.set CYFLD_CAN_IP_ENABLE__OFFSET, 0x0000001f +.set CYFLD_CAN_IP_ENABLE__SIZE, 0x00000001 +.set CYREG_CAN_TTCAN_COUNTER, 0x402e0404 +.set CYFLD_CAN_LOCAL_TIME__OFFSET, 0x00000010 +.set CYFLD_CAN_LOCAL_TIME__SIZE, 0x00000010 +.set CYREG_CAN_TTCAN_COMPARE, 0x402e0408 +.set CYFLD_CAN_TIME_MARK__OFFSET, 0x00000010 +.set CYFLD_CAN_TIME_MARK__SIZE, 0x00000010 +.set CYREG_CAN_TTCAN_CAPTURE, 0x402e040c +.set CYFLD_CAN_SYNC_MARK__OFFSET, 0x00000010 +.set CYFLD_CAN_SYNC_MARK__SIZE, 0x00000010 +.set CYREG_CAN_TTCAN_TIMING, 0x402e0410 +.set CYREG_CAN_INTR_CAN, 0x402e0414 +.set CYFLD_CAN_INT_STATUS__OFFSET, 0x00000000 +.set CYFLD_CAN_INT_STATUS__SIZE, 0x00000001 +.set CYFLD_CAN_TT_COMPARE__OFFSET, 0x00000001 +.set CYFLD_CAN_TT_COMPARE__SIZE, 0x00000001 +.set CYFLD_CAN_TT_CAPTURE__OFFSET, 0x00000002 +.set CYFLD_CAN_TT_CAPTURE__SIZE, 0x00000001 +.set CYREG_CAN_INTR_CAN_SET, 0x402e0418 +.set CYREG_CAN_INTR_CAN_MASK, 0x402e041c +.set CYREG_CAN_INTR_CAN_MASKED, 0x402e0420 +.set CYDEV_EXCO_BASE, 0x402f0000 +.set CYDEV_EXCO_SIZE, 0x00010000 +.set CYREG_EXCO_CLK_SELECT, 0x402f0000 +.set CYFLD_EXCO_CLK_SELECT__OFFSET, 0x00000000 +.set CYFLD_EXCO_CLK_SELECT__SIZE, 0x00000001 +.set CYFLD_EXCO_REF_SEL__OFFSET, 0x00000001 +.set CYFLD_EXCO_REF_SEL__SIZE, 0x00000001 +.set CYREG_EXCO_ECO_CONFIG, 0x402f0008 +.set CYFLD_EXCO_CLK_EN__OFFSET, 0x00000000 +.set CYFLD_EXCO_CLK_EN__SIZE, 0x00000001 +.set CYFLD_EXCO_AGC_EN__OFFSET, 0x00000001 +.set CYFLD_EXCO_AGC_EN__SIZE, 0x00000001 +.set CYFLD_EXCO_ENABLE__OFFSET, 0x0000001f +.set CYFLD_EXCO_ENABLE__SIZE, 0x00000001 +.set CYREG_EXCO_ECO_STATUS, 0x402f000c +.set CYFLD_EXCO_WATCHDOG_ERROR__OFFSET, 0x00000000 +.set CYFLD_EXCO_WATCHDOG_ERROR__SIZE, 0x00000001 +.set CYREG_EXCO_PLL_CONFIG, 0x402f0014 +.set CYFLD_EXCO_FEEDBACK_DIV__OFFSET, 0x00000000 +.set CYFLD_EXCO_FEEDBACK_DIV__SIZE, 0x00000008 +.set CYFLD_EXCO_REFERENCE_DIV__OFFSET, 0x00000008 +.set CYFLD_EXCO_REFERENCE_DIV__SIZE, 0x00000006 +.set CYFLD_EXCO_OUTPUT_DIV__OFFSET, 0x0000000e +.set CYFLD_EXCO_OUTPUT_DIV__SIZE, 0x00000002 +.set CYVAL_EXCO_OUTPUT_DIV_PASS, 0x00000000 +.set CYVAL_EXCO_OUTPUT_DIV_DIV2, 0x00000001 +.set CYVAL_EXCO_OUTPUT_DIV_DIV4, 0x00000002 +.set CYVAL_EXCO_OUTPUT_DIV_DIV8, 0x00000003 +.set CYFLD_EXCO_ICP_SEL__OFFSET, 0x00000010 +.set CYFLD_EXCO_ICP_SEL__SIZE, 0x00000003 +.set CYFLD_EXCO_BYPASS_SEL__OFFSET, 0x00000014 +.set CYFLD_EXCO_BYPASS_SEL__SIZE, 0x00000002 +.set CYVAL_EXCO_BYPASS_SEL_AUTO, 0x00000000 +.set CYVAL_EXCO_BYPASS_SEL_AUTO1, 0x00000001 +.set CYVAL_EXCO_BYPASS_SEL_PLL_REF, 0x00000002 +.set CYVAL_EXCO_BYPASS_SEL_PLL_OUT, 0x00000003 +.set CYFLD_EXCO_ISOLATE_N__OFFSET, 0x0000001e +.set CYFLD_EXCO_ISOLATE_N__SIZE, 0x00000001 +.set CYREG_EXCO_PLL_STATUS, 0x402f0018 +.set CYFLD_EXCO_LOCKED__OFFSET, 0x00000000 +.set CYFLD_EXCO_LOCKED__SIZE, 0x00000001 +.set CYREG_EXCO_PLL_TEST, 0x402f001c +.set CYFLD_EXCO_TEST_MODE__OFFSET, 0x00000000 +.set CYFLD_EXCO_TEST_MODE__SIZE, 0x00000003 +.set CYVAL_EXCO_TEST_MODE_NORMAL, 0x00000000 +.set CYVAL_EXCO_TEST_MODE_TEST_VC_LKG, 0x00000001 +.set CYVAL_EXCO_TEST_MODE_TEST_CP_DN, 0x00000002 +.set CYVAL_EXCO_TEST_MODE_TEST_CP_UP, 0x00000003 +.set CYVAL_EXCO_TEST_MODE_USER_EXT_FL, 0x00000004 +.set CYVAL_EXCO_TEST_MODE_TEST_CTR_PQ, 0x00000005 +.set CYVAL_EXCO_TEST_MODE_TEST_LD_DLY, 0x00000006 +.set CYVAL_EXCO_TEST_MODE_TEST_CTR_ALT, 0x00000007 +.set CYFLD_EXCO_FAST_LOCK_EN__OFFSET, 0x00000003 +.set CYFLD_EXCO_FAST_LOCK_EN__SIZE, 0x00000001 +.set CYFLD_EXCO_UNLOCK_OCCURRED__OFFSET, 0x00000004 +.set CYFLD_EXCO_UNLOCK_OCCURRED__SIZE, 0x00000001 +.set CYREG_EXCO_EXCO_PGM_CLK, 0x402f0020 +.set CYFLD_EXCO_CLK_ECO__OFFSET, 0x00000001 +.set CYFLD_EXCO_CLK_ECO__SIZE, 0x00000001 +.set CYFLD_EXCO_CLK_PLL0_IN__OFFSET, 0x00000002 +.set CYFLD_EXCO_CLK_PLL0_IN__SIZE, 0x00000001 +.set CYFLD_EXCO_CLK_PLL0_OUT__OFFSET, 0x00000003 +.set CYFLD_EXCO_CLK_PLL0_OUT__SIZE, 0x00000001 +.set CYFLD_EXCO_EN_CLK_PLL0__OFFSET, 0x00000004 +.set CYFLD_EXCO_EN_CLK_PLL0__SIZE, 0x00000001 +.set CYREG_EXCO_ECO_TRIM0, 0x402fff00 +.set CYFLD_EXCO_WDTRIM__OFFSET, 0x00000000 +.set CYFLD_EXCO_WDTRIM__SIZE, 0x00000002 +.set CYFLD_EXCO_ATRIM__OFFSET, 0x00000002 +.set CYFLD_EXCO_ATRIM__SIZE, 0x00000003 +.set CYREG_EXCO_ECO_TRIM1, 0x402fff04 +.set CYFLD_EXCO_FTRIM__OFFSET, 0x00000000 +.set CYFLD_EXCO_FTRIM__SIZE, 0x00000002 +.set CYFLD_EXCO_RTRIM__OFFSET, 0x00000002 +.set CYFLD_EXCO_RTRIM__SIZE, 0x00000002 +.set CYFLD_EXCO_GTRIM__OFFSET, 0x00000004 +.set CYFLD_EXCO_GTRIM__SIZE, 0x00000002 +.set CYREG_EXCO_ECO_TRIM2, 0x402fff08 +.set CYFLD_EXCO_ITRIM__OFFSET, 0x00000000 +.set CYFLD_EXCO_ITRIM__SIZE, 0x00000006 +.set CYREG_EXCO_PLL_TRIM, 0x402fff0c +.set CYFLD_EXCO_VCO_GAIN__OFFSET, 0x00000000 +.set CYFLD_EXCO_VCO_GAIN__SIZE, 0x00000002 +.set CYFLD_EXCO_LOCK_WINDOW__OFFSET, 0x00000002 +.set CYFLD_EXCO_LOCK_WINDOW__SIZE, 0x00000002 +.set CYVAL_EXCO_LOCK_WINDOW_DELAY_25NS, 0x00000000 +.set CYVAL_EXCO_LOCK_WINDOW_DELAY_50NS, 0x00000001 +.set CYVAL_EXCO_LOCK_WINDOW_DELAY_75NS, 0x00000002 +.set CYVAL_EXCO_LOCK_WINDOW_DELAY_100NS, 0x00000003 +.set CYFLD_EXCO_LOCK_DELAY__OFFSET, 0x00000004 +.set CYFLD_EXCO_LOCK_DELAY__SIZE, 0x00000002 +.set CYVAL_EXCO_LOCK_DELAY_PFD_CLK_16, 0x00000000 +.set CYVAL_EXCO_LOCK_DELAY_PFD_CLK_32, 0x00000001 +.set CYVAL_EXCO_LOCK_DELAY_PFD_CLK_48, 0x00000002 +.set CYVAL_EXCO_LOCK_DELAY_PFD_CLK_64, 0x00000003 +.set CYDEV_CTBM0_BASE, 0x40300000 +.set CYDEV_CTBM0_SIZE, 0x00010000 +.set CYREG_CTBM0_CTB_CTRL, 0x40300000 +.set CYFLD_CTBM_DEEPSLEEP_ON__OFFSET, 0x0000001e +.set CYFLD_CTBM_DEEPSLEEP_ON__SIZE, 0x00000001 +.set CYFLD_CTBM_ENABLED__OFFSET, 0x0000001f +.set CYFLD_CTBM_ENABLED__SIZE, 0x00000001 +.set CYREG_CTBM0_OA_RES0_CTRL, 0x40300004 +.set CYFLD_CTBM_OA0_PWR_MODE__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_PWR_MODE__SIZE, 0x00000002 +.set CYVAL_CTBM_OA0_PWR_MODE_OFF, 0x00000000 +.set CYVAL_CTBM_OA0_PWR_MODE_LOW, 0x00000001 +.set CYVAL_CTBM_OA0_PWR_MODE_MEDIUM, 0x00000002 +.set CYVAL_CTBM_OA0_PWR_MODE_HIGH, 0x00000003 +.set CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET, 0x00000002 +.set CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_COMP_EN__OFFSET, 0x00000004 +.set CYFLD_CTBM_OA0_COMP_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_HYST_EN__OFFSET, 0x00000005 +.set CYFLD_CTBM_OA0_HYST_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET, 0x00000006 +.set CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_DSI_LEVEL__OFFSET, 0x00000007 +.set CYFLD_CTBM_OA0_DSI_LEVEL__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0_COMPINT__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA0_COMPINT__SIZE, 0x00000002 +.set CYVAL_CTBM_OA0_COMPINT_DISABLE, 0x00000000 +.set CYVAL_CTBM_OA0_COMPINT_RISING, 0x00000001 +.set CYVAL_CTBM_OA0_COMPINT_FALLING, 0x00000002 +.set CYVAL_CTBM_OA0_COMPINT_BOTH, 0x00000003 +.set CYFLD_CTBM_OA0_PUMP_EN__OFFSET, 0x0000000b +.set CYFLD_CTBM_OA0_PUMP_EN__SIZE, 0x00000001 +.set CYREG_CTBM0_OA_RES1_CTRL, 0x40300008 +.set CYFLD_CTBM_OA1_PWR_MODE__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_PWR_MODE__SIZE, 0x00000002 +.set CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET, 0x00000002 +.set CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_COMP_EN__OFFSET, 0x00000004 +.set CYFLD_CTBM_OA1_COMP_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_HYST_EN__OFFSET, 0x00000005 +.set CYFLD_CTBM_OA1_HYST_EN__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET, 0x00000006 +.set CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_DSI_LEVEL__OFFSET, 0x00000007 +.set CYFLD_CTBM_OA1_DSI_LEVEL__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_COMPINT__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA1_COMPINT__SIZE, 0x00000002 +.set CYVAL_CTBM_OA1_COMPINT_DISABLE, 0x00000000 +.set CYVAL_CTBM_OA1_COMPINT_RISING, 0x00000001 +.set CYVAL_CTBM_OA1_COMPINT_FALLING, 0x00000002 +.set CYVAL_CTBM_OA1_COMPINT_BOTH, 0x00000003 +.set CYFLD_CTBM_OA1_PUMP_EN__OFFSET, 0x0000000b +.set CYFLD_CTBM_OA1_PUMP_EN__SIZE, 0x00000001 +.set CYREG_CTBM0_COMP_STAT, 0x4030000c +.set CYFLD_CTBM_OA0_COMP__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_COMP__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1_COMP__OFFSET, 0x00000010 +.set CYFLD_CTBM_OA1_COMP__SIZE, 0x00000001 +.set CYREG_CTBM0_INTR, 0x40300020 +.set CYFLD_CTBM_COMP0__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1__SIZE, 0x00000001 +.set CYREG_CTBM0_INTR_SET, 0x40300024 +.set CYFLD_CTBM_COMP0_SET__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0_SET__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1_SET__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1_SET__SIZE, 0x00000001 +.set CYREG_CTBM0_INTR_MASK, 0x40300028 +.set CYFLD_CTBM_COMP0_MASK__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0_MASK__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1_MASK__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1_MASK__SIZE, 0x00000001 +.set CYREG_CTBM0_INTR_MASKED, 0x4030002c +.set CYFLD_CTBM_COMP0_MASKED__OFFSET, 0x00000000 +.set CYFLD_CTBM_COMP0_MASKED__SIZE, 0x00000001 +.set CYFLD_CTBM_COMP1_MASKED__OFFSET, 0x00000001 +.set CYFLD_CTBM_COMP1_MASKED__SIZE, 0x00000001 +.set CYREG_CTBM0_DFT_CTRL, 0x40300030 +.set CYFLD_CTBM_DFT_MODE__OFFSET, 0x00000000 +.set CYFLD_CTBM_DFT_MODE__SIZE, 0x00000003 +.set CYFLD_CTBM_DFT_EN__OFFSET, 0x0000001f +.set CYFLD_CTBM_DFT_EN__SIZE, 0x00000001 +.set CYREG_CTBM0_OA0_SW, 0x40300080 +.set CYFLD_CTBM_OA0P_A00__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0P_A00__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0P_A20__OFFSET, 0x00000002 +.set CYFLD_CTBM_OA0P_A20__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0P_A30__OFFSET, 0x00000003 +.set CYFLD_CTBM_OA0P_A30__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0M_A11__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA0M_A11__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0M_A81__OFFSET, 0x0000000e +.set CYFLD_CTBM_OA0M_A81__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0O_D51__OFFSET, 0x00000012 +.set CYFLD_CTBM_OA0O_D51__SIZE, 0x00000001 +.set CYFLD_CTBM_OA0O_D81__OFFSET, 0x00000015 +.set CYFLD_CTBM_OA0O_D81__SIZE, 0x00000001 +.set CYREG_CTBM0_OA0_SW_CLEAR, 0x40300084 +.set CYREG_CTBM0_OA1_SW, 0x40300088 +.set CYFLD_CTBM_OA1P_A03__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1P_A03__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1P_A13__OFFSET, 0x00000001 +.set CYFLD_CTBM_OA1P_A13__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1P_A43__OFFSET, 0x00000004 +.set CYFLD_CTBM_OA1P_A43__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1M_A22__OFFSET, 0x00000008 +.set CYFLD_CTBM_OA1M_A22__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1M_A82__OFFSET, 0x0000000e +.set CYFLD_CTBM_OA1M_A82__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D52__OFFSET, 0x00000012 +.set CYFLD_CTBM_OA1O_D52__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D62__OFFSET, 0x00000013 +.set CYFLD_CTBM_OA1O_D62__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D82__OFFSET, 0x00000015 +.set CYFLD_CTBM_OA1O_D82__SIZE, 0x00000001 +.set CYREG_CTBM0_OA1_SW_CLEAR, 0x4030008c +.set CYREG_CTBM0_CTB_SW_HW_CTRL, 0x403000c0 +.set CYFLD_CTBM_P2_HW_CTRL__OFFSET, 0x00000002 +.set CYFLD_CTBM_P2_HW_CTRL__SIZE, 0x00000001 +.set CYFLD_CTBM_P3_HW_CTRL__OFFSET, 0x00000003 +.set CYFLD_CTBM_P3_HW_CTRL__SIZE, 0x00000001 +.set CYREG_CTBM0_CTB_SW_STATUS, 0x403000c4 +.set CYFLD_CTBM_OA0O_D51_STAT__OFFSET, 0x0000001c +.set CYFLD_CTBM_OA0O_D51_STAT__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D52_STAT__OFFSET, 0x0000001d +.set CYFLD_CTBM_OA1O_D52_STAT__SIZE, 0x00000001 +.set CYFLD_CTBM_OA1O_D62_STAT__OFFSET, 0x0000001e +.set CYFLD_CTBM_OA1O_D62_STAT__SIZE, 0x00000001 +.set CYREG_CTBM0_OA0_OFFSET_TRIM, 0x40300f00 +.set CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM0_OA0_SLOPE_OFFSET_TRIM, 0x40300f04 +.set CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM0_OA0_COMP_TRIM, 0x40300f08 +.set CYFLD_CTBM_OA0_COMP_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA0_COMP_TRIM__SIZE, 0x00000002 +.set CYREG_CTBM0_OA1_OFFSET_TRIM, 0x40300f0c +.set CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM0_OA1_SLOPE_OFFSET_TRIM, 0x40300f10 +.set CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE, 0x00000006 +.set CYREG_CTBM0_OA1_COMP_TRIM, 0x40300f14 +.set CYFLD_CTBM_OA1_COMP_TRIM__OFFSET, 0x00000000 +.set CYFLD_CTBM_OA1_COMP_TRIM__SIZE, 0x00000002 +.set CYDEV_SAR_BASE, 0x403a0000 +.set CYDEV_SAR_SIZE, 0x00010000 +.set CYREG_SAR_CTRL, 0x403a0000 +.set CYFLD_SAR_VREF_SEL__OFFSET, 0x00000004 +.set CYFLD_SAR_VREF_SEL__SIZE, 0x00000003 +.set CYVAL_SAR_VREF_SEL_VREF0, 0x00000000 +.set CYVAL_SAR_VREF_SEL_VREF1, 0x00000001 +.set CYVAL_SAR_VREF_SEL_VREF2, 0x00000002 +.set CYVAL_SAR_VREF_SEL_VREF_AROUTE, 0x00000003 +.set CYVAL_SAR_VREF_SEL_VBGR, 0x00000004 +.set CYVAL_SAR_VREF_SEL_VREF_EXT, 0x00000005 +.set CYVAL_SAR_VREF_SEL_VDDA_DIV_2, 0x00000006 +.set CYVAL_SAR_VREF_SEL_VDDA, 0x00000007 +.set CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET, 0x00000007 +.set CYFLD_SAR_VREF_BYP_CAP_EN__SIZE, 0x00000001 +.set CYFLD_SAR_NEG_SEL__OFFSET, 0x00000009 +.set CYFLD_SAR_NEG_SEL__SIZE, 0x00000003 +.set CYVAL_SAR_NEG_SEL_VSSA_KELVIN, 0x00000000 +.set CYVAL_SAR_NEG_SEL_ART_VSSA, 0x00000001 +.set CYVAL_SAR_NEG_SEL_P1, 0x00000002 +.set CYVAL_SAR_NEG_SEL_P3, 0x00000003 +.set CYVAL_SAR_NEG_SEL_P5, 0x00000004 +.set CYVAL_SAR_NEG_SEL_P7, 0x00000005 +.set CYVAL_SAR_NEG_SEL_ACORE, 0x00000006 +.set CYVAL_SAR_NEG_SEL_VREF, 0x00000007 +.set CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET, 0x0000000d +.set CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE, 0x00000001 +.set CYFLD_SAR_PWR_CTRL_VREF__OFFSET, 0x0000000e +.set CYFLD_SAR_PWR_CTRL_VREF__SIZE, 0x00000002 +.set CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR, 0x00000000 +.set CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR, 0x00000001 +.set CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR, 0x00000002 +.set CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR, 0x00000003 +.set CYFLD_SAR_SPARE__OFFSET, 0x00000010 +.set CYFLD_SAR_SPARE__SIZE, 0x00000004 +.set CYFLD_SAR_BOOSTPUMP_EN__OFFSET, 0x00000014 +.set CYFLD_SAR_BOOSTPUMP_EN__SIZE, 0x00000001 +.set CYFLD_SAR_ICONT_LV__OFFSET, 0x00000018 +.set CYFLD_SAR_ICONT_LV__SIZE, 0x00000002 +.set CYVAL_SAR_ICONT_LV_NORMAL_PWR, 0x00000000 +.set CYVAL_SAR_ICONT_LV_HALF_PWR, 0x00000001 +.set CYVAL_SAR_ICONT_LV_MORE_PWR, 0x00000002 +.set CYVAL_SAR_ICONT_LV_QUARTER_PWR, 0x00000003 +.set CYFLD_SAR_DEEPSLEEP_ON__OFFSET, 0x0000001b +.set CYFLD_SAR_DEEPSLEEP_ON__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET, 0x0000001c +.set CYFLD_SAR_DSI_SYNC_CONFIG__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_MODE__OFFSET, 0x0000001d +.set CYFLD_SAR_DSI_MODE__SIZE, 0x00000001 +.set CYFLD_SAR_SWITCH_DISABLE__OFFSET, 0x0000001e +.set CYFLD_SAR_SWITCH_DISABLE__SIZE, 0x00000001 +.set CYFLD_SAR_ENABLED__OFFSET, 0x0000001f +.set CYFLD_SAR_ENABLED__SIZE, 0x00000001 +.set CYREG_SAR_SAMPLE_CTRL, 0x403a0004 +.set CYFLD_SAR_SUB_RESOLUTION__OFFSET, 0x00000000 +.set CYFLD_SAR_SUB_RESOLUTION__SIZE, 0x00000001 +.set CYVAL_SAR_SUB_RESOLUTION_8B, 0x00000000 +.set CYVAL_SAR_SUB_RESOLUTION_10B, 0x00000001 +.set CYFLD_SAR_LEFT_ALIGN__OFFSET, 0x00000001 +.set CYFLD_SAR_LEFT_ALIGN__SIZE, 0x00000001 +.set CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET, 0x00000002 +.set CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE, 0x00000001 +.set CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED, 0x00000000 +.set CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED, 0x00000001 +.set CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET, 0x00000003 +.set CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE, 0x00000001 +.set CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED, 0x00000000 +.set CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED, 0x00000001 +.set CYFLD_SAR_AVG_CNT__OFFSET, 0x00000004 +.set CYFLD_SAR_AVG_CNT__SIZE, 0x00000003 +.set CYFLD_SAR_AVG_SHIFT__OFFSET, 0x00000007 +.set CYFLD_SAR_AVG_SHIFT__SIZE, 0x00000001 +.set CYFLD_SAR_CONTINUOUS__OFFSET, 0x00000010 +.set CYFLD_SAR_CONTINUOUS__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_TRIGGER_EN__OFFSET, 0x00000011 +.set CYFLD_SAR_DSI_TRIGGER_EN__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET, 0x00000012 +.set CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET, 0x00000013 +.set CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE, 0x00000001 +.set CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET, 0x0000001f +.set CYFLD_SAR_EOS_DSI_OUT_EN__SIZE, 0x00000001 +.set CYREG_SAR_SAMPLE_TIME01, 0x403a0010 +.set CYFLD_SAR_SAMPLE_TIME0__OFFSET, 0x00000000 +.set CYFLD_SAR_SAMPLE_TIME0__SIZE, 0x0000000a +.set CYFLD_SAR_SAMPLE_TIME1__OFFSET, 0x00000010 +.set CYFLD_SAR_SAMPLE_TIME1__SIZE, 0x0000000a +.set CYREG_SAR_SAMPLE_TIME23, 0x403a0014 +.set CYFLD_SAR_SAMPLE_TIME2__OFFSET, 0x00000000 +.set CYFLD_SAR_SAMPLE_TIME2__SIZE, 0x0000000a +.set CYFLD_SAR_SAMPLE_TIME3__OFFSET, 0x00000010 +.set CYFLD_SAR_SAMPLE_TIME3__SIZE, 0x0000000a +.set CYREG_SAR_RANGE_THRES, 0x403a0018 +.set CYFLD_SAR_RANGE_LOW__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_LOW__SIZE, 0x00000010 +.set CYFLD_SAR_RANGE_HIGH__OFFSET, 0x00000010 +.set CYFLD_SAR_RANGE_HIGH__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_COND, 0x403a001c +.set CYFLD_SAR_RANGE_COND__OFFSET, 0x0000001e +.set CYFLD_SAR_RANGE_COND__SIZE, 0x00000002 +.set CYVAL_SAR_RANGE_COND_BELOW, 0x00000000 +.set CYVAL_SAR_RANGE_COND_INSIDE, 0x00000001 +.set CYVAL_SAR_RANGE_COND_ABOVE, 0x00000002 +.set CYVAL_SAR_RANGE_COND_OUTSIDE, 0x00000003 +.set CYREG_SAR_CHAN_EN, 0x403a0020 +.set CYFLD_SAR_CHAN_EN__OFFSET, 0x00000000 +.set CYFLD_SAR_CHAN_EN__SIZE, 0x00000010 +.set CYREG_SAR_START_CTRL, 0x403a0024 +.set CYFLD_SAR_FW_TRIGGER__OFFSET, 0x00000000 +.set CYFLD_SAR_FW_TRIGGER__SIZE, 0x00000001 +.set CYREG_SAR_DFT_CTRL, 0x403a0030 +.set CYFLD_SAR_DLY_INC__OFFSET, 0x00000000 +.set CYFLD_SAR_DLY_INC__SIZE, 0x00000001 +.set CYFLD_SAR_HIZ__OFFSET, 0x00000001 +.set CYFLD_SAR_HIZ__SIZE, 0x00000001 +.set CYFLD_SAR_DFT_INC__OFFSET, 0x00000010 +.set CYFLD_SAR_DFT_INC__SIZE, 0x00000004 +.set CYFLD_SAR_DFT_OUTC__OFFSET, 0x00000014 +.set CYFLD_SAR_DFT_OUTC__SIZE, 0x00000003 +.set CYFLD_SAR_SEL_CSEL_DFT__OFFSET, 0x00000018 +.set CYFLD_SAR_SEL_CSEL_DFT__SIZE, 0x00000004 +.set CYFLD_SAR_EN_CSEL_DFT__OFFSET, 0x0000001c +.set CYFLD_SAR_EN_CSEL_DFT__SIZE, 0x00000001 +.set CYFLD_SAR_DCEN__OFFSET, 0x0000001d +.set CYFLD_SAR_DCEN__SIZE, 0x00000001 +.set CYFLD_SAR_ADFT_OVERRIDE__OFFSET, 0x0000001f +.set CYFLD_SAR_ADFT_OVERRIDE__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_CONFIG0, 0x403a0080 +.set CYFLD_SAR_PIN_ADDR__OFFSET, 0x00000000 +.set CYFLD_SAR_PIN_ADDR__SIZE, 0x00000003 +.set CYFLD_SAR_PORT_ADDR__OFFSET, 0x00000004 +.set CYFLD_SAR_PORT_ADDR__SIZE, 0x00000003 +.set CYVAL_SAR_PORT_ADDR_SARMUX, 0x00000000 +.set CYVAL_SAR_PORT_ADDR_CTB0, 0x00000001 +.set CYVAL_SAR_PORT_ADDR_CTB1, 0x00000002 +.set CYVAL_SAR_PORT_ADDR_CTB2, 0x00000003 +.set CYVAL_SAR_PORT_ADDR_CTB3, 0x00000004 +.set CYVAL_SAR_PORT_ADDR_AROUTE_VIRT2, 0x00000005 +.set CYVAL_SAR_PORT_ADDR_AROUTE_VIRT1, 0x00000006 +.set CYVAL_SAR_PORT_ADDR_SARMUX_VIRT, 0x00000007 +.set CYFLD_SAR_DIFFERENTIAL_EN__OFFSET, 0x00000008 +.set CYFLD_SAR_DIFFERENTIAL_EN__SIZE, 0x00000001 +.set CYFLD_SAR_RESOLUTION__OFFSET, 0x00000009 +.set CYFLD_SAR_RESOLUTION__SIZE, 0x00000001 +.set CYVAL_SAR_RESOLUTION_MAXRES, 0x00000000 +.set CYVAL_SAR_RESOLUTION_SUBRES, 0x00000001 +.set CYFLD_SAR_AVG_EN__OFFSET, 0x0000000a +.set CYFLD_SAR_AVG_EN__SIZE, 0x00000001 +.set CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET, 0x0000000c +.set CYFLD_SAR_SAMPLE_TIME_SEL__SIZE, 0x00000002 +.set CYFLD_SAR_DSI_OUT_EN__OFFSET, 0x0000001f +.set CYFLD_SAR_DSI_OUT_EN__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_CONFIG1, 0x403a0084 +.set CYREG_SAR_CHAN_CONFIG2, 0x403a0088 +.set CYREG_SAR_CHAN_CONFIG3, 0x403a008c +.set CYREG_SAR_CHAN_CONFIG4, 0x403a0090 +.set CYREG_SAR_CHAN_CONFIG5, 0x403a0094 +.set CYREG_SAR_CHAN_CONFIG6, 0x403a0098 +.set CYREG_SAR_CHAN_CONFIG7, 0x403a009c +.set CYREG_SAR_CHAN_CONFIG8, 0x403a00a0 +.set CYREG_SAR_CHAN_CONFIG9, 0x403a00a4 +.set CYREG_SAR_CHAN_CONFIG10, 0x403a00a8 +.set CYREG_SAR_CHAN_CONFIG11, 0x403a00ac +.set CYREG_SAR_CHAN_CONFIG12, 0x403a00b0 +.set CYREG_SAR_CHAN_CONFIG13, 0x403a00b4 +.set CYREG_SAR_CHAN_CONFIG14, 0x403a00b8 +.set CYREG_SAR_CHAN_CONFIG15, 0x403a00bc +.set CYREG_SAR_CHAN_WORK0, 0x403a0100 +.set CYFLD_SAR_WORK__OFFSET, 0x00000000 +.set CYFLD_SAR_WORK__SIZE, 0x00000010 +.set CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET, 0x0000001f +.set CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_WORK1, 0x403a0104 +.set CYREG_SAR_CHAN_WORK2, 0x403a0108 +.set CYREG_SAR_CHAN_WORK3, 0x403a010c +.set CYREG_SAR_CHAN_WORK4, 0x403a0110 +.set CYREG_SAR_CHAN_WORK5, 0x403a0114 +.set CYREG_SAR_CHAN_WORK6, 0x403a0118 +.set CYREG_SAR_CHAN_WORK7, 0x403a011c +.set CYREG_SAR_CHAN_WORK8, 0x403a0120 +.set CYREG_SAR_CHAN_WORK9, 0x403a0124 +.set CYREG_SAR_CHAN_WORK10, 0x403a0128 +.set CYREG_SAR_CHAN_WORK11, 0x403a012c +.set CYREG_SAR_CHAN_WORK12, 0x403a0130 +.set CYREG_SAR_CHAN_WORK13, 0x403a0134 +.set CYREG_SAR_CHAN_WORK14, 0x403a0138 +.set CYREG_SAR_CHAN_WORK15, 0x403a013c +.set CYREG_SAR_CHAN_RESULT0, 0x403a0180 +.set CYFLD_SAR_RESULT__OFFSET, 0x00000000 +.set CYFLD_SAR_RESULT__SIZE, 0x00000010 +.set CYFLD_SAR_SATURATE_INTR_MIR__OFFSET, 0x0000001d +.set CYFLD_SAR_SATURATE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_RANGE_INTR_MIR__OFFSET, 0x0000001e +.set CYFLD_SAR_RANGE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET, 0x0000001f +.set CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE, 0x00000001 +.set CYREG_SAR_CHAN_RESULT1, 0x403a0184 +.set CYREG_SAR_CHAN_RESULT2, 0x403a0188 +.set CYREG_SAR_CHAN_RESULT3, 0x403a018c +.set CYREG_SAR_CHAN_RESULT4, 0x403a0190 +.set CYREG_SAR_CHAN_RESULT5, 0x403a0194 +.set CYREG_SAR_CHAN_RESULT6, 0x403a0198 +.set CYREG_SAR_CHAN_RESULT7, 0x403a019c +.set CYREG_SAR_CHAN_RESULT8, 0x403a01a0 +.set CYREG_SAR_CHAN_RESULT9, 0x403a01a4 +.set CYREG_SAR_CHAN_RESULT10, 0x403a01a8 +.set CYREG_SAR_CHAN_RESULT11, 0x403a01ac +.set CYREG_SAR_CHAN_RESULT12, 0x403a01b0 +.set CYREG_SAR_CHAN_RESULT13, 0x403a01b4 +.set CYREG_SAR_CHAN_RESULT14, 0x403a01b8 +.set CYREG_SAR_CHAN_RESULT15, 0x403a01bc +.set CYREG_SAR_CHAN_WORK_VALID, 0x403a0200 +.set CYFLD_SAR_CHAN_WORK_VALID__OFFSET, 0x00000000 +.set CYFLD_SAR_CHAN_WORK_VALID__SIZE, 0x00000010 +.set CYREG_SAR_CHAN_RESULT_VALID, 0x403a0204 +.set CYFLD_SAR_CHAN_RESULT_VALID__OFFSET, 0x00000000 +.set CYFLD_SAR_CHAN_RESULT_VALID__SIZE, 0x00000010 +.set CYREG_SAR_STATUS, 0x403a0208 +.set CYFLD_SAR_CUR_CHAN__OFFSET, 0x00000000 +.set CYFLD_SAR_CUR_CHAN__SIZE, 0x00000005 +.set CYFLD_SAR_SW_VREF_NEG__OFFSET, 0x0000001e +.set CYFLD_SAR_SW_VREF_NEG__SIZE, 0x00000001 +.set CYFLD_SAR_BUSY__OFFSET, 0x0000001f +.set CYFLD_SAR_BUSY__SIZE, 0x00000001 +.set CYREG_SAR_AVG_STAT, 0x403a020c +.set CYFLD_SAR_CUR_AVG_ACCU__OFFSET, 0x00000000 +.set CYFLD_SAR_CUR_AVG_ACCU__SIZE, 0x00000014 +.set CYFLD_SAR_CUR_AVG_CNT__OFFSET, 0x00000018 +.set CYFLD_SAR_CUR_AVG_CNT__SIZE, 0x00000008 +.set CYREG_SAR_INTR, 0x403a0210 +.set CYFLD_SAR_EOS_INTR__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_INTR__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_INTR__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_INTR__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_INTR__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_INTR__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_INTR__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_INTR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_INTR__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_INTR__SIZE, 0x00000001 +.set CYREG_SAR_INTR_SET, 0x403a0214 +.set CYFLD_SAR_EOS_SET__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_SET__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_SET__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_SET__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_SET__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_SET__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_SET__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_SET__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_SET__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_SET__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_SET__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_SET__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_SET__SIZE, 0x00000001 +.set CYREG_SAR_INTR_MASK, 0x403a0218 +.set CYFLD_SAR_EOS_MASK__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASK__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_MASK__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_MASK__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_MASK__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_MASK__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_MASK__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_MASK__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_MASK__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_MASK__SIZE, 0x00000001 +.set CYREG_SAR_INTR_MASKED, 0x403a021c +.set CYFLD_SAR_EOS_MASKED__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_MASKED__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_MASKED__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_MASKED__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_MASKED__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_MASKED__SIZE, 0x00000001 +.set CYREG_SAR_SATURATE_INTR, 0x403a0220 +.set CYFLD_SAR_SATURATE_INTR__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_INTR__SIZE, 0x00000010 +.set CYREG_SAR_SATURATE_INTR_SET, 0x403a0224 +.set CYFLD_SAR_SATURATE_SET__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_SET__SIZE, 0x00000010 +.set CYREG_SAR_SATURATE_INTR_MASK, 0x403a0228 +.set CYFLD_SAR_SATURATE_MASK__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_MASK__SIZE, 0x00000010 +.set CYREG_SAR_SATURATE_INTR_MASKED, 0x403a022c +.set CYFLD_SAR_SATURATE_MASKED__OFFSET, 0x00000000 +.set CYFLD_SAR_SATURATE_MASKED__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR, 0x403a0230 +.set CYFLD_SAR_RANGE_INTR__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_INTR__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR_SET, 0x403a0234 +.set CYFLD_SAR_RANGE_SET__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_SET__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR_MASK, 0x403a0238 +.set CYFLD_SAR_RANGE_MASK__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_MASK__SIZE, 0x00000010 +.set CYREG_SAR_RANGE_INTR_MASKED, 0x403a023c +.set CYFLD_SAR_RANGE_MASKED__OFFSET, 0x00000000 +.set CYFLD_SAR_RANGE_MASKED__SIZE, 0x00000010 +.set CYREG_SAR_INTR_CAUSE, 0x403a0240 +.set CYFLD_SAR_EOS_MASKED_MIR__OFFSET, 0x00000000 +.set CYFLD_SAR_EOS_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET, 0x00000001 +.set CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET, 0x00000002 +.set CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET, 0x00000003 +.set CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET, 0x00000005 +.set CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET, 0x00000006 +.set CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET, 0x00000007 +.set CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_SATURATE_MASKED_RED__OFFSET, 0x0000001e +.set CYFLD_SAR_SATURATE_MASKED_RED__SIZE, 0x00000001 +.set CYFLD_SAR_RANGE_MASKED_RED__OFFSET, 0x0000001f +.set CYFLD_SAR_RANGE_MASKED_RED__SIZE, 0x00000001 +.set CYREG_SAR_INJ_CHAN_CONFIG, 0x403a0280 +.set CYFLD_SAR_INJ_PIN_ADDR__OFFSET, 0x00000000 +.set CYFLD_SAR_INJ_PIN_ADDR__SIZE, 0x00000003 +.set CYFLD_SAR_INJ_PORT_ADDR__OFFSET, 0x00000004 +.set CYFLD_SAR_INJ_PORT_ADDR__SIZE, 0x00000003 +.set CYVAL_SAR_INJ_PORT_ADDR_SARMUX, 0x00000000 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB0, 0x00000001 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB1, 0x00000002 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB2, 0x00000003 +.set CYVAL_SAR_INJ_PORT_ADDR_CTB3, 0x00000004 +.set CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT, 0x00000006 +.set CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT, 0x00000007 +.set CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET, 0x00000008 +.set CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RESOLUTION__OFFSET, 0x00000009 +.set CYFLD_SAR_INJ_RESOLUTION__SIZE, 0x00000001 +.set CYVAL_SAR_INJ_RESOLUTION_12B, 0x00000000 +.set CYVAL_SAR_INJ_RESOLUTION_SUBRES, 0x00000001 +.set CYFLD_SAR_INJ_AVG_EN__OFFSET, 0x0000000a +.set CYFLD_SAR_INJ_AVG_EN__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET, 0x0000000c +.set CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE, 0x00000002 +.set CYFLD_SAR_INJ_TAILGATING__OFFSET, 0x0000001e +.set CYFLD_SAR_INJ_TAILGATING__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_START_EN__OFFSET, 0x0000001f +.set CYFLD_SAR_INJ_START_EN__SIZE, 0x00000001 +.set CYREG_SAR_INJ_RESULT, 0x403a0290 +.set CYFLD_SAR_INJ_RESULT__OFFSET, 0x00000000 +.set CYFLD_SAR_INJ_RESULT__SIZE, 0x00000010 +.set CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET, 0x0000001c +.set CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET, 0x0000001d +.set CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET, 0x0000001e +.set CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE, 0x00000001 +.set CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET, 0x0000001f +.set CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH0, 0x403a0300 +.set CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET, 0x00000000 +.set CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET, 0x00000001 +.set CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET, 0x00000002 +.set CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET, 0x00000003 +.set CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET, 0x00000004 +.set CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET, 0x00000005 +.set CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET, 0x00000006 +.set CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET, 0x00000007 +.set CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET, 0x00000008 +.set CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET, 0x00000009 +.set CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET, 0x0000000a +.set CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET, 0x0000000b +.set CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET, 0x0000000c +.set CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET, 0x0000000d +.set CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET, 0x0000000e +.set CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET, 0x0000000f +.set CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET, 0x00000010 +.set CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET, 0x00000011 +.set CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET, 0x00000012 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET, 0x00000013 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET, 0x00000014 +.set CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET, 0x00000015 +.set CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET, 0x00000016 +.set CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET, 0x00000017 +.set CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET, 0x00000018 +.set CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET, 0x00000019 +.set CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET, 0x0000001a +.set CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET, 0x0000001b +.set CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET, 0x0000001c +.set CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET, 0x0000001d +.set CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH_CLEAR0, 0x403a0304 +.set CYREG_SAR_MUX_SWITCH1, 0x403a0308 +.set CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET, 0x00000000 +.set CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET, 0x00000001 +.set CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET, 0x00000002 +.set CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET, 0x00000003 +.set CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH_CLEAR1, 0x403a030c +.set CYREG_SAR_MUX_SWITCH_HW_CTRL, 0x403a0340 +.set CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET, 0x00000000 +.set CYFLD_SAR_MUX_HW_CTRL_P0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P1__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET, 0x00000002 +.set CYFLD_SAR_MUX_HW_CTRL_P2__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET, 0x00000003 +.set CYFLD_SAR_MUX_HW_CTRL_P3__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET, 0x00000004 +.set CYFLD_SAR_MUX_HW_CTRL_P4__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET, 0x00000005 +.set CYFLD_SAR_MUX_HW_CTRL_P5__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET, 0x00000006 +.set CYFLD_SAR_MUX_HW_CTRL_P6__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET, 0x00000007 +.set CYFLD_SAR_MUX_HW_CTRL_P7__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET, 0x00000010 +.set CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET, 0x00000011 +.set CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET, 0x00000012 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET, 0x00000013 +.set CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET, 0x00000016 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE, 0x00000001 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET, 0x00000017 +.set CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE, 0x00000001 +.set CYREG_SAR_MUX_SWITCH_STATUS, 0x403a0348 +.set CYREG_SAR_PUMP_CTRL, 0x403a0380 +.set CYFLD_SAR_CLOCK_SEL__OFFSET, 0x00000000 +.set CYFLD_SAR_CLOCK_SEL__SIZE, 0x00000001 +.set CYREG_SAR_ANA_TRIM, 0x403a0f00 +.set CYFLD_SAR_CAP_TRIM__OFFSET, 0x00000000 +.set CYFLD_SAR_CAP_TRIM__SIZE, 0x00000003 +.set CYFLD_SAR_TRIMUNIT__OFFSET, 0x00000003 +.set CYFLD_SAR_TRIMUNIT__SIZE, 0x00000001 +.set CYREG_SAR_WOUNDING, 0x403a0f04 +.set CYFLD_SAR_WOUND_RESOLUTION__OFFSET, 0x00000000 +.set CYFLD_SAR_WOUND_RESOLUTION__SIZE, 0x00000002 +.set CYVAL_SAR_WOUND_RESOLUTION_12BIT, 0x00000000 +.set CYVAL_SAR_WOUND_RESOLUTION_10BIT, 0x00000001 +.set CYVAL_SAR_WOUND_RESOLUTION_8BIT, 0x00000002 +.set CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO, 0x00000003 +.set CYDEV_PASS_BASE, 0x403f0000 +.set CYDEV_PASS_SIZE, 0x00010000 +.set CYREG_PASS_INTR_CAUSE, 0x403f0000 +.set CYFLD_PASS_CTB0_INT__OFFSET, 0x00000000 +.set CYFLD_PASS_CTB0_INT__SIZE, 0x00000001 +.set CYREG_PASS_DFT_CTRL, 0x403f0030 +.set CYFLD_PASS_DSAB_ADFT_RES_EN__OFFSET, 0x00000000 +.set CYFLD_PASS_DSAB_ADFT_RES_EN__SIZE, 0x00000001 +.set CYREG_PASS_PASS_CTRL, 0x403f0108 +.set CYFLD_PASS_PMPCLK_BYP__OFFSET, 0x00000000 +.set CYFLD_PASS_PMPCLK_BYP__SIZE, 0x00000001 +.set CYFLD_PASS_PMPCLK_SRC__OFFSET, 0x00000001 +.set CYFLD_PASS_PMPCLK_SRC__SIZE, 0x00000001 +.set CYFLD_PASS_RMB_BITS__OFFSET, 0x00000008 +.set CYFLD_PASS_RMB_BITS__SIZE, 0x00000008 +.set CYDEV_PASS_DSAB_BASE, 0x403f0e00 +.set CYDEV_PASS_DSAB_SIZE, 0x00000100 +.set CYREG_PASS_DSAB_DSAB_CTRL, 0x403f0e00 +.set CYFLD_PASS_DSAB_CURRENT_SEL__OFFSET, 0x00000000 +.set CYFLD_PASS_DSAB_CURRENT_SEL__SIZE, 0x00000006 +.set CYFLD_PASS_DSAB_SEL_OUT__OFFSET, 0x00000008 +.set CYFLD_PASS_DSAB_SEL_OUT__SIZE, 0x00000004 +.set CYFLD_PASS_DSAB_REF_SWAP_EN__OFFSET, 0x00000010 +.set CYFLD_PASS_DSAB_REF_SWAP_EN__SIZE, 0x00000004 +.set CYFLD_PASS_DSAB_BYPASS_MODE_EN__OFFSET, 0x00000018 +.set CYFLD_PASS_DSAB_BYPASS_MODE_EN__SIZE, 0x00000001 +.set CYFLD_PASS_DSAB_STARTUP_RM__OFFSET, 0x0000001c +.set CYFLD_PASS_DSAB_STARTUP_RM__SIZE, 0x00000001 +.set CYFLD_PASS_DSAB_ENABLED__OFFSET, 0x0000001f +.set CYFLD_PASS_DSAB_ENABLED__SIZE, 0x00000001 +.set CYREG_PASS_DSAB_DSAB_DFT, 0x403f0e04 +.set CYFLD_PASS_DSAB_EN_DFT__OFFSET, 0x00000000 +.set CYFLD_PASS_DSAB_EN_DFT__SIZE, 0x00000004 +.set CYREG_PASS_DSAB_TRIM, 0x403f0f00 +.set CYFLD_PASS_IBIAS_TRIM__OFFSET, 0x00000000 +.set CYFLD_PASS_IBIAS_TRIM__SIZE, 0x00000004 +.set CYFLD_PASS_DSAB_RMB_BITS__OFFSET, 0x00000004 +.set CYFLD_PASS_DSAB_RMB_BITS__SIZE, 0x00000002 +.set CYDEV_CM0P_BASE, 0xe0000000 +.set CYDEV_CM0P_SIZE, 0x00100000 +.set CYREG_CM0P_DWT_PID4, 0xe0001fd0 +.set CYFLD_CM0P_VALUE__OFFSET, 0x00000000 +.set CYFLD_CM0P_VALUE__SIZE, 0x00000020 +.set CYREG_CM0P_DWT_PID0, 0xe0001fe0 +.set CYREG_CM0P_DWT_PID1, 0xe0001fe4 +.set CYREG_CM0P_DWT_PID2, 0xe0001fe8 +.set CYREG_CM0P_DWT_PID3, 0xe0001fec +.set CYREG_CM0P_DWT_CID0, 0xe0001ff0 +.set CYREG_CM0P_DWT_CID1, 0xe0001ff4 +.set CYREG_CM0P_DWT_CID2, 0xe0001ff8 +.set CYREG_CM0P_DWT_CID3, 0xe0001ffc +.set CYREG_CM0P_BP_PID4, 0xe0002fd0 +.set CYREG_CM0P_BP_PID0, 0xe0002fe0 +.set CYREG_CM0P_BP_PID1, 0xe0002fe4 +.set CYREG_CM0P_BP_PID2, 0xe0002fe8 +.set CYREG_CM0P_BP_PID3, 0xe0002fec +.set CYREG_CM0P_BP_CID0, 0xe0002ff0 +.set CYREG_CM0P_BP_CID1, 0xe0002ff4 +.set CYREG_CM0P_BP_CID2, 0xe0002ff8 +.set CYREG_CM0P_BP_CID3, 0xe0002ffc +.set CYREG_CM0P_SYST_CSR, 0xe000e010 +.set CYFLD_CM0P_ENABLE__OFFSET, 0x00000000 +.set CYFLD_CM0P_ENABLE__SIZE, 0x00000001 +.set CYFLD_CM0P_TICKINT__OFFSET, 0x00000001 +.set CYFLD_CM0P_TICKINT__SIZE, 0x00000001 +.set CYFLD_CM0P_CLKSOURCE__OFFSET, 0x00000002 +.set CYFLD_CM0P_CLKSOURCE__SIZE, 0x00000001 +.set CYFLD_CM0P_COUNTFLAG__OFFSET, 0x00000010 +.set CYFLD_CM0P_COUNTFLAG__SIZE, 0x00000001 +.set CYREG_CM0P_SYST_RVR, 0xe000e014 +.set CYFLD_CM0P_RELOAD__OFFSET, 0x00000000 +.set CYFLD_CM0P_RELOAD__SIZE, 0x00000018 +.set CYREG_CM0P_SYST_CVR, 0xe000e018 +.set CYFLD_CM0P_CURRENT__OFFSET, 0x00000000 +.set CYFLD_CM0P_CURRENT__SIZE, 0x00000018 +.set CYREG_CM0P_SYST_CALIB, 0xe000e01c +.set CYFLD_CM0P_TENMS__OFFSET, 0x00000000 +.set CYFLD_CM0P_TENMS__SIZE, 0x00000018 +.set CYFLD_CM0P_SKEW__OFFSET, 0x0000001e +.set CYFLD_CM0P_SKEW__SIZE, 0x00000001 +.set CYFLD_CM0P_NOREF__OFFSET, 0x0000001f +.set CYFLD_CM0P_NOREF__SIZE, 0x00000001 +.set CYREG_CM0P_ISER, 0xe000e100 +.set CYFLD_CM0P_SETENA__OFFSET, 0x00000000 +.set CYFLD_CM0P_SETENA__SIZE, 0x00000020 +.set CYREG_CM0P_ICER, 0xe000e180 +.set CYFLD_CM0P_CLRENA__OFFSET, 0x00000000 +.set CYFLD_CM0P_CLRENA__SIZE, 0x00000020 +.set CYREG_CM0P_ISPR, 0xe000e200 +.set CYFLD_CM0P_SETPEND__OFFSET, 0x00000000 +.set CYFLD_CM0P_SETPEND__SIZE, 0x00000020 +.set CYREG_CM0P_ICPR, 0xe000e280 +.set CYFLD_CM0P_CLRPEND__OFFSET, 0x00000000 +.set CYFLD_CM0P_CLRPEND__SIZE, 0x00000020 +.set CYREG_CM0P_IPR0, 0xe000e400 +.set CYFLD_CM0P_PRI_N0__OFFSET, 0x00000006 +.set CYFLD_CM0P_PRI_N0__SIZE, 0x00000002 +.set CYFLD_CM0P_PRI_N1__OFFSET, 0x0000000e +.set CYFLD_CM0P_PRI_N1__SIZE, 0x00000002 +.set CYFLD_CM0P_PRI_N2__OFFSET, 0x00000016 +.set CYFLD_CM0P_PRI_N2__SIZE, 0x00000002 +.set CYFLD_CM0P_PRI_N3__OFFSET, 0x0000001e +.set CYFLD_CM0P_PRI_N3__SIZE, 0x00000002 +.set CYREG_CM0P_IPR1, 0xe000e404 +.set CYREG_CM0P_IPR2, 0xe000e408 +.set CYREG_CM0P_IPR3, 0xe000e40c +.set CYREG_CM0P_IPR4, 0xe000e410 +.set CYREG_CM0P_IPR5, 0xe000e414 +.set CYREG_CM0P_IPR6, 0xe000e418 +.set CYREG_CM0P_IPR7, 0xe000e41c +.set CYREG_CM0P_CPUID, 0xe000ed00 +.set CYFLD_CM0P_REVISION__OFFSET, 0x00000000 +.set CYFLD_CM0P_REVISION__SIZE, 0x00000004 +.set CYFLD_CM0P_PARTNO__OFFSET, 0x00000004 +.set CYFLD_CM0P_PARTNO__SIZE, 0x0000000c +.set CYFLD_CM0P_CONSTANT__OFFSET, 0x00000010 +.set CYFLD_CM0P_CONSTANT__SIZE, 0x00000004 +.set CYFLD_CM0P_VARIANT__OFFSET, 0x00000014 +.set CYFLD_CM0P_VARIANT__SIZE, 0x00000004 +.set CYFLD_CM0P_IMPLEMENTER__OFFSET, 0x00000018 +.set CYFLD_CM0P_IMPLEMENTER__SIZE, 0x00000008 +.set CYREG_CM0P_ICSR, 0xe000ed04 +.set CYFLD_CM0P_VECTACTIVE__OFFSET, 0x00000000 +.set CYFLD_CM0P_VECTACTIVE__SIZE, 0x00000009 +.set CYFLD_CM0P_VECTPENDING__OFFSET, 0x0000000c +.set CYFLD_CM0P_VECTPENDING__SIZE, 0x00000009 +.set CYFLD_CM0P_ISRPENDING__OFFSET, 0x00000016 +.set CYFLD_CM0P_ISRPENDING__SIZE, 0x00000001 +.set CYFLD_CM0P_ISRPREEMPT__OFFSET, 0x00000017 +.set CYFLD_CM0P_ISRPREEMPT__SIZE, 0x00000001 +.set CYFLD_CM0P_PENDSTCLR__OFFSET, 0x00000019 +.set CYFLD_CM0P_PENDSTCLR__SIZE, 0x00000001 +.set CYFLD_CM0P_PENDSTSETb__OFFSET, 0x0000001a +.set CYFLD_CM0P_PENDSTSETb__SIZE, 0x00000001 +.set CYFLD_CM0P_PENDSVCLR__OFFSET, 0x0000001b +.set CYFLD_CM0P_PENDSVCLR__SIZE, 0x00000001 +.set CYFLD_CM0P_PENDSVSET__OFFSET, 0x0000001c +.set CYFLD_CM0P_PENDSVSET__SIZE, 0x00000001 +.set CYFLD_CM0P_NMIPENDSET__OFFSET, 0x0000001f +.set CYFLD_CM0P_NMIPENDSET__SIZE, 0x00000001 +.set CYREG_CM0P_VTOR, 0xe000ed08 +.set CYFLD_CM0P_TBLOFF__OFFSET, 0x00000008 +.set CYFLD_CM0P_TBLOFF__SIZE, 0x00000018 +.set CYREG_CM0P_AIRCR, 0xe000ed0c +.set CYFLD_CM0P_VECTCLRACTIVE__OFFSET, 0x00000001 +.set CYFLD_CM0P_VECTCLRACTIVE__SIZE, 0x00000001 +.set CYFLD_CM0P_SYSRESETREQ__OFFSET, 0x00000002 +.set CYFLD_CM0P_SYSRESETREQ__SIZE, 0x00000001 +.set CYFLD_CM0P_ENDIANNESS__OFFSET, 0x0000000f +.set CYFLD_CM0P_ENDIANNESS__SIZE, 0x00000001 +.set CYFLD_CM0P_VECTKEY__OFFSET, 0x00000010 +.set CYFLD_CM0P_VECTKEY__SIZE, 0x00000010 +.set CYREG_CM0P_SCR, 0xe000ed10 +.set CYFLD_CM0P_SLEEPONEXIT__OFFSET, 0x00000001 +.set CYFLD_CM0P_SLEEPONEXIT__SIZE, 0x00000001 +.set CYFLD_CM0P_SLEEPDEEP__OFFSET, 0x00000002 +.set CYFLD_CM0P_SLEEPDEEP__SIZE, 0x00000001 +.set CYFLD_CM0P_SEVONPEND__OFFSET, 0x00000004 +.set CYFLD_CM0P_SEVONPEND__SIZE, 0x00000001 +.set CYREG_CM0P_CCR, 0xe000ed14 +.set CYFLD_CM0P_UNALIGN_TRP__OFFSET, 0x00000003 +.set CYFLD_CM0P_UNALIGN_TRP__SIZE, 0x00000001 +.set CYFLD_CM0P_STKALIGN__OFFSET, 0x00000009 +.set CYFLD_CM0P_STKALIGN__SIZE, 0x00000001 +.set CYREG_CM0P_SHPR2, 0xe000ed1c +.set CYFLD_CM0P_PRI_11__OFFSET, 0x0000001e +.set CYFLD_CM0P_PRI_11__SIZE, 0x00000002 +.set CYREG_CM0P_SHPR3, 0xe000ed20 +.set CYFLD_CM0P_PRI_14__OFFSET, 0x00000016 +.set CYFLD_CM0P_PRI_14__SIZE, 0x00000002 +.set CYFLD_CM0P_PRI_15__OFFSET, 0x0000001e +.set CYFLD_CM0P_PRI_15__SIZE, 0x00000002 +.set CYREG_CM0P_SHCSR, 0xe000ed24 +.set CYFLD_CM0P_SVCALLPENDED__OFFSET, 0x0000000f +.set CYFLD_CM0P_SVCALLPENDED__SIZE, 0x00000001 +.set CYREG_CM0P_SCS_PID4, 0xe000efd0 +.set CYREG_CM0P_SCS_PID0, 0xe000efe0 +.set CYREG_CM0P_SCS_PID1, 0xe000efe4 +.set CYREG_CM0P_SCS_PID2, 0xe000efe8 +.set CYREG_CM0P_SCS_PID3, 0xe000efec +.set CYREG_CM0P_SCS_CID0, 0xe000eff0 +.set CYREG_CM0P_SCS_CID1, 0xe000eff4 +.set CYREG_CM0P_SCS_CID2, 0xe000eff8 +.set CYREG_CM0P_SCS_CID3, 0xe000effc +.set CYREG_CM0P_ROM_SCS, 0xe00ff000 +.set CYREG_CM0P_ROM_DWT, 0xe00ff004 +.set CYREG_CM0P_ROM_BPU, 0xe00ff008 +.set CYREG_CM0P_ROM_END, 0xe00ff00c +.set CYREG_CM0P_ROM_CSMT, 0xe00fffcc +.set CYREG_CM0P_ROM_PID4, 0xe00fffd0 +.set CYREG_CM0P_ROM_PID0, 0xe00fffe0 +.set CYREG_CM0P_ROM_PID1, 0xe00fffe4 +.set CYREG_CM0P_ROM_PID2, 0xe00fffe8 +.set CYREG_CM0P_ROM_PID3, 0xe00fffec +.set CYREG_CM0P_ROM_CID0, 0xe00ffff0 +.set CYREG_CM0P_ROM_CID1, 0xe00ffff4 +.set CYREG_CM0P_ROM_CID2, 0xe00ffff8 +.set CYREG_CM0P_ROM_CID3, 0xe00ffffc +.set CYDEV_ROMTABLE_BASE, 0xf0000000 +.set CYDEV_ROMTABLE_SIZE, 0x00001000 +.set CYREG_ROMTABLE_ADDR, 0xf0000000 +.set CYFLD_ROMTABLE_PRESENT__OFFSET, 0x00000000 +.set CYFLD_ROMTABLE_PRESENT__SIZE, 0x00000001 +.set CYFLD_ROMTABLE_FORMAT_32BIT__OFFSET, 0x00000001 +.set CYFLD_ROMTABLE_FORMAT_32BIT__SIZE, 0x00000001 +.set CYFLD_ROMTABLE_ADDR_OFFSET__OFFSET, 0x0000000c +.set CYFLD_ROMTABLE_ADDR_OFFSET__SIZE, 0x00000014 +.set CYREG_ROMTABLE_DID, 0xf0000fcc +.set CYFLD_ROMTABLE_VALUE__OFFSET, 0x00000000 +.set CYFLD_ROMTABLE_VALUE__SIZE, 0x00000020 +.set CYREG_ROMTABLE_PID4, 0xf0000fd0 +.set CYFLD_ROMTABLE_JEP_CONTINUATION__OFFSET, 0x00000000 +.set CYFLD_ROMTABLE_JEP_CONTINUATION__SIZE, 0x00000004 +.set CYFLD_ROMTABLE_COUNT__OFFSET, 0x00000004 +.set CYFLD_ROMTABLE_COUNT__SIZE, 0x00000004 +.set CYREG_ROMTABLE_PID5, 0xf0000fd4 +.set CYREG_ROMTABLE_PID6, 0xf0000fd8 +.set CYREG_ROMTABLE_PID7, 0xf0000fdc +.set CYREG_ROMTABLE_PID0, 0xf0000fe0 +.set CYFLD_ROMTABLE_PN_MIN__OFFSET, 0x00000000 +.set CYFLD_ROMTABLE_PN_MIN__SIZE, 0x00000008 +.set CYREG_ROMTABLE_PID1, 0xf0000fe4 +.set CYFLD_ROMTABLE_PN_MAJ__OFFSET, 0x00000000 +.set CYFLD_ROMTABLE_PN_MAJ__SIZE, 0x00000004 +.set CYFLD_ROMTABLE_JEPID_MIN__OFFSET, 0x00000004 +.set CYFLD_ROMTABLE_JEPID_MIN__SIZE, 0x00000004 +.set CYREG_ROMTABLE_PID2, 0xf0000fe8 +.set CYFLD_ROMTABLE_JEPID_MAJ__OFFSET, 0x00000000 +.set CYFLD_ROMTABLE_JEPID_MAJ__SIZE, 0x00000003 +.set CYFLD_ROMTABLE_REV__OFFSET, 0x00000004 +.set CYFLD_ROMTABLE_REV__SIZE, 0x00000004 +.set CYREG_ROMTABLE_PID3, 0xf0000fec +.set CYFLD_ROMTABLE_CM__OFFSET, 0x00000000 +.set CYFLD_ROMTABLE_CM__SIZE, 0x00000004 +.set CYFLD_ROMTABLE_REV_AND__OFFSET, 0x00000004 +.set CYFLD_ROMTABLE_REV_AND__SIZE, 0x00000004 +.set CYREG_ROMTABLE_CID0, 0xf0000ff0 +.set CYREG_ROMTABLE_CID1, 0xf0000ff4 +.set CYREG_ROMTABLE_CID2, 0xf0000ff8 +.set CYREG_ROMTABLE_CID3, 0xf0000ffc +.set CYDEV_FLS_SECTOR_SIZE, 0x00020000 +.set CYDEV_FLS_ROW_SIZE, 0x00000100 diff --git a/cores/asr650x/projects/PSoC4/cydeviceiar_trm.inc b/cores/asr650x/projects/PSoC4/cydeviceiar_trm.inc new file mode 100644 index 00000000..c853c41e --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cydeviceiar_trm.inc @@ -0,0 +1,5490 @@ +; +; File Name: cydeviceiar_trm.inc +; +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#define CYDEV_FLASH_BASE 0x00000000 +#define CYDEV_FLASH_SIZE 0x00020000 +#define CYREG_FLASH_DATA_MBASE 0x00000000 +#define CYREG_FLASH_DATA_MSIZE 0x00020000 +#define CYDEV_SFLASH_BASE 0x0ffff000 +#define CYDEV_SFLASH_SIZE 0x00000800 +#define CYREG_SFLASH_PROT_ROW0 0x0ffff000 +#define CYFLD_SFLASH_DATA8__OFFSET 0x00000000 +#define CYFLD_SFLASH_DATA8__SIZE 0x00000008 +#define CYREG_SFLASH_PROT_ROW1 0x0ffff001 +#define CYREG_SFLASH_PROT_ROW2 0x0ffff002 +#define CYREG_SFLASH_PROT_ROW3 0x0ffff003 +#define CYREG_SFLASH_PROT_ROW4 0x0ffff004 +#define CYREG_SFLASH_PROT_ROW5 0x0ffff005 +#define CYREG_SFLASH_PROT_ROW6 0x0ffff006 +#define CYREG_SFLASH_PROT_ROW7 0x0ffff007 +#define CYREG_SFLASH_PROT_ROW8 0x0ffff008 +#define CYREG_SFLASH_PROT_ROW9 0x0ffff009 +#define CYREG_SFLASH_PROT_ROW10 0x0ffff00a +#define CYREG_SFLASH_PROT_ROW11 0x0ffff00b +#define CYREG_SFLASH_PROT_ROW12 0x0ffff00c +#define CYREG_SFLASH_PROT_ROW13 0x0ffff00d +#define CYREG_SFLASH_PROT_ROW14 0x0ffff00e +#define CYREG_SFLASH_PROT_ROW15 0x0ffff00f +#define CYREG_SFLASH_PROT_ROW16 0x0ffff010 +#define CYREG_SFLASH_PROT_ROW17 0x0ffff011 +#define CYREG_SFLASH_PROT_ROW18 0x0ffff012 +#define CYREG_SFLASH_PROT_ROW19 0x0ffff013 +#define CYREG_SFLASH_PROT_ROW20 0x0ffff014 +#define CYREG_SFLASH_PROT_ROW21 0x0ffff015 +#define CYREG_SFLASH_PROT_ROW22 0x0ffff016 +#define CYREG_SFLASH_PROT_ROW23 0x0ffff017 +#define CYREG_SFLASH_PROT_ROW24 0x0ffff018 +#define CYREG_SFLASH_PROT_ROW25 0x0ffff019 +#define CYREG_SFLASH_PROT_ROW26 0x0ffff01a +#define CYREG_SFLASH_PROT_ROW27 0x0ffff01b +#define CYREG_SFLASH_PROT_ROW28 0x0ffff01c +#define CYREG_SFLASH_PROT_ROW29 0x0ffff01d +#define CYREG_SFLASH_PROT_ROW30 0x0ffff01e +#define CYREG_SFLASH_PROT_ROW31 0x0ffff01f +#define CYREG_SFLASH_PROT_ROW32 0x0ffff020 +#define CYREG_SFLASH_PROT_ROW33 0x0ffff021 +#define CYREG_SFLASH_PROT_ROW34 0x0ffff022 +#define CYREG_SFLASH_PROT_ROW35 0x0ffff023 +#define CYREG_SFLASH_PROT_ROW36 0x0ffff024 +#define CYREG_SFLASH_PROT_ROW37 0x0ffff025 +#define CYREG_SFLASH_PROT_ROW38 0x0ffff026 +#define CYREG_SFLASH_PROT_ROW39 0x0ffff027 +#define CYREG_SFLASH_PROT_ROW40 0x0ffff028 +#define CYREG_SFLASH_PROT_ROW41 0x0ffff029 +#define CYREG_SFLASH_PROT_ROW42 0x0ffff02a +#define CYREG_SFLASH_PROT_ROW43 0x0ffff02b +#define CYREG_SFLASH_PROT_ROW44 0x0ffff02c +#define CYREG_SFLASH_PROT_ROW45 0x0ffff02d +#define CYREG_SFLASH_PROT_ROW46 0x0ffff02e +#define CYREG_SFLASH_PROT_ROW47 0x0ffff02f +#define CYREG_SFLASH_PROT_ROW48 0x0ffff030 +#define CYREG_SFLASH_PROT_ROW49 0x0ffff031 +#define CYREG_SFLASH_PROT_ROW50 0x0ffff032 +#define CYREG_SFLASH_PROT_ROW51 0x0ffff033 +#define CYREG_SFLASH_PROT_ROW52 0x0ffff034 +#define CYREG_SFLASH_PROT_ROW53 0x0ffff035 +#define CYREG_SFLASH_PROT_ROW54 0x0ffff036 +#define CYREG_SFLASH_PROT_ROW55 0x0ffff037 +#define CYREG_SFLASH_PROT_ROW56 0x0ffff038 +#define CYREG_SFLASH_PROT_ROW57 0x0ffff039 +#define CYREG_SFLASH_PROT_ROW58 0x0ffff03a +#define CYREG_SFLASH_PROT_ROW59 0x0ffff03b +#define CYREG_SFLASH_PROT_ROW60 0x0ffff03c +#define CYREG_SFLASH_PROT_ROW61 0x0ffff03d +#define CYREG_SFLASH_PROT_ROW62 0x0ffff03e +#define CYREG_SFLASH_PROT_ROW63 0x0ffff03f +#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff0ff +#define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000 +#define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002 +#define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001 +#define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000 +#define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002 +#define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003 +#define CYREG_SFLASH_AV_PAIRS_8B0 0x0ffff100 +#define CYREG_SFLASH_AV_PAIRS_8B1 0x0ffff101 +#define CYREG_SFLASH_AV_PAIRS_8B2 0x0ffff102 +#define CYREG_SFLASH_AV_PAIRS_8B3 0x0ffff103 +#define CYREG_SFLASH_AV_PAIRS_8B4 0x0ffff104 +#define CYREG_SFLASH_AV_PAIRS_8B5 0x0ffff105 +#define CYREG_SFLASH_AV_PAIRS_8B6 0x0ffff106 +#define CYREG_SFLASH_AV_PAIRS_8B7 0x0ffff107 +#define CYREG_SFLASH_AV_PAIRS_8B8 0x0ffff108 +#define CYREG_SFLASH_AV_PAIRS_8B9 0x0ffff109 +#define CYREG_SFLASH_AV_PAIRS_8B10 0x0ffff10a +#define CYREG_SFLASH_AV_PAIRS_8B11 0x0ffff10b +#define CYREG_SFLASH_AV_PAIRS_8B12 0x0ffff10c +#define CYREG_SFLASH_AV_PAIRS_8B13 0x0ffff10d +#define CYREG_SFLASH_AV_PAIRS_8B14 0x0ffff10e +#define CYREG_SFLASH_AV_PAIRS_8B15 0x0ffff10f +#define CYREG_SFLASH_AV_PAIRS_8B16 0x0ffff110 +#define CYREG_SFLASH_AV_PAIRS_8B17 0x0ffff111 +#define CYREG_SFLASH_AV_PAIRS_8B18 0x0ffff112 +#define CYREG_SFLASH_AV_PAIRS_8B19 0x0ffff113 +#define CYREG_SFLASH_AV_PAIRS_8B20 0x0ffff114 +#define CYREG_SFLASH_AV_PAIRS_8B21 0x0ffff115 +#define CYREG_SFLASH_AV_PAIRS_8B22 0x0ffff116 +#define CYREG_SFLASH_AV_PAIRS_8B23 0x0ffff117 +#define CYREG_SFLASH_AV_PAIRS_8B24 0x0ffff118 +#define CYREG_SFLASH_AV_PAIRS_8B25 0x0ffff119 +#define CYREG_SFLASH_AV_PAIRS_8B26 0x0ffff11a +#define CYREG_SFLASH_AV_PAIRS_8B27 0x0ffff11b +#define CYREG_SFLASH_AV_PAIRS_8B28 0x0ffff11c +#define CYREG_SFLASH_AV_PAIRS_8B29 0x0ffff11d +#define CYREG_SFLASH_AV_PAIRS_8B30 0x0ffff11e +#define CYREG_SFLASH_AV_PAIRS_8B31 0x0ffff11f +#define CYREG_SFLASH_AV_PAIRS_8B32 0x0ffff120 +#define CYREG_SFLASH_AV_PAIRS_8B33 0x0ffff121 +#define CYREG_SFLASH_AV_PAIRS_8B34 0x0ffff122 +#define CYREG_SFLASH_AV_PAIRS_8B35 0x0ffff123 +#define CYREG_SFLASH_AV_PAIRS_8B36 0x0ffff124 +#define CYREG_SFLASH_AV_PAIRS_8B37 0x0ffff125 +#define CYREG_SFLASH_AV_PAIRS_8B38 0x0ffff126 +#define CYREG_SFLASH_AV_PAIRS_8B39 0x0ffff127 +#define CYREG_SFLASH_AV_PAIRS_8B40 0x0ffff128 +#define CYREG_SFLASH_AV_PAIRS_8B41 0x0ffff129 +#define CYREG_SFLASH_AV_PAIRS_8B42 0x0ffff12a +#define CYREG_SFLASH_AV_PAIRS_8B43 0x0ffff12b +#define CYREG_SFLASH_AV_PAIRS_8B44 0x0ffff12c +#define CYREG_SFLASH_AV_PAIRS_8B45 0x0ffff12d +#define CYREG_SFLASH_AV_PAIRS_8B46 0x0ffff12e +#define CYREG_SFLASH_AV_PAIRS_8B47 0x0ffff12f +#define CYREG_SFLASH_AV_PAIRS_8B48 0x0ffff130 +#define CYREG_SFLASH_AV_PAIRS_8B49 0x0ffff131 +#define CYREG_SFLASH_AV_PAIRS_8B50 0x0ffff132 +#define CYREG_SFLASH_AV_PAIRS_8B51 0x0ffff133 +#define CYREG_SFLASH_AV_PAIRS_8B52 0x0ffff134 +#define CYREG_SFLASH_AV_PAIRS_8B53 0x0ffff135 +#define CYREG_SFLASH_AV_PAIRS_8B54 0x0ffff136 +#define CYREG_SFLASH_AV_PAIRS_8B55 0x0ffff137 +#define CYREG_SFLASH_AV_PAIRS_8B56 0x0ffff138 +#define CYREG_SFLASH_AV_PAIRS_8B57 0x0ffff139 +#define CYREG_SFLASH_AV_PAIRS_8B58 0x0ffff13a +#define CYREG_SFLASH_AV_PAIRS_8B59 0x0ffff13b +#define CYREG_SFLASH_AV_PAIRS_8B60 0x0ffff13c +#define CYREG_SFLASH_AV_PAIRS_8B61 0x0ffff13d +#define CYREG_SFLASH_AV_PAIRS_8B62 0x0ffff13e +#define CYREG_SFLASH_AV_PAIRS_8B63 0x0ffff13f +#define CYREG_SFLASH_AV_PAIRS_8B64 0x0ffff140 +#define CYREG_SFLASH_AV_PAIRS_8B65 0x0ffff141 +#define CYREG_SFLASH_AV_PAIRS_8B66 0x0ffff142 +#define CYREG_SFLASH_AV_PAIRS_8B67 0x0ffff143 +#define CYREG_SFLASH_AV_PAIRS_8B68 0x0ffff144 +#define CYREG_SFLASH_AV_PAIRS_8B69 0x0ffff145 +#define CYREG_SFLASH_AV_PAIRS_8B70 0x0ffff146 +#define CYREG_SFLASH_AV_PAIRS_8B71 0x0ffff147 +#define CYREG_SFLASH_AV_PAIRS_8B72 0x0ffff148 +#define CYREG_SFLASH_AV_PAIRS_8B73 0x0ffff149 +#define CYREG_SFLASH_AV_PAIRS_8B74 0x0ffff14a +#define CYREG_SFLASH_AV_PAIRS_8B75 0x0ffff14b +#define CYREG_SFLASH_AV_PAIRS_8B76 0x0ffff14c +#define CYREG_SFLASH_AV_PAIRS_8B77 0x0ffff14d +#define CYREG_SFLASH_AV_PAIRS_8B78 0x0ffff14e +#define CYREG_SFLASH_AV_PAIRS_8B79 0x0ffff14f +#define CYREG_SFLASH_AV_PAIRS_8B80 0x0ffff150 +#define CYREG_SFLASH_AV_PAIRS_8B81 0x0ffff151 +#define CYREG_SFLASH_AV_PAIRS_8B82 0x0ffff152 +#define CYREG_SFLASH_AV_PAIRS_8B83 0x0ffff153 +#define CYREG_SFLASH_AV_PAIRS_8B84 0x0ffff154 +#define CYREG_SFLASH_AV_PAIRS_8B85 0x0ffff155 +#define CYREG_SFLASH_AV_PAIRS_8B86 0x0ffff156 +#define CYREG_SFLASH_AV_PAIRS_8B87 0x0ffff157 +#define CYREG_SFLASH_AV_PAIRS_8B88 0x0ffff158 +#define CYREG_SFLASH_AV_PAIRS_8B89 0x0ffff159 +#define CYREG_SFLASH_AV_PAIRS_8B90 0x0ffff15a +#define CYREG_SFLASH_AV_PAIRS_8B91 0x0ffff15b +#define CYREG_SFLASH_AV_PAIRS_8B92 0x0ffff15c +#define CYREG_SFLASH_AV_PAIRS_8B93 0x0ffff15d +#define CYREG_SFLASH_AV_PAIRS_8B94 0x0ffff15e +#define CYREG_SFLASH_AV_PAIRS_8B95 0x0ffff15f +#define CYREG_SFLASH_AV_PAIRS_8B96 0x0ffff160 +#define CYREG_SFLASH_AV_PAIRS_8B97 0x0ffff161 +#define CYREG_SFLASH_AV_PAIRS_8B98 0x0ffff162 +#define CYREG_SFLASH_AV_PAIRS_8B99 0x0ffff163 +#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff164 +#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff165 +#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff166 +#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff167 +#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff168 +#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff169 +#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff16a +#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff16b +#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff16c +#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff16d +#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff16e +#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff16f +#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff170 +#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff171 +#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff172 +#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff173 +#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff174 +#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff175 +#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff176 +#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff177 +#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff178 +#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff179 +#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff17a +#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff17b +#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff17c +#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff17d +#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff17e +#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff17f +#define CYREG_SFLASH_AV_PAIRS_32B0 0x0ffff200 +#define CYFLD_SFLASH_DATA32__OFFSET 0x00000000 +#define CYFLD_SFLASH_DATA32__SIZE 0x00000020 +#define CYREG_SFLASH_AV_PAIRS_32B1 0x0ffff204 +#define CYREG_SFLASH_AV_PAIRS_32B2 0x0ffff208 +#define CYREG_SFLASH_AV_PAIRS_32B3 0x0ffff20c +#define CYREG_SFLASH_AV_PAIRS_32B4 0x0ffff210 +#define CYREG_SFLASH_AV_PAIRS_32B5 0x0ffff214 +#define CYREG_SFLASH_AV_PAIRS_32B6 0x0ffff218 +#define CYREG_SFLASH_AV_PAIRS_32B7 0x0ffff21c +#define CYREG_SFLASH_AV_PAIRS_32B8 0x0ffff220 +#define CYREG_SFLASH_AV_PAIRS_32B9 0x0ffff224 +#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff228 +#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff22c +#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff230 +#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff234 +#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff238 +#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff23c +#define CYREG_SFLASH_SILICON_ID 0x0ffff244 +#define CYFLD_SFLASH_ID__OFFSET 0x00000000 +#define CYFLD_SFLASH_ID__SIZE 0x00000010 +#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff250 +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000 +#define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000a +#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff252 +#define CYREG_SFLASH_SWD_CONFIG 0x0ffff254 +#define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000 +#define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001 +#define CYREG_SFLASH_SWD_LISTEN 0x0ffff258 +#define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000 +#define CYFLD_SFLASH_CYCLES__SIZE 0x00000020 +#define CYREG_SFLASH_FLASH_START 0x0ffff25c +#define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000 +#define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020 +#define CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM1 0x0ffff260 +#define CYFLD_SFLASH_CSD_ADC_CAL_LSB__OFFSET 0x00000000 +#define CYFLD_SFLASH_CSD_ADC_CAL_LSB__SIZE 0x00000008 +#define CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM2 0x0ffff261 +#define CYFLD_SFLASH_CSD_ADC_CAL_MSB__OFFSET 0x00000000 +#define CYFLD_SFLASH_CSD_ADC_CAL_MSB__SIZE 0x00000008 +#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff264 +#define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000 +#define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010 +#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff266 +#define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000 +#define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010 +#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff270 +#define CYFLD_SFLASH_KEY8__OFFSET 0x00000000 +#define CYFLD_SFLASH_KEY8__SIZE 0x00000008 +#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff271 +#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff272 +#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff273 +#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff274 +#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff275 +#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff276 +#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff277 +#define CYREG_SFLASH_DIE_LOT0 0x0ffff278 +#define CYFLD_SFLASH_LOT__OFFSET 0x00000000 +#define CYFLD_SFLASH_LOT__SIZE 0x00000008 +#define CYREG_SFLASH_DIE_LOT1 0x0ffff279 +#define CYREG_SFLASH_DIE_LOT2 0x0ffff27a +#define CYREG_SFLASH_DIE_WAFER 0x0ffff27b +#define CYFLD_SFLASH_WAFER__OFFSET 0x00000000 +#define CYFLD_SFLASH_WAFER__SIZE 0x00000008 +#define CYREG_SFLASH_DIE_X 0x0ffff27c +#define CYFLD_SFLASH_X__OFFSET 0x00000000 +#define CYFLD_SFLASH_X__SIZE 0x00000008 +#define CYREG_SFLASH_DIE_Y 0x0ffff27d +#define CYFLD_SFLASH_Y__OFFSET 0x00000000 +#define CYFLD_SFLASH_Y__SIZE 0x00000008 +#define CYREG_SFLASH_DIE_SORT 0x0ffff27e +#define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000 +#define CYFLD_SFLASH_S1_PASS__SIZE 0x00000001 +#define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000001 +#define CYFLD_SFLASH_S2_PASS__SIZE 0x00000001 +#define CYFLD_SFLASH_S3_PASS__OFFSET 0x00000002 +#define CYFLD_SFLASH_S3_PASS__SIZE 0x00000001 +#define CYFLD_SFLASH_CRI_PASS__OFFSET 0x00000003 +#define CYFLD_SFLASH_CRI_PASS__SIZE 0x00000001 +#define CYFLD_SFLASH_CHI_PASS__OFFSET 0x00000004 +#define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000001 +#define CYFLD_SFLASH_ENG_PASS__OFFSET 0x00000005 +#define CYFLD_SFLASH_ENG_PASS__SIZE 0x00000001 +#define CYREG_SFLASH_DIE_MINOR 0x0ffff27f +#define CYFLD_SFLASH_MINOR__OFFSET 0x00000000 +#define CYFLD_SFLASH_MINOR__SIZE 0x00000008 +#define CYREG_SFLASH_IMO_TRIM_USBMODE_24 0x0ffff33e +#define CYFLD_SFLASH_TRIM_24__OFFSET 0x00000000 +#define CYFLD_SFLASH_TRIM_24__SIZE 0x00000008 +#define CYREG_SFLASH_IMO_TRIM_USBMODE_48 0x0ffff33f +#define CYREG_SFLASH_IMO_TCTRIM_LT0 0x0ffff34c +#define CYFLD_SFLASH_STEPSIZE__OFFSET 0x00000000 +#define CYFLD_SFLASH_STEPSIZE__SIZE 0x00000005 +#define CYFLD_SFLASH_TCTRIM__OFFSET 0x00000005 +#define CYFLD_SFLASH_TCTRIM__SIZE 0x00000002 +#define CYREG_SFLASH_IMO_TCTRIM_LT1 0x0ffff34d +#define CYREG_SFLASH_IMO_TCTRIM_LT2 0x0ffff34e +#define CYREG_SFLASH_IMO_TCTRIM_LT3 0x0ffff34f +#define CYREG_SFLASH_IMO_TCTRIM_LT4 0x0ffff350 +#define CYREG_SFLASH_IMO_TCTRIM_LT5 0x0ffff351 +#define CYREG_SFLASH_IMO_TCTRIM_LT6 0x0ffff352 +#define CYREG_SFLASH_IMO_TCTRIM_LT7 0x0ffff353 +#define CYREG_SFLASH_IMO_TCTRIM_LT8 0x0ffff354 +#define CYREG_SFLASH_IMO_TCTRIM_LT9 0x0ffff355 +#define CYREG_SFLASH_IMO_TCTRIM_LT10 0x0ffff356 +#define CYREG_SFLASH_IMO_TCTRIM_LT11 0x0ffff357 +#define CYREG_SFLASH_IMO_TCTRIM_LT12 0x0ffff358 +#define CYREG_SFLASH_IMO_TCTRIM_LT13 0x0ffff359 +#define CYREG_SFLASH_IMO_TCTRIM_LT14 0x0ffff35a +#define CYREG_SFLASH_IMO_TCTRIM_LT15 0x0ffff35b +#define CYREG_SFLASH_IMO_TCTRIM_LT16 0x0ffff35c +#define CYREG_SFLASH_IMO_TCTRIM_LT17 0x0ffff35d +#define CYREG_SFLASH_IMO_TCTRIM_LT18 0x0ffff35e +#define CYREG_SFLASH_IMO_TCTRIM_LT19 0x0ffff35f +#define CYREG_SFLASH_IMO_TCTRIM_LT20 0x0ffff360 +#define CYREG_SFLASH_IMO_TCTRIM_LT21 0x0ffff361 +#define CYREG_SFLASH_IMO_TCTRIM_LT22 0x0ffff362 +#define CYREG_SFLASH_IMO_TCTRIM_LT23 0x0ffff363 +#define CYREG_SFLASH_IMO_TCTRIM_LT24 0x0ffff364 +#define CYREG_SFLASH_IMO_TRIM_LT0 0x0ffff365 +#define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000 +#define CYFLD_SFLASH_OFFSET__SIZE 0x00000008 +#define CYREG_SFLASH_IMO_TRIM_LT1 0x0ffff366 +#define CYREG_SFLASH_IMO_TRIM_LT2 0x0ffff367 +#define CYREG_SFLASH_IMO_TRIM_LT3 0x0ffff368 +#define CYREG_SFLASH_IMO_TRIM_LT4 0x0ffff369 +#define CYREG_SFLASH_IMO_TRIM_LT5 0x0ffff36a +#define CYREG_SFLASH_IMO_TRIM_LT6 0x0ffff36b +#define CYREG_SFLASH_IMO_TRIM_LT7 0x0ffff36c +#define CYREG_SFLASH_IMO_TRIM_LT8 0x0ffff36d +#define CYREG_SFLASH_IMO_TRIM_LT9 0x0ffff36e +#define CYREG_SFLASH_IMO_TRIM_LT10 0x0ffff36f +#define CYREG_SFLASH_IMO_TRIM_LT11 0x0ffff370 +#define CYREG_SFLASH_IMO_TRIM_LT12 0x0ffff371 +#define CYREG_SFLASH_IMO_TRIM_LT13 0x0ffff372 +#define CYREG_SFLASH_IMO_TRIM_LT14 0x0ffff373 +#define CYREG_SFLASH_IMO_TRIM_LT15 0x0ffff374 +#define CYREG_SFLASH_IMO_TRIM_LT16 0x0ffff375 +#define CYREG_SFLASH_IMO_TRIM_LT17 0x0ffff376 +#define CYREG_SFLASH_IMO_TRIM_LT18 0x0ffff377 +#define CYREG_SFLASH_IMO_TRIM_LT19 0x0ffff378 +#define CYREG_SFLASH_IMO_TRIM_LT20 0x0ffff379 +#define CYREG_SFLASH_IMO_TRIM_LT21 0x0ffff37a +#define CYREG_SFLASH_IMO_TRIM_LT22 0x0ffff37b +#define CYREG_SFLASH_IMO_TRIM_LT23 0x0ffff37c +#define CYREG_SFLASH_IMO_TRIM_LT24 0x0ffff37d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH0 0x0ffff400 +#define CYFLD_SFLASH_BYTE_MEM__OFFSET 0x00000000 +#define CYFLD_SFLASH_BYTE_MEM__SIZE 0x00000008 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1 0x0ffff401 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH2 0x0ffff402 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH3 0x0ffff403 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH4 0x0ffff404 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH5 0x0ffff405 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH6 0x0ffff406 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH7 0x0ffff407 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH8 0x0ffff408 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH9 0x0ffff409 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH10 0x0ffff40a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH11 0x0ffff40b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH12 0x0ffff40c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH13 0x0ffff40d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH14 0x0ffff40e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH15 0x0ffff40f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH16 0x0ffff410 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH17 0x0ffff411 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH18 0x0ffff412 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH19 0x0ffff413 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH20 0x0ffff414 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH21 0x0ffff415 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH22 0x0ffff416 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH23 0x0ffff417 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH24 0x0ffff418 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH25 0x0ffff419 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH26 0x0ffff41a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH27 0x0ffff41b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH28 0x0ffff41c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH29 0x0ffff41d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH30 0x0ffff41e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH31 0x0ffff41f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH32 0x0ffff420 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH33 0x0ffff421 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH34 0x0ffff422 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH35 0x0ffff423 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH36 0x0ffff424 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH37 0x0ffff425 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH38 0x0ffff426 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH39 0x0ffff427 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH40 0x0ffff428 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH41 0x0ffff429 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH42 0x0ffff42a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH43 0x0ffff42b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH44 0x0ffff42c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH45 0x0ffff42d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH46 0x0ffff42e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH47 0x0ffff42f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH48 0x0ffff430 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH49 0x0ffff431 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH50 0x0ffff432 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH51 0x0ffff433 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH52 0x0ffff434 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH53 0x0ffff435 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH54 0x0ffff436 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH55 0x0ffff437 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH56 0x0ffff438 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH57 0x0ffff439 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH58 0x0ffff43a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH59 0x0ffff43b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH60 0x0ffff43c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH61 0x0ffff43d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH62 0x0ffff43e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH63 0x0ffff43f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH64 0x0ffff440 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH65 0x0ffff441 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH66 0x0ffff442 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH67 0x0ffff443 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH68 0x0ffff444 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH69 0x0ffff445 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH70 0x0ffff446 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH71 0x0ffff447 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH72 0x0ffff448 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH73 0x0ffff449 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH74 0x0ffff44a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH75 0x0ffff44b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH76 0x0ffff44c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH77 0x0ffff44d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH78 0x0ffff44e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH79 0x0ffff44f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH80 0x0ffff450 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH81 0x0ffff451 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH82 0x0ffff452 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH83 0x0ffff453 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH84 0x0ffff454 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH85 0x0ffff455 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH86 0x0ffff456 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH87 0x0ffff457 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH88 0x0ffff458 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH89 0x0ffff459 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH90 0x0ffff45a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH91 0x0ffff45b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH92 0x0ffff45c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH93 0x0ffff45d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH94 0x0ffff45e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH95 0x0ffff45f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH96 0x0ffff460 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH97 0x0ffff461 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH98 0x0ffff462 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH99 0x0ffff463 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH100 0x0ffff464 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH101 0x0ffff465 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH102 0x0ffff466 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH103 0x0ffff467 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH104 0x0ffff468 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH105 0x0ffff469 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH106 0x0ffff46a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH107 0x0ffff46b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH108 0x0ffff46c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH109 0x0ffff46d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH110 0x0ffff46e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH111 0x0ffff46f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH112 0x0ffff470 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH113 0x0ffff471 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH114 0x0ffff472 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH115 0x0ffff473 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH116 0x0ffff474 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH117 0x0ffff475 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH118 0x0ffff476 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH119 0x0ffff477 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH120 0x0ffff478 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH121 0x0ffff479 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH122 0x0ffff47a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH123 0x0ffff47b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH124 0x0ffff47c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH125 0x0ffff47d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH126 0x0ffff47e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH127 0x0ffff47f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH128 0x0ffff480 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH129 0x0ffff481 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH130 0x0ffff482 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH131 0x0ffff483 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH132 0x0ffff484 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH133 0x0ffff485 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH134 0x0ffff486 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH135 0x0ffff487 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH136 0x0ffff488 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH137 0x0ffff489 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH138 0x0ffff48a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH139 0x0ffff48b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH140 0x0ffff48c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH141 0x0ffff48d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH142 0x0ffff48e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH143 0x0ffff48f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH144 0x0ffff490 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH145 0x0ffff491 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH146 0x0ffff492 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH147 0x0ffff493 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH148 0x0ffff494 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH149 0x0ffff495 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH150 0x0ffff496 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH151 0x0ffff497 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH152 0x0ffff498 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH153 0x0ffff499 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH154 0x0ffff49a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH155 0x0ffff49b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH156 0x0ffff49c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH157 0x0ffff49d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH158 0x0ffff49e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH159 0x0ffff49f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH160 0x0ffff4a0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH161 0x0ffff4a1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH162 0x0ffff4a2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH163 0x0ffff4a3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH164 0x0ffff4a4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH165 0x0ffff4a5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH166 0x0ffff4a6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH167 0x0ffff4a7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH168 0x0ffff4a8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH169 0x0ffff4a9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH170 0x0ffff4aa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH171 0x0ffff4ab +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH172 0x0ffff4ac +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH173 0x0ffff4ad +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH174 0x0ffff4ae +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH175 0x0ffff4af +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH176 0x0ffff4b0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH177 0x0ffff4b1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH178 0x0ffff4b2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH179 0x0ffff4b3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH180 0x0ffff4b4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH181 0x0ffff4b5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH182 0x0ffff4b6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH183 0x0ffff4b7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH184 0x0ffff4b8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH185 0x0ffff4b9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH186 0x0ffff4ba +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH187 0x0ffff4bb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH188 0x0ffff4bc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH189 0x0ffff4bd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH190 0x0ffff4be +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH191 0x0ffff4bf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH192 0x0ffff4c0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH193 0x0ffff4c1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH194 0x0ffff4c2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH195 0x0ffff4c3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH196 0x0ffff4c4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH197 0x0ffff4c5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH198 0x0ffff4c6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH199 0x0ffff4c7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH200 0x0ffff4c8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH201 0x0ffff4c9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH202 0x0ffff4ca +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH203 0x0ffff4cb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH204 0x0ffff4cc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH205 0x0ffff4cd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH206 0x0ffff4ce +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH207 0x0ffff4cf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH208 0x0ffff4d0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH209 0x0ffff4d1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH210 0x0ffff4d2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH211 0x0ffff4d3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH212 0x0ffff4d4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH213 0x0ffff4d5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH214 0x0ffff4d6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH215 0x0ffff4d7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH216 0x0ffff4d8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH217 0x0ffff4d9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH218 0x0ffff4da +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH219 0x0ffff4db +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH220 0x0ffff4dc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH221 0x0ffff4dd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH222 0x0ffff4de +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH223 0x0ffff4df +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH224 0x0ffff4e0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH225 0x0ffff4e1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH226 0x0ffff4e2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH227 0x0ffff4e3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH228 0x0ffff4e4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH229 0x0ffff4e5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH230 0x0ffff4e6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH231 0x0ffff4e7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH232 0x0ffff4e8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH233 0x0ffff4e9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH234 0x0ffff4ea +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH235 0x0ffff4eb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH236 0x0ffff4ec +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH237 0x0ffff4ed +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH238 0x0ffff4ee +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH239 0x0ffff4ef +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH240 0x0ffff4f0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH241 0x0ffff4f1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH242 0x0ffff4f2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH243 0x0ffff4f3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH244 0x0ffff4f4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH245 0x0ffff4f5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH246 0x0ffff4f6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH247 0x0ffff4f7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH248 0x0ffff4f8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH249 0x0ffff4f9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH250 0x0ffff4fa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH251 0x0ffff4fb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH252 0x0ffff4fc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH253 0x0ffff4fd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH254 0x0ffff4fe +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH255 0x0ffff4ff +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH256 0x0ffff500 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH257 0x0ffff501 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH258 0x0ffff502 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH259 0x0ffff503 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH260 0x0ffff504 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH261 0x0ffff505 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH262 0x0ffff506 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH263 0x0ffff507 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH264 0x0ffff508 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH265 0x0ffff509 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH266 0x0ffff50a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH267 0x0ffff50b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH268 0x0ffff50c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH269 0x0ffff50d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH270 0x0ffff50e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH271 0x0ffff50f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH272 0x0ffff510 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH273 0x0ffff511 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH274 0x0ffff512 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH275 0x0ffff513 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH276 0x0ffff514 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH277 0x0ffff515 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH278 0x0ffff516 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH279 0x0ffff517 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH280 0x0ffff518 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH281 0x0ffff519 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH282 0x0ffff51a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH283 0x0ffff51b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH284 0x0ffff51c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH285 0x0ffff51d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH286 0x0ffff51e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH287 0x0ffff51f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH288 0x0ffff520 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH289 0x0ffff521 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH290 0x0ffff522 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH291 0x0ffff523 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH292 0x0ffff524 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH293 0x0ffff525 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH294 0x0ffff526 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH295 0x0ffff527 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH296 0x0ffff528 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH297 0x0ffff529 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH298 0x0ffff52a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH299 0x0ffff52b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH300 0x0ffff52c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH301 0x0ffff52d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH302 0x0ffff52e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH303 0x0ffff52f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH304 0x0ffff530 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH305 0x0ffff531 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH306 0x0ffff532 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH307 0x0ffff533 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH308 0x0ffff534 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH309 0x0ffff535 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH310 0x0ffff536 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH311 0x0ffff537 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH312 0x0ffff538 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH313 0x0ffff539 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH314 0x0ffff53a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH315 0x0ffff53b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH316 0x0ffff53c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH317 0x0ffff53d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH318 0x0ffff53e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH319 0x0ffff53f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH320 0x0ffff540 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH321 0x0ffff541 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH322 0x0ffff542 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH323 0x0ffff543 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH324 0x0ffff544 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH325 0x0ffff545 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH326 0x0ffff546 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH327 0x0ffff547 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH328 0x0ffff548 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH329 0x0ffff549 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH330 0x0ffff54a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH331 0x0ffff54b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH332 0x0ffff54c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH333 0x0ffff54d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH334 0x0ffff54e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH335 0x0ffff54f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH336 0x0ffff550 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH337 0x0ffff551 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH338 0x0ffff552 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH339 0x0ffff553 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH340 0x0ffff554 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH341 0x0ffff555 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH342 0x0ffff556 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH343 0x0ffff557 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH344 0x0ffff558 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH345 0x0ffff559 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH346 0x0ffff55a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH347 0x0ffff55b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH348 0x0ffff55c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH349 0x0ffff55d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH350 0x0ffff55e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH351 0x0ffff55f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH352 0x0ffff560 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH353 0x0ffff561 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH354 0x0ffff562 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH355 0x0ffff563 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH356 0x0ffff564 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH357 0x0ffff565 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH358 0x0ffff566 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH359 0x0ffff567 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH360 0x0ffff568 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH361 0x0ffff569 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH362 0x0ffff56a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH363 0x0ffff56b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH364 0x0ffff56c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH365 0x0ffff56d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH366 0x0ffff56e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH367 0x0ffff56f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH368 0x0ffff570 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH369 0x0ffff571 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH370 0x0ffff572 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH371 0x0ffff573 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH372 0x0ffff574 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH373 0x0ffff575 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH374 0x0ffff576 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH375 0x0ffff577 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH376 0x0ffff578 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH377 0x0ffff579 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH378 0x0ffff57a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH379 0x0ffff57b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH380 0x0ffff57c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH381 0x0ffff57d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH382 0x0ffff57e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH383 0x0ffff57f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH384 0x0ffff580 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH385 0x0ffff581 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH386 0x0ffff582 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH387 0x0ffff583 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH388 0x0ffff584 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH389 0x0ffff585 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH390 0x0ffff586 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH391 0x0ffff587 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH392 0x0ffff588 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH393 0x0ffff589 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH394 0x0ffff58a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH395 0x0ffff58b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH396 0x0ffff58c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH397 0x0ffff58d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH398 0x0ffff58e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH399 0x0ffff58f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH400 0x0ffff590 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH401 0x0ffff591 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH402 0x0ffff592 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH403 0x0ffff593 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH404 0x0ffff594 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH405 0x0ffff595 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH406 0x0ffff596 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH407 0x0ffff597 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH408 0x0ffff598 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH409 0x0ffff599 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH410 0x0ffff59a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH411 0x0ffff59b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH412 0x0ffff59c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH413 0x0ffff59d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH414 0x0ffff59e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH415 0x0ffff59f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH416 0x0ffff5a0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH417 0x0ffff5a1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH418 0x0ffff5a2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH419 0x0ffff5a3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH420 0x0ffff5a4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH421 0x0ffff5a5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH422 0x0ffff5a6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH423 0x0ffff5a7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH424 0x0ffff5a8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH425 0x0ffff5a9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH426 0x0ffff5aa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH427 0x0ffff5ab +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH428 0x0ffff5ac +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH429 0x0ffff5ad +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH430 0x0ffff5ae +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH431 0x0ffff5af +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH432 0x0ffff5b0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH433 0x0ffff5b1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH434 0x0ffff5b2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH435 0x0ffff5b3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH436 0x0ffff5b4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH437 0x0ffff5b5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH438 0x0ffff5b6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH439 0x0ffff5b7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH440 0x0ffff5b8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH441 0x0ffff5b9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH442 0x0ffff5ba +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH443 0x0ffff5bb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH444 0x0ffff5bc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH445 0x0ffff5bd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH446 0x0ffff5be +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH447 0x0ffff5bf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH448 0x0ffff5c0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH449 0x0ffff5c1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH450 0x0ffff5c2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH451 0x0ffff5c3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH452 0x0ffff5c4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH453 0x0ffff5c5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH454 0x0ffff5c6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH455 0x0ffff5c7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH456 0x0ffff5c8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH457 0x0ffff5c9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH458 0x0ffff5ca +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH459 0x0ffff5cb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH460 0x0ffff5cc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH461 0x0ffff5cd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH462 0x0ffff5ce +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH463 0x0ffff5cf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH464 0x0ffff5d0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH465 0x0ffff5d1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH466 0x0ffff5d2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH467 0x0ffff5d3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH468 0x0ffff5d4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH469 0x0ffff5d5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH470 0x0ffff5d6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH471 0x0ffff5d7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH472 0x0ffff5d8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH473 0x0ffff5d9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH474 0x0ffff5da +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH475 0x0ffff5db +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH476 0x0ffff5dc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH477 0x0ffff5dd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH478 0x0ffff5de +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH479 0x0ffff5df +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH480 0x0ffff5e0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH481 0x0ffff5e1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH482 0x0ffff5e2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH483 0x0ffff5e3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH484 0x0ffff5e4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH485 0x0ffff5e5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH486 0x0ffff5e6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH487 0x0ffff5e7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH488 0x0ffff5e8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH489 0x0ffff5e9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH490 0x0ffff5ea +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH491 0x0ffff5eb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH492 0x0ffff5ec +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH493 0x0ffff5ed +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH494 0x0ffff5ee +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH495 0x0ffff5ef +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH496 0x0ffff5f0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH497 0x0ffff5f1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH498 0x0ffff5f2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH499 0x0ffff5f3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH500 0x0ffff5f4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH501 0x0ffff5f5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH502 0x0ffff5f6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH503 0x0ffff5f7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH504 0x0ffff5f8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH505 0x0ffff5f9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH506 0x0ffff5fa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH507 0x0ffff5fb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH508 0x0ffff5fc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH509 0x0ffff5fd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH510 0x0ffff5fe +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH511 0x0ffff5ff +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH512 0x0ffff600 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH513 0x0ffff601 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH514 0x0ffff602 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH515 0x0ffff603 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH516 0x0ffff604 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH517 0x0ffff605 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH518 0x0ffff606 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH519 0x0ffff607 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH520 0x0ffff608 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH521 0x0ffff609 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH522 0x0ffff60a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH523 0x0ffff60b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH524 0x0ffff60c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH525 0x0ffff60d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH526 0x0ffff60e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH527 0x0ffff60f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH528 0x0ffff610 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH529 0x0ffff611 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH530 0x0ffff612 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH531 0x0ffff613 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH532 0x0ffff614 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH533 0x0ffff615 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH534 0x0ffff616 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH535 0x0ffff617 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH536 0x0ffff618 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH537 0x0ffff619 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH538 0x0ffff61a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH539 0x0ffff61b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH540 0x0ffff61c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH541 0x0ffff61d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH542 0x0ffff61e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH543 0x0ffff61f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH544 0x0ffff620 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH545 0x0ffff621 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH546 0x0ffff622 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH547 0x0ffff623 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH548 0x0ffff624 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH549 0x0ffff625 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH550 0x0ffff626 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH551 0x0ffff627 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH552 0x0ffff628 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH553 0x0ffff629 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH554 0x0ffff62a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH555 0x0ffff62b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH556 0x0ffff62c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH557 0x0ffff62d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH558 0x0ffff62e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH559 0x0ffff62f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH560 0x0ffff630 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH561 0x0ffff631 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH562 0x0ffff632 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH563 0x0ffff633 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH564 0x0ffff634 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH565 0x0ffff635 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH566 0x0ffff636 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH567 0x0ffff637 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH568 0x0ffff638 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH569 0x0ffff639 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH570 0x0ffff63a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH571 0x0ffff63b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH572 0x0ffff63c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH573 0x0ffff63d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH574 0x0ffff63e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH575 0x0ffff63f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH576 0x0ffff640 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH577 0x0ffff641 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH578 0x0ffff642 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH579 0x0ffff643 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH580 0x0ffff644 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH581 0x0ffff645 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH582 0x0ffff646 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH583 0x0ffff647 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH584 0x0ffff648 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH585 0x0ffff649 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH586 0x0ffff64a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH587 0x0ffff64b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH588 0x0ffff64c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH589 0x0ffff64d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH590 0x0ffff64e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH591 0x0ffff64f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH592 0x0ffff650 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH593 0x0ffff651 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH594 0x0ffff652 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH595 0x0ffff653 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH596 0x0ffff654 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH597 0x0ffff655 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH598 0x0ffff656 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH599 0x0ffff657 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH600 0x0ffff658 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH601 0x0ffff659 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH602 0x0ffff65a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH603 0x0ffff65b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH604 0x0ffff65c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH605 0x0ffff65d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH606 0x0ffff65e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH607 0x0ffff65f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH608 0x0ffff660 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH609 0x0ffff661 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH610 0x0ffff662 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH611 0x0ffff663 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH612 0x0ffff664 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH613 0x0ffff665 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH614 0x0ffff666 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH615 0x0ffff667 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH616 0x0ffff668 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH617 0x0ffff669 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH618 0x0ffff66a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH619 0x0ffff66b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH620 0x0ffff66c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH621 0x0ffff66d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH622 0x0ffff66e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH623 0x0ffff66f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH624 0x0ffff670 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH625 0x0ffff671 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH626 0x0ffff672 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH627 0x0ffff673 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH628 0x0ffff674 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH629 0x0ffff675 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH630 0x0ffff676 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH631 0x0ffff677 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH632 0x0ffff678 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH633 0x0ffff679 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH634 0x0ffff67a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH635 0x0ffff67b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH636 0x0ffff67c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH637 0x0ffff67d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH638 0x0ffff67e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH639 0x0ffff67f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH640 0x0ffff680 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH641 0x0ffff681 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH642 0x0ffff682 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH643 0x0ffff683 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH644 0x0ffff684 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH645 0x0ffff685 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH646 0x0ffff686 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH647 0x0ffff687 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH648 0x0ffff688 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH649 0x0ffff689 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH650 0x0ffff68a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH651 0x0ffff68b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH652 0x0ffff68c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH653 0x0ffff68d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH654 0x0ffff68e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH655 0x0ffff68f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH656 0x0ffff690 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH657 0x0ffff691 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH658 0x0ffff692 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH659 0x0ffff693 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH660 0x0ffff694 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH661 0x0ffff695 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH662 0x0ffff696 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH663 0x0ffff697 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH664 0x0ffff698 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH665 0x0ffff699 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH666 0x0ffff69a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH667 0x0ffff69b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH668 0x0ffff69c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH669 0x0ffff69d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH670 0x0ffff69e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH671 0x0ffff69f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH672 0x0ffff6a0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH673 0x0ffff6a1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH674 0x0ffff6a2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH675 0x0ffff6a3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH676 0x0ffff6a4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH677 0x0ffff6a5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH678 0x0ffff6a6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH679 0x0ffff6a7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH680 0x0ffff6a8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH681 0x0ffff6a9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH682 0x0ffff6aa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH683 0x0ffff6ab +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH684 0x0ffff6ac +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH685 0x0ffff6ad +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH686 0x0ffff6ae +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH687 0x0ffff6af +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH688 0x0ffff6b0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH689 0x0ffff6b1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH690 0x0ffff6b2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH691 0x0ffff6b3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH692 0x0ffff6b4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH693 0x0ffff6b5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH694 0x0ffff6b6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH695 0x0ffff6b7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH696 0x0ffff6b8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH697 0x0ffff6b9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH698 0x0ffff6ba +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH699 0x0ffff6bb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH700 0x0ffff6bc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH701 0x0ffff6bd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH702 0x0ffff6be +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH703 0x0ffff6bf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH704 0x0ffff6c0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH705 0x0ffff6c1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH706 0x0ffff6c2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH707 0x0ffff6c3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH708 0x0ffff6c4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH709 0x0ffff6c5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH710 0x0ffff6c6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH711 0x0ffff6c7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH712 0x0ffff6c8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH713 0x0ffff6c9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH714 0x0ffff6ca +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH715 0x0ffff6cb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH716 0x0ffff6cc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH717 0x0ffff6cd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH718 0x0ffff6ce +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH719 0x0ffff6cf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH720 0x0ffff6d0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH721 0x0ffff6d1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH722 0x0ffff6d2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH723 0x0ffff6d3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH724 0x0ffff6d4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH725 0x0ffff6d5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH726 0x0ffff6d6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH727 0x0ffff6d7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH728 0x0ffff6d8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH729 0x0ffff6d9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH730 0x0ffff6da +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH731 0x0ffff6db +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH732 0x0ffff6dc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH733 0x0ffff6dd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH734 0x0ffff6de +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH735 0x0ffff6df +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH736 0x0ffff6e0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH737 0x0ffff6e1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH738 0x0ffff6e2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH739 0x0ffff6e3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH740 0x0ffff6e4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH741 0x0ffff6e5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH742 0x0ffff6e6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH743 0x0ffff6e7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH744 0x0ffff6e8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH745 0x0ffff6e9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH746 0x0ffff6ea +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH747 0x0ffff6eb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH748 0x0ffff6ec +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH749 0x0ffff6ed +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH750 0x0ffff6ee +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH751 0x0ffff6ef +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH752 0x0ffff6f0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH753 0x0ffff6f1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH754 0x0ffff6f2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH755 0x0ffff6f3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH756 0x0ffff6f4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH757 0x0ffff6f5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH758 0x0ffff6f6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH759 0x0ffff6f7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH760 0x0ffff6f8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH761 0x0ffff6f9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH762 0x0ffff6fa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH763 0x0ffff6fb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH764 0x0ffff6fc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH765 0x0ffff6fd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH766 0x0ffff6fe +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH767 0x0ffff6ff +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH768 0x0ffff700 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH769 0x0ffff701 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH770 0x0ffff702 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH771 0x0ffff703 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH772 0x0ffff704 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH773 0x0ffff705 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH774 0x0ffff706 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH775 0x0ffff707 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH776 0x0ffff708 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH777 0x0ffff709 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH778 0x0ffff70a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH779 0x0ffff70b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH780 0x0ffff70c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH781 0x0ffff70d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH782 0x0ffff70e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH783 0x0ffff70f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH784 0x0ffff710 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH785 0x0ffff711 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH786 0x0ffff712 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH787 0x0ffff713 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH788 0x0ffff714 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH789 0x0ffff715 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH790 0x0ffff716 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH791 0x0ffff717 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH792 0x0ffff718 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH793 0x0ffff719 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH794 0x0ffff71a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH795 0x0ffff71b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH796 0x0ffff71c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH797 0x0ffff71d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH798 0x0ffff71e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH799 0x0ffff71f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH800 0x0ffff720 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH801 0x0ffff721 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH802 0x0ffff722 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH803 0x0ffff723 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH804 0x0ffff724 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH805 0x0ffff725 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH806 0x0ffff726 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH807 0x0ffff727 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH808 0x0ffff728 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH809 0x0ffff729 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH810 0x0ffff72a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH811 0x0ffff72b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH812 0x0ffff72c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH813 0x0ffff72d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH814 0x0ffff72e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH815 0x0ffff72f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH816 0x0ffff730 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH817 0x0ffff731 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH818 0x0ffff732 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH819 0x0ffff733 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH820 0x0ffff734 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH821 0x0ffff735 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH822 0x0ffff736 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH823 0x0ffff737 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH824 0x0ffff738 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH825 0x0ffff739 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH826 0x0ffff73a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH827 0x0ffff73b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH828 0x0ffff73c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH829 0x0ffff73d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH830 0x0ffff73e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH831 0x0ffff73f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH832 0x0ffff740 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH833 0x0ffff741 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH834 0x0ffff742 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH835 0x0ffff743 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH836 0x0ffff744 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH837 0x0ffff745 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH838 0x0ffff746 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH839 0x0ffff747 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH840 0x0ffff748 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH841 0x0ffff749 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH842 0x0ffff74a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH843 0x0ffff74b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH844 0x0ffff74c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH845 0x0ffff74d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH846 0x0ffff74e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH847 0x0ffff74f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH848 0x0ffff750 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH849 0x0ffff751 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH850 0x0ffff752 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH851 0x0ffff753 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH852 0x0ffff754 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH853 0x0ffff755 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH854 0x0ffff756 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH855 0x0ffff757 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH856 0x0ffff758 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH857 0x0ffff759 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH858 0x0ffff75a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH859 0x0ffff75b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH860 0x0ffff75c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH861 0x0ffff75d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH862 0x0ffff75e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH863 0x0ffff75f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH864 0x0ffff760 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH865 0x0ffff761 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH866 0x0ffff762 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH867 0x0ffff763 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH868 0x0ffff764 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH869 0x0ffff765 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH870 0x0ffff766 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH871 0x0ffff767 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH872 0x0ffff768 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH873 0x0ffff769 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH874 0x0ffff76a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH875 0x0ffff76b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH876 0x0ffff76c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH877 0x0ffff76d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH878 0x0ffff76e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH879 0x0ffff76f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH880 0x0ffff770 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH881 0x0ffff771 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH882 0x0ffff772 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH883 0x0ffff773 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH884 0x0ffff774 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH885 0x0ffff775 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH886 0x0ffff776 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH887 0x0ffff777 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH888 0x0ffff778 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH889 0x0ffff779 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH890 0x0ffff77a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH891 0x0ffff77b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH892 0x0ffff77c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH893 0x0ffff77d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH894 0x0ffff77e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH895 0x0ffff77f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH896 0x0ffff780 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH897 0x0ffff781 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH898 0x0ffff782 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH899 0x0ffff783 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH900 0x0ffff784 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH901 0x0ffff785 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH902 0x0ffff786 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH903 0x0ffff787 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH904 0x0ffff788 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH905 0x0ffff789 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH906 0x0ffff78a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH907 0x0ffff78b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH908 0x0ffff78c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH909 0x0ffff78d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH910 0x0ffff78e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH911 0x0ffff78f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH912 0x0ffff790 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH913 0x0ffff791 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH914 0x0ffff792 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH915 0x0ffff793 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH916 0x0ffff794 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH917 0x0ffff795 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH918 0x0ffff796 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH919 0x0ffff797 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH920 0x0ffff798 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH921 0x0ffff799 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH922 0x0ffff79a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH923 0x0ffff79b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH924 0x0ffff79c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH925 0x0ffff79d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH926 0x0ffff79e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH927 0x0ffff79f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH928 0x0ffff7a0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH929 0x0ffff7a1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH930 0x0ffff7a2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH931 0x0ffff7a3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH932 0x0ffff7a4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH933 0x0ffff7a5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH934 0x0ffff7a6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH935 0x0ffff7a7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH936 0x0ffff7a8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH937 0x0ffff7a9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH938 0x0ffff7aa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH939 0x0ffff7ab +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH940 0x0ffff7ac +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH941 0x0ffff7ad +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH942 0x0ffff7ae +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH943 0x0ffff7af +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH944 0x0ffff7b0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH945 0x0ffff7b1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH946 0x0ffff7b2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH947 0x0ffff7b3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH948 0x0ffff7b4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH949 0x0ffff7b5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH950 0x0ffff7b6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH951 0x0ffff7b7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH952 0x0ffff7b8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH953 0x0ffff7b9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH954 0x0ffff7ba +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH955 0x0ffff7bb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH956 0x0ffff7bc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH957 0x0ffff7bd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH958 0x0ffff7be +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH959 0x0ffff7bf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH960 0x0ffff7c0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH961 0x0ffff7c1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH962 0x0ffff7c2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH963 0x0ffff7c3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH964 0x0ffff7c4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH965 0x0ffff7c5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH966 0x0ffff7c6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH967 0x0ffff7c7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH968 0x0ffff7c8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH969 0x0ffff7c9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH970 0x0ffff7ca +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH971 0x0ffff7cb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH972 0x0ffff7cc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH973 0x0ffff7cd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH974 0x0ffff7ce +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH975 0x0ffff7cf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH976 0x0ffff7d0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH977 0x0ffff7d1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH978 0x0ffff7d2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH979 0x0ffff7d3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH980 0x0ffff7d4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH981 0x0ffff7d5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH982 0x0ffff7d6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH983 0x0ffff7d7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH984 0x0ffff7d8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH985 0x0ffff7d9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH986 0x0ffff7da +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH987 0x0ffff7db +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH988 0x0ffff7dc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH989 0x0ffff7dd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH990 0x0ffff7de +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH991 0x0ffff7df +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH992 0x0ffff7e0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH993 0x0ffff7e1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH994 0x0ffff7e2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH995 0x0ffff7e3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH996 0x0ffff7e4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH997 0x0ffff7e5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH998 0x0ffff7e6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH999 0x0ffff7e7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1000 0x0ffff7e8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1001 0x0ffff7e9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1002 0x0ffff7ea +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1003 0x0ffff7eb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1004 0x0ffff7ec +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1005 0x0ffff7ed +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1006 0x0ffff7ee +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1007 0x0ffff7ef +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1008 0x0ffff7f0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1009 0x0ffff7f1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1010 0x0ffff7f2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1011 0x0ffff7f3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1012 0x0ffff7f4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1013 0x0ffff7f5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1014 0x0ffff7f6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1015 0x0ffff7f7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1016 0x0ffff7f8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1017 0x0ffff7f9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1018 0x0ffff7fa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1019 0x0ffff7fb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1020 0x0ffff7fc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1021 0x0ffff7fd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1022 0x0ffff7fe +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1023 0x0ffff7ff +#define CYDEV_ROM_BASE 0x10000000 +#define CYDEV_ROM_SIZE 0x00002000 +#define CYREG_ROM_DATA_MBASE 0x10000000 +#define CYREG_ROM_DATA_MSIZE 0x00002000 +#define CYDEV_SRAM_BASE 0x20000000 +#define CYDEV_SRAM_SIZE 0x00004000 +#define CYREG_SRAM_DATA_MBASE 0x20000000 +#define CYREG_SRAM_DATA_MSIZE 0x00004000 +#define CYDEV_PERI_BASE 0x40010000 +#define CYDEV_PERI_SIZE 0x00010000 +#define CYREG_PERI_DIV_CMD 0x40010000 +#define CYFLD_PERI_SEL_DIV__OFFSET 0x00000000 +#define CYFLD_PERI_SEL_DIV__SIZE 0x00000006 +#define CYFLD_PERI_SEL_TYPE__OFFSET 0x00000006 +#define CYFLD_PERI_SEL_TYPE__SIZE 0x00000002 +#define CYFLD_PERI_PA_SEL_DIV__OFFSET 0x00000008 +#define CYFLD_PERI_PA_SEL_DIV__SIZE 0x00000006 +#define CYFLD_PERI_PA_SEL_TYPE__OFFSET 0x0000000e +#define CYFLD_PERI_PA_SEL_TYPE__SIZE 0x00000002 +#define CYFLD_PERI_DISABLE__OFFSET 0x0000001e +#define CYFLD_PERI_DISABLE__SIZE 0x00000001 +#define CYFLD_PERI_ENABLE__OFFSET 0x0000001f +#define CYFLD_PERI_ENABLE__SIZE 0x00000001 +#define CYREG_PERI_PCLK_CTL0 0x40010100 +#define CYREG_PERI_PCLK_CTL1 0x40010104 +#define CYREG_PERI_PCLK_CTL2 0x40010108 +#define CYREG_PERI_PCLK_CTL3 0x4001010c +#define CYREG_PERI_PCLK_CTL4 0x40010110 +#define CYREG_PERI_PCLK_CTL5 0x40010114 +#define CYREG_PERI_PCLK_CTL6 0x40010118 +#define CYREG_PERI_PCLK_CTL7 0x4001011c +#define CYREG_PERI_PCLK_CTL8 0x40010120 +#define CYREG_PERI_PCLK_CTL9 0x40010124 +#define CYREG_PERI_PCLK_CTL10 0x40010128 +#define CYREG_PERI_PCLK_CTL11 0x4001012c +#define CYREG_PERI_PCLK_CTL12 0x40010130 +#define CYREG_PERI_PCLK_CTL13 0x40010134 +#define CYREG_PERI_PCLK_CTL14 0x40010138 +#define CYREG_PERI_PCLK_CTL15 0x4001013c +#define CYREG_PERI_PCLK_CTL16 0x40010140 +#define CYREG_PERI_PCLK_CTL17 0x40010144 +#define CYREG_PERI_PCLK_CTL18 0x40010148 +#define CYREG_PERI_DIV_16_CTL0 0x40010300 +#define CYFLD_PERI_EN__OFFSET 0x00000000 +#define CYFLD_PERI_EN__SIZE 0x00000001 +#define CYFLD_PERI_INT16_DIV__OFFSET 0x00000008 +#define CYFLD_PERI_INT16_DIV__SIZE 0x00000010 +#define CYREG_PERI_DIV_16_CTL1 0x40010304 +#define CYREG_PERI_DIV_16_CTL2 0x40010308 +#define CYREG_PERI_DIV_16_CTL3 0x4001030c +#define CYREG_PERI_DIV_16_CTL4 0x40010310 +#define CYREG_PERI_DIV_16_CTL5 0x40010314 +#define CYREG_PERI_DIV_16_CTL6 0x40010318 +#define CYREG_PERI_DIV_16_CTL7 0x4001031c +#define CYREG_PERI_DIV_16_CTL8 0x40010320 +#define CYREG_PERI_DIV_16_CTL9 0x40010324 +#define CYREG_PERI_DIV_16_CTL10 0x40010328 +#define CYREG_PERI_DIV_16_CTL11 0x4001032c +#define CYREG_PERI_DIV_16_5_CTL0 0x40010400 +#define CYFLD_PERI_FRAC5_DIV__OFFSET 0x00000003 +#define CYFLD_PERI_FRAC5_DIV__SIZE 0x00000005 +#define CYREG_PERI_DIV_16_5_CTL1 0x40010404 +#define CYREG_PERI_DIV_16_5_CTL2 0x40010408 +#define CYREG_PERI_DIV_16_5_CTL3 0x4001040c +#define CYREG_PERI_DIV_16_5_CTL4 0x40010410 +#define CYREG_PERI_DIV_24_5_CTL 0x40010500 +#define CYFLD_PERI_INT24_DIV__OFFSET 0x00000008 +#define CYFLD_PERI_INT24_DIV__SIZE 0x00000018 +#define CYREG_PERI_TR_CTL 0x40010600 +#define CYFLD_PERI_TR_SEL__OFFSET 0x00000000 +#define CYFLD_PERI_TR_SEL__SIZE 0x00000007 +#define CYFLD_PERI_TR_GROUP__OFFSET 0x00000008 +#define CYFLD_PERI_TR_GROUP__SIZE 0x00000004 +#define CYFLD_PERI_TR_COUNT__OFFSET 0x00000010 +#define CYFLD_PERI_TR_COUNT__SIZE 0x00000008 +#define CYFLD_PERI_TR_OUT__OFFSET 0x0000001e +#define CYFLD_PERI_TR_OUT__SIZE 0x00000001 +#define CYFLD_PERI_TR_ACT__OFFSET 0x0000001f +#define CYFLD_PERI_TR_ACT__SIZE 0x00000001 +#define CYDEV_PERI_TR_GROUP0_BASE 0x40012000 +#define CYDEV_PERI_TR_GROUP0_SIZE 0x00000200 +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL0 0x40012000 +#define CYFLD_PERI_TR_GROUP_SEL__OFFSET 0x00000000 +#define CYFLD_PERI_TR_GROUP_SEL__SIZE 0x00000006 +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL1 0x40012004 +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL2 0x40012008 +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL3 0x4001200c +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL4 0x40012010 +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL5 0x40012014 +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL6 0x40012018 +#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL7 0x4001201c +#define CYDEV_PERI_TR_GROUP1_BASE 0x40012200 +#define CYDEV_PERI_TR_GROUP1_SIZE 0x00000200 +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL0 0x40012200 +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL1 0x40012204 +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL2 0x40012208 +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL3 0x4001220c +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL4 0x40012210 +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL5 0x40012214 +#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL6 0x40012218 +#define CYDEV_PERI_TR_GROUP2_BASE 0x40012400 +#define CYDEV_PERI_TR_GROUP2_SIZE 0x00000200 +#define CYREG_PERI_TR_GROUP2_TR_OUT_CTL 0x40012400 +#define CYDEV_PERI_TR_GROUP3_BASE 0x40012600 +#define CYDEV_PERI_TR_GROUP3_SIZE 0x00000200 +#define CYREG_PERI_TR_GROUP3_TR_OUT_CTL 0x40012600 +#define CYDEV_HSIOM_BASE 0x40020000 +#define CYDEV_HSIOM_SIZE 0x00004000 +#define CYREG_HSIOM_PORT_SEL0 0x40020000 +#define CYFLD_HSIOM_IO0_SEL__OFFSET 0x00000000 +#define CYFLD_HSIOM_IO0_SEL__SIZE 0x00000004 +#define CYVAL_HSIOM_IO0_SEL_GPIO 0x00000000 +#define CYVAL_HSIOM_IO0_SEL_GPIO_DSI 0x00000001 +#define CYVAL_HSIOM_IO0_SEL_DSI_DSI 0x00000002 +#define CYVAL_HSIOM_IO0_SEL_DSI_GPIO 0x00000003 +#define CYVAL_HSIOM_IO0_SEL_CSD_SENSE 0x00000004 +#define CYVAL_HSIOM_IO0_SEL_CSD_SHIELD 0x00000005 +#define CYVAL_HSIOM_IO0_SEL_AMUXA 0x00000006 +#define CYVAL_HSIOM_IO0_SEL_AMUXB 0x00000007 +#define CYVAL_HSIOM_IO0_SEL_ACT_0 0x00000008 +#define CYVAL_HSIOM_IO0_SEL_ACT_1 0x00000009 +#define CYVAL_HSIOM_IO0_SEL_ACT_2 0x0000000a +#define CYVAL_HSIOM_IO0_SEL_ACT_3 0x0000000b +#define CYVAL_HSIOM_IO0_SEL_LCD_COM 0x0000000c +#define CYVAL_HSIOM_IO0_SEL_LCD_SEG 0x0000000d +#define CYVAL_HSIOM_IO0_SEL_DS_0 0x0000000c +#define CYVAL_HSIOM_IO0_SEL_DS_1 0x0000000d +#define CYVAL_HSIOM_IO0_SEL_DS_2 0x0000000e +#define CYVAL_HSIOM_IO0_SEL_DS_3 0x0000000f +#define CYFLD_HSIOM_IO1_SEL__OFFSET 0x00000004 +#define CYFLD_HSIOM_IO1_SEL__SIZE 0x00000004 +#define CYFLD_HSIOM_IO2_SEL__OFFSET 0x00000008 +#define CYFLD_HSIOM_IO2_SEL__SIZE 0x00000004 +#define CYFLD_HSIOM_IO3_SEL__OFFSET 0x0000000c +#define CYFLD_HSIOM_IO3_SEL__SIZE 0x00000004 +#define CYFLD_HSIOM_IO4_SEL__OFFSET 0x00000010 +#define CYFLD_HSIOM_IO4_SEL__SIZE 0x00000004 +#define CYFLD_HSIOM_IO5_SEL__OFFSET 0x00000014 +#define CYFLD_HSIOM_IO5_SEL__SIZE 0x00000004 +#define CYFLD_HSIOM_IO6_SEL__OFFSET 0x00000018 +#define CYFLD_HSIOM_IO6_SEL__SIZE 0x00000004 +#define CYFLD_HSIOM_IO7_SEL__OFFSET 0x0000001c +#define CYFLD_HSIOM_IO7_SEL__SIZE 0x00000004 +#define CYREG_HSIOM_PORT_SEL1 0x40020100 +#define CYREG_HSIOM_PORT_SEL2 0x40020200 +#define CYREG_HSIOM_PORT_SEL3 0x40020300 +#define CYREG_HSIOM_PORT_SEL4 0x40020400 +#define CYREG_HSIOM_PORT_SEL5 0x40020500 +#define CYREG_HSIOM_PORT_SEL6 0x40020600 +#define CYREG_HSIOM_PORT_SEL7 0x40020700 +#define CYREG_HSIOM_AMUX_SPLIT_CTL0 0x40022100 +#define CYFLD_HSIOM_SWITCH_AA_SL__OFFSET 0x00000000 +#define CYFLD_HSIOM_SWITCH_AA_SL__SIZE 0x00000001 +#define CYFLD_HSIOM_SWITCH_AA_SR__OFFSET 0x00000001 +#define CYFLD_HSIOM_SWITCH_AA_SR__SIZE 0x00000001 +#define CYFLD_HSIOM_SWITCH_AA_S0__OFFSET 0x00000002 +#define CYFLD_HSIOM_SWITCH_AA_S0__SIZE 0x00000001 +#define CYFLD_HSIOM_SWITCH_BB_SL__OFFSET 0x00000004 +#define CYFLD_HSIOM_SWITCH_BB_SL__SIZE 0x00000001 +#define CYFLD_HSIOM_SWITCH_BB_SR__OFFSET 0x00000005 +#define CYFLD_HSIOM_SWITCH_BB_SR__SIZE 0x00000001 +#define CYFLD_HSIOM_SWITCH_BB_S0__OFFSET 0x00000006 +#define CYFLD_HSIOM_SWITCH_BB_S0__SIZE 0x00000001 +#define CYREG_HSIOM_AMUX_SPLIT_CTL1 0x40022104 +#define CYREG_PWR_CONTROL 0x40030000 +#define CYFLD__POWER_MODE__OFFSET 0x00000000 +#define CYFLD__POWER_MODE__SIZE 0x00000004 +#define CYVAL__POWER_MODE_RESET 0x00000000 +#define CYVAL__POWER_MODE_ACTIVE 0x00000001 +#define CYVAL__POWER_MODE_SLEEP 0x00000002 +#define CYVAL__POWER_MODE_DEEP_SLEEP 0x00000003 +#define CYFLD__DEBUG_SESSION__OFFSET 0x00000004 +#define CYFLD__DEBUG_SESSION__SIZE 0x00000001 +#define CYVAL__DEBUG_SESSION_NO_SESSION 0x00000000 +#define CYVAL__DEBUG_SESSION_SESSION_ACTIVE 0x00000001 +#define CYFLD__LPM_READY__OFFSET 0x00000005 +#define CYFLD__LPM_READY__SIZE 0x00000001 +#define CYFLD__OVER_TEMP_EN__OFFSET 0x00000010 +#define CYFLD__OVER_TEMP_EN__SIZE 0x00000001 +#define CYFLD__OVER_TEMP_THRESH__OFFSET 0x00000011 +#define CYFLD__OVER_TEMP_THRESH__SIZE 0x00000001 +#define CYFLD__SPARE__OFFSET 0x00000012 +#define CYFLD__SPARE__SIZE 0x00000002 +#define CYFLD__EXT_VCCD__OFFSET 0x00000017 +#define CYFLD__EXT_VCCD__SIZE 0x00000001 +#define CYREG_PWR_KEY_DELAY 0x40030004 +#define CYFLD__WAKEUP_HOLDOFF__OFFSET 0x00000000 +#define CYFLD__WAKEUP_HOLDOFF__SIZE 0x0000000a +#define CYREG_PWR_DDFT_SELECT 0x4003000c +#define CYFLD__DDFT0_SEL__OFFSET 0x00000000 +#define CYFLD__DDFT0_SEL__SIZE 0x00000004 +#define CYVAL__DDFT0_SEL_WAKEUP 0x00000000 +#define CYVAL__DDFT0_SEL_AWAKE 0x00000001 +#define CYVAL__DDFT0_SEL_ACT_POWER_EN 0x00000002 +#define CYVAL__DDFT0_SEL_ACT_POWER_UP 0x00000003 +#define CYVAL__DDFT0_SEL_ACT_POWER_GOOD 0x00000004 +#define CYVAL__DDFT0_SEL_ACT_REF_EN 0x00000005 +#define CYVAL__DDFT0_SEL_ACT_COMP_EN 0x00000006 +#define CYVAL__DDFT0_SEL_DPSLP_REF_EN 0x00000007 +#define CYVAL__DDFT0_SEL_DPSLP_REG_EN 0x00000008 +#define CYVAL__DDFT0_SEL_DPSLP_COMP_EN 0x00000009 +#define CYVAL__DDFT0_SEL_OVER_TEMP_EN 0x0000000a +#define CYVAL__DDFT0_SEL_SLEEPHOLDREQ_N 0x0000000b +#define CYVAL__DDFT0_SEL_ADFT_BUF_EN 0x0000000c +#define CYVAL__DDFT0_SEL_ATPG_OBSERVE 0x0000000d +#define CYVAL__DDFT0_SEL_GND 0x0000000e +#define CYVAL__DDFT0_SEL_PWR 0x0000000f +#define CYFLD__DDFT1_SEL__OFFSET 0x00000004 +#define CYFLD__DDFT1_SEL__SIZE 0x00000004 +#define CYVAL__DDFT1_SEL_WAKEUP 0x00000000 +#define CYVAL__DDFT1_SEL_AWAKE 0x00000001 +#define CYVAL__DDFT1_SEL_ACT_POWER_EN 0x00000002 +#define CYVAL__DDFT1_SEL_ACT_POWER_UP 0x00000003 +#define CYVAL__DDFT1_SEL_ACT_POWER_GOOD 0x00000004 +#define CYVAL__DDFT1_SEL_ACT_REF_VALID 0x00000005 +#define CYVAL__DDFT1_SEL_ACT_REG_VALID 0x00000006 +#define CYVAL__DDFT1_SEL_ACT_COMP_OUT 0x00000007 +#define CYVAL__DDFT1_SEL_ACT_TEMP_HIGH 0x00000008 +#define CYVAL__DDFT1_SEL_DPSLP_COMP_OUT 0x00000009 +#define CYVAL__DDFT1_SEL_DPSLP_POWER_UP 0x0000000a +#define CYVAL__DDFT1_SEL_AWAKE_DELAYED 0x0000000b +#define CYVAL__DDFT1_SEL_LPM_READY 0x0000000c +#define CYVAL__DDFT1_SEL_SLEEPHOLDACK_N 0x0000000d +#define CYVAL__DDFT1_SEL_GND 0x0000000e +#define CYVAL__DDFT1_SEL_PWR 0x0000000f +#define CYREG_TST_MODE 0x40030014 +#define CYFLD__SWD_CONNECTED__OFFSET 0x00000002 +#define CYFLD__SWD_CONNECTED__SIZE 0x00000001 +#define CYFLD__BLOCK_ALT_XRES__OFFSET 0x0000001c +#define CYFLD__BLOCK_ALT_XRES__SIZE 0x00000001 +#define CYFLD__TEST_KEY_DFT_EN__OFFSET 0x0000001e +#define CYFLD__TEST_KEY_DFT_EN__SIZE 0x00000001 +#define CYFLD__TEST_MODE__OFFSET 0x0000001f +#define CYFLD__TEST_MODE__SIZE 0x00000001 +#define CYREG_TST_DDFT_CTRL 0x40030018 +#define CYFLD__DFT_SEL0__OFFSET 0x00000000 +#define CYFLD__DFT_SEL0__SIZE 0x00000004 +#define CYVAL__DFT_SEL0_SRC0 0x00000000 +#define CYVAL__DFT_SEL0_SRC1 0x00000001 +#define CYVAL__DFT_SEL0_SRC2 0x00000002 +#define CYVAL__DFT_SEL0_SRC3 0x00000003 +#define CYVAL__DFT_SEL0_SRC4 0x00000004 +#define CYVAL__DFT_SEL0_SRC5 0x00000005 +#define CYVAL__DFT_SEL0_SRC6 0x00000006 +#define CYVAL__DFT_SEL0_SRC7 0x00000007 +#define CYVAL__DFT_SEL0_CLK0 0x00000008 +#define CYVAL__DFT_SEL0_CLK1 0x00000009 +#define CYVAL__DFT_SEL0_PWR0 0x0000000a +#define CYVAL__DFT_SEL0_PWR1 0x0000000b +#define CYVAL__DFT_SEL0_RES0 0x0000000c +#define CYVAL__DFT_SEL0_RES1 0x0000000d +#define CYVAL__DFT_SEL0_ADFT_COMP 0x0000000e +#define CYVAL__DFT_SEL0_VSS 0x0000000f +#define CYFLD__DFT_SEL1__OFFSET 0x00000008 +#define CYFLD__DFT_SEL1__SIZE 0x00000004 +#define CYVAL__DFT_SEL1_SRC0 0x00000000 +#define CYVAL__DFT_SEL1_SRC1 0x00000001 +#define CYVAL__DFT_SEL1_SRC2 0x00000002 +#define CYVAL__DFT_SEL1_SRC3 0x00000003 +#define CYVAL__DFT_SEL1_SRC4 0x00000004 +#define CYVAL__DFT_SEL1_SRC5 0x00000005 +#define CYVAL__DFT_SEL1_SRC6 0x00000006 +#define CYVAL__DFT_SEL1_SRC7 0x00000007 +#define CYVAL__DFT_SEL1_CLK0 0x00000008 +#define CYVAL__DFT_SEL1_CLK1 0x00000009 +#define CYVAL__DFT_SEL1_PWR0 0x0000000a +#define CYVAL__DFT_SEL1_PWR1 0x0000000b +#define CYVAL__DFT_SEL1_RES0 0x0000000c +#define CYVAL__DFT_SEL1_RES1 0x0000000d +#define CYVAL__DFT_SEL1_ADFT_COMP 0x0000000e +#define CYVAL__DFT_SEL1_VSS 0x0000000f +#define CYFLD__ENABLE__OFFSET 0x0000001f +#define CYFLD__ENABLE__SIZE 0x00000001 +#define CYREG_TST_TRIM_CNTR1 0x4003001c +#define CYFLD__COUNTER__OFFSET 0x00000000 +#define CYFLD__COUNTER__SIZE 0x00000010 +#define CYFLD__COUNTER_DONE__OFFSET 0x0000001f +#define CYFLD__COUNTER_DONE__SIZE 0x00000001 +#define CYREG_TST_TRIM_CNTR2 0x40030020 +#define CYREG_TST_ADFT_CTRL 0x40030024 +#define CYFLD__BUF_AUTO_ZERO__OFFSET 0x00000000 +#define CYFLD__BUF_AUTO_ZERO__SIZE 0x00000001 +#define CYFLD__BUF_MODE__OFFSET 0x00000008 +#define CYFLD__BUF_MODE__SIZE 0x00000002 +#define CYFLD__BUF_COMP_OUT__OFFSET 0x00000010 +#define CYFLD__BUF_COMP_OUT__SIZE 0x00000001 +#define CYFLD__BUF_EN__OFFSET 0x0000001f +#define CYFLD__BUF_EN__SIZE 0x00000001 +#define CYREG_CLK_SELECT 0x40030028 +#define CYFLD__HFCLK_SEL__OFFSET 0x00000000 +#define CYFLD__HFCLK_SEL__SIZE 0x00000002 +#define CYVAL__HFCLK_SEL_IMO 0x00000000 +#define CYVAL__HFCLK_SEL_EXTCLK 0x00000001 +#define CYVAL__HFCLK_SEL_ECO 0x00000002 +#define CYFLD__HFCLK_DIV__OFFSET 0x00000002 +#define CYFLD__HFCLK_DIV__SIZE 0x00000002 +#define CYVAL__HFCLK_DIV_NO_DIV 0x00000000 +#define CYVAL__HFCLK_DIV_DIV_BY_2 0x00000001 +#define CYVAL__HFCLK_DIV_DIV_BY_4 0x00000002 +#define CYVAL__HFCLK_DIV_DIV_BY_8 0x00000003 +#define CYFLD__PUMP_SEL__OFFSET 0x00000004 +#define CYFLD__PUMP_SEL__SIZE 0x00000002 +#define CYVAL__PUMP_SEL_GND 0x00000000 +#define CYVAL__PUMP_SEL_IMO 0x00000001 +#define CYVAL__PUMP_SEL_HFCLK 0x00000002 +#define CYFLD__SYSCLK_DIV__OFFSET 0x00000006 +#define CYFLD__SYSCLK_DIV__SIZE 0x00000002 +#define CYVAL__SYSCLK_DIV_NO_DIV 0x00000000 +#define CYVAL__SYSCLK_DIV_DIV_BY_2 0x00000001 +#define CYVAL__SYSCLK_DIV_DIV_BY_4 0x00000002 +#define CYVAL__SYSCLK_DIV_DIV_BY_8 0x00000003 +#define CYREG_CLK_ILO_CONFIG 0x4003002c +#define CYREG_CLK_IMO_CONFIG 0x40030030 +#define CYREG_CLK_DFT_SELECT 0x40030034 +#define CYFLD__DFT_DIV0__OFFSET 0x00000004 +#define CYFLD__DFT_DIV0__SIZE 0x00000002 +#define CYVAL__DFT_DIV0_NO_DIV 0x00000000 +#define CYVAL__DFT_DIV0_DIV_BY_2 0x00000001 +#define CYVAL__DFT_DIV0_DIV_BY_4 0x00000002 +#define CYVAL__DFT_DIV0_DIV_BY_8 0x00000003 +#define CYFLD__DFT_EDGE0__OFFSET 0x00000006 +#define CYFLD__DFT_EDGE0__SIZE 0x00000001 +#define CYVAL__DFT_EDGE0_POSEDGE 0x00000000 +#define CYVAL__DFT_EDGE0_NEGEDGE 0x00000001 +#define CYFLD__DFT_DIV1__OFFSET 0x0000000c +#define CYFLD__DFT_DIV1__SIZE 0x00000002 +#define CYVAL__DFT_DIV1_NO_DIV 0x00000000 +#define CYVAL__DFT_DIV1_DIV_BY_2 0x00000001 +#define CYVAL__DFT_DIV1_DIV_BY_4 0x00000002 +#define CYVAL__DFT_DIV1_DIV_BY_8 0x00000003 +#define CYFLD__DFT_EDGE1__OFFSET 0x0000000e +#define CYFLD__DFT_EDGE1__SIZE 0x00000001 +#define CYVAL__DFT_EDGE1_POSEDGE 0x00000000 +#define CYVAL__DFT_EDGE1_NEGEDGE 0x00000001 +#define CYREG_WDT_DISABLE_KEY 0x40030038 +#define CYFLD__KEY__OFFSET 0x00000000 +#define CYFLD__KEY__SIZE 0x00000020 +#define CYREG_WDT_COUNTER 0x4003003c +#define CYREG_WDT_MATCH 0x40030040 +#define CYFLD__MATCH__OFFSET 0x00000000 +#define CYFLD__MATCH__SIZE 0x00000010 +#define CYFLD__IGNORE_BITS__OFFSET 0x00000010 +#define CYFLD__IGNORE_BITS__SIZE 0x00000004 +#define CYREG_SRSS_INTR 0x40030044 +#define CYFLD__WDT_MATCH__OFFSET 0x00000000 +#define CYFLD__WDT_MATCH__SIZE 0x00000001 +#define CYFLD__TEMP_HIGH__OFFSET 0x00000001 +#define CYFLD__TEMP_HIGH__SIZE 0x00000001 +#define CYREG_SRSS_INTR_SET 0x40030048 +#define CYREG_SRSS_INTR_MASK 0x4003004c +#define CYREG_RES_CAUSE 0x40030054 +#define CYFLD__RESET_WDT__OFFSET 0x00000000 +#define CYFLD__RESET_WDT__SIZE 0x00000001 +#define CYFLD__RESET_PROT_FAULT__OFFSET 0x00000003 +#define CYFLD__RESET_PROT_FAULT__SIZE 0x00000001 +#define CYFLD__RESET_SOFT__OFFSET 0x00000004 +#define CYFLD__RESET_SOFT__SIZE 0x00000001 +#define CYREG_PWR_BG_TRIM1 0x40030f00 +#define CYFLD__REF_VTRIM__OFFSET 0x00000000 +#define CYFLD__REF_VTRIM__SIZE 0x00000006 +#define CYREG_PWR_BG_TRIM2 0x40030f04 +#define CYFLD__REF_ITRIM__OFFSET 0x00000000 +#define CYFLD__REF_ITRIM__SIZE 0x00000006 +#define CYREG_CLK_IMO_SELECT 0x40030f08 +#define CYFLD__FREQ__OFFSET 0x00000000 +#define CYFLD__FREQ__SIZE 0x00000003 +#define CYVAL__FREQ_24_MHZ 0x00000000 +#define CYVAL__FREQ_28_MHZ 0x00000001 +#define CYVAL__FREQ_32_MHZ 0x00000002 +#define CYVAL__FREQ_36_MHZ 0x00000003 +#define CYVAL__FREQ_40_MHZ 0x00000004 +#define CYVAL__FREQ_44_MHZ 0x00000005 +#define CYVAL__FREQ_48_MHZ 0x00000006 +#define CYREG_CLK_IMO_TRIM1 0x40030f0c +#define CYFLD__OFFSET__OFFSET 0x00000000 +#define CYFLD__OFFSET__SIZE 0x00000008 +#define CYREG_CLK_IMO_TRIM2 0x40030f10 +#define CYFLD__FSOFFSET__OFFSET 0x00000000 +#define CYFLD__FSOFFSET__SIZE 0x00000003 +#define CYREG_PWR_PWRSYS_TRIM1 0x40030f14 +#define CYFLD__DPSLP_REF_TRIM__OFFSET 0x00000000 +#define CYFLD__DPSLP_REF_TRIM__SIZE 0x00000004 +#define CYFLD__SPARE_TRIM__OFFSET 0x00000004 +#define CYFLD__SPARE_TRIM__SIZE 0x00000004 +#define CYREG_CLK_IMO_TRIM3 0x40030f18 +#define CYFLD__STEPSIZE__OFFSET 0x00000000 +#define CYFLD__STEPSIZE__SIZE 0x00000005 +#define CYFLD__TCTRIM__OFFSET 0x00000005 +#define CYFLD__TCTRIM__SIZE 0x00000002 +#define CYDEV_GPIO_BASE 0x40040000 +#define CYDEV_GPIO_SIZE 0x00004000 +#define CYDEV_GPIO_PRT0_BASE 0x40040000 +#define CYDEV_GPIO_PRT0_SIZE 0x00000100 +#define CYREG_GPIO_PRT0_DR 0x40040000 +#define CYFLD_GPIO_PRT_DATA0__OFFSET 0x00000000 +#define CYFLD_GPIO_PRT_DATA0__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_DATA1__OFFSET 0x00000001 +#define CYFLD_GPIO_PRT_DATA1__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_DATA2__OFFSET 0x00000002 +#define CYFLD_GPIO_PRT_DATA2__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_DATA3__OFFSET 0x00000003 +#define CYFLD_GPIO_PRT_DATA3__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_DATA4__OFFSET 0x00000004 +#define CYFLD_GPIO_PRT_DATA4__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_DATA5__OFFSET 0x00000005 +#define CYFLD_GPIO_PRT_DATA5__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_DATA6__OFFSET 0x00000006 +#define CYFLD_GPIO_PRT_DATA6__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_DATA7__OFFSET 0x00000007 +#define CYFLD_GPIO_PRT_DATA7__SIZE 0x00000001 +#define CYREG_GPIO_PRT0_PS 0x40040004 +#define CYFLD_GPIO_PRT_FLT_DATA__OFFSET 0x00000008 +#define CYFLD_GPIO_PRT_FLT_DATA__SIZE 0x00000001 +#define CYREG_GPIO_PRT0_PC 0x40040008 +#define CYFLD_GPIO_PRT_DM0__OFFSET 0x00000000 +#define CYFLD_GPIO_PRT_DM0__SIZE 0x00000003 +#define CYVAL_GPIO_PRT_DM0_OFF 0x00000000 +#define CYVAL_GPIO_PRT_DM0_INPUT 0x00000001 +#define CYVAL_GPIO_PRT_DM0_0_PU 0x00000002 +#define CYVAL_GPIO_PRT_DM0_PD_1 0x00000003 +#define CYVAL_GPIO_PRT_DM0_0_Z 0x00000004 +#define CYVAL_GPIO_PRT_DM0_Z_1 0x00000005 +#define CYVAL_GPIO_PRT_DM0_0_1 0x00000006 +#define CYVAL_GPIO_PRT_DM0_PD_PU 0x00000007 +#define CYFLD_GPIO_PRT_DM1__OFFSET 0x00000003 +#define CYFLD_GPIO_PRT_DM1__SIZE 0x00000003 +#define CYFLD_GPIO_PRT_DM2__OFFSET 0x00000006 +#define CYFLD_GPIO_PRT_DM2__SIZE 0x00000003 +#define CYFLD_GPIO_PRT_DM3__OFFSET 0x00000009 +#define CYFLD_GPIO_PRT_DM3__SIZE 0x00000003 +#define CYFLD_GPIO_PRT_DM4__OFFSET 0x0000000c +#define CYFLD_GPIO_PRT_DM4__SIZE 0x00000003 +#define CYFLD_GPIO_PRT_DM5__OFFSET 0x0000000f +#define CYFLD_GPIO_PRT_DM5__SIZE 0x00000003 +#define CYFLD_GPIO_PRT_DM6__OFFSET 0x00000012 +#define CYFLD_GPIO_PRT_DM6__SIZE 0x00000003 +#define CYFLD_GPIO_PRT_DM7__OFFSET 0x00000015 +#define CYFLD_GPIO_PRT_DM7__SIZE 0x00000003 +#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__OFFSET 0x00000018 +#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_PORT_SLOW__OFFSET 0x00000019 +#define CYFLD_GPIO_PRT_PORT_SLOW__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__OFFSET 0x0000001e +#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__SIZE 0x00000002 +#define CYREG_GPIO_PRT0_INTR_CFG 0x4004000c +#define CYFLD_GPIO_PRT_EDGE0_SEL__OFFSET 0x00000000 +#define CYFLD_GPIO_PRT_EDGE0_SEL__SIZE 0x00000002 +#define CYVAL_GPIO_PRT_EDGE0_SEL_DISABLE 0x00000000 +#define CYVAL_GPIO_PRT_EDGE0_SEL_RISING 0x00000001 +#define CYVAL_GPIO_PRT_EDGE0_SEL_FALLING 0x00000002 +#define CYVAL_GPIO_PRT_EDGE0_SEL_BOTH 0x00000003 +#define CYFLD_GPIO_PRT_EDGE1_SEL__OFFSET 0x00000002 +#define CYFLD_GPIO_PRT_EDGE1_SEL__SIZE 0x00000002 +#define CYFLD_GPIO_PRT_EDGE2_SEL__OFFSET 0x00000004 +#define CYFLD_GPIO_PRT_EDGE2_SEL__SIZE 0x00000002 +#define CYFLD_GPIO_PRT_EDGE3_SEL__OFFSET 0x00000006 +#define CYFLD_GPIO_PRT_EDGE3_SEL__SIZE 0x00000002 +#define CYFLD_GPIO_PRT_EDGE4_SEL__OFFSET 0x00000008 +#define CYFLD_GPIO_PRT_EDGE4_SEL__SIZE 0x00000002 +#define CYFLD_GPIO_PRT_EDGE5_SEL__OFFSET 0x0000000a +#define CYFLD_GPIO_PRT_EDGE5_SEL__SIZE 0x00000002 +#define CYFLD_GPIO_PRT_EDGE6_SEL__OFFSET 0x0000000c +#define CYFLD_GPIO_PRT_EDGE6_SEL__SIZE 0x00000002 +#define CYFLD_GPIO_PRT_EDGE7_SEL__OFFSET 0x0000000e +#define CYFLD_GPIO_PRT_EDGE7_SEL__SIZE 0x00000002 +#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__OFFSET 0x00000010 +#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__SIZE 0x00000002 +#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_DISABLE 0x00000000 +#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_RISING 0x00000001 +#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_FALLING 0x00000002 +#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_BOTH 0x00000003 +#define CYFLD_GPIO_PRT_FLT_SEL__OFFSET 0x00000012 +#define CYFLD_GPIO_PRT_FLT_SEL__SIZE 0x00000003 +#define CYREG_GPIO_PRT0_INTR 0x40040010 +#define CYFLD_GPIO_PRT_PS_DATA0__OFFSET 0x00000010 +#define CYFLD_GPIO_PRT_PS_DATA0__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_PS_DATA1__OFFSET 0x00000011 +#define CYFLD_GPIO_PRT_PS_DATA1__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_PS_DATA2__OFFSET 0x00000012 +#define CYFLD_GPIO_PRT_PS_DATA2__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_PS_DATA3__OFFSET 0x00000013 +#define CYFLD_GPIO_PRT_PS_DATA3__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_PS_DATA4__OFFSET 0x00000014 +#define CYFLD_GPIO_PRT_PS_DATA4__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_PS_DATA5__OFFSET 0x00000015 +#define CYFLD_GPIO_PRT_PS_DATA5__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_PS_DATA6__OFFSET 0x00000016 +#define CYFLD_GPIO_PRT_PS_DATA6__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_PS_DATA7__OFFSET 0x00000017 +#define CYFLD_GPIO_PRT_PS_DATA7__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_PS_FLT_DATA__OFFSET 0x00000018 +#define CYFLD_GPIO_PRT_PS_FLT_DATA__SIZE 0x00000001 +#define CYREG_GPIO_PRT0_PC2 0x40040018 +#define CYFLD_GPIO_PRT_INP_DIS0__OFFSET 0x00000000 +#define CYFLD_GPIO_PRT_INP_DIS0__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_INP_DIS1__OFFSET 0x00000001 +#define CYFLD_GPIO_PRT_INP_DIS1__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_INP_DIS2__OFFSET 0x00000002 +#define CYFLD_GPIO_PRT_INP_DIS2__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_INP_DIS3__OFFSET 0x00000003 +#define CYFLD_GPIO_PRT_INP_DIS3__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_INP_DIS4__OFFSET 0x00000004 +#define CYFLD_GPIO_PRT_INP_DIS4__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_INP_DIS5__OFFSET 0x00000005 +#define CYFLD_GPIO_PRT_INP_DIS5__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_INP_DIS6__OFFSET 0x00000006 +#define CYFLD_GPIO_PRT_INP_DIS6__SIZE 0x00000001 +#define CYFLD_GPIO_PRT_INP_DIS7__OFFSET 0x00000007 +#define CYFLD_GPIO_PRT_INP_DIS7__SIZE 0x00000001 +#define CYREG_GPIO_PRT0_DR_SET 0x40040040 +#define CYFLD_GPIO_PRT_DATA__OFFSET 0x00000000 +#define CYFLD_GPIO_PRT_DATA__SIZE 0x00000008 +#define CYREG_GPIO_PRT0_DR_CLR 0x40040044 +#define CYREG_GPIO_PRT0_DR_INV 0x40040048 +#define CYDEV_GPIO_PRT1_BASE 0x40040100 +#define CYDEV_GPIO_PRT1_SIZE 0x00000100 +#define CYREG_GPIO_PRT1_DR 0x40040100 +#define CYREG_GPIO_PRT1_PS 0x40040104 +#define CYREG_GPIO_PRT1_PC 0x40040108 +#define CYREG_GPIO_PRT1_INTR_CFG 0x4004010c +#define CYREG_GPIO_PRT1_INTR 0x40040110 +#define CYREG_GPIO_PRT1_PC2 0x40040118 +#define CYREG_GPIO_PRT1_DR_SET 0x40040140 +#define CYREG_GPIO_PRT1_DR_CLR 0x40040144 +#define CYREG_GPIO_PRT1_DR_INV 0x40040148 +#define CYDEV_GPIO_PRT2_BASE 0x40040200 +#define CYDEV_GPIO_PRT2_SIZE 0x00000100 +#define CYREG_GPIO_PRT2_DR 0x40040200 +#define CYREG_GPIO_PRT2_PS 0x40040204 +#define CYREG_GPIO_PRT2_PC 0x40040208 +#define CYREG_GPIO_PRT2_INTR_CFG 0x4004020c +#define CYREG_GPIO_PRT2_INTR 0x40040210 +#define CYREG_GPIO_PRT2_PC2 0x40040218 +#define CYREG_GPIO_PRT2_DR_SET 0x40040240 +#define CYREG_GPIO_PRT2_DR_CLR 0x40040244 +#define CYREG_GPIO_PRT2_DR_INV 0x40040248 +#define CYDEV_GPIO_PRT3_BASE 0x40040300 +#define CYDEV_GPIO_PRT3_SIZE 0x00000100 +#define CYREG_GPIO_PRT3_DR 0x40040300 +#define CYREG_GPIO_PRT3_PS 0x40040304 +#define CYREG_GPIO_PRT3_PC 0x40040308 +#define CYREG_GPIO_PRT3_INTR_CFG 0x4004030c +#define CYREG_GPIO_PRT3_INTR 0x40040310 +#define CYREG_GPIO_PRT3_PC2 0x40040318 +#define CYREG_GPIO_PRT3_DR_SET 0x40040340 +#define CYREG_GPIO_PRT3_DR_CLR 0x40040344 +#define CYREG_GPIO_PRT3_DR_INV 0x40040348 +#define CYDEV_GPIO_PRT4_BASE 0x40040400 +#define CYDEV_GPIO_PRT4_SIZE 0x00000100 +#define CYREG_GPIO_PRT4_DR 0x40040400 +#define CYREG_GPIO_PRT4_PS 0x40040404 +#define CYREG_GPIO_PRT4_PC 0x40040408 +#define CYREG_GPIO_PRT4_INTR_CFG 0x4004040c +#define CYREG_GPIO_PRT4_INTR 0x40040410 +#define CYREG_GPIO_PRT4_PC2 0x40040418 +#define CYREG_GPIO_PRT4_DR_SET 0x40040440 +#define CYREG_GPIO_PRT4_DR_CLR 0x40040444 +#define CYREG_GPIO_PRT4_DR_INV 0x40040448 +#define CYDEV_GPIO_PRT5_BASE 0x40040500 +#define CYDEV_GPIO_PRT5_SIZE 0x00000100 +#define CYREG_GPIO_PRT5_DR 0x40040500 +#define CYREG_GPIO_PRT5_PS 0x40040504 +#define CYREG_GPIO_PRT5_PC 0x40040508 +#define CYREG_GPIO_PRT5_INTR_CFG 0x4004050c +#define CYREG_GPIO_PRT5_INTR 0x40040510 +#define CYREG_GPIO_PRT5_PC2 0x40040518 +#define CYREG_GPIO_PRT5_DR_SET 0x40040540 +#define CYREG_GPIO_PRT5_DR_CLR 0x40040544 +#define CYREG_GPIO_PRT5_DR_INV 0x40040548 +#define CYDEV_GPIO_PRT6_BASE 0x40040600 +#define CYDEV_GPIO_PRT6_SIZE 0x00000100 +#define CYREG_GPIO_PRT6_DR 0x40040600 +#define CYREG_GPIO_PRT6_PS 0x40040604 +#define CYREG_GPIO_PRT6_PC 0x40040608 +#define CYREG_GPIO_PRT6_INTR_CFG 0x4004060c +#define CYREG_GPIO_PRT6_INTR 0x40040610 +#define CYREG_GPIO_PRT6_PC2 0x40040618 +#define CYREG_GPIO_PRT6_DR_SET 0x40040640 +#define CYREG_GPIO_PRT6_DR_CLR 0x40040644 +#define CYREG_GPIO_PRT6_DR_INV 0x40040648 +#define CYDEV_GPIO_PRT7_BASE 0x40040700 +#define CYDEV_GPIO_PRT7_SIZE 0x00000100 +#define CYREG_GPIO_PRT7_DR 0x40040700 +#define CYREG_GPIO_PRT7_PS 0x40040704 +#define CYREG_GPIO_PRT7_PC 0x40040708 +#define CYREG_GPIO_PRT7_INTR_CFG 0x4004070c +#define CYREG_GPIO_PRT7_INTR 0x40040710 +#define CYREG_GPIO_PRT7_PC2 0x40040718 +#define CYREG_GPIO_PRT7_DR_SET 0x40040740 +#define CYREG_GPIO_PRT7_DR_CLR 0x40040744 +#define CYREG_GPIO_PRT7_DR_INV 0x40040748 +#define CYREG_GPIO_INTR_CAUSE 0x40041000 +#define CYFLD_GPIO_PORT_INT__OFFSET 0x00000000 +#define CYFLD_GPIO_PORT_INT__SIZE 0x00000008 +#define CYDEV_PRGIO_BASE 0x40050000 +#define CYDEV_PRGIO_SIZE 0x00001000 +#define CYDEV_PRGIO_PRT0_BASE 0x40050000 +#define CYDEV_PRGIO_PRT0_SIZE 0x00000100 +#define CYREG_PRGIO_PRT0_CTL 0x40050000 +#define CYFLD_PRGIO_PRT_BYPASS__OFFSET 0x00000000 +#define CYFLD_PRGIO_PRT_BYPASS__SIZE 0x00000008 +#define CYFLD_PRGIO_PRT_CLOCK_SRC__OFFSET 0x00000008 +#define CYFLD_PRGIO_PRT_CLOCK_SRC__SIZE 0x00000005 +#define CYFLD_PRGIO_PRT_HLD_OVR__OFFSET 0x00000018 +#define CYFLD_PRGIO_PRT_HLD_OVR__SIZE 0x00000001 +#define CYFLD_PRGIO_PRT_PIPELINE_EN__OFFSET 0x00000019 +#define CYFLD_PRGIO_PRT_PIPELINE_EN__SIZE 0x00000001 +#define CYFLD_PRGIO_PRT_ENABLED__OFFSET 0x0000001f +#define CYFLD_PRGIO_PRT_ENABLED__SIZE 0x00000001 +#define CYREG_PRGIO_PRT0_SYNC_CTL 0x40050010 +#define CYFLD_PRGIO_PRT_IO_SYNC_EN__OFFSET 0x00000000 +#define CYFLD_PRGIO_PRT_IO_SYNC_EN__SIZE 0x00000008 +#define CYFLD_PRGIO_PRT_CHIP_SYNC_EN__OFFSET 0x00000008 +#define CYFLD_PRGIO_PRT_CHIP_SYNC_EN__SIZE 0x00000008 +#define CYREG_PRGIO_PRT0_LUT_SEL0 0x40050020 +#define CYFLD_PRGIO_PRT_LUT_TR0_SEL__OFFSET 0x00000000 +#define CYFLD_PRGIO_PRT_LUT_TR0_SEL__SIZE 0x00000004 +#define CYFLD_PRGIO_PRT_LUT_TR1_SEL__OFFSET 0x00000008 +#define CYFLD_PRGIO_PRT_LUT_TR1_SEL__SIZE 0x00000004 +#define CYFLD_PRGIO_PRT_LUT_TR2_SEL__OFFSET 0x00000010 +#define CYFLD_PRGIO_PRT_LUT_TR2_SEL__SIZE 0x00000004 +#define CYREG_PRGIO_PRT0_LUT_SEL1 0x40050024 +#define CYREG_PRGIO_PRT0_LUT_SEL2 0x40050028 +#define CYREG_PRGIO_PRT0_LUT_SEL3 0x4005002c +#define CYREG_PRGIO_PRT0_LUT_SEL4 0x40050030 +#define CYREG_PRGIO_PRT0_LUT_SEL5 0x40050034 +#define CYREG_PRGIO_PRT0_LUT_SEL6 0x40050038 +#define CYREG_PRGIO_PRT0_LUT_SEL7 0x4005003c +#define CYREG_PRGIO_PRT0_LUT_CTL0 0x40050040 +#define CYFLD_PRGIO_PRT_LUT__OFFSET 0x00000000 +#define CYFLD_PRGIO_PRT_LUT__SIZE 0x00000008 +#define CYFLD_PRGIO_PRT_LUT_OPC__OFFSET 0x00000008 +#define CYFLD_PRGIO_PRT_LUT_OPC__SIZE 0x00000002 +#define CYREG_PRGIO_PRT0_LUT_CTL1 0x40050044 +#define CYREG_PRGIO_PRT0_LUT_CTL2 0x40050048 +#define CYREG_PRGIO_PRT0_LUT_CTL3 0x4005004c +#define CYREG_PRGIO_PRT0_LUT_CTL4 0x40050050 +#define CYREG_PRGIO_PRT0_LUT_CTL5 0x40050054 +#define CYREG_PRGIO_PRT0_LUT_CTL6 0x40050058 +#define CYREG_PRGIO_PRT0_LUT_CTL7 0x4005005c +#define CYREG_PRGIO_PRT0_DU_SEL 0x400500c0 +#define CYFLD_PRGIO_PRT_DU_TR0_SEL__OFFSET 0x00000000 +#define CYFLD_PRGIO_PRT_DU_TR0_SEL__SIZE 0x00000004 +#define CYFLD_PRGIO_PRT_DU_TR1_SEL__OFFSET 0x00000008 +#define CYFLD_PRGIO_PRT_DU_TR1_SEL__SIZE 0x00000004 +#define CYFLD_PRGIO_PRT_DU_TR2_SEL__OFFSET 0x00000010 +#define CYFLD_PRGIO_PRT_DU_TR2_SEL__SIZE 0x00000004 +#define CYFLD_PRGIO_PRT_DU_DATA0_SEL__OFFSET 0x00000018 +#define CYFLD_PRGIO_PRT_DU_DATA0_SEL__SIZE 0x00000002 +#define CYFLD_PRGIO_PRT_DU_DATA1_SEL__OFFSET 0x0000001c +#define CYFLD_PRGIO_PRT_DU_DATA1_SEL__SIZE 0x00000002 +#define CYREG_PRGIO_PRT0_DU_CTL 0x400500c4 +#define CYFLD_PRGIO_PRT_DU_SIZE__OFFSET 0x00000000 +#define CYFLD_PRGIO_PRT_DU_SIZE__SIZE 0x00000003 +#define CYFLD_PRGIO_PRT_DU_OPC__OFFSET 0x00000008 +#define CYFLD_PRGIO_PRT_DU_OPC__SIZE 0x00000004 +#define CYREG_PRGIO_PRT0_DATA 0x400500f0 +#define CYFLD_PRGIO_PRT_DATA__OFFSET 0x00000000 +#define CYFLD_PRGIO_PRT_DATA__SIZE 0x00000008 +#define CYDEV_PRGIO_PRT1_BASE 0x40050100 +#define CYDEV_PRGIO_PRT1_SIZE 0x00000100 +#define CYREG_PRGIO_PRT1_CTL 0x40050100 +#define CYREG_PRGIO_PRT1_SYNC_CTL 0x40050110 +#define CYREG_PRGIO_PRT1_LUT_SEL0 0x40050120 +#define CYREG_PRGIO_PRT1_LUT_SEL1 0x40050124 +#define CYREG_PRGIO_PRT1_LUT_SEL2 0x40050128 +#define CYREG_PRGIO_PRT1_LUT_SEL3 0x4005012c +#define CYREG_PRGIO_PRT1_LUT_SEL4 0x40050130 +#define CYREG_PRGIO_PRT1_LUT_SEL5 0x40050134 +#define CYREG_PRGIO_PRT1_LUT_SEL6 0x40050138 +#define CYREG_PRGIO_PRT1_LUT_SEL7 0x4005013c +#define CYREG_PRGIO_PRT1_LUT_CTL0 0x40050140 +#define CYREG_PRGIO_PRT1_LUT_CTL1 0x40050144 +#define CYREG_PRGIO_PRT1_LUT_CTL2 0x40050148 +#define CYREG_PRGIO_PRT1_LUT_CTL3 0x4005014c +#define CYREG_PRGIO_PRT1_LUT_CTL4 0x40050150 +#define CYREG_PRGIO_PRT1_LUT_CTL5 0x40050154 +#define CYREG_PRGIO_PRT1_LUT_CTL6 0x40050158 +#define CYREG_PRGIO_PRT1_LUT_CTL7 0x4005015c +#define CYREG_PRGIO_PRT1_DU_SEL 0x400501c0 +#define CYREG_PRGIO_PRT1_DU_CTL 0x400501c4 +#define CYREG_PRGIO_PRT1_DATA 0x400501f0 +#define CYDEV_PRGIO_PRT2_BASE 0x40050200 +#define CYDEV_PRGIO_PRT2_SIZE 0x00000100 +#define CYREG_PRGIO_PRT2_CTL 0x40050200 +#define CYREG_PRGIO_PRT2_SYNC_CTL 0x40050210 +#define CYREG_PRGIO_PRT2_LUT_SEL0 0x40050220 +#define CYREG_PRGIO_PRT2_LUT_SEL1 0x40050224 +#define CYREG_PRGIO_PRT2_LUT_SEL2 0x40050228 +#define CYREG_PRGIO_PRT2_LUT_SEL3 0x4005022c +#define CYREG_PRGIO_PRT2_LUT_SEL4 0x40050230 +#define CYREG_PRGIO_PRT2_LUT_SEL5 0x40050234 +#define CYREG_PRGIO_PRT2_LUT_SEL6 0x40050238 +#define CYREG_PRGIO_PRT2_LUT_SEL7 0x4005023c +#define CYREG_PRGIO_PRT2_LUT_CTL0 0x40050240 +#define CYREG_PRGIO_PRT2_LUT_CTL1 0x40050244 +#define CYREG_PRGIO_PRT2_LUT_CTL2 0x40050248 +#define CYREG_PRGIO_PRT2_LUT_CTL3 0x4005024c +#define CYREG_PRGIO_PRT2_LUT_CTL4 0x40050250 +#define CYREG_PRGIO_PRT2_LUT_CTL5 0x40050254 +#define CYREG_PRGIO_PRT2_LUT_CTL6 0x40050258 +#define CYREG_PRGIO_PRT2_LUT_CTL7 0x4005025c +#define CYREG_PRGIO_PRT2_DU_SEL 0x400502c0 +#define CYREG_PRGIO_PRT2_DU_CTL 0x400502c4 +#define CYREG_PRGIO_PRT2_DATA 0x400502f0 +#define CYDEV_CPUSS_BASE 0x40100000 +#define CYDEV_CPUSS_SIZE 0x00001000 +#define CYREG_CPUSS_SYSREQ 0x40100004 +#define CYFLD_CPUSS_SYSCALL_COMMAND__OFFSET 0x00000000 +#define CYFLD_CPUSS_SYSCALL_COMMAND__SIZE 0x00000010 +#define CYFLD_CPUSS_DIS_RESET_VECT_REL__OFFSET 0x0000001b +#define CYFLD_CPUSS_DIS_RESET_VECT_REL__SIZE 0x00000001 +#define CYFLD_CPUSS_PRIVILEGED__OFFSET 0x0000001c +#define CYFLD_CPUSS_PRIVILEGED__SIZE 0x00000001 +#define CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET 0x0000001d +#define CYFLD_CPUSS_ROM_ACCESS_EN__SIZE 0x00000001 +#define CYFLD_CPUSS_HMASTER_0__OFFSET 0x0000001e +#define CYFLD_CPUSS_HMASTER_0__SIZE 0x00000001 +#define CYFLD_CPUSS_SYSCALL_REQ__OFFSET 0x0000001f +#define CYFLD_CPUSS_SYSCALL_REQ__SIZE 0x00000001 +#define CYREG_CPUSS_SYSARG 0x40100008 +#define CYFLD_CPUSS_SYSCALL_ARG__OFFSET 0x00000000 +#define CYFLD_CPUSS_SYSCALL_ARG__SIZE 0x00000020 +#define CYREG_CPUSS_PROTECTION 0x4010000c +#define CYFLD_CPUSS_PROTECTION_MODE__OFFSET 0x00000000 +#define CYFLD_CPUSS_PROTECTION_MODE__SIZE 0x00000004 +#define CYFLD_CPUSS_FLASH_LOCK__OFFSET 0x0000001e +#define CYFLD_CPUSS_FLASH_LOCK__SIZE 0x00000001 +#define CYFLD_CPUSS_PROTECTION_LOCK__OFFSET 0x0000001f +#define CYFLD_CPUSS_PROTECTION_LOCK__SIZE 0x00000001 +#define CYREG_CPUSS_PRIV_ROM 0x40100010 +#define CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET 0x00000000 +#define CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE 0x00000008 +#define CYREG_CPUSS_PRIV_RAM 0x40100014 +#define CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET 0x00000000 +#define CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE 0x00000009 +#define CYREG_CPUSS_PRIV_FLASH 0x40100018 +#define CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET 0x00000000 +#define CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE 0x0000000c +#define CYREG_CPUSS_WOUNDING 0x4010001c +#define CYFLD_CPUSS_RAM_WOUND__OFFSET 0x00000010 +#define CYFLD_CPUSS_RAM_WOUND__SIZE 0x00000003 +#define CYFLD_CPUSS_FLASH_WOUND__OFFSET 0x00000014 +#define CYFLD_CPUSS_FLASH_WOUND__SIZE 0x00000003 +#define CYREG_CPUSS_FLASH_CTL 0x40100030 +#define CYFLD_CPUSS_FLASH_WS__OFFSET 0x00000000 +#define CYFLD_CPUSS_FLASH_WS__SIZE 0x00000002 +#define CYFLD_CPUSS_PREF_EN__OFFSET 0x00000004 +#define CYFLD_CPUSS_PREF_EN__SIZE 0x00000001 +#define CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET 0x00000008 +#define CYFLD_CPUSS_FLASH_INVALIDATE__SIZE 0x00000001 +#define CYFLD_CPUSS_ARB__OFFSET 0x00000010 +#define CYFLD_CPUSS_ARB__SIZE 0x00000002 +#define CYREG_CPUSS_ROM_CTL 0x40100034 +#define CYFLD_CPUSS_ROM_WS__OFFSET 0x00000000 +#define CYFLD_CPUSS_ROM_WS__SIZE 0x00000001 +#define CYREG_CPUSS_RAM_CTL 0x40100038 +#define CYREG_CPUSS_DMAC_CTL 0x4010003c +#define CYREG_CPUSS_SL_CTL0 0x40100100 +#define CYREG_CPUSS_SL_CTL1 0x40100104 +#define CYREG_CPUSS_SL_CTL2 0x40100108 +#define CYDEV_DMAC_BASE 0x40101000 +#define CYDEV_DMAC_SIZE 0x00001000 +#define CYREG_DMAC_CTL 0x40101000 +#define CYFLD_DMAC_ENABLED__OFFSET 0x0000001f +#define CYFLD_DMAC_ENABLED__SIZE 0x00000001 +#define CYREG_DMAC_STATUS 0x40101010 +#define CYFLD_DMAC_DATA_NR__OFFSET 0x00000000 +#define CYFLD_DMAC_DATA_NR__SIZE 0x00000010 +#define CYFLD_DMAC_CH_ADDR__OFFSET 0x00000010 +#define CYFLD_DMAC_CH_ADDR__SIZE 0x00000003 +#define CYFLD_DMAC_STATE__OFFSET 0x00000018 +#define CYFLD_DMAC_STATE__SIZE 0x00000003 +#define CYFLD_DMAC_PRIO__OFFSET 0x0000001c +#define CYFLD_DMAC_PRIO__SIZE 0x00000002 +#define CYFLD_DMAC_PING_PONG__OFFSET 0x0000001e +#define CYFLD_DMAC_PING_PONG__SIZE 0x00000001 +#define CYFLD_DMAC_ACTIVE__OFFSET 0x0000001f +#define CYFLD_DMAC_ACTIVE__SIZE 0x00000001 +#define CYREG_DMAC_STATUS_SRC_ADDR 0x40101014 +#define CYFLD_DMAC_ADDR__OFFSET 0x00000000 +#define CYFLD_DMAC_ADDR__SIZE 0x00000020 +#define CYREG_DMAC_STATUS_DST_ADDR 0x40101018 +#define CYREG_DMAC_STATUS_CH_ACT 0x4010101c +#define CYFLD_DMAC_CH__OFFSET 0x00000000 +#define CYFLD_DMAC_CH__SIZE 0x00000008 +#define CYREG_DMAC_CH_CTL0 0x40101080 +#define CYREG_DMAC_CH_CTL1 0x40101084 +#define CYREG_DMAC_CH_CTL2 0x40101088 +#define CYREG_DMAC_CH_CTL3 0x4010108c +#define CYREG_DMAC_CH_CTL4 0x40101090 +#define CYREG_DMAC_CH_CTL5 0x40101094 +#define CYREG_DMAC_CH_CTL6 0x40101098 +#define CYREG_DMAC_CH_CTL7 0x4010109c +#define CYREG_DMAC_INTR 0x401017f0 +#define CYREG_DMAC_INTR_SET 0x401017f4 +#define CYREG_DMAC_INTR_MASK 0x401017f8 +#define CYREG_DMAC_INTR_MASKED 0x401017fc +#define CYDEV_DMAC_DESCR0_BASE 0x40101800 +#define CYDEV_DMAC_DESCR0_SIZE 0x00000020 +#define CYREG_DMAC_DESCR0_PING_SRC 0x40101800 +#define CYFLD_DMAC_DESCR_ADDR__OFFSET 0x00000000 +#define CYFLD_DMAC_DESCR_ADDR__SIZE 0x00000020 +#define CYREG_DMAC_DESCR0_PING_DST 0x40101804 +#define CYREG_DMAC_DESCR0_PING_CTL 0x40101808 +#define CYFLD_DMAC_DESCR_DATA_NR__OFFSET 0x00000000 +#define CYFLD_DMAC_DESCR_DATA_NR__SIZE 0x00000010 +#define CYFLD_DMAC_DESCR_DATA_SIZE__OFFSET 0x00000010 +#define CYFLD_DMAC_DESCR_DATA_SIZE__SIZE 0x00000002 +#define CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__OFFSET 0x00000014 +#define CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__SIZE 0x00000001 +#define CYFLD_DMAC_DESCR_DST_ADDR_INCR__OFFSET 0x00000015 +#define CYFLD_DMAC_DESCR_DST_ADDR_INCR__SIZE 0x00000001 +#define CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__OFFSET 0x00000016 +#define CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__SIZE 0x00000001 +#define CYFLD_DMAC_DESCR_SRC_ADDR_INCR__OFFSET 0x00000017 +#define CYFLD_DMAC_DESCR_SRC_ADDR_INCR__SIZE 0x00000001 +#define CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__OFFSET 0x00000018 +#define CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__SIZE 0x00000002 +#define CYFLD_DMAC_DESCR_INV_DESCR__OFFSET 0x0000001a +#define CYFLD_DMAC_DESCR_INV_DESCR__SIZE 0x00000001 +#define CYFLD_DMAC_DESCR_SET_CAUSE__OFFSET 0x0000001b +#define CYFLD_DMAC_DESCR_SET_CAUSE__SIZE 0x00000001 +#define CYFLD_DMAC_DESCR_PREEMPTABLE__OFFSET 0x0000001c +#define CYFLD_DMAC_DESCR_PREEMPTABLE__SIZE 0x00000001 +#define CYFLD_DMAC_DESCR_FLIPPING__OFFSET 0x0000001d +#define CYFLD_DMAC_DESCR_FLIPPING__SIZE 0x00000001 +#define CYFLD_DMAC_DESCR_OPCODE__OFFSET 0x0000001e +#define CYFLD_DMAC_DESCR_OPCODE__SIZE 0x00000002 +#define CYREG_DMAC_DESCR0_PING_STATUS 0x4010180c +#define CYFLD_DMAC_DESCR_CURR_DATA_NR__OFFSET 0x00000000 +#define CYFLD_DMAC_DESCR_CURR_DATA_NR__SIZE 0x00000010 +#define CYFLD_DMAC_DESCR_RESPONSE__OFFSET 0x00000010 +#define CYFLD_DMAC_DESCR_RESPONSE__SIZE 0x00000003 +#define CYFLD_DMAC_DESCR_VALID__OFFSET 0x0000001f +#define CYFLD_DMAC_DESCR_VALID__SIZE 0x00000001 +#define CYREG_DMAC_DESCR0_PONG_SRC 0x40101810 +#define CYREG_DMAC_DESCR0_PONG_DST 0x40101814 +#define CYREG_DMAC_DESCR0_PONG_CTL 0x40101818 +#define CYREG_DMAC_DESCR0_PONG_STATUS 0x4010181c +#define CYDEV_DMAC_DESCR1_BASE 0x40101820 +#define CYDEV_DMAC_DESCR1_SIZE 0x00000020 +#define CYREG_DMAC_DESCR1_PING_SRC 0x40101820 +#define CYREG_DMAC_DESCR1_PING_DST 0x40101824 +#define CYREG_DMAC_DESCR1_PING_CTL 0x40101828 +#define CYREG_DMAC_DESCR1_PING_STATUS 0x4010182c +#define CYREG_DMAC_DESCR1_PONG_SRC 0x40101830 +#define CYREG_DMAC_DESCR1_PONG_DST 0x40101834 +#define CYREG_DMAC_DESCR1_PONG_CTL 0x40101838 +#define CYREG_DMAC_DESCR1_PONG_STATUS 0x4010183c +#define CYDEV_DMAC_DESCR2_BASE 0x40101840 +#define CYDEV_DMAC_DESCR2_SIZE 0x00000020 +#define CYREG_DMAC_DESCR2_PING_SRC 0x40101840 +#define CYREG_DMAC_DESCR2_PING_DST 0x40101844 +#define CYREG_DMAC_DESCR2_PING_CTL 0x40101848 +#define CYREG_DMAC_DESCR2_PING_STATUS 0x4010184c +#define CYREG_DMAC_DESCR2_PONG_SRC 0x40101850 +#define CYREG_DMAC_DESCR2_PONG_DST 0x40101854 +#define CYREG_DMAC_DESCR2_PONG_CTL 0x40101858 +#define CYREG_DMAC_DESCR2_PONG_STATUS 0x4010185c +#define CYDEV_DMAC_DESCR3_BASE 0x40101860 +#define CYDEV_DMAC_DESCR3_SIZE 0x00000020 +#define CYREG_DMAC_DESCR3_PING_SRC 0x40101860 +#define CYREG_DMAC_DESCR3_PING_DST 0x40101864 +#define CYREG_DMAC_DESCR3_PING_CTL 0x40101868 +#define CYREG_DMAC_DESCR3_PING_STATUS 0x4010186c +#define CYREG_DMAC_DESCR3_PONG_SRC 0x40101870 +#define CYREG_DMAC_DESCR3_PONG_DST 0x40101874 +#define CYREG_DMAC_DESCR3_PONG_CTL 0x40101878 +#define CYREG_DMAC_DESCR3_PONG_STATUS 0x4010187c +#define CYDEV_DMAC_DESCR4_BASE 0x40101880 +#define CYDEV_DMAC_DESCR4_SIZE 0x00000020 +#define CYREG_DMAC_DESCR4_PING_SRC 0x40101880 +#define CYREG_DMAC_DESCR4_PING_DST 0x40101884 +#define CYREG_DMAC_DESCR4_PING_CTL 0x40101888 +#define CYREG_DMAC_DESCR4_PING_STATUS 0x4010188c +#define CYREG_DMAC_DESCR4_PONG_SRC 0x40101890 +#define CYREG_DMAC_DESCR4_PONG_DST 0x40101894 +#define CYREG_DMAC_DESCR4_PONG_CTL 0x40101898 +#define CYREG_DMAC_DESCR4_PONG_STATUS 0x4010189c +#define CYDEV_DMAC_DESCR5_BASE 0x401018a0 +#define CYDEV_DMAC_DESCR5_SIZE 0x00000020 +#define CYREG_DMAC_DESCR5_PING_SRC 0x401018a0 +#define CYREG_DMAC_DESCR5_PING_DST 0x401018a4 +#define CYREG_DMAC_DESCR5_PING_CTL 0x401018a8 +#define CYREG_DMAC_DESCR5_PING_STATUS 0x401018ac +#define CYREG_DMAC_DESCR5_PONG_SRC 0x401018b0 +#define CYREG_DMAC_DESCR5_PONG_DST 0x401018b4 +#define CYREG_DMAC_DESCR5_PONG_CTL 0x401018b8 +#define CYREG_DMAC_DESCR5_PONG_STATUS 0x401018bc +#define CYDEV_DMAC_DESCR6_BASE 0x401018c0 +#define CYDEV_DMAC_DESCR6_SIZE 0x00000020 +#define CYREG_DMAC_DESCR6_PING_SRC 0x401018c0 +#define CYREG_DMAC_DESCR6_PING_DST 0x401018c4 +#define CYREG_DMAC_DESCR6_PING_CTL 0x401018c8 +#define CYREG_DMAC_DESCR6_PING_STATUS 0x401018cc +#define CYREG_DMAC_DESCR6_PONG_SRC 0x401018d0 +#define CYREG_DMAC_DESCR6_PONG_DST 0x401018d4 +#define CYREG_DMAC_DESCR6_PONG_CTL 0x401018d8 +#define CYREG_DMAC_DESCR6_PONG_STATUS 0x401018dc +#define CYDEV_DMAC_DESCR7_BASE 0x401018e0 +#define CYDEV_DMAC_DESCR7_SIZE 0x00000020 +#define CYREG_DMAC_DESCR7_PING_SRC 0x401018e0 +#define CYREG_DMAC_DESCR7_PING_DST 0x401018e4 +#define CYREG_DMAC_DESCR7_PING_CTL 0x401018e8 +#define CYREG_DMAC_DESCR7_PING_STATUS 0x401018ec +#define CYREG_DMAC_DESCR7_PONG_SRC 0x401018f0 +#define CYREG_DMAC_DESCR7_PONG_DST 0x401018f4 +#define CYREG_DMAC_DESCR7_PONG_CTL 0x401018f8 +#define CYREG_DMAC_DESCR7_PONG_STATUS 0x401018fc +#define CYDEV_SPCIF_BASE 0x40110000 +#define CYDEV_SPCIF_SIZE 0x00010000 +#define CYREG_SPCIF_GEOMETRY 0x40110000 +#define CYFLD_SPCIF_FLASH__OFFSET 0x00000000 +#define CYFLD_SPCIF_FLASH__SIZE 0x0000000e +#define CYFLD_SPCIF_SFLASH__OFFSET 0x0000000e +#define CYFLD_SPCIF_SFLASH__SIZE 0x00000006 +#define CYFLD_SPCIF_NUM_FLASH__OFFSET 0x00000014 +#define CYFLD_SPCIF_NUM_FLASH__SIZE 0x00000002 +#define CYFLD_SPCIF_FLASH_ROW__OFFSET 0x00000016 +#define CYFLD_SPCIF_FLASH_ROW__SIZE 0x00000002 +#define CYFLD_SPCIF_DE_CPD_LP__OFFSET 0x0000001f +#define CYFLD_SPCIF_DE_CPD_LP__SIZE 0x00000001 +#define CYREG_SPCIF_INTR 0x401107f0 +#define CYFLD_SPCIF_TIMER__OFFSET 0x00000000 +#define CYFLD_SPCIF_TIMER__SIZE 0x00000001 +#define CYREG_SPCIF_INTR_SET 0x401107f4 +#define CYREG_SPCIF_INTR_MASK 0x401107f8 +#define CYREG_SPCIF_INTR_MASKED 0x401107fc +#define CYDEV_TCPWM_BASE 0x40200000 +#define CYDEV_TCPWM_SIZE 0x00010000 +#define CYREG_TCPWM_CTRL 0x40200000 +#define CYFLD_TCPWM_COUNTER_ENABLED__OFFSET 0x00000000 +#define CYFLD_TCPWM_COUNTER_ENABLED__SIZE 0x00000008 +#define CYREG_TCPWM_CMD 0x40200008 +#define CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET 0x00000000 +#define CYFLD_TCPWM_COUNTER_CAPTURE__SIZE 0x00000008 +#define CYFLD_TCPWM_COUNTER_RELOAD__OFFSET 0x00000008 +#define CYFLD_TCPWM_COUNTER_RELOAD__SIZE 0x00000008 +#define CYFLD_TCPWM_COUNTER_STOP__OFFSET 0x00000010 +#define CYFLD_TCPWM_COUNTER_STOP__SIZE 0x00000008 +#define CYFLD_TCPWM_COUNTER_START__OFFSET 0x00000018 +#define CYFLD_TCPWM_COUNTER_START__SIZE 0x00000008 +#define CYREG_TCPWM_INTR_CAUSE 0x4020000c +#define CYFLD_TCPWM_COUNTER_INT__OFFSET 0x00000000 +#define CYFLD_TCPWM_COUNTER_INT__SIZE 0x00000008 +#define CYDEV_TCPWM_CNT0_BASE 0x40200100 +#define CYDEV_TCPWM_CNT0_SIZE 0x00000040 +#define CYREG_TCPWM_CNT0_CTRL 0x40200100 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET 0x00000001 +#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET 0x00000002 +#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET 0x00000003 +#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_GENERIC__OFFSET 0x00000008 +#define CYFLD_TCPWM_CNT_GENERIC__SIZE 0x00000008 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY1 0x00000000 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY2 0x00000001 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY4 0x00000002 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY8 0x00000003 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY16 0x00000004 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY32 0x00000005 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY64 0x00000006 +#define CYVAL_TCPWM_CNT_GENERIC_DIVBY128 0x00000007 +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET 0x00000010 +#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP 0x00000000 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN 0x00000001 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 0x00000002 +#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 0x00000003 +#define CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET 0x00000012 +#define CYFLD_TCPWM_CNT_ONE_SHOT__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET 0x00000014 +#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 0x00000000 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 0x00000001 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 0x00000002 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT 0x00000001 +#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT 0x00000002 +#define CYFLD_TCPWM_CNT_MODE__OFFSET 0x00000018 +#define CYFLD_TCPWM_CNT_MODE__SIZE 0x00000003 +#define CYVAL_TCPWM_CNT_MODE_TIMER 0x00000000 +#define CYVAL_TCPWM_CNT_MODE_CAPTURE 0x00000002 +#define CYVAL_TCPWM_CNT_MODE_QUAD 0x00000003 +#define CYVAL_TCPWM_CNT_MODE_PWM 0x00000004 +#define CYVAL_TCPWM_CNT_MODE_PWM_DT 0x00000005 +#define CYVAL_TCPWM_CNT_MODE_PWM_PR 0x00000006 +#define CYREG_TCPWM_CNT0_STATUS 0x40200104 +#define CYFLD_TCPWM_CNT_DOWN__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_DOWN__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_RUNNING__OFFSET 0x0000001f +#define CYFLD_TCPWM_CNT_RUNNING__SIZE 0x00000001 +#define CYREG_TCPWM_CNT0_COUNTER 0x40200108 +#define CYFLD_TCPWM_CNT_COUNTER__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_COUNTER__SIZE 0x00000010 +#define CYREG_TCPWM_CNT0_CC 0x4020010c +#define CYFLD_TCPWM_CNT_CC__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CC__SIZE 0x00000010 +#define CYREG_TCPWM_CNT0_CC_BUFF 0x40200110 +#define CYREG_TCPWM_CNT0_PERIOD 0x40200114 +#define CYFLD_TCPWM_CNT_PERIOD__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_PERIOD__SIZE 0x00000010 +#define CYREG_TCPWM_CNT0_PERIOD_BUFF 0x40200118 +#define CYREG_TCPWM_CNT0_TR_CTRL0 0x40200120 +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET 0x00000004 +#define CYFLD_TCPWM_CNT_COUNT_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET 0x00000008 +#define CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_STOP_SEL__OFFSET 0x0000000c +#define CYFLD_TCPWM_CNT_STOP_SEL__SIZE 0x00000004 +#define CYFLD_TCPWM_CNT_START_SEL__OFFSET 0x00000010 +#define CYFLD_TCPWM_CNT_START_SEL__SIZE 0x00000004 +#define CYREG_TCPWM_CNT0_TR_CTRL1 0x40200124 +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET 0x00000002 +#define CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET 0x00000004 +#define CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET 0x00000006 +#define CYFLD_TCPWM_CNT_STOP_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET 0x00000003 +#define CYFLD_TCPWM_CNT_START_EDGE__OFFSET 0x00000008 +#define CYFLD_TCPWM_CNT_START_EDGE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE 0x00000000 +#define CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE 0x00000001 +#define CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES 0x00000002 +#define CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET 0x00000003 +#define CYREG_TCPWM_CNT0_TR_CTRL2 0x40200128 +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET 0x00000000 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR 0x00000001 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT 0x00000002 +#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE 0x00000003 +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET 0x00000002 +#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET 0x00000000 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR 0x00000001 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT 0x00000002 +#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE 0x00000003 +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET 0x00000004 +#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE 0x00000002 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET 0x00000000 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR 0x00000001 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT 0x00000002 +#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE 0x00000003 +#define CYREG_TCPWM_CNT0_INTR 0x40200130 +#define CYFLD_TCPWM_CNT_TC__OFFSET 0x00000000 +#define CYFLD_TCPWM_CNT_TC__SIZE 0x00000001 +#define CYFLD_TCPWM_CNT_CC_MATCH__OFFSET 0x00000001 +#define CYFLD_TCPWM_CNT_CC_MATCH__SIZE 0x00000001 +#define CYREG_TCPWM_CNT0_INTR_SET 0x40200134 +#define CYREG_TCPWM_CNT0_INTR_MASK 0x40200138 +#define CYREG_TCPWM_CNT0_INTR_MASKED 0x4020013c +#define CYDEV_TCPWM_CNT1_BASE 0x40200140 +#define CYDEV_TCPWM_CNT1_SIZE 0x00000040 +#define CYREG_TCPWM_CNT1_CTRL 0x40200140 +#define CYREG_TCPWM_CNT1_STATUS 0x40200144 +#define CYREG_TCPWM_CNT1_COUNTER 0x40200148 +#define CYREG_TCPWM_CNT1_CC 0x4020014c +#define CYREG_TCPWM_CNT1_CC_BUFF 0x40200150 +#define CYREG_TCPWM_CNT1_PERIOD 0x40200154 +#define CYREG_TCPWM_CNT1_PERIOD_BUFF 0x40200158 +#define CYREG_TCPWM_CNT1_TR_CTRL0 0x40200160 +#define CYREG_TCPWM_CNT1_TR_CTRL1 0x40200164 +#define CYREG_TCPWM_CNT1_TR_CTRL2 0x40200168 +#define CYREG_TCPWM_CNT1_INTR 0x40200170 +#define CYREG_TCPWM_CNT1_INTR_SET 0x40200174 +#define CYREG_TCPWM_CNT1_INTR_MASK 0x40200178 +#define CYREG_TCPWM_CNT1_INTR_MASKED 0x4020017c +#define CYDEV_TCPWM_CNT2_BASE 0x40200180 +#define CYDEV_TCPWM_CNT2_SIZE 0x00000040 +#define CYREG_TCPWM_CNT2_CTRL 0x40200180 +#define CYREG_TCPWM_CNT2_STATUS 0x40200184 +#define CYREG_TCPWM_CNT2_COUNTER 0x40200188 +#define CYREG_TCPWM_CNT2_CC 0x4020018c +#define CYREG_TCPWM_CNT2_CC_BUFF 0x40200190 +#define CYREG_TCPWM_CNT2_PERIOD 0x40200194 +#define CYREG_TCPWM_CNT2_PERIOD_BUFF 0x40200198 +#define CYREG_TCPWM_CNT2_TR_CTRL0 0x402001a0 +#define CYREG_TCPWM_CNT2_TR_CTRL1 0x402001a4 +#define CYREG_TCPWM_CNT2_TR_CTRL2 0x402001a8 +#define CYREG_TCPWM_CNT2_INTR 0x402001b0 +#define CYREG_TCPWM_CNT2_INTR_SET 0x402001b4 +#define CYREG_TCPWM_CNT2_INTR_MASK 0x402001b8 +#define CYREG_TCPWM_CNT2_INTR_MASKED 0x402001bc +#define CYDEV_TCPWM_CNT3_BASE 0x402001c0 +#define CYDEV_TCPWM_CNT3_SIZE 0x00000040 +#define CYREG_TCPWM_CNT3_CTRL 0x402001c0 +#define CYREG_TCPWM_CNT3_STATUS 0x402001c4 +#define CYREG_TCPWM_CNT3_COUNTER 0x402001c8 +#define CYREG_TCPWM_CNT3_CC 0x402001cc +#define CYREG_TCPWM_CNT3_CC_BUFF 0x402001d0 +#define CYREG_TCPWM_CNT3_PERIOD 0x402001d4 +#define CYREG_TCPWM_CNT3_PERIOD_BUFF 0x402001d8 +#define CYREG_TCPWM_CNT3_TR_CTRL0 0x402001e0 +#define CYREG_TCPWM_CNT3_TR_CTRL1 0x402001e4 +#define CYREG_TCPWM_CNT3_TR_CTRL2 0x402001e8 +#define CYREG_TCPWM_CNT3_INTR 0x402001f0 +#define CYREG_TCPWM_CNT3_INTR_SET 0x402001f4 +#define CYREG_TCPWM_CNT3_INTR_MASK 0x402001f8 +#define CYREG_TCPWM_CNT3_INTR_MASKED 0x402001fc +#define CYDEV_TCPWM_CNT4_BASE 0x40200200 +#define CYDEV_TCPWM_CNT4_SIZE 0x00000040 +#define CYREG_TCPWM_CNT4_CTRL 0x40200200 +#define CYREG_TCPWM_CNT4_STATUS 0x40200204 +#define CYREG_TCPWM_CNT4_COUNTER 0x40200208 +#define CYREG_TCPWM_CNT4_CC 0x4020020c +#define CYREG_TCPWM_CNT4_CC_BUFF 0x40200210 +#define CYREG_TCPWM_CNT4_PERIOD 0x40200214 +#define CYREG_TCPWM_CNT4_PERIOD_BUFF 0x40200218 +#define CYREG_TCPWM_CNT4_TR_CTRL0 0x40200220 +#define CYREG_TCPWM_CNT4_TR_CTRL1 0x40200224 +#define CYREG_TCPWM_CNT4_TR_CTRL2 0x40200228 +#define CYREG_TCPWM_CNT4_INTR 0x40200230 +#define CYREG_TCPWM_CNT4_INTR_SET 0x40200234 +#define CYREG_TCPWM_CNT4_INTR_MASK 0x40200238 +#define CYREG_TCPWM_CNT4_INTR_MASKED 0x4020023c +#define CYDEV_TCPWM_CNT5_BASE 0x40200240 +#define CYDEV_TCPWM_CNT5_SIZE 0x00000040 +#define CYREG_TCPWM_CNT5_CTRL 0x40200240 +#define CYREG_TCPWM_CNT5_STATUS 0x40200244 +#define CYREG_TCPWM_CNT5_COUNTER 0x40200248 +#define CYREG_TCPWM_CNT5_CC 0x4020024c +#define CYREG_TCPWM_CNT5_CC_BUFF 0x40200250 +#define CYREG_TCPWM_CNT5_PERIOD 0x40200254 +#define CYREG_TCPWM_CNT5_PERIOD_BUFF 0x40200258 +#define CYREG_TCPWM_CNT5_TR_CTRL0 0x40200260 +#define CYREG_TCPWM_CNT5_TR_CTRL1 0x40200264 +#define CYREG_TCPWM_CNT5_TR_CTRL2 0x40200268 +#define CYREG_TCPWM_CNT5_INTR 0x40200270 +#define CYREG_TCPWM_CNT5_INTR_SET 0x40200274 +#define CYREG_TCPWM_CNT5_INTR_MASK 0x40200278 +#define CYREG_TCPWM_CNT5_INTR_MASKED 0x4020027c +#define CYDEV_TCPWM_CNT6_BASE 0x40200280 +#define CYDEV_TCPWM_CNT6_SIZE 0x00000040 +#define CYREG_TCPWM_CNT6_CTRL 0x40200280 +#define CYREG_TCPWM_CNT6_STATUS 0x40200284 +#define CYREG_TCPWM_CNT6_COUNTER 0x40200288 +#define CYREG_TCPWM_CNT6_CC 0x4020028c +#define CYREG_TCPWM_CNT6_CC_BUFF 0x40200290 +#define CYREG_TCPWM_CNT6_PERIOD 0x40200294 +#define CYREG_TCPWM_CNT6_PERIOD_BUFF 0x40200298 +#define CYREG_TCPWM_CNT6_TR_CTRL0 0x402002a0 +#define CYREG_TCPWM_CNT6_TR_CTRL1 0x402002a4 +#define CYREG_TCPWM_CNT6_TR_CTRL2 0x402002a8 +#define CYREG_TCPWM_CNT6_INTR 0x402002b0 +#define CYREG_TCPWM_CNT6_INTR_SET 0x402002b4 +#define CYREG_TCPWM_CNT6_INTR_MASK 0x402002b8 +#define CYREG_TCPWM_CNT6_INTR_MASKED 0x402002bc +#define CYDEV_TCPWM_CNT7_BASE 0x402002c0 +#define CYDEV_TCPWM_CNT7_SIZE 0x00000040 +#define CYREG_TCPWM_CNT7_CTRL 0x402002c0 +#define CYREG_TCPWM_CNT7_STATUS 0x402002c4 +#define CYREG_TCPWM_CNT7_COUNTER 0x402002c8 +#define CYREG_TCPWM_CNT7_CC 0x402002cc +#define CYREG_TCPWM_CNT7_CC_BUFF 0x402002d0 +#define CYREG_TCPWM_CNT7_PERIOD 0x402002d4 +#define CYREG_TCPWM_CNT7_PERIOD_BUFF 0x402002d8 +#define CYREG_TCPWM_CNT7_TR_CTRL0 0x402002e0 +#define CYREG_TCPWM_CNT7_TR_CTRL1 0x402002e4 +#define CYREG_TCPWM_CNT7_TR_CTRL2 0x402002e8 +#define CYREG_TCPWM_CNT7_INTR 0x402002f0 +#define CYREG_TCPWM_CNT7_INTR_SET 0x402002f4 +#define CYREG_TCPWM_CNT7_INTR_MASK 0x402002f8 +#define CYREG_TCPWM_CNT7_INTR_MASKED 0x402002fc +#define CYDEV_WCO_BASE 0x40220000 +#define CYDEV_WCO_SIZE 0x00010000 +#define CYREG_WCO_CONFIG 0x40220000 +#define CYFLD_WCO_LPM_EN__OFFSET 0x00000000 +#define CYFLD_WCO_LPM_EN__SIZE 0x00000001 +#define CYFLD_WCO_LPM_AUTO__OFFSET 0x00000001 +#define CYFLD_WCO_LPM_AUTO__SIZE 0x00000001 +#define CYFLD_WCO_EXT_INPUT_EN__OFFSET 0x00000002 +#define CYFLD_WCO_EXT_INPUT_EN__SIZE 0x00000001 +#define CYFLD_WCO_ENBUS__OFFSET 0x00000010 +#define CYFLD_WCO_ENBUS__SIZE 0x00000008 +#define CYFLD_WCO_DPLL_ENABLE__OFFSET 0x0000001e +#define CYFLD_WCO_DPLL_ENABLE__SIZE 0x00000001 +#define CYFLD_WCO_IP_ENABLE__OFFSET 0x0000001f +#define CYFLD_WCO_IP_ENABLE__SIZE 0x00000001 +#define CYREG_WCO_STATUS 0x40220004 +#define CYFLD_WCO_OUT_BLNK_A__OFFSET 0x00000000 +#define CYFLD_WCO_OUT_BLNK_A__SIZE 0x00000001 +#define CYREG_WCO_DPLL 0x40220008 +#define CYFLD_WCO_DPLL_MULT__OFFSET 0x00000000 +#define CYFLD_WCO_DPLL_MULT__SIZE 0x0000000b +#define CYFLD_WCO_DPLL_LF_IGAIN__OFFSET 0x00000010 +#define CYFLD_WCO_DPLL_LF_IGAIN__SIZE 0x00000003 +#define CYFLD_WCO_DPLL_LF_PGAIN__OFFSET 0x00000013 +#define CYFLD_WCO_DPLL_LF_PGAIN__SIZE 0x00000003 +#define CYFLD_WCO_DPLL_LF_LIMIT__OFFSET 0x00000016 +#define CYFLD_WCO_DPLL_LF_LIMIT__SIZE 0x00000008 +#define CYREG_WCO_WDT_CTRLOW 0x40220200 +#define CYFLD_WCO_WDT_CTR0__OFFSET 0x00000000 +#define CYFLD_WCO_WDT_CTR0__SIZE 0x00000010 +#define CYFLD_WCO_WDT_CTR1__OFFSET 0x00000010 +#define CYFLD_WCO_WDT_CTR1__SIZE 0x00000010 +#define CYREG_WCO_WDT_CTRHIGH 0x40220204 +#define CYFLD_WCO_WDT_CTR2__OFFSET 0x00000000 +#define CYFLD_WCO_WDT_CTR2__SIZE 0x00000020 +#define CYREG_WCO_WDT_MATCH 0x40220208 +#define CYFLD_WCO_WDT_MATCH0__OFFSET 0x00000000 +#define CYFLD_WCO_WDT_MATCH0__SIZE 0x00000010 +#define CYFLD_WCO_WDT_MATCH1__OFFSET 0x00000010 +#define CYFLD_WCO_WDT_MATCH1__SIZE 0x00000010 +#define CYREG_WCO_WDT_CONFIG 0x4022020c +#define CYFLD_WCO_WDT_MODE0__OFFSET 0x00000000 +#define CYFLD_WCO_WDT_MODE0__SIZE 0x00000002 +#define CYVAL_WCO_WDT_MODE0_NOTHING 0x00000000 +#define CYVAL_WCO_WDT_MODE0_INT 0x00000001 +#define CYVAL_WCO_WDT_MODE0_RESET 0x00000002 +#define CYVAL_WCO_WDT_MODE0_INT_THEN_RESET 0x00000003 +#define CYFLD_WCO_WDT_CLEAR0__OFFSET 0x00000002 +#define CYFLD_WCO_WDT_CLEAR0__SIZE 0x00000001 +#define CYFLD_WCO_WDT_CASCADE0_1__OFFSET 0x00000003 +#define CYFLD_WCO_WDT_CASCADE0_1__SIZE 0x00000001 +#define CYFLD_WCO_WDT_MODE1__OFFSET 0x00000008 +#define CYFLD_WCO_WDT_MODE1__SIZE 0x00000002 +#define CYVAL_WCO_WDT_MODE1_NOTHING 0x00000000 +#define CYVAL_WCO_WDT_MODE1_INT 0x00000001 +#define CYVAL_WCO_WDT_MODE1_RESET 0x00000002 +#define CYVAL_WCO_WDT_MODE1_INT_THEN_RESET 0x00000003 +#define CYFLD_WCO_WDT_CLEAR1__OFFSET 0x0000000a +#define CYFLD_WCO_WDT_CLEAR1__SIZE 0x00000001 +#define CYFLD_WCO_WDT_CASCADE1_2__OFFSET 0x0000000b +#define CYFLD_WCO_WDT_CASCADE1_2__SIZE 0x00000001 +#define CYFLD_WCO_WDT_MODE2__OFFSET 0x00000010 +#define CYFLD_WCO_WDT_MODE2__SIZE 0x00000001 +#define CYVAL_WCO_WDT_MODE2_NOTHING 0x00000000 +#define CYVAL_WCO_WDT_MODE2_INT 0x00000001 +#define CYFLD_WCO_WDT_BITS2__OFFSET 0x00000018 +#define CYFLD_WCO_WDT_BITS2__SIZE 0x00000005 +#define CYFLD_WCO_LFCLK_SEL__OFFSET 0x0000001e +#define CYFLD_WCO_LFCLK_SEL__SIZE 0x00000002 +#define CYREG_WCO_WDT_CONTROL 0x40220210 +#define CYFLD_WCO_WDT_ENABLE0__OFFSET 0x00000000 +#define CYFLD_WCO_WDT_ENABLE0__SIZE 0x00000001 +#define CYFLD_WCO_WDT_ENABLED0__OFFSET 0x00000001 +#define CYFLD_WCO_WDT_ENABLED0__SIZE 0x00000001 +#define CYFLD_WCO_WDT_INT0__OFFSET 0x00000002 +#define CYFLD_WCO_WDT_INT0__SIZE 0x00000001 +#define CYFLD_WCO_WDT_RESET0__OFFSET 0x00000003 +#define CYFLD_WCO_WDT_RESET0__SIZE 0x00000001 +#define CYFLD_WCO_WDT_ENABLE1__OFFSET 0x00000008 +#define CYFLD_WCO_WDT_ENABLE1__SIZE 0x00000001 +#define CYFLD_WCO_WDT_ENABLED1__OFFSET 0x00000009 +#define CYFLD_WCO_WDT_ENABLED1__SIZE 0x00000001 +#define CYFLD_WCO_WDT_INT1__OFFSET 0x0000000a +#define CYFLD_WCO_WDT_INT1__SIZE 0x00000001 +#define CYFLD_WCO_WDT_RESET1__OFFSET 0x0000000b +#define CYFLD_WCO_WDT_RESET1__SIZE 0x00000001 +#define CYFLD_WCO_WDT_ENABLE2__OFFSET 0x00000010 +#define CYFLD_WCO_WDT_ENABLE2__SIZE 0x00000001 +#define CYFLD_WCO_WDT_ENABLED2__OFFSET 0x00000011 +#define CYFLD_WCO_WDT_ENABLED2__SIZE 0x00000001 +#define CYFLD_WCO_WDT_INT2__OFFSET 0x00000012 +#define CYFLD_WCO_WDT_INT2__SIZE 0x00000001 +#define CYFLD_WCO_WDT_RESET2__OFFSET 0x00000013 +#define CYFLD_WCO_WDT_RESET2__SIZE 0x00000001 +#define CYREG_WCO_WDT_CLKEN 0x40220214 +#define CYFLD_WCO_CLK_WCO_EN_FOR_WDT__OFFSET 0x00000000 +#define CYFLD_WCO_CLK_WCO_EN_FOR_WDT__SIZE 0x00000001 +#define CYFLD_WCO_CLK_ILO_EN_FOR_WDT__OFFSET 0x00000001 +#define CYFLD_WCO_CLK_ILO_EN_FOR_WDT__SIZE 0x00000001 +#define CYREG_WCO_TRIM 0x40220f00 +#define CYFLD_WCO_XGM__OFFSET 0x00000000 +#define CYFLD_WCO_XGM__SIZE 0x00000003 +#define CYFLD_WCO_LPM_GM__OFFSET 0x00000004 +#define CYFLD_WCO_LPM_GM__SIZE 0x00000002 +#define CYDEV_SCB0_BASE 0x40240000 +#define CYDEV_SCB0_SIZE 0x00010000 +#define CYREG_SCB0_CTRL 0x40240000 +#define CYFLD_SCB_OVS__OFFSET 0x00000000 +#define CYFLD_SCB_OVS__SIZE 0x00000004 +#define CYFLD_SCB_EC_AM_MODE__OFFSET 0x00000008 +#define CYFLD_SCB_EC_AM_MODE__SIZE 0x00000001 +#define CYFLD_SCB_EC_OP_MODE__OFFSET 0x00000009 +#define CYFLD_SCB_EC_OP_MODE__SIZE 0x00000001 +#define CYFLD_SCB_EZ_MODE__OFFSET 0x0000000a +#define CYFLD_SCB_EZ_MODE__SIZE 0x00000001 +#define CYFLD_SCB_BYTE_MODE__OFFSET 0x0000000b +#define CYFLD_SCB_BYTE_MODE__SIZE 0x00000001 +#define CYFLD_SCB_ADDR_ACCEPT__OFFSET 0x00000010 +#define CYFLD_SCB_ADDR_ACCEPT__SIZE 0x00000001 +#define CYFLD_SCB_BLOCK__OFFSET 0x00000011 +#define CYFLD_SCB_BLOCK__SIZE 0x00000001 +#define CYFLD_SCB_MODE__OFFSET 0x00000018 +#define CYFLD_SCB_MODE__SIZE 0x00000002 +#define CYVAL_SCB_MODE_I2C 0x00000000 +#define CYVAL_SCB_MODE_SPI 0x00000001 +#define CYVAL_SCB_MODE_UART 0x00000002 +#define CYFLD_SCB_ENABLED__OFFSET 0x0000001f +#define CYFLD_SCB_ENABLED__SIZE 0x00000001 +#define CYREG_SCB0_STATUS 0x40240004 +#define CYFLD_SCB_EC_BUSY__OFFSET 0x00000000 +#define CYFLD_SCB_EC_BUSY__SIZE 0x00000001 +#define CYREG_SCB0_SPI_CTRL 0x40240020 +#define CYFLD_SCB_CONTINUOUS__OFFSET 0x00000000 +#define CYFLD_SCB_CONTINUOUS__SIZE 0x00000001 +#define CYFLD_SCB_SELECT_PRECEDE__OFFSET 0x00000001 +#define CYFLD_SCB_SELECT_PRECEDE__SIZE 0x00000001 +#define CYFLD_SCB_CPHA__OFFSET 0x00000002 +#define CYFLD_SCB_CPHA__SIZE 0x00000001 +#define CYFLD_SCB_CPOL__OFFSET 0x00000003 +#define CYFLD_SCB_CPOL__SIZE 0x00000001 +#define CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET 0x00000004 +#define CYFLD_SCB_LATE_MISO_SAMPLE__SIZE 0x00000001 +#define CYFLD_SCB_SCLK_CONTINUOUS__OFFSET 0x00000005 +#define CYFLD_SCB_SCLK_CONTINUOUS__SIZE 0x00000001 +#define CYFLD_SCB_SSEL_POLARITY0__OFFSET 0x00000008 +#define CYFLD_SCB_SSEL_POLARITY0__SIZE 0x00000001 +#define CYFLD_SCB_SSEL_POLARITY1__OFFSET 0x00000009 +#define CYFLD_SCB_SSEL_POLARITY1__SIZE 0x00000001 +#define CYFLD_SCB_SSEL_POLARITY2__OFFSET 0x0000000a +#define CYFLD_SCB_SSEL_POLARITY2__SIZE 0x00000001 +#define CYFLD_SCB_SSEL_POLARITY3__OFFSET 0x0000000b +#define CYFLD_SCB_SSEL_POLARITY3__SIZE 0x00000001 +#define CYFLD_SCB_LOOPBACK__OFFSET 0x00000010 +#define CYFLD_SCB_LOOPBACK__SIZE 0x00000001 +#define CYFLD_SCB_SLAVE_SELECT__OFFSET 0x0000001a +#define CYFLD_SCB_SLAVE_SELECT__SIZE 0x00000002 +#define CYFLD_SCB_MASTER_MODE__OFFSET 0x0000001f +#define CYFLD_SCB_MASTER_MODE__SIZE 0x00000001 +#define CYREG_SCB0_SPI_STATUS 0x40240024 +#define CYFLD_SCB_BUS_BUSY__OFFSET 0x00000000 +#define CYFLD_SCB_BUS_BUSY__SIZE 0x00000001 +#define CYFLD_SCB_SPI_EC_BUSY__OFFSET 0x00000001 +#define CYFLD_SCB_SPI_EC_BUSY__SIZE 0x00000001 +#define CYFLD_SCB_CURR_EZ_ADDR__OFFSET 0x00000008 +#define CYFLD_SCB_CURR_EZ_ADDR__SIZE 0x00000008 +#define CYFLD_SCB_BASE_EZ_ADDR__OFFSET 0x00000010 +#define CYFLD_SCB_BASE_EZ_ADDR__SIZE 0x00000008 +#define CYREG_SCB0_UART_CTRL 0x40240040 +#define CYREG_SCB0_UART_TX_CTRL 0x40240044 +#define CYFLD_SCB_STOP_BITS__OFFSET 0x00000000 +#define CYFLD_SCB_STOP_BITS__SIZE 0x00000003 +#define CYFLD_SCB_PARITY__OFFSET 0x00000004 +#define CYFLD_SCB_PARITY__SIZE 0x00000001 +#define CYFLD_SCB_PARITY_ENABLED__OFFSET 0x00000005 +#define CYFLD_SCB_PARITY_ENABLED__SIZE 0x00000001 +#define CYFLD_SCB_RETRY_ON_NACK__OFFSET 0x00000008 +#define CYFLD_SCB_RETRY_ON_NACK__SIZE 0x00000001 +#define CYREG_SCB0_UART_RX_CTRL 0x40240048 +#define CYFLD_SCB_POLARITY__OFFSET 0x00000006 +#define CYFLD_SCB_POLARITY__SIZE 0x00000001 +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET 0x00000008 +#define CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET 0x00000009 +#define CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_MP_MODE__OFFSET 0x0000000a +#define CYFLD_SCB_MP_MODE__SIZE 0x00000001 +#define CYFLD_SCB_LIN_MODE__OFFSET 0x0000000c +#define CYFLD_SCB_LIN_MODE__SIZE 0x00000001 +#define CYFLD_SCB_SKIP_START__OFFSET 0x0000000d +#define CYFLD_SCB_SKIP_START__SIZE 0x00000001 +#define CYFLD_SCB_BREAK_WIDTH__OFFSET 0x00000010 +#define CYFLD_SCB_BREAK_WIDTH__SIZE 0x00000004 +#define CYREG_SCB0_UART_RX_STATUS 0x4024004c +#define CYFLD_SCB_BR_COUNTER__OFFSET 0x00000000 +#define CYFLD_SCB_BR_COUNTER__SIZE 0x0000000c +#define CYREG_SCB0_UART_FLOW_CTRL 0x40240050 +#define CYFLD_SCB_TRIGGER_LEVEL__OFFSET 0x00000000 +#define CYFLD_SCB_TRIGGER_LEVEL__SIZE 0x00000004 +#define CYFLD_SCB_RTS_POLARITY__OFFSET 0x00000010 +#define CYFLD_SCB_RTS_POLARITY__SIZE 0x00000001 +#define CYFLD_SCB_CTS_POLARITY__OFFSET 0x00000018 +#define CYFLD_SCB_CTS_POLARITY__SIZE 0x00000001 +#define CYFLD_SCB_CTS_ENABLED__OFFSET 0x00000019 +#define CYFLD_SCB_CTS_ENABLED__SIZE 0x00000001 +#define CYREG_SCB0_I2C_CTRL 0x40240060 +#define CYFLD_SCB_HIGH_PHASE_OVS__OFFSET 0x00000000 +#define CYFLD_SCB_HIGH_PHASE_OVS__SIZE 0x00000004 +#define CYFLD_SCB_LOW_PHASE_OVS__OFFSET 0x00000004 +#define CYFLD_SCB_LOW_PHASE_OVS__SIZE 0x00000004 +#define CYFLD_SCB_M_READY_DATA_ACK__OFFSET 0x00000008 +#define CYFLD_SCB_M_READY_DATA_ACK__SIZE 0x00000001 +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET 0x00000009 +#define CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE 0x00000001 +#define CYFLD_SCB_S_GENERAL_IGNORE__OFFSET 0x0000000b +#define CYFLD_SCB_S_GENERAL_IGNORE__SIZE 0x00000001 +#define CYFLD_SCB_S_READY_ADDR_ACK__OFFSET 0x0000000c +#define CYFLD_SCB_S_READY_ADDR_ACK__SIZE 0x00000001 +#define CYFLD_SCB_S_READY_DATA_ACK__OFFSET 0x0000000d +#define CYFLD_SCB_S_READY_DATA_ACK__SIZE 0x00000001 +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET 0x0000000e +#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE 0x00000001 +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET 0x0000000f +#define CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE 0x00000001 +#define CYFLD_SCB_SLAVE_MODE__OFFSET 0x0000001e +#define CYFLD_SCB_SLAVE_MODE__SIZE 0x00000001 +#define CYREG_SCB0_I2C_STATUS 0x40240064 +#define CYFLD_SCB_I2C_EC_BUSY__OFFSET 0x00000001 +#define CYFLD_SCB_I2C_EC_BUSY__SIZE 0x00000001 +#define CYFLD_SCB_S_READ__OFFSET 0x00000004 +#define CYFLD_SCB_S_READ__SIZE 0x00000001 +#define CYFLD_SCB_M_READ__OFFSET 0x00000005 +#define CYFLD_SCB_M_READ__SIZE 0x00000001 +#define CYREG_SCB0_I2C_M_CMD 0x40240068 +#define CYFLD_SCB_M_START__OFFSET 0x00000000 +#define CYFLD_SCB_M_START__SIZE 0x00000001 +#define CYFLD_SCB_M_START_ON_IDLE__OFFSET 0x00000001 +#define CYFLD_SCB_M_START_ON_IDLE__SIZE 0x00000001 +#define CYFLD_SCB_M_ACK__OFFSET 0x00000002 +#define CYFLD_SCB_M_ACK__SIZE 0x00000001 +#define CYFLD_SCB_M_NACK__OFFSET 0x00000003 +#define CYFLD_SCB_M_NACK__SIZE 0x00000001 +#define CYFLD_SCB_M_STOP__OFFSET 0x00000004 +#define CYFLD_SCB_M_STOP__SIZE 0x00000001 +#define CYREG_SCB0_I2C_S_CMD 0x4024006c +#define CYFLD_SCB_S_ACK__OFFSET 0x00000000 +#define CYFLD_SCB_S_ACK__SIZE 0x00000001 +#define CYFLD_SCB_S_NACK__OFFSET 0x00000001 +#define CYFLD_SCB_S_NACK__SIZE 0x00000001 +#define CYREG_SCB0_I2C_CFG 0x40240070 +#define CYFLD_SCB_SDA_IN_FILT_TRIM__OFFSET 0x00000000 +#define CYFLD_SCB_SDA_IN_FILT_TRIM__SIZE 0x00000002 +#define CYFLD_SCB_SDA_IN_FILT_SEL__OFFSET 0x00000004 +#define CYFLD_SCB_SDA_IN_FILT_SEL__SIZE 0x00000001 +#define CYFLD_SCB_SCL_IN_FILT_TRIM__OFFSET 0x00000008 +#define CYFLD_SCB_SCL_IN_FILT_TRIM__SIZE 0x00000002 +#define CYFLD_SCB_SCL_IN_FILT_SEL__OFFSET 0x0000000c +#define CYFLD_SCB_SCL_IN_FILT_SEL__SIZE 0x00000001 +#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__OFFSET 0x00000010 +#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__SIZE 0x00000002 +#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__OFFSET 0x00000012 +#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__SIZE 0x00000002 +#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__OFFSET 0x00000014 +#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__SIZE 0x00000002 +#define CYFLD_SCB_SDA_OUT_FILT_SEL__OFFSET 0x0000001c +#define CYFLD_SCB_SDA_OUT_FILT_SEL__SIZE 0x00000002 +#define CYREG_SCB0_TX_CTRL 0x40240200 +#define CYFLD_SCB_DATA_WIDTH__OFFSET 0x00000000 +#define CYFLD_SCB_DATA_WIDTH__SIZE 0x00000004 +#define CYFLD_SCB_MSB_FIRST__OFFSET 0x00000008 +#define CYFLD_SCB_MSB_FIRST__SIZE 0x00000001 +#define CYREG_SCB0_TX_FIFO_CTRL 0x40240204 +#define CYFLD_SCB_CLEAR__OFFSET 0x00000010 +#define CYFLD_SCB_CLEAR__SIZE 0x00000001 +#define CYFLD_SCB_FREEZE__OFFSET 0x00000011 +#define CYFLD_SCB_FREEZE__SIZE 0x00000001 +#define CYREG_SCB0_TX_FIFO_STATUS 0x40240208 +#define CYFLD_SCB_USED__OFFSET 0x00000000 +#define CYFLD_SCB_USED__SIZE 0x00000005 +#define CYFLD_SCB_SR_VALID__OFFSET 0x0000000f +#define CYFLD_SCB_SR_VALID__SIZE 0x00000001 +#define CYFLD_SCB_RD_PTR__OFFSET 0x00000010 +#define CYFLD_SCB_RD_PTR__SIZE 0x00000004 +#define CYFLD_SCB_WR_PTR__OFFSET 0x00000018 +#define CYFLD_SCB_WR_PTR__SIZE 0x00000004 +#define CYREG_SCB0_TX_FIFO_WR 0x40240240 +#define CYFLD_SCB_DATA__OFFSET 0x00000000 +#define CYFLD_SCB_DATA__SIZE 0x00000010 +#define CYREG_SCB0_RX_CTRL 0x40240300 +#define CYFLD_SCB_MEDIAN__OFFSET 0x00000009 +#define CYFLD_SCB_MEDIAN__SIZE 0x00000001 +#define CYREG_SCB0_RX_FIFO_CTRL 0x40240304 +#define CYREG_SCB0_RX_FIFO_STATUS 0x40240308 +#define CYREG_SCB0_RX_MATCH 0x40240310 +#define CYFLD_SCB_ADDR__OFFSET 0x00000000 +#define CYFLD_SCB_ADDR__SIZE 0x00000008 +#define CYFLD_SCB_MASK__OFFSET 0x00000010 +#define CYFLD_SCB_MASK__SIZE 0x00000008 +#define CYREG_SCB0_RX_FIFO_RD 0x40240340 +#define CYREG_SCB0_RX_FIFO_RD_SILENT 0x40240344 +#define CYREG_SCB0_EZ_DATA0 0x40240400 +#define CYFLD_SCB_EZ_DATA__OFFSET 0x00000000 +#define CYFLD_SCB_EZ_DATA__SIZE 0x00000008 +#define CYREG_SCB0_EZ_DATA1 0x40240404 +#define CYREG_SCB0_EZ_DATA2 0x40240408 +#define CYREG_SCB0_EZ_DATA3 0x4024040c +#define CYREG_SCB0_EZ_DATA4 0x40240410 +#define CYREG_SCB0_EZ_DATA5 0x40240414 +#define CYREG_SCB0_EZ_DATA6 0x40240418 +#define CYREG_SCB0_EZ_DATA7 0x4024041c +#define CYREG_SCB0_EZ_DATA8 0x40240420 +#define CYREG_SCB0_EZ_DATA9 0x40240424 +#define CYREG_SCB0_EZ_DATA10 0x40240428 +#define CYREG_SCB0_EZ_DATA11 0x4024042c +#define CYREG_SCB0_EZ_DATA12 0x40240430 +#define CYREG_SCB0_EZ_DATA13 0x40240434 +#define CYREG_SCB0_EZ_DATA14 0x40240438 +#define CYREG_SCB0_EZ_DATA15 0x4024043c +#define CYREG_SCB0_EZ_DATA16 0x40240440 +#define CYREG_SCB0_EZ_DATA17 0x40240444 +#define CYREG_SCB0_EZ_DATA18 0x40240448 +#define CYREG_SCB0_EZ_DATA19 0x4024044c +#define CYREG_SCB0_EZ_DATA20 0x40240450 +#define CYREG_SCB0_EZ_DATA21 0x40240454 +#define CYREG_SCB0_EZ_DATA22 0x40240458 +#define CYREG_SCB0_EZ_DATA23 0x4024045c +#define CYREG_SCB0_EZ_DATA24 0x40240460 +#define CYREG_SCB0_EZ_DATA25 0x40240464 +#define CYREG_SCB0_EZ_DATA26 0x40240468 +#define CYREG_SCB0_EZ_DATA27 0x4024046c +#define CYREG_SCB0_EZ_DATA28 0x40240470 +#define CYREG_SCB0_EZ_DATA29 0x40240474 +#define CYREG_SCB0_EZ_DATA30 0x40240478 +#define CYREG_SCB0_EZ_DATA31 0x4024047c +#define CYREG_SCB0_INTR_CAUSE 0x40240e00 +#define CYFLD_SCB_M__OFFSET 0x00000000 +#define CYFLD_SCB_M__SIZE 0x00000001 +#define CYFLD_SCB_S__OFFSET 0x00000001 +#define CYFLD_SCB_S__SIZE 0x00000001 +#define CYFLD_SCB_TX__OFFSET 0x00000002 +#define CYFLD_SCB_TX__SIZE 0x00000001 +#define CYFLD_SCB_RX__OFFSET 0x00000003 +#define CYFLD_SCB_RX__SIZE 0x00000001 +#define CYFLD_SCB_I2C_EC__OFFSET 0x00000004 +#define CYFLD_SCB_I2C_EC__SIZE 0x00000001 +#define CYFLD_SCB_SPI_EC__OFFSET 0x00000005 +#define CYFLD_SCB_SPI_EC__SIZE 0x00000001 +#define CYREG_SCB0_INTR_I2C_EC 0x40240e80 +#define CYFLD_SCB_WAKE_UP__OFFSET 0x00000000 +#define CYFLD_SCB_WAKE_UP__SIZE 0x00000001 +#define CYFLD_SCB_EZ_STOP__OFFSET 0x00000001 +#define CYFLD_SCB_EZ_STOP__SIZE 0x00000001 +#define CYFLD_SCB_EZ_WRITE_STOP__OFFSET 0x00000002 +#define CYFLD_SCB_EZ_WRITE_STOP__SIZE 0x00000001 +#define CYFLD_SCB_EZ_READ_STOP__OFFSET 0x00000003 +#define CYFLD_SCB_EZ_READ_STOP__SIZE 0x00000001 +#define CYREG_SCB0_INTR_I2C_EC_MASK 0x40240e88 +#define CYREG_SCB0_INTR_I2C_EC_MASKED 0x40240e8c +#define CYREG_SCB0_INTR_SPI_EC 0x40240ec0 +#define CYREG_SCB0_INTR_SPI_EC_MASK 0x40240ec8 +#define CYREG_SCB0_INTR_SPI_EC_MASKED 0x40240ecc +#define CYREG_SCB0_INTR_M 0x40240f00 +#define CYFLD_SCB_I2C_ARB_LOST__OFFSET 0x00000000 +#define CYFLD_SCB_I2C_ARB_LOST__SIZE 0x00000001 +#define CYFLD_SCB_I2C_NACK__OFFSET 0x00000001 +#define CYFLD_SCB_I2C_NACK__SIZE 0x00000001 +#define CYFLD_SCB_I2C_ACK__OFFSET 0x00000002 +#define CYFLD_SCB_I2C_ACK__SIZE 0x00000001 +#define CYFLD_SCB_I2C_STOP__OFFSET 0x00000004 +#define CYFLD_SCB_I2C_STOP__SIZE 0x00000001 +#define CYFLD_SCB_I2C_BUS_ERROR__OFFSET 0x00000008 +#define CYFLD_SCB_I2C_BUS_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_SPI_DONE__OFFSET 0x00000009 +#define CYFLD_SCB_SPI_DONE__SIZE 0x00000001 +#define CYREG_SCB0_INTR_M_SET 0x40240f04 +#define CYREG_SCB0_INTR_M_MASK 0x40240f08 +#define CYREG_SCB0_INTR_M_MASKED 0x40240f0c +#define CYREG_SCB0_INTR_S 0x40240f40 +#define CYFLD_SCB_I2C_WRITE_STOP__OFFSET 0x00000003 +#define CYFLD_SCB_I2C_WRITE_STOP__SIZE 0x00000001 +#define CYFLD_SCB_I2C_START__OFFSET 0x00000005 +#define CYFLD_SCB_I2C_START__SIZE 0x00000001 +#define CYFLD_SCB_I2C_ADDR_MATCH__OFFSET 0x00000006 +#define CYFLD_SCB_I2C_ADDR_MATCH__SIZE 0x00000001 +#define CYFLD_SCB_I2C_GENERAL__OFFSET 0x00000007 +#define CYFLD_SCB_I2C_GENERAL__SIZE 0x00000001 +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET 0x00000009 +#define CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE 0x00000001 +#define CYFLD_SCB_SPI_EZ_STOP__OFFSET 0x0000000a +#define CYFLD_SCB_SPI_EZ_STOP__SIZE 0x00000001 +#define CYFLD_SCB_SPI_BUS_ERROR__OFFSET 0x0000000b +#define CYFLD_SCB_SPI_BUS_ERROR__SIZE 0x00000001 +#define CYREG_SCB0_INTR_S_SET 0x40240f44 +#define CYREG_SCB0_INTR_S_MASK 0x40240f48 +#define CYREG_SCB0_INTR_S_MASKED 0x40240f4c +#define CYREG_SCB0_INTR_TX 0x40240f80 +#define CYFLD_SCB_TRIGGER__OFFSET 0x00000000 +#define CYFLD_SCB_TRIGGER__SIZE 0x00000001 +#define CYFLD_SCB_NOT_FULL__OFFSET 0x00000001 +#define CYFLD_SCB_NOT_FULL__SIZE 0x00000001 +#define CYFLD_SCB_EMPTY__OFFSET 0x00000004 +#define CYFLD_SCB_EMPTY__SIZE 0x00000001 +#define CYFLD_SCB_OVERFLOW__OFFSET 0x00000005 +#define CYFLD_SCB_OVERFLOW__SIZE 0x00000001 +#define CYFLD_SCB_UNDERFLOW__OFFSET 0x00000006 +#define CYFLD_SCB_UNDERFLOW__SIZE 0x00000001 +#define CYFLD_SCB_BLOCKED__OFFSET 0x00000007 +#define CYFLD_SCB_BLOCKED__SIZE 0x00000001 +#define CYFLD_SCB_UART_NACK__OFFSET 0x00000008 +#define CYFLD_SCB_UART_NACK__SIZE 0x00000001 +#define CYFLD_SCB_UART_DONE__OFFSET 0x00000009 +#define CYFLD_SCB_UART_DONE__SIZE 0x00000001 +#define CYFLD_SCB_UART_ARB_LOST__OFFSET 0x0000000a +#define CYFLD_SCB_UART_ARB_LOST__SIZE 0x00000001 +#define CYREG_SCB0_INTR_TX_SET 0x40240f84 +#define CYREG_SCB0_INTR_TX_MASK 0x40240f88 +#define CYREG_SCB0_INTR_TX_MASKED 0x40240f8c +#define CYREG_SCB0_INTR_RX 0x40240fc0 +#define CYFLD_SCB_NOT_EMPTY__OFFSET 0x00000002 +#define CYFLD_SCB_NOT_EMPTY__SIZE 0x00000001 +#define CYFLD_SCB_FULL__OFFSET 0x00000003 +#define CYFLD_SCB_FULL__SIZE 0x00000001 +#define CYFLD_SCB_FRAME_ERROR__OFFSET 0x00000008 +#define CYFLD_SCB_FRAME_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_PARITY_ERROR__OFFSET 0x00000009 +#define CYFLD_SCB_PARITY_ERROR__SIZE 0x00000001 +#define CYFLD_SCB_BAUD_DETECT__OFFSET 0x0000000a +#define CYFLD_SCB_BAUD_DETECT__SIZE 0x00000001 +#define CYFLD_SCB_BREAK_DETECT__OFFSET 0x0000000b +#define CYFLD_SCB_BREAK_DETECT__SIZE 0x00000001 +#define CYREG_SCB0_INTR_RX_SET 0x40240fc4 +#define CYREG_SCB0_INTR_RX_MASK 0x40240fc8 +#define CYREG_SCB0_INTR_RX_MASKED 0x40240fcc +#define CYDEV_SCB1_BASE 0x40250000 +#define CYDEV_SCB1_SIZE 0x00010000 +#define CYREG_SCB1_CTRL 0x40250000 +#define CYREG_SCB1_STATUS 0x40250004 +#define CYREG_SCB1_SPI_CTRL 0x40250020 +#define CYREG_SCB1_SPI_STATUS 0x40250024 +#define CYREG_SCB1_UART_CTRL 0x40250040 +#define CYREG_SCB1_UART_TX_CTRL 0x40250044 +#define CYREG_SCB1_UART_RX_CTRL 0x40250048 +#define CYREG_SCB1_UART_RX_STATUS 0x4025004c +#define CYREG_SCB1_UART_FLOW_CTRL 0x40250050 +#define CYREG_SCB1_I2C_CTRL 0x40250060 +#define CYREG_SCB1_I2C_STATUS 0x40250064 +#define CYREG_SCB1_I2C_M_CMD 0x40250068 +#define CYREG_SCB1_I2C_S_CMD 0x4025006c +#define CYREG_SCB1_I2C_CFG 0x40250070 +#define CYREG_SCB1_TX_CTRL 0x40250200 +#define CYREG_SCB1_TX_FIFO_CTRL 0x40250204 +#define CYREG_SCB1_TX_FIFO_STATUS 0x40250208 +#define CYREG_SCB1_TX_FIFO_WR 0x40250240 +#define CYREG_SCB1_RX_CTRL 0x40250300 +#define CYREG_SCB1_RX_FIFO_CTRL 0x40250304 +#define CYREG_SCB1_RX_FIFO_STATUS 0x40250308 +#define CYREG_SCB1_RX_MATCH 0x40250310 +#define CYREG_SCB1_RX_FIFO_RD 0x40250340 +#define CYREG_SCB1_RX_FIFO_RD_SILENT 0x40250344 +#define CYREG_SCB1_EZ_DATA0 0x40250400 +#define CYREG_SCB1_EZ_DATA1 0x40250404 +#define CYREG_SCB1_EZ_DATA2 0x40250408 +#define CYREG_SCB1_EZ_DATA3 0x4025040c +#define CYREG_SCB1_EZ_DATA4 0x40250410 +#define CYREG_SCB1_EZ_DATA5 0x40250414 +#define CYREG_SCB1_EZ_DATA6 0x40250418 +#define CYREG_SCB1_EZ_DATA7 0x4025041c +#define CYREG_SCB1_EZ_DATA8 0x40250420 +#define CYREG_SCB1_EZ_DATA9 0x40250424 +#define CYREG_SCB1_EZ_DATA10 0x40250428 +#define CYREG_SCB1_EZ_DATA11 0x4025042c +#define CYREG_SCB1_EZ_DATA12 0x40250430 +#define CYREG_SCB1_EZ_DATA13 0x40250434 +#define CYREG_SCB1_EZ_DATA14 0x40250438 +#define CYREG_SCB1_EZ_DATA15 0x4025043c +#define CYREG_SCB1_EZ_DATA16 0x40250440 +#define CYREG_SCB1_EZ_DATA17 0x40250444 +#define CYREG_SCB1_EZ_DATA18 0x40250448 +#define CYREG_SCB1_EZ_DATA19 0x4025044c +#define CYREG_SCB1_EZ_DATA20 0x40250450 +#define CYREG_SCB1_EZ_DATA21 0x40250454 +#define CYREG_SCB1_EZ_DATA22 0x40250458 +#define CYREG_SCB1_EZ_DATA23 0x4025045c +#define CYREG_SCB1_EZ_DATA24 0x40250460 +#define CYREG_SCB1_EZ_DATA25 0x40250464 +#define CYREG_SCB1_EZ_DATA26 0x40250468 +#define CYREG_SCB1_EZ_DATA27 0x4025046c +#define CYREG_SCB1_EZ_DATA28 0x40250470 +#define CYREG_SCB1_EZ_DATA29 0x40250474 +#define CYREG_SCB1_EZ_DATA30 0x40250478 +#define CYREG_SCB1_EZ_DATA31 0x4025047c +#define CYREG_SCB1_INTR_CAUSE 0x40250e00 +#define CYREG_SCB1_INTR_I2C_EC 0x40250e80 +#define CYREG_SCB1_INTR_I2C_EC_MASK 0x40250e88 +#define CYREG_SCB1_INTR_I2C_EC_MASKED 0x40250e8c +#define CYREG_SCB1_INTR_SPI_EC 0x40250ec0 +#define CYREG_SCB1_INTR_SPI_EC_MASK 0x40250ec8 +#define CYREG_SCB1_INTR_SPI_EC_MASKED 0x40250ecc +#define CYREG_SCB1_INTR_M 0x40250f00 +#define CYREG_SCB1_INTR_M_SET 0x40250f04 +#define CYREG_SCB1_INTR_M_MASK 0x40250f08 +#define CYREG_SCB1_INTR_M_MASKED 0x40250f0c +#define CYREG_SCB1_INTR_S 0x40250f40 +#define CYREG_SCB1_INTR_S_SET 0x40250f44 +#define CYREG_SCB1_INTR_S_MASK 0x40250f48 +#define CYREG_SCB1_INTR_S_MASKED 0x40250f4c +#define CYREG_SCB1_INTR_TX 0x40250f80 +#define CYREG_SCB1_INTR_TX_SET 0x40250f84 +#define CYREG_SCB1_INTR_TX_MASK 0x40250f88 +#define CYREG_SCB1_INTR_TX_MASKED 0x40250f8c +#define CYREG_SCB1_INTR_RX 0x40250fc0 +#define CYREG_SCB1_INTR_RX_SET 0x40250fc4 +#define CYREG_SCB1_INTR_RX_MASK 0x40250fc8 +#define CYREG_SCB1_INTR_RX_MASKED 0x40250fcc +#define CYDEV_SCB2_BASE 0x40260000 +#define CYDEV_SCB2_SIZE 0x00010000 +#define CYREG_SCB2_CTRL 0x40260000 +#define CYREG_SCB2_STATUS 0x40260004 +#define CYREG_SCB2_SPI_CTRL 0x40260020 +#define CYREG_SCB2_SPI_STATUS 0x40260024 +#define CYREG_SCB2_UART_CTRL 0x40260040 +#define CYREG_SCB2_UART_TX_CTRL 0x40260044 +#define CYREG_SCB2_UART_RX_CTRL 0x40260048 +#define CYREG_SCB2_UART_RX_STATUS 0x4026004c +#define CYREG_SCB2_UART_FLOW_CTRL 0x40260050 +#define CYREG_SCB2_I2C_CTRL 0x40260060 +#define CYREG_SCB2_I2C_STATUS 0x40260064 +#define CYREG_SCB2_I2C_M_CMD 0x40260068 +#define CYREG_SCB2_I2C_S_CMD 0x4026006c +#define CYREG_SCB2_I2C_CFG 0x40260070 +#define CYREG_SCB2_TX_CTRL 0x40260200 +#define CYREG_SCB2_TX_FIFO_CTRL 0x40260204 +#define CYREG_SCB2_TX_FIFO_STATUS 0x40260208 +#define CYREG_SCB2_TX_FIFO_WR 0x40260240 +#define CYREG_SCB2_RX_CTRL 0x40260300 +#define CYREG_SCB2_RX_FIFO_CTRL 0x40260304 +#define CYREG_SCB2_RX_FIFO_STATUS 0x40260308 +#define CYREG_SCB2_RX_MATCH 0x40260310 +#define CYREG_SCB2_RX_FIFO_RD 0x40260340 +#define CYREG_SCB2_RX_FIFO_RD_SILENT 0x40260344 +#define CYREG_SCB2_EZ_DATA0 0x40260400 +#define CYREG_SCB2_EZ_DATA1 0x40260404 +#define CYREG_SCB2_EZ_DATA2 0x40260408 +#define CYREG_SCB2_EZ_DATA3 0x4026040c +#define CYREG_SCB2_EZ_DATA4 0x40260410 +#define CYREG_SCB2_EZ_DATA5 0x40260414 +#define CYREG_SCB2_EZ_DATA6 0x40260418 +#define CYREG_SCB2_EZ_DATA7 0x4026041c +#define CYREG_SCB2_EZ_DATA8 0x40260420 +#define CYREG_SCB2_EZ_DATA9 0x40260424 +#define CYREG_SCB2_EZ_DATA10 0x40260428 +#define CYREG_SCB2_EZ_DATA11 0x4026042c +#define CYREG_SCB2_EZ_DATA12 0x40260430 +#define CYREG_SCB2_EZ_DATA13 0x40260434 +#define CYREG_SCB2_EZ_DATA14 0x40260438 +#define CYREG_SCB2_EZ_DATA15 0x4026043c +#define CYREG_SCB2_EZ_DATA16 0x40260440 +#define CYREG_SCB2_EZ_DATA17 0x40260444 +#define CYREG_SCB2_EZ_DATA18 0x40260448 +#define CYREG_SCB2_EZ_DATA19 0x4026044c +#define CYREG_SCB2_EZ_DATA20 0x40260450 +#define CYREG_SCB2_EZ_DATA21 0x40260454 +#define CYREG_SCB2_EZ_DATA22 0x40260458 +#define CYREG_SCB2_EZ_DATA23 0x4026045c +#define CYREG_SCB2_EZ_DATA24 0x40260460 +#define CYREG_SCB2_EZ_DATA25 0x40260464 +#define CYREG_SCB2_EZ_DATA26 0x40260468 +#define CYREG_SCB2_EZ_DATA27 0x4026046c +#define CYREG_SCB2_EZ_DATA28 0x40260470 +#define CYREG_SCB2_EZ_DATA29 0x40260474 +#define CYREG_SCB2_EZ_DATA30 0x40260478 +#define CYREG_SCB2_EZ_DATA31 0x4026047c +#define CYREG_SCB2_INTR_CAUSE 0x40260e00 +#define CYREG_SCB2_INTR_I2C_EC 0x40260e80 +#define CYREG_SCB2_INTR_I2C_EC_MASK 0x40260e88 +#define CYREG_SCB2_INTR_I2C_EC_MASKED 0x40260e8c +#define CYREG_SCB2_INTR_SPI_EC 0x40260ec0 +#define CYREG_SCB2_INTR_SPI_EC_MASK 0x40260ec8 +#define CYREG_SCB2_INTR_SPI_EC_MASKED 0x40260ecc +#define CYREG_SCB2_INTR_M 0x40260f00 +#define CYREG_SCB2_INTR_M_SET 0x40260f04 +#define CYREG_SCB2_INTR_M_MASK 0x40260f08 +#define CYREG_SCB2_INTR_M_MASKED 0x40260f0c +#define CYREG_SCB2_INTR_S 0x40260f40 +#define CYREG_SCB2_INTR_S_SET 0x40260f44 +#define CYREG_SCB2_INTR_S_MASK 0x40260f48 +#define CYREG_SCB2_INTR_S_MASKED 0x40260f4c +#define CYREG_SCB2_INTR_TX 0x40260f80 +#define CYREG_SCB2_INTR_TX_SET 0x40260f84 +#define CYREG_SCB2_INTR_TX_MASK 0x40260f88 +#define CYREG_SCB2_INTR_TX_MASKED 0x40260f8c +#define CYREG_SCB2_INTR_RX 0x40260fc0 +#define CYREG_SCB2_INTR_RX_SET 0x40260fc4 +#define CYREG_SCB2_INTR_RX_MASK 0x40260fc8 +#define CYREG_SCB2_INTR_RX_MASKED 0x40260fcc +#define CYDEV_SCB3_BASE 0x40270000 +#define CYDEV_SCB3_SIZE 0x00010000 +#define CYREG_SCB3_CTRL 0x40270000 +#define CYREG_SCB3_STATUS 0x40270004 +#define CYREG_SCB3_SPI_CTRL 0x40270020 +#define CYREG_SCB3_SPI_STATUS 0x40270024 +#define CYREG_SCB3_UART_CTRL 0x40270040 +#define CYREG_SCB3_UART_TX_CTRL 0x40270044 +#define CYREG_SCB3_UART_RX_CTRL 0x40270048 +#define CYREG_SCB3_UART_RX_STATUS 0x4027004c +#define CYREG_SCB3_UART_FLOW_CTRL 0x40270050 +#define CYREG_SCB3_I2C_CTRL 0x40270060 +#define CYREG_SCB3_I2C_STATUS 0x40270064 +#define CYREG_SCB3_I2C_M_CMD 0x40270068 +#define CYREG_SCB3_I2C_S_CMD 0x4027006c +#define CYREG_SCB3_I2C_CFG 0x40270070 +#define CYREG_SCB3_TX_CTRL 0x40270200 +#define CYREG_SCB3_TX_FIFO_CTRL 0x40270204 +#define CYREG_SCB3_TX_FIFO_STATUS 0x40270208 +#define CYREG_SCB3_TX_FIFO_WR 0x40270240 +#define CYREG_SCB3_RX_CTRL 0x40270300 +#define CYREG_SCB3_RX_FIFO_CTRL 0x40270304 +#define CYREG_SCB3_RX_FIFO_STATUS 0x40270308 +#define CYREG_SCB3_RX_MATCH 0x40270310 +#define CYREG_SCB3_RX_FIFO_RD 0x40270340 +#define CYREG_SCB3_RX_FIFO_RD_SILENT 0x40270344 +#define CYREG_SCB3_EZ_DATA0 0x40270400 +#define CYREG_SCB3_EZ_DATA1 0x40270404 +#define CYREG_SCB3_EZ_DATA2 0x40270408 +#define CYREG_SCB3_EZ_DATA3 0x4027040c +#define CYREG_SCB3_EZ_DATA4 0x40270410 +#define CYREG_SCB3_EZ_DATA5 0x40270414 +#define CYREG_SCB3_EZ_DATA6 0x40270418 +#define CYREG_SCB3_EZ_DATA7 0x4027041c +#define CYREG_SCB3_EZ_DATA8 0x40270420 +#define CYREG_SCB3_EZ_DATA9 0x40270424 +#define CYREG_SCB3_EZ_DATA10 0x40270428 +#define CYREG_SCB3_EZ_DATA11 0x4027042c +#define CYREG_SCB3_EZ_DATA12 0x40270430 +#define CYREG_SCB3_EZ_DATA13 0x40270434 +#define CYREG_SCB3_EZ_DATA14 0x40270438 +#define CYREG_SCB3_EZ_DATA15 0x4027043c +#define CYREG_SCB3_EZ_DATA16 0x40270440 +#define CYREG_SCB3_EZ_DATA17 0x40270444 +#define CYREG_SCB3_EZ_DATA18 0x40270448 +#define CYREG_SCB3_EZ_DATA19 0x4027044c +#define CYREG_SCB3_EZ_DATA20 0x40270450 +#define CYREG_SCB3_EZ_DATA21 0x40270454 +#define CYREG_SCB3_EZ_DATA22 0x40270458 +#define CYREG_SCB3_EZ_DATA23 0x4027045c +#define CYREG_SCB3_EZ_DATA24 0x40270460 +#define CYREG_SCB3_EZ_DATA25 0x40270464 +#define CYREG_SCB3_EZ_DATA26 0x40270468 +#define CYREG_SCB3_EZ_DATA27 0x4027046c +#define CYREG_SCB3_EZ_DATA28 0x40270470 +#define CYREG_SCB3_EZ_DATA29 0x40270474 +#define CYREG_SCB3_EZ_DATA30 0x40270478 +#define CYREG_SCB3_EZ_DATA31 0x4027047c +#define CYREG_SCB3_INTR_CAUSE 0x40270e00 +#define CYREG_SCB3_INTR_I2C_EC 0x40270e80 +#define CYREG_SCB3_INTR_I2C_EC_MASK 0x40270e88 +#define CYREG_SCB3_INTR_I2C_EC_MASKED 0x40270e8c +#define CYREG_SCB3_INTR_SPI_EC 0x40270ec0 +#define CYREG_SCB3_INTR_SPI_EC_MASK 0x40270ec8 +#define CYREG_SCB3_INTR_SPI_EC_MASKED 0x40270ecc +#define CYREG_SCB3_INTR_M 0x40270f00 +#define CYREG_SCB3_INTR_M_SET 0x40270f04 +#define CYREG_SCB3_INTR_M_MASK 0x40270f08 +#define CYREG_SCB3_INTR_M_MASKED 0x40270f0c +#define CYREG_SCB3_INTR_S 0x40270f40 +#define CYREG_SCB3_INTR_S_SET 0x40270f44 +#define CYREG_SCB3_INTR_S_MASK 0x40270f48 +#define CYREG_SCB3_INTR_S_MASKED 0x40270f4c +#define CYREG_SCB3_INTR_TX 0x40270f80 +#define CYREG_SCB3_INTR_TX_SET 0x40270f84 +#define CYREG_SCB3_INTR_TX_MASK 0x40270f88 +#define CYREG_SCB3_INTR_TX_MASKED 0x40270f8c +#define CYREG_SCB3_INTR_RX 0x40270fc0 +#define CYREG_SCB3_INTR_RX_SET 0x40270fc4 +#define CYREG_SCB3_INTR_RX_MASK 0x40270fc8 +#define CYREG_SCB3_INTR_RX_MASKED 0x40270fcc +#define CYDEV_SCB4_BASE 0x40280000 +#define CYDEV_SCB4_SIZE 0x00010000 +#define CYREG_SCB4_CTRL 0x40280000 +#define CYREG_SCB4_STATUS 0x40280004 +#define CYREG_SCB4_SPI_CTRL 0x40280020 +#define CYREG_SCB4_SPI_STATUS 0x40280024 +#define CYREG_SCB4_UART_CTRL 0x40280040 +#define CYREG_SCB4_UART_TX_CTRL 0x40280044 +#define CYREG_SCB4_UART_RX_CTRL 0x40280048 +#define CYREG_SCB4_UART_RX_STATUS 0x4028004c +#define CYREG_SCB4_UART_FLOW_CTRL 0x40280050 +#define CYREG_SCB4_I2C_CTRL 0x40280060 +#define CYREG_SCB4_I2C_STATUS 0x40280064 +#define CYREG_SCB4_I2C_M_CMD 0x40280068 +#define CYREG_SCB4_I2C_S_CMD 0x4028006c +#define CYREG_SCB4_I2C_CFG 0x40280070 +#define CYREG_SCB4_TX_CTRL 0x40280200 +#define CYREG_SCB4_TX_FIFO_CTRL 0x40280204 +#define CYREG_SCB4_TX_FIFO_STATUS 0x40280208 +#define CYREG_SCB4_TX_FIFO_WR 0x40280240 +#define CYREG_SCB4_RX_CTRL 0x40280300 +#define CYREG_SCB4_RX_FIFO_CTRL 0x40280304 +#define CYREG_SCB4_RX_FIFO_STATUS 0x40280308 +#define CYREG_SCB4_RX_MATCH 0x40280310 +#define CYREG_SCB4_RX_FIFO_RD 0x40280340 +#define CYREG_SCB4_RX_FIFO_RD_SILENT 0x40280344 +#define CYREG_SCB4_EZ_DATA0 0x40280400 +#define CYREG_SCB4_EZ_DATA1 0x40280404 +#define CYREG_SCB4_EZ_DATA2 0x40280408 +#define CYREG_SCB4_EZ_DATA3 0x4028040c +#define CYREG_SCB4_EZ_DATA4 0x40280410 +#define CYREG_SCB4_EZ_DATA5 0x40280414 +#define CYREG_SCB4_EZ_DATA6 0x40280418 +#define CYREG_SCB4_EZ_DATA7 0x4028041c +#define CYREG_SCB4_EZ_DATA8 0x40280420 +#define CYREG_SCB4_EZ_DATA9 0x40280424 +#define CYREG_SCB4_EZ_DATA10 0x40280428 +#define CYREG_SCB4_EZ_DATA11 0x4028042c +#define CYREG_SCB4_EZ_DATA12 0x40280430 +#define CYREG_SCB4_EZ_DATA13 0x40280434 +#define CYREG_SCB4_EZ_DATA14 0x40280438 +#define CYREG_SCB4_EZ_DATA15 0x4028043c +#define CYREG_SCB4_EZ_DATA16 0x40280440 +#define CYREG_SCB4_EZ_DATA17 0x40280444 +#define CYREG_SCB4_EZ_DATA18 0x40280448 +#define CYREG_SCB4_EZ_DATA19 0x4028044c +#define CYREG_SCB4_EZ_DATA20 0x40280450 +#define CYREG_SCB4_EZ_DATA21 0x40280454 +#define CYREG_SCB4_EZ_DATA22 0x40280458 +#define CYREG_SCB4_EZ_DATA23 0x4028045c +#define CYREG_SCB4_EZ_DATA24 0x40280460 +#define CYREG_SCB4_EZ_DATA25 0x40280464 +#define CYREG_SCB4_EZ_DATA26 0x40280468 +#define CYREG_SCB4_EZ_DATA27 0x4028046c +#define CYREG_SCB4_EZ_DATA28 0x40280470 +#define CYREG_SCB4_EZ_DATA29 0x40280474 +#define CYREG_SCB4_EZ_DATA30 0x40280478 +#define CYREG_SCB4_EZ_DATA31 0x4028047c +#define CYREG_SCB4_INTR_CAUSE 0x40280e00 +#define CYREG_SCB4_INTR_I2C_EC 0x40280e80 +#define CYREG_SCB4_INTR_I2C_EC_MASK 0x40280e88 +#define CYREG_SCB4_INTR_I2C_EC_MASKED 0x40280e8c +#define CYREG_SCB4_INTR_SPI_EC 0x40280ec0 +#define CYREG_SCB4_INTR_SPI_EC_MASK 0x40280ec8 +#define CYREG_SCB4_INTR_SPI_EC_MASKED 0x40280ecc +#define CYREG_SCB4_INTR_M 0x40280f00 +#define CYREG_SCB4_INTR_M_SET 0x40280f04 +#define CYREG_SCB4_INTR_M_MASK 0x40280f08 +#define CYREG_SCB4_INTR_M_MASKED 0x40280f0c +#define CYREG_SCB4_INTR_S 0x40280f40 +#define CYREG_SCB4_INTR_S_SET 0x40280f44 +#define CYREG_SCB4_INTR_S_MASK 0x40280f48 +#define CYREG_SCB4_INTR_S_MASKED 0x40280f4c +#define CYREG_SCB4_INTR_TX 0x40280f80 +#define CYREG_SCB4_INTR_TX_SET 0x40280f84 +#define CYREG_SCB4_INTR_TX_MASK 0x40280f88 +#define CYREG_SCB4_INTR_TX_MASKED 0x40280f8c +#define CYREG_SCB4_INTR_RX 0x40280fc0 +#define CYREG_SCB4_INTR_RX_SET 0x40280fc4 +#define CYREG_SCB4_INTR_RX_MASK 0x40280fc8 +#define CYREG_SCB4_INTR_RX_MASKED 0x40280fcc +#define CYDEV_CSD_BASE 0x40290000 +#define CYDEV_CSD_SIZE 0x00001000 +#define CYREG_CSD_CONFIG 0x40290000 +#define CYFLD_CSD_LOW_VDDA__OFFSET 0x00000003 +#define CYFLD_CSD_LOW_VDDA__SIZE 0x00000001 +#define CYFLD_CSD_FILTER_DELAY__OFFSET 0x00000004 +#define CYFLD_CSD_FILTER_DELAY__SIZE 0x00000003 +#define CYFLD_CSD_SHIELD_DELAY__OFFSET 0x00000008 +#define CYFLD_CSD_SHIELD_DELAY__SIZE 0x00000002 +#define CYVAL_CSD_SHIELD_DELAY_OFF 0x00000000 +#define CYVAL_CSD_SHIELD_DELAY_D5NS 0x00000001 +#define CYVAL_CSD_SHIELD_DELAY_D10NS 0x00000002 +#define CYVAL_CSD_SHIELD_DELAY_D20NS 0x00000003 +#define CYFLD_CSD_SENSE_EN__OFFSET 0x0000000c +#define CYFLD_CSD_SENSE_EN__SIZE 0x00000001 +#define CYFLD_CSD_CHARGE_MODE__OFFSET 0x0000000e +#define CYFLD_CSD_CHARGE_MODE__SIZE 0x00000001 +#define CYVAL_CSD_CHARGE_MODE_CHARGE_OFF 0x00000000 +#define CYVAL_CSD_CHARGE_MODE_CHARGE_IO 0x00000001 +#define CYFLD_CSD_FULL_WAVE__OFFSET 0x00000011 +#define CYFLD_CSD_FULL_WAVE__SIZE 0x00000001 +#define CYVAL_CSD_FULL_WAVE_HALFWAVE 0x00000000 +#define CYVAL_CSD_FULL_WAVE_FULLWAVE 0x00000001 +#define CYFLD_CSD_MUTUAL_CAP__OFFSET 0x00000012 +#define CYFLD_CSD_MUTUAL_CAP__SIZE 0x00000001 +#define CYVAL_CSD_MUTUAL_CAP_SELFCAP 0x00000000 +#define CYVAL_CSD_MUTUAL_CAP_MUTUALCAP 0x00000001 +#define CYFLD_CSD_CSX_DUAL_CNT__OFFSET 0x00000013 +#define CYFLD_CSD_CSX_DUAL_CNT__SIZE 0x00000001 +#define CYVAL_CSD_CSX_DUAL_CNT_ONE 0x00000000 +#define CYVAL_CSD_CSX_DUAL_CNT_TWO 0x00000001 +#define CYFLD_CSD_DSI_COUNT_SEL__OFFSET 0x00000018 +#define CYFLD_CSD_DSI_COUNT_SEL__SIZE 0x00000001 +#define CYVAL_CSD_DSI_COUNT_SEL_CSD_RESULT 0x00000000 +#define CYVAL_CSD_DSI_COUNT_SEL_ADC_RESULT 0x00000001 +#define CYFLD_CSD_DSI_SAMPLE_EN__OFFSET 0x00000019 +#define CYFLD_CSD_DSI_SAMPLE_EN__SIZE 0x00000001 +#define CYFLD_CSD_SAMPLE_SYNC__OFFSET 0x0000001a +#define CYFLD_CSD_SAMPLE_SYNC__SIZE 0x00000001 +#define CYFLD_CSD_DSI_SENSE_EN__OFFSET 0x0000001b +#define CYFLD_CSD_DSI_SENSE_EN__SIZE 0x00000001 +#define CYFLD_CSD_LP_MODE__OFFSET 0x0000001e +#define CYFLD_CSD_LP_MODE__SIZE 0x00000001 +#define CYFLD_CSD_ENABLE__OFFSET 0x0000001f +#define CYFLD_CSD_ENABLE__SIZE 0x00000001 +#define CYREG_CSD_SPARE 0x40290004 +#define CYFLD_CSD_SPARE__OFFSET 0x00000000 +#define CYFLD_CSD_SPARE__SIZE 0x00000004 +#define CYREG_CSD_STATUS 0x40290080 +#define CYFLD_CSD_CSD_CHARGE__OFFSET 0x00000000 +#define CYFLD_CSD_CSD_CHARGE__SIZE 0x00000001 +#define CYFLD_CSD_CSD_SENSE__OFFSET 0x00000001 +#define CYFLD_CSD_CSD_SENSE__SIZE 0x00000001 +#define CYFLD_CSD_HSCMP_OUT__OFFSET 0x00000002 +#define CYFLD_CSD_HSCMP_OUT__SIZE 0x00000001 +#define CYVAL_CSD_HSCMP_OUT_C_LT_VREF 0x00000000 +#define CYVAL_CSD_HSCMP_OUT_C_GT_VREF 0x00000001 +#define CYFLD_CSD_CSDCMP_OUT__OFFSET 0x00000003 +#define CYFLD_CSD_CSDCMP_OUT__SIZE 0x00000001 +#define CYREG_CSD_STAT_SEQ 0x40290084 +#define CYFLD_CSD_SEQ_STATE__OFFSET 0x00000000 +#define CYFLD_CSD_SEQ_STATE__SIZE 0x00000003 +#define CYFLD_CSD_ADC_STATE__OFFSET 0x00000010 +#define CYFLD_CSD_ADC_STATE__SIZE 0x00000003 +#define CYREG_CSD_STAT_CNTS 0x40290088 +#define CYFLD_CSD_NUM_CONV__OFFSET 0x00000000 +#define CYFLD_CSD_NUM_CONV__SIZE 0x00000010 +#define CYREG_CSD_STAT_HCNT 0x4029008c +#define CYFLD_CSD_CNT__OFFSET 0x00000000 +#define CYFLD_CSD_CNT__SIZE 0x00000010 +#define CYREG_CSD_RESULT_VAL1 0x402900d0 +#define CYFLD_CSD_VALUE__OFFSET 0x00000000 +#define CYFLD_CSD_VALUE__SIZE 0x00000010 +#define CYFLD_CSD_BAD_CONVS__OFFSET 0x00000010 +#define CYFLD_CSD_BAD_CONVS__SIZE 0x00000008 +#define CYREG_CSD_RESULT_VAL2 0x402900d4 +#define CYREG_CSD_ADC_RES 0x402900e0 +#define CYFLD_CSD_VIN_CNT__OFFSET 0x00000000 +#define CYFLD_CSD_VIN_CNT__SIZE 0x00000010 +#define CYFLD_CSD_HSCMP_POL__OFFSET 0x00000010 +#define CYFLD_CSD_HSCMP_POL__SIZE 0x00000001 +#define CYFLD_CSD_ADC_OVERFLOW__OFFSET 0x0000001e +#define CYFLD_CSD_ADC_OVERFLOW__SIZE 0x00000001 +#define CYFLD_CSD_ADC_ABORT__OFFSET 0x0000001f +#define CYFLD_CSD_ADC_ABORT__SIZE 0x00000001 +#define CYREG_CSD_INTR 0x402900f0 +#define CYFLD_CSD_SAMPLE__OFFSET 0x00000001 +#define CYFLD_CSD_SAMPLE__SIZE 0x00000001 +#define CYFLD_CSD_INIT__OFFSET 0x00000002 +#define CYFLD_CSD_INIT__SIZE 0x00000001 +#define CYFLD_CSD_ADC_RES__OFFSET 0x00000008 +#define CYFLD_CSD_ADC_RES__SIZE 0x00000001 +#define CYREG_CSD_INTR_SET 0x402900f4 +#define CYREG_CSD_INTR_MASK 0x402900f8 +#define CYREG_CSD_INTR_MASKED 0x402900fc +#define CYREG_CSD_HSCMP 0x40290180 +#define CYFLD_CSD_HSCMP_EN__OFFSET 0x00000000 +#define CYFLD_CSD_HSCMP_EN__SIZE 0x00000001 +#define CYVAL_CSD_HSCMP_EN_OFF 0x00000000 +#define CYVAL_CSD_HSCMP_EN_ON 0x00000001 +#define CYFLD_CSD_HSCMP_INVERT__OFFSET 0x00000004 +#define CYFLD_CSD_HSCMP_INVERT__SIZE 0x00000001 +#define CYFLD_CSD_AZ_EN__OFFSET 0x0000001f +#define CYFLD_CSD_AZ_EN__SIZE 0x00000001 +#define CYREG_CSD_AMBUF 0x40290184 +#define CYFLD_CSD_PWR_MODE__OFFSET 0x00000000 +#define CYFLD_CSD_PWR_MODE__SIZE 0x00000002 +#define CYVAL_CSD_PWR_MODE_OFF 0x00000000 +#define CYVAL_CSD_PWR_MODE_NORM 0x00000001 +#define CYVAL_CSD_PWR_MODE_HI 0x00000002 +#define CYREG_CSD_REFGEN 0x40290188 +#define CYFLD_CSD_REFGEN_EN__OFFSET 0x00000000 +#define CYFLD_CSD_REFGEN_EN__SIZE 0x00000001 +#define CYVAL_CSD_REFGEN_EN_OFF 0x00000000 +#define CYVAL_CSD_REFGEN_EN_ON 0x00000001 +#define CYFLD_CSD_BYPASS__OFFSET 0x00000004 +#define CYFLD_CSD_BYPASS__SIZE 0x00000001 +#define CYFLD_CSD_VDDA_EN__OFFSET 0x00000005 +#define CYFLD_CSD_VDDA_EN__SIZE 0x00000001 +#define CYFLD_CSD_RES_EN__OFFSET 0x00000006 +#define CYFLD_CSD_RES_EN__SIZE 0x00000001 +#define CYFLD_CSD_GAIN__OFFSET 0x00000008 +#define CYFLD_CSD_GAIN__SIZE 0x00000005 +#define CYFLD_CSD_VREFLO_SEL__OFFSET 0x00000010 +#define CYFLD_CSD_VREFLO_SEL__SIZE 0x00000005 +#define CYFLD_CSD_VREFLO_INT__OFFSET 0x00000017 +#define CYFLD_CSD_VREFLO_INT__SIZE 0x00000001 +#define CYREG_CSD_CSDCMP 0x4029018c +#define CYFLD_CSD_CSDCMP_EN__OFFSET 0x00000000 +#define CYFLD_CSD_CSDCMP_EN__SIZE 0x00000001 +#define CYVAL_CSD_CSDCMP_EN_OFF 0x00000000 +#define CYVAL_CSD_CSDCMP_EN_ON 0x00000001 +#define CYFLD_CSD_POLARITY_SEL__OFFSET 0x00000004 +#define CYFLD_CSD_POLARITY_SEL__SIZE 0x00000002 +#define CYVAL_CSD_POLARITY_SEL_IDACA_POL 0x00000000 +#define CYVAL_CSD_POLARITY_SEL_IDACB_POL 0x00000001 +#define CYVAL_CSD_POLARITY_SEL_DUAL_POL 0x00000002 +#define CYFLD_CSD_CMP_PHASE__OFFSET 0x00000008 +#define CYFLD_CSD_CMP_PHASE__SIZE 0x00000002 +#define CYVAL_CSD_CMP_PHASE_FULL 0x00000000 +#define CYVAL_CSD_CMP_PHASE_PHI1 0x00000001 +#define CYVAL_CSD_CMP_PHASE_PHI2 0x00000002 +#define CYVAL_CSD_CMP_PHASE_PHI1_2 0x00000003 +#define CYFLD_CSD_CMP_MODE__OFFSET 0x0000001c +#define CYFLD_CSD_CMP_MODE__SIZE 0x00000001 +#define CYVAL_CSD_CMP_MODE_CSD 0x00000000 +#define CYVAL_CSD_CMP_MODE_GP 0x00000001 +#define CYFLD_CSD_FEEDBACK_MODE__OFFSET 0x0000001d +#define CYFLD_CSD_FEEDBACK_MODE__SIZE 0x00000001 +#define CYVAL_CSD_FEEDBACK_MODE_FLOP 0x00000000 +#define CYVAL_CSD_FEEDBACK_MODE_COMP 0x00000001 +#define CYREG_CSD_IDACA 0x402901c0 +#define CYFLD_CSD_VAL__OFFSET 0x00000000 +#define CYFLD_CSD_VAL__SIZE 0x00000007 +#define CYFLD_CSD_POL_DYN__OFFSET 0x00000007 +#define CYFLD_CSD_POL_DYN__SIZE 0x00000001 +#define CYVAL_CSD_POL_DYN_STATIC 0x00000000 +#define CYVAL_CSD_POL_DYN_DYNAMIC 0x00000001 +#define CYFLD_CSD_POLARITY__OFFSET 0x00000008 +#define CYFLD_CSD_POLARITY__SIZE 0x00000002 +#define CYVAL_CSD_POLARITY_VSSA_SRC 0x00000000 +#define CYVAL_CSD_POLARITY_VDDA_SNK 0x00000001 +#define CYVAL_CSD_POLARITY_SENSE 0x00000002 +#define CYVAL_CSD_POLARITY_SENSE_INV 0x00000003 +#define CYFLD_CSD_BAL_MODE__OFFSET 0x0000000a +#define CYFLD_CSD_BAL_MODE__SIZE 0x00000002 +#define CYVAL_CSD_BAL_MODE_FULL 0x00000000 +#define CYVAL_CSD_BAL_MODE_PHI1 0x00000001 +#define CYVAL_CSD_BAL_MODE_PHI2 0x00000002 +#define CYVAL_CSD_BAL_MODE_PHI1_2 0x00000003 +#define CYFLD_CSD_LEG1_MODE__OFFSET 0x00000010 +#define CYFLD_CSD_LEG1_MODE__SIZE 0x00000002 +#define CYVAL_CSD_LEG1_MODE_GP_STATIC 0x00000000 +#define CYVAL_CSD_LEG1_MODE_GP 0x00000001 +#define CYVAL_CSD_LEG1_MODE_CSD_STATIC 0x00000002 +#define CYVAL_CSD_LEG1_MODE_CSD 0x00000003 +#define CYFLD_CSD_LEG2_MODE__OFFSET 0x00000012 +#define CYFLD_CSD_LEG2_MODE__SIZE 0x00000002 +#define CYVAL_CSD_LEG2_MODE_GP_STATIC 0x00000000 +#define CYVAL_CSD_LEG2_MODE_GP 0x00000001 +#define CYVAL_CSD_LEG2_MODE_CSD_STATIC 0x00000002 +#define CYVAL_CSD_LEG2_MODE_CSD 0x00000003 +#define CYFLD_CSD_DSI_CTRL_EN__OFFSET 0x00000015 +#define CYFLD_CSD_DSI_CTRL_EN__SIZE 0x00000001 +#define CYFLD_CSD_RANGE__OFFSET 0x00000016 +#define CYFLD_CSD_RANGE__SIZE 0x00000002 +#define CYVAL_CSD_RANGE_IDAC_LO 0x00000000 +#define CYVAL_CSD_RANGE_IDAC_MED 0x00000001 +#define CYVAL_CSD_RANGE_IDAC_HI 0x00000002 +#define CYVAL_CSD_RANGE_IDAC_MED2 0x00000003 +#define CYFLD_CSD_LEG1_EN__OFFSET 0x00000018 +#define CYFLD_CSD_LEG1_EN__SIZE 0x00000001 +#define CYFLD_CSD_LEG2_EN__OFFSET 0x00000019 +#define CYFLD_CSD_LEG2_EN__SIZE 0x00000001 +#define CYREG_CSD_IDACB 0x402901c4 +#define CYFLD_CSD_LEG3_EN__OFFSET 0x0000001a +#define CYFLD_CSD_LEG3_EN__SIZE 0x00000001 +#define CYREG_CSD_SW_RES 0x402901f0 +#define CYFLD_CSD_RES_HCAV__OFFSET 0x00000000 +#define CYFLD_CSD_RES_HCAV__SIZE 0x00000002 +#define CYVAL_CSD_RES_HCAV_LOW 0x00000000 +#define CYVAL_CSD_RES_HCAV_MED 0x00000001 +#define CYVAL_CSD_RES_HCAV_HIGH 0x00000002 +#define CYVAL_CSD_RES_HCAV_LOWEMI 0x00000003 +#define CYFLD_CSD_RES_HCAG__OFFSET 0x00000002 +#define CYFLD_CSD_RES_HCAG__SIZE 0x00000002 +#define CYFLD_CSD_RES_HCBV__OFFSET 0x00000004 +#define CYFLD_CSD_RES_HCBV__SIZE 0x00000002 +#define CYFLD_CSD_RES_HCBG__OFFSET 0x00000006 +#define CYFLD_CSD_RES_HCBG__SIZE 0x00000002 +#define CYFLD_CSD_RES_F1PM__OFFSET 0x00000010 +#define CYFLD_CSD_RES_F1PM__SIZE 0x00000002 +#define CYVAL_CSD_RES_F1PM_LOW 0x00000000 +#define CYVAL_CSD_RES_F1PM_MED 0x00000001 +#define CYVAL_CSD_RES_F1PM_HIGH 0x00000002 +#define CYVAL_CSD_RES_F1PM_RESERVED 0x00000003 +#define CYFLD_CSD_RES_F2PT__OFFSET 0x00000012 +#define CYFLD_CSD_RES_F2PT__SIZE 0x00000002 +#define CYREG_CSD_SENSE_PERIOD 0x40290200 +#define CYFLD_CSD_SENSE_DIV__OFFSET 0x00000000 +#define CYFLD_CSD_SENSE_DIV__SIZE 0x0000000c +#define CYFLD_CSD_LFSR_SIZE__OFFSET 0x00000010 +#define CYFLD_CSD_LFSR_SIZE__SIZE 0x00000003 +#define CYVAL_CSD_LFSR_SIZE_OFF 0x00000000 +#define CYVAL_CSD_LFSR_SIZE_6B 0x00000001 +#define CYVAL_CSD_LFSR_SIZE_7B 0x00000002 +#define CYVAL_CSD_LFSR_SIZE_9B 0x00000003 +#define CYVAL_CSD_LFSR_SIZE_10B 0x00000004 +#define CYVAL_CSD_LFSR_SIZE_8B 0x00000005 +#define CYVAL_CSD_LFSR_SIZE_12B 0x00000006 +#define CYFLD_CSD_LFSR_SCALE__OFFSET 0x00000014 +#define CYFLD_CSD_LFSR_SCALE__SIZE 0x00000004 +#define CYFLD_CSD_LFSR_CLEAR__OFFSET 0x00000018 +#define CYFLD_CSD_LFSR_CLEAR__SIZE 0x00000001 +#define CYFLD_CSD_SEL_LFSR_MSB__OFFSET 0x00000019 +#define CYFLD_CSD_SEL_LFSR_MSB__SIZE 0x00000001 +#define CYFLD_CSD_LFSR_BITS__OFFSET 0x0000001a +#define CYFLD_CSD_LFSR_BITS__SIZE 0x00000002 +#define CYVAL_CSD_LFSR_BITS_2B 0x00000000 +#define CYVAL_CSD_LFSR_BITS_3B 0x00000001 +#define CYVAL_CSD_LFSR_BITS_4B 0x00000002 +#define CYVAL_CSD_LFSR_BITS_5B 0x00000003 +#define CYREG_CSD_SENSE_DUTY 0x40290204 +#define CYFLD_CSD_SENSE_WIDTH__OFFSET 0x00000000 +#define CYFLD_CSD_SENSE_WIDTH__SIZE 0x0000000c +#define CYFLD_CSD_SENSE_POL__OFFSET 0x00000010 +#define CYFLD_CSD_SENSE_POL__SIZE 0x00000001 +#define CYFLD_CSD_OVERLAP_PHI1__OFFSET 0x00000012 +#define CYFLD_CSD_OVERLAP_PHI1__SIZE 0x00000001 +#define CYFLD_CSD_OVERLAP_PHI2__OFFSET 0x00000013 +#define CYFLD_CSD_OVERLAP_PHI2__SIZE 0x00000001 +#define CYREG_CSD_SW_HS_P_SEL 0x40290280 +#define CYFLD_CSD_SW_HMPM__OFFSET 0x00000000 +#define CYFLD_CSD_SW_HMPM__SIZE 0x00000001 +#define CYFLD_CSD_SW_HMPT__OFFSET 0x00000004 +#define CYFLD_CSD_SW_HMPT__SIZE 0x00000001 +#define CYFLD_CSD_SW_HMPS__OFFSET 0x00000008 +#define CYFLD_CSD_SW_HMPS__SIZE 0x00000001 +#define CYFLD_CSD_SW_HMMA__OFFSET 0x0000000c +#define CYFLD_CSD_SW_HMMA__SIZE 0x00000001 +#define CYFLD_CSD_SW_HMMB__OFFSET 0x00000010 +#define CYFLD_CSD_SW_HMMB__SIZE 0x00000001 +#define CYFLD_CSD_SW_HMCA__OFFSET 0x00000014 +#define CYFLD_CSD_SW_HMCA__SIZE 0x00000001 +#define CYFLD_CSD_SW_HMCB__OFFSET 0x00000018 +#define CYFLD_CSD_SW_HMCB__SIZE 0x00000001 +#define CYFLD_CSD_SW_HMRH__OFFSET 0x0000001c +#define CYFLD_CSD_SW_HMRH__SIZE 0x00000001 +#define CYREG_CSD_SW_HS_N_SEL 0x40290284 +#define CYFLD_CSD_SW_HCCC__OFFSET 0x00000010 +#define CYFLD_CSD_SW_HCCC__SIZE 0x00000001 +#define CYFLD_CSD_SW_HCCD__OFFSET 0x00000014 +#define CYFLD_CSD_SW_HCCD__SIZE 0x00000001 +#define CYFLD_CSD_SW_HCRH__OFFSET 0x00000018 +#define CYFLD_CSD_SW_HCRH__SIZE 0x00000003 +#define CYFLD_CSD_SW_HCRL__OFFSET 0x0000001c +#define CYFLD_CSD_SW_HCRL__SIZE 0x00000003 +#define CYREG_CSD_SW_SHIELD_SEL 0x40290288 +#define CYFLD_CSD_SW_HCAV__OFFSET 0x00000000 +#define CYFLD_CSD_SW_HCAV__SIZE 0x00000003 +#define CYFLD_CSD_SW_HCAG__OFFSET 0x00000004 +#define CYFLD_CSD_SW_HCAG__SIZE 0x00000003 +#define CYFLD_CSD_SW_HCBV__OFFSET 0x00000008 +#define CYFLD_CSD_SW_HCBV__SIZE 0x00000003 +#define CYFLD_CSD_SW_HCBG__OFFSET 0x0000000c +#define CYFLD_CSD_SW_HCBG__SIZE 0x00000003 +#define CYFLD_CSD_SW_HCCV__OFFSET 0x00000010 +#define CYFLD_CSD_SW_HCCV__SIZE 0x00000001 +#define CYFLD_CSD_SW_HCCG__OFFSET 0x00000014 +#define CYFLD_CSD_SW_HCCG__SIZE 0x00000001 +#define CYREG_CSD_SW_HS_P_SEL1 0x4029028c +#define CYFLD_CSD_SW_HMRE__OFFSET 0x00000000 +#define CYFLD_CSD_SW_HMRE__SIZE 0x00000001 +#define CYREG_CSD_SW_AMUXBUF_SEL 0x40290290 +#define CYFLD_CSD_SW_IRBY__OFFSET 0x00000004 +#define CYFLD_CSD_SW_IRBY__SIZE 0x00000001 +#define CYFLD_CSD_SW_IRLB__OFFSET 0x00000008 +#define CYFLD_CSD_SW_IRLB__SIZE 0x00000001 +#define CYFLD_CSD_SW_ICA__OFFSET 0x0000000c +#define CYFLD_CSD_SW_ICA__SIZE 0x00000001 +#define CYFLD_CSD_SW_ICB__OFFSET 0x00000010 +#define CYFLD_CSD_SW_ICB__SIZE 0x00000003 +#define CYFLD_CSD_SW_IRLI__OFFSET 0x00000014 +#define CYFLD_CSD_SW_IRLI__SIZE 0x00000001 +#define CYFLD_CSD_SW_IRH__OFFSET 0x00000018 +#define CYFLD_CSD_SW_IRH__SIZE 0x00000001 +#define CYFLD_CSD_SW_IRL__OFFSET 0x0000001c +#define CYFLD_CSD_SW_IRL__SIZE 0x00000001 +#define CYREG_CSD_SW_BYP_SEL 0x40290294 +#define CYFLD_CSD_SW_BYA__OFFSET 0x0000000c +#define CYFLD_CSD_SW_BYA__SIZE 0x00000001 +#define CYFLD_CSD_SW_BYB__OFFSET 0x00000010 +#define CYFLD_CSD_SW_BYB__SIZE 0x00000001 +#define CYFLD_CSD_SW_CBCC__OFFSET 0x00000014 +#define CYFLD_CSD_SW_CBCC__SIZE 0x00000001 +#define CYREG_CSD_SW_CMP_P_SEL 0x402902a0 +#define CYFLD_CSD_SW_SFPM__OFFSET 0x00000000 +#define CYFLD_CSD_SW_SFPM__SIZE 0x00000003 +#define CYFLD_CSD_SW_SFPT__OFFSET 0x00000004 +#define CYFLD_CSD_SW_SFPT__SIZE 0x00000003 +#define CYFLD_CSD_SW_SFPS__OFFSET 0x00000008 +#define CYFLD_CSD_SW_SFPS__SIZE 0x00000003 +#define CYFLD_CSD_SW_SFMA__OFFSET 0x0000000c +#define CYFLD_CSD_SW_SFMA__SIZE 0x00000001 +#define CYFLD_CSD_SW_SFMB__OFFSET 0x00000010 +#define CYFLD_CSD_SW_SFMB__SIZE 0x00000001 +#define CYFLD_CSD_SW_SFCA__OFFSET 0x00000014 +#define CYFLD_CSD_SW_SFCA__SIZE 0x00000001 +#define CYFLD_CSD_SW_SFCB__OFFSET 0x00000018 +#define CYFLD_CSD_SW_SFCB__SIZE 0x00000001 +#define CYREG_CSD_SW_CMP_N_SEL 0x402902a4 +#define CYFLD_CSD_SW_SCRH__OFFSET 0x00000018 +#define CYFLD_CSD_SW_SCRH__SIZE 0x00000003 +#define CYFLD_CSD_SW_SCRL__OFFSET 0x0000001c +#define CYFLD_CSD_SW_SCRL__SIZE 0x00000003 +#define CYREG_CSD_SW_REFGEN_SEL 0x402902a8 +#define CYFLD_CSD_SW_IAIB__OFFSET 0x00000000 +#define CYFLD_CSD_SW_IAIB__SIZE 0x00000001 +#define CYFLD_CSD_SW_IBCB__OFFSET 0x00000004 +#define CYFLD_CSD_SW_IBCB__SIZE 0x00000001 +#define CYFLD_CSD_SW_SGMB__OFFSET 0x00000010 +#define CYFLD_CSD_SW_SGMB__SIZE 0x00000001 +#define CYFLD_CSD_SW_SGRE__OFFSET 0x00000018 +#define CYFLD_CSD_SW_SGRE__SIZE 0x00000001 +#define CYFLD_CSD_SW_SGR__OFFSET 0x0000001c +#define CYFLD_CSD_SW_SGR__SIZE 0x00000001 +#define CYREG_CSD_SW_FW_MOD_SEL 0x402902b0 +#define CYFLD_CSD_SW_F1PM__OFFSET 0x00000000 +#define CYFLD_CSD_SW_F1PM__SIZE 0x00000001 +#define CYFLD_CSD_SW_F1MA__OFFSET 0x00000008 +#define CYFLD_CSD_SW_F1MA__SIZE 0x00000003 +#define CYFLD_CSD_SW_F1CA__OFFSET 0x00000010 +#define CYFLD_CSD_SW_F1CA__SIZE 0x00000003 +#define CYFLD_CSD_SW_C1CC__OFFSET 0x00000014 +#define CYFLD_CSD_SW_C1CC__SIZE 0x00000001 +#define CYFLD_CSD_SW_C1CD__OFFSET 0x00000018 +#define CYFLD_CSD_SW_C1CD__SIZE 0x00000001 +#define CYFLD_CSD_SW_C1F1__OFFSET 0x0000001c +#define CYFLD_CSD_SW_C1F1__SIZE 0x00000001 +#define CYREG_CSD_SW_FW_TANK_SEL 0x402902b4 +#define CYFLD_CSD_SW_F2PT__OFFSET 0x00000004 +#define CYFLD_CSD_SW_F2PT__SIZE 0x00000001 +#define CYFLD_CSD_SW_F2MA__OFFSET 0x00000008 +#define CYFLD_CSD_SW_F2MA__SIZE 0x00000003 +#define CYFLD_CSD_SW_F2CA__OFFSET 0x0000000c +#define CYFLD_CSD_SW_F2CA__SIZE 0x00000003 +#define CYFLD_CSD_SW_F2CB__OFFSET 0x00000010 +#define CYFLD_CSD_SW_F2CB__SIZE 0x00000003 +#define CYFLD_CSD_SW_C2CC__OFFSET 0x00000014 +#define CYFLD_CSD_SW_C2CC__SIZE 0x00000001 +#define CYFLD_CSD_SW_C2CD__OFFSET 0x00000018 +#define CYFLD_CSD_SW_C2CD__SIZE 0x00000001 +#define CYFLD_CSD_SW_C2F2__OFFSET 0x0000001c +#define CYFLD_CSD_SW_C2F2__SIZE 0x00000001 +#define CYREG_CSD_SW_DSI_SEL 0x402902c0 +#define CYFLD_CSD_DSI_CSH_TANK__OFFSET 0x00000000 +#define CYFLD_CSD_DSI_CSH_TANK__SIZE 0x00000003 +#define CYFLD_CSD_DSI_CMOD__OFFSET 0x00000004 +#define CYFLD_CSD_DSI_CMOD__SIZE 0x00000003 +#define CYREG_CSD_SEQ_TIME 0x40290300 +#define CYFLD_CSD_AZ_TIME__OFFSET 0x00000000 +#define CYFLD_CSD_AZ_TIME__SIZE 0x00000008 +#define CYREG_CSD_SEQ_INIT_CNT 0x40290310 +#define CYFLD_CSD_CONV_CNT__OFFSET 0x00000000 +#define CYFLD_CSD_CONV_CNT__SIZE 0x00000010 +#define CYREG_CSD_SEQ_NORM_CNT 0x40290314 +#define CYREG_CSD_ADC_CTL 0x40290320 +#define CYFLD_CSD_ADC_TIME__OFFSET 0x00000000 +#define CYFLD_CSD_ADC_TIME__SIZE 0x00000008 +#define CYFLD_CSD_ADC_MODE__OFFSET 0x00000010 +#define CYFLD_CSD_ADC_MODE__SIZE 0x00000002 +#define CYVAL_CSD_ADC_MODE_OFF 0x00000000 +#define CYVAL_CSD_ADC_MODE_VREF_CNT 0x00000001 +#define CYVAL_CSD_ADC_MODE_VREF_BY2_CNT 0x00000002 +#define CYVAL_CSD_ADC_MODE_VIN_CNT 0x00000003 +#define CYREG_CSD_SEQ_START 0x40290340 +#define CYFLD_CSD_START__OFFSET 0x00000000 +#define CYFLD_CSD_START__SIZE 0x00000001 +#define CYFLD_CSD_SEQ_MODE__OFFSET 0x00000001 +#define CYFLD_CSD_SEQ_MODE__SIZE 0x00000001 +#define CYFLD_CSD_ABORT__OFFSET 0x00000003 +#define CYFLD_CSD_ABORT__SIZE 0x00000001 +#define CYFLD_CSD_DSI_START_EN__OFFSET 0x00000004 +#define CYFLD_CSD_DSI_START_EN__SIZE 0x00000001 +#define CYFLD_CSD_AZ0_SKIP__OFFSET 0x00000008 +#define CYFLD_CSD_AZ0_SKIP__SIZE 0x00000001 +#define CYFLD_CSD_AZ1_SKIP__OFFSET 0x00000009 +#define CYFLD_CSD_AZ1_SKIP__SIZE 0x00000001 +#define CYDEV_LCD_BASE 0x402a0000 +#define CYDEV_LCD_SIZE 0x00010000 +#define CYREG_LCD_ID 0x402a0000 +#define CYFLD_LCD_ID__OFFSET 0x00000000 +#define CYFLD_LCD_ID__SIZE 0x00000010 +#define CYFLD_LCD_REVISION__OFFSET 0x00000010 +#define CYFLD_LCD_REVISION__SIZE 0x00000010 +#define CYREG_LCD_DIVIDER 0x402a0004 +#define CYFLD_LCD_SUBFR_DIV__OFFSET 0x00000000 +#define CYFLD_LCD_SUBFR_DIV__SIZE 0x00000010 +#define CYFLD_LCD_DEAD_DIV__OFFSET 0x00000010 +#define CYFLD_LCD_DEAD_DIV__SIZE 0x00000010 +#define CYREG_LCD_CONTROL 0x402a0008 +#define CYFLD_LCD_LS_EN__OFFSET 0x00000000 +#define CYFLD_LCD_LS_EN__SIZE 0x00000001 +#define CYFLD_LCD_HS_EN__OFFSET 0x00000001 +#define CYFLD_LCD_HS_EN__SIZE 0x00000001 +#define CYFLD_LCD_LCD_MODE__OFFSET 0x00000002 +#define CYFLD_LCD_LCD_MODE__SIZE 0x00000001 +#define CYVAL_LCD_LCD_MODE_LS 0x00000000 +#define CYVAL_LCD_LCD_MODE_HS 0x00000001 +#define CYFLD_LCD_TYPE__OFFSET 0x00000003 +#define CYFLD_LCD_TYPE__SIZE 0x00000001 +#define CYVAL_LCD_TYPE_TYPE_A 0x00000000 +#define CYVAL_LCD_TYPE_TYPE_B 0x00000001 +#define CYFLD_LCD_OP_MODE__OFFSET 0x00000004 +#define CYFLD_LCD_OP_MODE__SIZE 0x00000001 +#define CYVAL_LCD_OP_MODE_PWM 0x00000000 +#define CYVAL_LCD_OP_MODE_CORRELATION 0x00000001 +#define CYFLD_LCD_BIAS__OFFSET 0x00000005 +#define CYFLD_LCD_BIAS__SIZE 0x00000002 +#define CYVAL_LCD_BIAS_HALF 0x00000000 +#define CYVAL_LCD_BIAS_THIRD 0x00000001 +#define CYVAL_LCD_BIAS_FOURTH 0x00000002 +#define CYVAL_LCD_BIAS_FIFTH 0x00000003 +#define CYFLD_LCD_COM_NUM__OFFSET 0x00000008 +#define CYFLD_LCD_COM_NUM__SIZE 0x00000004 +#define CYFLD_LCD_LS_EN_STAT__OFFSET 0x0000001f +#define CYFLD_LCD_LS_EN_STAT__SIZE 0x00000001 +#define CYREG_LCD_DATA00 0x402a0100 +#define CYFLD_LCD_DATA__OFFSET 0x00000000 +#define CYFLD_LCD_DATA__SIZE 0x00000020 +#define CYREG_LCD_DATA01 0x402a0104 +#define CYREG_LCD_DATA02 0x402a0108 +#define CYREG_LCD_DATA03 0x402a010c +#define CYREG_LCD_DATA04 0x402a0110 +#define CYREG_LCD_DATA05 0x402a0114 +#define CYREG_LCD_DATA06 0x402a0118 +#define CYREG_LCD_DATA07 0x402a011c +#define CYREG_LCD_DATA10 0x402a0200 +#define CYREG_LCD_DATA11 0x402a0204 +#define CYREG_LCD_DATA12 0x402a0208 +#define CYREG_LCD_DATA13 0x402a020c +#define CYREG_LCD_DATA14 0x402a0210 +#define CYREG_LCD_DATA15 0x402a0214 +#define CYREG_LCD_DATA16 0x402a0218 +#define CYREG_LCD_DATA17 0x402a021c +#define CYDEV_LPCOMP_BASE 0x402b0000 +#define CYDEV_LPCOMP_SIZE 0x00010000 +#define CYREG_LPCOMP_ID 0x402b0000 +#define CYFLD_LPCOMP_ID__OFFSET 0x00000000 +#define CYFLD_LPCOMP_ID__SIZE 0x00000010 +#define CYFLD_LPCOMP_REVISION__OFFSET 0x00000010 +#define CYFLD_LPCOMP_REVISION__SIZE 0x00000010 +#define CYREG_LPCOMP_CONFIG 0x402b0004 +#define CYFLD_LPCOMP_MODE1__OFFSET 0x00000000 +#define CYFLD_LPCOMP_MODE1__SIZE 0x00000002 +#define CYVAL_LPCOMP_MODE1_SLOW 0x00000000 +#define CYVAL_LPCOMP_MODE1_FAST 0x00000001 +#define CYVAL_LPCOMP_MODE1_ULP 0x00000002 +#define CYFLD_LPCOMP_HYST1__OFFSET 0x00000002 +#define CYFLD_LPCOMP_HYST1__SIZE 0x00000001 +#define CYFLD_LPCOMP_FILTER1__OFFSET 0x00000003 +#define CYFLD_LPCOMP_FILTER1__SIZE 0x00000001 +#define CYFLD_LPCOMP_INTTYPE1__OFFSET 0x00000004 +#define CYFLD_LPCOMP_INTTYPE1__SIZE 0x00000002 +#define CYVAL_LPCOMP_INTTYPE1_DISABLE 0x00000000 +#define CYVAL_LPCOMP_INTTYPE1_RISING 0x00000001 +#define CYVAL_LPCOMP_INTTYPE1_FALLING 0x00000002 +#define CYVAL_LPCOMP_INTTYPE1_BOTH 0x00000003 +#define CYFLD_LPCOMP_OUT1__OFFSET 0x00000006 +#define CYFLD_LPCOMP_OUT1__SIZE 0x00000001 +#define CYFLD_LPCOMP_ENABLE1__OFFSET 0x00000007 +#define CYFLD_LPCOMP_ENABLE1__SIZE 0x00000001 +#define CYFLD_LPCOMP_MODE2__OFFSET 0x00000008 +#define CYFLD_LPCOMP_MODE2__SIZE 0x00000002 +#define CYVAL_LPCOMP_MODE2_SLOW 0x00000000 +#define CYVAL_LPCOMP_MODE2_FAST 0x00000001 +#define CYVAL_LPCOMP_MODE2_ULP 0x00000002 +#define CYFLD_LPCOMP_HYST2__OFFSET 0x0000000a +#define CYFLD_LPCOMP_HYST2__SIZE 0x00000001 +#define CYFLD_LPCOMP_FILTER2__OFFSET 0x0000000b +#define CYFLD_LPCOMP_FILTER2__SIZE 0x00000001 +#define CYFLD_LPCOMP_INTTYPE2__OFFSET 0x0000000c +#define CYFLD_LPCOMP_INTTYPE2__SIZE 0x00000002 +#define CYVAL_LPCOMP_INTTYPE2_DISABLE 0x00000000 +#define CYVAL_LPCOMP_INTTYPE2_RISING 0x00000001 +#define CYVAL_LPCOMP_INTTYPE2_FALLING 0x00000002 +#define CYVAL_LPCOMP_INTTYPE2_BOTH 0x00000003 +#define CYFLD_LPCOMP_OUT2__OFFSET 0x0000000e +#define CYFLD_LPCOMP_OUT2__SIZE 0x00000001 +#define CYFLD_LPCOMP_ENABLE2__OFFSET 0x0000000f +#define CYFLD_LPCOMP_ENABLE2__SIZE 0x00000001 +#define CYFLD_LPCOMP_DSI_BYPASS1__OFFSET 0x00000010 +#define CYFLD_LPCOMP_DSI_BYPASS1__SIZE 0x00000001 +#define CYFLD_LPCOMP_DSI_LEVEL1__OFFSET 0x00000011 +#define CYFLD_LPCOMP_DSI_LEVEL1__SIZE 0x00000001 +#define CYFLD_LPCOMP_DSI_BYPASS2__OFFSET 0x00000014 +#define CYFLD_LPCOMP_DSI_BYPASS2__SIZE 0x00000001 +#define CYFLD_LPCOMP_DSI_LEVEL2__OFFSET 0x00000015 +#define CYFLD_LPCOMP_DSI_LEVEL2__SIZE 0x00000001 +#define CYREG_LPCOMP_DFT 0x402b0008 +#define CYFLD_LPCOMP_CAL_EN__OFFSET 0x00000000 +#define CYFLD_LPCOMP_CAL_EN__SIZE 0x00000001 +#define CYFLD_LPCOMP_BYPASS__OFFSET 0x00000001 +#define CYFLD_LPCOMP_BYPASS__SIZE 0x00000001 +#define CYREG_LPCOMP_INTR 0x402b0010 +#define CYFLD_LPCOMP_COMP1__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP1__SIZE 0x00000001 +#define CYFLD_LPCOMP_COMP2__OFFSET 0x00000001 +#define CYFLD_LPCOMP_COMP2__SIZE 0x00000001 +#define CYREG_LPCOMP_INTR_SET 0x402b0014 +#define CYREG_LPCOMP_INTR_MASK 0x402b0018 +#define CYFLD_LPCOMP_COMP1_MASK__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP1_MASK__SIZE 0x00000001 +#define CYFLD_LPCOMP_COMP2_MASK__OFFSET 0x00000001 +#define CYFLD_LPCOMP_COMP2_MASK__SIZE 0x00000001 +#define CYREG_LPCOMP_INTR_MASKED 0x402b001c +#define CYFLD_LPCOMP_COMP1_MASKED__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP1_MASKED__SIZE 0x00000001 +#define CYFLD_LPCOMP_COMP2_MASKED__OFFSET 0x00000001 +#define CYFLD_LPCOMP_COMP2_MASKED__SIZE 0x00000001 +#define CYREG_LPCOMP_TRIM1 0x402bff00 +#define CYFLD_LPCOMP_COMP1_TRIMA__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP1_TRIMA__SIZE 0x00000005 +#define CYREG_LPCOMP_TRIM2 0x402bff04 +#define CYFLD_LPCOMP_COMP1_TRIMB__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP1_TRIMB__SIZE 0x00000005 +#define CYREG_LPCOMP_TRIM3 0x402bff08 +#define CYFLD_LPCOMP_COMP2_TRIMA__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP2_TRIMA__SIZE 0x00000005 +#define CYREG_LPCOMP_TRIM4 0x402bff0c +#define CYFLD_LPCOMP_COMP2_TRIMB__OFFSET 0x00000000 +#define CYFLD_LPCOMP_COMP2_TRIMB__SIZE 0x00000005 +#define CYDEV_CRYPTO_BASE 0x402c0000 +#define CYDEV_CRYPTO_SIZE 0x00010000 +#define CYREG_CRYPTO_CTL 0x402c0000 +#define CYFLD_CRYPTO_OPCODE__OFFSET 0x00000000 +#define CYFLD_CRYPTO_OPCODE__SIZE 0x00000005 +#define CYVAL_CRYPTO_OPCODE_AES_FORWARD 0x00000000 +#define CYVAL_CRYPTO_OPCODE_AES_INVERSE 0x00000001 +#define CYVAL_CRYPTO_OPCODE_SHA 0x00000010 +#define CYVAL_CRYPTO_OPCODE_CRC 0x00000018 +#define CYFLD_CRYPTO_ENABLED__OFFSET 0x0000001f +#define CYFLD_CRYPTO_ENABLED__SIZE 0x00000001 +#define CYREG_CRYPTO_STATUS 0x402c0004 +#define CYFLD_CRYPTO_BUSY__OFFSET 0x00000000 +#define CYFLD_CRYPTO_BUSY__SIZE 0x00000001 +#define CYREG_CRYPTO_CMD 0x402c0008 +#define CYFLD_CRYPTO_START__OFFSET 0x00000000 +#define CYFLD_CRYPTO_START__SIZE 0x00000001 +#define CYREG_CRYPTO_TR_CTL0 0x402c0280 +#define CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__OFFSET 0x00000000 +#define CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__SIZE 0x00000008 +#define CYFLD_CRYPTO_RED_CLOCK_DIV__OFFSET 0x00000008 +#define CYFLD_CRYPTO_RED_CLOCK_DIV__SIZE 0x00000008 +#define CYFLD_CRYPTO_INIT_DELAY__OFFSET 0x00000010 +#define CYFLD_CRYPTO_INIT_DELAY__SIZE 0x00000008 +#define CYFLD_CRYPTO_VON_NEUMANN_CORR__OFFSET 0x00000018 +#define CYFLD_CRYPTO_VON_NEUMANN_CORR__SIZE 0x00000001 +#define CYFLD_CRYPTO_STOP_ON_AP_DETECT__OFFSET 0x0000001c +#define CYFLD_CRYPTO_STOP_ON_AP_DETECT__SIZE 0x00000001 +#define CYFLD_CRYPTO_STOP_ON_RC_DETECT__OFFSET 0x0000001d +#define CYFLD_CRYPTO_STOP_ON_RC_DETECT__SIZE 0x00000001 +#define CYREG_CRYPTO_TR_CTL1 0x402c0284 +#define CYFLD_CRYPTO_DATA_BIT_SIZE__OFFSET 0x00000000 +#define CYFLD_CRYPTO_DATA_BIT_SIZE__SIZE 0x00000006 +#define CYREG_CRYPTO_TR_RESULT0 0x402c0288 +#define CYFLD_CRYPTO_DATA32__OFFSET 0x00000000 +#define CYFLD_CRYPTO_DATA32__SIZE 0x00000020 +#define CYREG_CRYPTO_TR_RESULT1 0x402c028c +#define CYREG_CRYPTO_TR_CMD 0x402c0290 +#define CYFLD_CRYPTO_START_RO11__OFFSET 0x00000000 +#define CYFLD_CRYPTO_START_RO11__SIZE 0x00000001 +#define CYFLD_CRYPTO_START_RO15__OFFSET 0x00000001 +#define CYFLD_CRYPTO_START_RO15__SIZE 0x00000001 +#define CYFLD_CRYPTO_START_GARO15__OFFSET 0x00000002 +#define CYFLD_CRYPTO_START_GARO15__SIZE 0x00000001 +#define CYFLD_CRYPTO_START_GARO31__OFFSET 0x00000003 +#define CYFLD_CRYPTO_START_GARO31__SIZE 0x00000001 +#define CYFLD_CRYPTO_START_FIRO15__OFFSET 0x00000004 +#define CYFLD_CRYPTO_START_FIRO15__SIZE 0x00000001 +#define CYFLD_CRYPTO_START_FIRO31__OFFSET 0x00000005 +#define CYFLD_CRYPTO_START_FIRO31__SIZE 0x00000001 +#define CYREG_CRYPTO_TR_GARO_CTL 0x402c02a0 +#define CYFLD_CRYPTO_POLYNOMIAL31__OFFSET 0x00000000 +#define CYFLD_CRYPTO_POLYNOMIAL31__SIZE 0x0000001f +#define CYREG_CRYPTO_TR_FIRO_CTL 0x402c02a4 +#define CYREG_CRYPTO_TR_MON_CTL 0x402c02c0 +#define CYFLD_CRYPTO_BITSTREAM_SEL__OFFSET 0x00000000 +#define CYFLD_CRYPTO_BITSTREAM_SEL__SIZE 0x00000002 +#define CYREG_CRYPTO_TR_MON_CMD 0x402c02c8 +#define CYFLD_CRYPTO_START_AP__OFFSET 0x00000000 +#define CYFLD_CRYPTO_START_AP__SIZE 0x00000001 +#define CYFLD_CRYPTO_START_RC__OFFSET 0x00000001 +#define CYFLD_CRYPTO_START_RC__SIZE 0x00000001 +#define CYREG_CRYPTO_TR_MON_RC_CTL 0x402c02d0 +#define CYFLD_CRYPTO_CUTOFF_COUNT8__OFFSET 0x00000000 +#define CYFLD_CRYPTO_CUTOFF_COUNT8__SIZE 0x00000008 +#define CYREG_CRYPTO_TR_MON_RC_STATUS0 0x402c02d8 +#define CYFLD_CRYPTO_BIT__OFFSET 0x00000000 +#define CYFLD_CRYPTO_BIT__SIZE 0x00000001 +#define CYREG_CRYPTO_TR_MON_RC_STATUS1 0x402c02dc +#define CYFLD_CRYPTO_REP_COUNT__OFFSET 0x00000000 +#define CYFLD_CRYPTO_REP_COUNT__SIZE 0x00000008 +#define CYREG_CRYPTO_TR_MON_AP_CTL 0x402c02e0 +#define CYFLD_CRYPTO_CUTOFF_COUNT16__OFFSET 0x00000000 +#define CYFLD_CRYPTO_CUTOFF_COUNT16__SIZE 0x00000010 +#define CYFLD_CRYPTO_WINDOW_SIZE__OFFSET 0x00000010 +#define CYFLD_CRYPTO_WINDOW_SIZE__SIZE 0x00000010 +#define CYREG_CRYPTO_TR_MON_AP_STATUS0 0x402c02e8 +#define CYREG_CRYPTO_TR_MON_AP_STATUS1 0x402c02ec +#define CYFLD_CRYPTO_OCC_COUNT__OFFSET 0x00000000 +#define CYFLD_CRYPTO_OCC_COUNT__SIZE 0x00000010 +#define CYFLD_CRYPTO_WINDOW_INDEX__OFFSET 0x00000010 +#define CYFLD_CRYPTO_WINDOW_INDEX__SIZE 0x00000010 +#define CYREG_CRYPTO_INTR 0x402c07c0 +#define CYFLD_CRYPTO_DONE__OFFSET 0x00000000 +#define CYFLD_CRYPTO_DONE__SIZE 0x00000001 +#define CYFLD_CRYPTO_ACCESS_ERROR__OFFSET 0x00000001 +#define CYFLD_CRYPTO_ACCESS_ERROR__SIZE 0x00000001 +#define CYFLD_CRYPTO_TR_INITIALIZED__OFFSET 0x00000006 +#define CYFLD_CRYPTO_TR_INITIALIZED__SIZE 0x00000001 +#define CYFLD_CRYPTO_TR_DATA_AVAILABLE__OFFSET 0x00000007 +#define CYFLD_CRYPTO_TR_DATA_AVAILABLE__SIZE 0x00000001 +#define CYFLD_CRYPTO_TR_AP_DETECT__OFFSET 0x00000008 +#define CYFLD_CRYPTO_TR_AP_DETECT__SIZE 0x00000001 +#define CYFLD_CRYPTO_TR_RC_DETECT__OFFSET 0x00000009 +#define CYFLD_CRYPTO_TR_RC_DETECT__SIZE 0x00000001 +#define CYREG_CRYPTO_INTR_SET 0x402c07c4 +#define CYREG_CRYPTO_INTR_MASK 0x402c07c8 +#define CYREG_CRYPTO_INTR_MASKED 0x402c07cc +#define CYREG_CRYPTO_MEM_BUFF0 0x402c0800 +#define CYREG_CRYPTO_MEM_BUFF1 0x402c0804 +#define CYREG_CRYPTO_MEM_BUFF2 0x402c0808 +#define CYREG_CRYPTO_MEM_BUFF3 0x402c080c +#define CYREG_CRYPTO_MEM_BUFF4 0x402c0810 +#define CYREG_CRYPTO_MEM_BUFF5 0x402c0814 +#define CYREG_CRYPTO_MEM_BUFF6 0x402c0818 +#define CYREG_CRYPTO_MEM_BUFF7 0x402c081c +#define CYREG_CRYPTO_MEM_BUFF8 0x402c0820 +#define CYREG_CRYPTO_MEM_BUFF9 0x402c0824 +#define CYREG_CRYPTO_MEM_BUFF10 0x402c0828 +#define CYREG_CRYPTO_MEM_BUFF11 0x402c082c +#define CYREG_CRYPTO_MEM_BUFF12 0x402c0830 +#define CYREG_CRYPTO_MEM_BUFF13 0x402c0834 +#define CYREG_CRYPTO_MEM_BUFF14 0x402c0838 +#define CYREG_CRYPTO_MEM_BUFF15 0x402c083c +#define CYREG_CRYPTO_MEM_BUFF16 0x402c0840 +#define CYREG_CRYPTO_MEM_BUFF17 0x402c0844 +#define CYREG_CRYPTO_MEM_BUFF18 0x402c0848 +#define CYREG_CRYPTO_MEM_BUFF19 0x402c084c +#define CYREG_CRYPTO_MEM_BUFF20 0x402c0850 +#define CYREG_CRYPTO_MEM_BUFF21 0x402c0854 +#define CYREG_CRYPTO_MEM_BUFF22 0x402c0858 +#define CYREG_CRYPTO_MEM_BUFF23 0x402c085c +#define CYREG_CRYPTO_MEM_BUFF24 0x402c0860 +#define CYREG_CRYPTO_MEM_BUFF25 0x402c0864 +#define CYREG_CRYPTO_MEM_BUFF26 0x402c0868 +#define CYREG_CRYPTO_MEM_BUFF27 0x402c086c +#define CYREG_CRYPTO_MEM_BUFF28 0x402c0870 +#define CYREG_CRYPTO_MEM_BUFF29 0x402c0874 +#define CYREG_CRYPTO_MEM_BUFF30 0x402c0878 +#define CYREG_CRYPTO_MEM_BUFF31 0x402c087c +#define CYREG_CRYPTO_MEM_BUFF32 0x402c0880 +#define CYREG_CRYPTO_MEM_BUFF33 0x402c0884 +#define CYREG_CRYPTO_MEM_BUFF34 0x402c0888 +#define CYREG_CRYPTO_MEM_BUFF35 0x402c088c +#define CYREG_CRYPTO_MEM_BUFF36 0x402c0890 +#define CYREG_CRYPTO_MEM_BUFF37 0x402c0894 +#define CYREG_CRYPTO_MEM_BUFF38 0x402c0898 +#define CYREG_CRYPTO_MEM_BUFF39 0x402c089c +#define CYREG_CRYPTO_MEM_BUFF40 0x402c08a0 +#define CYREG_CRYPTO_MEM_BUFF41 0x402c08a4 +#define CYREG_CRYPTO_MEM_BUFF42 0x402c08a8 +#define CYREG_CRYPTO_MEM_BUFF43 0x402c08ac +#define CYREG_CRYPTO_MEM_BUFF44 0x402c08b0 +#define CYREG_CRYPTO_MEM_BUFF45 0x402c08b4 +#define CYREG_CRYPTO_MEM_BUFF46 0x402c08b8 +#define CYREG_CRYPTO_MEM_BUFF47 0x402c08bc +#define CYREG_CRYPTO_MEM_BUFF48 0x402c08c0 +#define CYREG_CRYPTO_MEM_BUFF49 0x402c08c4 +#define CYREG_CRYPTO_MEM_BUFF50 0x402c08c8 +#define CYREG_CRYPTO_MEM_BUFF51 0x402c08cc +#define CYREG_CRYPTO_MEM_BUFF52 0x402c08d0 +#define CYREG_CRYPTO_MEM_BUFF53 0x402c08d4 +#define CYREG_CRYPTO_MEM_BUFF54 0x402c08d8 +#define CYREG_CRYPTO_MEM_BUFF55 0x402c08dc +#define CYREG_CRYPTO_MEM_BUFF56 0x402c08e0 +#define CYREG_CRYPTO_MEM_BUFF57 0x402c08e4 +#define CYREG_CRYPTO_MEM_BUFF58 0x402c08e8 +#define CYREG_CRYPTO_MEM_BUFF59 0x402c08ec +#define CYREG_CRYPTO_MEM_BUFF60 0x402c08f0 +#define CYREG_CRYPTO_MEM_BUFF61 0x402c08f4 +#define CYREG_CRYPTO_MEM_BUFF62 0x402c08f8 +#define CYREG_CRYPTO_MEM_BUFF63 0x402c08fc +#define CYREG_CRYPTO_PRIV_BUF 0x402cff00 +#define CYFLD_CRYPTO_BUF_PRIV_LIMIT__OFFSET 0x00000000 +#define CYFLD_CRYPTO_BUF_PRIV_LIMIT__SIZE 0x00000003 +#define CYDEV_CAN_BASE 0x402e0000 +#define CYDEV_CAN_SIZE 0x00010000 +#define CYREG_CAN_INT_STATUS 0x402e0000 +#define CYFLD_CAN_ARB_LOSS__OFFSET 0x00000002 +#define CYFLD_CAN_ARB_LOSS__SIZE 0x00000001 +#define CYFLD_CAN_OVR_LOAD__OFFSET 0x00000003 +#define CYFLD_CAN_OVR_LOAD__SIZE 0x00000001 +#define CYFLD_CAN_BIT_ERR__OFFSET 0x00000004 +#define CYFLD_CAN_BIT_ERR__SIZE 0x00000001 +#define CYFLD_CAN_STUFF_ERR__OFFSET 0x00000005 +#define CYFLD_CAN_STUFF_ERR__SIZE 0x00000001 +#define CYFLD_CAN_ACK_ERR__OFFSET 0x00000006 +#define CYFLD_CAN_ACK_ERR__SIZE 0x00000001 +#define CYFLD_CAN_FORM_ERR__OFFSET 0x00000007 +#define CYFLD_CAN_FORM_ERR__SIZE 0x00000001 +#define CYFLD_CAN_CRC_ERR__OFFSET 0x00000008 +#define CYFLD_CAN_CRC_ERR__SIZE 0x00000001 +#define CYFLD_CAN_BUS_OFF__OFFSET 0x00000009 +#define CYFLD_CAN_BUS_OFF__SIZE 0x00000001 +#define CYFLD_CAN_RX_MSG_LOSS__OFFSET 0x0000000a +#define CYFLD_CAN_RX_MSG_LOSS__SIZE 0x00000001 +#define CYFLD_CAN_TX_MSG__OFFSET 0x0000000b +#define CYFLD_CAN_TX_MSG__SIZE 0x00000001 +#define CYFLD_CAN_RX_MSG__OFFSET 0x0000000c +#define CYFLD_CAN_RX_MSG__SIZE 0x00000001 +#define CYFLD_CAN_RTR_MSG__OFFSET 0x0000000d +#define CYFLD_CAN_RTR_MSG__SIZE 0x00000001 +#define CYFLD_CAN_STUCK_AT_0__OFFSET 0x0000000e +#define CYFLD_CAN_STUCK_AT_0__SIZE 0x00000001 +#define CYFLD_CAN_SST_FAILURE__OFFSET 0x0000000f +#define CYFLD_CAN_SST_FAILURE__SIZE 0x00000001 +#define CYREG_CAN_INT_EBL 0x402e0004 +#define CYFLD_CAN_GLOBAL_INT_ENBL__OFFSET 0x00000000 +#define CYFLD_CAN_GLOBAL_INT_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_ARB_LOSS_ENBL__OFFSET 0x00000002 +#define CYFLD_CAN_ARB_LOSS_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_OVR_LOAD_ENBL__OFFSET 0x00000003 +#define CYFLD_CAN_OVR_LOAD_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_BIT_ERR_ENBL__OFFSET 0x00000004 +#define CYFLD_CAN_BIT_ERR_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_STUFF_ERR_ENBL__OFFSET 0x00000005 +#define CYFLD_CAN_STUFF_ERR_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_ACK_ERR_ENBL__OFFSET 0x00000006 +#define CYFLD_CAN_ACK_ERR_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_FORM_ERR_ENBL__OFFSET 0x00000007 +#define CYFLD_CAN_FORM_ERR_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_CRC_ERR_ENBL__OFFSET 0x00000008 +#define CYFLD_CAN_CRC_ERR_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_BUS_OFF_ENBL__OFFSET 0x00000009 +#define CYFLD_CAN_BUS_OFF_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_TX_MSG_ENBL__OFFSET 0x0000000b +#define CYFLD_CAN_TX_MSG_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_RX_MSG_ENBl__OFFSET 0x0000000c +#define CYFLD_CAN_RX_MSG_ENBl__SIZE 0x00000001 +#define CYFLD_CAN_RTR_MSG_ENBL__OFFSET 0x0000000d +#define CYFLD_CAN_RTR_MSG_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_STUCK_AT_0_ENBL__OFFSET 0x0000000e +#define CYFLD_CAN_STUCK_AT_0_ENBL__SIZE 0x00000001 +#define CYFLD_CAN_SST_FAILURE_ENBL__OFFSET 0x0000000f +#define CYFLD_CAN_SST_FAILURE_ENBL__SIZE 0x00000001 +#define CYREG_CAN_BUFFER_STATUS 0x402e0008 +#define CYFLD_CAN_RX0_MSG_AV__OFFSET 0x00000000 +#define CYFLD_CAN_RX0_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX1_MSG_AV__OFFSET 0x00000001 +#define CYFLD_CAN_RX1_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX2_MSG_AV__OFFSET 0x00000002 +#define CYFLD_CAN_RX2_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX3_MSG_AV__OFFSET 0x00000003 +#define CYFLD_CAN_RX3_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX4_MSG_AV__OFFSET 0x00000004 +#define CYFLD_CAN_RX4_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX5_MSG_AV__OFFSET 0x00000005 +#define CYFLD_CAN_RX5_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX6_MSG_AV__OFFSET 0x00000006 +#define CYFLD_CAN_RX6_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX7_MSG_AV__OFFSET 0x00000007 +#define CYFLD_CAN_RX7_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX8_MSG_AV__OFFSET 0x00000008 +#define CYFLD_CAN_RX8_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX9_MSG_AV__OFFSET 0x00000009 +#define CYFLD_CAN_RX9_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX10_MSG_AV__OFFSET 0x0000000a +#define CYFLD_CAN_RX10_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX11_MSG_AV__OFFSET 0x0000000b +#define CYFLD_CAN_RX11_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX12_MSG_AV__OFFSET 0x0000000c +#define CYFLD_CAN_RX12_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX13_MSG_AV__OFFSET 0x0000000d +#define CYFLD_CAN_RX13_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX14_MSG_AV__OFFSET 0x0000000e +#define CYFLD_CAN_RX14_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_RX15_MSG_AV__OFFSET 0x0000000f +#define CYFLD_CAN_RX15_MSG_AV__SIZE 0x00000001 +#define CYFLD_CAN_TX0_REQ_PEND__OFFSET 0x00000010 +#define CYFLD_CAN_TX0_REQ_PEND__SIZE 0x00000001 +#define CYFLD_CAN_TX1_REQ_PEND__OFFSET 0x00000011 +#define CYFLD_CAN_TX1_REQ_PEND__SIZE 0x00000001 +#define CYFLD_CAN_TX2_REQ_PEND__OFFSET 0x00000012 +#define CYFLD_CAN_TX2_REQ_PEND__SIZE 0x00000001 +#define CYFLD_CAN_TX3_REQ_PEND__OFFSET 0x00000013 +#define CYFLD_CAN_TX3_REQ_PEND__SIZE 0x00000001 +#define CYFLD_CAN_TX4_REQ_PEND__OFFSET 0x00000014 +#define CYFLD_CAN_TX4_REQ_PEND__SIZE 0x00000001 +#define CYFLD_CAN_TX5_REQ_PEND__OFFSET 0x00000015 +#define CYFLD_CAN_TX5_REQ_PEND__SIZE 0x00000001 +#define CYFLD_CAN_TX6_REQ_PEND__OFFSET 0x00000016 +#define CYFLD_CAN_TX6_REQ_PEND__SIZE 0x00000001 +#define CYFLD_CAN_TX7_REQ_PEND__OFFSET 0x00000017 +#define CYFLD_CAN_TX7_REQ_PEND__SIZE 0x00000001 +#define CYREG_CAN_ERROR_STATUS 0x402e000c +#define CYFLD_CAN_TX_ERR_CNT__OFFSET 0x00000000 +#define CYFLD_CAN_TX_ERR_CNT__SIZE 0x00000008 +#define CYFLD_CAN_RX_ERR_CNT__OFFSET 0x00000008 +#define CYFLD_CAN_RX_ERR_CNT__SIZE 0x00000008 +#define CYFLD_CAN_ERROR_STATE__OFFSET 0x00000010 +#define CYFLD_CAN_ERROR_STATE__SIZE 0x00000002 +#define CYFLD_CAN_TXGTE96__OFFSET 0x00000012 +#define CYFLD_CAN_TXGTE96__SIZE 0x00000001 +#define CYFLD_CAN_RXGTE96__OFFSET 0x00000013 +#define CYFLD_CAN_RXGTE96__SIZE 0x00000001 +#define CYREG_CAN_COMMAND 0x402e0010 +#define CYFLD_CAN_RUN__OFFSET 0x00000000 +#define CYFLD_CAN_RUN__SIZE 0x00000001 +#define CYFLD_CAN_LISTEN__OFFSET 0x00000001 +#define CYFLD_CAN_LISTEN__SIZE 0x00000001 +#define CYFLD_CAN_LOOPBACK_TEST__OFFSET 0x00000002 +#define CYFLD_CAN_LOOPBACK_TEST__SIZE 0x00000001 +#define CYFLD_CAN_SRAM_TEST__OFFSET 0x00000003 +#define CYFLD_CAN_SRAM_TEST__SIZE 0x00000001 +#define CYFLD_CAN_IP_REV_NUMBER__OFFSET 0x00000010 +#define CYFLD_CAN_IP_REV_NUMBER__SIZE 0x00000008 +#define CYFLD_CAN_IP_MINOR_VERSION__OFFSET 0x00000018 +#define CYFLD_CAN_IP_MINOR_VERSION__SIZE 0x00000004 +#define CYFLD_CAN_IP_MAJOR_VERSION__OFFSET 0x0000001c +#define CYFLD_CAN_IP_MAJOR_VERSION__SIZE 0x00000004 +#define CYREG_CAN_CONFIG 0x402e0014 +#define CYFLD_CAN_EDGE_MODE__OFFSET 0x00000000 +#define CYFLD_CAN_EDGE_MODE__SIZE 0x00000001 +#define CYFLD_CAN_SAMPLING_MODE__OFFSET 0x00000001 +#define CYFLD_CAN_SAMPLING_MODE__SIZE 0x00000001 +#define CYFLD_CAN_CFG_SJW__OFFSET 0x00000002 +#define CYFLD_CAN_CFG_SJW__SIZE 0x00000002 +#define CYFLD_CAN_AUTO_RESTART__OFFSET 0x00000004 +#define CYFLD_CAN_AUTO_RESTART__SIZE 0x00000001 +#define CYFLD_CAN_CFG_TSEG2__OFFSET 0x00000005 +#define CYFLD_CAN_CFG_TSEG2__SIZE 0x00000003 +#define CYFLD_CAN_CFG_TSEG1__OFFSET 0x00000008 +#define CYFLD_CAN_CFG_TSEG1__SIZE 0x00000004 +#define CYFLD_CAN_CFG_ARBITER__OFFSET 0x0000000c +#define CYFLD_CAN_CFG_ARBITER__SIZE 0x00000001 +#define CYFLD_CAN_SWAP_ENDIAN__OFFSET 0x0000000d +#define CYFLD_CAN_SWAP_ENDIAN__SIZE 0x00000001 +#define CYFLD_CAN_ECR_MODE__OFFSET 0x0000000e +#define CYFLD_CAN_ECR_MODE__SIZE 0x00000001 +#define CYFLD_CAN_CFG_BITRATE__OFFSET 0x00000010 +#define CYFLD_CAN_CFG_BITRATE__SIZE 0x0000000f +#define CYREG_CAN_ECR 0x402e0018 +#define CYFLD_CAN_ECR_STATUS__OFFSET 0x00000000 +#define CYFLD_CAN_ECR_STATUS__SIZE 0x00000001 +#define CYFLD_CAN_ERROR_TYPE__OFFSET 0x00000001 +#define CYFLD_CAN_ERROR_TYPE__SIZE 0x00000003 +#define CYFLD_CAN_RX_MODE__OFFSET 0x00000004 +#define CYFLD_CAN_RX_MODE__SIZE 0x00000001 +#define CYFLD_CAN_TX_MODE__OFFSET 0x00000005 +#define CYFLD_CAN_TX_MODE__SIZE 0x00000001 +#define CYFLD_CAN_BIT__OFFSET 0x00000006 +#define CYFLD_CAN_BIT__SIZE 0x00000006 +#define CYFLD_CAN_Field__OFFSET 0x0000000c +#define CYFLD_CAN_Field__SIZE 0x00000005 +#define CYDEV_CAN_CAN_TX0_BASE 0x402e0020 +#define CYDEV_CAN_CAN_TX0_SIZE 0x00000010 +#define CYREG_CAN_CAN_TX0_CONTROL 0x402e0020 +#define CYFLD_CAN_CAN_TX_TX_REQ__OFFSET 0x00000000 +#define CYFLD_CAN_CAN_TX_TX_REQ__SIZE 0x00000001 +#define CYFLD_CAN_CAN_TX_TX_ABORT__OFFSET 0x00000001 +#define CYFLD_CAN_CAN_TX_TX_ABORT__SIZE 0x00000001 +#define CYFLD_CAN_CAN_TX_TX_INT_EBL__OFFSET 0x00000002 +#define CYFLD_CAN_CAN_TX_TX_INT_EBL__SIZE 0x00000001 +#define CYFLD_CAN_CAN_TX_WPNL__OFFSET 0x00000003 +#define CYFLD_CAN_CAN_TX_WPNL__SIZE 0x00000001 +#define CYFLD_CAN_CAN_TX_DLC__OFFSET 0x00000010 +#define CYFLD_CAN_CAN_TX_DLC__SIZE 0x00000004 +#define CYFLD_CAN_CAN_TX_IDE__OFFSET 0x00000014 +#define CYFLD_CAN_CAN_TX_IDE__SIZE 0x00000001 +#define CYFLD_CAN_CAN_TX_RTR__OFFSET 0x00000015 +#define CYFLD_CAN_CAN_TX_RTR__SIZE 0x00000001 +#define CYFLD_CAN_CAN_TX_WPNH__OFFSET 0x00000017 +#define CYFLD_CAN_CAN_TX_WPNH__SIZE 0x00000001 +#define CYREG_CAN_CAN_TX0_ID 0x402e0024 +#define CYFLD_CAN_CAN_TX_ID__OFFSET 0x00000003 +#define CYFLD_CAN_CAN_TX_ID__SIZE 0x0000001d +#define CYREG_CAN_CAN_TX0_DATA_HIGH 0x402e0028 +#define CYFLD_CAN_CAN_TX_DATA__OFFSET 0x00000000 +#define CYFLD_CAN_CAN_TX_DATA__SIZE 0x00000020 +#define CYREG_CAN_CAN_TX0_DATA_LOW 0x402e002c +#define CYDEV_CAN_CAN_TX1_BASE 0x402e0030 +#define CYDEV_CAN_CAN_TX1_SIZE 0x00000010 +#define CYREG_CAN_CAN_TX1_CONTROL 0x402e0030 +#define CYREG_CAN_CAN_TX1_ID 0x402e0034 +#define CYREG_CAN_CAN_TX1_DATA_HIGH 0x402e0038 +#define CYREG_CAN_CAN_TX1_DATA_LOW 0x402e003c +#define CYDEV_CAN_CAN_TX2_BASE 0x402e0040 +#define CYDEV_CAN_CAN_TX2_SIZE 0x00000010 +#define CYREG_CAN_CAN_TX2_CONTROL 0x402e0040 +#define CYREG_CAN_CAN_TX2_ID 0x402e0044 +#define CYREG_CAN_CAN_TX2_DATA_HIGH 0x402e0048 +#define CYREG_CAN_CAN_TX2_DATA_LOW 0x402e004c +#define CYDEV_CAN_CAN_TX3_BASE 0x402e0050 +#define CYDEV_CAN_CAN_TX3_SIZE 0x00000010 +#define CYREG_CAN_CAN_TX3_CONTROL 0x402e0050 +#define CYREG_CAN_CAN_TX3_ID 0x402e0054 +#define CYREG_CAN_CAN_TX3_DATA_HIGH 0x402e0058 +#define CYREG_CAN_CAN_TX3_DATA_LOW 0x402e005c +#define CYDEV_CAN_CAN_TX4_BASE 0x402e0060 +#define CYDEV_CAN_CAN_TX4_SIZE 0x00000010 +#define CYREG_CAN_CAN_TX4_CONTROL 0x402e0060 +#define CYREG_CAN_CAN_TX4_ID 0x402e0064 +#define CYREG_CAN_CAN_TX4_DATA_HIGH 0x402e0068 +#define CYREG_CAN_CAN_TX4_DATA_LOW 0x402e006c +#define CYDEV_CAN_CAN_TX5_BASE 0x402e0070 +#define CYDEV_CAN_CAN_TX5_SIZE 0x00000010 +#define CYREG_CAN_CAN_TX5_CONTROL 0x402e0070 +#define CYREG_CAN_CAN_TX5_ID 0x402e0074 +#define CYREG_CAN_CAN_TX5_DATA_HIGH 0x402e0078 +#define CYREG_CAN_CAN_TX5_DATA_LOW 0x402e007c +#define CYDEV_CAN_CAN_TX6_BASE 0x402e0080 +#define CYDEV_CAN_CAN_TX6_SIZE 0x00000010 +#define CYREG_CAN_CAN_TX6_CONTROL 0x402e0080 +#define CYREG_CAN_CAN_TX6_ID 0x402e0084 +#define CYREG_CAN_CAN_TX6_DATA_HIGH 0x402e0088 +#define CYREG_CAN_CAN_TX6_DATA_LOW 0x402e008c +#define CYDEV_CAN_CAN_TX7_BASE 0x402e0090 +#define CYDEV_CAN_CAN_TX7_SIZE 0x00000010 +#define CYREG_CAN_CAN_TX7_CONTROL 0x402e0090 +#define CYREG_CAN_CAN_TX7_ID 0x402e0094 +#define CYREG_CAN_CAN_TX7_DATA_HIGH 0x402e0098 +#define CYREG_CAN_CAN_TX7_DATA_LOW 0x402e009c +#define CYDEV_CAN_CAN_RX0_BASE 0x402e00a0 +#define CYDEV_CAN_CAN_RX0_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX0_CONTROL 0x402e00a0 +#define CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__OFFSET 0x00000000 +#define CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__SIZE 0x00000001 +#define CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__OFFSET 0x00000001 +#define CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__SIZE 0x00000001 +#define CYFLD_CAN_CAN_RX_RTR_ABORT__OFFSET 0x00000002 +#define CYFLD_CAN_CAN_RX_RTR_ABORT__SIZE 0x00000001 +#define CYFLD_CAN_CAN_RX_BUFFER_EN__OFFSET 0x00000003 +#define CYFLD_CAN_CAN_RX_BUFFER_EN__SIZE 0x00000001 +#define CYFLD_CAN_CAN_RX_RTR_REPLY__OFFSET 0x00000004 +#define CYFLD_CAN_CAN_RX_RTR_REPLY__SIZE 0x00000001 +#define CYFLD_CAN_CAN_RX_RX_INT_EBL__OFFSET 0x00000005 +#define CYFLD_CAN_CAN_RX_RX_INT_EBL__SIZE 0x00000001 +#define CYFLD_CAN_CAN_RX_LINK_FLAG__OFFSET 0x00000006 +#define CYFLD_CAN_CAN_RX_LINK_FLAG__SIZE 0x00000001 +#define CYFLD_CAN_CAN_RX_WPNL__OFFSET 0x00000007 +#define CYFLD_CAN_CAN_RX_WPNL__SIZE 0x00000001 +#define CYFLD_CAN_CAN_RX_DLC__OFFSET 0x00000010 +#define CYFLD_CAN_CAN_RX_DLC__SIZE 0x00000004 +#define CYFLD_CAN_CAN_RX_IDE_FMT__OFFSET 0x00000014 +#define CYFLD_CAN_CAN_RX_IDE_FMT__SIZE 0x00000001 +#define CYFLD_CAN_CAN_RX_RTR_MSG__OFFSET 0x00000015 +#define CYFLD_CAN_CAN_RX_RTR_MSG__SIZE 0x00000001 +#define CYFLD_CAN_CAN_RX_WPNH__OFFSET 0x00000017 +#define CYFLD_CAN_CAN_RX_WPNH__SIZE 0x00000001 +#define CYREG_CAN_CAN_RX0_ID 0x402e00a4 +#define CYFLD_CAN_CAN_RX_ID__OFFSET 0x00000003 +#define CYFLD_CAN_CAN_RX_ID__SIZE 0x0000001d +#define CYREG_CAN_CAN_RX0_DATA_HIGH 0x402e00a8 +#define CYFLD_CAN_CAN_RX_DATA__OFFSET 0x00000000 +#define CYFLD_CAN_CAN_RX_DATA__SIZE 0x00000020 +#define CYREG_CAN_CAN_RX0_DATA_LOW 0x402e00ac +#define CYREG_CAN_CAN_RX0_AMR 0x402e00b0 +#define CYFLD_CAN_CAN_RX_RTR__OFFSET 0x00000001 +#define CYFLD_CAN_CAN_RX_RTR__SIZE 0x00000001 +#define CYFLD_CAN_CAN_RX_IDE__OFFSET 0x00000002 +#define CYFLD_CAN_CAN_RX_IDE__SIZE 0x00000001 +#define CYREG_CAN_CAN_RX0_ACR 0x402e00b4 +#define CYREG_CAN_CAN_RX0_AMR_DATA 0x402e00b8 +#define CYFLD_CAN_CAN_RX_DATAL__OFFSET 0x00000000 +#define CYFLD_CAN_CAN_RX_DATAL__SIZE 0x00000010 +#define CYREG_CAN_CAN_RX0_ACR_DATA 0x402e00bc +#define CYDEV_CAN_CAN_RX1_BASE 0x402e00c0 +#define CYDEV_CAN_CAN_RX1_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX1_CONTROL 0x402e00c0 +#define CYREG_CAN_CAN_RX1_ID 0x402e00c4 +#define CYREG_CAN_CAN_RX1_DATA_HIGH 0x402e00c8 +#define CYREG_CAN_CAN_RX1_DATA_LOW 0x402e00cc +#define CYREG_CAN_CAN_RX1_AMR 0x402e00d0 +#define CYREG_CAN_CAN_RX1_ACR 0x402e00d4 +#define CYREG_CAN_CAN_RX1_AMR_DATA 0x402e00d8 +#define CYREG_CAN_CAN_RX1_ACR_DATA 0x402e00dc +#define CYDEV_CAN_CAN_RX2_BASE 0x402e00e0 +#define CYDEV_CAN_CAN_RX2_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX2_CONTROL 0x402e00e0 +#define CYREG_CAN_CAN_RX2_ID 0x402e00e4 +#define CYREG_CAN_CAN_RX2_DATA_HIGH 0x402e00e8 +#define CYREG_CAN_CAN_RX2_DATA_LOW 0x402e00ec +#define CYREG_CAN_CAN_RX2_AMR 0x402e00f0 +#define CYREG_CAN_CAN_RX2_ACR 0x402e00f4 +#define CYREG_CAN_CAN_RX2_AMR_DATA 0x402e00f8 +#define CYREG_CAN_CAN_RX2_ACR_DATA 0x402e00fc +#define CYDEV_CAN_CAN_RX3_BASE 0x402e0100 +#define CYDEV_CAN_CAN_RX3_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX3_CONTROL 0x402e0100 +#define CYREG_CAN_CAN_RX3_ID 0x402e0104 +#define CYREG_CAN_CAN_RX3_DATA_HIGH 0x402e0108 +#define CYREG_CAN_CAN_RX3_DATA_LOW 0x402e010c +#define CYREG_CAN_CAN_RX3_AMR 0x402e0110 +#define CYREG_CAN_CAN_RX3_ACR 0x402e0114 +#define CYREG_CAN_CAN_RX3_AMR_DATA 0x402e0118 +#define CYREG_CAN_CAN_RX3_ACR_DATA 0x402e011c +#define CYDEV_CAN_CAN_RX4_BASE 0x402e0120 +#define CYDEV_CAN_CAN_RX4_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX4_CONTROL 0x402e0120 +#define CYREG_CAN_CAN_RX4_ID 0x402e0124 +#define CYREG_CAN_CAN_RX4_DATA_HIGH 0x402e0128 +#define CYREG_CAN_CAN_RX4_DATA_LOW 0x402e012c +#define CYREG_CAN_CAN_RX4_AMR 0x402e0130 +#define CYREG_CAN_CAN_RX4_ACR 0x402e0134 +#define CYREG_CAN_CAN_RX4_AMR_DATA 0x402e0138 +#define CYREG_CAN_CAN_RX4_ACR_DATA 0x402e013c +#define CYDEV_CAN_CAN_RX5_BASE 0x402e0140 +#define CYDEV_CAN_CAN_RX5_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX5_CONTROL 0x402e0140 +#define CYREG_CAN_CAN_RX5_ID 0x402e0144 +#define CYREG_CAN_CAN_RX5_DATA_HIGH 0x402e0148 +#define CYREG_CAN_CAN_RX5_DATA_LOW 0x402e014c +#define CYREG_CAN_CAN_RX5_AMR 0x402e0150 +#define CYREG_CAN_CAN_RX5_ACR 0x402e0154 +#define CYREG_CAN_CAN_RX5_AMR_DATA 0x402e0158 +#define CYREG_CAN_CAN_RX5_ACR_DATA 0x402e015c +#define CYDEV_CAN_CAN_RX6_BASE 0x402e0160 +#define CYDEV_CAN_CAN_RX6_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX6_CONTROL 0x402e0160 +#define CYREG_CAN_CAN_RX6_ID 0x402e0164 +#define CYREG_CAN_CAN_RX6_DATA_HIGH 0x402e0168 +#define CYREG_CAN_CAN_RX6_DATA_LOW 0x402e016c +#define CYREG_CAN_CAN_RX6_AMR 0x402e0170 +#define CYREG_CAN_CAN_RX6_ACR 0x402e0174 +#define CYREG_CAN_CAN_RX6_AMR_DATA 0x402e0178 +#define CYREG_CAN_CAN_RX6_ACR_DATA 0x402e017c +#define CYDEV_CAN_CAN_RX7_BASE 0x402e0180 +#define CYDEV_CAN_CAN_RX7_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX7_CONTROL 0x402e0180 +#define CYREG_CAN_CAN_RX7_ID 0x402e0184 +#define CYREG_CAN_CAN_RX7_DATA_HIGH 0x402e0188 +#define CYREG_CAN_CAN_RX7_DATA_LOW 0x402e018c +#define CYREG_CAN_CAN_RX7_AMR 0x402e0190 +#define CYREG_CAN_CAN_RX7_ACR 0x402e0194 +#define CYREG_CAN_CAN_RX7_AMR_DATA 0x402e0198 +#define CYREG_CAN_CAN_RX7_ACR_DATA 0x402e019c +#define CYDEV_CAN_CAN_RX8_BASE 0x402e01a0 +#define CYDEV_CAN_CAN_RX8_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX8_CONTROL 0x402e01a0 +#define CYREG_CAN_CAN_RX8_ID 0x402e01a4 +#define CYREG_CAN_CAN_RX8_DATA_HIGH 0x402e01a8 +#define CYREG_CAN_CAN_RX8_DATA_LOW 0x402e01ac +#define CYREG_CAN_CAN_RX8_AMR 0x402e01b0 +#define CYREG_CAN_CAN_RX8_ACR 0x402e01b4 +#define CYREG_CAN_CAN_RX8_AMR_DATA 0x402e01b8 +#define CYREG_CAN_CAN_RX8_ACR_DATA 0x402e01bc +#define CYDEV_CAN_CAN_RX9_BASE 0x402e01c0 +#define CYDEV_CAN_CAN_RX9_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX9_CONTROL 0x402e01c0 +#define CYREG_CAN_CAN_RX9_ID 0x402e01c4 +#define CYREG_CAN_CAN_RX9_DATA_HIGH 0x402e01c8 +#define CYREG_CAN_CAN_RX9_DATA_LOW 0x402e01cc +#define CYREG_CAN_CAN_RX9_AMR 0x402e01d0 +#define CYREG_CAN_CAN_RX9_ACR 0x402e01d4 +#define CYREG_CAN_CAN_RX9_AMR_DATA 0x402e01d8 +#define CYREG_CAN_CAN_RX9_ACR_DATA 0x402e01dc +#define CYDEV_CAN_CAN_RX10_BASE 0x402e01e0 +#define CYDEV_CAN_CAN_RX10_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX10_CONTROL 0x402e01e0 +#define CYREG_CAN_CAN_RX10_ID 0x402e01e4 +#define CYREG_CAN_CAN_RX10_DATA_HIGH 0x402e01e8 +#define CYREG_CAN_CAN_RX10_DATA_LOW 0x402e01ec +#define CYREG_CAN_CAN_RX10_AMR 0x402e01f0 +#define CYREG_CAN_CAN_RX10_ACR 0x402e01f4 +#define CYREG_CAN_CAN_RX10_AMR_DATA 0x402e01f8 +#define CYREG_CAN_CAN_RX10_ACR_DATA 0x402e01fc +#define CYDEV_CAN_CAN_RX11_BASE 0x402e0200 +#define CYDEV_CAN_CAN_RX11_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX11_CONTROL 0x402e0200 +#define CYREG_CAN_CAN_RX11_ID 0x402e0204 +#define CYREG_CAN_CAN_RX11_DATA_HIGH 0x402e0208 +#define CYREG_CAN_CAN_RX11_DATA_LOW 0x402e020c +#define CYREG_CAN_CAN_RX11_AMR 0x402e0210 +#define CYREG_CAN_CAN_RX11_ACR 0x402e0214 +#define CYREG_CAN_CAN_RX11_AMR_DATA 0x402e0218 +#define CYREG_CAN_CAN_RX11_ACR_DATA 0x402e021c +#define CYDEV_CAN_CAN_RX12_BASE 0x402e0220 +#define CYDEV_CAN_CAN_RX12_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX12_CONTROL 0x402e0220 +#define CYREG_CAN_CAN_RX12_ID 0x402e0224 +#define CYREG_CAN_CAN_RX12_DATA_HIGH 0x402e0228 +#define CYREG_CAN_CAN_RX12_DATA_LOW 0x402e022c +#define CYREG_CAN_CAN_RX12_AMR 0x402e0230 +#define CYREG_CAN_CAN_RX12_ACR 0x402e0234 +#define CYREG_CAN_CAN_RX12_AMR_DATA 0x402e0238 +#define CYREG_CAN_CAN_RX12_ACR_DATA 0x402e023c +#define CYDEV_CAN_CAN_RX13_BASE 0x402e0240 +#define CYDEV_CAN_CAN_RX13_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX13_CONTROL 0x402e0240 +#define CYREG_CAN_CAN_RX13_ID 0x402e0244 +#define CYREG_CAN_CAN_RX13_DATA_HIGH 0x402e0248 +#define CYREG_CAN_CAN_RX13_DATA_LOW 0x402e024c +#define CYREG_CAN_CAN_RX13_AMR 0x402e0250 +#define CYREG_CAN_CAN_RX13_ACR 0x402e0254 +#define CYREG_CAN_CAN_RX13_AMR_DATA 0x402e0258 +#define CYREG_CAN_CAN_RX13_ACR_DATA 0x402e025c +#define CYDEV_CAN_CAN_RX14_BASE 0x402e0260 +#define CYDEV_CAN_CAN_RX14_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX14_CONTROL 0x402e0260 +#define CYREG_CAN_CAN_RX14_ID 0x402e0264 +#define CYREG_CAN_CAN_RX14_DATA_HIGH 0x402e0268 +#define CYREG_CAN_CAN_RX14_DATA_LOW 0x402e026c +#define CYREG_CAN_CAN_RX14_AMR 0x402e0270 +#define CYREG_CAN_CAN_RX14_ACR 0x402e0274 +#define CYREG_CAN_CAN_RX14_AMR_DATA 0x402e0278 +#define CYREG_CAN_CAN_RX14_ACR_DATA 0x402e027c +#define CYDEV_CAN_CAN_RX15_BASE 0x402e0280 +#define CYDEV_CAN_CAN_RX15_SIZE 0x00000020 +#define CYREG_CAN_CAN_RX15_CONTROL 0x402e0280 +#define CYREG_CAN_CAN_RX15_ID 0x402e0284 +#define CYREG_CAN_CAN_RX15_DATA_HIGH 0x402e0288 +#define CYREG_CAN_CAN_RX15_DATA_LOW 0x402e028c +#define CYREG_CAN_CAN_RX15_AMR 0x402e0290 +#define CYREG_CAN_CAN_RX15_ACR 0x402e0294 +#define CYREG_CAN_CAN_RX15_AMR_DATA 0x402e0298 +#define CYREG_CAN_CAN_RX15_ACR_DATA 0x402e029c +#define CYREG_CAN_CNTL 0x402e0400 +#define CYFLD_CAN_TT_ENABLE__OFFSET 0x00000000 +#define CYFLD_CAN_TT_ENABLE__SIZE 0x00000001 +#define CYFLD_CAN_IP_ENABLE__OFFSET 0x0000001f +#define CYFLD_CAN_IP_ENABLE__SIZE 0x00000001 +#define CYREG_CAN_TTCAN_COUNTER 0x402e0404 +#define CYFLD_CAN_LOCAL_TIME__OFFSET 0x00000010 +#define CYFLD_CAN_LOCAL_TIME__SIZE 0x00000010 +#define CYREG_CAN_TTCAN_COMPARE 0x402e0408 +#define CYFLD_CAN_TIME_MARK__OFFSET 0x00000010 +#define CYFLD_CAN_TIME_MARK__SIZE 0x00000010 +#define CYREG_CAN_TTCAN_CAPTURE 0x402e040c +#define CYFLD_CAN_SYNC_MARK__OFFSET 0x00000010 +#define CYFLD_CAN_SYNC_MARK__SIZE 0x00000010 +#define CYREG_CAN_TTCAN_TIMING 0x402e0410 +#define CYREG_CAN_INTR_CAN 0x402e0414 +#define CYFLD_CAN_INT_STATUS__OFFSET 0x00000000 +#define CYFLD_CAN_INT_STATUS__SIZE 0x00000001 +#define CYFLD_CAN_TT_COMPARE__OFFSET 0x00000001 +#define CYFLD_CAN_TT_COMPARE__SIZE 0x00000001 +#define CYFLD_CAN_TT_CAPTURE__OFFSET 0x00000002 +#define CYFLD_CAN_TT_CAPTURE__SIZE 0x00000001 +#define CYREG_CAN_INTR_CAN_SET 0x402e0418 +#define CYREG_CAN_INTR_CAN_MASK 0x402e041c +#define CYREG_CAN_INTR_CAN_MASKED 0x402e0420 +#define CYDEV_EXCO_BASE 0x402f0000 +#define CYDEV_EXCO_SIZE 0x00010000 +#define CYREG_EXCO_CLK_SELECT 0x402f0000 +#define CYFLD_EXCO_CLK_SELECT__OFFSET 0x00000000 +#define CYFLD_EXCO_CLK_SELECT__SIZE 0x00000001 +#define CYFLD_EXCO_REF_SEL__OFFSET 0x00000001 +#define CYFLD_EXCO_REF_SEL__SIZE 0x00000001 +#define CYREG_EXCO_ECO_CONFIG 0x402f0008 +#define CYFLD_EXCO_CLK_EN__OFFSET 0x00000000 +#define CYFLD_EXCO_CLK_EN__SIZE 0x00000001 +#define CYFLD_EXCO_AGC_EN__OFFSET 0x00000001 +#define CYFLD_EXCO_AGC_EN__SIZE 0x00000001 +#define CYFLD_EXCO_ENABLE__OFFSET 0x0000001f +#define CYFLD_EXCO_ENABLE__SIZE 0x00000001 +#define CYREG_EXCO_ECO_STATUS 0x402f000c +#define CYFLD_EXCO_WATCHDOG_ERROR__OFFSET 0x00000000 +#define CYFLD_EXCO_WATCHDOG_ERROR__SIZE 0x00000001 +#define CYREG_EXCO_PLL_CONFIG 0x402f0014 +#define CYFLD_EXCO_FEEDBACK_DIV__OFFSET 0x00000000 +#define CYFLD_EXCO_FEEDBACK_DIV__SIZE 0x00000008 +#define CYFLD_EXCO_REFERENCE_DIV__OFFSET 0x00000008 +#define CYFLD_EXCO_REFERENCE_DIV__SIZE 0x00000006 +#define CYFLD_EXCO_OUTPUT_DIV__OFFSET 0x0000000e +#define CYFLD_EXCO_OUTPUT_DIV__SIZE 0x00000002 +#define CYVAL_EXCO_OUTPUT_DIV_PASS 0x00000000 +#define CYVAL_EXCO_OUTPUT_DIV_DIV2 0x00000001 +#define CYVAL_EXCO_OUTPUT_DIV_DIV4 0x00000002 +#define CYVAL_EXCO_OUTPUT_DIV_DIV8 0x00000003 +#define CYFLD_EXCO_ICP_SEL__OFFSET 0x00000010 +#define CYFLD_EXCO_ICP_SEL__SIZE 0x00000003 +#define CYFLD_EXCO_BYPASS_SEL__OFFSET 0x00000014 +#define CYFLD_EXCO_BYPASS_SEL__SIZE 0x00000002 +#define CYVAL_EXCO_BYPASS_SEL_AUTO 0x00000000 +#define CYVAL_EXCO_BYPASS_SEL_AUTO1 0x00000001 +#define CYVAL_EXCO_BYPASS_SEL_PLL_REF 0x00000002 +#define CYVAL_EXCO_BYPASS_SEL_PLL_OUT 0x00000003 +#define CYFLD_EXCO_ISOLATE_N__OFFSET 0x0000001e +#define CYFLD_EXCO_ISOLATE_N__SIZE 0x00000001 +#define CYREG_EXCO_PLL_STATUS 0x402f0018 +#define CYFLD_EXCO_LOCKED__OFFSET 0x00000000 +#define CYFLD_EXCO_LOCKED__SIZE 0x00000001 +#define CYREG_EXCO_PLL_TEST 0x402f001c +#define CYFLD_EXCO_TEST_MODE__OFFSET 0x00000000 +#define CYFLD_EXCO_TEST_MODE__SIZE 0x00000003 +#define CYVAL_EXCO_TEST_MODE_NORMAL 0x00000000 +#define CYVAL_EXCO_TEST_MODE_TEST_VC_LKG 0x00000001 +#define CYVAL_EXCO_TEST_MODE_TEST_CP_DN 0x00000002 +#define CYVAL_EXCO_TEST_MODE_TEST_CP_UP 0x00000003 +#define CYVAL_EXCO_TEST_MODE_USER_EXT_FL 0x00000004 +#define CYVAL_EXCO_TEST_MODE_TEST_CTR_PQ 0x00000005 +#define CYVAL_EXCO_TEST_MODE_TEST_LD_DLY 0x00000006 +#define CYVAL_EXCO_TEST_MODE_TEST_CTR_ALT 0x00000007 +#define CYFLD_EXCO_FAST_LOCK_EN__OFFSET 0x00000003 +#define CYFLD_EXCO_FAST_LOCK_EN__SIZE 0x00000001 +#define CYFLD_EXCO_UNLOCK_OCCURRED__OFFSET 0x00000004 +#define CYFLD_EXCO_UNLOCK_OCCURRED__SIZE 0x00000001 +#define CYREG_EXCO_EXCO_PGM_CLK 0x402f0020 +#define CYFLD_EXCO_CLK_ECO__OFFSET 0x00000001 +#define CYFLD_EXCO_CLK_ECO__SIZE 0x00000001 +#define CYFLD_EXCO_CLK_PLL0_IN__OFFSET 0x00000002 +#define CYFLD_EXCO_CLK_PLL0_IN__SIZE 0x00000001 +#define CYFLD_EXCO_CLK_PLL0_OUT__OFFSET 0x00000003 +#define CYFLD_EXCO_CLK_PLL0_OUT__SIZE 0x00000001 +#define CYFLD_EXCO_EN_CLK_PLL0__OFFSET 0x00000004 +#define CYFLD_EXCO_EN_CLK_PLL0__SIZE 0x00000001 +#define CYREG_EXCO_ECO_TRIM0 0x402fff00 +#define CYFLD_EXCO_WDTRIM__OFFSET 0x00000000 +#define CYFLD_EXCO_WDTRIM__SIZE 0x00000002 +#define CYFLD_EXCO_ATRIM__OFFSET 0x00000002 +#define CYFLD_EXCO_ATRIM__SIZE 0x00000003 +#define CYREG_EXCO_ECO_TRIM1 0x402fff04 +#define CYFLD_EXCO_FTRIM__OFFSET 0x00000000 +#define CYFLD_EXCO_FTRIM__SIZE 0x00000002 +#define CYFLD_EXCO_RTRIM__OFFSET 0x00000002 +#define CYFLD_EXCO_RTRIM__SIZE 0x00000002 +#define CYFLD_EXCO_GTRIM__OFFSET 0x00000004 +#define CYFLD_EXCO_GTRIM__SIZE 0x00000002 +#define CYREG_EXCO_ECO_TRIM2 0x402fff08 +#define CYFLD_EXCO_ITRIM__OFFSET 0x00000000 +#define CYFLD_EXCO_ITRIM__SIZE 0x00000006 +#define CYREG_EXCO_PLL_TRIM 0x402fff0c +#define CYFLD_EXCO_VCO_GAIN__OFFSET 0x00000000 +#define CYFLD_EXCO_VCO_GAIN__SIZE 0x00000002 +#define CYFLD_EXCO_LOCK_WINDOW__OFFSET 0x00000002 +#define CYFLD_EXCO_LOCK_WINDOW__SIZE 0x00000002 +#define CYVAL_EXCO_LOCK_WINDOW_DELAY_25NS 0x00000000 +#define CYVAL_EXCO_LOCK_WINDOW_DELAY_50NS 0x00000001 +#define CYVAL_EXCO_LOCK_WINDOW_DELAY_75NS 0x00000002 +#define CYVAL_EXCO_LOCK_WINDOW_DELAY_100NS 0x00000003 +#define CYFLD_EXCO_LOCK_DELAY__OFFSET 0x00000004 +#define CYFLD_EXCO_LOCK_DELAY__SIZE 0x00000002 +#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_16 0x00000000 +#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_32 0x00000001 +#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_48 0x00000002 +#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_64 0x00000003 +#define CYDEV_CTBM0_BASE 0x40300000 +#define CYDEV_CTBM0_SIZE 0x00010000 +#define CYREG_CTBM0_CTB_CTRL 0x40300000 +#define CYFLD_CTBM_DEEPSLEEP_ON__OFFSET 0x0000001e +#define CYFLD_CTBM_DEEPSLEEP_ON__SIZE 0x00000001 +#define CYFLD_CTBM_ENABLED__OFFSET 0x0000001f +#define CYFLD_CTBM_ENABLED__SIZE 0x00000001 +#define CYREG_CTBM0_OA_RES0_CTRL 0x40300004 +#define CYFLD_CTBM_OA0_PWR_MODE__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_PWR_MODE__SIZE 0x00000002 +#define CYVAL_CTBM_OA0_PWR_MODE_OFF 0x00000000 +#define CYVAL_CTBM_OA0_PWR_MODE_LOW 0x00000001 +#define CYVAL_CTBM_OA0_PWR_MODE_MEDIUM 0x00000002 +#define CYVAL_CTBM_OA0_PWR_MODE_HIGH 0x00000003 +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET 0x00000002 +#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_COMP_EN__OFFSET 0x00000004 +#define CYFLD_CTBM_OA0_COMP_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_HYST_EN__OFFSET 0x00000005 +#define CYFLD_CTBM_OA0_HYST_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET 0x00000006 +#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_DSI_LEVEL__OFFSET 0x00000007 +#define CYFLD_CTBM_OA0_DSI_LEVEL__SIZE 0x00000001 +#define CYFLD_CTBM_OA0_COMPINT__OFFSET 0x00000008 +#define CYFLD_CTBM_OA0_COMPINT__SIZE 0x00000002 +#define CYVAL_CTBM_OA0_COMPINT_DISABLE 0x00000000 +#define CYVAL_CTBM_OA0_COMPINT_RISING 0x00000001 +#define CYVAL_CTBM_OA0_COMPINT_FALLING 0x00000002 +#define CYVAL_CTBM_OA0_COMPINT_BOTH 0x00000003 +#define CYFLD_CTBM_OA0_PUMP_EN__OFFSET 0x0000000b +#define CYFLD_CTBM_OA0_PUMP_EN__SIZE 0x00000001 +#define CYREG_CTBM0_OA_RES1_CTRL 0x40300008 +#define CYFLD_CTBM_OA1_PWR_MODE__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_PWR_MODE__SIZE 0x00000002 +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET 0x00000002 +#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_COMP_EN__OFFSET 0x00000004 +#define CYFLD_CTBM_OA1_COMP_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_HYST_EN__OFFSET 0x00000005 +#define CYFLD_CTBM_OA1_HYST_EN__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET 0x00000006 +#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_DSI_LEVEL__OFFSET 0x00000007 +#define CYFLD_CTBM_OA1_DSI_LEVEL__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_COMPINT__OFFSET 0x00000008 +#define CYFLD_CTBM_OA1_COMPINT__SIZE 0x00000002 +#define CYVAL_CTBM_OA1_COMPINT_DISABLE 0x00000000 +#define CYVAL_CTBM_OA1_COMPINT_RISING 0x00000001 +#define CYVAL_CTBM_OA1_COMPINT_FALLING 0x00000002 +#define CYVAL_CTBM_OA1_COMPINT_BOTH 0x00000003 +#define CYFLD_CTBM_OA1_PUMP_EN__OFFSET 0x0000000b +#define CYFLD_CTBM_OA1_PUMP_EN__SIZE 0x00000001 +#define CYREG_CTBM0_COMP_STAT 0x4030000c +#define CYFLD_CTBM_OA0_COMP__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_COMP__SIZE 0x00000001 +#define CYFLD_CTBM_OA1_COMP__OFFSET 0x00000010 +#define CYFLD_CTBM_OA1_COMP__SIZE 0x00000001 +#define CYREG_CTBM0_INTR 0x40300020 +#define CYFLD_CTBM_COMP0__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1__SIZE 0x00000001 +#define CYREG_CTBM0_INTR_SET 0x40300024 +#define CYFLD_CTBM_COMP0_SET__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0_SET__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1_SET__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1_SET__SIZE 0x00000001 +#define CYREG_CTBM0_INTR_MASK 0x40300028 +#define CYFLD_CTBM_COMP0_MASK__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0_MASK__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1_MASK__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1_MASK__SIZE 0x00000001 +#define CYREG_CTBM0_INTR_MASKED 0x4030002c +#define CYFLD_CTBM_COMP0_MASKED__OFFSET 0x00000000 +#define CYFLD_CTBM_COMP0_MASKED__SIZE 0x00000001 +#define CYFLD_CTBM_COMP1_MASKED__OFFSET 0x00000001 +#define CYFLD_CTBM_COMP1_MASKED__SIZE 0x00000001 +#define CYREG_CTBM0_DFT_CTRL 0x40300030 +#define CYFLD_CTBM_DFT_MODE__OFFSET 0x00000000 +#define CYFLD_CTBM_DFT_MODE__SIZE 0x00000003 +#define CYFLD_CTBM_DFT_EN__OFFSET 0x0000001f +#define CYFLD_CTBM_DFT_EN__SIZE 0x00000001 +#define CYREG_CTBM0_OA0_SW 0x40300080 +#define CYFLD_CTBM_OA0P_A00__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0P_A00__SIZE 0x00000001 +#define CYFLD_CTBM_OA0P_A20__OFFSET 0x00000002 +#define CYFLD_CTBM_OA0P_A20__SIZE 0x00000001 +#define CYFLD_CTBM_OA0P_A30__OFFSET 0x00000003 +#define CYFLD_CTBM_OA0P_A30__SIZE 0x00000001 +#define CYFLD_CTBM_OA0M_A11__OFFSET 0x00000008 +#define CYFLD_CTBM_OA0M_A11__SIZE 0x00000001 +#define CYFLD_CTBM_OA0M_A81__OFFSET 0x0000000e +#define CYFLD_CTBM_OA0M_A81__SIZE 0x00000001 +#define CYFLD_CTBM_OA0O_D51__OFFSET 0x00000012 +#define CYFLD_CTBM_OA0O_D51__SIZE 0x00000001 +#define CYFLD_CTBM_OA0O_D81__OFFSET 0x00000015 +#define CYFLD_CTBM_OA0O_D81__SIZE 0x00000001 +#define CYREG_CTBM0_OA0_SW_CLEAR 0x40300084 +#define CYREG_CTBM0_OA1_SW 0x40300088 +#define CYFLD_CTBM_OA1P_A03__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1P_A03__SIZE 0x00000001 +#define CYFLD_CTBM_OA1P_A13__OFFSET 0x00000001 +#define CYFLD_CTBM_OA1P_A13__SIZE 0x00000001 +#define CYFLD_CTBM_OA1P_A43__OFFSET 0x00000004 +#define CYFLD_CTBM_OA1P_A43__SIZE 0x00000001 +#define CYFLD_CTBM_OA1M_A22__OFFSET 0x00000008 +#define CYFLD_CTBM_OA1M_A22__SIZE 0x00000001 +#define CYFLD_CTBM_OA1M_A82__OFFSET 0x0000000e +#define CYFLD_CTBM_OA1M_A82__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D52__OFFSET 0x00000012 +#define CYFLD_CTBM_OA1O_D52__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D62__OFFSET 0x00000013 +#define CYFLD_CTBM_OA1O_D62__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D82__OFFSET 0x00000015 +#define CYFLD_CTBM_OA1O_D82__SIZE 0x00000001 +#define CYREG_CTBM0_OA1_SW_CLEAR 0x4030008c +#define CYREG_CTBM0_CTB_SW_HW_CTRL 0x403000c0 +#define CYFLD_CTBM_P2_HW_CTRL__OFFSET 0x00000002 +#define CYFLD_CTBM_P2_HW_CTRL__SIZE 0x00000001 +#define CYFLD_CTBM_P3_HW_CTRL__OFFSET 0x00000003 +#define CYFLD_CTBM_P3_HW_CTRL__SIZE 0x00000001 +#define CYREG_CTBM0_CTB_SW_STATUS 0x403000c4 +#define CYFLD_CTBM_OA0O_D51_STAT__OFFSET 0x0000001c +#define CYFLD_CTBM_OA0O_D51_STAT__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D52_STAT__OFFSET 0x0000001d +#define CYFLD_CTBM_OA1O_D52_STAT__SIZE 0x00000001 +#define CYFLD_CTBM_OA1O_D62_STAT__OFFSET 0x0000001e +#define CYFLD_CTBM_OA1O_D62_STAT__SIZE 0x00000001 +#define CYREG_CTBM0_OA0_OFFSET_TRIM 0x40300f00 +#define CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM0_OA0_SLOPE_OFFSET_TRIM 0x40300f04 +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM0_OA0_COMP_TRIM 0x40300f08 +#define CYFLD_CTBM_OA0_COMP_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA0_COMP_TRIM__SIZE 0x00000002 +#define CYREG_CTBM0_OA1_OFFSET_TRIM 0x40300f0c +#define CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM0_OA1_SLOPE_OFFSET_TRIM 0x40300f10 +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE 0x00000006 +#define CYREG_CTBM0_OA1_COMP_TRIM 0x40300f14 +#define CYFLD_CTBM_OA1_COMP_TRIM__OFFSET 0x00000000 +#define CYFLD_CTBM_OA1_COMP_TRIM__SIZE 0x00000002 +#define CYDEV_SAR_BASE 0x403a0000 +#define CYDEV_SAR_SIZE 0x00010000 +#define CYREG_SAR_CTRL 0x403a0000 +#define CYFLD_SAR_VREF_SEL__OFFSET 0x00000004 +#define CYFLD_SAR_VREF_SEL__SIZE 0x00000003 +#define CYVAL_SAR_VREF_SEL_VREF0 0x00000000 +#define CYVAL_SAR_VREF_SEL_VREF1 0x00000001 +#define CYVAL_SAR_VREF_SEL_VREF2 0x00000002 +#define CYVAL_SAR_VREF_SEL_VREF_AROUTE 0x00000003 +#define CYVAL_SAR_VREF_SEL_VBGR 0x00000004 +#define CYVAL_SAR_VREF_SEL_VREF_EXT 0x00000005 +#define CYVAL_SAR_VREF_SEL_VDDA_DIV_2 0x00000006 +#define CYVAL_SAR_VREF_SEL_VDDA 0x00000007 +#define CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET 0x00000007 +#define CYFLD_SAR_VREF_BYP_CAP_EN__SIZE 0x00000001 +#define CYFLD_SAR_NEG_SEL__OFFSET 0x00000009 +#define CYFLD_SAR_NEG_SEL__SIZE 0x00000003 +#define CYVAL_SAR_NEG_SEL_VSSA_KELVIN 0x00000000 +#define CYVAL_SAR_NEG_SEL_ART_VSSA 0x00000001 +#define CYVAL_SAR_NEG_SEL_P1 0x00000002 +#define CYVAL_SAR_NEG_SEL_P3 0x00000003 +#define CYVAL_SAR_NEG_SEL_P5 0x00000004 +#define CYVAL_SAR_NEG_SEL_P7 0x00000005 +#define CYVAL_SAR_NEG_SEL_ACORE 0x00000006 +#define CYVAL_SAR_NEG_SEL_VREF 0x00000007 +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET 0x0000000d +#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE 0x00000001 +#define CYFLD_SAR_PWR_CTRL_VREF__OFFSET 0x0000000e +#define CYFLD_SAR_PWR_CTRL_VREF__SIZE 0x00000002 +#define CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR 0x00000000 +#define CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR 0x00000001 +#define CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR 0x00000002 +#define CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR 0x00000003 +#define CYFLD_SAR_SPARE__OFFSET 0x00000010 +#define CYFLD_SAR_SPARE__SIZE 0x00000004 +#define CYFLD_SAR_BOOSTPUMP_EN__OFFSET 0x00000014 +#define CYFLD_SAR_BOOSTPUMP_EN__SIZE 0x00000001 +#define CYFLD_SAR_ICONT_LV__OFFSET 0x00000018 +#define CYFLD_SAR_ICONT_LV__SIZE 0x00000002 +#define CYVAL_SAR_ICONT_LV_NORMAL_PWR 0x00000000 +#define CYVAL_SAR_ICONT_LV_HALF_PWR 0x00000001 +#define CYVAL_SAR_ICONT_LV_MORE_PWR 0x00000002 +#define CYVAL_SAR_ICONT_LV_QUARTER_PWR 0x00000003 +#define CYFLD_SAR_DEEPSLEEP_ON__OFFSET 0x0000001b +#define CYFLD_SAR_DEEPSLEEP_ON__SIZE 0x00000001 +#define CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET 0x0000001c +#define CYFLD_SAR_DSI_SYNC_CONFIG__SIZE 0x00000001 +#define CYFLD_SAR_DSI_MODE__OFFSET 0x0000001d +#define CYFLD_SAR_DSI_MODE__SIZE 0x00000001 +#define CYFLD_SAR_SWITCH_DISABLE__OFFSET 0x0000001e +#define CYFLD_SAR_SWITCH_DISABLE__SIZE 0x00000001 +#define CYFLD_SAR_ENABLED__OFFSET 0x0000001f +#define CYFLD_SAR_ENABLED__SIZE 0x00000001 +#define CYREG_SAR_SAMPLE_CTRL 0x403a0004 +#define CYFLD_SAR_SUB_RESOLUTION__OFFSET 0x00000000 +#define CYFLD_SAR_SUB_RESOLUTION__SIZE 0x00000001 +#define CYVAL_SAR_SUB_RESOLUTION_8B 0x00000000 +#define CYVAL_SAR_SUB_RESOLUTION_10B 0x00000001 +#define CYFLD_SAR_LEFT_ALIGN__OFFSET 0x00000001 +#define CYFLD_SAR_LEFT_ALIGN__SIZE 0x00000001 +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET 0x00000002 +#define CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE 0x00000001 +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED 0x00000000 +#define CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED 0x00000001 +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET 0x00000003 +#define CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE 0x00000001 +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED 0x00000000 +#define CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED 0x00000001 +#define CYFLD_SAR_AVG_CNT__OFFSET 0x00000004 +#define CYFLD_SAR_AVG_CNT__SIZE 0x00000003 +#define CYFLD_SAR_AVG_SHIFT__OFFSET 0x00000007 +#define CYFLD_SAR_AVG_SHIFT__SIZE 0x00000001 +#define CYFLD_SAR_CONTINUOUS__OFFSET 0x00000010 +#define CYFLD_SAR_CONTINUOUS__SIZE 0x00000001 +#define CYFLD_SAR_DSI_TRIGGER_EN__OFFSET 0x00000011 +#define CYFLD_SAR_DSI_TRIGGER_EN__SIZE 0x00000001 +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET 0x00000012 +#define CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE 0x00000001 +#define CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET 0x00000013 +#define CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE 0x00000001 +#define CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET 0x0000001f +#define CYFLD_SAR_EOS_DSI_OUT_EN__SIZE 0x00000001 +#define CYREG_SAR_SAMPLE_TIME01 0x403a0010 +#define CYFLD_SAR_SAMPLE_TIME0__OFFSET 0x00000000 +#define CYFLD_SAR_SAMPLE_TIME0__SIZE 0x0000000a +#define CYFLD_SAR_SAMPLE_TIME1__OFFSET 0x00000010 +#define CYFLD_SAR_SAMPLE_TIME1__SIZE 0x0000000a +#define CYREG_SAR_SAMPLE_TIME23 0x403a0014 +#define CYFLD_SAR_SAMPLE_TIME2__OFFSET 0x00000000 +#define CYFLD_SAR_SAMPLE_TIME2__SIZE 0x0000000a +#define CYFLD_SAR_SAMPLE_TIME3__OFFSET 0x00000010 +#define CYFLD_SAR_SAMPLE_TIME3__SIZE 0x0000000a +#define CYREG_SAR_RANGE_THRES 0x403a0018 +#define CYFLD_SAR_RANGE_LOW__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_LOW__SIZE 0x00000010 +#define CYFLD_SAR_RANGE_HIGH__OFFSET 0x00000010 +#define CYFLD_SAR_RANGE_HIGH__SIZE 0x00000010 +#define CYREG_SAR_RANGE_COND 0x403a001c +#define CYFLD_SAR_RANGE_COND__OFFSET 0x0000001e +#define CYFLD_SAR_RANGE_COND__SIZE 0x00000002 +#define CYVAL_SAR_RANGE_COND_BELOW 0x00000000 +#define CYVAL_SAR_RANGE_COND_INSIDE 0x00000001 +#define CYVAL_SAR_RANGE_COND_ABOVE 0x00000002 +#define CYVAL_SAR_RANGE_COND_OUTSIDE 0x00000003 +#define CYREG_SAR_CHAN_EN 0x403a0020 +#define CYFLD_SAR_CHAN_EN__OFFSET 0x00000000 +#define CYFLD_SAR_CHAN_EN__SIZE 0x00000010 +#define CYREG_SAR_START_CTRL 0x403a0024 +#define CYFLD_SAR_FW_TRIGGER__OFFSET 0x00000000 +#define CYFLD_SAR_FW_TRIGGER__SIZE 0x00000001 +#define CYREG_SAR_DFT_CTRL 0x403a0030 +#define CYFLD_SAR_DLY_INC__OFFSET 0x00000000 +#define CYFLD_SAR_DLY_INC__SIZE 0x00000001 +#define CYFLD_SAR_HIZ__OFFSET 0x00000001 +#define CYFLD_SAR_HIZ__SIZE 0x00000001 +#define CYFLD_SAR_DFT_INC__OFFSET 0x00000010 +#define CYFLD_SAR_DFT_INC__SIZE 0x00000004 +#define CYFLD_SAR_DFT_OUTC__OFFSET 0x00000014 +#define CYFLD_SAR_DFT_OUTC__SIZE 0x00000003 +#define CYFLD_SAR_SEL_CSEL_DFT__OFFSET 0x00000018 +#define CYFLD_SAR_SEL_CSEL_DFT__SIZE 0x00000004 +#define CYFLD_SAR_EN_CSEL_DFT__OFFSET 0x0000001c +#define CYFLD_SAR_EN_CSEL_DFT__SIZE 0x00000001 +#define CYFLD_SAR_DCEN__OFFSET 0x0000001d +#define CYFLD_SAR_DCEN__SIZE 0x00000001 +#define CYFLD_SAR_ADFT_OVERRIDE__OFFSET 0x0000001f +#define CYFLD_SAR_ADFT_OVERRIDE__SIZE 0x00000001 +#define CYREG_SAR_CHAN_CONFIG0 0x403a0080 +#define CYFLD_SAR_PIN_ADDR__OFFSET 0x00000000 +#define CYFLD_SAR_PIN_ADDR__SIZE 0x00000003 +#define CYFLD_SAR_PORT_ADDR__OFFSET 0x00000004 +#define CYFLD_SAR_PORT_ADDR__SIZE 0x00000003 +#define CYVAL_SAR_PORT_ADDR_SARMUX 0x00000000 +#define CYVAL_SAR_PORT_ADDR_CTB0 0x00000001 +#define CYVAL_SAR_PORT_ADDR_CTB1 0x00000002 +#define CYVAL_SAR_PORT_ADDR_CTB2 0x00000003 +#define CYVAL_SAR_PORT_ADDR_CTB3 0x00000004 +#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT2 0x00000005 +#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT1 0x00000006 +#define CYVAL_SAR_PORT_ADDR_SARMUX_VIRT 0x00000007 +#define CYFLD_SAR_DIFFERENTIAL_EN__OFFSET 0x00000008 +#define CYFLD_SAR_DIFFERENTIAL_EN__SIZE 0x00000001 +#define CYFLD_SAR_RESOLUTION__OFFSET 0x00000009 +#define CYFLD_SAR_RESOLUTION__SIZE 0x00000001 +#define CYVAL_SAR_RESOLUTION_MAXRES 0x00000000 +#define CYVAL_SAR_RESOLUTION_SUBRES 0x00000001 +#define CYFLD_SAR_AVG_EN__OFFSET 0x0000000a +#define CYFLD_SAR_AVG_EN__SIZE 0x00000001 +#define CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET 0x0000000c +#define CYFLD_SAR_SAMPLE_TIME_SEL__SIZE 0x00000002 +#define CYFLD_SAR_DSI_OUT_EN__OFFSET 0x0000001f +#define CYFLD_SAR_DSI_OUT_EN__SIZE 0x00000001 +#define CYREG_SAR_CHAN_CONFIG1 0x403a0084 +#define CYREG_SAR_CHAN_CONFIG2 0x403a0088 +#define CYREG_SAR_CHAN_CONFIG3 0x403a008c +#define CYREG_SAR_CHAN_CONFIG4 0x403a0090 +#define CYREG_SAR_CHAN_CONFIG5 0x403a0094 +#define CYREG_SAR_CHAN_CONFIG6 0x403a0098 +#define CYREG_SAR_CHAN_CONFIG7 0x403a009c +#define CYREG_SAR_CHAN_CONFIG8 0x403a00a0 +#define CYREG_SAR_CHAN_CONFIG9 0x403a00a4 +#define CYREG_SAR_CHAN_CONFIG10 0x403a00a8 +#define CYREG_SAR_CHAN_CONFIG11 0x403a00ac +#define CYREG_SAR_CHAN_CONFIG12 0x403a00b0 +#define CYREG_SAR_CHAN_CONFIG13 0x403a00b4 +#define CYREG_SAR_CHAN_CONFIG14 0x403a00b8 +#define CYREG_SAR_CHAN_CONFIG15 0x403a00bc +#define CYREG_SAR_CHAN_WORK0 0x403a0100 +#define CYFLD_SAR_WORK__OFFSET 0x00000000 +#define CYFLD_SAR_WORK__SIZE 0x00000010 +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET 0x0000001f +#define CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE 0x00000001 +#define CYREG_SAR_CHAN_WORK1 0x403a0104 +#define CYREG_SAR_CHAN_WORK2 0x403a0108 +#define CYREG_SAR_CHAN_WORK3 0x403a010c +#define CYREG_SAR_CHAN_WORK4 0x403a0110 +#define CYREG_SAR_CHAN_WORK5 0x403a0114 +#define CYREG_SAR_CHAN_WORK6 0x403a0118 +#define CYREG_SAR_CHAN_WORK7 0x403a011c +#define CYREG_SAR_CHAN_WORK8 0x403a0120 +#define CYREG_SAR_CHAN_WORK9 0x403a0124 +#define CYREG_SAR_CHAN_WORK10 0x403a0128 +#define CYREG_SAR_CHAN_WORK11 0x403a012c +#define CYREG_SAR_CHAN_WORK12 0x403a0130 +#define CYREG_SAR_CHAN_WORK13 0x403a0134 +#define CYREG_SAR_CHAN_WORK14 0x403a0138 +#define CYREG_SAR_CHAN_WORK15 0x403a013c +#define CYREG_SAR_CHAN_RESULT0 0x403a0180 +#define CYFLD_SAR_RESULT__OFFSET 0x00000000 +#define CYFLD_SAR_RESULT__SIZE 0x00000010 +#define CYFLD_SAR_SATURATE_INTR_MIR__OFFSET 0x0000001d +#define CYFLD_SAR_SATURATE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_RANGE_INTR_MIR__OFFSET 0x0000001e +#define CYFLD_SAR_RANGE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET 0x0000001f +#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE 0x00000001 +#define CYREG_SAR_CHAN_RESULT1 0x403a0184 +#define CYREG_SAR_CHAN_RESULT2 0x403a0188 +#define CYREG_SAR_CHAN_RESULT3 0x403a018c +#define CYREG_SAR_CHAN_RESULT4 0x403a0190 +#define CYREG_SAR_CHAN_RESULT5 0x403a0194 +#define CYREG_SAR_CHAN_RESULT6 0x403a0198 +#define CYREG_SAR_CHAN_RESULT7 0x403a019c +#define CYREG_SAR_CHAN_RESULT8 0x403a01a0 +#define CYREG_SAR_CHAN_RESULT9 0x403a01a4 +#define CYREG_SAR_CHAN_RESULT10 0x403a01a8 +#define CYREG_SAR_CHAN_RESULT11 0x403a01ac +#define CYREG_SAR_CHAN_RESULT12 0x403a01b0 +#define CYREG_SAR_CHAN_RESULT13 0x403a01b4 +#define CYREG_SAR_CHAN_RESULT14 0x403a01b8 +#define CYREG_SAR_CHAN_RESULT15 0x403a01bc +#define CYREG_SAR_CHAN_WORK_VALID 0x403a0200 +#define CYFLD_SAR_CHAN_WORK_VALID__OFFSET 0x00000000 +#define CYFLD_SAR_CHAN_WORK_VALID__SIZE 0x00000010 +#define CYREG_SAR_CHAN_RESULT_VALID 0x403a0204 +#define CYFLD_SAR_CHAN_RESULT_VALID__OFFSET 0x00000000 +#define CYFLD_SAR_CHAN_RESULT_VALID__SIZE 0x00000010 +#define CYREG_SAR_STATUS 0x403a0208 +#define CYFLD_SAR_CUR_CHAN__OFFSET 0x00000000 +#define CYFLD_SAR_CUR_CHAN__SIZE 0x00000005 +#define CYFLD_SAR_SW_VREF_NEG__OFFSET 0x0000001e +#define CYFLD_SAR_SW_VREF_NEG__SIZE 0x00000001 +#define CYFLD_SAR_BUSY__OFFSET 0x0000001f +#define CYFLD_SAR_BUSY__SIZE 0x00000001 +#define CYREG_SAR_AVG_STAT 0x403a020c +#define CYFLD_SAR_CUR_AVG_ACCU__OFFSET 0x00000000 +#define CYFLD_SAR_CUR_AVG_ACCU__SIZE 0x00000014 +#define CYFLD_SAR_CUR_AVG_CNT__OFFSET 0x00000018 +#define CYFLD_SAR_CUR_AVG_CNT__SIZE 0x00000008 +#define CYREG_SAR_INTR 0x403a0210 +#define CYFLD_SAR_EOS_INTR__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_INTR__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_INTR__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_INTR__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_INTR__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_INTR__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_INTR__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_INTR__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_INTR__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_INTR__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_INTR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_INTR__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_INTR__SIZE 0x00000001 +#define CYREG_SAR_INTR_SET 0x403a0214 +#define CYFLD_SAR_EOS_SET__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_SET__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_SET__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_SET__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_SET__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_SET__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_SET__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_SET__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_SET__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_SET__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_SET__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_SET__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_SET__SIZE 0x00000001 +#define CYREG_SAR_INTR_MASK 0x403a0218 +#define CYFLD_SAR_EOS_MASK__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_MASK__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASK__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASK__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_MASK__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_MASK__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_MASK__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_MASK__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_MASK__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_MASK__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_MASK__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_MASK__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_MASK__SIZE 0x00000001 +#define CYREG_SAR_INTR_MASKED 0x403a021c +#define CYFLD_SAR_EOS_MASKED__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_MASKED__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_MASKED__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_MASKED__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_MASKED__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_MASKED__SIZE 0x00000001 +#define CYREG_SAR_SATURATE_INTR 0x403a0220 +#define CYFLD_SAR_SATURATE_INTR__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_INTR__SIZE 0x00000010 +#define CYREG_SAR_SATURATE_INTR_SET 0x403a0224 +#define CYFLD_SAR_SATURATE_SET__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_SET__SIZE 0x00000010 +#define CYREG_SAR_SATURATE_INTR_MASK 0x403a0228 +#define CYFLD_SAR_SATURATE_MASK__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_MASK__SIZE 0x00000010 +#define CYREG_SAR_SATURATE_INTR_MASKED 0x403a022c +#define CYFLD_SAR_SATURATE_MASKED__OFFSET 0x00000000 +#define CYFLD_SAR_SATURATE_MASKED__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR 0x403a0230 +#define CYFLD_SAR_RANGE_INTR__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_INTR__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR_SET 0x403a0234 +#define CYFLD_SAR_RANGE_SET__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_SET__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR_MASK 0x403a0238 +#define CYFLD_SAR_RANGE_MASK__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_MASK__SIZE 0x00000010 +#define CYREG_SAR_RANGE_INTR_MASKED 0x403a023c +#define CYFLD_SAR_RANGE_MASKED__OFFSET 0x00000000 +#define CYFLD_SAR_RANGE_MASKED__SIZE 0x00000010 +#define CYREG_SAR_INTR_CAUSE 0x403a0240 +#define CYFLD_SAR_EOS_MASKED_MIR__OFFSET 0x00000000 +#define CYFLD_SAR_EOS_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET 0x00000001 +#define CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET 0x00000002 +#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET 0x00000003 +#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET 0x00000005 +#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET 0x00000006 +#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET 0x00000007 +#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE 0x00000001 +#define CYFLD_SAR_SATURATE_MASKED_RED__OFFSET 0x0000001e +#define CYFLD_SAR_SATURATE_MASKED_RED__SIZE 0x00000001 +#define CYFLD_SAR_RANGE_MASKED_RED__OFFSET 0x0000001f +#define CYFLD_SAR_RANGE_MASKED_RED__SIZE 0x00000001 +#define CYREG_SAR_INJ_CHAN_CONFIG 0x403a0280 +#define CYFLD_SAR_INJ_PIN_ADDR__OFFSET 0x00000000 +#define CYFLD_SAR_INJ_PIN_ADDR__SIZE 0x00000003 +#define CYFLD_SAR_INJ_PORT_ADDR__OFFSET 0x00000004 +#define CYFLD_SAR_INJ_PORT_ADDR__SIZE 0x00000003 +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX 0x00000000 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB0 0x00000001 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB1 0x00000002 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB2 0x00000003 +#define CYVAL_SAR_INJ_PORT_ADDR_CTB3 0x00000004 +#define CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT 0x00000006 +#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT 0x00000007 +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET 0x00000008 +#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RESOLUTION__OFFSET 0x00000009 +#define CYFLD_SAR_INJ_RESOLUTION__SIZE 0x00000001 +#define CYVAL_SAR_INJ_RESOLUTION_12B 0x00000000 +#define CYVAL_SAR_INJ_RESOLUTION_SUBRES 0x00000001 +#define CYFLD_SAR_INJ_AVG_EN__OFFSET 0x0000000a +#define CYFLD_SAR_INJ_AVG_EN__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET 0x0000000c +#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE 0x00000002 +#define CYFLD_SAR_INJ_TAILGATING__OFFSET 0x0000001e +#define CYFLD_SAR_INJ_TAILGATING__SIZE 0x00000001 +#define CYFLD_SAR_INJ_START_EN__OFFSET 0x0000001f +#define CYFLD_SAR_INJ_START_EN__SIZE 0x00000001 +#define CYREG_SAR_INJ_RESULT 0x403a0290 +#define CYFLD_SAR_INJ_RESULT__OFFSET 0x00000000 +#define CYFLD_SAR_INJ_RESULT__SIZE 0x00000010 +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET 0x0000001c +#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET 0x0000001d +#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET 0x0000001e +#define CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE 0x00000001 +#define CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET 0x0000001f +#define CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH0 0x403a0300 +#define CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET 0x00000000 +#define CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET 0x00000001 +#define CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET 0x00000002 +#define CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET 0x00000003 +#define CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET 0x00000004 +#define CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET 0x00000005 +#define CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET 0x00000006 +#define CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET 0x00000007 +#define CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET 0x00000008 +#define CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET 0x00000009 +#define CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET 0x0000000a +#define CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET 0x0000000b +#define CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET 0x0000000c +#define CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET 0x0000000d +#define CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET 0x0000000e +#define CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET 0x0000000f +#define CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET 0x00000010 +#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET 0x00000011 +#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET 0x00000012 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET 0x00000013 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET 0x00000014 +#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET 0x00000015 +#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET 0x00000016 +#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET 0x00000017 +#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET 0x00000018 +#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET 0x00000019 +#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET 0x0000001a +#define CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET 0x0000001b +#define CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET 0x0000001c +#define CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET 0x0000001d +#define CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH_CLEAR0 0x403a0304 +#define CYREG_SAR_MUX_SWITCH1 0x403a0308 +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET 0x00000000 +#define CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET 0x00000001 +#define CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET 0x00000002 +#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET 0x00000003 +#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH_CLEAR1 0x403a030c +#define CYREG_SAR_MUX_SWITCH_HW_CTRL 0x403a0340 +#define CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET 0x00000000 +#define CYFLD_SAR_MUX_HW_CTRL_P0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P1__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET 0x00000002 +#define CYFLD_SAR_MUX_HW_CTRL_P2__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET 0x00000003 +#define CYFLD_SAR_MUX_HW_CTRL_P3__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET 0x00000004 +#define CYFLD_SAR_MUX_HW_CTRL_P4__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET 0x00000005 +#define CYFLD_SAR_MUX_HW_CTRL_P5__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET 0x00000006 +#define CYFLD_SAR_MUX_HW_CTRL_P6__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET 0x00000007 +#define CYFLD_SAR_MUX_HW_CTRL_P7__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET 0x00000010 +#define CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET 0x00000011 +#define CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET 0x00000012 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET 0x00000013 +#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET 0x00000016 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE 0x00000001 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET 0x00000017 +#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE 0x00000001 +#define CYREG_SAR_MUX_SWITCH_STATUS 0x403a0348 +#define CYREG_SAR_PUMP_CTRL 0x403a0380 +#define CYFLD_SAR_CLOCK_SEL__OFFSET 0x00000000 +#define CYFLD_SAR_CLOCK_SEL__SIZE 0x00000001 +#define CYREG_SAR_ANA_TRIM 0x403a0f00 +#define CYFLD_SAR_CAP_TRIM__OFFSET 0x00000000 +#define CYFLD_SAR_CAP_TRIM__SIZE 0x00000003 +#define CYFLD_SAR_TRIMUNIT__OFFSET 0x00000003 +#define CYFLD_SAR_TRIMUNIT__SIZE 0x00000001 +#define CYREG_SAR_WOUNDING 0x403a0f04 +#define CYFLD_SAR_WOUND_RESOLUTION__OFFSET 0x00000000 +#define CYFLD_SAR_WOUND_RESOLUTION__SIZE 0x00000002 +#define CYVAL_SAR_WOUND_RESOLUTION_12BIT 0x00000000 +#define CYVAL_SAR_WOUND_RESOLUTION_10BIT 0x00000001 +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT 0x00000002 +#define CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO 0x00000003 +#define CYDEV_PASS_BASE 0x403f0000 +#define CYDEV_PASS_SIZE 0x00010000 +#define CYREG_PASS_INTR_CAUSE 0x403f0000 +#define CYFLD_PASS_CTB0_INT__OFFSET 0x00000000 +#define CYFLD_PASS_CTB0_INT__SIZE 0x00000001 +#define CYREG_PASS_DFT_CTRL 0x403f0030 +#define CYFLD_PASS_DSAB_ADFT_RES_EN__OFFSET 0x00000000 +#define CYFLD_PASS_DSAB_ADFT_RES_EN__SIZE 0x00000001 +#define CYREG_PASS_PASS_CTRL 0x403f0108 +#define CYFLD_PASS_PMPCLK_BYP__OFFSET 0x00000000 +#define CYFLD_PASS_PMPCLK_BYP__SIZE 0x00000001 +#define CYFLD_PASS_PMPCLK_SRC__OFFSET 0x00000001 +#define CYFLD_PASS_PMPCLK_SRC__SIZE 0x00000001 +#define CYFLD_PASS_RMB_BITS__OFFSET 0x00000008 +#define CYFLD_PASS_RMB_BITS__SIZE 0x00000008 +#define CYDEV_PASS_DSAB_BASE 0x403f0e00 +#define CYDEV_PASS_DSAB_SIZE 0x00000100 +#define CYREG_PASS_DSAB_DSAB_CTRL 0x403f0e00 +#define CYFLD_PASS_DSAB_CURRENT_SEL__OFFSET 0x00000000 +#define CYFLD_PASS_DSAB_CURRENT_SEL__SIZE 0x00000006 +#define CYFLD_PASS_DSAB_SEL_OUT__OFFSET 0x00000008 +#define CYFLD_PASS_DSAB_SEL_OUT__SIZE 0x00000004 +#define CYFLD_PASS_DSAB_REF_SWAP_EN__OFFSET 0x00000010 +#define CYFLD_PASS_DSAB_REF_SWAP_EN__SIZE 0x00000004 +#define CYFLD_PASS_DSAB_BYPASS_MODE_EN__OFFSET 0x00000018 +#define CYFLD_PASS_DSAB_BYPASS_MODE_EN__SIZE 0x00000001 +#define CYFLD_PASS_DSAB_STARTUP_RM__OFFSET 0x0000001c +#define CYFLD_PASS_DSAB_STARTUP_RM__SIZE 0x00000001 +#define CYFLD_PASS_DSAB_ENABLED__OFFSET 0x0000001f +#define CYFLD_PASS_DSAB_ENABLED__SIZE 0x00000001 +#define CYREG_PASS_DSAB_DSAB_DFT 0x403f0e04 +#define CYFLD_PASS_DSAB_EN_DFT__OFFSET 0x00000000 +#define CYFLD_PASS_DSAB_EN_DFT__SIZE 0x00000004 +#define CYREG_PASS_DSAB_TRIM 0x403f0f00 +#define CYFLD_PASS_IBIAS_TRIM__OFFSET 0x00000000 +#define CYFLD_PASS_IBIAS_TRIM__SIZE 0x00000004 +#define CYFLD_PASS_DSAB_RMB_BITS__OFFSET 0x00000004 +#define CYFLD_PASS_DSAB_RMB_BITS__SIZE 0x00000002 +#define CYDEV_CM0P_BASE 0xe0000000 +#define CYDEV_CM0P_SIZE 0x00100000 +#define CYREG_CM0P_DWT_PID4 0xe0001fd0 +#define CYFLD_CM0P_VALUE__OFFSET 0x00000000 +#define CYFLD_CM0P_VALUE__SIZE 0x00000020 +#define CYREG_CM0P_DWT_PID0 0xe0001fe0 +#define CYREG_CM0P_DWT_PID1 0xe0001fe4 +#define CYREG_CM0P_DWT_PID2 0xe0001fe8 +#define CYREG_CM0P_DWT_PID3 0xe0001fec +#define CYREG_CM0P_DWT_CID0 0xe0001ff0 +#define CYREG_CM0P_DWT_CID1 0xe0001ff4 +#define CYREG_CM0P_DWT_CID2 0xe0001ff8 +#define CYREG_CM0P_DWT_CID3 0xe0001ffc +#define CYREG_CM0P_BP_PID4 0xe0002fd0 +#define CYREG_CM0P_BP_PID0 0xe0002fe0 +#define CYREG_CM0P_BP_PID1 0xe0002fe4 +#define CYREG_CM0P_BP_PID2 0xe0002fe8 +#define CYREG_CM0P_BP_PID3 0xe0002fec +#define CYREG_CM0P_BP_CID0 0xe0002ff0 +#define CYREG_CM0P_BP_CID1 0xe0002ff4 +#define CYREG_CM0P_BP_CID2 0xe0002ff8 +#define CYREG_CM0P_BP_CID3 0xe0002ffc +#define CYREG_CM0P_SYST_CSR 0xe000e010 +#define CYFLD_CM0P_ENABLE__OFFSET 0x00000000 +#define CYFLD_CM0P_ENABLE__SIZE 0x00000001 +#define CYFLD_CM0P_TICKINT__OFFSET 0x00000001 +#define CYFLD_CM0P_TICKINT__SIZE 0x00000001 +#define CYFLD_CM0P_CLKSOURCE__OFFSET 0x00000002 +#define CYFLD_CM0P_CLKSOURCE__SIZE 0x00000001 +#define CYFLD_CM0P_COUNTFLAG__OFFSET 0x00000010 +#define CYFLD_CM0P_COUNTFLAG__SIZE 0x00000001 +#define CYREG_CM0P_SYST_RVR 0xe000e014 +#define CYFLD_CM0P_RELOAD__OFFSET 0x00000000 +#define CYFLD_CM0P_RELOAD__SIZE 0x00000018 +#define CYREG_CM0P_SYST_CVR 0xe000e018 +#define CYFLD_CM0P_CURRENT__OFFSET 0x00000000 +#define CYFLD_CM0P_CURRENT__SIZE 0x00000018 +#define CYREG_CM0P_SYST_CALIB 0xe000e01c +#define CYFLD_CM0P_TENMS__OFFSET 0x00000000 +#define CYFLD_CM0P_TENMS__SIZE 0x00000018 +#define CYFLD_CM0P_SKEW__OFFSET 0x0000001e +#define CYFLD_CM0P_SKEW__SIZE 0x00000001 +#define CYFLD_CM0P_NOREF__OFFSET 0x0000001f +#define CYFLD_CM0P_NOREF__SIZE 0x00000001 +#define CYREG_CM0P_ISER 0xe000e100 +#define CYFLD_CM0P_SETENA__OFFSET 0x00000000 +#define CYFLD_CM0P_SETENA__SIZE 0x00000020 +#define CYREG_CM0P_ICER 0xe000e180 +#define CYFLD_CM0P_CLRENA__OFFSET 0x00000000 +#define CYFLD_CM0P_CLRENA__SIZE 0x00000020 +#define CYREG_CM0P_ISPR 0xe000e200 +#define CYFLD_CM0P_SETPEND__OFFSET 0x00000000 +#define CYFLD_CM0P_SETPEND__SIZE 0x00000020 +#define CYREG_CM0P_ICPR 0xe000e280 +#define CYFLD_CM0P_CLRPEND__OFFSET 0x00000000 +#define CYFLD_CM0P_CLRPEND__SIZE 0x00000020 +#define CYREG_CM0P_IPR0 0xe000e400 +#define CYFLD_CM0P_PRI_N0__OFFSET 0x00000006 +#define CYFLD_CM0P_PRI_N0__SIZE 0x00000002 +#define CYFLD_CM0P_PRI_N1__OFFSET 0x0000000e +#define CYFLD_CM0P_PRI_N1__SIZE 0x00000002 +#define CYFLD_CM0P_PRI_N2__OFFSET 0x00000016 +#define CYFLD_CM0P_PRI_N2__SIZE 0x00000002 +#define CYFLD_CM0P_PRI_N3__OFFSET 0x0000001e +#define CYFLD_CM0P_PRI_N3__SIZE 0x00000002 +#define CYREG_CM0P_IPR1 0xe000e404 +#define CYREG_CM0P_IPR2 0xe000e408 +#define CYREG_CM0P_IPR3 0xe000e40c +#define CYREG_CM0P_IPR4 0xe000e410 +#define CYREG_CM0P_IPR5 0xe000e414 +#define CYREG_CM0P_IPR6 0xe000e418 +#define CYREG_CM0P_IPR7 0xe000e41c +#define CYREG_CM0P_CPUID 0xe000ed00 +#define CYFLD_CM0P_REVISION__OFFSET 0x00000000 +#define CYFLD_CM0P_REVISION__SIZE 0x00000004 +#define CYFLD_CM0P_PARTNO__OFFSET 0x00000004 +#define CYFLD_CM0P_PARTNO__SIZE 0x0000000c +#define CYFLD_CM0P_CONSTANT__OFFSET 0x00000010 +#define CYFLD_CM0P_CONSTANT__SIZE 0x00000004 +#define CYFLD_CM0P_VARIANT__OFFSET 0x00000014 +#define CYFLD_CM0P_VARIANT__SIZE 0x00000004 +#define CYFLD_CM0P_IMPLEMENTER__OFFSET 0x00000018 +#define CYFLD_CM0P_IMPLEMENTER__SIZE 0x00000008 +#define CYREG_CM0P_ICSR 0xe000ed04 +#define CYFLD_CM0P_VECTACTIVE__OFFSET 0x00000000 +#define CYFLD_CM0P_VECTACTIVE__SIZE 0x00000009 +#define CYFLD_CM0P_VECTPENDING__OFFSET 0x0000000c +#define CYFLD_CM0P_VECTPENDING__SIZE 0x00000009 +#define CYFLD_CM0P_ISRPENDING__OFFSET 0x00000016 +#define CYFLD_CM0P_ISRPENDING__SIZE 0x00000001 +#define CYFLD_CM0P_ISRPREEMPT__OFFSET 0x00000017 +#define CYFLD_CM0P_ISRPREEMPT__SIZE 0x00000001 +#define CYFLD_CM0P_PENDSTCLR__OFFSET 0x00000019 +#define CYFLD_CM0P_PENDSTCLR__SIZE 0x00000001 +#define CYFLD_CM0P_PENDSTSETb__OFFSET 0x0000001a +#define CYFLD_CM0P_PENDSTSETb__SIZE 0x00000001 +#define CYFLD_CM0P_PENDSVCLR__OFFSET 0x0000001b +#define CYFLD_CM0P_PENDSVCLR__SIZE 0x00000001 +#define CYFLD_CM0P_PENDSVSET__OFFSET 0x0000001c +#define CYFLD_CM0P_PENDSVSET__SIZE 0x00000001 +#define CYFLD_CM0P_NMIPENDSET__OFFSET 0x0000001f +#define CYFLD_CM0P_NMIPENDSET__SIZE 0x00000001 +#define CYREG_CM0P_VTOR 0xe000ed08 +#define CYFLD_CM0P_TBLOFF__OFFSET 0x00000008 +#define CYFLD_CM0P_TBLOFF__SIZE 0x00000018 +#define CYREG_CM0P_AIRCR 0xe000ed0c +#define CYFLD_CM0P_VECTCLRACTIVE__OFFSET 0x00000001 +#define CYFLD_CM0P_VECTCLRACTIVE__SIZE 0x00000001 +#define CYFLD_CM0P_SYSRESETREQ__OFFSET 0x00000002 +#define CYFLD_CM0P_SYSRESETREQ__SIZE 0x00000001 +#define CYFLD_CM0P_ENDIANNESS__OFFSET 0x0000000f +#define CYFLD_CM0P_ENDIANNESS__SIZE 0x00000001 +#define CYFLD_CM0P_VECTKEY__OFFSET 0x00000010 +#define CYFLD_CM0P_VECTKEY__SIZE 0x00000010 +#define CYREG_CM0P_SCR 0xe000ed10 +#define CYFLD_CM0P_SLEEPONEXIT__OFFSET 0x00000001 +#define CYFLD_CM0P_SLEEPONEXIT__SIZE 0x00000001 +#define CYFLD_CM0P_SLEEPDEEP__OFFSET 0x00000002 +#define CYFLD_CM0P_SLEEPDEEP__SIZE 0x00000001 +#define CYFLD_CM0P_SEVONPEND__OFFSET 0x00000004 +#define CYFLD_CM0P_SEVONPEND__SIZE 0x00000001 +#define CYREG_CM0P_CCR 0xe000ed14 +#define CYFLD_CM0P_UNALIGN_TRP__OFFSET 0x00000003 +#define CYFLD_CM0P_UNALIGN_TRP__SIZE 0x00000001 +#define CYFLD_CM0P_STKALIGN__OFFSET 0x00000009 +#define CYFLD_CM0P_STKALIGN__SIZE 0x00000001 +#define CYREG_CM0P_SHPR2 0xe000ed1c +#define CYFLD_CM0P_PRI_11__OFFSET 0x0000001e +#define CYFLD_CM0P_PRI_11__SIZE 0x00000002 +#define CYREG_CM0P_SHPR3 0xe000ed20 +#define CYFLD_CM0P_PRI_14__OFFSET 0x00000016 +#define CYFLD_CM0P_PRI_14__SIZE 0x00000002 +#define CYFLD_CM0P_PRI_15__OFFSET 0x0000001e +#define CYFLD_CM0P_PRI_15__SIZE 0x00000002 +#define CYREG_CM0P_SHCSR 0xe000ed24 +#define CYFLD_CM0P_SVCALLPENDED__OFFSET 0x0000000f +#define CYFLD_CM0P_SVCALLPENDED__SIZE 0x00000001 +#define CYREG_CM0P_SCS_PID4 0xe000efd0 +#define CYREG_CM0P_SCS_PID0 0xe000efe0 +#define CYREG_CM0P_SCS_PID1 0xe000efe4 +#define CYREG_CM0P_SCS_PID2 0xe000efe8 +#define CYREG_CM0P_SCS_PID3 0xe000efec +#define CYREG_CM0P_SCS_CID0 0xe000eff0 +#define CYREG_CM0P_SCS_CID1 0xe000eff4 +#define CYREG_CM0P_SCS_CID2 0xe000eff8 +#define CYREG_CM0P_SCS_CID3 0xe000effc +#define CYREG_CM0P_ROM_SCS 0xe00ff000 +#define CYREG_CM0P_ROM_DWT 0xe00ff004 +#define CYREG_CM0P_ROM_BPU 0xe00ff008 +#define CYREG_CM0P_ROM_END 0xe00ff00c +#define CYREG_CM0P_ROM_CSMT 0xe00fffcc +#define CYREG_CM0P_ROM_PID4 0xe00fffd0 +#define CYREG_CM0P_ROM_PID0 0xe00fffe0 +#define CYREG_CM0P_ROM_PID1 0xe00fffe4 +#define CYREG_CM0P_ROM_PID2 0xe00fffe8 +#define CYREG_CM0P_ROM_PID3 0xe00fffec +#define CYREG_CM0P_ROM_CID0 0xe00ffff0 +#define CYREG_CM0P_ROM_CID1 0xe00ffff4 +#define CYREG_CM0P_ROM_CID2 0xe00ffff8 +#define CYREG_CM0P_ROM_CID3 0xe00ffffc +#define CYDEV_ROMTABLE_BASE 0xf0000000 +#define CYDEV_ROMTABLE_SIZE 0x00001000 +#define CYREG_ROMTABLE_ADDR 0xf0000000 +#define CYFLD_ROMTABLE_PRESENT__OFFSET 0x00000000 +#define CYFLD_ROMTABLE_PRESENT__SIZE 0x00000001 +#define CYFLD_ROMTABLE_FORMAT_32BIT__OFFSET 0x00000001 +#define CYFLD_ROMTABLE_FORMAT_32BIT__SIZE 0x00000001 +#define CYFLD_ROMTABLE_ADDR_OFFSET__OFFSET 0x0000000c +#define CYFLD_ROMTABLE_ADDR_OFFSET__SIZE 0x00000014 +#define CYREG_ROMTABLE_DID 0xf0000fcc +#define CYFLD_ROMTABLE_VALUE__OFFSET 0x00000000 +#define CYFLD_ROMTABLE_VALUE__SIZE 0x00000020 +#define CYREG_ROMTABLE_PID4 0xf0000fd0 +#define CYFLD_ROMTABLE_JEP_CONTINUATION__OFFSET 0x00000000 +#define CYFLD_ROMTABLE_JEP_CONTINUATION__SIZE 0x00000004 +#define CYFLD_ROMTABLE_COUNT__OFFSET 0x00000004 +#define CYFLD_ROMTABLE_COUNT__SIZE 0x00000004 +#define CYREG_ROMTABLE_PID5 0xf0000fd4 +#define CYREG_ROMTABLE_PID6 0xf0000fd8 +#define CYREG_ROMTABLE_PID7 0xf0000fdc +#define CYREG_ROMTABLE_PID0 0xf0000fe0 +#define CYFLD_ROMTABLE_PN_MIN__OFFSET 0x00000000 +#define CYFLD_ROMTABLE_PN_MIN__SIZE 0x00000008 +#define CYREG_ROMTABLE_PID1 0xf0000fe4 +#define CYFLD_ROMTABLE_PN_MAJ__OFFSET 0x00000000 +#define CYFLD_ROMTABLE_PN_MAJ__SIZE 0x00000004 +#define CYFLD_ROMTABLE_JEPID_MIN__OFFSET 0x00000004 +#define CYFLD_ROMTABLE_JEPID_MIN__SIZE 0x00000004 +#define CYREG_ROMTABLE_PID2 0xf0000fe8 +#define CYFLD_ROMTABLE_JEPID_MAJ__OFFSET 0x00000000 +#define CYFLD_ROMTABLE_JEPID_MAJ__SIZE 0x00000003 +#define CYFLD_ROMTABLE_REV__OFFSET 0x00000004 +#define CYFLD_ROMTABLE_REV__SIZE 0x00000004 +#define CYREG_ROMTABLE_PID3 0xf0000fec +#define CYFLD_ROMTABLE_CM__OFFSET 0x00000000 +#define CYFLD_ROMTABLE_CM__SIZE 0x00000004 +#define CYFLD_ROMTABLE_REV_AND__OFFSET 0x00000004 +#define CYFLD_ROMTABLE_REV_AND__SIZE 0x00000004 +#define CYREG_ROMTABLE_CID0 0xf0000ff0 +#define CYREG_ROMTABLE_CID1 0xf0000ff4 +#define CYREG_ROMTABLE_CID2 0xf0000ff8 +#define CYREG_ROMTABLE_CID3 0xf0000ffc +#define CYDEV_FLS_SECTOR_SIZE 0x00020000 +#define CYDEV_FLS_ROW_SIZE 0x00000100 diff --git a/cores/asr650x/projects/PSoC4/cydevicerv_trm.inc b/cores/asr650x/projects/PSoC4/cydevicerv_trm.inc new file mode 100644 index 00000000..b531904e --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cydevicerv_trm.inc @@ -0,0 +1,16441 @@ +; +; File Name: cydevicerv_trm.inc +; +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE +CYREG_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE +CYREG_FLASH_DATA_MSIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_SFLASH_BASE +CYDEV_SFLASH_BASE EQU 0x0ffff000 + ENDIF + IF :LNOT::DEF:CYDEV_SFLASH_SIZE +CYDEV_SFLASH_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW0 +CYREG_SFLASH_PROT_ROW0 EQU 0x0ffff000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA8__OFFSET +CYFLD_SFLASH_DATA8__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA8__SIZE +CYFLD_SFLASH_DATA8__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW1 +CYREG_SFLASH_PROT_ROW1 EQU 0x0ffff001 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW2 +CYREG_SFLASH_PROT_ROW2 EQU 0x0ffff002 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW3 +CYREG_SFLASH_PROT_ROW3 EQU 0x0ffff003 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW4 +CYREG_SFLASH_PROT_ROW4 EQU 0x0ffff004 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW5 +CYREG_SFLASH_PROT_ROW5 EQU 0x0ffff005 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW6 +CYREG_SFLASH_PROT_ROW6 EQU 0x0ffff006 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW7 +CYREG_SFLASH_PROT_ROW7 EQU 0x0ffff007 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW8 +CYREG_SFLASH_PROT_ROW8 EQU 0x0ffff008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW9 +CYREG_SFLASH_PROT_ROW9 EQU 0x0ffff009 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW10 +CYREG_SFLASH_PROT_ROW10 EQU 0x0ffff00a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW11 +CYREG_SFLASH_PROT_ROW11 EQU 0x0ffff00b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW12 +CYREG_SFLASH_PROT_ROW12 EQU 0x0ffff00c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW13 +CYREG_SFLASH_PROT_ROW13 EQU 0x0ffff00d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW14 +CYREG_SFLASH_PROT_ROW14 EQU 0x0ffff00e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW15 +CYREG_SFLASH_PROT_ROW15 EQU 0x0ffff00f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW16 +CYREG_SFLASH_PROT_ROW16 EQU 0x0ffff010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW17 +CYREG_SFLASH_PROT_ROW17 EQU 0x0ffff011 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW18 +CYREG_SFLASH_PROT_ROW18 EQU 0x0ffff012 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW19 +CYREG_SFLASH_PROT_ROW19 EQU 0x0ffff013 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW20 +CYREG_SFLASH_PROT_ROW20 EQU 0x0ffff014 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW21 +CYREG_SFLASH_PROT_ROW21 EQU 0x0ffff015 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW22 +CYREG_SFLASH_PROT_ROW22 EQU 0x0ffff016 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW23 +CYREG_SFLASH_PROT_ROW23 EQU 0x0ffff017 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW24 +CYREG_SFLASH_PROT_ROW24 EQU 0x0ffff018 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW25 +CYREG_SFLASH_PROT_ROW25 EQU 0x0ffff019 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW26 +CYREG_SFLASH_PROT_ROW26 EQU 0x0ffff01a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW27 +CYREG_SFLASH_PROT_ROW27 EQU 0x0ffff01b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW28 +CYREG_SFLASH_PROT_ROW28 EQU 0x0ffff01c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW29 +CYREG_SFLASH_PROT_ROW29 EQU 0x0ffff01d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW30 +CYREG_SFLASH_PROT_ROW30 EQU 0x0ffff01e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW31 +CYREG_SFLASH_PROT_ROW31 EQU 0x0ffff01f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW32 +CYREG_SFLASH_PROT_ROW32 EQU 0x0ffff020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW33 +CYREG_SFLASH_PROT_ROW33 EQU 0x0ffff021 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW34 +CYREG_SFLASH_PROT_ROW34 EQU 0x0ffff022 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW35 +CYREG_SFLASH_PROT_ROW35 EQU 0x0ffff023 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW36 +CYREG_SFLASH_PROT_ROW36 EQU 0x0ffff024 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW37 +CYREG_SFLASH_PROT_ROW37 EQU 0x0ffff025 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW38 +CYREG_SFLASH_PROT_ROW38 EQU 0x0ffff026 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW39 +CYREG_SFLASH_PROT_ROW39 EQU 0x0ffff027 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW40 +CYREG_SFLASH_PROT_ROW40 EQU 0x0ffff028 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW41 +CYREG_SFLASH_PROT_ROW41 EQU 0x0ffff029 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW42 +CYREG_SFLASH_PROT_ROW42 EQU 0x0ffff02a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW43 +CYREG_SFLASH_PROT_ROW43 EQU 0x0ffff02b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW44 +CYREG_SFLASH_PROT_ROW44 EQU 0x0ffff02c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW45 +CYREG_SFLASH_PROT_ROW45 EQU 0x0ffff02d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW46 +CYREG_SFLASH_PROT_ROW46 EQU 0x0ffff02e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW47 +CYREG_SFLASH_PROT_ROW47 EQU 0x0ffff02f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW48 +CYREG_SFLASH_PROT_ROW48 EQU 0x0ffff030 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW49 +CYREG_SFLASH_PROT_ROW49 EQU 0x0ffff031 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW50 +CYREG_SFLASH_PROT_ROW50 EQU 0x0ffff032 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW51 +CYREG_SFLASH_PROT_ROW51 EQU 0x0ffff033 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW52 +CYREG_SFLASH_PROT_ROW52 EQU 0x0ffff034 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW53 +CYREG_SFLASH_PROT_ROW53 EQU 0x0ffff035 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW54 +CYREG_SFLASH_PROT_ROW54 EQU 0x0ffff036 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW55 +CYREG_SFLASH_PROT_ROW55 EQU 0x0ffff037 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW56 +CYREG_SFLASH_PROT_ROW56 EQU 0x0ffff038 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW57 +CYREG_SFLASH_PROT_ROW57 EQU 0x0ffff039 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW58 +CYREG_SFLASH_PROT_ROW58 EQU 0x0ffff03a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW59 +CYREG_SFLASH_PROT_ROW59 EQU 0x0ffff03b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW60 +CYREG_SFLASH_PROT_ROW60 EQU 0x0ffff03c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW61 +CYREG_SFLASH_PROT_ROW61 EQU 0x0ffff03d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW62 +CYREG_SFLASH_PROT_ROW62 EQU 0x0ffff03e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW63 +CYREG_SFLASH_PROT_ROW63 EQU 0x0ffff03f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_PROTECTION +CYREG_SFLASH_PROT_PROTECTION EQU 0x0ffff0ff + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PROT_LEVEL__OFFSET +CYFLD_SFLASH_PROT_LEVEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_PROT_LEVEL__SIZE +CYFLD_SFLASH_PROT_LEVEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_VIRGIN +CYVAL_SFLASH_PROT_LEVEL_VIRGIN EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_OPEN +CYVAL_SFLASH_PROT_LEVEL_OPEN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_PROTECTED +CYVAL_SFLASH_PROT_LEVEL_PROTECTED EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SFLASH_PROT_LEVEL_KILL +CYVAL_SFLASH_PROT_LEVEL_KILL EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B0 +CYREG_SFLASH_AV_PAIRS_8B0 EQU 0x0ffff100 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B1 +CYREG_SFLASH_AV_PAIRS_8B1 EQU 0x0ffff101 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B2 +CYREG_SFLASH_AV_PAIRS_8B2 EQU 0x0ffff102 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B3 +CYREG_SFLASH_AV_PAIRS_8B3 EQU 0x0ffff103 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B4 +CYREG_SFLASH_AV_PAIRS_8B4 EQU 0x0ffff104 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B5 +CYREG_SFLASH_AV_PAIRS_8B5 EQU 0x0ffff105 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B6 +CYREG_SFLASH_AV_PAIRS_8B6 EQU 0x0ffff106 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B7 +CYREG_SFLASH_AV_PAIRS_8B7 EQU 0x0ffff107 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B8 +CYREG_SFLASH_AV_PAIRS_8B8 EQU 0x0ffff108 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B9 +CYREG_SFLASH_AV_PAIRS_8B9 EQU 0x0ffff109 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B10 +CYREG_SFLASH_AV_PAIRS_8B10 EQU 0x0ffff10a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B11 +CYREG_SFLASH_AV_PAIRS_8B11 EQU 0x0ffff10b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B12 +CYREG_SFLASH_AV_PAIRS_8B12 EQU 0x0ffff10c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B13 +CYREG_SFLASH_AV_PAIRS_8B13 EQU 0x0ffff10d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B14 +CYREG_SFLASH_AV_PAIRS_8B14 EQU 0x0ffff10e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B15 +CYREG_SFLASH_AV_PAIRS_8B15 EQU 0x0ffff10f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B16 +CYREG_SFLASH_AV_PAIRS_8B16 EQU 0x0ffff110 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B17 +CYREG_SFLASH_AV_PAIRS_8B17 EQU 0x0ffff111 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B18 +CYREG_SFLASH_AV_PAIRS_8B18 EQU 0x0ffff112 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B19 +CYREG_SFLASH_AV_PAIRS_8B19 EQU 0x0ffff113 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B20 +CYREG_SFLASH_AV_PAIRS_8B20 EQU 0x0ffff114 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B21 +CYREG_SFLASH_AV_PAIRS_8B21 EQU 0x0ffff115 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B22 +CYREG_SFLASH_AV_PAIRS_8B22 EQU 0x0ffff116 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B23 +CYREG_SFLASH_AV_PAIRS_8B23 EQU 0x0ffff117 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B24 +CYREG_SFLASH_AV_PAIRS_8B24 EQU 0x0ffff118 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B25 +CYREG_SFLASH_AV_PAIRS_8B25 EQU 0x0ffff119 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B26 +CYREG_SFLASH_AV_PAIRS_8B26 EQU 0x0ffff11a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B27 +CYREG_SFLASH_AV_PAIRS_8B27 EQU 0x0ffff11b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B28 +CYREG_SFLASH_AV_PAIRS_8B28 EQU 0x0ffff11c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B29 +CYREG_SFLASH_AV_PAIRS_8B29 EQU 0x0ffff11d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B30 +CYREG_SFLASH_AV_PAIRS_8B30 EQU 0x0ffff11e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B31 +CYREG_SFLASH_AV_PAIRS_8B31 EQU 0x0ffff11f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B32 +CYREG_SFLASH_AV_PAIRS_8B32 EQU 0x0ffff120 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B33 +CYREG_SFLASH_AV_PAIRS_8B33 EQU 0x0ffff121 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B34 +CYREG_SFLASH_AV_PAIRS_8B34 EQU 0x0ffff122 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B35 +CYREG_SFLASH_AV_PAIRS_8B35 EQU 0x0ffff123 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B36 +CYREG_SFLASH_AV_PAIRS_8B36 EQU 0x0ffff124 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B37 +CYREG_SFLASH_AV_PAIRS_8B37 EQU 0x0ffff125 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B38 +CYREG_SFLASH_AV_PAIRS_8B38 EQU 0x0ffff126 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B39 +CYREG_SFLASH_AV_PAIRS_8B39 EQU 0x0ffff127 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B40 +CYREG_SFLASH_AV_PAIRS_8B40 EQU 0x0ffff128 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B41 +CYREG_SFLASH_AV_PAIRS_8B41 EQU 0x0ffff129 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B42 +CYREG_SFLASH_AV_PAIRS_8B42 EQU 0x0ffff12a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B43 +CYREG_SFLASH_AV_PAIRS_8B43 EQU 0x0ffff12b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B44 +CYREG_SFLASH_AV_PAIRS_8B44 EQU 0x0ffff12c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B45 +CYREG_SFLASH_AV_PAIRS_8B45 EQU 0x0ffff12d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B46 +CYREG_SFLASH_AV_PAIRS_8B46 EQU 0x0ffff12e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B47 +CYREG_SFLASH_AV_PAIRS_8B47 EQU 0x0ffff12f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B48 +CYREG_SFLASH_AV_PAIRS_8B48 EQU 0x0ffff130 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B49 +CYREG_SFLASH_AV_PAIRS_8B49 EQU 0x0ffff131 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B50 +CYREG_SFLASH_AV_PAIRS_8B50 EQU 0x0ffff132 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B51 +CYREG_SFLASH_AV_PAIRS_8B51 EQU 0x0ffff133 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B52 +CYREG_SFLASH_AV_PAIRS_8B52 EQU 0x0ffff134 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B53 +CYREG_SFLASH_AV_PAIRS_8B53 EQU 0x0ffff135 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B54 +CYREG_SFLASH_AV_PAIRS_8B54 EQU 0x0ffff136 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B55 +CYREG_SFLASH_AV_PAIRS_8B55 EQU 0x0ffff137 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B56 +CYREG_SFLASH_AV_PAIRS_8B56 EQU 0x0ffff138 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B57 +CYREG_SFLASH_AV_PAIRS_8B57 EQU 0x0ffff139 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B58 +CYREG_SFLASH_AV_PAIRS_8B58 EQU 0x0ffff13a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B59 +CYREG_SFLASH_AV_PAIRS_8B59 EQU 0x0ffff13b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B60 +CYREG_SFLASH_AV_PAIRS_8B60 EQU 0x0ffff13c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B61 +CYREG_SFLASH_AV_PAIRS_8B61 EQU 0x0ffff13d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B62 +CYREG_SFLASH_AV_PAIRS_8B62 EQU 0x0ffff13e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B63 +CYREG_SFLASH_AV_PAIRS_8B63 EQU 0x0ffff13f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B64 +CYREG_SFLASH_AV_PAIRS_8B64 EQU 0x0ffff140 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B65 +CYREG_SFLASH_AV_PAIRS_8B65 EQU 0x0ffff141 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B66 +CYREG_SFLASH_AV_PAIRS_8B66 EQU 0x0ffff142 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B67 +CYREG_SFLASH_AV_PAIRS_8B67 EQU 0x0ffff143 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B68 +CYREG_SFLASH_AV_PAIRS_8B68 EQU 0x0ffff144 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B69 +CYREG_SFLASH_AV_PAIRS_8B69 EQU 0x0ffff145 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B70 +CYREG_SFLASH_AV_PAIRS_8B70 EQU 0x0ffff146 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B71 +CYREG_SFLASH_AV_PAIRS_8B71 EQU 0x0ffff147 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B72 +CYREG_SFLASH_AV_PAIRS_8B72 EQU 0x0ffff148 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B73 +CYREG_SFLASH_AV_PAIRS_8B73 EQU 0x0ffff149 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B74 +CYREG_SFLASH_AV_PAIRS_8B74 EQU 0x0ffff14a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B75 +CYREG_SFLASH_AV_PAIRS_8B75 EQU 0x0ffff14b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B76 +CYREG_SFLASH_AV_PAIRS_8B76 EQU 0x0ffff14c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B77 +CYREG_SFLASH_AV_PAIRS_8B77 EQU 0x0ffff14d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B78 +CYREG_SFLASH_AV_PAIRS_8B78 EQU 0x0ffff14e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B79 +CYREG_SFLASH_AV_PAIRS_8B79 EQU 0x0ffff14f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B80 +CYREG_SFLASH_AV_PAIRS_8B80 EQU 0x0ffff150 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B81 +CYREG_SFLASH_AV_PAIRS_8B81 EQU 0x0ffff151 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B82 +CYREG_SFLASH_AV_PAIRS_8B82 EQU 0x0ffff152 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B83 +CYREG_SFLASH_AV_PAIRS_8B83 EQU 0x0ffff153 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B84 +CYREG_SFLASH_AV_PAIRS_8B84 EQU 0x0ffff154 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B85 +CYREG_SFLASH_AV_PAIRS_8B85 EQU 0x0ffff155 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B86 +CYREG_SFLASH_AV_PAIRS_8B86 EQU 0x0ffff156 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B87 +CYREG_SFLASH_AV_PAIRS_8B87 EQU 0x0ffff157 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B88 +CYREG_SFLASH_AV_PAIRS_8B88 EQU 0x0ffff158 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B89 +CYREG_SFLASH_AV_PAIRS_8B89 EQU 0x0ffff159 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B90 +CYREG_SFLASH_AV_PAIRS_8B90 EQU 0x0ffff15a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B91 +CYREG_SFLASH_AV_PAIRS_8B91 EQU 0x0ffff15b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B92 +CYREG_SFLASH_AV_PAIRS_8B92 EQU 0x0ffff15c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B93 +CYREG_SFLASH_AV_PAIRS_8B93 EQU 0x0ffff15d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B94 +CYREG_SFLASH_AV_PAIRS_8B94 EQU 0x0ffff15e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B95 +CYREG_SFLASH_AV_PAIRS_8B95 EQU 0x0ffff15f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B96 +CYREG_SFLASH_AV_PAIRS_8B96 EQU 0x0ffff160 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B97 +CYREG_SFLASH_AV_PAIRS_8B97 EQU 0x0ffff161 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B98 +CYREG_SFLASH_AV_PAIRS_8B98 EQU 0x0ffff162 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B99 +CYREG_SFLASH_AV_PAIRS_8B99 EQU 0x0ffff163 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B100 +CYREG_SFLASH_AV_PAIRS_8B100 EQU 0x0ffff164 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B101 +CYREG_SFLASH_AV_PAIRS_8B101 EQU 0x0ffff165 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B102 +CYREG_SFLASH_AV_PAIRS_8B102 EQU 0x0ffff166 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B103 +CYREG_SFLASH_AV_PAIRS_8B103 EQU 0x0ffff167 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B104 +CYREG_SFLASH_AV_PAIRS_8B104 EQU 0x0ffff168 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B105 +CYREG_SFLASH_AV_PAIRS_8B105 EQU 0x0ffff169 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B106 +CYREG_SFLASH_AV_PAIRS_8B106 EQU 0x0ffff16a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B107 +CYREG_SFLASH_AV_PAIRS_8B107 EQU 0x0ffff16b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B108 +CYREG_SFLASH_AV_PAIRS_8B108 EQU 0x0ffff16c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B109 +CYREG_SFLASH_AV_PAIRS_8B109 EQU 0x0ffff16d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B110 +CYREG_SFLASH_AV_PAIRS_8B110 EQU 0x0ffff16e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B111 +CYREG_SFLASH_AV_PAIRS_8B111 EQU 0x0ffff16f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B112 +CYREG_SFLASH_AV_PAIRS_8B112 EQU 0x0ffff170 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B113 +CYREG_SFLASH_AV_PAIRS_8B113 EQU 0x0ffff171 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B114 +CYREG_SFLASH_AV_PAIRS_8B114 EQU 0x0ffff172 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B115 +CYREG_SFLASH_AV_PAIRS_8B115 EQU 0x0ffff173 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B116 +CYREG_SFLASH_AV_PAIRS_8B116 EQU 0x0ffff174 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B117 +CYREG_SFLASH_AV_PAIRS_8B117 EQU 0x0ffff175 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B118 +CYREG_SFLASH_AV_PAIRS_8B118 EQU 0x0ffff176 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B119 +CYREG_SFLASH_AV_PAIRS_8B119 EQU 0x0ffff177 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B120 +CYREG_SFLASH_AV_PAIRS_8B120 EQU 0x0ffff178 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B121 +CYREG_SFLASH_AV_PAIRS_8B121 EQU 0x0ffff179 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B122 +CYREG_SFLASH_AV_PAIRS_8B122 EQU 0x0ffff17a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B123 +CYREG_SFLASH_AV_PAIRS_8B123 EQU 0x0ffff17b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B124 +CYREG_SFLASH_AV_PAIRS_8B124 EQU 0x0ffff17c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B125 +CYREG_SFLASH_AV_PAIRS_8B125 EQU 0x0ffff17d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B126 +CYREG_SFLASH_AV_PAIRS_8B126 EQU 0x0ffff17e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B127 +CYREG_SFLASH_AV_PAIRS_8B127 EQU 0x0ffff17f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B0 +CYREG_SFLASH_AV_PAIRS_32B0 EQU 0x0ffff200 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA32__OFFSET +CYFLD_SFLASH_DATA32__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_DATA32__SIZE +CYFLD_SFLASH_DATA32__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B1 +CYREG_SFLASH_AV_PAIRS_32B1 EQU 0x0ffff204 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B2 +CYREG_SFLASH_AV_PAIRS_32B2 EQU 0x0ffff208 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B3 +CYREG_SFLASH_AV_PAIRS_32B3 EQU 0x0ffff20c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B4 +CYREG_SFLASH_AV_PAIRS_32B4 EQU 0x0ffff210 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B5 +CYREG_SFLASH_AV_PAIRS_32B5 EQU 0x0ffff214 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B6 +CYREG_SFLASH_AV_PAIRS_32B6 EQU 0x0ffff218 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B7 +CYREG_SFLASH_AV_PAIRS_32B7 EQU 0x0ffff21c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B8 +CYREG_SFLASH_AV_PAIRS_32B8 EQU 0x0ffff220 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B9 +CYREG_SFLASH_AV_PAIRS_32B9 EQU 0x0ffff224 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B10 +CYREG_SFLASH_AV_PAIRS_32B10 EQU 0x0ffff228 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B11 +CYREG_SFLASH_AV_PAIRS_32B11 EQU 0x0ffff22c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B12 +CYREG_SFLASH_AV_PAIRS_32B12 EQU 0x0ffff230 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B13 +CYREG_SFLASH_AV_PAIRS_32B13 EQU 0x0ffff234 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B14 +CYREG_SFLASH_AV_PAIRS_32B14 EQU 0x0ffff238 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B15 +CYREG_SFLASH_AV_PAIRS_32B15 EQU 0x0ffff23c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SILICON_ID +CYREG_SFLASH_SILICON_ID EQU 0x0ffff244 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ID__OFFSET +CYFLD_SFLASH_ID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ID__SIZE +CYFLD_SFLASH_ID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_HIB_KEY_DELAY +CYREG_SFLASH_HIB_KEY_DELAY EQU 0x0ffff250 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET +CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE +CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DPSLP_KEY_DELAY +CYREG_SFLASH_DPSLP_KEY_DELAY EQU 0x0ffff252 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SWD_CONFIG +CYREG_SFLASH_SWD_CONFIG EQU 0x0ffff254 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_SWD_SELECT__OFFSET +CYFLD_SFLASH_SWD_SELECT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_SWD_SELECT__SIZE +CYFLD_SFLASH_SWD_SELECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SWD_LISTEN +CYREG_SFLASH_SWD_LISTEN EQU 0x0ffff258 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CYCLES__OFFSET +CYFLD_SFLASH_CYCLES__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CYCLES__SIZE +CYFLD_SFLASH_CYCLES__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_FLASH_START +CYREG_SFLASH_FLASH_START EQU 0x0ffff25c + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ADDRESS__OFFSET +CYFLD_SFLASH_ADDRESS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ADDRESS__SIZE +CYFLD_SFLASH_ADDRESS__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM1 +CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM1 EQU 0x0ffff260 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CSD_ADC_CAL_LSB__OFFSET +CYFLD_SFLASH_CSD_ADC_CAL_LSB__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CSD_ADC_CAL_LSB__SIZE +CYFLD_SFLASH_CSD_ADC_CAL_LSB__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM2 +CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM2 EQU 0x0ffff261 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CSD_ADC_CAL_MSB__OFFSET +CYFLD_SFLASH_CSD_ADC_CAL_MSB__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CSD_ADC_CAL_MSB__SIZE +CYFLD_SFLASH_CSD_ADC_CAL_MSB__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SAR_TEMP_MULTIPLIER +CYREG_SFLASH_SAR_TEMP_MULTIPLIER EQU 0x0ffff264 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET +CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE +CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_SAR_TEMP_OFFSET +CYREG_SFLASH_SAR_TEMP_OFFSET EQU 0x0ffff266 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_OFFSET__OFFSET +CYFLD_SFLASH_TEMP_OFFSET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TEMP_OFFSET__SIZE +CYFLD_SFLASH_TEMP_OFFSET__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY0 +CYREG_SFLASH_PROT_VIRGINKEY0 EQU 0x0ffff270 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_KEY8__OFFSET +CYFLD_SFLASH_KEY8__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_KEY8__SIZE +CYFLD_SFLASH_KEY8__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY1 +CYREG_SFLASH_PROT_VIRGINKEY1 EQU 0x0ffff271 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY2 +CYREG_SFLASH_PROT_VIRGINKEY2 EQU 0x0ffff272 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY3 +CYREG_SFLASH_PROT_VIRGINKEY3 EQU 0x0ffff273 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY4 +CYREG_SFLASH_PROT_VIRGINKEY4 EQU 0x0ffff274 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY5 +CYREG_SFLASH_PROT_VIRGINKEY5 EQU 0x0ffff275 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY6 +CYREG_SFLASH_PROT_VIRGINKEY6 EQU 0x0ffff276 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY7 +CYREG_SFLASH_PROT_VIRGINKEY7 EQU 0x0ffff277 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT0 +CYREG_SFLASH_DIE_LOT0 EQU 0x0ffff278 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_LOT__OFFSET +CYFLD_SFLASH_LOT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_LOT__SIZE +CYFLD_SFLASH_LOT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT1 +CYREG_SFLASH_DIE_LOT1 EQU 0x0ffff279 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT2 +CYREG_SFLASH_DIE_LOT2 EQU 0x0ffff27a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_WAFER +CYREG_SFLASH_DIE_WAFER EQU 0x0ffff27b + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAFER__OFFSET +CYFLD_SFLASH_WAFER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_WAFER__SIZE +CYFLD_SFLASH_WAFER__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_X +CYREG_SFLASH_DIE_X EQU 0x0ffff27c + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_X__OFFSET +CYFLD_SFLASH_X__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_X__SIZE +CYFLD_SFLASH_X__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_Y +CYREG_SFLASH_DIE_Y EQU 0x0ffff27d + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_Y__OFFSET +CYFLD_SFLASH_Y__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_Y__SIZE +CYFLD_SFLASH_Y__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_SORT +CYREG_SFLASH_DIE_SORT EQU 0x0ffff27e + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S1_PASS__OFFSET +CYFLD_SFLASH_S1_PASS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S1_PASS__SIZE +CYFLD_SFLASH_S1_PASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S2_PASS__OFFSET +CYFLD_SFLASH_S2_PASS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S2_PASS__SIZE +CYFLD_SFLASH_S2_PASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S3_PASS__OFFSET +CYFLD_SFLASH_S3_PASS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_S3_PASS__SIZE +CYFLD_SFLASH_S3_PASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CRI_PASS__OFFSET +CYFLD_SFLASH_CRI_PASS__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CRI_PASS__SIZE +CYFLD_SFLASH_CRI_PASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CHI_PASS__OFFSET +CYFLD_SFLASH_CHI_PASS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_CHI_PASS__SIZE +CYFLD_SFLASH_CHI_PASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ENG_PASS__OFFSET +CYFLD_SFLASH_ENG_PASS__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_ENG_PASS__SIZE +CYFLD_SFLASH_ENG_PASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_DIE_MINOR +CYREG_SFLASH_DIE_MINOR EQU 0x0ffff27f + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MINOR__OFFSET +CYFLD_SFLASH_MINOR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_MINOR__SIZE +CYFLD_SFLASH_MINOR__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_USBMODE_24 +CYREG_SFLASH_IMO_TRIM_USBMODE_24 EQU 0x0ffff33e + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TRIM_24__OFFSET +CYFLD_SFLASH_TRIM_24__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TRIM_24__SIZE +CYFLD_SFLASH_TRIM_24__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_USBMODE_48 +CYREG_SFLASH_IMO_TRIM_USBMODE_48 EQU 0x0ffff33f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT0 +CYREG_SFLASH_IMO_TCTRIM_LT0 EQU 0x0ffff34c + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_STEPSIZE__OFFSET +CYFLD_SFLASH_STEPSIZE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_STEPSIZE__SIZE +CYFLD_SFLASH_STEPSIZE__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TCTRIM__OFFSET +CYFLD_SFLASH_TCTRIM__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_TCTRIM__SIZE +CYFLD_SFLASH_TCTRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT1 +CYREG_SFLASH_IMO_TCTRIM_LT1 EQU 0x0ffff34d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT2 +CYREG_SFLASH_IMO_TCTRIM_LT2 EQU 0x0ffff34e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT3 +CYREG_SFLASH_IMO_TCTRIM_LT3 EQU 0x0ffff34f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT4 +CYREG_SFLASH_IMO_TCTRIM_LT4 EQU 0x0ffff350 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT5 +CYREG_SFLASH_IMO_TCTRIM_LT5 EQU 0x0ffff351 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT6 +CYREG_SFLASH_IMO_TCTRIM_LT6 EQU 0x0ffff352 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT7 +CYREG_SFLASH_IMO_TCTRIM_LT7 EQU 0x0ffff353 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT8 +CYREG_SFLASH_IMO_TCTRIM_LT8 EQU 0x0ffff354 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT9 +CYREG_SFLASH_IMO_TCTRIM_LT9 EQU 0x0ffff355 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT10 +CYREG_SFLASH_IMO_TCTRIM_LT10 EQU 0x0ffff356 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT11 +CYREG_SFLASH_IMO_TCTRIM_LT11 EQU 0x0ffff357 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT12 +CYREG_SFLASH_IMO_TCTRIM_LT12 EQU 0x0ffff358 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT13 +CYREG_SFLASH_IMO_TCTRIM_LT13 EQU 0x0ffff359 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT14 +CYREG_SFLASH_IMO_TCTRIM_LT14 EQU 0x0ffff35a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT15 +CYREG_SFLASH_IMO_TCTRIM_LT15 EQU 0x0ffff35b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT16 +CYREG_SFLASH_IMO_TCTRIM_LT16 EQU 0x0ffff35c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT17 +CYREG_SFLASH_IMO_TCTRIM_LT17 EQU 0x0ffff35d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT18 +CYREG_SFLASH_IMO_TCTRIM_LT18 EQU 0x0ffff35e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT19 +CYREG_SFLASH_IMO_TCTRIM_LT19 EQU 0x0ffff35f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT20 +CYREG_SFLASH_IMO_TCTRIM_LT20 EQU 0x0ffff360 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT21 +CYREG_SFLASH_IMO_TCTRIM_LT21 EQU 0x0ffff361 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT22 +CYREG_SFLASH_IMO_TCTRIM_LT22 EQU 0x0ffff362 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT23 +CYREG_SFLASH_IMO_TCTRIM_LT23 EQU 0x0ffff363 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TCTRIM_LT24 +CYREG_SFLASH_IMO_TCTRIM_LT24 EQU 0x0ffff364 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT0 +CYREG_SFLASH_IMO_TRIM_LT0 EQU 0x0ffff365 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_OFFSET__OFFSET +CYFLD_SFLASH_OFFSET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_OFFSET__SIZE +CYFLD_SFLASH_OFFSET__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT1 +CYREG_SFLASH_IMO_TRIM_LT1 EQU 0x0ffff366 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT2 +CYREG_SFLASH_IMO_TRIM_LT2 EQU 0x0ffff367 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT3 +CYREG_SFLASH_IMO_TRIM_LT3 EQU 0x0ffff368 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT4 +CYREG_SFLASH_IMO_TRIM_LT4 EQU 0x0ffff369 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT5 +CYREG_SFLASH_IMO_TRIM_LT5 EQU 0x0ffff36a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT6 +CYREG_SFLASH_IMO_TRIM_LT6 EQU 0x0ffff36b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT7 +CYREG_SFLASH_IMO_TRIM_LT7 EQU 0x0ffff36c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT8 +CYREG_SFLASH_IMO_TRIM_LT8 EQU 0x0ffff36d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT9 +CYREG_SFLASH_IMO_TRIM_LT9 EQU 0x0ffff36e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT10 +CYREG_SFLASH_IMO_TRIM_LT10 EQU 0x0ffff36f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT11 +CYREG_SFLASH_IMO_TRIM_LT11 EQU 0x0ffff370 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT12 +CYREG_SFLASH_IMO_TRIM_LT12 EQU 0x0ffff371 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT13 +CYREG_SFLASH_IMO_TRIM_LT13 EQU 0x0ffff372 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT14 +CYREG_SFLASH_IMO_TRIM_LT14 EQU 0x0ffff373 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT15 +CYREG_SFLASH_IMO_TRIM_LT15 EQU 0x0ffff374 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT16 +CYREG_SFLASH_IMO_TRIM_LT16 EQU 0x0ffff375 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT17 +CYREG_SFLASH_IMO_TRIM_LT17 EQU 0x0ffff376 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT18 +CYREG_SFLASH_IMO_TRIM_LT18 EQU 0x0ffff377 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT19 +CYREG_SFLASH_IMO_TRIM_LT19 EQU 0x0ffff378 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT20 +CYREG_SFLASH_IMO_TRIM_LT20 EQU 0x0ffff379 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT21 +CYREG_SFLASH_IMO_TRIM_LT21 EQU 0x0ffff37a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT22 +CYREG_SFLASH_IMO_TRIM_LT22 EQU 0x0ffff37b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT23 +CYREG_SFLASH_IMO_TRIM_LT23 EQU 0x0ffff37c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_LT24 +CYREG_SFLASH_IMO_TRIM_LT24 EQU 0x0ffff37d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH0 EQU 0x0ffff400 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_BYTE_MEM__OFFSET +CYFLD_SFLASH_BYTE_MEM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SFLASH_BYTE_MEM__SIZE +CYFLD_SFLASH_BYTE_MEM__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1 EQU 0x0ffff401 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH2 EQU 0x0ffff402 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH3 EQU 0x0ffff403 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH4 EQU 0x0ffff404 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH5 EQU 0x0ffff405 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH6 EQU 0x0ffff406 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH7 EQU 0x0ffff407 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH8 EQU 0x0ffff408 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH9 EQU 0x0ffff409 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH10 +CYREG_SFLASH_MACRO_0_FREE_SFLASH10 EQU 0x0ffff40a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH11 +CYREG_SFLASH_MACRO_0_FREE_SFLASH11 EQU 0x0ffff40b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH12 +CYREG_SFLASH_MACRO_0_FREE_SFLASH12 EQU 0x0ffff40c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH13 +CYREG_SFLASH_MACRO_0_FREE_SFLASH13 EQU 0x0ffff40d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH14 +CYREG_SFLASH_MACRO_0_FREE_SFLASH14 EQU 0x0ffff40e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH15 +CYREG_SFLASH_MACRO_0_FREE_SFLASH15 EQU 0x0ffff40f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH16 +CYREG_SFLASH_MACRO_0_FREE_SFLASH16 EQU 0x0ffff410 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH17 +CYREG_SFLASH_MACRO_0_FREE_SFLASH17 EQU 0x0ffff411 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH18 +CYREG_SFLASH_MACRO_0_FREE_SFLASH18 EQU 0x0ffff412 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH19 +CYREG_SFLASH_MACRO_0_FREE_SFLASH19 EQU 0x0ffff413 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH20 +CYREG_SFLASH_MACRO_0_FREE_SFLASH20 EQU 0x0ffff414 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH21 +CYREG_SFLASH_MACRO_0_FREE_SFLASH21 EQU 0x0ffff415 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH22 +CYREG_SFLASH_MACRO_0_FREE_SFLASH22 EQU 0x0ffff416 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH23 +CYREG_SFLASH_MACRO_0_FREE_SFLASH23 EQU 0x0ffff417 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH24 +CYREG_SFLASH_MACRO_0_FREE_SFLASH24 EQU 0x0ffff418 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH25 +CYREG_SFLASH_MACRO_0_FREE_SFLASH25 EQU 0x0ffff419 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH26 +CYREG_SFLASH_MACRO_0_FREE_SFLASH26 EQU 0x0ffff41a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH27 +CYREG_SFLASH_MACRO_0_FREE_SFLASH27 EQU 0x0ffff41b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH28 +CYREG_SFLASH_MACRO_0_FREE_SFLASH28 EQU 0x0ffff41c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH29 +CYREG_SFLASH_MACRO_0_FREE_SFLASH29 EQU 0x0ffff41d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH30 +CYREG_SFLASH_MACRO_0_FREE_SFLASH30 EQU 0x0ffff41e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH31 +CYREG_SFLASH_MACRO_0_FREE_SFLASH31 EQU 0x0ffff41f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH32 +CYREG_SFLASH_MACRO_0_FREE_SFLASH32 EQU 0x0ffff420 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH33 +CYREG_SFLASH_MACRO_0_FREE_SFLASH33 EQU 0x0ffff421 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH34 +CYREG_SFLASH_MACRO_0_FREE_SFLASH34 EQU 0x0ffff422 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH35 +CYREG_SFLASH_MACRO_0_FREE_SFLASH35 EQU 0x0ffff423 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH36 +CYREG_SFLASH_MACRO_0_FREE_SFLASH36 EQU 0x0ffff424 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH37 +CYREG_SFLASH_MACRO_0_FREE_SFLASH37 EQU 0x0ffff425 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH38 +CYREG_SFLASH_MACRO_0_FREE_SFLASH38 EQU 0x0ffff426 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH39 +CYREG_SFLASH_MACRO_0_FREE_SFLASH39 EQU 0x0ffff427 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH40 +CYREG_SFLASH_MACRO_0_FREE_SFLASH40 EQU 0x0ffff428 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH41 +CYREG_SFLASH_MACRO_0_FREE_SFLASH41 EQU 0x0ffff429 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH42 +CYREG_SFLASH_MACRO_0_FREE_SFLASH42 EQU 0x0ffff42a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH43 +CYREG_SFLASH_MACRO_0_FREE_SFLASH43 EQU 0x0ffff42b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH44 +CYREG_SFLASH_MACRO_0_FREE_SFLASH44 EQU 0x0ffff42c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH45 +CYREG_SFLASH_MACRO_0_FREE_SFLASH45 EQU 0x0ffff42d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH46 +CYREG_SFLASH_MACRO_0_FREE_SFLASH46 EQU 0x0ffff42e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH47 +CYREG_SFLASH_MACRO_0_FREE_SFLASH47 EQU 0x0ffff42f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH48 +CYREG_SFLASH_MACRO_0_FREE_SFLASH48 EQU 0x0ffff430 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH49 +CYREG_SFLASH_MACRO_0_FREE_SFLASH49 EQU 0x0ffff431 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH50 +CYREG_SFLASH_MACRO_0_FREE_SFLASH50 EQU 0x0ffff432 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH51 +CYREG_SFLASH_MACRO_0_FREE_SFLASH51 EQU 0x0ffff433 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH52 +CYREG_SFLASH_MACRO_0_FREE_SFLASH52 EQU 0x0ffff434 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH53 +CYREG_SFLASH_MACRO_0_FREE_SFLASH53 EQU 0x0ffff435 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH54 +CYREG_SFLASH_MACRO_0_FREE_SFLASH54 EQU 0x0ffff436 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH55 +CYREG_SFLASH_MACRO_0_FREE_SFLASH55 EQU 0x0ffff437 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH56 +CYREG_SFLASH_MACRO_0_FREE_SFLASH56 EQU 0x0ffff438 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH57 +CYREG_SFLASH_MACRO_0_FREE_SFLASH57 EQU 0x0ffff439 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH58 +CYREG_SFLASH_MACRO_0_FREE_SFLASH58 EQU 0x0ffff43a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH59 +CYREG_SFLASH_MACRO_0_FREE_SFLASH59 EQU 0x0ffff43b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH60 +CYREG_SFLASH_MACRO_0_FREE_SFLASH60 EQU 0x0ffff43c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH61 +CYREG_SFLASH_MACRO_0_FREE_SFLASH61 EQU 0x0ffff43d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH62 +CYREG_SFLASH_MACRO_0_FREE_SFLASH62 EQU 0x0ffff43e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH63 +CYREG_SFLASH_MACRO_0_FREE_SFLASH63 EQU 0x0ffff43f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH64 +CYREG_SFLASH_MACRO_0_FREE_SFLASH64 EQU 0x0ffff440 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH65 +CYREG_SFLASH_MACRO_0_FREE_SFLASH65 EQU 0x0ffff441 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH66 +CYREG_SFLASH_MACRO_0_FREE_SFLASH66 EQU 0x0ffff442 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH67 +CYREG_SFLASH_MACRO_0_FREE_SFLASH67 EQU 0x0ffff443 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH68 +CYREG_SFLASH_MACRO_0_FREE_SFLASH68 EQU 0x0ffff444 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH69 +CYREG_SFLASH_MACRO_0_FREE_SFLASH69 EQU 0x0ffff445 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH70 +CYREG_SFLASH_MACRO_0_FREE_SFLASH70 EQU 0x0ffff446 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH71 +CYREG_SFLASH_MACRO_0_FREE_SFLASH71 EQU 0x0ffff447 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH72 +CYREG_SFLASH_MACRO_0_FREE_SFLASH72 EQU 0x0ffff448 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH73 +CYREG_SFLASH_MACRO_0_FREE_SFLASH73 EQU 0x0ffff449 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH74 +CYREG_SFLASH_MACRO_0_FREE_SFLASH74 EQU 0x0ffff44a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH75 +CYREG_SFLASH_MACRO_0_FREE_SFLASH75 EQU 0x0ffff44b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH76 +CYREG_SFLASH_MACRO_0_FREE_SFLASH76 EQU 0x0ffff44c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH77 +CYREG_SFLASH_MACRO_0_FREE_SFLASH77 EQU 0x0ffff44d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH78 +CYREG_SFLASH_MACRO_0_FREE_SFLASH78 EQU 0x0ffff44e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH79 +CYREG_SFLASH_MACRO_0_FREE_SFLASH79 EQU 0x0ffff44f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH80 +CYREG_SFLASH_MACRO_0_FREE_SFLASH80 EQU 0x0ffff450 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH81 +CYREG_SFLASH_MACRO_0_FREE_SFLASH81 EQU 0x0ffff451 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH82 +CYREG_SFLASH_MACRO_0_FREE_SFLASH82 EQU 0x0ffff452 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH83 +CYREG_SFLASH_MACRO_0_FREE_SFLASH83 EQU 0x0ffff453 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH84 +CYREG_SFLASH_MACRO_0_FREE_SFLASH84 EQU 0x0ffff454 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH85 +CYREG_SFLASH_MACRO_0_FREE_SFLASH85 EQU 0x0ffff455 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH86 +CYREG_SFLASH_MACRO_0_FREE_SFLASH86 EQU 0x0ffff456 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH87 +CYREG_SFLASH_MACRO_0_FREE_SFLASH87 EQU 0x0ffff457 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH88 +CYREG_SFLASH_MACRO_0_FREE_SFLASH88 EQU 0x0ffff458 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH89 +CYREG_SFLASH_MACRO_0_FREE_SFLASH89 EQU 0x0ffff459 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH90 +CYREG_SFLASH_MACRO_0_FREE_SFLASH90 EQU 0x0ffff45a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH91 +CYREG_SFLASH_MACRO_0_FREE_SFLASH91 EQU 0x0ffff45b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH92 +CYREG_SFLASH_MACRO_0_FREE_SFLASH92 EQU 0x0ffff45c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH93 +CYREG_SFLASH_MACRO_0_FREE_SFLASH93 EQU 0x0ffff45d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH94 +CYREG_SFLASH_MACRO_0_FREE_SFLASH94 EQU 0x0ffff45e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH95 +CYREG_SFLASH_MACRO_0_FREE_SFLASH95 EQU 0x0ffff45f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH96 +CYREG_SFLASH_MACRO_0_FREE_SFLASH96 EQU 0x0ffff460 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH97 +CYREG_SFLASH_MACRO_0_FREE_SFLASH97 EQU 0x0ffff461 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH98 +CYREG_SFLASH_MACRO_0_FREE_SFLASH98 EQU 0x0ffff462 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH99 +CYREG_SFLASH_MACRO_0_FREE_SFLASH99 EQU 0x0ffff463 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH100 +CYREG_SFLASH_MACRO_0_FREE_SFLASH100 EQU 0x0ffff464 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH101 +CYREG_SFLASH_MACRO_0_FREE_SFLASH101 EQU 0x0ffff465 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH102 +CYREG_SFLASH_MACRO_0_FREE_SFLASH102 EQU 0x0ffff466 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH103 +CYREG_SFLASH_MACRO_0_FREE_SFLASH103 EQU 0x0ffff467 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH104 +CYREG_SFLASH_MACRO_0_FREE_SFLASH104 EQU 0x0ffff468 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH105 +CYREG_SFLASH_MACRO_0_FREE_SFLASH105 EQU 0x0ffff469 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH106 +CYREG_SFLASH_MACRO_0_FREE_SFLASH106 EQU 0x0ffff46a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH107 +CYREG_SFLASH_MACRO_0_FREE_SFLASH107 EQU 0x0ffff46b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH108 +CYREG_SFLASH_MACRO_0_FREE_SFLASH108 EQU 0x0ffff46c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH109 +CYREG_SFLASH_MACRO_0_FREE_SFLASH109 EQU 0x0ffff46d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH110 +CYREG_SFLASH_MACRO_0_FREE_SFLASH110 EQU 0x0ffff46e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH111 +CYREG_SFLASH_MACRO_0_FREE_SFLASH111 EQU 0x0ffff46f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH112 +CYREG_SFLASH_MACRO_0_FREE_SFLASH112 EQU 0x0ffff470 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH113 +CYREG_SFLASH_MACRO_0_FREE_SFLASH113 EQU 0x0ffff471 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH114 +CYREG_SFLASH_MACRO_0_FREE_SFLASH114 EQU 0x0ffff472 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH115 +CYREG_SFLASH_MACRO_0_FREE_SFLASH115 EQU 0x0ffff473 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH116 +CYREG_SFLASH_MACRO_0_FREE_SFLASH116 EQU 0x0ffff474 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH117 +CYREG_SFLASH_MACRO_0_FREE_SFLASH117 EQU 0x0ffff475 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH118 +CYREG_SFLASH_MACRO_0_FREE_SFLASH118 EQU 0x0ffff476 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH119 +CYREG_SFLASH_MACRO_0_FREE_SFLASH119 EQU 0x0ffff477 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH120 +CYREG_SFLASH_MACRO_0_FREE_SFLASH120 EQU 0x0ffff478 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH121 +CYREG_SFLASH_MACRO_0_FREE_SFLASH121 EQU 0x0ffff479 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH122 +CYREG_SFLASH_MACRO_0_FREE_SFLASH122 EQU 0x0ffff47a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH123 +CYREG_SFLASH_MACRO_0_FREE_SFLASH123 EQU 0x0ffff47b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH124 +CYREG_SFLASH_MACRO_0_FREE_SFLASH124 EQU 0x0ffff47c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH125 +CYREG_SFLASH_MACRO_0_FREE_SFLASH125 EQU 0x0ffff47d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH126 +CYREG_SFLASH_MACRO_0_FREE_SFLASH126 EQU 0x0ffff47e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH127 +CYREG_SFLASH_MACRO_0_FREE_SFLASH127 EQU 0x0ffff47f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH128 +CYREG_SFLASH_MACRO_0_FREE_SFLASH128 EQU 0x0ffff480 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH129 +CYREG_SFLASH_MACRO_0_FREE_SFLASH129 EQU 0x0ffff481 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH130 +CYREG_SFLASH_MACRO_0_FREE_SFLASH130 EQU 0x0ffff482 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH131 +CYREG_SFLASH_MACRO_0_FREE_SFLASH131 EQU 0x0ffff483 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH132 +CYREG_SFLASH_MACRO_0_FREE_SFLASH132 EQU 0x0ffff484 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH133 +CYREG_SFLASH_MACRO_0_FREE_SFLASH133 EQU 0x0ffff485 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH134 +CYREG_SFLASH_MACRO_0_FREE_SFLASH134 EQU 0x0ffff486 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH135 +CYREG_SFLASH_MACRO_0_FREE_SFLASH135 EQU 0x0ffff487 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH136 +CYREG_SFLASH_MACRO_0_FREE_SFLASH136 EQU 0x0ffff488 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH137 +CYREG_SFLASH_MACRO_0_FREE_SFLASH137 EQU 0x0ffff489 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH138 +CYREG_SFLASH_MACRO_0_FREE_SFLASH138 EQU 0x0ffff48a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH139 +CYREG_SFLASH_MACRO_0_FREE_SFLASH139 EQU 0x0ffff48b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH140 +CYREG_SFLASH_MACRO_0_FREE_SFLASH140 EQU 0x0ffff48c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH141 +CYREG_SFLASH_MACRO_0_FREE_SFLASH141 EQU 0x0ffff48d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH142 +CYREG_SFLASH_MACRO_0_FREE_SFLASH142 EQU 0x0ffff48e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH143 +CYREG_SFLASH_MACRO_0_FREE_SFLASH143 EQU 0x0ffff48f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH144 +CYREG_SFLASH_MACRO_0_FREE_SFLASH144 EQU 0x0ffff490 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH145 +CYREG_SFLASH_MACRO_0_FREE_SFLASH145 EQU 0x0ffff491 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH146 +CYREG_SFLASH_MACRO_0_FREE_SFLASH146 EQU 0x0ffff492 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH147 +CYREG_SFLASH_MACRO_0_FREE_SFLASH147 EQU 0x0ffff493 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH148 +CYREG_SFLASH_MACRO_0_FREE_SFLASH148 EQU 0x0ffff494 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH149 +CYREG_SFLASH_MACRO_0_FREE_SFLASH149 EQU 0x0ffff495 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH150 +CYREG_SFLASH_MACRO_0_FREE_SFLASH150 EQU 0x0ffff496 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH151 +CYREG_SFLASH_MACRO_0_FREE_SFLASH151 EQU 0x0ffff497 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH152 +CYREG_SFLASH_MACRO_0_FREE_SFLASH152 EQU 0x0ffff498 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH153 +CYREG_SFLASH_MACRO_0_FREE_SFLASH153 EQU 0x0ffff499 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH154 +CYREG_SFLASH_MACRO_0_FREE_SFLASH154 EQU 0x0ffff49a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH155 +CYREG_SFLASH_MACRO_0_FREE_SFLASH155 EQU 0x0ffff49b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH156 +CYREG_SFLASH_MACRO_0_FREE_SFLASH156 EQU 0x0ffff49c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH157 +CYREG_SFLASH_MACRO_0_FREE_SFLASH157 EQU 0x0ffff49d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH158 +CYREG_SFLASH_MACRO_0_FREE_SFLASH158 EQU 0x0ffff49e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH159 +CYREG_SFLASH_MACRO_0_FREE_SFLASH159 EQU 0x0ffff49f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH160 +CYREG_SFLASH_MACRO_0_FREE_SFLASH160 EQU 0x0ffff4a0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH161 +CYREG_SFLASH_MACRO_0_FREE_SFLASH161 EQU 0x0ffff4a1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH162 +CYREG_SFLASH_MACRO_0_FREE_SFLASH162 EQU 0x0ffff4a2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH163 +CYREG_SFLASH_MACRO_0_FREE_SFLASH163 EQU 0x0ffff4a3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH164 +CYREG_SFLASH_MACRO_0_FREE_SFLASH164 EQU 0x0ffff4a4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH165 +CYREG_SFLASH_MACRO_0_FREE_SFLASH165 EQU 0x0ffff4a5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH166 +CYREG_SFLASH_MACRO_0_FREE_SFLASH166 EQU 0x0ffff4a6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH167 +CYREG_SFLASH_MACRO_0_FREE_SFLASH167 EQU 0x0ffff4a7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH168 +CYREG_SFLASH_MACRO_0_FREE_SFLASH168 EQU 0x0ffff4a8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH169 +CYREG_SFLASH_MACRO_0_FREE_SFLASH169 EQU 0x0ffff4a9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH170 +CYREG_SFLASH_MACRO_0_FREE_SFLASH170 EQU 0x0ffff4aa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH171 +CYREG_SFLASH_MACRO_0_FREE_SFLASH171 EQU 0x0ffff4ab + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH172 +CYREG_SFLASH_MACRO_0_FREE_SFLASH172 EQU 0x0ffff4ac + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH173 +CYREG_SFLASH_MACRO_0_FREE_SFLASH173 EQU 0x0ffff4ad + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH174 +CYREG_SFLASH_MACRO_0_FREE_SFLASH174 EQU 0x0ffff4ae + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH175 +CYREG_SFLASH_MACRO_0_FREE_SFLASH175 EQU 0x0ffff4af + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH176 +CYREG_SFLASH_MACRO_0_FREE_SFLASH176 EQU 0x0ffff4b0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH177 +CYREG_SFLASH_MACRO_0_FREE_SFLASH177 EQU 0x0ffff4b1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH178 +CYREG_SFLASH_MACRO_0_FREE_SFLASH178 EQU 0x0ffff4b2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH179 +CYREG_SFLASH_MACRO_0_FREE_SFLASH179 EQU 0x0ffff4b3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH180 +CYREG_SFLASH_MACRO_0_FREE_SFLASH180 EQU 0x0ffff4b4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH181 +CYREG_SFLASH_MACRO_0_FREE_SFLASH181 EQU 0x0ffff4b5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH182 +CYREG_SFLASH_MACRO_0_FREE_SFLASH182 EQU 0x0ffff4b6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH183 +CYREG_SFLASH_MACRO_0_FREE_SFLASH183 EQU 0x0ffff4b7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH184 +CYREG_SFLASH_MACRO_0_FREE_SFLASH184 EQU 0x0ffff4b8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH185 +CYREG_SFLASH_MACRO_0_FREE_SFLASH185 EQU 0x0ffff4b9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH186 +CYREG_SFLASH_MACRO_0_FREE_SFLASH186 EQU 0x0ffff4ba + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH187 +CYREG_SFLASH_MACRO_0_FREE_SFLASH187 EQU 0x0ffff4bb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH188 +CYREG_SFLASH_MACRO_0_FREE_SFLASH188 EQU 0x0ffff4bc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH189 +CYREG_SFLASH_MACRO_0_FREE_SFLASH189 EQU 0x0ffff4bd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH190 +CYREG_SFLASH_MACRO_0_FREE_SFLASH190 EQU 0x0ffff4be + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH191 +CYREG_SFLASH_MACRO_0_FREE_SFLASH191 EQU 0x0ffff4bf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH192 +CYREG_SFLASH_MACRO_0_FREE_SFLASH192 EQU 0x0ffff4c0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH193 +CYREG_SFLASH_MACRO_0_FREE_SFLASH193 EQU 0x0ffff4c1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH194 +CYREG_SFLASH_MACRO_0_FREE_SFLASH194 EQU 0x0ffff4c2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH195 +CYREG_SFLASH_MACRO_0_FREE_SFLASH195 EQU 0x0ffff4c3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH196 +CYREG_SFLASH_MACRO_0_FREE_SFLASH196 EQU 0x0ffff4c4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH197 +CYREG_SFLASH_MACRO_0_FREE_SFLASH197 EQU 0x0ffff4c5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH198 +CYREG_SFLASH_MACRO_0_FREE_SFLASH198 EQU 0x0ffff4c6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH199 +CYREG_SFLASH_MACRO_0_FREE_SFLASH199 EQU 0x0ffff4c7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH200 +CYREG_SFLASH_MACRO_0_FREE_SFLASH200 EQU 0x0ffff4c8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH201 +CYREG_SFLASH_MACRO_0_FREE_SFLASH201 EQU 0x0ffff4c9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH202 +CYREG_SFLASH_MACRO_0_FREE_SFLASH202 EQU 0x0ffff4ca + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH203 +CYREG_SFLASH_MACRO_0_FREE_SFLASH203 EQU 0x0ffff4cb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH204 +CYREG_SFLASH_MACRO_0_FREE_SFLASH204 EQU 0x0ffff4cc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH205 +CYREG_SFLASH_MACRO_0_FREE_SFLASH205 EQU 0x0ffff4cd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH206 +CYREG_SFLASH_MACRO_0_FREE_SFLASH206 EQU 0x0ffff4ce + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH207 +CYREG_SFLASH_MACRO_0_FREE_SFLASH207 EQU 0x0ffff4cf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH208 +CYREG_SFLASH_MACRO_0_FREE_SFLASH208 EQU 0x0ffff4d0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH209 +CYREG_SFLASH_MACRO_0_FREE_SFLASH209 EQU 0x0ffff4d1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH210 +CYREG_SFLASH_MACRO_0_FREE_SFLASH210 EQU 0x0ffff4d2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH211 +CYREG_SFLASH_MACRO_0_FREE_SFLASH211 EQU 0x0ffff4d3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH212 +CYREG_SFLASH_MACRO_0_FREE_SFLASH212 EQU 0x0ffff4d4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH213 +CYREG_SFLASH_MACRO_0_FREE_SFLASH213 EQU 0x0ffff4d5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH214 +CYREG_SFLASH_MACRO_0_FREE_SFLASH214 EQU 0x0ffff4d6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH215 +CYREG_SFLASH_MACRO_0_FREE_SFLASH215 EQU 0x0ffff4d7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH216 +CYREG_SFLASH_MACRO_0_FREE_SFLASH216 EQU 0x0ffff4d8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH217 +CYREG_SFLASH_MACRO_0_FREE_SFLASH217 EQU 0x0ffff4d9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH218 +CYREG_SFLASH_MACRO_0_FREE_SFLASH218 EQU 0x0ffff4da + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH219 +CYREG_SFLASH_MACRO_0_FREE_SFLASH219 EQU 0x0ffff4db + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH220 +CYREG_SFLASH_MACRO_0_FREE_SFLASH220 EQU 0x0ffff4dc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH221 +CYREG_SFLASH_MACRO_0_FREE_SFLASH221 EQU 0x0ffff4dd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH222 +CYREG_SFLASH_MACRO_0_FREE_SFLASH222 EQU 0x0ffff4de + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH223 +CYREG_SFLASH_MACRO_0_FREE_SFLASH223 EQU 0x0ffff4df + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH224 +CYREG_SFLASH_MACRO_0_FREE_SFLASH224 EQU 0x0ffff4e0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH225 +CYREG_SFLASH_MACRO_0_FREE_SFLASH225 EQU 0x0ffff4e1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH226 +CYREG_SFLASH_MACRO_0_FREE_SFLASH226 EQU 0x0ffff4e2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH227 +CYREG_SFLASH_MACRO_0_FREE_SFLASH227 EQU 0x0ffff4e3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH228 +CYREG_SFLASH_MACRO_0_FREE_SFLASH228 EQU 0x0ffff4e4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH229 +CYREG_SFLASH_MACRO_0_FREE_SFLASH229 EQU 0x0ffff4e5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH230 +CYREG_SFLASH_MACRO_0_FREE_SFLASH230 EQU 0x0ffff4e6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH231 +CYREG_SFLASH_MACRO_0_FREE_SFLASH231 EQU 0x0ffff4e7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH232 +CYREG_SFLASH_MACRO_0_FREE_SFLASH232 EQU 0x0ffff4e8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH233 +CYREG_SFLASH_MACRO_0_FREE_SFLASH233 EQU 0x0ffff4e9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH234 +CYREG_SFLASH_MACRO_0_FREE_SFLASH234 EQU 0x0ffff4ea + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH235 +CYREG_SFLASH_MACRO_0_FREE_SFLASH235 EQU 0x0ffff4eb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH236 +CYREG_SFLASH_MACRO_0_FREE_SFLASH236 EQU 0x0ffff4ec + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH237 +CYREG_SFLASH_MACRO_0_FREE_SFLASH237 EQU 0x0ffff4ed + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH238 +CYREG_SFLASH_MACRO_0_FREE_SFLASH238 EQU 0x0ffff4ee + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH239 +CYREG_SFLASH_MACRO_0_FREE_SFLASH239 EQU 0x0ffff4ef + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH240 +CYREG_SFLASH_MACRO_0_FREE_SFLASH240 EQU 0x0ffff4f0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH241 +CYREG_SFLASH_MACRO_0_FREE_SFLASH241 EQU 0x0ffff4f1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH242 +CYREG_SFLASH_MACRO_0_FREE_SFLASH242 EQU 0x0ffff4f2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH243 +CYREG_SFLASH_MACRO_0_FREE_SFLASH243 EQU 0x0ffff4f3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH244 +CYREG_SFLASH_MACRO_0_FREE_SFLASH244 EQU 0x0ffff4f4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH245 +CYREG_SFLASH_MACRO_0_FREE_SFLASH245 EQU 0x0ffff4f5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH246 +CYREG_SFLASH_MACRO_0_FREE_SFLASH246 EQU 0x0ffff4f6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH247 +CYREG_SFLASH_MACRO_0_FREE_SFLASH247 EQU 0x0ffff4f7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH248 +CYREG_SFLASH_MACRO_0_FREE_SFLASH248 EQU 0x0ffff4f8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH249 +CYREG_SFLASH_MACRO_0_FREE_SFLASH249 EQU 0x0ffff4f9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH250 +CYREG_SFLASH_MACRO_0_FREE_SFLASH250 EQU 0x0ffff4fa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH251 +CYREG_SFLASH_MACRO_0_FREE_SFLASH251 EQU 0x0ffff4fb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH252 +CYREG_SFLASH_MACRO_0_FREE_SFLASH252 EQU 0x0ffff4fc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH253 +CYREG_SFLASH_MACRO_0_FREE_SFLASH253 EQU 0x0ffff4fd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH254 +CYREG_SFLASH_MACRO_0_FREE_SFLASH254 EQU 0x0ffff4fe + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH255 +CYREG_SFLASH_MACRO_0_FREE_SFLASH255 EQU 0x0ffff4ff + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH256 +CYREG_SFLASH_MACRO_0_FREE_SFLASH256 EQU 0x0ffff500 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH257 +CYREG_SFLASH_MACRO_0_FREE_SFLASH257 EQU 0x0ffff501 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH258 +CYREG_SFLASH_MACRO_0_FREE_SFLASH258 EQU 0x0ffff502 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH259 +CYREG_SFLASH_MACRO_0_FREE_SFLASH259 EQU 0x0ffff503 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH260 +CYREG_SFLASH_MACRO_0_FREE_SFLASH260 EQU 0x0ffff504 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH261 +CYREG_SFLASH_MACRO_0_FREE_SFLASH261 EQU 0x0ffff505 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH262 +CYREG_SFLASH_MACRO_0_FREE_SFLASH262 EQU 0x0ffff506 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH263 +CYREG_SFLASH_MACRO_0_FREE_SFLASH263 EQU 0x0ffff507 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH264 +CYREG_SFLASH_MACRO_0_FREE_SFLASH264 EQU 0x0ffff508 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH265 +CYREG_SFLASH_MACRO_0_FREE_SFLASH265 EQU 0x0ffff509 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH266 +CYREG_SFLASH_MACRO_0_FREE_SFLASH266 EQU 0x0ffff50a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH267 +CYREG_SFLASH_MACRO_0_FREE_SFLASH267 EQU 0x0ffff50b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH268 +CYREG_SFLASH_MACRO_0_FREE_SFLASH268 EQU 0x0ffff50c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH269 +CYREG_SFLASH_MACRO_0_FREE_SFLASH269 EQU 0x0ffff50d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH270 +CYREG_SFLASH_MACRO_0_FREE_SFLASH270 EQU 0x0ffff50e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH271 +CYREG_SFLASH_MACRO_0_FREE_SFLASH271 EQU 0x0ffff50f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH272 +CYREG_SFLASH_MACRO_0_FREE_SFLASH272 EQU 0x0ffff510 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH273 +CYREG_SFLASH_MACRO_0_FREE_SFLASH273 EQU 0x0ffff511 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH274 +CYREG_SFLASH_MACRO_0_FREE_SFLASH274 EQU 0x0ffff512 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH275 +CYREG_SFLASH_MACRO_0_FREE_SFLASH275 EQU 0x0ffff513 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH276 +CYREG_SFLASH_MACRO_0_FREE_SFLASH276 EQU 0x0ffff514 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH277 +CYREG_SFLASH_MACRO_0_FREE_SFLASH277 EQU 0x0ffff515 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH278 +CYREG_SFLASH_MACRO_0_FREE_SFLASH278 EQU 0x0ffff516 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH279 +CYREG_SFLASH_MACRO_0_FREE_SFLASH279 EQU 0x0ffff517 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH280 +CYREG_SFLASH_MACRO_0_FREE_SFLASH280 EQU 0x0ffff518 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH281 +CYREG_SFLASH_MACRO_0_FREE_SFLASH281 EQU 0x0ffff519 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH282 +CYREG_SFLASH_MACRO_0_FREE_SFLASH282 EQU 0x0ffff51a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH283 +CYREG_SFLASH_MACRO_0_FREE_SFLASH283 EQU 0x0ffff51b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH284 +CYREG_SFLASH_MACRO_0_FREE_SFLASH284 EQU 0x0ffff51c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH285 +CYREG_SFLASH_MACRO_0_FREE_SFLASH285 EQU 0x0ffff51d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH286 +CYREG_SFLASH_MACRO_0_FREE_SFLASH286 EQU 0x0ffff51e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH287 +CYREG_SFLASH_MACRO_0_FREE_SFLASH287 EQU 0x0ffff51f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH288 +CYREG_SFLASH_MACRO_0_FREE_SFLASH288 EQU 0x0ffff520 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH289 +CYREG_SFLASH_MACRO_0_FREE_SFLASH289 EQU 0x0ffff521 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH290 +CYREG_SFLASH_MACRO_0_FREE_SFLASH290 EQU 0x0ffff522 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH291 +CYREG_SFLASH_MACRO_0_FREE_SFLASH291 EQU 0x0ffff523 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH292 +CYREG_SFLASH_MACRO_0_FREE_SFLASH292 EQU 0x0ffff524 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH293 +CYREG_SFLASH_MACRO_0_FREE_SFLASH293 EQU 0x0ffff525 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH294 +CYREG_SFLASH_MACRO_0_FREE_SFLASH294 EQU 0x0ffff526 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH295 +CYREG_SFLASH_MACRO_0_FREE_SFLASH295 EQU 0x0ffff527 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH296 +CYREG_SFLASH_MACRO_0_FREE_SFLASH296 EQU 0x0ffff528 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH297 +CYREG_SFLASH_MACRO_0_FREE_SFLASH297 EQU 0x0ffff529 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH298 +CYREG_SFLASH_MACRO_0_FREE_SFLASH298 EQU 0x0ffff52a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH299 +CYREG_SFLASH_MACRO_0_FREE_SFLASH299 EQU 0x0ffff52b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH300 +CYREG_SFLASH_MACRO_0_FREE_SFLASH300 EQU 0x0ffff52c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH301 +CYREG_SFLASH_MACRO_0_FREE_SFLASH301 EQU 0x0ffff52d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH302 +CYREG_SFLASH_MACRO_0_FREE_SFLASH302 EQU 0x0ffff52e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH303 +CYREG_SFLASH_MACRO_0_FREE_SFLASH303 EQU 0x0ffff52f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH304 +CYREG_SFLASH_MACRO_0_FREE_SFLASH304 EQU 0x0ffff530 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH305 +CYREG_SFLASH_MACRO_0_FREE_SFLASH305 EQU 0x0ffff531 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH306 +CYREG_SFLASH_MACRO_0_FREE_SFLASH306 EQU 0x0ffff532 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH307 +CYREG_SFLASH_MACRO_0_FREE_SFLASH307 EQU 0x0ffff533 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH308 +CYREG_SFLASH_MACRO_0_FREE_SFLASH308 EQU 0x0ffff534 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH309 +CYREG_SFLASH_MACRO_0_FREE_SFLASH309 EQU 0x0ffff535 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH310 +CYREG_SFLASH_MACRO_0_FREE_SFLASH310 EQU 0x0ffff536 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH311 +CYREG_SFLASH_MACRO_0_FREE_SFLASH311 EQU 0x0ffff537 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH312 +CYREG_SFLASH_MACRO_0_FREE_SFLASH312 EQU 0x0ffff538 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH313 +CYREG_SFLASH_MACRO_0_FREE_SFLASH313 EQU 0x0ffff539 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH314 +CYREG_SFLASH_MACRO_0_FREE_SFLASH314 EQU 0x0ffff53a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH315 +CYREG_SFLASH_MACRO_0_FREE_SFLASH315 EQU 0x0ffff53b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH316 +CYREG_SFLASH_MACRO_0_FREE_SFLASH316 EQU 0x0ffff53c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH317 +CYREG_SFLASH_MACRO_0_FREE_SFLASH317 EQU 0x0ffff53d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH318 +CYREG_SFLASH_MACRO_0_FREE_SFLASH318 EQU 0x0ffff53e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH319 +CYREG_SFLASH_MACRO_0_FREE_SFLASH319 EQU 0x0ffff53f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH320 +CYREG_SFLASH_MACRO_0_FREE_SFLASH320 EQU 0x0ffff540 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH321 +CYREG_SFLASH_MACRO_0_FREE_SFLASH321 EQU 0x0ffff541 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH322 +CYREG_SFLASH_MACRO_0_FREE_SFLASH322 EQU 0x0ffff542 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH323 +CYREG_SFLASH_MACRO_0_FREE_SFLASH323 EQU 0x0ffff543 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH324 +CYREG_SFLASH_MACRO_0_FREE_SFLASH324 EQU 0x0ffff544 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH325 +CYREG_SFLASH_MACRO_0_FREE_SFLASH325 EQU 0x0ffff545 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH326 +CYREG_SFLASH_MACRO_0_FREE_SFLASH326 EQU 0x0ffff546 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH327 +CYREG_SFLASH_MACRO_0_FREE_SFLASH327 EQU 0x0ffff547 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH328 +CYREG_SFLASH_MACRO_0_FREE_SFLASH328 EQU 0x0ffff548 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH329 +CYREG_SFLASH_MACRO_0_FREE_SFLASH329 EQU 0x0ffff549 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH330 +CYREG_SFLASH_MACRO_0_FREE_SFLASH330 EQU 0x0ffff54a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH331 +CYREG_SFLASH_MACRO_0_FREE_SFLASH331 EQU 0x0ffff54b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH332 +CYREG_SFLASH_MACRO_0_FREE_SFLASH332 EQU 0x0ffff54c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH333 +CYREG_SFLASH_MACRO_0_FREE_SFLASH333 EQU 0x0ffff54d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH334 +CYREG_SFLASH_MACRO_0_FREE_SFLASH334 EQU 0x0ffff54e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH335 +CYREG_SFLASH_MACRO_0_FREE_SFLASH335 EQU 0x0ffff54f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH336 +CYREG_SFLASH_MACRO_0_FREE_SFLASH336 EQU 0x0ffff550 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH337 +CYREG_SFLASH_MACRO_0_FREE_SFLASH337 EQU 0x0ffff551 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH338 +CYREG_SFLASH_MACRO_0_FREE_SFLASH338 EQU 0x0ffff552 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH339 +CYREG_SFLASH_MACRO_0_FREE_SFLASH339 EQU 0x0ffff553 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH340 +CYREG_SFLASH_MACRO_0_FREE_SFLASH340 EQU 0x0ffff554 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH341 +CYREG_SFLASH_MACRO_0_FREE_SFLASH341 EQU 0x0ffff555 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH342 +CYREG_SFLASH_MACRO_0_FREE_SFLASH342 EQU 0x0ffff556 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH343 +CYREG_SFLASH_MACRO_0_FREE_SFLASH343 EQU 0x0ffff557 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH344 +CYREG_SFLASH_MACRO_0_FREE_SFLASH344 EQU 0x0ffff558 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH345 +CYREG_SFLASH_MACRO_0_FREE_SFLASH345 EQU 0x0ffff559 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH346 +CYREG_SFLASH_MACRO_0_FREE_SFLASH346 EQU 0x0ffff55a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH347 +CYREG_SFLASH_MACRO_0_FREE_SFLASH347 EQU 0x0ffff55b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH348 +CYREG_SFLASH_MACRO_0_FREE_SFLASH348 EQU 0x0ffff55c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH349 +CYREG_SFLASH_MACRO_0_FREE_SFLASH349 EQU 0x0ffff55d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH350 +CYREG_SFLASH_MACRO_0_FREE_SFLASH350 EQU 0x0ffff55e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH351 +CYREG_SFLASH_MACRO_0_FREE_SFLASH351 EQU 0x0ffff55f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH352 +CYREG_SFLASH_MACRO_0_FREE_SFLASH352 EQU 0x0ffff560 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH353 +CYREG_SFLASH_MACRO_0_FREE_SFLASH353 EQU 0x0ffff561 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH354 +CYREG_SFLASH_MACRO_0_FREE_SFLASH354 EQU 0x0ffff562 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH355 +CYREG_SFLASH_MACRO_0_FREE_SFLASH355 EQU 0x0ffff563 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH356 +CYREG_SFLASH_MACRO_0_FREE_SFLASH356 EQU 0x0ffff564 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH357 +CYREG_SFLASH_MACRO_0_FREE_SFLASH357 EQU 0x0ffff565 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH358 +CYREG_SFLASH_MACRO_0_FREE_SFLASH358 EQU 0x0ffff566 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH359 +CYREG_SFLASH_MACRO_0_FREE_SFLASH359 EQU 0x0ffff567 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH360 +CYREG_SFLASH_MACRO_0_FREE_SFLASH360 EQU 0x0ffff568 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH361 +CYREG_SFLASH_MACRO_0_FREE_SFLASH361 EQU 0x0ffff569 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH362 +CYREG_SFLASH_MACRO_0_FREE_SFLASH362 EQU 0x0ffff56a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH363 +CYREG_SFLASH_MACRO_0_FREE_SFLASH363 EQU 0x0ffff56b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH364 +CYREG_SFLASH_MACRO_0_FREE_SFLASH364 EQU 0x0ffff56c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH365 +CYREG_SFLASH_MACRO_0_FREE_SFLASH365 EQU 0x0ffff56d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH366 +CYREG_SFLASH_MACRO_0_FREE_SFLASH366 EQU 0x0ffff56e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH367 +CYREG_SFLASH_MACRO_0_FREE_SFLASH367 EQU 0x0ffff56f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH368 +CYREG_SFLASH_MACRO_0_FREE_SFLASH368 EQU 0x0ffff570 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH369 +CYREG_SFLASH_MACRO_0_FREE_SFLASH369 EQU 0x0ffff571 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH370 +CYREG_SFLASH_MACRO_0_FREE_SFLASH370 EQU 0x0ffff572 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH371 +CYREG_SFLASH_MACRO_0_FREE_SFLASH371 EQU 0x0ffff573 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH372 +CYREG_SFLASH_MACRO_0_FREE_SFLASH372 EQU 0x0ffff574 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH373 +CYREG_SFLASH_MACRO_0_FREE_SFLASH373 EQU 0x0ffff575 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH374 +CYREG_SFLASH_MACRO_0_FREE_SFLASH374 EQU 0x0ffff576 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH375 +CYREG_SFLASH_MACRO_0_FREE_SFLASH375 EQU 0x0ffff577 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH376 +CYREG_SFLASH_MACRO_0_FREE_SFLASH376 EQU 0x0ffff578 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH377 +CYREG_SFLASH_MACRO_0_FREE_SFLASH377 EQU 0x0ffff579 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH378 +CYREG_SFLASH_MACRO_0_FREE_SFLASH378 EQU 0x0ffff57a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH379 +CYREG_SFLASH_MACRO_0_FREE_SFLASH379 EQU 0x0ffff57b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH380 +CYREG_SFLASH_MACRO_0_FREE_SFLASH380 EQU 0x0ffff57c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH381 +CYREG_SFLASH_MACRO_0_FREE_SFLASH381 EQU 0x0ffff57d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH382 +CYREG_SFLASH_MACRO_0_FREE_SFLASH382 EQU 0x0ffff57e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH383 +CYREG_SFLASH_MACRO_0_FREE_SFLASH383 EQU 0x0ffff57f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH384 +CYREG_SFLASH_MACRO_0_FREE_SFLASH384 EQU 0x0ffff580 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH385 +CYREG_SFLASH_MACRO_0_FREE_SFLASH385 EQU 0x0ffff581 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH386 +CYREG_SFLASH_MACRO_0_FREE_SFLASH386 EQU 0x0ffff582 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH387 +CYREG_SFLASH_MACRO_0_FREE_SFLASH387 EQU 0x0ffff583 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH388 +CYREG_SFLASH_MACRO_0_FREE_SFLASH388 EQU 0x0ffff584 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH389 +CYREG_SFLASH_MACRO_0_FREE_SFLASH389 EQU 0x0ffff585 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH390 +CYREG_SFLASH_MACRO_0_FREE_SFLASH390 EQU 0x0ffff586 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH391 +CYREG_SFLASH_MACRO_0_FREE_SFLASH391 EQU 0x0ffff587 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH392 +CYREG_SFLASH_MACRO_0_FREE_SFLASH392 EQU 0x0ffff588 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH393 +CYREG_SFLASH_MACRO_0_FREE_SFLASH393 EQU 0x0ffff589 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH394 +CYREG_SFLASH_MACRO_0_FREE_SFLASH394 EQU 0x0ffff58a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH395 +CYREG_SFLASH_MACRO_0_FREE_SFLASH395 EQU 0x0ffff58b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH396 +CYREG_SFLASH_MACRO_0_FREE_SFLASH396 EQU 0x0ffff58c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH397 +CYREG_SFLASH_MACRO_0_FREE_SFLASH397 EQU 0x0ffff58d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH398 +CYREG_SFLASH_MACRO_0_FREE_SFLASH398 EQU 0x0ffff58e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH399 +CYREG_SFLASH_MACRO_0_FREE_SFLASH399 EQU 0x0ffff58f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH400 +CYREG_SFLASH_MACRO_0_FREE_SFLASH400 EQU 0x0ffff590 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH401 +CYREG_SFLASH_MACRO_0_FREE_SFLASH401 EQU 0x0ffff591 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH402 +CYREG_SFLASH_MACRO_0_FREE_SFLASH402 EQU 0x0ffff592 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH403 +CYREG_SFLASH_MACRO_0_FREE_SFLASH403 EQU 0x0ffff593 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH404 +CYREG_SFLASH_MACRO_0_FREE_SFLASH404 EQU 0x0ffff594 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH405 +CYREG_SFLASH_MACRO_0_FREE_SFLASH405 EQU 0x0ffff595 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH406 +CYREG_SFLASH_MACRO_0_FREE_SFLASH406 EQU 0x0ffff596 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH407 +CYREG_SFLASH_MACRO_0_FREE_SFLASH407 EQU 0x0ffff597 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH408 +CYREG_SFLASH_MACRO_0_FREE_SFLASH408 EQU 0x0ffff598 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH409 +CYREG_SFLASH_MACRO_0_FREE_SFLASH409 EQU 0x0ffff599 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH410 +CYREG_SFLASH_MACRO_0_FREE_SFLASH410 EQU 0x0ffff59a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH411 +CYREG_SFLASH_MACRO_0_FREE_SFLASH411 EQU 0x0ffff59b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH412 +CYREG_SFLASH_MACRO_0_FREE_SFLASH412 EQU 0x0ffff59c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH413 +CYREG_SFLASH_MACRO_0_FREE_SFLASH413 EQU 0x0ffff59d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH414 +CYREG_SFLASH_MACRO_0_FREE_SFLASH414 EQU 0x0ffff59e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH415 +CYREG_SFLASH_MACRO_0_FREE_SFLASH415 EQU 0x0ffff59f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH416 +CYREG_SFLASH_MACRO_0_FREE_SFLASH416 EQU 0x0ffff5a0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH417 +CYREG_SFLASH_MACRO_0_FREE_SFLASH417 EQU 0x0ffff5a1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH418 +CYREG_SFLASH_MACRO_0_FREE_SFLASH418 EQU 0x0ffff5a2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH419 +CYREG_SFLASH_MACRO_0_FREE_SFLASH419 EQU 0x0ffff5a3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH420 +CYREG_SFLASH_MACRO_0_FREE_SFLASH420 EQU 0x0ffff5a4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH421 +CYREG_SFLASH_MACRO_0_FREE_SFLASH421 EQU 0x0ffff5a5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH422 +CYREG_SFLASH_MACRO_0_FREE_SFLASH422 EQU 0x0ffff5a6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH423 +CYREG_SFLASH_MACRO_0_FREE_SFLASH423 EQU 0x0ffff5a7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH424 +CYREG_SFLASH_MACRO_0_FREE_SFLASH424 EQU 0x0ffff5a8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH425 +CYREG_SFLASH_MACRO_0_FREE_SFLASH425 EQU 0x0ffff5a9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH426 +CYREG_SFLASH_MACRO_0_FREE_SFLASH426 EQU 0x0ffff5aa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH427 +CYREG_SFLASH_MACRO_0_FREE_SFLASH427 EQU 0x0ffff5ab + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH428 +CYREG_SFLASH_MACRO_0_FREE_SFLASH428 EQU 0x0ffff5ac + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH429 +CYREG_SFLASH_MACRO_0_FREE_SFLASH429 EQU 0x0ffff5ad + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH430 +CYREG_SFLASH_MACRO_0_FREE_SFLASH430 EQU 0x0ffff5ae + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH431 +CYREG_SFLASH_MACRO_0_FREE_SFLASH431 EQU 0x0ffff5af + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH432 +CYREG_SFLASH_MACRO_0_FREE_SFLASH432 EQU 0x0ffff5b0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH433 +CYREG_SFLASH_MACRO_0_FREE_SFLASH433 EQU 0x0ffff5b1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH434 +CYREG_SFLASH_MACRO_0_FREE_SFLASH434 EQU 0x0ffff5b2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH435 +CYREG_SFLASH_MACRO_0_FREE_SFLASH435 EQU 0x0ffff5b3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH436 +CYREG_SFLASH_MACRO_0_FREE_SFLASH436 EQU 0x0ffff5b4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH437 +CYREG_SFLASH_MACRO_0_FREE_SFLASH437 EQU 0x0ffff5b5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH438 +CYREG_SFLASH_MACRO_0_FREE_SFLASH438 EQU 0x0ffff5b6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH439 +CYREG_SFLASH_MACRO_0_FREE_SFLASH439 EQU 0x0ffff5b7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH440 +CYREG_SFLASH_MACRO_0_FREE_SFLASH440 EQU 0x0ffff5b8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH441 +CYREG_SFLASH_MACRO_0_FREE_SFLASH441 EQU 0x0ffff5b9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH442 +CYREG_SFLASH_MACRO_0_FREE_SFLASH442 EQU 0x0ffff5ba + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH443 +CYREG_SFLASH_MACRO_0_FREE_SFLASH443 EQU 0x0ffff5bb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH444 +CYREG_SFLASH_MACRO_0_FREE_SFLASH444 EQU 0x0ffff5bc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH445 +CYREG_SFLASH_MACRO_0_FREE_SFLASH445 EQU 0x0ffff5bd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH446 +CYREG_SFLASH_MACRO_0_FREE_SFLASH446 EQU 0x0ffff5be + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH447 +CYREG_SFLASH_MACRO_0_FREE_SFLASH447 EQU 0x0ffff5bf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH448 +CYREG_SFLASH_MACRO_0_FREE_SFLASH448 EQU 0x0ffff5c0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH449 +CYREG_SFLASH_MACRO_0_FREE_SFLASH449 EQU 0x0ffff5c1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH450 +CYREG_SFLASH_MACRO_0_FREE_SFLASH450 EQU 0x0ffff5c2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH451 +CYREG_SFLASH_MACRO_0_FREE_SFLASH451 EQU 0x0ffff5c3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH452 +CYREG_SFLASH_MACRO_0_FREE_SFLASH452 EQU 0x0ffff5c4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH453 +CYREG_SFLASH_MACRO_0_FREE_SFLASH453 EQU 0x0ffff5c5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH454 +CYREG_SFLASH_MACRO_0_FREE_SFLASH454 EQU 0x0ffff5c6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH455 +CYREG_SFLASH_MACRO_0_FREE_SFLASH455 EQU 0x0ffff5c7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH456 +CYREG_SFLASH_MACRO_0_FREE_SFLASH456 EQU 0x0ffff5c8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH457 +CYREG_SFLASH_MACRO_0_FREE_SFLASH457 EQU 0x0ffff5c9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH458 +CYREG_SFLASH_MACRO_0_FREE_SFLASH458 EQU 0x0ffff5ca + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH459 +CYREG_SFLASH_MACRO_0_FREE_SFLASH459 EQU 0x0ffff5cb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH460 +CYREG_SFLASH_MACRO_0_FREE_SFLASH460 EQU 0x0ffff5cc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH461 +CYREG_SFLASH_MACRO_0_FREE_SFLASH461 EQU 0x0ffff5cd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH462 +CYREG_SFLASH_MACRO_0_FREE_SFLASH462 EQU 0x0ffff5ce + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH463 +CYREG_SFLASH_MACRO_0_FREE_SFLASH463 EQU 0x0ffff5cf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH464 +CYREG_SFLASH_MACRO_0_FREE_SFLASH464 EQU 0x0ffff5d0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH465 +CYREG_SFLASH_MACRO_0_FREE_SFLASH465 EQU 0x0ffff5d1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH466 +CYREG_SFLASH_MACRO_0_FREE_SFLASH466 EQU 0x0ffff5d2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH467 +CYREG_SFLASH_MACRO_0_FREE_SFLASH467 EQU 0x0ffff5d3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH468 +CYREG_SFLASH_MACRO_0_FREE_SFLASH468 EQU 0x0ffff5d4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH469 +CYREG_SFLASH_MACRO_0_FREE_SFLASH469 EQU 0x0ffff5d5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH470 +CYREG_SFLASH_MACRO_0_FREE_SFLASH470 EQU 0x0ffff5d6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH471 +CYREG_SFLASH_MACRO_0_FREE_SFLASH471 EQU 0x0ffff5d7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH472 +CYREG_SFLASH_MACRO_0_FREE_SFLASH472 EQU 0x0ffff5d8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH473 +CYREG_SFLASH_MACRO_0_FREE_SFLASH473 EQU 0x0ffff5d9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH474 +CYREG_SFLASH_MACRO_0_FREE_SFLASH474 EQU 0x0ffff5da + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH475 +CYREG_SFLASH_MACRO_0_FREE_SFLASH475 EQU 0x0ffff5db + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH476 +CYREG_SFLASH_MACRO_0_FREE_SFLASH476 EQU 0x0ffff5dc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH477 +CYREG_SFLASH_MACRO_0_FREE_SFLASH477 EQU 0x0ffff5dd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH478 +CYREG_SFLASH_MACRO_0_FREE_SFLASH478 EQU 0x0ffff5de + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH479 +CYREG_SFLASH_MACRO_0_FREE_SFLASH479 EQU 0x0ffff5df + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH480 +CYREG_SFLASH_MACRO_0_FREE_SFLASH480 EQU 0x0ffff5e0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH481 +CYREG_SFLASH_MACRO_0_FREE_SFLASH481 EQU 0x0ffff5e1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH482 +CYREG_SFLASH_MACRO_0_FREE_SFLASH482 EQU 0x0ffff5e2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH483 +CYREG_SFLASH_MACRO_0_FREE_SFLASH483 EQU 0x0ffff5e3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH484 +CYREG_SFLASH_MACRO_0_FREE_SFLASH484 EQU 0x0ffff5e4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH485 +CYREG_SFLASH_MACRO_0_FREE_SFLASH485 EQU 0x0ffff5e5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH486 +CYREG_SFLASH_MACRO_0_FREE_SFLASH486 EQU 0x0ffff5e6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH487 +CYREG_SFLASH_MACRO_0_FREE_SFLASH487 EQU 0x0ffff5e7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH488 +CYREG_SFLASH_MACRO_0_FREE_SFLASH488 EQU 0x0ffff5e8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH489 +CYREG_SFLASH_MACRO_0_FREE_SFLASH489 EQU 0x0ffff5e9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH490 +CYREG_SFLASH_MACRO_0_FREE_SFLASH490 EQU 0x0ffff5ea + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH491 +CYREG_SFLASH_MACRO_0_FREE_SFLASH491 EQU 0x0ffff5eb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH492 +CYREG_SFLASH_MACRO_0_FREE_SFLASH492 EQU 0x0ffff5ec + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH493 +CYREG_SFLASH_MACRO_0_FREE_SFLASH493 EQU 0x0ffff5ed + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH494 +CYREG_SFLASH_MACRO_0_FREE_SFLASH494 EQU 0x0ffff5ee + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH495 +CYREG_SFLASH_MACRO_0_FREE_SFLASH495 EQU 0x0ffff5ef + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH496 +CYREG_SFLASH_MACRO_0_FREE_SFLASH496 EQU 0x0ffff5f0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH497 +CYREG_SFLASH_MACRO_0_FREE_SFLASH497 EQU 0x0ffff5f1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH498 +CYREG_SFLASH_MACRO_0_FREE_SFLASH498 EQU 0x0ffff5f2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH499 +CYREG_SFLASH_MACRO_0_FREE_SFLASH499 EQU 0x0ffff5f3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH500 +CYREG_SFLASH_MACRO_0_FREE_SFLASH500 EQU 0x0ffff5f4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH501 +CYREG_SFLASH_MACRO_0_FREE_SFLASH501 EQU 0x0ffff5f5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH502 +CYREG_SFLASH_MACRO_0_FREE_SFLASH502 EQU 0x0ffff5f6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH503 +CYREG_SFLASH_MACRO_0_FREE_SFLASH503 EQU 0x0ffff5f7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH504 +CYREG_SFLASH_MACRO_0_FREE_SFLASH504 EQU 0x0ffff5f8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH505 +CYREG_SFLASH_MACRO_0_FREE_SFLASH505 EQU 0x0ffff5f9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH506 +CYREG_SFLASH_MACRO_0_FREE_SFLASH506 EQU 0x0ffff5fa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH507 +CYREG_SFLASH_MACRO_0_FREE_SFLASH507 EQU 0x0ffff5fb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH508 +CYREG_SFLASH_MACRO_0_FREE_SFLASH508 EQU 0x0ffff5fc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH509 +CYREG_SFLASH_MACRO_0_FREE_SFLASH509 EQU 0x0ffff5fd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH510 +CYREG_SFLASH_MACRO_0_FREE_SFLASH510 EQU 0x0ffff5fe + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH511 +CYREG_SFLASH_MACRO_0_FREE_SFLASH511 EQU 0x0ffff5ff + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH512 +CYREG_SFLASH_MACRO_0_FREE_SFLASH512 EQU 0x0ffff600 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH513 +CYREG_SFLASH_MACRO_0_FREE_SFLASH513 EQU 0x0ffff601 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH514 +CYREG_SFLASH_MACRO_0_FREE_SFLASH514 EQU 0x0ffff602 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH515 +CYREG_SFLASH_MACRO_0_FREE_SFLASH515 EQU 0x0ffff603 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH516 +CYREG_SFLASH_MACRO_0_FREE_SFLASH516 EQU 0x0ffff604 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH517 +CYREG_SFLASH_MACRO_0_FREE_SFLASH517 EQU 0x0ffff605 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH518 +CYREG_SFLASH_MACRO_0_FREE_SFLASH518 EQU 0x0ffff606 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH519 +CYREG_SFLASH_MACRO_0_FREE_SFLASH519 EQU 0x0ffff607 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH520 +CYREG_SFLASH_MACRO_0_FREE_SFLASH520 EQU 0x0ffff608 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH521 +CYREG_SFLASH_MACRO_0_FREE_SFLASH521 EQU 0x0ffff609 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH522 +CYREG_SFLASH_MACRO_0_FREE_SFLASH522 EQU 0x0ffff60a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH523 +CYREG_SFLASH_MACRO_0_FREE_SFLASH523 EQU 0x0ffff60b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH524 +CYREG_SFLASH_MACRO_0_FREE_SFLASH524 EQU 0x0ffff60c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH525 +CYREG_SFLASH_MACRO_0_FREE_SFLASH525 EQU 0x0ffff60d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH526 +CYREG_SFLASH_MACRO_0_FREE_SFLASH526 EQU 0x0ffff60e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH527 +CYREG_SFLASH_MACRO_0_FREE_SFLASH527 EQU 0x0ffff60f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH528 +CYREG_SFLASH_MACRO_0_FREE_SFLASH528 EQU 0x0ffff610 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH529 +CYREG_SFLASH_MACRO_0_FREE_SFLASH529 EQU 0x0ffff611 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH530 +CYREG_SFLASH_MACRO_0_FREE_SFLASH530 EQU 0x0ffff612 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH531 +CYREG_SFLASH_MACRO_0_FREE_SFLASH531 EQU 0x0ffff613 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH532 +CYREG_SFLASH_MACRO_0_FREE_SFLASH532 EQU 0x0ffff614 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH533 +CYREG_SFLASH_MACRO_0_FREE_SFLASH533 EQU 0x0ffff615 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH534 +CYREG_SFLASH_MACRO_0_FREE_SFLASH534 EQU 0x0ffff616 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH535 +CYREG_SFLASH_MACRO_0_FREE_SFLASH535 EQU 0x0ffff617 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH536 +CYREG_SFLASH_MACRO_0_FREE_SFLASH536 EQU 0x0ffff618 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH537 +CYREG_SFLASH_MACRO_0_FREE_SFLASH537 EQU 0x0ffff619 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH538 +CYREG_SFLASH_MACRO_0_FREE_SFLASH538 EQU 0x0ffff61a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH539 +CYREG_SFLASH_MACRO_0_FREE_SFLASH539 EQU 0x0ffff61b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH540 +CYREG_SFLASH_MACRO_0_FREE_SFLASH540 EQU 0x0ffff61c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH541 +CYREG_SFLASH_MACRO_0_FREE_SFLASH541 EQU 0x0ffff61d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH542 +CYREG_SFLASH_MACRO_0_FREE_SFLASH542 EQU 0x0ffff61e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH543 +CYREG_SFLASH_MACRO_0_FREE_SFLASH543 EQU 0x0ffff61f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH544 +CYREG_SFLASH_MACRO_0_FREE_SFLASH544 EQU 0x0ffff620 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH545 +CYREG_SFLASH_MACRO_0_FREE_SFLASH545 EQU 0x0ffff621 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH546 +CYREG_SFLASH_MACRO_0_FREE_SFLASH546 EQU 0x0ffff622 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH547 +CYREG_SFLASH_MACRO_0_FREE_SFLASH547 EQU 0x0ffff623 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH548 +CYREG_SFLASH_MACRO_0_FREE_SFLASH548 EQU 0x0ffff624 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH549 +CYREG_SFLASH_MACRO_0_FREE_SFLASH549 EQU 0x0ffff625 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH550 +CYREG_SFLASH_MACRO_0_FREE_SFLASH550 EQU 0x0ffff626 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH551 +CYREG_SFLASH_MACRO_0_FREE_SFLASH551 EQU 0x0ffff627 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH552 +CYREG_SFLASH_MACRO_0_FREE_SFLASH552 EQU 0x0ffff628 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH553 +CYREG_SFLASH_MACRO_0_FREE_SFLASH553 EQU 0x0ffff629 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH554 +CYREG_SFLASH_MACRO_0_FREE_SFLASH554 EQU 0x0ffff62a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH555 +CYREG_SFLASH_MACRO_0_FREE_SFLASH555 EQU 0x0ffff62b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH556 +CYREG_SFLASH_MACRO_0_FREE_SFLASH556 EQU 0x0ffff62c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH557 +CYREG_SFLASH_MACRO_0_FREE_SFLASH557 EQU 0x0ffff62d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH558 +CYREG_SFLASH_MACRO_0_FREE_SFLASH558 EQU 0x0ffff62e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH559 +CYREG_SFLASH_MACRO_0_FREE_SFLASH559 EQU 0x0ffff62f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH560 +CYREG_SFLASH_MACRO_0_FREE_SFLASH560 EQU 0x0ffff630 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH561 +CYREG_SFLASH_MACRO_0_FREE_SFLASH561 EQU 0x0ffff631 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH562 +CYREG_SFLASH_MACRO_0_FREE_SFLASH562 EQU 0x0ffff632 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH563 +CYREG_SFLASH_MACRO_0_FREE_SFLASH563 EQU 0x0ffff633 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH564 +CYREG_SFLASH_MACRO_0_FREE_SFLASH564 EQU 0x0ffff634 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH565 +CYREG_SFLASH_MACRO_0_FREE_SFLASH565 EQU 0x0ffff635 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH566 +CYREG_SFLASH_MACRO_0_FREE_SFLASH566 EQU 0x0ffff636 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH567 +CYREG_SFLASH_MACRO_0_FREE_SFLASH567 EQU 0x0ffff637 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH568 +CYREG_SFLASH_MACRO_0_FREE_SFLASH568 EQU 0x0ffff638 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH569 +CYREG_SFLASH_MACRO_0_FREE_SFLASH569 EQU 0x0ffff639 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH570 +CYREG_SFLASH_MACRO_0_FREE_SFLASH570 EQU 0x0ffff63a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH571 +CYREG_SFLASH_MACRO_0_FREE_SFLASH571 EQU 0x0ffff63b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH572 +CYREG_SFLASH_MACRO_0_FREE_SFLASH572 EQU 0x0ffff63c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH573 +CYREG_SFLASH_MACRO_0_FREE_SFLASH573 EQU 0x0ffff63d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH574 +CYREG_SFLASH_MACRO_0_FREE_SFLASH574 EQU 0x0ffff63e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH575 +CYREG_SFLASH_MACRO_0_FREE_SFLASH575 EQU 0x0ffff63f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH576 +CYREG_SFLASH_MACRO_0_FREE_SFLASH576 EQU 0x0ffff640 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH577 +CYREG_SFLASH_MACRO_0_FREE_SFLASH577 EQU 0x0ffff641 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH578 +CYREG_SFLASH_MACRO_0_FREE_SFLASH578 EQU 0x0ffff642 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH579 +CYREG_SFLASH_MACRO_0_FREE_SFLASH579 EQU 0x0ffff643 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH580 +CYREG_SFLASH_MACRO_0_FREE_SFLASH580 EQU 0x0ffff644 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH581 +CYREG_SFLASH_MACRO_0_FREE_SFLASH581 EQU 0x0ffff645 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH582 +CYREG_SFLASH_MACRO_0_FREE_SFLASH582 EQU 0x0ffff646 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH583 +CYREG_SFLASH_MACRO_0_FREE_SFLASH583 EQU 0x0ffff647 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH584 +CYREG_SFLASH_MACRO_0_FREE_SFLASH584 EQU 0x0ffff648 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH585 +CYREG_SFLASH_MACRO_0_FREE_SFLASH585 EQU 0x0ffff649 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH586 +CYREG_SFLASH_MACRO_0_FREE_SFLASH586 EQU 0x0ffff64a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH587 +CYREG_SFLASH_MACRO_0_FREE_SFLASH587 EQU 0x0ffff64b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH588 +CYREG_SFLASH_MACRO_0_FREE_SFLASH588 EQU 0x0ffff64c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH589 +CYREG_SFLASH_MACRO_0_FREE_SFLASH589 EQU 0x0ffff64d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH590 +CYREG_SFLASH_MACRO_0_FREE_SFLASH590 EQU 0x0ffff64e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH591 +CYREG_SFLASH_MACRO_0_FREE_SFLASH591 EQU 0x0ffff64f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH592 +CYREG_SFLASH_MACRO_0_FREE_SFLASH592 EQU 0x0ffff650 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH593 +CYREG_SFLASH_MACRO_0_FREE_SFLASH593 EQU 0x0ffff651 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH594 +CYREG_SFLASH_MACRO_0_FREE_SFLASH594 EQU 0x0ffff652 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH595 +CYREG_SFLASH_MACRO_0_FREE_SFLASH595 EQU 0x0ffff653 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH596 +CYREG_SFLASH_MACRO_0_FREE_SFLASH596 EQU 0x0ffff654 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH597 +CYREG_SFLASH_MACRO_0_FREE_SFLASH597 EQU 0x0ffff655 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH598 +CYREG_SFLASH_MACRO_0_FREE_SFLASH598 EQU 0x0ffff656 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH599 +CYREG_SFLASH_MACRO_0_FREE_SFLASH599 EQU 0x0ffff657 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH600 +CYREG_SFLASH_MACRO_0_FREE_SFLASH600 EQU 0x0ffff658 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH601 +CYREG_SFLASH_MACRO_0_FREE_SFLASH601 EQU 0x0ffff659 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH602 +CYREG_SFLASH_MACRO_0_FREE_SFLASH602 EQU 0x0ffff65a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH603 +CYREG_SFLASH_MACRO_0_FREE_SFLASH603 EQU 0x0ffff65b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH604 +CYREG_SFLASH_MACRO_0_FREE_SFLASH604 EQU 0x0ffff65c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH605 +CYREG_SFLASH_MACRO_0_FREE_SFLASH605 EQU 0x0ffff65d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH606 +CYREG_SFLASH_MACRO_0_FREE_SFLASH606 EQU 0x0ffff65e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH607 +CYREG_SFLASH_MACRO_0_FREE_SFLASH607 EQU 0x0ffff65f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH608 +CYREG_SFLASH_MACRO_0_FREE_SFLASH608 EQU 0x0ffff660 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH609 +CYREG_SFLASH_MACRO_0_FREE_SFLASH609 EQU 0x0ffff661 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH610 +CYREG_SFLASH_MACRO_0_FREE_SFLASH610 EQU 0x0ffff662 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH611 +CYREG_SFLASH_MACRO_0_FREE_SFLASH611 EQU 0x0ffff663 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH612 +CYREG_SFLASH_MACRO_0_FREE_SFLASH612 EQU 0x0ffff664 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH613 +CYREG_SFLASH_MACRO_0_FREE_SFLASH613 EQU 0x0ffff665 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH614 +CYREG_SFLASH_MACRO_0_FREE_SFLASH614 EQU 0x0ffff666 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH615 +CYREG_SFLASH_MACRO_0_FREE_SFLASH615 EQU 0x0ffff667 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH616 +CYREG_SFLASH_MACRO_0_FREE_SFLASH616 EQU 0x0ffff668 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH617 +CYREG_SFLASH_MACRO_0_FREE_SFLASH617 EQU 0x0ffff669 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH618 +CYREG_SFLASH_MACRO_0_FREE_SFLASH618 EQU 0x0ffff66a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH619 +CYREG_SFLASH_MACRO_0_FREE_SFLASH619 EQU 0x0ffff66b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH620 +CYREG_SFLASH_MACRO_0_FREE_SFLASH620 EQU 0x0ffff66c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH621 +CYREG_SFLASH_MACRO_0_FREE_SFLASH621 EQU 0x0ffff66d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH622 +CYREG_SFLASH_MACRO_0_FREE_SFLASH622 EQU 0x0ffff66e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH623 +CYREG_SFLASH_MACRO_0_FREE_SFLASH623 EQU 0x0ffff66f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH624 +CYREG_SFLASH_MACRO_0_FREE_SFLASH624 EQU 0x0ffff670 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH625 +CYREG_SFLASH_MACRO_0_FREE_SFLASH625 EQU 0x0ffff671 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH626 +CYREG_SFLASH_MACRO_0_FREE_SFLASH626 EQU 0x0ffff672 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH627 +CYREG_SFLASH_MACRO_0_FREE_SFLASH627 EQU 0x0ffff673 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH628 +CYREG_SFLASH_MACRO_0_FREE_SFLASH628 EQU 0x0ffff674 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH629 +CYREG_SFLASH_MACRO_0_FREE_SFLASH629 EQU 0x0ffff675 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH630 +CYREG_SFLASH_MACRO_0_FREE_SFLASH630 EQU 0x0ffff676 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH631 +CYREG_SFLASH_MACRO_0_FREE_SFLASH631 EQU 0x0ffff677 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH632 +CYREG_SFLASH_MACRO_0_FREE_SFLASH632 EQU 0x0ffff678 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH633 +CYREG_SFLASH_MACRO_0_FREE_SFLASH633 EQU 0x0ffff679 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH634 +CYREG_SFLASH_MACRO_0_FREE_SFLASH634 EQU 0x0ffff67a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH635 +CYREG_SFLASH_MACRO_0_FREE_SFLASH635 EQU 0x0ffff67b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH636 +CYREG_SFLASH_MACRO_0_FREE_SFLASH636 EQU 0x0ffff67c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH637 +CYREG_SFLASH_MACRO_0_FREE_SFLASH637 EQU 0x0ffff67d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH638 +CYREG_SFLASH_MACRO_0_FREE_SFLASH638 EQU 0x0ffff67e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH639 +CYREG_SFLASH_MACRO_0_FREE_SFLASH639 EQU 0x0ffff67f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH640 +CYREG_SFLASH_MACRO_0_FREE_SFLASH640 EQU 0x0ffff680 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH641 +CYREG_SFLASH_MACRO_0_FREE_SFLASH641 EQU 0x0ffff681 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH642 +CYREG_SFLASH_MACRO_0_FREE_SFLASH642 EQU 0x0ffff682 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH643 +CYREG_SFLASH_MACRO_0_FREE_SFLASH643 EQU 0x0ffff683 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH644 +CYREG_SFLASH_MACRO_0_FREE_SFLASH644 EQU 0x0ffff684 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH645 +CYREG_SFLASH_MACRO_0_FREE_SFLASH645 EQU 0x0ffff685 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH646 +CYREG_SFLASH_MACRO_0_FREE_SFLASH646 EQU 0x0ffff686 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH647 +CYREG_SFLASH_MACRO_0_FREE_SFLASH647 EQU 0x0ffff687 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH648 +CYREG_SFLASH_MACRO_0_FREE_SFLASH648 EQU 0x0ffff688 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH649 +CYREG_SFLASH_MACRO_0_FREE_SFLASH649 EQU 0x0ffff689 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH650 +CYREG_SFLASH_MACRO_0_FREE_SFLASH650 EQU 0x0ffff68a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH651 +CYREG_SFLASH_MACRO_0_FREE_SFLASH651 EQU 0x0ffff68b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH652 +CYREG_SFLASH_MACRO_0_FREE_SFLASH652 EQU 0x0ffff68c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH653 +CYREG_SFLASH_MACRO_0_FREE_SFLASH653 EQU 0x0ffff68d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH654 +CYREG_SFLASH_MACRO_0_FREE_SFLASH654 EQU 0x0ffff68e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH655 +CYREG_SFLASH_MACRO_0_FREE_SFLASH655 EQU 0x0ffff68f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH656 +CYREG_SFLASH_MACRO_0_FREE_SFLASH656 EQU 0x0ffff690 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH657 +CYREG_SFLASH_MACRO_0_FREE_SFLASH657 EQU 0x0ffff691 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH658 +CYREG_SFLASH_MACRO_0_FREE_SFLASH658 EQU 0x0ffff692 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH659 +CYREG_SFLASH_MACRO_0_FREE_SFLASH659 EQU 0x0ffff693 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH660 +CYREG_SFLASH_MACRO_0_FREE_SFLASH660 EQU 0x0ffff694 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH661 +CYREG_SFLASH_MACRO_0_FREE_SFLASH661 EQU 0x0ffff695 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH662 +CYREG_SFLASH_MACRO_0_FREE_SFLASH662 EQU 0x0ffff696 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH663 +CYREG_SFLASH_MACRO_0_FREE_SFLASH663 EQU 0x0ffff697 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH664 +CYREG_SFLASH_MACRO_0_FREE_SFLASH664 EQU 0x0ffff698 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH665 +CYREG_SFLASH_MACRO_0_FREE_SFLASH665 EQU 0x0ffff699 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH666 +CYREG_SFLASH_MACRO_0_FREE_SFLASH666 EQU 0x0ffff69a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH667 +CYREG_SFLASH_MACRO_0_FREE_SFLASH667 EQU 0x0ffff69b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH668 +CYREG_SFLASH_MACRO_0_FREE_SFLASH668 EQU 0x0ffff69c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH669 +CYREG_SFLASH_MACRO_0_FREE_SFLASH669 EQU 0x0ffff69d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH670 +CYREG_SFLASH_MACRO_0_FREE_SFLASH670 EQU 0x0ffff69e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH671 +CYREG_SFLASH_MACRO_0_FREE_SFLASH671 EQU 0x0ffff69f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH672 +CYREG_SFLASH_MACRO_0_FREE_SFLASH672 EQU 0x0ffff6a0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH673 +CYREG_SFLASH_MACRO_0_FREE_SFLASH673 EQU 0x0ffff6a1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH674 +CYREG_SFLASH_MACRO_0_FREE_SFLASH674 EQU 0x0ffff6a2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH675 +CYREG_SFLASH_MACRO_0_FREE_SFLASH675 EQU 0x0ffff6a3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH676 +CYREG_SFLASH_MACRO_0_FREE_SFLASH676 EQU 0x0ffff6a4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH677 +CYREG_SFLASH_MACRO_0_FREE_SFLASH677 EQU 0x0ffff6a5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH678 +CYREG_SFLASH_MACRO_0_FREE_SFLASH678 EQU 0x0ffff6a6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH679 +CYREG_SFLASH_MACRO_0_FREE_SFLASH679 EQU 0x0ffff6a7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH680 +CYREG_SFLASH_MACRO_0_FREE_SFLASH680 EQU 0x0ffff6a8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH681 +CYREG_SFLASH_MACRO_0_FREE_SFLASH681 EQU 0x0ffff6a9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH682 +CYREG_SFLASH_MACRO_0_FREE_SFLASH682 EQU 0x0ffff6aa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH683 +CYREG_SFLASH_MACRO_0_FREE_SFLASH683 EQU 0x0ffff6ab + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH684 +CYREG_SFLASH_MACRO_0_FREE_SFLASH684 EQU 0x0ffff6ac + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH685 +CYREG_SFLASH_MACRO_0_FREE_SFLASH685 EQU 0x0ffff6ad + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH686 +CYREG_SFLASH_MACRO_0_FREE_SFLASH686 EQU 0x0ffff6ae + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH687 +CYREG_SFLASH_MACRO_0_FREE_SFLASH687 EQU 0x0ffff6af + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH688 +CYREG_SFLASH_MACRO_0_FREE_SFLASH688 EQU 0x0ffff6b0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH689 +CYREG_SFLASH_MACRO_0_FREE_SFLASH689 EQU 0x0ffff6b1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH690 +CYREG_SFLASH_MACRO_0_FREE_SFLASH690 EQU 0x0ffff6b2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH691 +CYREG_SFLASH_MACRO_0_FREE_SFLASH691 EQU 0x0ffff6b3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH692 +CYREG_SFLASH_MACRO_0_FREE_SFLASH692 EQU 0x0ffff6b4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH693 +CYREG_SFLASH_MACRO_0_FREE_SFLASH693 EQU 0x0ffff6b5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH694 +CYREG_SFLASH_MACRO_0_FREE_SFLASH694 EQU 0x0ffff6b6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH695 +CYREG_SFLASH_MACRO_0_FREE_SFLASH695 EQU 0x0ffff6b7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH696 +CYREG_SFLASH_MACRO_0_FREE_SFLASH696 EQU 0x0ffff6b8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH697 +CYREG_SFLASH_MACRO_0_FREE_SFLASH697 EQU 0x0ffff6b9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH698 +CYREG_SFLASH_MACRO_0_FREE_SFLASH698 EQU 0x0ffff6ba + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH699 +CYREG_SFLASH_MACRO_0_FREE_SFLASH699 EQU 0x0ffff6bb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH700 +CYREG_SFLASH_MACRO_0_FREE_SFLASH700 EQU 0x0ffff6bc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH701 +CYREG_SFLASH_MACRO_0_FREE_SFLASH701 EQU 0x0ffff6bd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH702 +CYREG_SFLASH_MACRO_0_FREE_SFLASH702 EQU 0x0ffff6be + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH703 +CYREG_SFLASH_MACRO_0_FREE_SFLASH703 EQU 0x0ffff6bf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH704 +CYREG_SFLASH_MACRO_0_FREE_SFLASH704 EQU 0x0ffff6c0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH705 +CYREG_SFLASH_MACRO_0_FREE_SFLASH705 EQU 0x0ffff6c1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH706 +CYREG_SFLASH_MACRO_0_FREE_SFLASH706 EQU 0x0ffff6c2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH707 +CYREG_SFLASH_MACRO_0_FREE_SFLASH707 EQU 0x0ffff6c3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH708 +CYREG_SFLASH_MACRO_0_FREE_SFLASH708 EQU 0x0ffff6c4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH709 +CYREG_SFLASH_MACRO_0_FREE_SFLASH709 EQU 0x0ffff6c5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH710 +CYREG_SFLASH_MACRO_0_FREE_SFLASH710 EQU 0x0ffff6c6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH711 +CYREG_SFLASH_MACRO_0_FREE_SFLASH711 EQU 0x0ffff6c7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH712 +CYREG_SFLASH_MACRO_0_FREE_SFLASH712 EQU 0x0ffff6c8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH713 +CYREG_SFLASH_MACRO_0_FREE_SFLASH713 EQU 0x0ffff6c9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH714 +CYREG_SFLASH_MACRO_0_FREE_SFLASH714 EQU 0x0ffff6ca + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH715 +CYREG_SFLASH_MACRO_0_FREE_SFLASH715 EQU 0x0ffff6cb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH716 +CYREG_SFLASH_MACRO_0_FREE_SFLASH716 EQU 0x0ffff6cc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH717 +CYREG_SFLASH_MACRO_0_FREE_SFLASH717 EQU 0x0ffff6cd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH718 +CYREG_SFLASH_MACRO_0_FREE_SFLASH718 EQU 0x0ffff6ce + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH719 +CYREG_SFLASH_MACRO_0_FREE_SFLASH719 EQU 0x0ffff6cf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH720 +CYREG_SFLASH_MACRO_0_FREE_SFLASH720 EQU 0x0ffff6d0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH721 +CYREG_SFLASH_MACRO_0_FREE_SFLASH721 EQU 0x0ffff6d1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH722 +CYREG_SFLASH_MACRO_0_FREE_SFLASH722 EQU 0x0ffff6d2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH723 +CYREG_SFLASH_MACRO_0_FREE_SFLASH723 EQU 0x0ffff6d3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH724 +CYREG_SFLASH_MACRO_0_FREE_SFLASH724 EQU 0x0ffff6d4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH725 +CYREG_SFLASH_MACRO_0_FREE_SFLASH725 EQU 0x0ffff6d5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH726 +CYREG_SFLASH_MACRO_0_FREE_SFLASH726 EQU 0x0ffff6d6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH727 +CYREG_SFLASH_MACRO_0_FREE_SFLASH727 EQU 0x0ffff6d7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH728 +CYREG_SFLASH_MACRO_0_FREE_SFLASH728 EQU 0x0ffff6d8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH729 +CYREG_SFLASH_MACRO_0_FREE_SFLASH729 EQU 0x0ffff6d9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH730 +CYREG_SFLASH_MACRO_0_FREE_SFLASH730 EQU 0x0ffff6da + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH731 +CYREG_SFLASH_MACRO_0_FREE_SFLASH731 EQU 0x0ffff6db + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH732 +CYREG_SFLASH_MACRO_0_FREE_SFLASH732 EQU 0x0ffff6dc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH733 +CYREG_SFLASH_MACRO_0_FREE_SFLASH733 EQU 0x0ffff6dd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH734 +CYREG_SFLASH_MACRO_0_FREE_SFLASH734 EQU 0x0ffff6de + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH735 +CYREG_SFLASH_MACRO_0_FREE_SFLASH735 EQU 0x0ffff6df + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH736 +CYREG_SFLASH_MACRO_0_FREE_SFLASH736 EQU 0x0ffff6e0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH737 +CYREG_SFLASH_MACRO_0_FREE_SFLASH737 EQU 0x0ffff6e1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH738 +CYREG_SFLASH_MACRO_0_FREE_SFLASH738 EQU 0x0ffff6e2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH739 +CYREG_SFLASH_MACRO_0_FREE_SFLASH739 EQU 0x0ffff6e3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH740 +CYREG_SFLASH_MACRO_0_FREE_SFLASH740 EQU 0x0ffff6e4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH741 +CYREG_SFLASH_MACRO_0_FREE_SFLASH741 EQU 0x0ffff6e5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH742 +CYREG_SFLASH_MACRO_0_FREE_SFLASH742 EQU 0x0ffff6e6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH743 +CYREG_SFLASH_MACRO_0_FREE_SFLASH743 EQU 0x0ffff6e7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH744 +CYREG_SFLASH_MACRO_0_FREE_SFLASH744 EQU 0x0ffff6e8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH745 +CYREG_SFLASH_MACRO_0_FREE_SFLASH745 EQU 0x0ffff6e9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH746 +CYREG_SFLASH_MACRO_0_FREE_SFLASH746 EQU 0x0ffff6ea + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH747 +CYREG_SFLASH_MACRO_0_FREE_SFLASH747 EQU 0x0ffff6eb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH748 +CYREG_SFLASH_MACRO_0_FREE_SFLASH748 EQU 0x0ffff6ec + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH749 +CYREG_SFLASH_MACRO_0_FREE_SFLASH749 EQU 0x0ffff6ed + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH750 +CYREG_SFLASH_MACRO_0_FREE_SFLASH750 EQU 0x0ffff6ee + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH751 +CYREG_SFLASH_MACRO_0_FREE_SFLASH751 EQU 0x0ffff6ef + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH752 +CYREG_SFLASH_MACRO_0_FREE_SFLASH752 EQU 0x0ffff6f0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH753 +CYREG_SFLASH_MACRO_0_FREE_SFLASH753 EQU 0x0ffff6f1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH754 +CYREG_SFLASH_MACRO_0_FREE_SFLASH754 EQU 0x0ffff6f2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH755 +CYREG_SFLASH_MACRO_0_FREE_SFLASH755 EQU 0x0ffff6f3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH756 +CYREG_SFLASH_MACRO_0_FREE_SFLASH756 EQU 0x0ffff6f4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH757 +CYREG_SFLASH_MACRO_0_FREE_SFLASH757 EQU 0x0ffff6f5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH758 +CYREG_SFLASH_MACRO_0_FREE_SFLASH758 EQU 0x0ffff6f6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH759 +CYREG_SFLASH_MACRO_0_FREE_SFLASH759 EQU 0x0ffff6f7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH760 +CYREG_SFLASH_MACRO_0_FREE_SFLASH760 EQU 0x0ffff6f8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH761 +CYREG_SFLASH_MACRO_0_FREE_SFLASH761 EQU 0x0ffff6f9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH762 +CYREG_SFLASH_MACRO_0_FREE_SFLASH762 EQU 0x0ffff6fa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH763 +CYREG_SFLASH_MACRO_0_FREE_SFLASH763 EQU 0x0ffff6fb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH764 +CYREG_SFLASH_MACRO_0_FREE_SFLASH764 EQU 0x0ffff6fc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH765 +CYREG_SFLASH_MACRO_0_FREE_SFLASH765 EQU 0x0ffff6fd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH766 +CYREG_SFLASH_MACRO_0_FREE_SFLASH766 EQU 0x0ffff6fe + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH767 +CYREG_SFLASH_MACRO_0_FREE_SFLASH767 EQU 0x0ffff6ff + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH768 +CYREG_SFLASH_MACRO_0_FREE_SFLASH768 EQU 0x0ffff700 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH769 +CYREG_SFLASH_MACRO_0_FREE_SFLASH769 EQU 0x0ffff701 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH770 +CYREG_SFLASH_MACRO_0_FREE_SFLASH770 EQU 0x0ffff702 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH771 +CYREG_SFLASH_MACRO_0_FREE_SFLASH771 EQU 0x0ffff703 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH772 +CYREG_SFLASH_MACRO_0_FREE_SFLASH772 EQU 0x0ffff704 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH773 +CYREG_SFLASH_MACRO_0_FREE_SFLASH773 EQU 0x0ffff705 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH774 +CYREG_SFLASH_MACRO_0_FREE_SFLASH774 EQU 0x0ffff706 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH775 +CYREG_SFLASH_MACRO_0_FREE_SFLASH775 EQU 0x0ffff707 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH776 +CYREG_SFLASH_MACRO_0_FREE_SFLASH776 EQU 0x0ffff708 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH777 +CYREG_SFLASH_MACRO_0_FREE_SFLASH777 EQU 0x0ffff709 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH778 +CYREG_SFLASH_MACRO_0_FREE_SFLASH778 EQU 0x0ffff70a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH779 +CYREG_SFLASH_MACRO_0_FREE_SFLASH779 EQU 0x0ffff70b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH780 +CYREG_SFLASH_MACRO_0_FREE_SFLASH780 EQU 0x0ffff70c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH781 +CYREG_SFLASH_MACRO_0_FREE_SFLASH781 EQU 0x0ffff70d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH782 +CYREG_SFLASH_MACRO_0_FREE_SFLASH782 EQU 0x0ffff70e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH783 +CYREG_SFLASH_MACRO_0_FREE_SFLASH783 EQU 0x0ffff70f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH784 +CYREG_SFLASH_MACRO_0_FREE_SFLASH784 EQU 0x0ffff710 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH785 +CYREG_SFLASH_MACRO_0_FREE_SFLASH785 EQU 0x0ffff711 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH786 +CYREG_SFLASH_MACRO_0_FREE_SFLASH786 EQU 0x0ffff712 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH787 +CYREG_SFLASH_MACRO_0_FREE_SFLASH787 EQU 0x0ffff713 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH788 +CYREG_SFLASH_MACRO_0_FREE_SFLASH788 EQU 0x0ffff714 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH789 +CYREG_SFLASH_MACRO_0_FREE_SFLASH789 EQU 0x0ffff715 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH790 +CYREG_SFLASH_MACRO_0_FREE_SFLASH790 EQU 0x0ffff716 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH791 +CYREG_SFLASH_MACRO_0_FREE_SFLASH791 EQU 0x0ffff717 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH792 +CYREG_SFLASH_MACRO_0_FREE_SFLASH792 EQU 0x0ffff718 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH793 +CYREG_SFLASH_MACRO_0_FREE_SFLASH793 EQU 0x0ffff719 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH794 +CYREG_SFLASH_MACRO_0_FREE_SFLASH794 EQU 0x0ffff71a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH795 +CYREG_SFLASH_MACRO_0_FREE_SFLASH795 EQU 0x0ffff71b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH796 +CYREG_SFLASH_MACRO_0_FREE_SFLASH796 EQU 0x0ffff71c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH797 +CYREG_SFLASH_MACRO_0_FREE_SFLASH797 EQU 0x0ffff71d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH798 +CYREG_SFLASH_MACRO_0_FREE_SFLASH798 EQU 0x0ffff71e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH799 +CYREG_SFLASH_MACRO_0_FREE_SFLASH799 EQU 0x0ffff71f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH800 +CYREG_SFLASH_MACRO_0_FREE_SFLASH800 EQU 0x0ffff720 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH801 +CYREG_SFLASH_MACRO_0_FREE_SFLASH801 EQU 0x0ffff721 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH802 +CYREG_SFLASH_MACRO_0_FREE_SFLASH802 EQU 0x0ffff722 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH803 +CYREG_SFLASH_MACRO_0_FREE_SFLASH803 EQU 0x0ffff723 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH804 +CYREG_SFLASH_MACRO_0_FREE_SFLASH804 EQU 0x0ffff724 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH805 +CYREG_SFLASH_MACRO_0_FREE_SFLASH805 EQU 0x0ffff725 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH806 +CYREG_SFLASH_MACRO_0_FREE_SFLASH806 EQU 0x0ffff726 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH807 +CYREG_SFLASH_MACRO_0_FREE_SFLASH807 EQU 0x0ffff727 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH808 +CYREG_SFLASH_MACRO_0_FREE_SFLASH808 EQU 0x0ffff728 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH809 +CYREG_SFLASH_MACRO_0_FREE_SFLASH809 EQU 0x0ffff729 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH810 +CYREG_SFLASH_MACRO_0_FREE_SFLASH810 EQU 0x0ffff72a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH811 +CYREG_SFLASH_MACRO_0_FREE_SFLASH811 EQU 0x0ffff72b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH812 +CYREG_SFLASH_MACRO_0_FREE_SFLASH812 EQU 0x0ffff72c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH813 +CYREG_SFLASH_MACRO_0_FREE_SFLASH813 EQU 0x0ffff72d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH814 +CYREG_SFLASH_MACRO_0_FREE_SFLASH814 EQU 0x0ffff72e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH815 +CYREG_SFLASH_MACRO_0_FREE_SFLASH815 EQU 0x0ffff72f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH816 +CYREG_SFLASH_MACRO_0_FREE_SFLASH816 EQU 0x0ffff730 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH817 +CYREG_SFLASH_MACRO_0_FREE_SFLASH817 EQU 0x0ffff731 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH818 +CYREG_SFLASH_MACRO_0_FREE_SFLASH818 EQU 0x0ffff732 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH819 +CYREG_SFLASH_MACRO_0_FREE_SFLASH819 EQU 0x0ffff733 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH820 +CYREG_SFLASH_MACRO_0_FREE_SFLASH820 EQU 0x0ffff734 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH821 +CYREG_SFLASH_MACRO_0_FREE_SFLASH821 EQU 0x0ffff735 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH822 +CYREG_SFLASH_MACRO_0_FREE_SFLASH822 EQU 0x0ffff736 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH823 +CYREG_SFLASH_MACRO_0_FREE_SFLASH823 EQU 0x0ffff737 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH824 +CYREG_SFLASH_MACRO_0_FREE_SFLASH824 EQU 0x0ffff738 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH825 +CYREG_SFLASH_MACRO_0_FREE_SFLASH825 EQU 0x0ffff739 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH826 +CYREG_SFLASH_MACRO_0_FREE_SFLASH826 EQU 0x0ffff73a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH827 +CYREG_SFLASH_MACRO_0_FREE_SFLASH827 EQU 0x0ffff73b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH828 +CYREG_SFLASH_MACRO_0_FREE_SFLASH828 EQU 0x0ffff73c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH829 +CYREG_SFLASH_MACRO_0_FREE_SFLASH829 EQU 0x0ffff73d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH830 +CYREG_SFLASH_MACRO_0_FREE_SFLASH830 EQU 0x0ffff73e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH831 +CYREG_SFLASH_MACRO_0_FREE_SFLASH831 EQU 0x0ffff73f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH832 +CYREG_SFLASH_MACRO_0_FREE_SFLASH832 EQU 0x0ffff740 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH833 +CYREG_SFLASH_MACRO_0_FREE_SFLASH833 EQU 0x0ffff741 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH834 +CYREG_SFLASH_MACRO_0_FREE_SFLASH834 EQU 0x0ffff742 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH835 +CYREG_SFLASH_MACRO_0_FREE_SFLASH835 EQU 0x0ffff743 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH836 +CYREG_SFLASH_MACRO_0_FREE_SFLASH836 EQU 0x0ffff744 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH837 +CYREG_SFLASH_MACRO_0_FREE_SFLASH837 EQU 0x0ffff745 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH838 +CYREG_SFLASH_MACRO_0_FREE_SFLASH838 EQU 0x0ffff746 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH839 +CYREG_SFLASH_MACRO_0_FREE_SFLASH839 EQU 0x0ffff747 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH840 +CYREG_SFLASH_MACRO_0_FREE_SFLASH840 EQU 0x0ffff748 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH841 +CYREG_SFLASH_MACRO_0_FREE_SFLASH841 EQU 0x0ffff749 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH842 +CYREG_SFLASH_MACRO_0_FREE_SFLASH842 EQU 0x0ffff74a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH843 +CYREG_SFLASH_MACRO_0_FREE_SFLASH843 EQU 0x0ffff74b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH844 +CYREG_SFLASH_MACRO_0_FREE_SFLASH844 EQU 0x0ffff74c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH845 +CYREG_SFLASH_MACRO_0_FREE_SFLASH845 EQU 0x0ffff74d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH846 +CYREG_SFLASH_MACRO_0_FREE_SFLASH846 EQU 0x0ffff74e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH847 +CYREG_SFLASH_MACRO_0_FREE_SFLASH847 EQU 0x0ffff74f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH848 +CYREG_SFLASH_MACRO_0_FREE_SFLASH848 EQU 0x0ffff750 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH849 +CYREG_SFLASH_MACRO_0_FREE_SFLASH849 EQU 0x0ffff751 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH850 +CYREG_SFLASH_MACRO_0_FREE_SFLASH850 EQU 0x0ffff752 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH851 +CYREG_SFLASH_MACRO_0_FREE_SFLASH851 EQU 0x0ffff753 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH852 +CYREG_SFLASH_MACRO_0_FREE_SFLASH852 EQU 0x0ffff754 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH853 +CYREG_SFLASH_MACRO_0_FREE_SFLASH853 EQU 0x0ffff755 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH854 +CYREG_SFLASH_MACRO_0_FREE_SFLASH854 EQU 0x0ffff756 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH855 +CYREG_SFLASH_MACRO_0_FREE_SFLASH855 EQU 0x0ffff757 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH856 +CYREG_SFLASH_MACRO_0_FREE_SFLASH856 EQU 0x0ffff758 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH857 +CYREG_SFLASH_MACRO_0_FREE_SFLASH857 EQU 0x0ffff759 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH858 +CYREG_SFLASH_MACRO_0_FREE_SFLASH858 EQU 0x0ffff75a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH859 +CYREG_SFLASH_MACRO_0_FREE_SFLASH859 EQU 0x0ffff75b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH860 +CYREG_SFLASH_MACRO_0_FREE_SFLASH860 EQU 0x0ffff75c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH861 +CYREG_SFLASH_MACRO_0_FREE_SFLASH861 EQU 0x0ffff75d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH862 +CYREG_SFLASH_MACRO_0_FREE_SFLASH862 EQU 0x0ffff75e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH863 +CYREG_SFLASH_MACRO_0_FREE_SFLASH863 EQU 0x0ffff75f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH864 +CYREG_SFLASH_MACRO_0_FREE_SFLASH864 EQU 0x0ffff760 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH865 +CYREG_SFLASH_MACRO_0_FREE_SFLASH865 EQU 0x0ffff761 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH866 +CYREG_SFLASH_MACRO_0_FREE_SFLASH866 EQU 0x0ffff762 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH867 +CYREG_SFLASH_MACRO_0_FREE_SFLASH867 EQU 0x0ffff763 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH868 +CYREG_SFLASH_MACRO_0_FREE_SFLASH868 EQU 0x0ffff764 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH869 +CYREG_SFLASH_MACRO_0_FREE_SFLASH869 EQU 0x0ffff765 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH870 +CYREG_SFLASH_MACRO_0_FREE_SFLASH870 EQU 0x0ffff766 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH871 +CYREG_SFLASH_MACRO_0_FREE_SFLASH871 EQU 0x0ffff767 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH872 +CYREG_SFLASH_MACRO_0_FREE_SFLASH872 EQU 0x0ffff768 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH873 +CYREG_SFLASH_MACRO_0_FREE_SFLASH873 EQU 0x0ffff769 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH874 +CYREG_SFLASH_MACRO_0_FREE_SFLASH874 EQU 0x0ffff76a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH875 +CYREG_SFLASH_MACRO_0_FREE_SFLASH875 EQU 0x0ffff76b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH876 +CYREG_SFLASH_MACRO_0_FREE_SFLASH876 EQU 0x0ffff76c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH877 +CYREG_SFLASH_MACRO_0_FREE_SFLASH877 EQU 0x0ffff76d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH878 +CYREG_SFLASH_MACRO_0_FREE_SFLASH878 EQU 0x0ffff76e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH879 +CYREG_SFLASH_MACRO_0_FREE_SFLASH879 EQU 0x0ffff76f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH880 +CYREG_SFLASH_MACRO_0_FREE_SFLASH880 EQU 0x0ffff770 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH881 +CYREG_SFLASH_MACRO_0_FREE_SFLASH881 EQU 0x0ffff771 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH882 +CYREG_SFLASH_MACRO_0_FREE_SFLASH882 EQU 0x0ffff772 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH883 +CYREG_SFLASH_MACRO_0_FREE_SFLASH883 EQU 0x0ffff773 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH884 +CYREG_SFLASH_MACRO_0_FREE_SFLASH884 EQU 0x0ffff774 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH885 +CYREG_SFLASH_MACRO_0_FREE_SFLASH885 EQU 0x0ffff775 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH886 +CYREG_SFLASH_MACRO_0_FREE_SFLASH886 EQU 0x0ffff776 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH887 +CYREG_SFLASH_MACRO_0_FREE_SFLASH887 EQU 0x0ffff777 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH888 +CYREG_SFLASH_MACRO_0_FREE_SFLASH888 EQU 0x0ffff778 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH889 +CYREG_SFLASH_MACRO_0_FREE_SFLASH889 EQU 0x0ffff779 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH890 +CYREG_SFLASH_MACRO_0_FREE_SFLASH890 EQU 0x0ffff77a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH891 +CYREG_SFLASH_MACRO_0_FREE_SFLASH891 EQU 0x0ffff77b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH892 +CYREG_SFLASH_MACRO_0_FREE_SFLASH892 EQU 0x0ffff77c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH893 +CYREG_SFLASH_MACRO_0_FREE_SFLASH893 EQU 0x0ffff77d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH894 +CYREG_SFLASH_MACRO_0_FREE_SFLASH894 EQU 0x0ffff77e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH895 +CYREG_SFLASH_MACRO_0_FREE_SFLASH895 EQU 0x0ffff77f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH896 +CYREG_SFLASH_MACRO_0_FREE_SFLASH896 EQU 0x0ffff780 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH897 +CYREG_SFLASH_MACRO_0_FREE_SFLASH897 EQU 0x0ffff781 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH898 +CYREG_SFLASH_MACRO_0_FREE_SFLASH898 EQU 0x0ffff782 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH899 +CYREG_SFLASH_MACRO_0_FREE_SFLASH899 EQU 0x0ffff783 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH900 +CYREG_SFLASH_MACRO_0_FREE_SFLASH900 EQU 0x0ffff784 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH901 +CYREG_SFLASH_MACRO_0_FREE_SFLASH901 EQU 0x0ffff785 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH902 +CYREG_SFLASH_MACRO_0_FREE_SFLASH902 EQU 0x0ffff786 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH903 +CYREG_SFLASH_MACRO_0_FREE_SFLASH903 EQU 0x0ffff787 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH904 +CYREG_SFLASH_MACRO_0_FREE_SFLASH904 EQU 0x0ffff788 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH905 +CYREG_SFLASH_MACRO_0_FREE_SFLASH905 EQU 0x0ffff789 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH906 +CYREG_SFLASH_MACRO_0_FREE_SFLASH906 EQU 0x0ffff78a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH907 +CYREG_SFLASH_MACRO_0_FREE_SFLASH907 EQU 0x0ffff78b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH908 +CYREG_SFLASH_MACRO_0_FREE_SFLASH908 EQU 0x0ffff78c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH909 +CYREG_SFLASH_MACRO_0_FREE_SFLASH909 EQU 0x0ffff78d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH910 +CYREG_SFLASH_MACRO_0_FREE_SFLASH910 EQU 0x0ffff78e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH911 +CYREG_SFLASH_MACRO_0_FREE_SFLASH911 EQU 0x0ffff78f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH912 +CYREG_SFLASH_MACRO_0_FREE_SFLASH912 EQU 0x0ffff790 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH913 +CYREG_SFLASH_MACRO_0_FREE_SFLASH913 EQU 0x0ffff791 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH914 +CYREG_SFLASH_MACRO_0_FREE_SFLASH914 EQU 0x0ffff792 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH915 +CYREG_SFLASH_MACRO_0_FREE_SFLASH915 EQU 0x0ffff793 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH916 +CYREG_SFLASH_MACRO_0_FREE_SFLASH916 EQU 0x0ffff794 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH917 +CYREG_SFLASH_MACRO_0_FREE_SFLASH917 EQU 0x0ffff795 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH918 +CYREG_SFLASH_MACRO_0_FREE_SFLASH918 EQU 0x0ffff796 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH919 +CYREG_SFLASH_MACRO_0_FREE_SFLASH919 EQU 0x0ffff797 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH920 +CYREG_SFLASH_MACRO_0_FREE_SFLASH920 EQU 0x0ffff798 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH921 +CYREG_SFLASH_MACRO_0_FREE_SFLASH921 EQU 0x0ffff799 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH922 +CYREG_SFLASH_MACRO_0_FREE_SFLASH922 EQU 0x0ffff79a + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH923 +CYREG_SFLASH_MACRO_0_FREE_SFLASH923 EQU 0x0ffff79b + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH924 +CYREG_SFLASH_MACRO_0_FREE_SFLASH924 EQU 0x0ffff79c + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH925 +CYREG_SFLASH_MACRO_0_FREE_SFLASH925 EQU 0x0ffff79d + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH926 +CYREG_SFLASH_MACRO_0_FREE_SFLASH926 EQU 0x0ffff79e + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH927 +CYREG_SFLASH_MACRO_0_FREE_SFLASH927 EQU 0x0ffff79f + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH928 +CYREG_SFLASH_MACRO_0_FREE_SFLASH928 EQU 0x0ffff7a0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH929 +CYREG_SFLASH_MACRO_0_FREE_SFLASH929 EQU 0x0ffff7a1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH930 +CYREG_SFLASH_MACRO_0_FREE_SFLASH930 EQU 0x0ffff7a2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH931 +CYREG_SFLASH_MACRO_0_FREE_SFLASH931 EQU 0x0ffff7a3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH932 +CYREG_SFLASH_MACRO_0_FREE_SFLASH932 EQU 0x0ffff7a4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH933 +CYREG_SFLASH_MACRO_0_FREE_SFLASH933 EQU 0x0ffff7a5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH934 +CYREG_SFLASH_MACRO_0_FREE_SFLASH934 EQU 0x0ffff7a6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH935 +CYREG_SFLASH_MACRO_0_FREE_SFLASH935 EQU 0x0ffff7a7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH936 +CYREG_SFLASH_MACRO_0_FREE_SFLASH936 EQU 0x0ffff7a8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH937 +CYREG_SFLASH_MACRO_0_FREE_SFLASH937 EQU 0x0ffff7a9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH938 +CYREG_SFLASH_MACRO_0_FREE_SFLASH938 EQU 0x0ffff7aa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH939 +CYREG_SFLASH_MACRO_0_FREE_SFLASH939 EQU 0x0ffff7ab + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH940 +CYREG_SFLASH_MACRO_0_FREE_SFLASH940 EQU 0x0ffff7ac + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH941 +CYREG_SFLASH_MACRO_0_FREE_SFLASH941 EQU 0x0ffff7ad + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH942 +CYREG_SFLASH_MACRO_0_FREE_SFLASH942 EQU 0x0ffff7ae + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH943 +CYREG_SFLASH_MACRO_0_FREE_SFLASH943 EQU 0x0ffff7af + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH944 +CYREG_SFLASH_MACRO_0_FREE_SFLASH944 EQU 0x0ffff7b0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH945 +CYREG_SFLASH_MACRO_0_FREE_SFLASH945 EQU 0x0ffff7b1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH946 +CYREG_SFLASH_MACRO_0_FREE_SFLASH946 EQU 0x0ffff7b2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH947 +CYREG_SFLASH_MACRO_0_FREE_SFLASH947 EQU 0x0ffff7b3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH948 +CYREG_SFLASH_MACRO_0_FREE_SFLASH948 EQU 0x0ffff7b4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH949 +CYREG_SFLASH_MACRO_0_FREE_SFLASH949 EQU 0x0ffff7b5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH950 +CYREG_SFLASH_MACRO_0_FREE_SFLASH950 EQU 0x0ffff7b6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH951 +CYREG_SFLASH_MACRO_0_FREE_SFLASH951 EQU 0x0ffff7b7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH952 +CYREG_SFLASH_MACRO_0_FREE_SFLASH952 EQU 0x0ffff7b8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH953 +CYREG_SFLASH_MACRO_0_FREE_SFLASH953 EQU 0x0ffff7b9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH954 +CYREG_SFLASH_MACRO_0_FREE_SFLASH954 EQU 0x0ffff7ba + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH955 +CYREG_SFLASH_MACRO_0_FREE_SFLASH955 EQU 0x0ffff7bb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH956 +CYREG_SFLASH_MACRO_0_FREE_SFLASH956 EQU 0x0ffff7bc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH957 +CYREG_SFLASH_MACRO_0_FREE_SFLASH957 EQU 0x0ffff7bd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH958 +CYREG_SFLASH_MACRO_0_FREE_SFLASH958 EQU 0x0ffff7be + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH959 +CYREG_SFLASH_MACRO_0_FREE_SFLASH959 EQU 0x0ffff7bf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH960 +CYREG_SFLASH_MACRO_0_FREE_SFLASH960 EQU 0x0ffff7c0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH961 +CYREG_SFLASH_MACRO_0_FREE_SFLASH961 EQU 0x0ffff7c1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH962 +CYREG_SFLASH_MACRO_0_FREE_SFLASH962 EQU 0x0ffff7c2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH963 +CYREG_SFLASH_MACRO_0_FREE_SFLASH963 EQU 0x0ffff7c3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH964 +CYREG_SFLASH_MACRO_0_FREE_SFLASH964 EQU 0x0ffff7c4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH965 +CYREG_SFLASH_MACRO_0_FREE_SFLASH965 EQU 0x0ffff7c5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH966 +CYREG_SFLASH_MACRO_0_FREE_SFLASH966 EQU 0x0ffff7c6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH967 +CYREG_SFLASH_MACRO_0_FREE_SFLASH967 EQU 0x0ffff7c7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH968 +CYREG_SFLASH_MACRO_0_FREE_SFLASH968 EQU 0x0ffff7c8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH969 +CYREG_SFLASH_MACRO_0_FREE_SFLASH969 EQU 0x0ffff7c9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH970 +CYREG_SFLASH_MACRO_0_FREE_SFLASH970 EQU 0x0ffff7ca + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH971 +CYREG_SFLASH_MACRO_0_FREE_SFLASH971 EQU 0x0ffff7cb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH972 +CYREG_SFLASH_MACRO_0_FREE_SFLASH972 EQU 0x0ffff7cc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH973 +CYREG_SFLASH_MACRO_0_FREE_SFLASH973 EQU 0x0ffff7cd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH974 +CYREG_SFLASH_MACRO_0_FREE_SFLASH974 EQU 0x0ffff7ce + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH975 +CYREG_SFLASH_MACRO_0_FREE_SFLASH975 EQU 0x0ffff7cf + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH976 +CYREG_SFLASH_MACRO_0_FREE_SFLASH976 EQU 0x0ffff7d0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH977 +CYREG_SFLASH_MACRO_0_FREE_SFLASH977 EQU 0x0ffff7d1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH978 +CYREG_SFLASH_MACRO_0_FREE_SFLASH978 EQU 0x0ffff7d2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH979 +CYREG_SFLASH_MACRO_0_FREE_SFLASH979 EQU 0x0ffff7d3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH980 +CYREG_SFLASH_MACRO_0_FREE_SFLASH980 EQU 0x0ffff7d4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH981 +CYREG_SFLASH_MACRO_0_FREE_SFLASH981 EQU 0x0ffff7d5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH982 +CYREG_SFLASH_MACRO_0_FREE_SFLASH982 EQU 0x0ffff7d6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH983 +CYREG_SFLASH_MACRO_0_FREE_SFLASH983 EQU 0x0ffff7d7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH984 +CYREG_SFLASH_MACRO_0_FREE_SFLASH984 EQU 0x0ffff7d8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH985 +CYREG_SFLASH_MACRO_0_FREE_SFLASH985 EQU 0x0ffff7d9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH986 +CYREG_SFLASH_MACRO_0_FREE_SFLASH986 EQU 0x0ffff7da + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH987 +CYREG_SFLASH_MACRO_0_FREE_SFLASH987 EQU 0x0ffff7db + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH988 +CYREG_SFLASH_MACRO_0_FREE_SFLASH988 EQU 0x0ffff7dc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH989 +CYREG_SFLASH_MACRO_0_FREE_SFLASH989 EQU 0x0ffff7dd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH990 +CYREG_SFLASH_MACRO_0_FREE_SFLASH990 EQU 0x0ffff7de + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH991 +CYREG_SFLASH_MACRO_0_FREE_SFLASH991 EQU 0x0ffff7df + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH992 +CYREG_SFLASH_MACRO_0_FREE_SFLASH992 EQU 0x0ffff7e0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH993 +CYREG_SFLASH_MACRO_0_FREE_SFLASH993 EQU 0x0ffff7e1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH994 +CYREG_SFLASH_MACRO_0_FREE_SFLASH994 EQU 0x0ffff7e2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH995 +CYREG_SFLASH_MACRO_0_FREE_SFLASH995 EQU 0x0ffff7e3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH996 +CYREG_SFLASH_MACRO_0_FREE_SFLASH996 EQU 0x0ffff7e4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH997 +CYREG_SFLASH_MACRO_0_FREE_SFLASH997 EQU 0x0ffff7e5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH998 +CYREG_SFLASH_MACRO_0_FREE_SFLASH998 EQU 0x0ffff7e6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH999 +CYREG_SFLASH_MACRO_0_FREE_SFLASH999 EQU 0x0ffff7e7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1000 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1000 EQU 0x0ffff7e8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1001 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1001 EQU 0x0ffff7e9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1002 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1002 EQU 0x0ffff7ea + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1003 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1003 EQU 0x0ffff7eb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1004 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1004 EQU 0x0ffff7ec + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1005 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1005 EQU 0x0ffff7ed + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1006 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1006 EQU 0x0ffff7ee + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1007 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1007 EQU 0x0ffff7ef + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1008 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1008 EQU 0x0ffff7f0 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1009 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1009 EQU 0x0ffff7f1 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1010 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1010 EQU 0x0ffff7f2 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1011 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1011 EQU 0x0ffff7f3 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1012 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1012 EQU 0x0ffff7f4 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1013 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1013 EQU 0x0ffff7f5 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1014 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1014 EQU 0x0ffff7f6 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1015 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1015 EQU 0x0ffff7f7 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1016 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1016 EQU 0x0ffff7f8 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1017 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1017 EQU 0x0ffff7f9 + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1018 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1018 EQU 0x0ffff7fa + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1019 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1019 EQU 0x0ffff7fb + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1020 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1020 EQU 0x0ffff7fc + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1021 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1021 EQU 0x0ffff7fd + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1022 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1022 EQU 0x0ffff7fe + ENDIF + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1023 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1023 EQU 0x0ffff7ff + ENDIF + IF :LNOT::DEF:CYDEV_ROM_BASE +CYDEV_ROM_BASE EQU 0x10000000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_SIZE +CYDEV_ROM_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_DATA_MBASE +CYREG_ROM_DATA_MBASE EQU 0x10000000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_DATA_MSIZE +CYREG_ROM_DATA_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE +CYREG_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE +CYREG_SRAM_DATA_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_PERI_BASE +CYDEV_PERI_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_PERI_SIZE +CYDEV_PERI_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_CMD +CYREG_PERI_DIV_CMD EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_SEL_DIV__OFFSET +CYFLD_PERI_SEL_DIV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_SEL_DIV__SIZE +CYFLD_PERI_SEL_DIV__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_SEL_TYPE__OFFSET +CYFLD_PERI_SEL_TYPE__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_SEL_TYPE__SIZE +CYFLD_PERI_SEL_TYPE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_PA_SEL_DIV__OFFSET +CYFLD_PERI_PA_SEL_DIV__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_PA_SEL_DIV__SIZE +CYFLD_PERI_PA_SEL_DIV__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_PA_SEL_TYPE__OFFSET +CYFLD_PERI_PA_SEL_TYPE__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_PERI_PA_SEL_TYPE__SIZE +CYFLD_PERI_PA_SEL_TYPE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_DISABLE__OFFSET +CYFLD_PERI_DISABLE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_PERI_DISABLE__SIZE +CYFLD_PERI_DISABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_ENABLE__OFFSET +CYFLD_PERI_ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_PERI_ENABLE__SIZE +CYFLD_PERI_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL0 +CYREG_PERI_PCLK_CTL0 EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL1 +CYREG_PERI_PCLK_CTL1 EQU 0x40010104 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL2 +CYREG_PERI_PCLK_CTL2 EQU 0x40010108 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL3 +CYREG_PERI_PCLK_CTL3 EQU 0x4001010c + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL4 +CYREG_PERI_PCLK_CTL4 EQU 0x40010110 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL5 +CYREG_PERI_PCLK_CTL5 EQU 0x40010114 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL6 +CYREG_PERI_PCLK_CTL6 EQU 0x40010118 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL7 +CYREG_PERI_PCLK_CTL7 EQU 0x4001011c + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL8 +CYREG_PERI_PCLK_CTL8 EQU 0x40010120 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL9 +CYREG_PERI_PCLK_CTL9 EQU 0x40010124 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL10 +CYREG_PERI_PCLK_CTL10 EQU 0x40010128 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL11 +CYREG_PERI_PCLK_CTL11 EQU 0x4001012c + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL12 +CYREG_PERI_PCLK_CTL12 EQU 0x40010130 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL13 +CYREG_PERI_PCLK_CTL13 EQU 0x40010134 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL14 +CYREG_PERI_PCLK_CTL14 EQU 0x40010138 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL15 +CYREG_PERI_PCLK_CTL15 EQU 0x4001013c + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL16 +CYREG_PERI_PCLK_CTL16 EQU 0x40010140 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL17 +CYREG_PERI_PCLK_CTL17 EQU 0x40010144 + ENDIF + IF :LNOT::DEF:CYREG_PERI_PCLK_CTL18 +CYREG_PERI_PCLK_CTL18 EQU 0x40010148 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL0 +CYREG_PERI_DIV_16_CTL0 EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_EN__OFFSET +CYFLD_PERI_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_EN__SIZE +CYFLD_PERI_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_INT16_DIV__OFFSET +CYFLD_PERI_INT16_DIV__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_INT16_DIV__SIZE +CYFLD_PERI_INT16_DIV__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL1 +CYREG_PERI_DIV_16_CTL1 EQU 0x40010304 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL2 +CYREG_PERI_DIV_16_CTL2 EQU 0x40010308 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL3 +CYREG_PERI_DIV_16_CTL3 EQU 0x4001030c + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL4 +CYREG_PERI_DIV_16_CTL4 EQU 0x40010310 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL5 +CYREG_PERI_DIV_16_CTL5 EQU 0x40010314 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL6 +CYREG_PERI_DIV_16_CTL6 EQU 0x40010318 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL7 +CYREG_PERI_DIV_16_CTL7 EQU 0x4001031c + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL8 +CYREG_PERI_DIV_16_CTL8 EQU 0x40010320 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL9 +CYREG_PERI_DIV_16_CTL9 EQU 0x40010324 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL10 +CYREG_PERI_DIV_16_CTL10 EQU 0x40010328 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_CTL11 +CYREG_PERI_DIV_16_CTL11 EQU 0x4001032c + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_5_CTL0 +CYREG_PERI_DIV_16_5_CTL0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_FRAC5_DIV__OFFSET +CYFLD_PERI_FRAC5_DIV__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_FRAC5_DIV__SIZE +CYFLD_PERI_FRAC5_DIV__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_5_CTL1 +CYREG_PERI_DIV_16_5_CTL1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_5_CTL2 +CYREG_PERI_DIV_16_5_CTL2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_5_CTL3 +CYREG_PERI_DIV_16_5_CTL3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_16_5_CTL4 +CYREG_PERI_DIV_16_5_CTL4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYREG_PERI_DIV_24_5_CTL +CYREG_PERI_DIV_24_5_CTL EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_INT24_DIV__OFFSET +CYFLD_PERI_INT24_DIV__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_INT24_DIV__SIZE +CYFLD_PERI_INT24_DIV__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_CTL +CYREG_PERI_TR_CTL EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_SEL__OFFSET +CYFLD_PERI_TR_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_SEL__SIZE +CYFLD_PERI_TR_SEL__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_GROUP__OFFSET +CYFLD_PERI_TR_GROUP__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_GROUP__SIZE +CYFLD_PERI_TR_GROUP__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_COUNT__OFFSET +CYFLD_PERI_TR_COUNT__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_COUNT__SIZE +CYFLD_PERI_TR_COUNT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_OUT__OFFSET +CYFLD_PERI_TR_OUT__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_OUT__SIZE +CYFLD_PERI_TR_OUT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_ACT__OFFSET +CYFLD_PERI_TR_ACT__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_ACT__SIZE +CYFLD_PERI_TR_ACT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PERI_TR_GROUP0_BASE +CYDEV_PERI_TR_GROUP0_BASE EQU 0x40012000 + ENDIF + IF :LNOT::DEF:CYDEV_PERI_TR_GROUP0_SIZE +CYDEV_PERI_TR_GROUP0_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP0_TR_OUT_CTL0 +CYREG_PERI_TR_GROUP0_TR_OUT_CTL0 EQU 0x40012000 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_GROUP_SEL__OFFSET +CYFLD_PERI_TR_GROUP_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PERI_TR_GROUP_SEL__SIZE +CYFLD_PERI_TR_GROUP_SEL__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP0_TR_OUT_CTL1 +CYREG_PERI_TR_GROUP0_TR_OUT_CTL1 EQU 0x40012004 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP0_TR_OUT_CTL2 +CYREG_PERI_TR_GROUP0_TR_OUT_CTL2 EQU 0x40012008 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP0_TR_OUT_CTL3 +CYREG_PERI_TR_GROUP0_TR_OUT_CTL3 EQU 0x4001200c + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP0_TR_OUT_CTL4 +CYREG_PERI_TR_GROUP0_TR_OUT_CTL4 EQU 0x40012010 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP0_TR_OUT_CTL5 +CYREG_PERI_TR_GROUP0_TR_OUT_CTL5 EQU 0x40012014 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP0_TR_OUT_CTL6 +CYREG_PERI_TR_GROUP0_TR_OUT_CTL6 EQU 0x40012018 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP0_TR_OUT_CTL7 +CYREG_PERI_TR_GROUP0_TR_OUT_CTL7 EQU 0x4001201c + ENDIF + IF :LNOT::DEF:CYDEV_PERI_TR_GROUP1_BASE +CYDEV_PERI_TR_GROUP1_BASE EQU 0x40012200 + ENDIF + IF :LNOT::DEF:CYDEV_PERI_TR_GROUP1_SIZE +CYDEV_PERI_TR_GROUP1_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP1_TR_OUT_CTL0 +CYREG_PERI_TR_GROUP1_TR_OUT_CTL0 EQU 0x40012200 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP1_TR_OUT_CTL1 +CYREG_PERI_TR_GROUP1_TR_OUT_CTL1 EQU 0x40012204 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP1_TR_OUT_CTL2 +CYREG_PERI_TR_GROUP1_TR_OUT_CTL2 EQU 0x40012208 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP1_TR_OUT_CTL3 +CYREG_PERI_TR_GROUP1_TR_OUT_CTL3 EQU 0x4001220c + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP1_TR_OUT_CTL4 +CYREG_PERI_TR_GROUP1_TR_OUT_CTL4 EQU 0x40012210 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP1_TR_OUT_CTL5 +CYREG_PERI_TR_GROUP1_TR_OUT_CTL5 EQU 0x40012214 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP1_TR_OUT_CTL6 +CYREG_PERI_TR_GROUP1_TR_OUT_CTL6 EQU 0x40012218 + ENDIF + IF :LNOT::DEF:CYDEV_PERI_TR_GROUP2_BASE +CYDEV_PERI_TR_GROUP2_BASE EQU 0x40012400 + ENDIF + IF :LNOT::DEF:CYDEV_PERI_TR_GROUP2_SIZE +CYDEV_PERI_TR_GROUP2_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP2_TR_OUT_CTL +CYREG_PERI_TR_GROUP2_TR_OUT_CTL EQU 0x40012400 + ENDIF + IF :LNOT::DEF:CYDEV_PERI_TR_GROUP3_BASE +CYDEV_PERI_TR_GROUP3_BASE EQU 0x40012600 + ENDIF + IF :LNOT::DEF:CYDEV_PERI_TR_GROUP3_SIZE +CYDEV_PERI_TR_GROUP3_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_PERI_TR_GROUP3_TR_OUT_CTL +CYREG_PERI_TR_GROUP3_TR_OUT_CTL EQU 0x40012600 + ENDIF + IF :LNOT::DEF:CYDEV_HSIOM_BASE +CYDEV_HSIOM_BASE EQU 0x40020000 + ENDIF + IF :LNOT::DEF:CYDEV_HSIOM_SIZE +CYDEV_HSIOM_SIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL0 +CYREG_HSIOM_PORT_SEL0 EQU 0x40020000 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO0_SEL__OFFSET +CYFLD_HSIOM_IO0_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO0_SEL__SIZE +CYFLD_HSIOM_IO0_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_GPIO +CYVAL_HSIOM_IO0_SEL_GPIO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_GPIO_DSI +CYVAL_HSIOM_IO0_SEL_GPIO_DSI EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_DSI_DSI +CYVAL_HSIOM_IO0_SEL_DSI_DSI EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_DSI_GPIO +CYVAL_HSIOM_IO0_SEL_DSI_GPIO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_CSD_SENSE +CYVAL_HSIOM_IO0_SEL_CSD_SENSE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_CSD_SHIELD +CYVAL_HSIOM_IO0_SEL_CSD_SHIELD EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_AMUXA +CYVAL_HSIOM_IO0_SEL_AMUXA EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_AMUXB +CYVAL_HSIOM_IO0_SEL_AMUXB EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_ACT_0 +CYVAL_HSIOM_IO0_SEL_ACT_0 EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_ACT_1 +CYVAL_HSIOM_IO0_SEL_ACT_1 EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_ACT_2 +CYVAL_HSIOM_IO0_SEL_ACT_2 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_ACT_3 +CYVAL_HSIOM_IO0_SEL_ACT_3 EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_LCD_COM +CYVAL_HSIOM_IO0_SEL_LCD_COM EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_LCD_SEG +CYVAL_HSIOM_IO0_SEL_LCD_SEG EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_DS_0 +CYVAL_HSIOM_IO0_SEL_DS_0 EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_DS_1 +CYVAL_HSIOM_IO0_SEL_DS_1 EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_DS_2 +CYVAL_HSIOM_IO0_SEL_DS_2 EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL_HSIOM_IO0_SEL_DS_3 +CYVAL_HSIOM_IO0_SEL_DS_3 EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO1_SEL__OFFSET +CYFLD_HSIOM_IO1_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO1_SEL__SIZE +CYFLD_HSIOM_IO1_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO2_SEL__OFFSET +CYFLD_HSIOM_IO2_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO2_SEL__SIZE +CYFLD_HSIOM_IO2_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO3_SEL__OFFSET +CYFLD_HSIOM_IO3_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO3_SEL__SIZE +CYFLD_HSIOM_IO3_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO4_SEL__OFFSET +CYFLD_HSIOM_IO4_SEL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO4_SEL__SIZE +CYFLD_HSIOM_IO4_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO5_SEL__OFFSET +CYFLD_HSIOM_IO5_SEL__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO5_SEL__SIZE +CYFLD_HSIOM_IO5_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO6_SEL__OFFSET +CYFLD_HSIOM_IO6_SEL__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO6_SEL__SIZE +CYFLD_HSIOM_IO6_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO7_SEL__OFFSET +CYFLD_HSIOM_IO7_SEL__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_IO7_SEL__SIZE +CYFLD_HSIOM_IO7_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL1 +CYREG_HSIOM_PORT_SEL1 EQU 0x40020100 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL2 +CYREG_HSIOM_PORT_SEL2 EQU 0x40020200 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL3 +CYREG_HSIOM_PORT_SEL3 EQU 0x40020300 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL4 +CYREG_HSIOM_PORT_SEL4 EQU 0x40020400 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL5 +CYREG_HSIOM_PORT_SEL5 EQU 0x40020500 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL6 +CYREG_HSIOM_PORT_SEL6 EQU 0x40020600 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_PORT_SEL7 +CYREG_HSIOM_PORT_SEL7 EQU 0x40020700 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_AMUX_SPLIT_CTL0 +CYREG_HSIOM_AMUX_SPLIT_CTL0 EQU 0x40022100 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_AA_SL__OFFSET +CYFLD_HSIOM_SWITCH_AA_SL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_AA_SL__SIZE +CYFLD_HSIOM_SWITCH_AA_SL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_AA_SR__OFFSET +CYFLD_HSIOM_SWITCH_AA_SR__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_AA_SR__SIZE +CYFLD_HSIOM_SWITCH_AA_SR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_AA_S0__OFFSET +CYFLD_HSIOM_SWITCH_AA_S0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_AA_S0__SIZE +CYFLD_HSIOM_SWITCH_AA_S0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_BB_SL__OFFSET +CYFLD_HSIOM_SWITCH_BB_SL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_BB_SL__SIZE +CYFLD_HSIOM_SWITCH_BB_SL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_BB_SR__OFFSET +CYFLD_HSIOM_SWITCH_BB_SR__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_BB_SR__SIZE +CYFLD_HSIOM_SWITCH_BB_SR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_BB_S0__OFFSET +CYFLD_HSIOM_SWITCH_BB_S0__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_HSIOM_SWITCH_BB_S0__SIZE +CYFLD_HSIOM_SWITCH_BB_S0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_HSIOM_AMUX_SPLIT_CTL1 +CYREG_HSIOM_AMUX_SPLIT_CTL1 EQU 0x40022104 + ENDIF + IF :LNOT::DEF:CYREG_PWR_CONTROL +CYREG_PWR_CONTROL EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_MODE__OFFSET +CYFLD__POWER_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__POWER_MODE__SIZE +CYFLD__POWER_MODE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_RESET +CYVAL__POWER_MODE_RESET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_ACTIVE +CYVAL__POWER_MODE_ACTIVE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_SLEEP +CYVAL__POWER_MODE_SLEEP EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__POWER_MODE_DEEP_SLEEP +CYVAL__POWER_MODE_DEEP_SLEEP EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__DEBUG_SESSION__OFFSET +CYFLD__DEBUG_SESSION__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DEBUG_SESSION__SIZE +CYFLD__DEBUG_SESSION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DEBUG_SESSION_NO_SESSION +CYVAL__DEBUG_SESSION_NO_SESSION EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DEBUG_SESSION_SESSION_ACTIVE +CYVAL__DEBUG_SESSION_SESSION_ACTIVE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__LPM_READY__OFFSET +CYFLD__LPM_READY__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__LPM_READY__SIZE +CYFLD__LPM_READY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__OVER_TEMP_EN__OFFSET +CYFLD__OVER_TEMP_EN__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__OVER_TEMP_EN__SIZE +CYFLD__OVER_TEMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__OVER_TEMP_THRESH__OFFSET +CYFLD__OVER_TEMP_THRESH__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD__OVER_TEMP_THRESH__SIZE +CYFLD__OVER_TEMP_THRESH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__SPARE__OFFSET +CYFLD__SPARE__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD__SPARE__SIZE +CYFLD__SPARE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__EXT_VCCD__OFFSET +CYFLD__EXT_VCCD__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD__EXT_VCCD__SIZE +CYFLD__EXT_VCCD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_KEY_DELAY +CYREG_PWR_KEY_DELAY EQU 0x40030004 + ENDIF + IF :LNOT::DEF:CYFLD__WAKEUP_HOLDOFF__OFFSET +CYFLD__WAKEUP_HOLDOFF__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WAKEUP_HOLDOFF__SIZE +CYFLD__WAKEUP_HOLDOFF__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_PWR_DDFT_SELECT +CYREG_PWR_DDFT_SELECT EQU 0x4003000c + ENDIF + IF :LNOT::DEF:CYFLD__DDFT0_SEL__OFFSET +CYFLD__DDFT0_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__DDFT0_SEL__SIZE +CYFLD__DDFT0_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_WAKEUP +CYVAL__DDFT0_SEL_WAKEUP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_AWAKE +CYVAL__DDFT0_SEL_AWAKE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_ACT_POWER_EN +CYVAL__DDFT0_SEL_ACT_POWER_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_ACT_POWER_UP +CYVAL__DDFT0_SEL_ACT_POWER_UP EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_ACT_POWER_GOOD +CYVAL__DDFT0_SEL_ACT_POWER_GOOD EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_ACT_REF_EN +CYVAL__DDFT0_SEL_ACT_REF_EN EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_ACT_COMP_EN +CYVAL__DDFT0_SEL_ACT_COMP_EN EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_DPSLP_REF_EN +CYVAL__DDFT0_SEL_DPSLP_REF_EN EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_DPSLP_REG_EN +CYVAL__DDFT0_SEL_DPSLP_REG_EN EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_DPSLP_COMP_EN +CYVAL__DDFT0_SEL_DPSLP_COMP_EN EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_OVER_TEMP_EN +CYVAL__DDFT0_SEL_OVER_TEMP_EN EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_SLEEPHOLDREQ_N +CYVAL__DDFT0_SEL_SLEEPHOLDREQ_N EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_ADFT_BUF_EN +CYVAL__DDFT0_SEL_ADFT_BUF_EN EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_ATPG_OBSERVE +CYVAL__DDFT0_SEL_ATPG_OBSERVE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_GND +CYVAL__DDFT0_SEL_GND EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL__DDFT0_SEL_PWR +CYVAL__DDFT0_SEL_PWR EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD__DDFT1_SEL__OFFSET +CYFLD__DDFT1_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DDFT1_SEL__SIZE +CYFLD__DDFT1_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_WAKEUP +CYVAL__DDFT1_SEL_WAKEUP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_AWAKE +CYVAL__DDFT1_SEL_AWAKE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_ACT_POWER_EN +CYVAL__DDFT1_SEL_ACT_POWER_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_ACT_POWER_UP +CYVAL__DDFT1_SEL_ACT_POWER_UP EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_ACT_POWER_GOOD +CYVAL__DDFT1_SEL_ACT_POWER_GOOD EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_ACT_REF_VALID +CYVAL__DDFT1_SEL_ACT_REF_VALID EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_ACT_REG_VALID +CYVAL__DDFT1_SEL_ACT_REG_VALID EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_ACT_COMP_OUT +CYVAL__DDFT1_SEL_ACT_COMP_OUT EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_ACT_TEMP_HIGH +CYVAL__DDFT1_SEL_ACT_TEMP_HIGH EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_DPSLP_COMP_OUT +CYVAL__DDFT1_SEL_DPSLP_COMP_OUT EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_DPSLP_POWER_UP +CYVAL__DDFT1_SEL_DPSLP_POWER_UP EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_AWAKE_DELAYED +CYVAL__DDFT1_SEL_AWAKE_DELAYED EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_LPM_READY +CYVAL__DDFT1_SEL_LPM_READY EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_SLEEPHOLDACK_N +CYVAL__DDFT1_SEL_SLEEPHOLDACK_N EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_GND +CYVAL__DDFT1_SEL_GND EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL__DDFT1_SEL_PWR +CYVAL__DDFT1_SEL_PWR EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_TST_MODE +CYREG_TST_MODE EQU 0x40030014 + ENDIF + IF :LNOT::DEF:CYFLD__SWD_CONNECTED__OFFSET +CYFLD__SWD_CONNECTED__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__SWD_CONNECTED__SIZE +CYFLD__SWD_CONNECTED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BLOCK_ALT_XRES__OFFSET +CYFLD__BLOCK_ALT_XRES__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD__BLOCK_ALT_XRES__SIZE +CYFLD__BLOCK_ALT_XRES__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__TEST_KEY_DFT_EN__OFFSET +CYFLD__TEST_KEY_DFT_EN__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD__TEST_KEY_DFT_EN__SIZE +CYFLD__TEST_KEY_DFT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__TEST_MODE__OFFSET +CYFLD__TEST_MODE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__TEST_MODE__SIZE +CYFLD__TEST_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TST_DDFT_CTRL +CYREG_TST_DDFT_CTRL EQU 0x40030018 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL0__OFFSET +CYFLD__DFT_SEL0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL0__SIZE +CYFLD__DFT_SEL0__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_SRC0 +CYVAL__DFT_SEL0_SRC0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_SRC1 +CYVAL__DFT_SEL0_SRC1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_SRC2 +CYVAL__DFT_SEL0_SRC2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_SRC3 +CYVAL__DFT_SEL0_SRC3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_SRC4 +CYVAL__DFT_SEL0_SRC4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_SRC5 +CYVAL__DFT_SEL0_SRC5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_SRC6 +CYVAL__DFT_SEL0_SRC6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_SRC7 +CYVAL__DFT_SEL0_SRC7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_CLK0 +CYVAL__DFT_SEL0_CLK0 EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_CLK1 +CYVAL__DFT_SEL0_CLK1 EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_PWR0 +CYVAL__DFT_SEL0_PWR0 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_PWR1 +CYVAL__DFT_SEL0_PWR1 EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_RES0 +CYVAL__DFT_SEL0_RES0 EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_RES1 +CYVAL__DFT_SEL0_RES1 EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_ADFT_COMP +CYVAL__DFT_SEL0_ADFT_COMP EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL0_VSS +CYVAL__DFT_SEL0_VSS EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL1__OFFSET +CYFLD__DFT_SEL1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_SEL1__SIZE +CYFLD__DFT_SEL1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_SRC0 +CYVAL__DFT_SEL1_SRC0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_SRC1 +CYVAL__DFT_SEL1_SRC1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_SRC2 +CYVAL__DFT_SEL1_SRC2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_SRC3 +CYVAL__DFT_SEL1_SRC3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_SRC4 +CYVAL__DFT_SEL1_SRC4 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_SRC5 +CYVAL__DFT_SEL1_SRC5 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_SRC6 +CYVAL__DFT_SEL1_SRC6 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_SRC7 +CYVAL__DFT_SEL1_SRC7 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_CLK0 +CYVAL__DFT_SEL1_CLK0 EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_CLK1 +CYVAL__DFT_SEL1_CLK1 EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_PWR0 +CYVAL__DFT_SEL1_PWR0 EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_PWR1 +CYVAL__DFT_SEL1_PWR1 EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_RES0 +CYVAL__DFT_SEL1_RES0 EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_RES1 +CYVAL__DFT_SEL1_RES1 EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_ADFT_COMP +CYVAL__DFT_SEL1_ADFT_COMP EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYVAL__DFT_SEL1_VSS +CYVAL__DFT_SEL1_VSS EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD__ENABLE__OFFSET +CYFLD__ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__ENABLE__SIZE +CYFLD__ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TST_TRIM_CNTR1 +CYREG_TST_TRIM_CNTR1 EQU 0x4003001c + ENDIF + IF :LNOT::DEF:CYFLD__COUNTER__OFFSET +CYFLD__COUNTER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__COUNTER__SIZE +CYFLD__COUNTER__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__COUNTER_DONE__OFFSET +CYFLD__COUNTER_DONE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__COUNTER_DONE__SIZE +CYFLD__COUNTER_DONE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TST_TRIM_CNTR2 +CYREG_TST_TRIM_CNTR2 EQU 0x40030020 + ENDIF + IF :LNOT::DEF:CYREG_TST_ADFT_CTRL +CYREG_TST_ADFT_CTRL EQU 0x40030024 + ENDIF + IF :LNOT::DEF:CYFLD__BUF_AUTO_ZERO__OFFSET +CYFLD__BUF_AUTO_ZERO__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__BUF_AUTO_ZERO__SIZE +CYFLD__BUF_AUTO_ZERO__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BUF_MODE__OFFSET +CYFLD__BUF_MODE__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD__BUF_MODE__SIZE +CYFLD__BUF_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__BUF_COMP_OUT__OFFSET +CYFLD__BUF_COMP_OUT__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__BUF_COMP_OUT__SIZE +CYFLD__BUF_COMP_OUT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__BUF_EN__OFFSET +CYFLD__BUF_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD__BUF_EN__SIZE +CYFLD__BUF_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CLK_SELECT +CYREG_CLK_SELECT EQU 0x40030028 + ENDIF + IF :LNOT::DEF:CYFLD__HFCLK_SEL__OFFSET +CYFLD__HFCLK_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__HFCLK_SEL__SIZE +CYFLD__HFCLK_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_SEL_IMO +CYVAL__HFCLK_SEL_IMO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_SEL_EXTCLK +CYVAL__HFCLK_SEL_EXTCLK EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_SEL_ECO +CYVAL__HFCLK_SEL_ECO EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__HFCLK_DIV__OFFSET +CYFLD__HFCLK_DIV__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__HFCLK_DIV__SIZE +CYFLD__HFCLK_DIV__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_DIV_NO_DIV +CYVAL__HFCLK_DIV_NO_DIV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_DIV_DIV_BY_2 +CYVAL__HFCLK_DIV_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_DIV_DIV_BY_4 +CYVAL__HFCLK_DIV_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__HFCLK_DIV_DIV_BY_8 +CYVAL__HFCLK_DIV_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__PUMP_SEL__OFFSET +CYFLD__PUMP_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__PUMP_SEL__SIZE +CYFLD__PUMP_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_GND +CYVAL__PUMP_SEL_GND EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_IMO +CYVAL__PUMP_SEL_IMO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__PUMP_SEL_HFCLK +CYVAL__PUMP_SEL_HFCLK EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD__SYSCLK_DIV__OFFSET +CYFLD__SYSCLK_DIV__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__SYSCLK_DIV__SIZE +CYFLD__SYSCLK_DIV__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_NO_DIV +CYVAL__SYSCLK_DIV_NO_DIV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_2 +CYVAL__SYSCLK_DIV_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_4 +CYVAL__SYSCLK_DIV_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__SYSCLK_DIV_DIV_BY_8 +CYVAL__SYSCLK_DIV_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLK_ILO_CONFIG +CYREG_CLK_ILO_CONFIG EQU 0x4003002c + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_CONFIG +CYREG_CLK_IMO_CONFIG EQU 0x40030030 + ENDIF + IF :LNOT::DEF:CYREG_CLK_DFT_SELECT +CYREG_CLK_DFT_SELECT EQU 0x40030034 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV0__OFFSET +CYFLD__DFT_DIV0__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV0__SIZE +CYFLD__DFT_DIV0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV0_NO_DIV +CYVAL__DFT_DIV0_NO_DIV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV0_DIV_BY_2 +CYVAL__DFT_DIV0_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV0_DIV_BY_4 +CYVAL__DFT_DIV0_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV0_DIV_BY_8 +CYVAL__DFT_DIV0_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_EDGE0__OFFSET +CYFLD__DFT_EDGE0__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_EDGE0__SIZE +CYFLD__DFT_EDGE0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_EDGE0_POSEDGE +CYVAL__DFT_EDGE0_POSEDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_EDGE0_NEGEDGE +CYVAL__DFT_EDGE0_NEGEDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV1__OFFSET +CYFLD__DFT_DIV1__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD__DFT_DIV1__SIZE +CYFLD__DFT_DIV1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_NO_DIV +CYVAL__DFT_DIV1_NO_DIV EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_DIV_BY_2 +CYVAL__DFT_DIV1_DIV_BY_2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_DIV_BY_4 +CYVAL__DFT_DIV1_DIV_BY_4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_DIV1_DIV_BY_8 +CYVAL__DFT_DIV1_DIV_BY_8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__DFT_EDGE1__OFFSET +CYFLD__DFT_EDGE1__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD__DFT_EDGE1__SIZE +CYFLD__DFT_EDGE1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_EDGE1_POSEDGE +CYVAL__DFT_EDGE1_POSEDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__DFT_EDGE1_NEGEDGE +CYVAL__DFT_EDGE1_NEGEDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_WDT_DISABLE_KEY +CYREG_WDT_DISABLE_KEY EQU 0x40030038 + ENDIF + IF :LNOT::DEF:CYFLD__KEY__OFFSET +CYFLD__KEY__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__KEY__SIZE +CYFLD__KEY__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_WDT_COUNTER +CYREG_WDT_COUNTER EQU 0x4003003c + ENDIF + IF :LNOT::DEF:CYREG_WDT_MATCH +CYREG_WDT_MATCH EQU 0x40030040 + ENDIF + IF :LNOT::DEF:CYFLD__MATCH__OFFSET +CYFLD__MATCH__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__MATCH__SIZE +CYFLD__MATCH__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__IGNORE_BITS__OFFSET +CYFLD__IGNORE_BITS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD__IGNORE_BITS__SIZE +CYFLD__IGNORE_BITS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_SRSS_INTR +CYREG_SRSS_INTR EQU 0x40030044 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MATCH__OFFSET +CYFLD__WDT_MATCH__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__WDT_MATCH__SIZE +CYFLD__WDT_MATCH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__TEMP_HIGH__OFFSET +CYFLD__TEMP_HIGH__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__TEMP_HIGH__SIZE +CYFLD__TEMP_HIGH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SRSS_INTR_SET +CYREG_SRSS_INTR_SET EQU 0x40030048 + ENDIF + IF :LNOT::DEF:CYREG_SRSS_INTR_MASK +CYREG_SRSS_INTR_MASK EQU 0x4003004c + ENDIF + IF :LNOT::DEF:CYREG_RES_CAUSE +CYREG_RES_CAUSE EQU 0x40030054 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_WDT__OFFSET +CYFLD__RESET_WDT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_WDT__SIZE +CYFLD__RESET_WDT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_PROT_FAULT__OFFSET +CYFLD__RESET_PROT_FAULT__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_PROT_FAULT__SIZE +CYFLD__RESET_PROT_FAULT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_SOFT__OFFSET +CYFLD__RESET_SOFT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__RESET_SOFT__SIZE +CYFLD__RESET_SOFT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM1 +CYREG_PWR_BG_TRIM1 EQU 0x40030f00 + ENDIF + IF :LNOT::DEF:CYFLD__REF_VTRIM__OFFSET +CYFLD__REF_VTRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__REF_VTRIM__SIZE +CYFLD__REF_VTRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_PWR_BG_TRIM2 +CYREG_PWR_BG_TRIM2 EQU 0x40030f04 + ENDIF + IF :LNOT::DEF:CYFLD__REF_ITRIM__OFFSET +CYFLD__REF_ITRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__REF_ITRIM__SIZE +CYFLD__REF_ITRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_SELECT +CYREG_CLK_IMO_SELECT EQU 0x40030f08 + ENDIF + IF :LNOT::DEF:CYFLD__FREQ__OFFSET +CYFLD__FREQ__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__FREQ__SIZE +CYFLD__FREQ__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__FREQ_24_MHZ +CYVAL__FREQ_24_MHZ EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL__FREQ_28_MHZ +CYVAL__FREQ_28_MHZ EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL__FREQ_32_MHZ +CYVAL__FREQ_32_MHZ EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL__FREQ_36_MHZ +CYVAL__FREQ_36_MHZ EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL__FREQ_40_MHZ +CYVAL__FREQ_40_MHZ EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL__FREQ_44_MHZ +CYVAL__FREQ_44_MHZ EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL__FREQ_48_MHZ +CYVAL__FREQ_48_MHZ EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_TRIM1 +CYREG_CLK_IMO_TRIM1 EQU 0x40030f0c + ENDIF + IF :LNOT::DEF:CYFLD__OFFSET__OFFSET +CYFLD__OFFSET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__OFFSET__SIZE +CYFLD__OFFSET__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_TRIM2 +CYREG_CLK_IMO_TRIM2 EQU 0x40030f10 + ENDIF + IF :LNOT::DEF:CYFLD__FSOFFSET__OFFSET +CYFLD__FSOFFSET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__FSOFFSET__SIZE +CYFLD__FSOFFSET__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_PWR_PWRSYS_TRIM1 +CYREG_PWR_PWRSYS_TRIM1 EQU 0x40030f14 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_REF_TRIM__OFFSET +CYFLD__DPSLP_REF_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__DPSLP_REF_TRIM__SIZE +CYFLD__DPSLP_REF_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__SPARE_TRIM__OFFSET +CYFLD__SPARE_TRIM__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD__SPARE_TRIM__SIZE +CYFLD__SPARE_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLK_IMO_TRIM3 +CYREG_CLK_IMO_TRIM3 EQU 0x40030f18 + ENDIF + IF :LNOT::DEF:CYFLD__STEPSIZE__OFFSET +CYFLD__STEPSIZE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD__STEPSIZE__SIZE +CYFLD__STEPSIZE__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__TCTRIM__OFFSET +CYFLD__TCTRIM__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD__TCTRIM__SIZE +CYFLD__TCTRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_BASE +CYDEV_GPIO_BASE EQU 0x40040000 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_SIZE +CYDEV_GPIO_SIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT0_BASE +CYDEV_GPIO_PRT0_BASE EQU 0x40040000 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT0_SIZE +CYDEV_GPIO_PRT0_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT0_DR +CYREG_GPIO_PRT0_DR EQU 0x40040000 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA0__OFFSET +CYFLD_GPIO_PRT_DATA0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA0__SIZE +CYFLD_GPIO_PRT_DATA0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA1__OFFSET +CYFLD_GPIO_PRT_DATA1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA1__SIZE +CYFLD_GPIO_PRT_DATA1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA2__OFFSET +CYFLD_GPIO_PRT_DATA2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA2__SIZE +CYFLD_GPIO_PRT_DATA2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA3__OFFSET +CYFLD_GPIO_PRT_DATA3__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA3__SIZE +CYFLD_GPIO_PRT_DATA3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA4__OFFSET +CYFLD_GPIO_PRT_DATA4__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA4__SIZE +CYFLD_GPIO_PRT_DATA4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA5__OFFSET +CYFLD_GPIO_PRT_DATA5__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA5__SIZE +CYFLD_GPIO_PRT_DATA5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA6__OFFSET +CYFLD_GPIO_PRT_DATA6__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA6__SIZE +CYFLD_GPIO_PRT_DATA6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA7__OFFSET +CYFLD_GPIO_PRT_DATA7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA7__SIZE +CYFLD_GPIO_PRT_DATA7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT0_PS +CYREG_GPIO_PRT0_PS EQU 0x40040004 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_FLT_DATA__OFFSET +CYFLD_GPIO_PRT_FLT_DATA__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_FLT_DATA__SIZE +CYFLD_GPIO_PRT_FLT_DATA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT0_PC +CYREG_GPIO_PRT0_PC EQU 0x40040008 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM0__OFFSET +CYFLD_GPIO_PRT_DM0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM0__SIZE +CYFLD_GPIO_PRT_DM0__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_DM0_OFF +CYVAL_GPIO_PRT_DM0_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_DM0_INPUT +CYVAL_GPIO_PRT_DM0_INPUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_DM0_0_PU +CYVAL_GPIO_PRT_DM0_0_PU EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_DM0_PD_1 +CYVAL_GPIO_PRT_DM0_PD_1 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_DM0_0_Z +CYVAL_GPIO_PRT_DM0_0_Z EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_DM0_Z_1 +CYVAL_GPIO_PRT_DM0_Z_1 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_DM0_0_1 +CYVAL_GPIO_PRT_DM0_0_1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_DM0_PD_PU +CYVAL_GPIO_PRT_DM0_PD_PU EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM1__OFFSET +CYFLD_GPIO_PRT_DM1__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM1__SIZE +CYFLD_GPIO_PRT_DM1__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM2__OFFSET +CYFLD_GPIO_PRT_DM2__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM2__SIZE +CYFLD_GPIO_PRT_DM2__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM3__OFFSET +CYFLD_GPIO_PRT_DM3__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM3__SIZE +CYFLD_GPIO_PRT_DM3__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM4__OFFSET +CYFLD_GPIO_PRT_DM4__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM4__SIZE +CYFLD_GPIO_PRT_DM4__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM5__OFFSET +CYFLD_GPIO_PRT_DM5__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM5__SIZE +CYFLD_GPIO_PRT_DM5__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM6__OFFSET +CYFLD_GPIO_PRT_DM6__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM6__SIZE +CYFLD_GPIO_PRT_DM6__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM7__OFFSET +CYFLD_GPIO_PRT_DM7__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DM7__SIZE +CYFLD_GPIO_PRT_DM7__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PORT_VTRIP_SEL__OFFSET +CYFLD_GPIO_PRT_PORT_VTRIP_SEL__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PORT_VTRIP_SEL__SIZE +CYFLD_GPIO_PRT_PORT_VTRIP_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PORT_SLOW__OFFSET +CYFLD_GPIO_PRT_PORT_SLOW__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PORT_SLOW__SIZE +CYFLD_GPIO_PRT_PORT_SLOW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__OFFSET +CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__SIZE +CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT0_INTR_CFG +CYREG_GPIO_PRT0_INTR_CFG EQU 0x4004000c + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE0_SEL__OFFSET +CYFLD_GPIO_PRT_EDGE0_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE0_SEL__SIZE +CYFLD_GPIO_PRT_EDGE0_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_EDGE0_SEL_DISABLE +CYVAL_GPIO_PRT_EDGE0_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_EDGE0_SEL_RISING +CYVAL_GPIO_PRT_EDGE0_SEL_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_EDGE0_SEL_FALLING +CYVAL_GPIO_PRT_EDGE0_SEL_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_EDGE0_SEL_BOTH +CYVAL_GPIO_PRT_EDGE0_SEL_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE1_SEL__OFFSET +CYFLD_GPIO_PRT_EDGE1_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE1_SEL__SIZE +CYFLD_GPIO_PRT_EDGE1_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE2_SEL__OFFSET +CYFLD_GPIO_PRT_EDGE2_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE2_SEL__SIZE +CYFLD_GPIO_PRT_EDGE2_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE3_SEL__OFFSET +CYFLD_GPIO_PRT_EDGE3_SEL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE3_SEL__SIZE +CYFLD_GPIO_PRT_EDGE3_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE4_SEL__OFFSET +CYFLD_GPIO_PRT_EDGE4_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE4_SEL__SIZE +CYFLD_GPIO_PRT_EDGE4_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE5_SEL__OFFSET +CYFLD_GPIO_PRT_EDGE5_SEL__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE5_SEL__SIZE +CYFLD_GPIO_PRT_EDGE5_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE6_SEL__OFFSET +CYFLD_GPIO_PRT_EDGE6_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE6_SEL__SIZE +CYFLD_GPIO_PRT_EDGE6_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE7_SEL__OFFSET +CYFLD_GPIO_PRT_EDGE7_SEL__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_EDGE7_SEL__SIZE +CYFLD_GPIO_PRT_EDGE7_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_FLT_EDGE_SEL__OFFSET +CYFLD_GPIO_PRT_FLT_EDGE_SEL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_FLT_EDGE_SEL__SIZE +CYFLD_GPIO_PRT_FLT_EDGE_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_FLT_EDGE_SEL_DISABLE +CYVAL_GPIO_PRT_FLT_EDGE_SEL_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_FLT_EDGE_SEL_RISING +CYVAL_GPIO_PRT_FLT_EDGE_SEL_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_FLT_EDGE_SEL_FALLING +CYVAL_GPIO_PRT_FLT_EDGE_SEL_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_GPIO_PRT_FLT_EDGE_SEL_BOTH +CYVAL_GPIO_PRT_FLT_EDGE_SEL_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_FLT_SEL__OFFSET +CYFLD_GPIO_PRT_FLT_SEL__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_FLT_SEL__SIZE +CYFLD_GPIO_PRT_FLT_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT0_INTR +CYREG_GPIO_PRT0_INTR EQU 0x40040010 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA0__OFFSET +CYFLD_GPIO_PRT_PS_DATA0__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA0__SIZE +CYFLD_GPIO_PRT_PS_DATA0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA1__OFFSET +CYFLD_GPIO_PRT_PS_DATA1__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA1__SIZE +CYFLD_GPIO_PRT_PS_DATA1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA2__OFFSET +CYFLD_GPIO_PRT_PS_DATA2__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA2__SIZE +CYFLD_GPIO_PRT_PS_DATA2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA3__OFFSET +CYFLD_GPIO_PRT_PS_DATA3__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA3__SIZE +CYFLD_GPIO_PRT_PS_DATA3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA4__OFFSET +CYFLD_GPIO_PRT_PS_DATA4__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA4__SIZE +CYFLD_GPIO_PRT_PS_DATA4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA5__OFFSET +CYFLD_GPIO_PRT_PS_DATA5__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA5__SIZE +CYFLD_GPIO_PRT_PS_DATA5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA6__OFFSET +CYFLD_GPIO_PRT_PS_DATA6__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA6__SIZE +CYFLD_GPIO_PRT_PS_DATA6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA7__OFFSET +CYFLD_GPIO_PRT_PS_DATA7__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_DATA7__SIZE +CYFLD_GPIO_PRT_PS_DATA7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_FLT_DATA__OFFSET +CYFLD_GPIO_PRT_PS_FLT_DATA__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_PS_FLT_DATA__SIZE +CYFLD_GPIO_PRT_PS_FLT_DATA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT0_PC2 +CYREG_GPIO_PRT0_PC2 EQU 0x40040018 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS0__OFFSET +CYFLD_GPIO_PRT_INP_DIS0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS0__SIZE +CYFLD_GPIO_PRT_INP_DIS0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS1__OFFSET +CYFLD_GPIO_PRT_INP_DIS1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS1__SIZE +CYFLD_GPIO_PRT_INP_DIS1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS2__OFFSET +CYFLD_GPIO_PRT_INP_DIS2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS2__SIZE +CYFLD_GPIO_PRT_INP_DIS2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS3__OFFSET +CYFLD_GPIO_PRT_INP_DIS3__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS3__SIZE +CYFLD_GPIO_PRT_INP_DIS3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS4__OFFSET +CYFLD_GPIO_PRT_INP_DIS4__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS4__SIZE +CYFLD_GPIO_PRT_INP_DIS4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS5__OFFSET +CYFLD_GPIO_PRT_INP_DIS5__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS5__SIZE +CYFLD_GPIO_PRT_INP_DIS5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS6__OFFSET +CYFLD_GPIO_PRT_INP_DIS6__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS6__SIZE +CYFLD_GPIO_PRT_INP_DIS6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS7__OFFSET +CYFLD_GPIO_PRT_INP_DIS7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_INP_DIS7__SIZE +CYFLD_GPIO_PRT_INP_DIS7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT0_DR_SET +CYREG_GPIO_PRT0_DR_SET EQU 0x40040040 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA__OFFSET +CYFLD_GPIO_PRT_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PRT_DATA__SIZE +CYFLD_GPIO_PRT_DATA__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT0_DR_CLR +CYREG_GPIO_PRT0_DR_CLR EQU 0x40040044 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT0_DR_INV +CYREG_GPIO_PRT0_DR_INV EQU 0x40040048 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT1_BASE +CYDEV_GPIO_PRT1_BASE EQU 0x40040100 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT1_SIZE +CYDEV_GPIO_PRT1_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT1_DR +CYREG_GPIO_PRT1_DR EQU 0x40040100 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT1_PS +CYREG_GPIO_PRT1_PS EQU 0x40040104 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT1_PC +CYREG_GPIO_PRT1_PC EQU 0x40040108 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT1_INTR_CFG +CYREG_GPIO_PRT1_INTR_CFG EQU 0x4004010c + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT1_INTR +CYREG_GPIO_PRT1_INTR EQU 0x40040110 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT1_PC2 +CYREG_GPIO_PRT1_PC2 EQU 0x40040118 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT1_DR_SET +CYREG_GPIO_PRT1_DR_SET EQU 0x40040140 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT1_DR_CLR +CYREG_GPIO_PRT1_DR_CLR EQU 0x40040144 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT1_DR_INV +CYREG_GPIO_PRT1_DR_INV EQU 0x40040148 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT2_BASE +CYDEV_GPIO_PRT2_BASE EQU 0x40040200 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT2_SIZE +CYDEV_GPIO_PRT2_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT2_DR +CYREG_GPIO_PRT2_DR EQU 0x40040200 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT2_PS +CYREG_GPIO_PRT2_PS EQU 0x40040204 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT2_PC +CYREG_GPIO_PRT2_PC EQU 0x40040208 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT2_INTR_CFG +CYREG_GPIO_PRT2_INTR_CFG EQU 0x4004020c + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT2_INTR +CYREG_GPIO_PRT2_INTR EQU 0x40040210 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT2_PC2 +CYREG_GPIO_PRT2_PC2 EQU 0x40040218 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT2_DR_SET +CYREG_GPIO_PRT2_DR_SET EQU 0x40040240 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT2_DR_CLR +CYREG_GPIO_PRT2_DR_CLR EQU 0x40040244 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT2_DR_INV +CYREG_GPIO_PRT2_DR_INV EQU 0x40040248 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT3_BASE +CYDEV_GPIO_PRT3_BASE EQU 0x40040300 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT3_SIZE +CYDEV_GPIO_PRT3_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT3_DR +CYREG_GPIO_PRT3_DR EQU 0x40040300 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT3_PS +CYREG_GPIO_PRT3_PS EQU 0x40040304 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT3_PC +CYREG_GPIO_PRT3_PC EQU 0x40040308 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT3_INTR_CFG +CYREG_GPIO_PRT3_INTR_CFG EQU 0x4004030c + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT3_INTR +CYREG_GPIO_PRT3_INTR EQU 0x40040310 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT3_PC2 +CYREG_GPIO_PRT3_PC2 EQU 0x40040318 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT3_DR_SET +CYREG_GPIO_PRT3_DR_SET EQU 0x40040340 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT3_DR_CLR +CYREG_GPIO_PRT3_DR_CLR EQU 0x40040344 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT3_DR_INV +CYREG_GPIO_PRT3_DR_INV EQU 0x40040348 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT4_BASE +CYDEV_GPIO_PRT4_BASE EQU 0x40040400 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT4_SIZE +CYDEV_GPIO_PRT4_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT4_DR +CYREG_GPIO_PRT4_DR EQU 0x40040400 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT4_PS +CYREG_GPIO_PRT4_PS EQU 0x40040404 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT4_PC +CYREG_GPIO_PRT4_PC EQU 0x40040408 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT4_INTR_CFG +CYREG_GPIO_PRT4_INTR_CFG EQU 0x4004040c + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT4_INTR +CYREG_GPIO_PRT4_INTR EQU 0x40040410 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT4_PC2 +CYREG_GPIO_PRT4_PC2 EQU 0x40040418 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT4_DR_SET +CYREG_GPIO_PRT4_DR_SET EQU 0x40040440 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT4_DR_CLR +CYREG_GPIO_PRT4_DR_CLR EQU 0x40040444 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT4_DR_INV +CYREG_GPIO_PRT4_DR_INV EQU 0x40040448 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT5_BASE +CYDEV_GPIO_PRT5_BASE EQU 0x40040500 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT5_SIZE +CYDEV_GPIO_PRT5_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT5_DR +CYREG_GPIO_PRT5_DR EQU 0x40040500 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT5_PS +CYREG_GPIO_PRT5_PS EQU 0x40040504 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT5_PC +CYREG_GPIO_PRT5_PC EQU 0x40040508 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT5_INTR_CFG +CYREG_GPIO_PRT5_INTR_CFG EQU 0x4004050c + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT5_INTR +CYREG_GPIO_PRT5_INTR EQU 0x40040510 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT5_PC2 +CYREG_GPIO_PRT5_PC2 EQU 0x40040518 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT5_DR_SET +CYREG_GPIO_PRT5_DR_SET EQU 0x40040540 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT5_DR_CLR +CYREG_GPIO_PRT5_DR_CLR EQU 0x40040544 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT5_DR_INV +CYREG_GPIO_PRT5_DR_INV EQU 0x40040548 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT6_BASE +CYDEV_GPIO_PRT6_BASE EQU 0x40040600 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT6_SIZE +CYDEV_GPIO_PRT6_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT6_DR +CYREG_GPIO_PRT6_DR EQU 0x40040600 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT6_PS +CYREG_GPIO_PRT6_PS EQU 0x40040604 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT6_PC +CYREG_GPIO_PRT6_PC EQU 0x40040608 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT6_INTR_CFG +CYREG_GPIO_PRT6_INTR_CFG EQU 0x4004060c + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT6_INTR +CYREG_GPIO_PRT6_INTR EQU 0x40040610 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT6_PC2 +CYREG_GPIO_PRT6_PC2 EQU 0x40040618 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT6_DR_SET +CYREG_GPIO_PRT6_DR_SET EQU 0x40040640 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT6_DR_CLR +CYREG_GPIO_PRT6_DR_CLR EQU 0x40040644 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT6_DR_INV +CYREG_GPIO_PRT6_DR_INV EQU 0x40040648 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT7_BASE +CYDEV_GPIO_PRT7_BASE EQU 0x40040700 + ENDIF + IF :LNOT::DEF:CYDEV_GPIO_PRT7_SIZE +CYDEV_GPIO_PRT7_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT7_DR +CYREG_GPIO_PRT7_DR EQU 0x40040700 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT7_PS +CYREG_GPIO_PRT7_PS EQU 0x40040704 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT7_PC +CYREG_GPIO_PRT7_PC EQU 0x40040708 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT7_INTR_CFG +CYREG_GPIO_PRT7_INTR_CFG EQU 0x4004070c + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT7_INTR +CYREG_GPIO_PRT7_INTR EQU 0x40040710 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT7_PC2 +CYREG_GPIO_PRT7_PC2 EQU 0x40040718 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT7_DR_SET +CYREG_GPIO_PRT7_DR_SET EQU 0x40040740 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT7_DR_CLR +CYREG_GPIO_PRT7_DR_CLR EQU 0x40040744 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_PRT7_DR_INV +CYREG_GPIO_PRT7_DR_INV EQU 0x40040748 + ENDIF + IF :LNOT::DEF:CYREG_GPIO_INTR_CAUSE +CYREG_GPIO_INTR_CAUSE EQU 0x40041000 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PORT_INT__OFFSET +CYFLD_GPIO_PORT_INT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_GPIO_PORT_INT__SIZE +CYFLD_GPIO_PORT_INT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PRGIO_BASE +CYDEV_PRGIO_BASE EQU 0x40050000 + ENDIF + IF :LNOT::DEF:CYDEV_PRGIO_SIZE +CYDEV_PRGIO_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_PRGIO_PRT0_BASE +CYDEV_PRGIO_PRT0_BASE EQU 0x40050000 + ENDIF + IF :LNOT::DEF:CYDEV_PRGIO_PRT0_SIZE +CYDEV_PRGIO_PRT0_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_CTL +CYREG_PRGIO_PRT0_CTL EQU 0x40050000 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_BYPASS__OFFSET +CYFLD_PRGIO_PRT_BYPASS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_BYPASS__SIZE +CYFLD_PRGIO_PRT_BYPASS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_CLOCK_SRC__OFFSET +CYFLD_PRGIO_PRT_CLOCK_SRC__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_CLOCK_SRC__SIZE +CYFLD_PRGIO_PRT_CLOCK_SRC__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_HLD_OVR__OFFSET +CYFLD_PRGIO_PRT_HLD_OVR__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_HLD_OVR__SIZE +CYFLD_PRGIO_PRT_HLD_OVR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_PIPELINE_EN__OFFSET +CYFLD_PRGIO_PRT_PIPELINE_EN__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_PIPELINE_EN__SIZE +CYFLD_PRGIO_PRT_PIPELINE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_ENABLED__OFFSET +CYFLD_PRGIO_PRT_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_ENABLED__SIZE +CYFLD_PRGIO_PRT_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_SYNC_CTL +CYREG_PRGIO_PRT0_SYNC_CTL EQU 0x40050010 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_IO_SYNC_EN__OFFSET +CYFLD_PRGIO_PRT_IO_SYNC_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_IO_SYNC_EN__SIZE +CYFLD_PRGIO_PRT_IO_SYNC_EN__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_CHIP_SYNC_EN__OFFSET +CYFLD_PRGIO_PRT_CHIP_SYNC_EN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_CHIP_SYNC_EN__SIZE +CYFLD_PRGIO_PRT_CHIP_SYNC_EN__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_SEL0 +CYREG_PRGIO_PRT0_LUT_SEL0 EQU 0x40050020 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_LUT_TR0_SEL__OFFSET +CYFLD_PRGIO_PRT_LUT_TR0_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_LUT_TR0_SEL__SIZE +CYFLD_PRGIO_PRT_LUT_TR0_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_LUT_TR1_SEL__OFFSET +CYFLD_PRGIO_PRT_LUT_TR1_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_LUT_TR1_SEL__SIZE +CYFLD_PRGIO_PRT_LUT_TR1_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_LUT_TR2_SEL__OFFSET +CYFLD_PRGIO_PRT_LUT_TR2_SEL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_LUT_TR2_SEL__SIZE +CYFLD_PRGIO_PRT_LUT_TR2_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_SEL1 +CYREG_PRGIO_PRT0_LUT_SEL1 EQU 0x40050024 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_SEL2 +CYREG_PRGIO_PRT0_LUT_SEL2 EQU 0x40050028 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_SEL3 +CYREG_PRGIO_PRT0_LUT_SEL3 EQU 0x4005002c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_SEL4 +CYREG_PRGIO_PRT0_LUT_SEL4 EQU 0x40050030 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_SEL5 +CYREG_PRGIO_PRT0_LUT_SEL5 EQU 0x40050034 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_SEL6 +CYREG_PRGIO_PRT0_LUT_SEL6 EQU 0x40050038 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_SEL7 +CYREG_PRGIO_PRT0_LUT_SEL7 EQU 0x4005003c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_CTL0 +CYREG_PRGIO_PRT0_LUT_CTL0 EQU 0x40050040 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_LUT__OFFSET +CYFLD_PRGIO_PRT_LUT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_LUT__SIZE +CYFLD_PRGIO_PRT_LUT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_LUT_OPC__OFFSET +CYFLD_PRGIO_PRT_LUT_OPC__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_LUT_OPC__SIZE +CYFLD_PRGIO_PRT_LUT_OPC__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_CTL1 +CYREG_PRGIO_PRT0_LUT_CTL1 EQU 0x40050044 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_CTL2 +CYREG_PRGIO_PRT0_LUT_CTL2 EQU 0x40050048 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_CTL3 +CYREG_PRGIO_PRT0_LUT_CTL3 EQU 0x4005004c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_CTL4 +CYREG_PRGIO_PRT0_LUT_CTL4 EQU 0x40050050 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_CTL5 +CYREG_PRGIO_PRT0_LUT_CTL5 EQU 0x40050054 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_CTL6 +CYREG_PRGIO_PRT0_LUT_CTL6 EQU 0x40050058 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_LUT_CTL7 +CYREG_PRGIO_PRT0_LUT_CTL7 EQU 0x4005005c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_DU_SEL +CYREG_PRGIO_PRT0_DU_SEL EQU 0x400500c0 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_TR0_SEL__OFFSET +CYFLD_PRGIO_PRT_DU_TR0_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_TR0_SEL__SIZE +CYFLD_PRGIO_PRT_DU_TR0_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_TR1_SEL__OFFSET +CYFLD_PRGIO_PRT_DU_TR1_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_TR1_SEL__SIZE +CYFLD_PRGIO_PRT_DU_TR1_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_TR2_SEL__OFFSET +CYFLD_PRGIO_PRT_DU_TR2_SEL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_TR2_SEL__SIZE +CYFLD_PRGIO_PRT_DU_TR2_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_DATA0_SEL__OFFSET +CYFLD_PRGIO_PRT_DU_DATA0_SEL__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_DATA0_SEL__SIZE +CYFLD_PRGIO_PRT_DU_DATA0_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_DATA1_SEL__OFFSET +CYFLD_PRGIO_PRT_DU_DATA1_SEL__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_DATA1_SEL__SIZE +CYFLD_PRGIO_PRT_DU_DATA1_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_DU_CTL +CYREG_PRGIO_PRT0_DU_CTL EQU 0x400500c4 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_SIZE__OFFSET +CYFLD_PRGIO_PRT_DU_SIZE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_SIZE__SIZE +CYFLD_PRGIO_PRT_DU_SIZE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_OPC__OFFSET +CYFLD_PRGIO_PRT_DU_OPC__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DU_OPC__SIZE +CYFLD_PRGIO_PRT_DU_OPC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT0_DATA +CYREG_PRGIO_PRT0_DATA EQU 0x400500f0 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DATA__OFFSET +CYFLD_PRGIO_PRT_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PRGIO_PRT_DATA__SIZE +CYFLD_PRGIO_PRT_DATA__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PRGIO_PRT1_BASE +CYDEV_PRGIO_PRT1_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_PRGIO_PRT1_SIZE +CYDEV_PRGIO_PRT1_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_CTL +CYREG_PRGIO_PRT1_CTL EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_SYNC_CTL +CYREG_PRGIO_PRT1_SYNC_CTL EQU 0x40050110 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_SEL0 +CYREG_PRGIO_PRT1_LUT_SEL0 EQU 0x40050120 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_SEL1 +CYREG_PRGIO_PRT1_LUT_SEL1 EQU 0x40050124 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_SEL2 +CYREG_PRGIO_PRT1_LUT_SEL2 EQU 0x40050128 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_SEL3 +CYREG_PRGIO_PRT1_LUT_SEL3 EQU 0x4005012c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_SEL4 +CYREG_PRGIO_PRT1_LUT_SEL4 EQU 0x40050130 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_SEL5 +CYREG_PRGIO_PRT1_LUT_SEL5 EQU 0x40050134 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_SEL6 +CYREG_PRGIO_PRT1_LUT_SEL6 EQU 0x40050138 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_SEL7 +CYREG_PRGIO_PRT1_LUT_SEL7 EQU 0x4005013c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_CTL0 +CYREG_PRGIO_PRT1_LUT_CTL0 EQU 0x40050140 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_CTL1 +CYREG_PRGIO_PRT1_LUT_CTL1 EQU 0x40050144 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_CTL2 +CYREG_PRGIO_PRT1_LUT_CTL2 EQU 0x40050148 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_CTL3 +CYREG_PRGIO_PRT1_LUT_CTL3 EQU 0x4005014c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_CTL4 +CYREG_PRGIO_PRT1_LUT_CTL4 EQU 0x40050150 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_CTL5 +CYREG_PRGIO_PRT1_LUT_CTL5 EQU 0x40050154 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_CTL6 +CYREG_PRGIO_PRT1_LUT_CTL6 EQU 0x40050158 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_LUT_CTL7 +CYREG_PRGIO_PRT1_LUT_CTL7 EQU 0x4005015c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_DU_SEL +CYREG_PRGIO_PRT1_DU_SEL EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_DU_CTL +CYREG_PRGIO_PRT1_DU_CTL EQU 0x400501c4 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT1_DATA +CYREG_PRGIO_PRT1_DATA EQU 0x400501f0 + ENDIF + IF :LNOT::DEF:CYDEV_PRGIO_PRT2_BASE +CYDEV_PRGIO_PRT2_BASE EQU 0x40050200 + ENDIF + IF :LNOT::DEF:CYDEV_PRGIO_PRT2_SIZE +CYDEV_PRGIO_PRT2_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_CTL +CYREG_PRGIO_PRT2_CTL EQU 0x40050200 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_SYNC_CTL +CYREG_PRGIO_PRT2_SYNC_CTL EQU 0x40050210 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_SEL0 +CYREG_PRGIO_PRT2_LUT_SEL0 EQU 0x40050220 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_SEL1 +CYREG_PRGIO_PRT2_LUT_SEL1 EQU 0x40050224 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_SEL2 +CYREG_PRGIO_PRT2_LUT_SEL2 EQU 0x40050228 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_SEL3 +CYREG_PRGIO_PRT2_LUT_SEL3 EQU 0x4005022c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_SEL4 +CYREG_PRGIO_PRT2_LUT_SEL4 EQU 0x40050230 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_SEL5 +CYREG_PRGIO_PRT2_LUT_SEL5 EQU 0x40050234 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_SEL6 +CYREG_PRGIO_PRT2_LUT_SEL6 EQU 0x40050238 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_SEL7 +CYREG_PRGIO_PRT2_LUT_SEL7 EQU 0x4005023c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_CTL0 +CYREG_PRGIO_PRT2_LUT_CTL0 EQU 0x40050240 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_CTL1 +CYREG_PRGIO_PRT2_LUT_CTL1 EQU 0x40050244 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_CTL2 +CYREG_PRGIO_PRT2_LUT_CTL2 EQU 0x40050248 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_CTL3 +CYREG_PRGIO_PRT2_LUT_CTL3 EQU 0x4005024c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_CTL4 +CYREG_PRGIO_PRT2_LUT_CTL4 EQU 0x40050250 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_CTL5 +CYREG_PRGIO_PRT2_LUT_CTL5 EQU 0x40050254 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_CTL6 +CYREG_PRGIO_PRT2_LUT_CTL6 EQU 0x40050258 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_LUT_CTL7 +CYREG_PRGIO_PRT2_LUT_CTL7 EQU 0x4005025c + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_DU_SEL +CYREG_PRGIO_PRT2_DU_SEL EQU 0x400502c0 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_DU_CTL +CYREG_PRGIO_PRT2_DU_CTL EQU 0x400502c4 + ENDIF + IF :LNOT::DEF:CYREG_PRGIO_PRT2_DATA +CYREG_PRGIO_PRT2_DATA EQU 0x400502f0 + ENDIF + IF :LNOT::DEF:CYDEV_CPUSS_BASE +CYDEV_CPUSS_BASE EQU 0x40100000 + ENDIF + IF :LNOT::DEF:CYDEV_CPUSS_SIZE +CYDEV_CPUSS_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_SYSREQ +CYREG_CPUSS_SYSREQ EQU 0x40100004 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SYSCALL_COMMAND__OFFSET +CYFLD_CPUSS_SYSCALL_COMMAND__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SYSCALL_COMMAND__SIZE +CYFLD_CPUSS_SYSCALL_COMMAND__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_DIS_RESET_VECT_REL__OFFSET +CYFLD_CPUSS_DIS_RESET_VECT_REL__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_DIS_RESET_VECT_REL__SIZE +CYFLD_CPUSS_DIS_RESET_VECT_REL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PRIVILEGED__OFFSET +CYFLD_CPUSS_PRIVILEGED__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PRIVILEGED__SIZE +CYFLD_CPUSS_PRIVILEGED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET +CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_ACCESS_EN__SIZE +CYFLD_CPUSS_ROM_ACCESS_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_HMASTER_0__OFFSET +CYFLD_CPUSS_HMASTER_0__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_HMASTER_0__SIZE +CYFLD_CPUSS_HMASTER_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SYSCALL_REQ__OFFSET +CYFLD_CPUSS_SYSCALL_REQ__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SYSCALL_REQ__SIZE +CYFLD_CPUSS_SYSCALL_REQ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_SYSARG +CYREG_CPUSS_SYSARG EQU 0x40100008 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SYSCALL_ARG__OFFSET +CYFLD_CPUSS_SYSCALL_ARG__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_SYSCALL_ARG__SIZE +CYFLD_CPUSS_SYSCALL_ARG__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PROTECTION +CYREG_CPUSS_PROTECTION EQU 0x4010000c + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROTECTION_MODE__OFFSET +CYFLD_CPUSS_PROTECTION_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROTECTION_MODE__SIZE +CYFLD_CPUSS_PROTECTION_MODE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_LOCK__OFFSET +CYFLD_CPUSS_FLASH_LOCK__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_LOCK__SIZE +CYFLD_CPUSS_FLASH_LOCK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROTECTION_LOCK__OFFSET +CYFLD_CPUSS_PROTECTION_LOCK__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PROTECTION_LOCK__SIZE +CYFLD_CPUSS_PROTECTION_LOCK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PRIV_ROM +CYREG_CPUSS_PRIV_ROM EQU 0x40100010 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET +CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE +CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PRIV_RAM +CYREG_CPUSS_PRIV_RAM EQU 0x40100014 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET +CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE +CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_PRIV_FLASH +CYREG_CPUSS_PRIV_FLASH EQU 0x40100018 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET +CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE +CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_WOUNDING +CYREG_CPUSS_WOUNDING EQU 0x4010001c + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_WOUND__OFFSET +CYFLD_CPUSS_RAM_WOUND__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_RAM_WOUND__SIZE +CYFLD_CPUSS_RAM_WOUND__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WOUND__OFFSET +CYFLD_CPUSS_FLASH_WOUND__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WOUND__SIZE +CYFLD_CPUSS_FLASH_WOUND__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_FLASH_CTL +CYREG_CPUSS_FLASH_CTL EQU 0x40100030 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WS__OFFSET +CYFLD_CPUSS_FLASH_WS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WS__SIZE +CYFLD_CPUSS_FLASH_WS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PREF_EN__OFFSET +CYFLD_CPUSS_PREF_EN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_PREF_EN__SIZE +CYFLD_CPUSS_PREF_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET +CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_INVALIDATE__SIZE +CYFLD_CPUSS_FLASH_INVALIDATE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ARB__OFFSET +CYFLD_CPUSS_ARB__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ARB__SIZE +CYFLD_CPUSS_ARB__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_ROM_CTL +CYREG_CPUSS_ROM_CTL EQU 0x40100034 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_WS__OFFSET +CYFLD_CPUSS_ROM_WS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CPUSS_ROM_WS__SIZE +CYFLD_CPUSS_ROM_WS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_RAM_CTL +CYREG_CPUSS_RAM_CTL EQU 0x40100038 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_DMAC_CTL +CYREG_CPUSS_DMAC_CTL EQU 0x4010003c + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_SL_CTL0 +CYREG_CPUSS_SL_CTL0 EQU 0x40100100 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_SL_CTL1 +CYREG_CPUSS_SL_CTL1 EQU 0x40100104 + ENDIF + IF :LNOT::DEF:CYREG_CPUSS_SL_CTL2 +CYREG_CPUSS_SL_CTL2 EQU 0x40100108 + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_BASE +CYDEV_DMAC_BASE EQU 0x40101000 + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_SIZE +CYDEV_DMAC_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_CTL +CYREG_DMAC_CTL EQU 0x40101000 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_ENABLED__OFFSET +CYFLD_DMAC_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_ENABLED__SIZE +CYFLD_DMAC_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_STATUS +CYREG_DMAC_STATUS EQU 0x40101010 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DATA_NR__OFFSET +CYFLD_DMAC_DATA_NR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DATA_NR__SIZE +CYFLD_DMAC_DATA_NR__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_CH_ADDR__OFFSET +CYFLD_DMAC_CH_ADDR__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_CH_ADDR__SIZE +CYFLD_DMAC_CH_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_STATE__OFFSET +CYFLD_DMAC_STATE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_STATE__SIZE +CYFLD_DMAC_STATE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_PRIO__OFFSET +CYFLD_DMAC_PRIO__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_PRIO__SIZE +CYFLD_DMAC_PRIO__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_PING_PONG__OFFSET +CYFLD_DMAC_PING_PONG__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_PING_PONG__SIZE +CYFLD_DMAC_PING_PONG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_ACTIVE__OFFSET +CYFLD_DMAC_ACTIVE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_ACTIVE__SIZE +CYFLD_DMAC_ACTIVE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_STATUS_SRC_ADDR +CYREG_DMAC_STATUS_SRC_ADDR EQU 0x40101014 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_ADDR__OFFSET +CYFLD_DMAC_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_ADDR__SIZE +CYFLD_DMAC_ADDR__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_STATUS_DST_ADDR +CYREG_DMAC_STATUS_DST_ADDR EQU 0x40101018 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_STATUS_CH_ACT +CYREG_DMAC_STATUS_CH_ACT EQU 0x4010101c + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_CH__OFFSET +CYFLD_DMAC_CH__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_CH__SIZE +CYFLD_DMAC_CH__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_CH_CTL0 +CYREG_DMAC_CH_CTL0 EQU 0x40101080 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_CH_CTL1 +CYREG_DMAC_CH_CTL1 EQU 0x40101084 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_CH_CTL2 +CYREG_DMAC_CH_CTL2 EQU 0x40101088 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_CH_CTL3 +CYREG_DMAC_CH_CTL3 EQU 0x4010108c + ENDIF + IF :LNOT::DEF:CYREG_DMAC_CH_CTL4 +CYREG_DMAC_CH_CTL4 EQU 0x40101090 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_CH_CTL5 +CYREG_DMAC_CH_CTL5 EQU 0x40101094 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_CH_CTL6 +CYREG_DMAC_CH_CTL6 EQU 0x40101098 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_CH_CTL7 +CYREG_DMAC_CH_CTL7 EQU 0x4010109c + ENDIF + IF :LNOT::DEF:CYREG_DMAC_INTR +CYREG_DMAC_INTR EQU 0x401017f0 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_INTR_SET +CYREG_DMAC_INTR_SET EQU 0x401017f4 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_INTR_MASK +CYREG_DMAC_INTR_MASK EQU 0x401017f8 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_INTR_MASKED +CYREG_DMAC_INTR_MASKED EQU 0x401017fc + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR0_BASE +CYDEV_DMAC_DESCR0_BASE EQU 0x40101800 + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR0_SIZE +CYDEV_DMAC_DESCR0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR0_PING_SRC +CYREG_DMAC_DESCR0_PING_SRC EQU 0x40101800 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_ADDR__OFFSET +CYFLD_DMAC_DESCR_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_ADDR__SIZE +CYFLD_DMAC_DESCR_ADDR__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR0_PING_DST +CYREG_DMAC_DESCR0_PING_DST EQU 0x40101804 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR0_PING_CTL +CYREG_DMAC_DESCR0_PING_CTL EQU 0x40101808 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_DATA_NR__OFFSET +CYFLD_DMAC_DESCR_DATA_NR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_DATA_NR__SIZE +CYFLD_DMAC_DESCR_DATA_NR__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_DATA_SIZE__OFFSET +CYFLD_DMAC_DESCR_DATA_SIZE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_DATA_SIZE__SIZE +CYFLD_DMAC_DESCR_DATA_SIZE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__OFFSET +CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__SIZE +CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_DST_ADDR_INCR__OFFSET +CYFLD_DMAC_DESCR_DST_ADDR_INCR__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_DST_ADDR_INCR__SIZE +CYFLD_DMAC_DESCR_DST_ADDR_INCR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__OFFSET +CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__SIZE +CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_SRC_ADDR_INCR__OFFSET +CYFLD_DMAC_DESCR_SRC_ADDR_INCR__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_SRC_ADDR_INCR__SIZE +CYFLD_DMAC_DESCR_SRC_ADDR_INCR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__OFFSET +CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__SIZE +CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_INV_DESCR__OFFSET +CYFLD_DMAC_DESCR_INV_DESCR__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_INV_DESCR__SIZE +CYFLD_DMAC_DESCR_INV_DESCR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_SET_CAUSE__OFFSET +CYFLD_DMAC_DESCR_SET_CAUSE__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_SET_CAUSE__SIZE +CYFLD_DMAC_DESCR_SET_CAUSE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_PREEMPTABLE__OFFSET +CYFLD_DMAC_DESCR_PREEMPTABLE__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_PREEMPTABLE__SIZE +CYFLD_DMAC_DESCR_PREEMPTABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_FLIPPING__OFFSET +CYFLD_DMAC_DESCR_FLIPPING__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_FLIPPING__SIZE +CYFLD_DMAC_DESCR_FLIPPING__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_OPCODE__OFFSET +CYFLD_DMAC_DESCR_OPCODE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_OPCODE__SIZE +CYFLD_DMAC_DESCR_OPCODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR0_PING_STATUS +CYREG_DMAC_DESCR0_PING_STATUS EQU 0x4010180c + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_CURR_DATA_NR__OFFSET +CYFLD_DMAC_DESCR_CURR_DATA_NR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_CURR_DATA_NR__SIZE +CYFLD_DMAC_DESCR_CURR_DATA_NR__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_RESPONSE__OFFSET +CYFLD_DMAC_DESCR_RESPONSE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_RESPONSE__SIZE +CYFLD_DMAC_DESCR_RESPONSE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_VALID__OFFSET +CYFLD_DMAC_DESCR_VALID__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_DMAC_DESCR_VALID__SIZE +CYFLD_DMAC_DESCR_VALID__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR0_PONG_SRC +CYREG_DMAC_DESCR0_PONG_SRC EQU 0x40101810 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR0_PONG_DST +CYREG_DMAC_DESCR0_PONG_DST EQU 0x40101814 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR0_PONG_CTL +CYREG_DMAC_DESCR0_PONG_CTL EQU 0x40101818 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR0_PONG_STATUS +CYREG_DMAC_DESCR0_PONG_STATUS EQU 0x4010181c + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR1_BASE +CYDEV_DMAC_DESCR1_BASE EQU 0x40101820 + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR1_SIZE +CYDEV_DMAC_DESCR1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR1_PING_SRC +CYREG_DMAC_DESCR1_PING_SRC EQU 0x40101820 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR1_PING_DST +CYREG_DMAC_DESCR1_PING_DST EQU 0x40101824 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR1_PING_CTL +CYREG_DMAC_DESCR1_PING_CTL EQU 0x40101828 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR1_PING_STATUS +CYREG_DMAC_DESCR1_PING_STATUS EQU 0x4010182c + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR1_PONG_SRC +CYREG_DMAC_DESCR1_PONG_SRC EQU 0x40101830 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR1_PONG_DST +CYREG_DMAC_DESCR1_PONG_DST EQU 0x40101834 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR1_PONG_CTL +CYREG_DMAC_DESCR1_PONG_CTL EQU 0x40101838 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR1_PONG_STATUS +CYREG_DMAC_DESCR1_PONG_STATUS EQU 0x4010183c + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR2_BASE +CYDEV_DMAC_DESCR2_BASE EQU 0x40101840 + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR2_SIZE +CYDEV_DMAC_DESCR2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR2_PING_SRC +CYREG_DMAC_DESCR2_PING_SRC EQU 0x40101840 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR2_PING_DST +CYREG_DMAC_DESCR2_PING_DST EQU 0x40101844 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR2_PING_CTL +CYREG_DMAC_DESCR2_PING_CTL EQU 0x40101848 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR2_PING_STATUS +CYREG_DMAC_DESCR2_PING_STATUS EQU 0x4010184c + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR2_PONG_SRC +CYREG_DMAC_DESCR2_PONG_SRC EQU 0x40101850 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR2_PONG_DST +CYREG_DMAC_DESCR2_PONG_DST EQU 0x40101854 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR2_PONG_CTL +CYREG_DMAC_DESCR2_PONG_CTL EQU 0x40101858 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR2_PONG_STATUS +CYREG_DMAC_DESCR2_PONG_STATUS EQU 0x4010185c + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR3_BASE +CYDEV_DMAC_DESCR3_BASE EQU 0x40101860 + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR3_SIZE +CYDEV_DMAC_DESCR3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR3_PING_SRC +CYREG_DMAC_DESCR3_PING_SRC EQU 0x40101860 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR3_PING_DST +CYREG_DMAC_DESCR3_PING_DST EQU 0x40101864 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR3_PING_CTL +CYREG_DMAC_DESCR3_PING_CTL EQU 0x40101868 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR3_PING_STATUS +CYREG_DMAC_DESCR3_PING_STATUS EQU 0x4010186c + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR3_PONG_SRC +CYREG_DMAC_DESCR3_PONG_SRC EQU 0x40101870 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR3_PONG_DST +CYREG_DMAC_DESCR3_PONG_DST EQU 0x40101874 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR3_PONG_CTL +CYREG_DMAC_DESCR3_PONG_CTL EQU 0x40101878 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR3_PONG_STATUS +CYREG_DMAC_DESCR3_PONG_STATUS EQU 0x4010187c + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR4_BASE +CYDEV_DMAC_DESCR4_BASE EQU 0x40101880 + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR4_SIZE +CYDEV_DMAC_DESCR4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR4_PING_SRC +CYREG_DMAC_DESCR4_PING_SRC EQU 0x40101880 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR4_PING_DST +CYREG_DMAC_DESCR4_PING_DST EQU 0x40101884 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR4_PING_CTL +CYREG_DMAC_DESCR4_PING_CTL EQU 0x40101888 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR4_PING_STATUS +CYREG_DMAC_DESCR4_PING_STATUS EQU 0x4010188c + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR4_PONG_SRC +CYREG_DMAC_DESCR4_PONG_SRC EQU 0x40101890 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR4_PONG_DST +CYREG_DMAC_DESCR4_PONG_DST EQU 0x40101894 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR4_PONG_CTL +CYREG_DMAC_DESCR4_PONG_CTL EQU 0x40101898 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR4_PONG_STATUS +CYREG_DMAC_DESCR4_PONG_STATUS EQU 0x4010189c + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR5_BASE +CYDEV_DMAC_DESCR5_BASE EQU 0x401018a0 + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR5_SIZE +CYDEV_DMAC_DESCR5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR5_PING_SRC +CYREG_DMAC_DESCR5_PING_SRC EQU 0x401018a0 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR5_PING_DST +CYREG_DMAC_DESCR5_PING_DST EQU 0x401018a4 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR5_PING_CTL +CYREG_DMAC_DESCR5_PING_CTL EQU 0x401018a8 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR5_PING_STATUS +CYREG_DMAC_DESCR5_PING_STATUS EQU 0x401018ac + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR5_PONG_SRC +CYREG_DMAC_DESCR5_PONG_SRC EQU 0x401018b0 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR5_PONG_DST +CYREG_DMAC_DESCR5_PONG_DST EQU 0x401018b4 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR5_PONG_CTL +CYREG_DMAC_DESCR5_PONG_CTL EQU 0x401018b8 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR5_PONG_STATUS +CYREG_DMAC_DESCR5_PONG_STATUS EQU 0x401018bc + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR6_BASE +CYDEV_DMAC_DESCR6_BASE EQU 0x401018c0 + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR6_SIZE +CYDEV_DMAC_DESCR6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR6_PING_SRC +CYREG_DMAC_DESCR6_PING_SRC EQU 0x401018c0 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR6_PING_DST +CYREG_DMAC_DESCR6_PING_DST EQU 0x401018c4 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR6_PING_CTL +CYREG_DMAC_DESCR6_PING_CTL EQU 0x401018c8 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR6_PING_STATUS +CYREG_DMAC_DESCR6_PING_STATUS EQU 0x401018cc + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR6_PONG_SRC +CYREG_DMAC_DESCR6_PONG_SRC EQU 0x401018d0 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR6_PONG_DST +CYREG_DMAC_DESCR6_PONG_DST EQU 0x401018d4 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR6_PONG_CTL +CYREG_DMAC_DESCR6_PONG_CTL EQU 0x401018d8 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR6_PONG_STATUS +CYREG_DMAC_DESCR6_PONG_STATUS EQU 0x401018dc + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR7_BASE +CYDEV_DMAC_DESCR7_BASE EQU 0x401018e0 + ENDIF + IF :LNOT::DEF:CYDEV_DMAC_DESCR7_SIZE +CYDEV_DMAC_DESCR7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR7_PING_SRC +CYREG_DMAC_DESCR7_PING_SRC EQU 0x401018e0 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR7_PING_DST +CYREG_DMAC_DESCR7_PING_DST EQU 0x401018e4 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR7_PING_CTL +CYREG_DMAC_DESCR7_PING_CTL EQU 0x401018e8 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR7_PING_STATUS +CYREG_DMAC_DESCR7_PING_STATUS EQU 0x401018ec + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR7_PONG_SRC +CYREG_DMAC_DESCR7_PONG_SRC EQU 0x401018f0 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR7_PONG_DST +CYREG_DMAC_DESCR7_PONG_DST EQU 0x401018f4 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR7_PONG_CTL +CYREG_DMAC_DESCR7_PONG_CTL EQU 0x401018f8 + ENDIF + IF :LNOT::DEF:CYREG_DMAC_DESCR7_PONG_STATUS +CYREG_DMAC_DESCR7_PONG_STATUS EQU 0x401018fc + ENDIF + IF :LNOT::DEF:CYDEV_SPCIF_BASE +CYDEV_SPCIF_BASE EQU 0x40110000 + ENDIF + IF :LNOT::DEF:CYDEV_SPCIF_SIZE +CYDEV_SPCIF_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SPCIF_GEOMETRY +CYREG_SPCIF_GEOMETRY EQU 0x40110000 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH__OFFSET +CYFLD_SPCIF_FLASH__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH__SIZE +CYFLD_SPCIF_FLASH__SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_SFLASH__OFFSET +CYFLD_SPCIF_SFLASH__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_SFLASH__SIZE +CYFLD_SPCIF_SFLASH__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_NUM_FLASH__OFFSET +CYFLD_SPCIF_NUM_FLASH__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_NUM_FLASH__SIZE +CYFLD_SPCIF_NUM_FLASH__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH_ROW__OFFSET +CYFLD_SPCIF_FLASH_ROW__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_FLASH_ROW__SIZE +CYFLD_SPCIF_FLASH_ROW__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_DE_CPD_LP__OFFSET +CYFLD_SPCIF_DE_CPD_LP__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_DE_CPD_LP__SIZE +CYFLD_SPCIF_DE_CPD_LP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SPCIF_INTR +CYREG_SPCIF_INTR EQU 0x401107f0 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_TIMER__OFFSET +CYFLD_SPCIF_TIMER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SPCIF_TIMER__SIZE +CYFLD_SPCIF_TIMER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SPCIF_INTR_SET +CYREG_SPCIF_INTR_SET EQU 0x401107f4 + ENDIF + IF :LNOT::DEF:CYREG_SPCIF_INTR_MASK +CYREG_SPCIF_INTR_MASK EQU 0x401107f8 + ENDIF + IF :LNOT::DEF:CYREG_SPCIF_INTR_MASKED +CYREG_SPCIF_INTR_MASKED EQU 0x401107fc + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_BASE +CYDEV_TCPWM_BASE EQU 0x40200000 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_SIZE +CYDEV_TCPWM_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CTRL +CYREG_TCPWM_CTRL EQU 0x40200000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_ENABLED__OFFSET +CYFLD_TCPWM_COUNTER_ENABLED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_ENABLED__SIZE +CYFLD_TCPWM_COUNTER_ENABLED__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CMD +CYREG_TCPWM_CMD EQU 0x40200008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET +CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_CAPTURE__SIZE +CYFLD_TCPWM_COUNTER_CAPTURE__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_RELOAD__OFFSET +CYFLD_TCPWM_COUNTER_RELOAD__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_RELOAD__SIZE +CYFLD_TCPWM_COUNTER_RELOAD__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_STOP__OFFSET +CYFLD_TCPWM_COUNTER_STOP__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_STOP__SIZE +CYFLD_TCPWM_COUNTER_STOP__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_START__OFFSET +CYFLD_TCPWM_COUNTER_START__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_START__SIZE +CYFLD_TCPWM_COUNTER_START__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_INTR_CAUSE +CYREG_TCPWM_INTR_CAUSE EQU 0x4020000c + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_INT__OFFSET +CYFLD_TCPWM_COUNTER_INT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_COUNTER_INT__SIZE +CYFLD_TCPWM_COUNTER_INT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT0_BASE +CYDEV_TCPWM_CNT0_BASE EQU 0x40200100 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT0_SIZE +CYDEV_TCPWM_CNT0_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_CTRL +CYREG_TCPWM_CNT0_CTRL EQU 0x40200100 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET +CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE +CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET +CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE +CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET +CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE +CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET +CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE +CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_GENERIC__OFFSET +CYFLD_TCPWM_CNT_GENERIC__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_GENERIC__SIZE +CYFLD_TCPWM_CNT_GENERIC__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY1 +CYVAL_TCPWM_CNT_GENERIC_DIVBY1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY2 +CYVAL_TCPWM_CNT_GENERIC_DIVBY2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY4 +CYVAL_TCPWM_CNT_GENERIC_DIVBY4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY8 +CYVAL_TCPWM_CNT_GENERIC_DIVBY8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY16 +CYVAL_TCPWM_CNT_GENERIC_DIVBY16 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY32 +CYVAL_TCPWM_CNT_GENERIC_DIVBY32 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY64 +CYVAL_TCPWM_CNT_GENERIC_DIVBY64 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_GENERIC_DIVBY128 +CYVAL_TCPWM_CNT_GENERIC_DIVBY128 EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET +CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE +CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 +CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET +CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_ONE_SHOT__SIZE +CYFLD_TCPWM_CNT_ONE_SHOT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET +CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE +CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 +CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 +CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 +CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT +CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT +CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_MODE__OFFSET +CYFLD_TCPWM_CNT_MODE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_MODE__SIZE +CYFLD_TCPWM_CNT_MODE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_TIMER +CYVAL_TCPWM_CNT_MODE_TIMER EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_CAPTURE +CYVAL_TCPWM_CNT_MODE_CAPTURE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_QUAD +CYVAL_TCPWM_CNT_MODE_QUAD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_PWM +CYVAL_TCPWM_CNT_MODE_PWM EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_PWM_DT +CYVAL_TCPWM_CNT_MODE_PWM_DT EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_MODE_PWM_PR +CYVAL_TCPWM_CNT_MODE_PWM_PR EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_STATUS +CYREG_TCPWM_CNT0_STATUS EQU 0x40200104 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_DOWN__OFFSET +CYFLD_TCPWM_CNT_DOWN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_DOWN__SIZE +CYFLD_TCPWM_CNT_DOWN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RUNNING__OFFSET +CYFLD_TCPWM_CNT_RUNNING__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RUNNING__SIZE +CYFLD_TCPWM_CNT_RUNNING__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_COUNTER +CYREG_TCPWM_CNT0_COUNTER EQU 0x40200108 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNTER__OFFSET +CYFLD_TCPWM_CNT_COUNTER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNTER__SIZE +CYFLD_TCPWM_CNT_COUNTER__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_CC +CYREG_TCPWM_CNT0_CC EQU 0x4020010c + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC__OFFSET +CYFLD_TCPWM_CNT_CC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC__SIZE +CYFLD_TCPWM_CNT_CC__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_CC_BUFF +CYREG_TCPWM_CNT0_CC_BUFF EQU 0x40200110 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_PERIOD +CYREG_TCPWM_CNT0_PERIOD EQU 0x40200114 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PERIOD__OFFSET +CYFLD_TCPWM_CNT_PERIOD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_PERIOD__SIZE +CYFLD_TCPWM_CNT_PERIOD__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_PERIOD_BUFF +CYREG_TCPWM_CNT0_PERIOD_BUFF EQU 0x40200118 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_TR_CTRL0 +CYREG_TCPWM_CNT0_TR_CTRL0 EQU 0x40200120 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET +CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE +CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET +CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_SEL__SIZE +CYFLD_TCPWM_CNT_COUNT_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET +CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE +CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_SEL__OFFSET +CYFLD_TCPWM_CNT_STOP_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_SEL__SIZE +CYFLD_TCPWM_CNT_STOP_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_SEL__OFFSET +CYFLD_TCPWM_CNT_START_SEL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_SEL__SIZE +CYFLD_TCPWM_CNT_START_SEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_TR_CTRL1 +CYREG_TCPWM_CNT0_TR_CTRL1 EQU 0x40200124 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET +CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE +CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET +CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE +CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET +CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE +CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET +CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_STOP_EDGE__SIZE +CYFLD_TCPWM_CNT_STOP_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_EDGE__OFFSET +CYFLD_TCPWM_CNT_START_EDGE__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_START_EDGE__SIZE +CYFLD_TCPWM_CNT_START_EDGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE +CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE +CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES +CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET +CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_TR_CTRL2 +CYREG_TCPWM_CNT0_TR_CTRL2 EQU 0x40200128 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET +CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE +CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET +CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR +CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT +CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE +CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET +CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE +CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET +CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR +CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT +CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE +CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET +CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE +CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE +CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR +CYREG_TCPWM_CNT0_INTR EQU 0x40200130 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_TC__OFFSET +CYFLD_TCPWM_CNT_TC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_TC__SIZE +CYFLD_TCPWM_CNT_TC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH__OFFSET +CYFLD_TCPWM_CNT_CC_MATCH__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_TCPWM_CNT_CC_MATCH__SIZE +CYFLD_TCPWM_CNT_CC_MATCH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR_SET +CYREG_TCPWM_CNT0_INTR_SET EQU 0x40200134 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR_MASK +CYREG_TCPWM_CNT0_INTR_MASK EQU 0x40200138 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT0_INTR_MASKED +CYREG_TCPWM_CNT0_INTR_MASKED EQU 0x4020013c + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT1_BASE +CYDEV_TCPWM_CNT1_BASE EQU 0x40200140 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT1_SIZE +CYDEV_TCPWM_CNT1_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_CTRL +CYREG_TCPWM_CNT1_CTRL EQU 0x40200140 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_STATUS +CYREG_TCPWM_CNT1_STATUS EQU 0x40200144 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_COUNTER +CYREG_TCPWM_CNT1_COUNTER EQU 0x40200148 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_CC +CYREG_TCPWM_CNT1_CC EQU 0x4020014c + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_CC_BUFF +CYREG_TCPWM_CNT1_CC_BUFF EQU 0x40200150 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_PERIOD +CYREG_TCPWM_CNT1_PERIOD EQU 0x40200154 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_PERIOD_BUFF +CYREG_TCPWM_CNT1_PERIOD_BUFF EQU 0x40200158 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_TR_CTRL0 +CYREG_TCPWM_CNT1_TR_CTRL0 EQU 0x40200160 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_TR_CTRL1 +CYREG_TCPWM_CNT1_TR_CTRL1 EQU 0x40200164 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_TR_CTRL2 +CYREG_TCPWM_CNT1_TR_CTRL2 EQU 0x40200168 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR +CYREG_TCPWM_CNT1_INTR EQU 0x40200170 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR_SET +CYREG_TCPWM_CNT1_INTR_SET EQU 0x40200174 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR_MASK +CYREG_TCPWM_CNT1_INTR_MASK EQU 0x40200178 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT1_INTR_MASKED +CYREG_TCPWM_CNT1_INTR_MASKED EQU 0x4020017c + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT2_BASE +CYDEV_TCPWM_CNT2_BASE EQU 0x40200180 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT2_SIZE +CYDEV_TCPWM_CNT2_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_CTRL +CYREG_TCPWM_CNT2_CTRL EQU 0x40200180 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_STATUS +CYREG_TCPWM_CNT2_STATUS EQU 0x40200184 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_COUNTER +CYREG_TCPWM_CNT2_COUNTER EQU 0x40200188 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_CC +CYREG_TCPWM_CNT2_CC EQU 0x4020018c + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_CC_BUFF +CYREG_TCPWM_CNT2_CC_BUFF EQU 0x40200190 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_PERIOD +CYREG_TCPWM_CNT2_PERIOD EQU 0x40200194 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_PERIOD_BUFF +CYREG_TCPWM_CNT2_PERIOD_BUFF EQU 0x40200198 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_TR_CTRL0 +CYREG_TCPWM_CNT2_TR_CTRL0 EQU 0x402001a0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_TR_CTRL1 +CYREG_TCPWM_CNT2_TR_CTRL1 EQU 0x402001a4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_TR_CTRL2 +CYREG_TCPWM_CNT2_TR_CTRL2 EQU 0x402001a8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR +CYREG_TCPWM_CNT2_INTR EQU 0x402001b0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR_SET +CYREG_TCPWM_CNT2_INTR_SET EQU 0x402001b4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR_MASK +CYREG_TCPWM_CNT2_INTR_MASK EQU 0x402001b8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT2_INTR_MASKED +CYREG_TCPWM_CNT2_INTR_MASKED EQU 0x402001bc + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT3_BASE +CYDEV_TCPWM_CNT3_BASE EQU 0x402001c0 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT3_SIZE +CYDEV_TCPWM_CNT3_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_CTRL +CYREG_TCPWM_CNT3_CTRL EQU 0x402001c0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_STATUS +CYREG_TCPWM_CNT3_STATUS EQU 0x402001c4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_COUNTER +CYREG_TCPWM_CNT3_COUNTER EQU 0x402001c8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_CC +CYREG_TCPWM_CNT3_CC EQU 0x402001cc + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_CC_BUFF +CYREG_TCPWM_CNT3_CC_BUFF EQU 0x402001d0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_PERIOD +CYREG_TCPWM_CNT3_PERIOD EQU 0x402001d4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_PERIOD_BUFF +CYREG_TCPWM_CNT3_PERIOD_BUFF EQU 0x402001d8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_TR_CTRL0 +CYREG_TCPWM_CNT3_TR_CTRL0 EQU 0x402001e0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_TR_CTRL1 +CYREG_TCPWM_CNT3_TR_CTRL1 EQU 0x402001e4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_TR_CTRL2 +CYREG_TCPWM_CNT3_TR_CTRL2 EQU 0x402001e8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR +CYREG_TCPWM_CNT3_INTR EQU 0x402001f0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR_SET +CYREG_TCPWM_CNT3_INTR_SET EQU 0x402001f4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR_MASK +CYREG_TCPWM_CNT3_INTR_MASK EQU 0x402001f8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT3_INTR_MASKED +CYREG_TCPWM_CNT3_INTR_MASKED EQU 0x402001fc + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT4_BASE +CYDEV_TCPWM_CNT4_BASE EQU 0x40200200 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT4_SIZE +CYDEV_TCPWM_CNT4_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_CTRL +CYREG_TCPWM_CNT4_CTRL EQU 0x40200200 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_STATUS +CYREG_TCPWM_CNT4_STATUS EQU 0x40200204 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_COUNTER +CYREG_TCPWM_CNT4_COUNTER EQU 0x40200208 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_CC +CYREG_TCPWM_CNT4_CC EQU 0x4020020c + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_CC_BUFF +CYREG_TCPWM_CNT4_CC_BUFF EQU 0x40200210 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_PERIOD +CYREG_TCPWM_CNT4_PERIOD EQU 0x40200214 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_PERIOD_BUFF +CYREG_TCPWM_CNT4_PERIOD_BUFF EQU 0x40200218 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_TR_CTRL0 +CYREG_TCPWM_CNT4_TR_CTRL0 EQU 0x40200220 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_TR_CTRL1 +CYREG_TCPWM_CNT4_TR_CTRL1 EQU 0x40200224 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_TR_CTRL2 +CYREG_TCPWM_CNT4_TR_CTRL2 EQU 0x40200228 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_INTR +CYREG_TCPWM_CNT4_INTR EQU 0x40200230 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_INTR_SET +CYREG_TCPWM_CNT4_INTR_SET EQU 0x40200234 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_INTR_MASK +CYREG_TCPWM_CNT4_INTR_MASK EQU 0x40200238 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT4_INTR_MASKED +CYREG_TCPWM_CNT4_INTR_MASKED EQU 0x4020023c + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT5_BASE +CYDEV_TCPWM_CNT5_BASE EQU 0x40200240 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT5_SIZE +CYDEV_TCPWM_CNT5_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_CTRL +CYREG_TCPWM_CNT5_CTRL EQU 0x40200240 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_STATUS +CYREG_TCPWM_CNT5_STATUS EQU 0x40200244 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_COUNTER +CYREG_TCPWM_CNT5_COUNTER EQU 0x40200248 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_CC +CYREG_TCPWM_CNT5_CC EQU 0x4020024c + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_CC_BUFF +CYREG_TCPWM_CNT5_CC_BUFF EQU 0x40200250 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_PERIOD +CYREG_TCPWM_CNT5_PERIOD EQU 0x40200254 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_PERIOD_BUFF +CYREG_TCPWM_CNT5_PERIOD_BUFF EQU 0x40200258 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_TR_CTRL0 +CYREG_TCPWM_CNT5_TR_CTRL0 EQU 0x40200260 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_TR_CTRL1 +CYREG_TCPWM_CNT5_TR_CTRL1 EQU 0x40200264 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_TR_CTRL2 +CYREG_TCPWM_CNT5_TR_CTRL2 EQU 0x40200268 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_INTR +CYREG_TCPWM_CNT5_INTR EQU 0x40200270 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_INTR_SET +CYREG_TCPWM_CNT5_INTR_SET EQU 0x40200274 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_INTR_MASK +CYREG_TCPWM_CNT5_INTR_MASK EQU 0x40200278 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT5_INTR_MASKED +CYREG_TCPWM_CNT5_INTR_MASKED EQU 0x4020027c + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT6_BASE +CYDEV_TCPWM_CNT6_BASE EQU 0x40200280 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT6_SIZE +CYDEV_TCPWM_CNT6_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_CTRL +CYREG_TCPWM_CNT6_CTRL EQU 0x40200280 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_STATUS +CYREG_TCPWM_CNT6_STATUS EQU 0x40200284 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_COUNTER +CYREG_TCPWM_CNT6_COUNTER EQU 0x40200288 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_CC +CYREG_TCPWM_CNT6_CC EQU 0x4020028c + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_CC_BUFF +CYREG_TCPWM_CNT6_CC_BUFF EQU 0x40200290 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_PERIOD +CYREG_TCPWM_CNT6_PERIOD EQU 0x40200294 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_PERIOD_BUFF +CYREG_TCPWM_CNT6_PERIOD_BUFF EQU 0x40200298 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_TR_CTRL0 +CYREG_TCPWM_CNT6_TR_CTRL0 EQU 0x402002a0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_TR_CTRL1 +CYREG_TCPWM_CNT6_TR_CTRL1 EQU 0x402002a4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_TR_CTRL2 +CYREG_TCPWM_CNT6_TR_CTRL2 EQU 0x402002a8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_INTR +CYREG_TCPWM_CNT6_INTR EQU 0x402002b0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_INTR_SET +CYREG_TCPWM_CNT6_INTR_SET EQU 0x402002b4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_INTR_MASK +CYREG_TCPWM_CNT6_INTR_MASK EQU 0x402002b8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT6_INTR_MASKED +CYREG_TCPWM_CNT6_INTR_MASKED EQU 0x402002bc + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT7_BASE +CYDEV_TCPWM_CNT7_BASE EQU 0x402002c0 + ENDIF + IF :LNOT::DEF:CYDEV_TCPWM_CNT7_SIZE +CYDEV_TCPWM_CNT7_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_CTRL +CYREG_TCPWM_CNT7_CTRL EQU 0x402002c0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_STATUS +CYREG_TCPWM_CNT7_STATUS EQU 0x402002c4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_COUNTER +CYREG_TCPWM_CNT7_COUNTER EQU 0x402002c8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_CC +CYREG_TCPWM_CNT7_CC EQU 0x402002cc + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_CC_BUFF +CYREG_TCPWM_CNT7_CC_BUFF EQU 0x402002d0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_PERIOD +CYREG_TCPWM_CNT7_PERIOD EQU 0x402002d4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_PERIOD_BUFF +CYREG_TCPWM_CNT7_PERIOD_BUFF EQU 0x402002d8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_TR_CTRL0 +CYREG_TCPWM_CNT7_TR_CTRL0 EQU 0x402002e0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_TR_CTRL1 +CYREG_TCPWM_CNT7_TR_CTRL1 EQU 0x402002e4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_TR_CTRL2 +CYREG_TCPWM_CNT7_TR_CTRL2 EQU 0x402002e8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_INTR +CYREG_TCPWM_CNT7_INTR EQU 0x402002f0 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_INTR_SET +CYREG_TCPWM_CNT7_INTR_SET EQU 0x402002f4 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_INTR_MASK +CYREG_TCPWM_CNT7_INTR_MASK EQU 0x402002f8 + ENDIF + IF :LNOT::DEF:CYREG_TCPWM_CNT7_INTR_MASKED +CYREG_TCPWM_CNT7_INTR_MASKED EQU 0x402002fc + ENDIF + IF :LNOT::DEF:CYDEV_WCO_BASE +CYDEV_WCO_BASE EQU 0x40220000 + ENDIF + IF :LNOT::DEF:CYDEV_WCO_SIZE +CYDEV_WCO_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_WCO_CONFIG +CYREG_WCO_CONFIG EQU 0x40220000 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_LPM_EN__OFFSET +CYFLD_WCO_LPM_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_LPM_EN__SIZE +CYFLD_WCO_LPM_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_LPM_AUTO__OFFSET +CYFLD_WCO_LPM_AUTO__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_LPM_AUTO__SIZE +CYFLD_WCO_LPM_AUTO__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_EXT_INPUT_EN__OFFSET +CYFLD_WCO_EXT_INPUT_EN__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_EXT_INPUT_EN__SIZE +CYFLD_WCO_EXT_INPUT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_ENBUS__OFFSET +CYFLD_WCO_ENBUS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_ENBUS__SIZE +CYFLD_WCO_ENBUS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_DPLL_ENABLE__OFFSET +CYFLD_WCO_DPLL_ENABLE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_WCO_DPLL_ENABLE__SIZE +CYFLD_WCO_DPLL_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_IP_ENABLE__OFFSET +CYFLD_WCO_IP_ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_WCO_IP_ENABLE__SIZE +CYFLD_WCO_IP_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_WCO_STATUS +CYREG_WCO_STATUS EQU 0x40220004 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_OUT_BLNK_A__OFFSET +CYFLD_WCO_OUT_BLNK_A__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_OUT_BLNK_A__SIZE +CYFLD_WCO_OUT_BLNK_A__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_WCO_DPLL +CYREG_WCO_DPLL EQU 0x40220008 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_DPLL_MULT__OFFSET +CYFLD_WCO_DPLL_MULT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_DPLL_MULT__SIZE +CYFLD_WCO_DPLL_MULT__SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_WCO_DPLL_LF_IGAIN__OFFSET +CYFLD_WCO_DPLL_LF_IGAIN__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_DPLL_LF_IGAIN__SIZE +CYFLD_WCO_DPLL_LF_IGAIN__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_DPLL_LF_PGAIN__OFFSET +CYFLD_WCO_DPLL_LF_PGAIN__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_DPLL_LF_PGAIN__SIZE +CYFLD_WCO_DPLL_LF_PGAIN__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_DPLL_LF_LIMIT__OFFSET +CYFLD_WCO_DPLL_LF_LIMIT__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_DPLL_LF_LIMIT__SIZE +CYFLD_WCO_DPLL_LF_LIMIT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_WCO_WDT_CTRLOW +CYREG_WCO_WDT_CTRLOW EQU 0x40220200 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CTR0__OFFSET +CYFLD_WCO_WDT_CTR0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CTR0__SIZE +CYFLD_WCO_WDT_CTR0__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CTR1__OFFSET +CYFLD_WCO_WDT_CTR1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CTR1__SIZE +CYFLD_WCO_WDT_CTR1__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_WCO_WDT_CTRHIGH +CYREG_WCO_WDT_CTRHIGH EQU 0x40220204 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CTR2__OFFSET +CYFLD_WCO_WDT_CTR2__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CTR2__SIZE +CYFLD_WCO_WDT_CTR2__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_WCO_WDT_MATCH +CYREG_WCO_WDT_MATCH EQU 0x40220208 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_MATCH0__OFFSET +CYFLD_WCO_WDT_MATCH0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_MATCH0__SIZE +CYFLD_WCO_WDT_MATCH0__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_MATCH1__OFFSET +CYFLD_WCO_WDT_MATCH1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_MATCH1__SIZE +CYFLD_WCO_WDT_MATCH1__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_WCO_WDT_CONFIG +CYREG_WCO_WDT_CONFIG EQU 0x4022020c + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_MODE0__OFFSET +CYFLD_WCO_WDT_MODE0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_MODE0__SIZE +CYFLD_WCO_WDT_MODE0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_WCO_WDT_MODE0_NOTHING +CYVAL_WCO_WDT_MODE0_NOTHING EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_WCO_WDT_MODE0_INT +CYVAL_WCO_WDT_MODE0_INT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_WCO_WDT_MODE0_RESET +CYVAL_WCO_WDT_MODE0_RESET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_WCO_WDT_MODE0_INT_THEN_RESET +CYVAL_WCO_WDT_MODE0_INT_THEN_RESET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CLEAR0__OFFSET +CYFLD_WCO_WDT_CLEAR0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CLEAR0__SIZE +CYFLD_WCO_WDT_CLEAR0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CASCADE0_1__OFFSET +CYFLD_WCO_WDT_CASCADE0_1__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CASCADE0_1__SIZE +CYFLD_WCO_WDT_CASCADE0_1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_MODE1__OFFSET +CYFLD_WCO_WDT_MODE1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_MODE1__SIZE +CYFLD_WCO_WDT_MODE1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_WCO_WDT_MODE1_NOTHING +CYVAL_WCO_WDT_MODE1_NOTHING EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_WCO_WDT_MODE1_INT +CYVAL_WCO_WDT_MODE1_INT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_WCO_WDT_MODE1_RESET +CYVAL_WCO_WDT_MODE1_RESET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_WCO_WDT_MODE1_INT_THEN_RESET +CYVAL_WCO_WDT_MODE1_INT_THEN_RESET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CLEAR1__OFFSET +CYFLD_WCO_WDT_CLEAR1__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CLEAR1__SIZE +CYFLD_WCO_WDT_CLEAR1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CASCADE1_2__OFFSET +CYFLD_WCO_WDT_CASCADE1_2__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_CASCADE1_2__SIZE +CYFLD_WCO_WDT_CASCADE1_2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_MODE2__OFFSET +CYFLD_WCO_WDT_MODE2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_MODE2__SIZE +CYFLD_WCO_WDT_MODE2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_WCO_WDT_MODE2_NOTHING +CYVAL_WCO_WDT_MODE2_NOTHING EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_WCO_WDT_MODE2_INT +CYVAL_WCO_WDT_MODE2_INT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_BITS2__OFFSET +CYFLD_WCO_WDT_BITS2__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_BITS2__SIZE +CYFLD_WCO_WDT_BITS2__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_LFCLK_SEL__OFFSET +CYFLD_WCO_LFCLK_SEL__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_WCO_LFCLK_SEL__SIZE +CYFLD_WCO_LFCLK_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_WCO_WDT_CONTROL +CYREG_WCO_WDT_CONTROL EQU 0x40220210 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLE0__OFFSET +CYFLD_WCO_WDT_ENABLE0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLE0__SIZE +CYFLD_WCO_WDT_ENABLE0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLED0__OFFSET +CYFLD_WCO_WDT_ENABLED0__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLED0__SIZE +CYFLD_WCO_WDT_ENABLED0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_INT0__OFFSET +CYFLD_WCO_WDT_INT0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_INT0__SIZE +CYFLD_WCO_WDT_INT0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_RESET0__OFFSET +CYFLD_WCO_WDT_RESET0__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_RESET0__SIZE +CYFLD_WCO_WDT_RESET0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLE1__OFFSET +CYFLD_WCO_WDT_ENABLE1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLE1__SIZE +CYFLD_WCO_WDT_ENABLE1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLED1__OFFSET +CYFLD_WCO_WDT_ENABLED1__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLED1__SIZE +CYFLD_WCO_WDT_ENABLED1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_INT1__OFFSET +CYFLD_WCO_WDT_INT1__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_INT1__SIZE +CYFLD_WCO_WDT_INT1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_RESET1__OFFSET +CYFLD_WCO_WDT_RESET1__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_RESET1__SIZE +CYFLD_WCO_WDT_RESET1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLE2__OFFSET +CYFLD_WCO_WDT_ENABLE2__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLE2__SIZE +CYFLD_WCO_WDT_ENABLE2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLED2__OFFSET +CYFLD_WCO_WDT_ENABLED2__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_ENABLED2__SIZE +CYFLD_WCO_WDT_ENABLED2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_INT2__OFFSET +CYFLD_WCO_WDT_INT2__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_INT2__SIZE +CYFLD_WCO_WDT_INT2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_RESET2__OFFSET +CYFLD_WCO_WDT_RESET2__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_WDT_RESET2__SIZE +CYFLD_WCO_WDT_RESET2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_WCO_WDT_CLKEN +CYREG_WCO_WDT_CLKEN EQU 0x40220214 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_CLK_WCO_EN_FOR_WDT__OFFSET +CYFLD_WCO_CLK_WCO_EN_FOR_WDT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_CLK_WCO_EN_FOR_WDT__SIZE +CYFLD_WCO_CLK_WCO_EN_FOR_WDT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_CLK_ILO_EN_FOR_WDT__OFFSET +CYFLD_WCO_CLK_ILO_EN_FOR_WDT__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_CLK_ILO_EN_FOR_WDT__SIZE +CYFLD_WCO_CLK_ILO_EN_FOR_WDT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_WCO_TRIM +CYREG_WCO_TRIM EQU 0x40220f00 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_XGM__OFFSET +CYFLD_WCO_XGM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_XGM__SIZE +CYFLD_WCO_XGM__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_LPM_GM__OFFSET +CYFLD_WCO_LPM_GM__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_WCO_LPM_GM__SIZE +CYFLD_WCO_LPM_GM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_SCB0_BASE +CYDEV_SCB0_BASE EQU 0x40240000 + ENDIF + IF :LNOT::DEF:CYDEV_SCB0_SIZE +CYDEV_SCB0_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_CTRL +CYREG_SCB0_CTRL EQU 0x40240000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVS__OFFSET +CYFLD_SCB_OVS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVS__SIZE +CYFLD_SCB_OVS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_AM_MODE__OFFSET +CYFLD_SCB_EC_AM_MODE__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_AM_MODE__SIZE +CYFLD_SCB_EC_AM_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_OP_MODE__OFFSET +CYFLD_SCB_EC_OP_MODE__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_OP_MODE__SIZE +CYFLD_SCB_EC_OP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_MODE__OFFSET +CYFLD_SCB_EZ_MODE__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_MODE__SIZE +CYFLD_SCB_EZ_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BYTE_MODE__OFFSET +CYFLD_SCB_BYTE_MODE__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BYTE_MODE__SIZE +CYFLD_SCB_BYTE_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR_ACCEPT__OFFSET +CYFLD_SCB_ADDR_ACCEPT__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR_ACCEPT__SIZE +CYFLD_SCB_ADDR_ACCEPT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCK__OFFSET +CYFLD_SCB_BLOCK__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCK__SIZE +CYFLD_SCB_BLOCK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MODE__OFFSET +CYFLD_SCB_MODE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MODE__SIZE +CYFLD_SCB_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SCB_MODE_I2C +CYVAL_SCB_MODE_I2C EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SCB_MODE_SPI +CYVAL_SCB_MODE_SPI EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SCB_MODE_UART +CYVAL_SCB_MODE_UART EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ENABLED__OFFSET +CYFLD_SCB_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ENABLED__SIZE +CYFLD_SCB_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_STATUS +CYREG_SCB0_STATUS EQU 0x40240004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_BUSY__OFFSET +CYFLD_SCB_EC_BUSY__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EC_BUSY__SIZE +CYFLD_SCB_EC_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_SPI_CTRL +CYREG_SCB0_SPI_CTRL EQU 0x40240020 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CONTINUOUS__OFFSET +CYFLD_SCB_CONTINUOUS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CONTINUOUS__SIZE +CYFLD_SCB_CONTINUOUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SELECT_PRECEDE__OFFSET +CYFLD_SCB_SELECT_PRECEDE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SELECT_PRECEDE__SIZE +CYFLD_SCB_SELECT_PRECEDE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPHA__OFFSET +CYFLD_SCB_CPHA__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPHA__SIZE +CYFLD_SCB_CPHA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPOL__OFFSET +CYFLD_SCB_CPOL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CPOL__SIZE +CYFLD_SCB_CPOL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET +CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LATE_MISO_SAMPLE__SIZE +CYFLD_SCB_LATE_MISO_SAMPLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCLK_CONTINUOUS__OFFSET +CYFLD_SCB_SCLK_CONTINUOUS__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCLK_CONTINUOUS__SIZE +CYFLD_SCB_SCLK_CONTINUOUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SSEL_POLARITY0__OFFSET +CYFLD_SCB_SSEL_POLARITY0__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SSEL_POLARITY0__SIZE +CYFLD_SCB_SSEL_POLARITY0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SSEL_POLARITY1__OFFSET +CYFLD_SCB_SSEL_POLARITY1__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SSEL_POLARITY1__SIZE +CYFLD_SCB_SSEL_POLARITY1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SSEL_POLARITY2__OFFSET +CYFLD_SCB_SSEL_POLARITY2__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SSEL_POLARITY2__SIZE +CYFLD_SCB_SSEL_POLARITY2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SSEL_POLARITY3__OFFSET +CYFLD_SCB_SSEL_POLARITY3__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SSEL_POLARITY3__SIZE +CYFLD_SCB_SSEL_POLARITY3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOOPBACK__OFFSET +CYFLD_SCB_LOOPBACK__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOOPBACK__SIZE +CYFLD_SCB_LOOPBACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_SELECT__OFFSET +CYFLD_SCB_SLAVE_SELECT__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_SELECT__SIZE +CYFLD_SCB_SLAVE_SELECT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASTER_MODE__OFFSET +CYFLD_SCB_MASTER_MODE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASTER_MODE__SIZE +CYFLD_SCB_MASTER_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_SPI_STATUS +CYREG_SCB0_SPI_STATUS EQU 0x40240024 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BUS_BUSY__OFFSET +CYFLD_SCB_BUS_BUSY__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BUS_BUSY__SIZE +CYFLD_SCB_BUS_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EC_BUSY__OFFSET +CYFLD_SCB_SPI_EC_BUSY__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EC_BUSY__SIZE +CYFLD_SCB_SPI_EC_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CURR_EZ_ADDR__OFFSET +CYFLD_SCB_CURR_EZ_ADDR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CURR_EZ_ADDR__SIZE +CYFLD_SCB_CURR_EZ_ADDR__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BASE_EZ_ADDR__OFFSET +CYFLD_SCB_BASE_EZ_ADDR__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BASE_EZ_ADDR__SIZE +CYFLD_SCB_BASE_EZ_ADDR__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_CTRL +CYREG_SCB0_UART_CTRL EQU 0x40240040 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_TX_CTRL +CYREG_SCB0_UART_TX_CTRL EQU 0x40240044 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_STOP_BITS__OFFSET +CYFLD_SCB_STOP_BITS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_STOP_BITS__SIZE +CYFLD_SCB_STOP_BITS__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY__OFFSET +CYFLD_SCB_PARITY__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY__SIZE +CYFLD_SCB_PARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ENABLED__OFFSET +CYFLD_SCB_PARITY_ENABLED__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ENABLED__SIZE +CYFLD_SCB_PARITY_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RETRY_ON_NACK__OFFSET +CYFLD_SCB_RETRY_ON_NACK__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RETRY_ON_NACK__SIZE +CYFLD_SCB_RETRY_ON_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_RX_CTRL +CYREG_SCB0_UART_RX_CTRL EQU 0x40240048 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_POLARITY__OFFSET +CYFLD_SCB_POLARITY__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_POLARITY__SIZE +CYFLD_SCB_POLARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET +CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE +CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET +CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE +CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MP_MODE__OFFSET +CYFLD_SCB_MP_MODE__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MP_MODE__SIZE +CYFLD_SCB_MP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LIN_MODE__OFFSET +CYFLD_SCB_LIN_MODE__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LIN_MODE__SIZE +CYFLD_SCB_LIN_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SKIP_START__OFFSET +CYFLD_SCB_SKIP_START__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SKIP_START__SIZE +CYFLD_SCB_SKIP_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_WIDTH__OFFSET +CYFLD_SCB_BREAK_WIDTH__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_WIDTH__SIZE +CYFLD_SCB_BREAK_WIDTH__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_RX_STATUS +CYREG_SCB0_UART_RX_STATUS EQU 0x4024004c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BR_COUNTER__OFFSET +CYFLD_SCB_BR_COUNTER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BR_COUNTER__SIZE +CYFLD_SCB_BR_COUNTER__SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_UART_FLOW_CTRL +CYREG_SCB0_UART_FLOW_CTRL EQU 0x40240050 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER_LEVEL__OFFSET +CYFLD_SCB_TRIGGER_LEVEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER_LEVEL__SIZE +CYFLD_SCB_TRIGGER_LEVEL__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RTS_POLARITY__OFFSET +CYFLD_SCB_RTS_POLARITY__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RTS_POLARITY__SIZE +CYFLD_SCB_RTS_POLARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CTS_POLARITY__OFFSET +CYFLD_SCB_CTS_POLARITY__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CTS_POLARITY__SIZE +CYFLD_SCB_CTS_POLARITY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CTS_ENABLED__OFFSET +CYFLD_SCB_CTS_ENABLED__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CTS_ENABLED__SIZE +CYFLD_SCB_CTS_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_CTRL +CYREG_SCB0_I2C_CTRL EQU 0x40240060 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_HIGH_PHASE_OVS__OFFSET +CYFLD_SCB_HIGH_PHASE_OVS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_HIGH_PHASE_OVS__SIZE +CYFLD_SCB_HIGH_PHASE_OVS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOW_PHASE_OVS__OFFSET +CYFLD_SCB_LOW_PHASE_OVS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_LOW_PHASE_OVS__SIZE +CYFLD_SCB_LOW_PHASE_OVS__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READY_DATA_ACK__OFFSET +CYFLD_SCB_M_READY_DATA_ACK__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READY_DATA_ACK__SIZE +CYFLD_SCB_M_READY_DATA_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET +CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE +CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_GENERAL_IGNORE__OFFSET +CYFLD_SCB_S_GENERAL_IGNORE__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_GENERAL_IGNORE__SIZE +CYFLD_SCB_S_GENERAL_IGNORE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_ADDR_ACK__OFFSET +CYFLD_SCB_S_READY_ADDR_ACK__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_ADDR_ACK__SIZE +CYFLD_SCB_S_READY_ADDR_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_DATA_ACK__OFFSET +CYFLD_SCB_S_READY_DATA_ACK__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READY_DATA_ACK__SIZE +CYFLD_SCB_S_READY_DATA_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET +CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE +CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET +CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE +CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_MODE__OFFSET +CYFLD_SCB_SLAVE_MODE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SLAVE_MODE__SIZE +CYFLD_SCB_SLAVE_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_STATUS +CYREG_SCB0_I2C_STATUS EQU 0x40240064 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_EC_BUSY__OFFSET +CYFLD_SCB_I2C_EC_BUSY__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_EC_BUSY__SIZE +CYFLD_SCB_I2C_EC_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READ__OFFSET +CYFLD_SCB_S_READ__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_READ__SIZE +CYFLD_SCB_S_READ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READ__OFFSET +CYFLD_SCB_M_READ__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_READ__SIZE +CYFLD_SCB_M_READ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_M_CMD +CYREG_SCB0_I2C_M_CMD EQU 0x40240068 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START__OFFSET +CYFLD_SCB_M_START__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START__SIZE +CYFLD_SCB_M_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START_ON_IDLE__OFFSET +CYFLD_SCB_M_START_ON_IDLE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_START_ON_IDLE__SIZE +CYFLD_SCB_M_START_ON_IDLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_ACK__OFFSET +CYFLD_SCB_M_ACK__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_ACK__SIZE +CYFLD_SCB_M_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NACK__OFFSET +CYFLD_SCB_M_NACK__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_NACK__SIZE +CYFLD_SCB_M_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_STOP__OFFSET +CYFLD_SCB_M_STOP__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M_STOP__SIZE +CYFLD_SCB_M_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_S_CMD +CYREG_SCB0_I2C_S_CMD EQU 0x4024006c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_ACK__OFFSET +CYFLD_SCB_S_ACK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_ACK__SIZE +CYFLD_SCB_S_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NACK__OFFSET +CYFLD_SCB_S_NACK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S_NACK__SIZE +CYFLD_SCB_S_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_I2C_CFG +CYREG_SCB0_I2C_CFG EQU 0x40240070 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_IN_FILT_TRIM__OFFSET +CYFLD_SCB_SDA_IN_FILT_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_IN_FILT_TRIM__SIZE +CYFLD_SCB_SDA_IN_FILT_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_IN_FILT_SEL__OFFSET +CYFLD_SCB_SDA_IN_FILT_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_IN_FILT_SEL__SIZE +CYFLD_SCB_SDA_IN_FILT_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_IN_FILT_TRIM__OFFSET +CYFLD_SCB_SCL_IN_FILT_TRIM__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_IN_FILT_TRIM__SIZE +CYFLD_SCB_SCL_IN_FILT_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_IN_FILT_SEL__OFFSET +CYFLD_SCB_SCL_IN_FILT_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SCL_IN_FILT_SEL__SIZE +CYFLD_SCB_SCL_IN_FILT_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_OUT_FILT0_TRIM__OFFSET +CYFLD_SCB_SDA_OUT_FILT0_TRIM__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_OUT_FILT0_TRIM__SIZE +CYFLD_SCB_SDA_OUT_FILT0_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_OUT_FILT1_TRIM__OFFSET +CYFLD_SCB_SDA_OUT_FILT1_TRIM__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_OUT_FILT1_TRIM__SIZE +CYFLD_SCB_SDA_OUT_FILT1_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_OUT_FILT2_TRIM__OFFSET +CYFLD_SCB_SDA_OUT_FILT2_TRIM__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_OUT_FILT2_TRIM__SIZE +CYFLD_SCB_SDA_OUT_FILT2_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_OUT_FILT_SEL__OFFSET +CYFLD_SCB_SDA_OUT_FILT_SEL__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SDA_OUT_FILT_SEL__SIZE +CYFLD_SCB_SDA_OUT_FILT_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_CTRL +CYREG_SCB0_TX_CTRL EQU 0x40240200 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA_WIDTH__OFFSET +CYFLD_SCB_DATA_WIDTH__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA_WIDTH__SIZE +CYFLD_SCB_DATA_WIDTH__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MSB_FIRST__OFFSET +CYFLD_SCB_MSB_FIRST__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MSB_FIRST__SIZE +CYFLD_SCB_MSB_FIRST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_FIFO_CTRL +CYREG_SCB0_TX_FIFO_CTRL EQU 0x40240204 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CLEAR__OFFSET +CYFLD_SCB_CLEAR__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_CLEAR__SIZE +CYFLD_SCB_CLEAR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FREEZE__OFFSET +CYFLD_SCB_FREEZE__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FREEZE__SIZE +CYFLD_SCB_FREEZE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_FIFO_STATUS +CYREG_SCB0_TX_FIFO_STATUS EQU 0x40240208 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_USED__OFFSET +CYFLD_SCB_USED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_USED__SIZE +CYFLD_SCB_USED__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SR_VALID__OFFSET +CYFLD_SCB_SR_VALID__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SR_VALID__SIZE +CYFLD_SCB_SR_VALID__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RD_PTR__OFFSET +CYFLD_SCB_RD_PTR__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RD_PTR__SIZE +CYFLD_SCB_RD_PTR__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WR_PTR__OFFSET +CYFLD_SCB_WR_PTR__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WR_PTR__SIZE +CYFLD_SCB_WR_PTR__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_TX_FIFO_WR +CYREG_SCB0_TX_FIFO_WR EQU 0x40240240 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA__OFFSET +CYFLD_SCB_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_DATA__SIZE +CYFLD_SCB_DATA__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_CTRL +CYREG_SCB0_RX_CTRL EQU 0x40240300 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MEDIAN__OFFSET +CYFLD_SCB_MEDIAN__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MEDIAN__SIZE +CYFLD_SCB_MEDIAN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_CTRL +CYREG_SCB0_RX_FIFO_CTRL EQU 0x40240304 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_STATUS +CYREG_SCB0_RX_FIFO_STATUS EQU 0x40240308 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_MATCH +CYREG_SCB0_RX_MATCH EQU 0x40240310 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR__OFFSET +CYFLD_SCB_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_ADDR__SIZE +CYFLD_SCB_ADDR__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASK__OFFSET +CYFLD_SCB_MASK__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_MASK__SIZE +CYFLD_SCB_MASK__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_RD +CYREG_SCB0_RX_FIFO_RD EQU 0x40240340 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_RX_FIFO_RD_SILENT +CYREG_SCB0_RX_FIFO_RD_SILENT EQU 0x40240344 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA0 +CYREG_SCB0_EZ_DATA0 EQU 0x40240400 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_DATA__OFFSET +CYFLD_SCB_EZ_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_DATA__SIZE +CYFLD_SCB_EZ_DATA__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA1 +CYREG_SCB0_EZ_DATA1 EQU 0x40240404 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA2 +CYREG_SCB0_EZ_DATA2 EQU 0x40240408 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA3 +CYREG_SCB0_EZ_DATA3 EQU 0x4024040c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA4 +CYREG_SCB0_EZ_DATA4 EQU 0x40240410 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA5 +CYREG_SCB0_EZ_DATA5 EQU 0x40240414 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA6 +CYREG_SCB0_EZ_DATA6 EQU 0x40240418 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA7 +CYREG_SCB0_EZ_DATA7 EQU 0x4024041c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA8 +CYREG_SCB0_EZ_DATA8 EQU 0x40240420 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA9 +CYREG_SCB0_EZ_DATA9 EQU 0x40240424 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA10 +CYREG_SCB0_EZ_DATA10 EQU 0x40240428 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA11 +CYREG_SCB0_EZ_DATA11 EQU 0x4024042c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA12 +CYREG_SCB0_EZ_DATA12 EQU 0x40240430 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA13 +CYREG_SCB0_EZ_DATA13 EQU 0x40240434 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA14 +CYREG_SCB0_EZ_DATA14 EQU 0x40240438 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA15 +CYREG_SCB0_EZ_DATA15 EQU 0x4024043c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA16 +CYREG_SCB0_EZ_DATA16 EQU 0x40240440 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA17 +CYREG_SCB0_EZ_DATA17 EQU 0x40240444 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA18 +CYREG_SCB0_EZ_DATA18 EQU 0x40240448 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA19 +CYREG_SCB0_EZ_DATA19 EQU 0x4024044c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA20 +CYREG_SCB0_EZ_DATA20 EQU 0x40240450 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA21 +CYREG_SCB0_EZ_DATA21 EQU 0x40240454 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA22 +CYREG_SCB0_EZ_DATA22 EQU 0x40240458 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA23 +CYREG_SCB0_EZ_DATA23 EQU 0x4024045c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA24 +CYREG_SCB0_EZ_DATA24 EQU 0x40240460 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA25 +CYREG_SCB0_EZ_DATA25 EQU 0x40240464 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA26 +CYREG_SCB0_EZ_DATA26 EQU 0x40240468 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA27 +CYREG_SCB0_EZ_DATA27 EQU 0x4024046c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA28 +CYREG_SCB0_EZ_DATA28 EQU 0x40240470 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA29 +CYREG_SCB0_EZ_DATA29 EQU 0x40240474 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA30 +CYREG_SCB0_EZ_DATA30 EQU 0x40240478 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_EZ_DATA31 +CYREG_SCB0_EZ_DATA31 EQU 0x4024047c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_CAUSE +CYREG_SCB0_INTR_CAUSE EQU 0x40240e00 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M__OFFSET +CYFLD_SCB_M__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_M__SIZE +CYFLD_SCB_M__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S__OFFSET +CYFLD_SCB_S__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_S__SIZE +CYFLD_SCB_S__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TX__OFFSET +CYFLD_SCB_TX__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TX__SIZE +CYFLD_SCB_TX__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RX__OFFSET +CYFLD_SCB_RX__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_RX__SIZE +CYFLD_SCB_RX__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_EC__OFFSET +CYFLD_SCB_I2C_EC__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_EC__SIZE +CYFLD_SCB_I2C_EC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EC__OFFSET +CYFLD_SCB_SPI_EC__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EC__SIZE +CYFLD_SCB_SPI_EC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_I2C_EC +CYREG_SCB0_INTR_I2C_EC EQU 0x40240e80 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WAKE_UP__OFFSET +CYFLD_SCB_WAKE_UP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_WAKE_UP__SIZE +CYFLD_SCB_WAKE_UP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_STOP__OFFSET +CYFLD_SCB_EZ_STOP__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_STOP__SIZE +CYFLD_SCB_EZ_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_WRITE_STOP__OFFSET +CYFLD_SCB_EZ_WRITE_STOP__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_WRITE_STOP__SIZE +CYFLD_SCB_EZ_WRITE_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_READ_STOP__OFFSET +CYFLD_SCB_EZ_READ_STOP__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EZ_READ_STOP__SIZE +CYFLD_SCB_EZ_READ_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_I2C_EC_MASK +CYREG_SCB0_INTR_I2C_EC_MASK EQU 0x40240e88 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_I2C_EC_MASKED +CYREG_SCB0_INTR_I2C_EC_MASKED EQU 0x40240e8c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_SPI_EC +CYREG_SCB0_INTR_SPI_EC EQU 0x40240ec0 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_SPI_EC_MASK +CYREG_SCB0_INTR_SPI_EC_MASK EQU 0x40240ec8 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_SPI_EC_MASKED +CYREG_SCB0_INTR_SPI_EC_MASKED EQU 0x40240ecc + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M +CYREG_SCB0_INTR_M EQU 0x40240f00 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ARB_LOST__OFFSET +CYFLD_SCB_I2C_ARB_LOST__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ARB_LOST__SIZE +CYFLD_SCB_I2C_ARB_LOST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_NACK__OFFSET +CYFLD_SCB_I2C_NACK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_NACK__SIZE +CYFLD_SCB_I2C_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ACK__OFFSET +CYFLD_SCB_I2C_ACK__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ACK__SIZE +CYFLD_SCB_I2C_ACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_STOP__OFFSET +CYFLD_SCB_I2C_STOP__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_STOP__SIZE +CYFLD_SCB_I2C_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_BUS_ERROR__OFFSET +CYFLD_SCB_I2C_BUS_ERROR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_BUS_ERROR__SIZE +CYFLD_SCB_I2C_BUS_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_DONE__OFFSET +CYFLD_SCB_SPI_DONE__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_DONE__SIZE +CYFLD_SCB_SPI_DONE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M_SET +CYREG_SCB0_INTR_M_SET EQU 0x40240f04 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M_MASK +CYREG_SCB0_INTR_M_MASK EQU 0x40240f08 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_M_MASKED +CYREG_SCB0_INTR_M_MASKED EQU 0x40240f0c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S +CYREG_SCB0_INTR_S EQU 0x40240f40 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_WRITE_STOP__OFFSET +CYFLD_SCB_I2C_WRITE_STOP__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_WRITE_STOP__SIZE +CYFLD_SCB_I2C_WRITE_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_START__OFFSET +CYFLD_SCB_I2C_START__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_START__SIZE +CYFLD_SCB_I2C_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ADDR_MATCH__OFFSET +CYFLD_SCB_I2C_ADDR_MATCH__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_ADDR_MATCH__SIZE +CYFLD_SCB_I2C_ADDR_MATCH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_GENERAL__OFFSET +CYFLD_SCB_I2C_GENERAL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_I2C_GENERAL__SIZE +CYFLD_SCB_I2C_GENERAL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET +CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE +CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_STOP__OFFSET +CYFLD_SCB_SPI_EZ_STOP__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_EZ_STOP__SIZE +CYFLD_SCB_SPI_EZ_STOP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_BUS_ERROR__OFFSET +CYFLD_SCB_SPI_BUS_ERROR__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_SPI_BUS_ERROR__SIZE +CYFLD_SCB_SPI_BUS_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S_SET +CYREG_SCB0_INTR_S_SET EQU 0x40240f44 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S_MASK +CYREG_SCB0_INTR_S_MASK EQU 0x40240f48 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_S_MASKED +CYREG_SCB0_INTR_S_MASKED EQU 0x40240f4c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX +CYREG_SCB0_INTR_TX EQU 0x40240f80 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER__OFFSET +CYFLD_SCB_TRIGGER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_TRIGGER__SIZE +CYFLD_SCB_TRIGGER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_FULL__OFFSET +CYFLD_SCB_NOT_FULL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_FULL__SIZE +CYFLD_SCB_NOT_FULL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EMPTY__OFFSET +CYFLD_SCB_EMPTY__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_EMPTY__SIZE +CYFLD_SCB_EMPTY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVERFLOW__OFFSET +CYFLD_SCB_OVERFLOW__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_OVERFLOW__SIZE +CYFLD_SCB_OVERFLOW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UNDERFLOW__OFFSET +CYFLD_SCB_UNDERFLOW__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UNDERFLOW__SIZE +CYFLD_SCB_UNDERFLOW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCKED__OFFSET +CYFLD_SCB_BLOCKED__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BLOCKED__SIZE +CYFLD_SCB_BLOCKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_NACK__OFFSET +CYFLD_SCB_UART_NACK__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_NACK__SIZE +CYFLD_SCB_UART_NACK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_DONE__OFFSET +CYFLD_SCB_UART_DONE__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_DONE__SIZE +CYFLD_SCB_UART_DONE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_ARB_LOST__OFFSET +CYFLD_SCB_UART_ARB_LOST__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_UART_ARB_LOST__SIZE +CYFLD_SCB_UART_ARB_LOST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX_SET +CYREG_SCB0_INTR_TX_SET EQU 0x40240f84 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX_MASK +CYREG_SCB0_INTR_TX_MASK EQU 0x40240f88 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_TX_MASKED +CYREG_SCB0_INTR_TX_MASKED EQU 0x40240f8c + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX +CYREG_SCB0_INTR_RX EQU 0x40240fc0 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_EMPTY__OFFSET +CYFLD_SCB_NOT_EMPTY__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_NOT_EMPTY__SIZE +CYFLD_SCB_NOT_EMPTY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FULL__OFFSET +CYFLD_SCB_FULL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FULL__SIZE +CYFLD_SCB_FULL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FRAME_ERROR__OFFSET +CYFLD_SCB_FRAME_ERROR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_FRAME_ERROR__SIZE +CYFLD_SCB_FRAME_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ERROR__OFFSET +CYFLD_SCB_PARITY_ERROR__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_PARITY_ERROR__SIZE +CYFLD_SCB_PARITY_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BAUD_DETECT__OFFSET +CYFLD_SCB_BAUD_DETECT__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BAUD_DETECT__SIZE +CYFLD_SCB_BAUD_DETECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_DETECT__OFFSET +CYFLD_SCB_BREAK_DETECT__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SCB_BREAK_DETECT__SIZE +CYFLD_SCB_BREAK_DETECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX_SET +CYREG_SCB0_INTR_RX_SET EQU 0x40240fc4 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX_MASK +CYREG_SCB0_INTR_RX_MASK EQU 0x40240fc8 + ENDIF + IF :LNOT::DEF:CYREG_SCB0_INTR_RX_MASKED +CYREG_SCB0_INTR_RX_MASKED EQU 0x40240fcc + ENDIF + IF :LNOT::DEF:CYDEV_SCB1_BASE +CYDEV_SCB1_BASE EQU 0x40250000 + ENDIF + IF :LNOT::DEF:CYDEV_SCB1_SIZE +CYDEV_SCB1_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_CTRL +CYREG_SCB1_CTRL EQU 0x40250000 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_STATUS +CYREG_SCB1_STATUS EQU 0x40250004 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_SPI_CTRL +CYREG_SCB1_SPI_CTRL EQU 0x40250020 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_SPI_STATUS +CYREG_SCB1_SPI_STATUS EQU 0x40250024 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_CTRL +CYREG_SCB1_UART_CTRL EQU 0x40250040 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_TX_CTRL +CYREG_SCB1_UART_TX_CTRL EQU 0x40250044 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_RX_CTRL +CYREG_SCB1_UART_RX_CTRL EQU 0x40250048 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_RX_STATUS +CYREG_SCB1_UART_RX_STATUS EQU 0x4025004c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_UART_FLOW_CTRL +CYREG_SCB1_UART_FLOW_CTRL EQU 0x40250050 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_CTRL +CYREG_SCB1_I2C_CTRL EQU 0x40250060 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_STATUS +CYREG_SCB1_I2C_STATUS EQU 0x40250064 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_M_CMD +CYREG_SCB1_I2C_M_CMD EQU 0x40250068 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_S_CMD +CYREG_SCB1_I2C_S_CMD EQU 0x4025006c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_I2C_CFG +CYREG_SCB1_I2C_CFG EQU 0x40250070 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_CTRL +CYREG_SCB1_TX_CTRL EQU 0x40250200 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_FIFO_CTRL +CYREG_SCB1_TX_FIFO_CTRL EQU 0x40250204 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_FIFO_STATUS +CYREG_SCB1_TX_FIFO_STATUS EQU 0x40250208 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_TX_FIFO_WR +CYREG_SCB1_TX_FIFO_WR EQU 0x40250240 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_CTRL +CYREG_SCB1_RX_CTRL EQU 0x40250300 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_CTRL +CYREG_SCB1_RX_FIFO_CTRL EQU 0x40250304 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_STATUS +CYREG_SCB1_RX_FIFO_STATUS EQU 0x40250308 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_MATCH +CYREG_SCB1_RX_MATCH EQU 0x40250310 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_RD +CYREG_SCB1_RX_FIFO_RD EQU 0x40250340 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_RX_FIFO_RD_SILENT +CYREG_SCB1_RX_FIFO_RD_SILENT EQU 0x40250344 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA0 +CYREG_SCB1_EZ_DATA0 EQU 0x40250400 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA1 +CYREG_SCB1_EZ_DATA1 EQU 0x40250404 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA2 +CYREG_SCB1_EZ_DATA2 EQU 0x40250408 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA3 +CYREG_SCB1_EZ_DATA3 EQU 0x4025040c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA4 +CYREG_SCB1_EZ_DATA4 EQU 0x40250410 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA5 +CYREG_SCB1_EZ_DATA5 EQU 0x40250414 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA6 +CYREG_SCB1_EZ_DATA6 EQU 0x40250418 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA7 +CYREG_SCB1_EZ_DATA7 EQU 0x4025041c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA8 +CYREG_SCB1_EZ_DATA8 EQU 0x40250420 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA9 +CYREG_SCB1_EZ_DATA9 EQU 0x40250424 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA10 +CYREG_SCB1_EZ_DATA10 EQU 0x40250428 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA11 +CYREG_SCB1_EZ_DATA11 EQU 0x4025042c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA12 +CYREG_SCB1_EZ_DATA12 EQU 0x40250430 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA13 +CYREG_SCB1_EZ_DATA13 EQU 0x40250434 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA14 +CYREG_SCB1_EZ_DATA14 EQU 0x40250438 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA15 +CYREG_SCB1_EZ_DATA15 EQU 0x4025043c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA16 +CYREG_SCB1_EZ_DATA16 EQU 0x40250440 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA17 +CYREG_SCB1_EZ_DATA17 EQU 0x40250444 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA18 +CYREG_SCB1_EZ_DATA18 EQU 0x40250448 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA19 +CYREG_SCB1_EZ_DATA19 EQU 0x4025044c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA20 +CYREG_SCB1_EZ_DATA20 EQU 0x40250450 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA21 +CYREG_SCB1_EZ_DATA21 EQU 0x40250454 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA22 +CYREG_SCB1_EZ_DATA22 EQU 0x40250458 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA23 +CYREG_SCB1_EZ_DATA23 EQU 0x4025045c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA24 +CYREG_SCB1_EZ_DATA24 EQU 0x40250460 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA25 +CYREG_SCB1_EZ_DATA25 EQU 0x40250464 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA26 +CYREG_SCB1_EZ_DATA26 EQU 0x40250468 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA27 +CYREG_SCB1_EZ_DATA27 EQU 0x4025046c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA28 +CYREG_SCB1_EZ_DATA28 EQU 0x40250470 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA29 +CYREG_SCB1_EZ_DATA29 EQU 0x40250474 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA30 +CYREG_SCB1_EZ_DATA30 EQU 0x40250478 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_EZ_DATA31 +CYREG_SCB1_EZ_DATA31 EQU 0x4025047c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_CAUSE +CYREG_SCB1_INTR_CAUSE EQU 0x40250e00 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_I2C_EC +CYREG_SCB1_INTR_I2C_EC EQU 0x40250e80 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_I2C_EC_MASK +CYREG_SCB1_INTR_I2C_EC_MASK EQU 0x40250e88 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_I2C_EC_MASKED +CYREG_SCB1_INTR_I2C_EC_MASKED EQU 0x40250e8c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_SPI_EC +CYREG_SCB1_INTR_SPI_EC EQU 0x40250ec0 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_SPI_EC_MASK +CYREG_SCB1_INTR_SPI_EC_MASK EQU 0x40250ec8 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_SPI_EC_MASKED +CYREG_SCB1_INTR_SPI_EC_MASKED EQU 0x40250ecc + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M +CYREG_SCB1_INTR_M EQU 0x40250f00 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M_SET +CYREG_SCB1_INTR_M_SET EQU 0x40250f04 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M_MASK +CYREG_SCB1_INTR_M_MASK EQU 0x40250f08 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_M_MASKED +CYREG_SCB1_INTR_M_MASKED EQU 0x40250f0c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S +CYREG_SCB1_INTR_S EQU 0x40250f40 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S_SET +CYREG_SCB1_INTR_S_SET EQU 0x40250f44 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S_MASK +CYREG_SCB1_INTR_S_MASK EQU 0x40250f48 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_S_MASKED +CYREG_SCB1_INTR_S_MASKED EQU 0x40250f4c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX +CYREG_SCB1_INTR_TX EQU 0x40250f80 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX_SET +CYREG_SCB1_INTR_TX_SET EQU 0x40250f84 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX_MASK +CYREG_SCB1_INTR_TX_MASK EQU 0x40250f88 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_TX_MASKED +CYREG_SCB1_INTR_TX_MASKED EQU 0x40250f8c + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX +CYREG_SCB1_INTR_RX EQU 0x40250fc0 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX_SET +CYREG_SCB1_INTR_RX_SET EQU 0x40250fc4 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX_MASK +CYREG_SCB1_INTR_RX_MASK EQU 0x40250fc8 + ENDIF + IF :LNOT::DEF:CYREG_SCB1_INTR_RX_MASKED +CYREG_SCB1_INTR_RX_MASKED EQU 0x40250fcc + ENDIF + IF :LNOT::DEF:CYDEV_SCB2_BASE +CYDEV_SCB2_BASE EQU 0x40260000 + ENDIF + IF :LNOT::DEF:CYDEV_SCB2_SIZE +CYDEV_SCB2_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_CTRL +CYREG_SCB2_CTRL EQU 0x40260000 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_STATUS +CYREG_SCB2_STATUS EQU 0x40260004 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_SPI_CTRL +CYREG_SCB2_SPI_CTRL EQU 0x40260020 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_SPI_STATUS +CYREG_SCB2_SPI_STATUS EQU 0x40260024 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_UART_CTRL +CYREG_SCB2_UART_CTRL EQU 0x40260040 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_UART_TX_CTRL +CYREG_SCB2_UART_TX_CTRL EQU 0x40260044 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_UART_RX_CTRL +CYREG_SCB2_UART_RX_CTRL EQU 0x40260048 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_UART_RX_STATUS +CYREG_SCB2_UART_RX_STATUS EQU 0x4026004c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_UART_FLOW_CTRL +CYREG_SCB2_UART_FLOW_CTRL EQU 0x40260050 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_I2C_CTRL +CYREG_SCB2_I2C_CTRL EQU 0x40260060 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_I2C_STATUS +CYREG_SCB2_I2C_STATUS EQU 0x40260064 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_I2C_M_CMD +CYREG_SCB2_I2C_M_CMD EQU 0x40260068 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_I2C_S_CMD +CYREG_SCB2_I2C_S_CMD EQU 0x4026006c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_I2C_CFG +CYREG_SCB2_I2C_CFG EQU 0x40260070 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_TX_CTRL +CYREG_SCB2_TX_CTRL EQU 0x40260200 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_TX_FIFO_CTRL +CYREG_SCB2_TX_FIFO_CTRL EQU 0x40260204 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_TX_FIFO_STATUS +CYREG_SCB2_TX_FIFO_STATUS EQU 0x40260208 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_TX_FIFO_WR +CYREG_SCB2_TX_FIFO_WR EQU 0x40260240 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_RX_CTRL +CYREG_SCB2_RX_CTRL EQU 0x40260300 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_RX_FIFO_CTRL +CYREG_SCB2_RX_FIFO_CTRL EQU 0x40260304 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_RX_FIFO_STATUS +CYREG_SCB2_RX_FIFO_STATUS EQU 0x40260308 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_RX_MATCH +CYREG_SCB2_RX_MATCH EQU 0x40260310 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_RX_FIFO_RD +CYREG_SCB2_RX_FIFO_RD EQU 0x40260340 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_RX_FIFO_RD_SILENT +CYREG_SCB2_RX_FIFO_RD_SILENT EQU 0x40260344 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA0 +CYREG_SCB2_EZ_DATA0 EQU 0x40260400 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA1 +CYREG_SCB2_EZ_DATA1 EQU 0x40260404 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA2 +CYREG_SCB2_EZ_DATA2 EQU 0x40260408 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA3 +CYREG_SCB2_EZ_DATA3 EQU 0x4026040c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA4 +CYREG_SCB2_EZ_DATA4 EQU 0x40260410 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA5 +CYREG_SCB2_EZ_DATA5 EQU 0x40260414 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA6 +CYREG_SCB2_EZ_DATA6 EQU 0x40260418 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA7 +CYREG_SCB2_EZ_DATA7 EQU 0x4026041c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA8 +CYREG_SCB2_EZ_DATA8 EQU 0x40260420 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA9 +CYREG_SCB2_EZ_DATA9 EQU 0x40260424 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA10 +CYREG_SCB2_EZ_DATA10 EQU 0x40260428 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA11 +CYREG_SCB2_EZ_DATA11 EQU 0x4026042c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA12 +CYREG_SCB2_EZ_DATA12 EQU 0x40260430 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA13 +CYREG_SCB2_EZ_DATA13 EQU 0x40260434 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA14 +CYREG_SCB2_EZ_DATA14 EQU 0x40260438 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA15 +CYREG_SCB2_EZ_DATA15 EQU 0x4026043c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA16 +CYREG_SCB2_EZ_DATA16 EQU 0x40260440 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA17 +CYREG_SCB2_EZ_DATA17 EQU 0x40260444 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA18 +CYREG_SCB2_EZ_DATA18 EQU 0x40260448 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA19 +CYREG_SCB2_EZ_DATA19 EQU 0x4026044c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA20 +CYREG_SCB2_EZ_DATA20 EQU 0x40260450 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA21 +CYREG_SCB2_EZ_DATA21 EQU 0x40260454 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA22 +CYREG_SCB2_EZ_DATA22 EQU 0x40260458 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA23 +CYREG_SCB2_EZ_DATA23 EQU 0x4026045c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA24 +CYREG_SCB2_EZ_DATA24 EQU 0x40260460 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA25 +CYREG_SCB2_EZ_DATA25 EQU 0x40260464 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA26 +CYREG_SCB2_EZ_DATA26 EQU 0x40260468 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA27 +CYREG_SCB2_EZ_DATA27 EQU 0x4026046c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA28 +CYREG_SCB2_EZ_DATA28 EQU 0x40260470 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA29 +CYREG_SCB2_EZ_DATA29 EQU 0x40260474 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA30 +CYREG_SCB2_EZ_DATA30 EQU 0x40260478 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_EZ_DATA31 +CYREG_SCB2_EZ_DATA31 EQU 0x4026047c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_CAUSE +CYREG_SCB2_INTR_CAUSE EQU 0x40260e00 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_I2C_EC +CYREG_SCB2_INTR_I2C_EC EQU 0x40260e80 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_I2C_EC_MASK +CYREG_SCB2_INTR_I2C_EC_MASK EQU 0x40260e88 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_I2C_EC_MASKED +CYREG_SCB2_INTR_I2C_EC_MASKED EQU 0x40260e8c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_SPI_EC +CYREG_SCB2_INTR_SPI_EC EQU 0x40260ec0 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_SPI_EC_MASK +CYREG_SCB2_INTR_SPI_EC_MASK EQU 0x40260ec8 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_SPI_EC_MASKED +CYREG_SCB2_INTR_SPI_EC_MASKED EQU 0x40260ecc + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_M +CYREG_SCB2_INTR_M EQU 0x40260f00 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_M_SET +CYREG_SCB2_INTR_M_SET EQU 0x40260f04 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_M_MASK +CYREG_SCB2_INTR_M_MASK EQU 0x40260f08 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_M_MASKED +CYREG_SCB2_INTR_M_MASKED EQU 0x40260f0c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_S +CYREG_SCB2_INTR_S EQU 0x40260f40 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_S_SET +CYREG_SCB2_INTR_S_SET EQU 0x40260f44 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_S_MASK +CYREG_SCB2_INTR_S_MASK EQU 0x40260f48 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_S_MASKED +CYREG_SCB2_INTR_S_MASKED EQU 0x40260f4c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_TX +CYREG_SCB2_INTR_TX EQU 0x40260f80 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_TX_SET +CYREG_SCB2_INTR_TX_SET EQU 0x40260f84 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_TX_MASK +CYREG_SCB2_INTR_TX_MASK EQU 0x40260f88 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_TX_MASKED +CYREG_SCB2_INTR_TX_MASKED EQU 0x40260f8c + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_RX +CYREG_SCB2_INTR_RX EQU 0x40260fc0 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_RX_SET +CYREG_SCB2_INTR_RX_SET EQU 0x40260fc4 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_RX_MASK +CYREG_SCB2_INTR_RX_MASK EQU 0x40260fc8 + ENDIF + IF :LNOT::DEF:CYREG_SCB2_INTR_RX_MASKED +CYREG_SCB2_INTR_RX_MASKED EQU 0x40260fcc + ENDIF + IF :LNOT::DEF:CYDEV_SCB3_BASE +CYDEV_SCB3_BASE EQU 0x40270000 + ENDIF + IF :LNOT::DEF:CYDEV_SCB3_SIZE +CYDEV_SCB3_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_CTRL +CYREG_SCB3_CTRL EQU 0x40270000 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_STATUS +CYREG_SCB3_STATUS EQU 0x40270004 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_SPI_CTRL +CYREG_SCB3_SPI_CTRL EQU 0x40270020 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_SPI_STATUS +CYREG_SCB3_SPI_STATUS EQU 0x40270024 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_UART_CTRL +CYREG_SCB3_UART_CTRL EQU 0x40270040 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_UART_TX_CTRL +CYREG_SCB3_UART_TX_CTRL EQU 0x40270044 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_UART_RX_CTRL +CYREG_SCB3_UART_RX_CTRL EQU 0x40270048 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_UART_RX_STATUS +CYREG_SCB3_UART_RX_STATUS EQU 0x4027004c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_UART_FLOW_CTRL +CYREG_SCB3_UART_FLOW_CTRL EQU 0x40270050 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_I2C_CTRL +CYREG_SCB3_I2C_CTRL EQU 0x40270060 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_I2C_STATUS +CYREG_SCB3_I2C_STATUS EQU 0x40270064 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_I2C_M_CMD +CYREG_SCB3_I2C_M_CMD EQU 0x40270068 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_I2C_S_CMD +CYREG_SCB3_I2C_S_CMD EQU 0x4027006c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_I2C_CFG +CYREG_SCB3_I2C_CFG EQU 0x40270070 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_TX_CTRL +CYREG_SCB3_TX_CTRL EQU 0x40270200 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_TX_FIFO_CTRL +CYREG_SCB3_TX_FIFO_CTRL EQU 0x40270204 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_TX_FIFO_STATUS +CYREG_SCB3_TX_FIFO_STATUS EQU 0x40270208 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_TX_FIFO_WR +CYREG_SCB3_TX_FIFO_WR EQU 0x40270240 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_RX_CTRL +CYREG_SCB3_RX_CTRL EQU 0x40270300 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_RX_FIFO_CTRL +CYREG_SCB3_RX_FIFO_CTRL EQU 0x40270304 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_RX_FIFO_STATUS +CYREG_SCB3_RX_FIFO_STATUS EQU 0x40270308 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_RX_MATCH +CYREG_SCB3_RX_MATCH EQU 0x40270310 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_RX_FIFO_RD +CYREG_SCB3_RX_FIFO_RD EQU 0x40270340 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_RX_FIFO_RD_SILENT +CYREG_SCB3_RX_FIFO_RD_SILENT EQU 0x40270344 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA0 +CYREG_SCB3_EZ_DATA0 EQU 0x40270400 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA1 +CYREG_SCB3_EZ_DATA1 EQU 0x40270404 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA2 +CYREG_SCB3_EZ_DATA2 EQU 0x40270408 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA3 +CYREG_SCB3_EZ_DATA3 EQU 0x4027040c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA4 +CYREG_SCB3_EZ_DATA4 EQU 0x40270410 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA5 +CYREG_SCB3_EZ_DATA5 EQU 0x40270414 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA6 +CYREG_SCB3_EZ_DATA6 EQU 0x40270418 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA7 +CYREG_SCB3_EZ_DATA7 EQU 0x4027041c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA8 +CYREG_SCB3_EZ_DATA8 EQU 0x40270420 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA9 +CYREG_SCB3_EZ_DATA9 EQU 0x40270424 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA10 +CYREG_SCB3_EZ_DATA10 EQU 0x40270428 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA11 +CYREG_SCB3_EZ_DATA11 EQU 0x4027042c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA12 +CYREG_SCB3_EZ_DATA12 EQU 0x40270430 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA13 +CYREG_SCB3_EZ_DATA13 EQU 0x40270434 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA14 +CYREG_SCB3_EZ_DATA14 EQU 0x40270438 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA15 +CYREG_SCB3_EZ_DATA15 EQU 0x4027043c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA16 +CYREG_SCB3_EZ_DATA16 EQU 0x40270440 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA17 +CYREG_SCB3_EZ_DATA17 EQU 0x40270444 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA18 +CYREG_SCB3_EZ_DATA18 EQU 0x40270448 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA19 +CYREG_SCB3_EZ_DATA19 EQU 0x4027044c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA20 +CYREG_SCB3_EZ_DATA20 EQU 0x40270450 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA21 +CYREG_SCB3_EZ_DATA21 EQU 0x40270454 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA22 +CYREG_SCB3_EZ_DATA22 EQU 0x40270458 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA23 +CYREG_SCB3_EZ_DATA23 EQU 0x4027045c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA24 +CYREG_SCB3_EZ_DATA24 EQU 0x40270460 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA25 +CYREG_SCB3_EZ_DATA25 EQU 0x40270464 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA26 +CYREG_SCB3_EZ_DATA26 EQU 0x40270468 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA27 +CYREG_SCB3_EZ_DATA27 EQU 0x4027046c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA28 +CYREG_SCB3_EZ_DATA28 EQU 0x40270470 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA29 +CYREG_SCB3_EZ_DATA29 EQU 0x40270474 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA30 +CYREG_SCB3_EZ_DATA30 EQU 0x40270478 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_EZ_DATA31 +CYREG_SCB3_EZ_DATA31 EQU 0x4027047c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_CAUSE +CYREG_SCB3_INTR_CAUSE EQU 0x40270e00 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_I2C_EC +CYREG_SCB3_INTR_I2C_EC EQU 0x40270e80 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_I2C_EC_MASK +CYREG_SCB3_INTR_I2C_EC_MASK EQU 0x40270e88 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_I2C_EC_MASKED +CYREG_SCB3_INTR_I2C_EC_MASKED EQU 0x40270e8c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_SPI_EC +CYREG_SCB3_INTR_SPI_EC EQU 0x40270ec0 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_SPI_EC_MASK +CYREG_SCB3_INTR_SPI_EC_MASK EQU 0x40270ec8 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_SPI_EC_MASKED +CYREG_SCB3_INTR_SPI_EC_MASKED EQU 0x40270ecc + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_M +CYREG_SCB3_INTR_M EQU 0x40270f00 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_M_SET +CYREG_SCB3_INTR_M_SET EQU 0x40270f04 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_M_MASK +CYREG_SCB3_INTR_M_MASK EQU 0x40270f08 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_M_MASKED +CYREG_SCB3_INTR_M_MASKED EQU 0x40270f0c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_S +CYREG_SCB3_INTR_S EQU 0x40270f40 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_S_SET +CYREG_SCB3_INTR_S_SET EQU 0x40270f44 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_S_MASK +CYREG_SCB3_INTR_S_MASK EQU 0x40270f48 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_S_MASKED +CYREG_SCB3_INTR_S_MASKED EQU 0x40270f4c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_TX +CYREG_SCB3_INTR_TX EQU 0x40270f80 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_TX_SET +CYREG_SCB3_INTR_TX_SET EQU 0x40270f84 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_TX_MASK +CYREG_SCB3_INTR_TX_MASK EQU 0x40270f88 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_TX_MASKED +CYREG_SCB3_INTR_TX_MASKED EQU 0x40270f8c + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_RX +CYREG_SCB3_INTR_RX EQU 0x40270fc0 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_RX_SET +CYREG_SCB3_INTR_RX_SET EQU 0x40270fc4 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_RX_MASK +CYREG_SCB3_INTR_RX_MASK EQU 0x40270fc8 + ENDIF + IF :LNOT::DEF:CYREG_SCB3_INTR_RX_MASKED +CYREG_SCB3_INTR_RX_MASKED EQU 0x40270fcc + ENDIF + IF :LNOT::DEF:CYDEV_SCB4_BASE +CYDEV_SCB4_BASE EQU 0x40280000 + ENDIF + IF :LNOT::DEF:CYDEV_SCB4_SIZE +CYDEV_SCB4_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_CTRL +CYREG_SCB4_CTRL EQU 0x40280000 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_STATUS +CYREG_SCB4_STATUS EQU 0x40280004 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_SPI_CTRL +CYREG_SCB4_SPI_CTRL EQU 0x40280020 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_SPI_STATUS +CYREG_SCB4_SPI_STATUS EQU 0x40280024 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_UART_CTRL +CYREG_SCB4_UART_CTRL EQU 0x40280040 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_UART_TX_CTRL +CYREG_SCB4_UART_TX_CTRL EQU 0x40280044 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_UART_RX_CTRL +CYREG_SCB4_UART_RX_CTRL EQU 0x40280048 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_UART_RX_STATUS +CYREG_SCB4_UART_RX_STATUS EQU 0x4028004c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_UART_FLOW_CTRL +CYREG_SCB4_UART_FLOW_CTRL EQU 0x40280050 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_I2C_CTRL +CYREG_SCB4_I2C_CTRL EQU 0x40280060 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_I2C_STATUS +CYREG_SCB4_I2C_STATUS EQU 0x40280064 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_I2C_M_CMD +CYREG_SCB4_I2C_M_CMD EQU 0x40280068 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_I2C_S_CMD +CYREG_SCB4_I2C_S_CMD EQU 0x4028006c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_I2C_CFG +CYREG_SCB4_I2C_CFG EQU 0x40280070 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_TX_CTRL +CYREG_SCB4_TX_CTRL EQU 0x40280200 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_TX_FIFO_CTRL +CYREG_SCB4_TX_FIFO_CTRL EQU 0x40280204 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_TX_FIFO_STATUS +CYREG_SCB4_TX_FIFO_STATUS EQU 0x40280208 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_TX_FIFO_WR +CYREG_SCB4_TX_FIFO_WR EQU 0x40280240 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_RX_CTRL +CYREG_SCB4_RX_CTRL EQU 0x40280300 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_RX_FIFO_CTRL +CYREG_SCB4_RX_FIFO_CTRL EQU 0x40280304 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_RX_FIFO_STATUS +CYREG_SCB4_RX_FIFO_STATUS EQU 0x40280308 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_RX_MATCH +CYREG_SCB4_RX_MATCH EQU 0x40280310 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_RX_FIFO_RD +CYREG_SCB4_RX_FIFO_RD EQU 0x40280340 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_RX_FIFO_RD_SILENT +CYREG_SCB4_RX_FIFO_RD_SILENT EQU 0x40280344 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA0 +CYREG_SCB4_EZ_DATA0 EQU 0x40280400 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA1 +CYREG_SCB4_EZ_DATA1 EQU 0x40280404 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA2 +CYREG_SCB4_EZ_DATA2 EQU 0x40280408 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA3 +CYREG_SCB4_EZ_DATA3 EQU 0x4028040c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA4 +CYREG_SCB4_EZ_DATA4 EQU 0x40280410 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA5 +CYREG_SCB4_EZ_DATA5 EQU 0x40280414 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA6 +CYREG_SCB4_EZ_DATA6 EQU 0x40280418 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA7 +CYREG_SCB4_EZ_DATA7 EQU 0x4028041c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA8 +CYREG_SCB4_EZ_DATA8 EQU 0x40280420 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA9 +CYREG_SCB4_EZ_DATA9 EQU 0x40280424 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA10 +CYREG_SCB4_EZ_DATA10 EQU 0x40280428 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA11 +CYREG_SCB4_EZ_DATA11 EQU 0x4028042c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA12 +CYREG_SCB4_EZ_DATA12 EQU 0x40280430 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA13 +CYREG_SCB4_EZ_DATA13 EQU 0x40280434 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA14 +CYREG_SCB4_EZ_DATA14 EQU 0x40280438 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA15 +CYREG_SCB4_EZ_DATA15 EQU 0x4028043c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA16 +CYREG_SCB4_EZ_DATA16 EQU 0x40280440 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA17 +CYREG_SCB4_EZ_DATA17 EQU 0x40280444 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA18 +CYREG_SCB4_EZ_DATA18 EQU 0x40280448 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA19 +CYREG_SCB4_EZ_DATA19 EQU 0x4028044c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA20 +CYREG_SCB4_EZ_DATA20 EQU 0x40280450 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA21 +CYREG_SCB4_EZ_DATA21 EQU 0x40280454 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA22 +CYREG_SCB4_EZ_DATA22 EQU 0x40280458 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA23 +CYREG_SCB4_EZ_DATA23 EQU 0x4028045c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA24 +CYREG_SCB4_EZ_DATA24 EQU 0x40280460 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA25 +CYREG_SCB4_EZ_DATA25 EQU 0x40280464 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA26 +CYREG_SCB4_EZ_DATA26 EQU 0x40280468 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA27 +CYREG_SCB4_EZ_DATA27 EQU 0x4028046c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA28 +CYREG_SCB4_EZ_DATA28 EQU 0x40280470 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA29 +CYREG_SCB4_EZ_DATA29 EQU 0x40280474 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA30 +CYREG_SCB4_EZ_DATA30 EQU 0x40280478 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_EZ_DATA31 +CYREG_SCB4_EZ_DATA31 EQU 0x4028047c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_CAUSE +CYREG_SCB4_INTR_CAUSE EQU 0x40280e00 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_I2C_EC +CYREG_SCB4_INTR_I2C_EC EQU 0x40280e80 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_I2C_EC_MASK +CYREG_SCB4_INTR_I2C_EC_MASK EQU 0x40280e88 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_I2C_EC_MASKED +CYREG_SCB4_INTR_I2C_EC_MASKED EQU 0x40280e8c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_SPI_EC +CYREG_SCB4_INTR_SPI_EC EQU 0x40280ec0 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_SPI_EC_MASK +CYREG_SCB4_INTR_SPI_EC_MASK EQU 0x40280ec8 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_SPI_EC_MASKED +CYREG_SCB4_INTR_SPI_EC_MASKED EQU 0x40280ecc + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_M +CYREG_SCB4_INTR_M EQU 0x40280f00 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_M_SET +CYREG_SCB4_INTR_M_SET EQU 0x40280f04 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_M_MASK +CYREG_SCB4_INTR_M_MASK EQU 0x40280f08 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_M_MASKED +CYREG_SCB4_INTR_M_MASKED EQU 0x40280f0c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_S +CYREG_SCB4_INTR_S EQU 0x40280f40 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_S_SET +CYREG_SCB4_INTR_S_SET EQU 0x40280f44 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_S_MASK +CYREG_SCB4_INTR_S_MASK EQU 0x40280f48 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_S_MASKED +CYREG_SCB4_INTR_S_MASKED EQU 0x40280f4c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_TX +CYREG_SCB4_INTR_TX EQU 0x40280f80 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_TX_SET +CYREG_SCB4_INTR_TX_SET EQU 0x40280f84 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_TX_MASK +CYREG_SCB4_INTR_TX_MASK EQU 0x40280f88 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_TX_MASKED +CYREG_SCB4_INTR_TX_MASKED EQU 0x40280f8c + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_RX +CYREG_SCB4_INTR_RX EQU 0x40280fc0 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_RX_SET +CYREG_SCB4_INTR_RX_SET EQU 0x40280fc4 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_RX_MASK +CYREG_SCB4_INTR_RX_MASK EQU 0x40280fc8 + ENDIF + IF :LNOT::DEF:CYREG_SCB4_INTR_RX_MASKED +CYREG_SCB4_INTR_RX_MASKED EQU 0x40280fcc + ENDIF + IF :LNOT::DEF:CYDEV_CSD_BASE +CYDEV_CSD_BASE EQU 0x40290000 + ENDIF + IF :LNOT::DEF:CYDEV_CSD_SIZE +CYDEV_CSD_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_CSD_CONFIG +CYREG_CSD_CONFIG EQU 0x40290000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LOW_VDDA__OFFSET +CYFLD_CSD_LOW_VDDA__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LOW_VDDA__SIZE +CYFLD_CSD_LOW_VDDA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_FILTER_DELAY__OFFSET +CYFLD_CSD_FILTER_DELAY__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_FILTER_DELAY__SIZE +CYFLD_CSD_FILTER_DELAY__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SHIELD_DELAY__OFFSET +CYFLD_CSD_SHIELD_DELAY__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SHIELD_DELAY__SIZE +CYFLD_CSD_SHIELD_DELAY__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SHIELD_DELAY_OFF +CYVAL_CSD_SHIELD_DELAY_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SHIELD_DELAY_D5NS +CYVAL_CSD_SHIELD_DELAY_D5NS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SHIELD_DELAY_D10NS +CYVAL_CSD_SHIELD_DELAY_D10NS EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_SHIELD_DELAY_D20NS +CYVAL_CSD_SHIELD_DELAY_D20NS EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_EN__OFFSET +CYFLD_CSD_SENSE_EN__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_EN__SIZE +CYFLD_CSD_SENSE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CHARGE_MODE__OFFSET +CYFLD_CSD_CHARGE_MODE__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CHARGE_MODE__SIZE +CYFLD_CSD_CHARGE_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CHARGE_MODE_CHARGE_OFF +CYVAL_CSD_CHARGE_MODE_CHARGE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CHARGE_MODE_CHARGE_IO +CYVAL_CSD_CHARGE_MODE_CHARGE_IO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_FULL_WAVE__OFFSET +CYFLD_CSD_FULL_WAVE__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_FULL_WAVE__SIZE +CYFLD_CSD_FULL_WAVE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_FULL_WAVE_HALFWAVE +CYVAL_CSD_FULL_WAVE_HALFWAVE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_FULL_WAVE_FULLWAVE +CYVAL_CSD_FULL_WAVE_FULLWAVE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_MUTUAL_CAP__OFFSET +CYFLD_CSD_MUTUAL_CAP__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_MUTUAL_CAP__SIZE +CYFLD_CSD_MUTUAL_CAP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_MUTUAL_CAP_SELFCAP +CYVAL_CSD_MUTUAL_CAP_SELFCAP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_MUTUAL_CAP_MUTUALCAP +CYVAL_CSD_MUTUAL_CAP_MUTUALCAP EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSX_DUAL_CNT__OFFSET +CYFLD_CSD_CSX_DUAL_CNT__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSX_DUAL_CNT__SIZE +CYFLD_CSD_CSX_DUAL_CNT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CSX_DUAL_CNT_ONE +CYVAL_CSD_CSX_DUAL_CNT_ONE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CSX_DUAL_CNT_TWO +CYVAL_CSD_CSX_DUAL_CNT_TWO EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_COUNT_SEL__OFFSET +CYFLD_CSD_DSI_COUNT_SEL__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_COUNT_SEL__SIZE +CYFLD_CSD_DSI_COUNT_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DSI_COUNT_SEL_CSD_RESULT +CYVAL_CSD_DSI_COUNT_SEL_CSD_RESULT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_DSI_COUNT_SEL_ADC_RESULT +CYVAL_CSD_DSI_COUNT_SEL_ADC_RESULT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SAMPLE_EN__OFFSET +CYFLD_CSD_DSI_SAMPLE_EN__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SAMPLE_EN__SIZE +CYFLD_CSD_DSI_SAMPLE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE_SYNC__OFFSET +CYFLD_CSD_SAMPLE_SYNC__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE_SYNC__SIZE +CYFLD_CSD_SAMPLE_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SENSE_EN__OFFSET +CYFLD_CSD_DSI_SENSE_EN__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_SENSE_EN__SIZE +CYFLD_CSD_DSI_SENSE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LP_MODE__OFFSET +CYFLD_CSD_LP_MODE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LP_MODE__SIZE +CYFLD_CSD_LP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ENABLE__OFFSET +CYFLD_CSD_ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ENABLE__SIZE +CYFLD_CSD_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SPARE +CYREG_CSD_SPARE EQU 0x40290004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SPARE__OFFSET +CYFLD_CSD_SPARE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SPARE__SIZE +CYFLD_CSD_SPARE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CSD_STATUS +CYREG_CSD_STATUS EQU 0x40290080 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_CHARGE__OFFSET +CYFLD_CSD_CSD_CHARGE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_CHARGE__SIZE +CYFLD_CSD_CSD_CHARGE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_SENSE__OFFSET +CYFLD_CSD_CSD_SENSE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSD_SENSE__SIZE +CYFLD_CSD_CSD_SENSE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_HSCMP_OUT__OFFSET +CYFLD_CSD_HSCMP_OUT__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_HSCMP_OUT__SIZE +CYFLD_CSD_HSCMP_OUT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_HSCMP_OUT_C_LT_VREF +CYVAL_CSD_HSCMP_OUT_C_LT_VREF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_HSCMP_OUT_C_GT_VREF +CYVAL_CSD_HSCMP_OUT_C_GT_VREF EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSDCMP_OUT__OFFSET +CYFLD_CSD_CSDCMP_OUT__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSDCMP_OUT__SIZE +CYFLD_CSD_CSDCMP_OUT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_STAT_SEQ +CYREG_CSD_STAT_SEQ EQU 0x40290084 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SEQ_STATE__OFFSET +CYFLD_CSD_SEQ_STATE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SEQ_STATE__SIZE +CYFLD_CSD_SEQ_STATE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_STATE__OFFSET +CYFLD_CSD_ADC_STATE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_STATE__SIZE +CYFLD_CSD_ADC_STATE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CSD_STAT_CNTS +CYREG_CSD_STAT_CNTS EQU 0x40290088 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_NUM_CONV__OFFSET +CYFLD_CSD_NUM_CONV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_NUM_CONV__SIZE +CYFLD_CSD_NUM_CONV__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CSD_STAT_HCNT +CYREG_CSD_STAT_HCNT EQU 0x4029008c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CNT__OFFSET +CYFLD_CSD_CNT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CNT__SIZE +CYFLD_CSD_CNT__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CSD_RESULT_VAL1 +CYREG_CSD_RESULT_VAL1 EQU 0x402900d0 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VALUE__OFFSET +CYFLD_CSD_VALUE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VALUE__SIZE +CYFLD_CSD_VALUE__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_BAD_CONVS__OFFSET +CYFLD_CSD_BAD_CONVS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_BAD_CONVS__SIZE +CYFLD_CSD_BAD_CONVS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CSD_RESULT_VAL2 +CYREG_CSD_RESULT_VAL2 EQU 0x402900d4 + ENDIF + IF :LNOT::DEF:CYREG_CSD_ADC_RES +CYREG_CSD_ADC_RES EQU 0x402900e0 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VIN_CNT__OFFSET +CYFLD_CSD_VIN_CNT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VIN_CNT__SIZE +CYFLD_CSD_VIN_CNT__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_HSCMP_POL__OFFSET +CYFLD_CSD_HSCMP_POL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_HSCMP_POL__SIZE +CYFLD_CSD_HSCMP_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_OVERFLOW__OFFSET +CYFLD_CSD_ADC_OVERFLOW__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_OVERFLOW__SIZE +CYFLD_CSD_ADC_OVERFLOW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_ABORT__OFFSET +CYFLD_CSD_ADC_ABORT__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_ABORT__SIZE +CYFLD_CSD_ADC_ABORT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_INTR +CYREG_CSD_INTR EQU 0x402900f0 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE__OFFSET +CYFLD_CSD_SAMPLE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SAMPLE__SIZE +CYFLD_CSD_SAMPLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_INIT__OFFSET +CYFLD_CSD_INIT__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_INIT__SIZE +CYFLD_CSD_INIT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_RES__OFFSET +CYFLD_CSD_ADC_RES__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_RES__SIZE +CYFLD_CSD_ADC_RES__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_INTR_SET +CYREG_CSD_INTR_SET EQU 0x402900f4 + ENDIF + IF :LNOT::DEF:CYREG_CSD_INTR_MASK +CYREG_CSD_INTR_MASK EQU 0x402900f8 + ENDIF + IF :LNOT::DEF:CYREG_CSD_INTR_MASKED +CYREG_CSD_INTR_MASKED EQU 0x402900fc + ENDIF + IF :LNOT::DEF:CYREG_CSD_HSCMP +CYREG_CSD_HSCMP EQU 0x40290180 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_HSCMP_EN__OFFSET +CYFLD_CSD_HSCMP_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_HSCMP_EN__SIZE +CYFLD_CSD_HSCMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_HSCMP_EN_OFF +CYVAL_CSD_HSCMP_EN_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_HSCMP_EN_ON +CYVAL_CSD_HSCMP_EN_ON EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_HSCMP_INVERT__OFFSET +CYFLD_CSD_HSCMP_INVERT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_HSCMP_INVERT__SIZE +CYFLD_CSD_HSCMP_INVERT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_AZ_EN__OFFSET +CYFLD_CSD_AZ_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CSD_AZ_EN__SIZE +CYFLD_CSD_AZ_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_AMBUF +CYREG_CSD_AMBUF EQU 0x40290184 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PWR_MODE__OFFSET +CYFLD_CSD_PWR_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_PWR_MODE__SIZE +CYFLD_CSD_PWR_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_PWR_MODE_OFF +CYVAL_CSD_PWR_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_PWR_MODE_NORM +CYVAL_CSD_PWR_MODE_NORM EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_PWR_MODE_HI +CYVAL_CSD_PWR_MODE_HI EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CSD_REFGEN +CYREG_CSD_REFGEN EQU 0x40290188 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REFGEN_EN__OFFSET +CYFLD_CSD_REFGEN_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_REFGEN_EN__SIZE +CYFLD_CSD_REFGEN_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REFGEN_EN_OFF +CYVAL_CSD_REFGEN_EN_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_REFGEN_EN_ON +CYVAL_CSD_REFGEN_EN_ON EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_BYPASS__OFFSET +CYFLD_CSD_BYPASS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_BYPASS__SIZE +CYFLD_CSD_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VDDA_EN__OFFSET +CYFLD_CSD_VDDA_EN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VDDA_EN__SIZE +CYFLD_CSD_VDDA_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_EN__OFFSET +CYFLD_CSD_RES_EN__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_EN__SIZE +CYFLD_CSD_RES_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_GAIN__OFFSET +CYFLD_CSD_GAIN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_GAIN__SIZE +CYFLD_CSD_GAIN__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VREFLO_SEL__OFFSET +CYFLD_CSD_VREFLO_SEL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VREFLO_SEL__SIZE +CYFLD_CSD_VREFLO_SEL__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VREFLO_INT__OFFSET +CYFLD_CSD_VREFLO_INT__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VREFLO_INT__SIZE +CYFLD_CSD_VREFLO_INT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_CSDCMP +CYREG_CSD_CSDCMP EQU 0x4029018c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSDCMP_EN__OFFSET +CYFLD_CSD_CSDCMP_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CSDCMP_EN__SIZE +CYFLD_CSD_CSDCMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CSDCMP_EN_OFF +CYVAL_CSD_CSDCMP_EN_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CSDCMP_EN_ON +CYVAL_CSD_CSDCMP_EN_ON EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY_SEL__OFFSET +CYFLD_CSD_POLARITY_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY_SEL__SIZE +CYFLD_CSD_POLARITY_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY_SEL_IDACA_POL +CYVAL_CSD_POLARITY_SEL_IDACA_POL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY_SEL_IDACB_POL +CYVAL_CSD_POLARITY_SEL_IDACB_POL EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY_SEL_DUAL_POL +CYVAL_CSD_POLARITY_SEL_DUAL_POL EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CMP_PHASE__OFFSET +CYFLD_CSD_CMP_PHASE__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CMP_PHASE__SIZE +CYFLD_CSD_CMP_PHASE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CMP_PHASE_FULL +CYVAL_CSD_CMP_PHASE_FULL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CMP_PHASE_PHI1 +CYVAL_CSD_CMP_PHASE_PHI1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CMP_PHASE_PHI2 +CYVAL_CSD_CMP_PHASE_PHI2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CMP_PHASE_PHI1_2 +CYVAL_CSD_CMP_PHASE_PHI1_2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CMP_MODE__OFFSET +CYFLD_CSD_CMP_MODE__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CMP_MODE__SIZE +CYFLD_CSD_CMP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CMP_MODE_CSD +CYVAL_CSD_CMP_MODE_CSD EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_CMP_MODE_GP +CYVAL_CSD_CMP_MODE_GP EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_FEEDBACK_MODE__OFFSET +CYFLD_CSD_FEEDBACK_MODE__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_CSD_FEEDBACK_MODE__SIZE +CYFLD_CSD_FEEDBACK_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_FEEDBACK_MODE_FLOP +CYVAL_CSD_FEEDBACK_MODE_FLOP EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_FEEDBACK_MODE_COMP +CYVAL_CSD_FEEDBACK_MODE_COMP EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_IDACA +CYREG_CSD_IDACA EQU 0x402901c0 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VAL__OFFSET +CYFLD_CSD_VAL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_VAL__SIZE +CYFLD_CSD_VAL__SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POL_DYN__OFFSET +CYFLD_CSD_POL_DYN__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POL_DYN__SIZE +CYFLD_CSD_POL_DYN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POL_DYN_STATIC +CYVAL_CSD_POL_DYN_STATIC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POL_DYN_DYNAMIC +CYVAL_CSD_POL_DYN_DYNAMIC EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY__OFFSET +CYFLD_CSD_POLARITY__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_POLARITY__SIZE +CYFLD_CSD_POLARITY__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY_VSSA_SRC +CYVAL_CSD_POLARITY_VSSA_SRC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY_VDDA_SNK +CYVAL_CSD_POLARITY_VDDA_SNK EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY_SENSE +CYVAL_CSD_POLARITY_SENSE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_POLARITY_SENSE_INV +CYVAL_CSD_POLARITY_SENSE_INV EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_BAL_MODE__OFFSET +CYFLD_CSD_BAL_MODE__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_CSD_BAL_MODE__SIZE +CYFLD_CSD_BAL_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_BAL_MODE_FULL +CYVAL_CSD_BAL_MODE_FULL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_BAL_MODE_PHI1 +CYVAL_CSD_BAL_MODE_PHI1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_BAL_MODE_PHI2 +CYVAL_CSD_BAL_MODE_PHI2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_BAL_MODE_PHI1_2 +CYVAL_CSD_BAL_MODE_PHI1_2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LEG1_MODE__OFFSET +CYFLD_CSD_LEG1_MODE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LEG1_MODE__SIZE +CYFLD_CSD_LEG1_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LEG1_MODE_GP_STATIC +CYVAL_CSD_LEG1_MODE_GP_STATIC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LEG1_MODE_GP +CYVAL_CSD_LEG1_MODE_GP EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LEG1_MODE_CSD_STATIC +CYVAL_CSD_LEG1_MODE_CSD_STATIC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LEG1_MODE_CSD +CYVAL_CSD_LEG1_MODE_CSD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LEG2_MODE__OFFSET +CYFLD_CSD_LEG2_MODE__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LEG2_MODE__SIZE +CYFLD_CSD_LEG2_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LEG2_MODE_GP_STATIC +CYVAL_CSD_LEG2_MODE_GP_STATIC EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LEG2_MODE_GP +CYVAL_CSD_LEG2_MODE_GP EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LEG2_MODE_CSD_STATIC +CYVAL_CSD_LEG2_MODE_CSD_STATIC EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LEG2_MODE_CSD +CYVAL_CSD_LEG2_MODE_CSD EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_CTRL_EN__OFFSET +CYFLD_CSD_DSI_CTRL_EN__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_CTRL_EN__SIZE +CYFLD_CSD_DSI_CTRL_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RANGE__OFFSET +CYFLD_CSD_RANGE__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RANGE__SIZE +CYFLD_CSD_RANGE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RANGE_IDAC_LO +CYVAL_CSD_RANGE_IDAC_LO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RANGE_IDAC_MED +CYVAL_CSD_RANGE_IDAC_MED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RANGE_IDAC_HI +CYVAL_CSD_RANGE_IDAC_HI EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RANGE_IDAC_MED2 +CYVAL_CSD_RANGE_IDAC_MED2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LEG1_EN__OFFSET +CYFLD_CSD_LEG1_EN__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LEG1_EN__SIZE +CYFLD_CSD_LEG1_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LEG2_EN__OFFSET +CYFLD_CSD_LEG2_EN__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LEG2_EN__SIZE +CYFLD_CSD_LEG2_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_IDACB +CYREG_CSD_IDACB EQU 0x402901c4 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LEG3_EN__OFFSET +CYFLD_CSD_LEG3_EN__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LEG3_EN__SIZE +CYFLD_CSD_LEG3_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_RES +CYREG_CSD_SW_RES EQU 0x402901f0 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_HCAV__OFFSET +CYFLD_CSD_RES_HCAV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_HCAV__SIZE +CYFLD_CSD_RES_HCAV__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RES_HCAV_LOW +CYVAL_CSD_RES_HCAV_LOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RES_HCAV_MED +CYVAL_CSD_RES_HCAV_MED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RES_HCAV_HIGH +CYVAL_CSD_RES_HCAV_HIGH EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RES_HCAV_LOWEMI +CYVAL_CSD_RES_HCAV_LOWEMI EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_HCAG__OFFSET +CYFLD_CSD_RES_HCAG__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_HCAG__SIZE +CYFLD_CSD_RES_HCAG__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_HCBV__OFFSET +CYFLD_CSD_RES_HCBV__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_HCBV__SIZE +CYFLD_CSD_RES_HCBV__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_HCBG__OFFSET +CYFLD_CSD_RES_HCBG__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_HCBG__SIZE +CYFLD_CSD_RES_HCBG__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_F1PM__OFFSET +CYFLD_CSD_RES_F1PM__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_F1PM__SIZE +CYFLD_CSD_RES_F1PM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RES_F1PM_LOW +CYVAL_CSD_RES_F1PM_LOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RES_F1PM_MED +CYVAL_CSD_RES_F1PM_MED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RES_F1PM_HIGH +CYVAL_CSD_RES_F1PM_HIGH EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_RES_F1PM_RESERVED +CYVAL_CSD_RES_F1PM_RESERVED EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_F2PT__OFFSET +CYFLD_CSD_RES_F2PT__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_RES_F2PT__SIZE +CYFLD_CSD_RES_F2PT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SENSE_PERIOD +CYREG_CSD_SENSE_PERIOD EQU 0x40290200 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_DIV__OFFSET +CYFLD_CSD_SENSE_DIV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_DIV__SIZE +CYFLD_CSD_SENSE_DIV__SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LFSR_SIZE__OFFSET +CYFLD_CSD_LFSR_SIZE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LFSR_SIZE__SIZE +CYFLD_CSD_LFSR_SIZE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LFSR_SIZE_OFF +CYVAL_CSD_LFSR_SIZE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LFSR_SIZE_6B +CYVAL_CSD_LFSR_SIZE_6B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LFSR_SIZE_7B +CYVAL_CSD_LFSR_SIZE_7B EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LFSR_SIZE_9B +CYVAL_CSD_LFSR_SIZE_9B EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LFSR_SIZE_10B +CYVAL_CSD_LFSR_SIZE_10B EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LFSR_SIZE_8B +CYVAL_CSD_LFSR_SIZE_8B EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LFSR_SIZE_12B +CYVAL_CSD_LFSR_SIZE_12B EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LFSR_SCALE__OFFSET +CYFLD_CSD_LFSR_SCALE__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LFSR_SCALE__SIZE +CYFLD_CSD_LFSR_SCALE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LFSR_CLEAR__OFFSET +CYFLD_CSD_LFSR_CLEAR__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LFSR_CLEAR__SIZE +CYFLD_CSD_LFSR_CLEAR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SEL_LFSR_MSB__OFFSET +CYFLD_CSD_SEL_LFSR_MSB__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SEL_LFSR_MSB__SIZE +CYFLD_CSD_SEL_LFSR_MSB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LFSR_BITS__OFFSET +CYFLD_CSD_LFSR_BITS__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_CSD_LFSR_BITS__SIZE +CYFLD_CSD_LFSR_BITS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LFSR_BITS_2B +CYVAL_CSD_LFSR_BITS_2B EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LFSR_BITS_3B +CYVAL_CSD_LFSR_BITS_3B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LFSR_BITS_4B +CYVAL_CSD_LFSR_BITS_4B EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_LFSR_BITS_5B +CYVAL_CSD_LFSR_BITS_5B EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SENSE_DUTY +CYREG_CSD_SENSE_DUTY EQU 0x40290204 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_WIDTH__OFFSET +CYFLD_CSD_SENSE_WIDTH__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_WIDTH__SIZE +CYFLD_CSD_SENSE_WIDTH__SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_POL__OFFSET +CYFLD_CSD_SENSE_POL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SENSE_POL__SIZE +CYFLD_CSD_SENSE_POL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_OVERLAP_PHI1__OFFSET +CYFLD_CSD_OVERLAP_PHI1__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_OVERLAP_PHI1__SIZE +CYFLD_CSD_OVERLAP_PHI1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_OVERLAP_PHI2__OFFSET +CYFLD_CSD_OVERLAP_PHI2__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_OVERLAP_PHI2__SIZE +CYFLD_CSD_OVERLAP_PHI2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_HS_P_SEL +CYREG_CSD_SW_HS_P_SEL EQU 0x40290280 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMPM__OFFSET +CYFLD_CSD_SW_HMPM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMPM__SIZE +CYFLD_CSD_SW_HMPM__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMPT__OFFSET +CYFLD_CSD_SW_HMPT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMPT__SIZE +CYFLD_CSD_SW_HMPT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMPS__OFFSET +CYFLD_CSD_SW_HMPS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMPS__SIZE +CYFLD_CSD_SW_HMPS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMMA__OFFSET +CYFLD_CSD_SW_HMMA__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMMA__SIZE +CYFLD_CSD_SW_HMMA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMMB__OFFSET +CYFLD_CSD_SW_HMMB__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMMB__SIZE +CYFLD_CSD_SW_HMMB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMCA__OFFSET +CYFLD_CSD_SW_HMCA__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMCA__SIZE +CYFLD_CSD_SW_HMCA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMCB__OFFSET +CYFLD_CSD_SW_HMCB__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMCB__SIZE +CYFLD_CSD_SW_HMCB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMRH__OFFSET +CYFLD_CSD_SW_HMRH__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMRH__SIZE +CYFLD_CSD_SW_HMRH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_HS_N_SEL +CYREG_CSD_SW_HS_N_SEL EQU 0x40290284 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCCC__OFFSET +CYFLD_CSD_SW_HCCC__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCCC__SIZE +CYFLD_CSD_SW_HCCC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCCD__OFFSET +CYFLD_CSD_SW_HCCD__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCCD__SIZE +CYFLD_CSD_SW_HCCD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCRH__OFFSET +CYFLD_CSD_SW_HCRH__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCRH__SIZE +CYFLD_CSD_SW_HCRH__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCRL__OFFSET +CYFLD_CSD_SW_HCRL__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCRL__SIZE +CYFLD_CSD_SW_HCRL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_SHIELD_SEL +CYREG_CSD_SW_SHIELD_SEL EQU 0x40290288 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCAV__OFFSET +CYFLD_CSD_SW_HCAV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCAV__SIZE +CYFLD_CSD_SW_HCAV__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCAG__OFFSET +CYFLD_CSD_SW_HCAG__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCAG__SIZE +CYFLD_CSD_SW_HCAG__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCBV__OFFSET +CYFLD_CSD_SW_HCBV__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCBV__SIZE +CYFLD_CSD_SW_HCBV__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCBG__OFFSET +CYFLD_CSD_SW_HCBG__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCBG__SIZE +CYFLD_CSD_SW_HCBG__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCCV__OFFSET +CYFLD_CSD_SW_HCCV__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCCV__SIZE +CYFLD_CSD_SW_HCCV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCCG__OFFSET +CYFLD_CSD_SW_HCCG__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HCCG__SIZE +CYFLD_CSD_SW_HCCG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_HS_P_SEL1 +CYREG_CSD_SW_HS_P_SEL1 EQU 0x4029028c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMRE__OFFSET +CYFLD_CSD_SW_HMRE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_HMRE__SIZE +CYFLD_CSD_SW_HMRE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_AMUXBUF_SEL +CYREG_CSD_SW_AMUXBUF_SEL EQU 0x40290290 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IRBY__OFFSET +CYFLD_CSD_SW_IRBY__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IRBY__SIZE +CYFLD_CSD_SW_IRBY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IRLB__OFFSET +CYFLD_CSD_SW_IRLB__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IRLB__SIZE +CYFLD_CSD_SW_IRLB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_ICA__OFFSET +CYFLD_CSD_SW_ICA__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_ICA__SIZE +CYFLD_CSD_SW_ICA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_ICB__OFFSET +CYFLD_CSD_SW_ICB__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_ICB__SIZE +CYFLD_CSD_SW_ICB__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IRLI__OFFSET +CYFLD_CSD_SW_IRLI__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IRLI__SIZE +CYFLD_CSD_SW_IRLI__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IRH__OFFSET +CYFLD_CSD_SW_IRH__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IRH__SIZE +CYFLD_CSD_SW_IRH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IRL__OFFSET +CYFLD_CSD_SW_IRL__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IRL__SIZE +CYFLD_CSD_SW_IRL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_BYP_SEL +CYREG_CSD_SW_BYP_SEL EQU 0x40290294 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_BYA__OFFSET +CYFLD_CSD_SW_BYA__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_BYA__SIZE +CYFLD_CSD_SW_BYA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_BYB__OFFSET +CYFLD_CSD_SW_BYB__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_BYB__SIZE +CYFLD_CSD_SW_BYB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_CBCC__OFFSET +CYFLD_CSD_SW_CBCC__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_CBCC__SIZE +CYFLD_CSD_SW_CBCC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_CMP_P_SEL +CYREG_CSD_SW_CMP_P_SEL EQU 0x402902a0 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFPM__OFFSET +CYFLD_CSD_SW_SFPM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFPM__SIZE +CYFLD_CSD_SW_SFPM__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFPT__OFFSET +CYFLD_CSD_SW_SFPT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFPT__SIZE +CYFLD_CSD_SW_SFPT__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFPS__OFFSET +CYFLD_CSD_SW_SFPS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFPS__SIZE +CYFLD_CSD_SW_SFPS__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFMA__OFFSET +CYFLD_CSD_SW_SFMA__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFMA__SIZE +CYFLD_CSD_SW_SFMA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFMB__OFFSET +CYFLD_CSD_SW_SFMB__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFMB__SIZE +CYFLD_CSD_SW_SFMB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFCA__OFFSET +CYFLD_CSD_SW_SFCA__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFCA__SIZE +CYFLD_CSD_SW_SFCA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFCB__OFFSET +CYFLD_CSD_SW_SFCB__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SFCB__SIZE +CYFLD_CSD_SW_SFCB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_CMP_N_SEL +CYREG_CSD_SW_CMP_N_SEL EQU 0x402902a4 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SCRH__OFFSET +CYFLD_CSD_SW_SCRH__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SCRH__SIZE +CYFLD_CSD_SW_SCRH__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SCRL__OFFSET +CYFLD_CSD_SW_SCRL__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SCRL__SIZE +CYFLD_CSD_SW_SCRL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_REFGEN_SEL +CYREG_CSD_SW_REFGEN_SEL EQU 0x402902a8 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IAIB__OFFSET +CYFLD_CSD_SW_IAIB__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IAIB__SIZE +CYFLD_CSD_SW_IAIB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IBCB__OFFSET +CYFLD_CSD_SW_IBCB__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_IBCB__SIZE +CYFLD_CSD_SW_IBCB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SGMB__OFFSET +CYFLD_CSD_SW_SGMB__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SGMB__SIZE +CYFLD_CSD_SW_SGMB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SGRE__OFFSET +CYFLD_CSD_SW_SGRE__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SGRE__SIZE +CYFLD_CSD_SW_SGRE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SGR__OFFSET +CYFLD_CSD_SW_SGR__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_SGR__SIZE +CYFLD_CSD_SW_SGR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_FW_MOD_SEL +CYREG_CSD_SW_FW_MOD_SEL EQU 0x402902b0 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F1PM__OFFSET +CYFLD_CSD_SW_F1PM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F1PM__SIZE +CYFLD_CSD_SW_F1PM__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F1MA__OFFSET +CYFLD_CSD_SW_F1MA__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F1MA__SIZE +CYFLD_CSD_SW_F1MA__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F1CA__OFFSET +CYFLD_CSD_SW_F1CA__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F1CA__SIZE +CYFLD_CSD_SW_F1CA__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C1CC__OFFSET +CYFLD_CSD_SW_C1CC__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C1CC__SIZE +CYFLD_CSD_SW_C1CC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C1CD__OFFSET +CYFLD_CSD_SW_C1CD__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C1CD__SIZE +CYFLD_CSD_SW_C1CD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C1F1__OFFSET +CYFLD_CSD_SW_C1F1__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C1F1__SIZE +CYFLD_CSD_SW_C1F1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_FW_TANK_SEL +CYREG_CSD_SW_FW_TANK_SEL EQU 0x402902b4 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F2PT__OFFSET +CYFLD_CSD_SW_F2PT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F2PT__SIZE +CYFLD_CSD_SW_F2PT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F2MA__OFFSET +CYFLD_CSD_SW_F2MA__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F2MA__SIZE +CYFLD_CSD_SW_F2MA__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F2CA__OFFSET +CYFLD_CSD_SW_F2CA__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F2CA__SIZE +CYFLD_CSD_SW_F2CA__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F2CB__OFFSET +CYFLD_CSD_SW_F2CB__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_F2CB__SIZE +CYFLD_CSD_SW_F2CB__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C2CC__OFFSET +CYFLD_CSD_SW_C2CC__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C2CC__SIZE +CYFLD_CSD_SW_C2CC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C2CD__OFFSET +CYFLD_CSD_SW_C2CD__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C2CD__SIZE +CYFLD_CSD_SW_C2CD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C2F2__OFFSET +CYFLD_CSD_SW_C2F2__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SW_C2F2__SIZE +CYFLD_CSD_SW_C2F2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SW_DSI_SEL +CYREG_CSD_SW_DSI_SEL EQU 0x402902c0 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_CSH_TANK__OFFSET +CYFLD_CSD_DSI_CSH_TANK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_CSH_TANK__SIZE +CYFLD_CSD_DSI_CSH_TANK__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_CMOD__OFFSET +CYFLD_CSD_DSI_CMOD__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_CMOD__SIZE +CYFLD_CSD_DSI_CMOD__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SEQ_TIME +CYREG_CSD_SEQ_TIME EQU 0x40290300 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_AZ_TIME__OFFSET +CYFLD_CSD_AZ_TIME__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_AZ_TIME__SIZE +CYFLD_CSD_AZ_TIME__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SEQ_INIT_CNT +CYREG_CSD_SEQ_INIT_CNT EQU 0x40290310 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CONV_CNT__OFFSET +CYFLD_CSD_CONV_CNT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_CONV_CNT__SIZE +CYFLD_CSD_CONV_CNT__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SEQ_NORM_CNT +CYREG_CSD_SEQ_NORM_CNT EQU 0x40290314 + ENDIF + IF :LNOT::DEF:CYREG_CSD_ADC_CTL +CYREG_CSD_ADC_CTL EQU 0x40290320 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_TIME__OFFSET +CYFLD_CSD_ADC_TIME__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_TIME__SIZE +CYFLD_CSD_ADC_TIME__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_MODE__OFFSET +CYFLD_CSD_ADC_MODE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ADC_MODE__SIZE +CYFLD_CSD_ADC_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_ADC_MODE_OFF +CYVAL_CSD_ADC_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_ADC_MODE_VREF_CNT +CYVAL_CSD_ADC_MODE_VREF_CNT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_ADC_MODE_VREF_BY2_CNT +CYVAL_CSD_ADC_MODE_VREF_BY2_CNT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CSD_ADC_MODE_VIN_CNT +CYVAL_CSD_ADC_MODE_VIN_CNT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CSD_SEQ_START +CYREG_CSD_SEQ_START EQU 0x40290340 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_START__OFFSET +CYFLD_CSD_START__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_START__SIZE +CYFLD_CSD_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SEQ_MODE__OFFSET +CYFLD_CSD_SEQ_MODE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_SEQ_MODE__SIZE +CYFLD_CSD_SEQ_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ABORT__OFFSET +CYFLD_CSD_ABORT__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_ABORT__SIZE +CYFLD_CSD_ABORT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_START_EN__OFFSET +CYFLD_CSD_DSI_START_EN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_DSI_START_EN__SIZE +CYFLD_CSD_DSI_START_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_AZ0_SKIP__OFFSET +CYFLD_CSD_AZ0_SKIP__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_AZ0_SKIP__SIZE +CYFLD_CSD_AZ0_SKIP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_AZ1_SKIP__OFFSET +CYFLD_CSD_AZ1_SKIP__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CSD_AZ1_SKIP__SIZE +CYFLD_CSD_AZ1_SKIP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_LCD_BASE +CYDEV_LCD_BASE EQU 0x402a0000 + ENDIF + IF :LNOT::DEF:CYDEV_LCD_SIZE +CYDEV_LCD_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_LCD_ID +CYREG_LCD_ID EQU 0x402a0000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_ID__OFFSET +CYFLD_LCD_ID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_ID__SIZE +CYFLD_LCD_ID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_REVISION__OFFSET +CYFLD_LCD_REVISION__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_REVISION__SIZE +CYFLD_LCD_REVISION__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DIVIDER +CYREG_LCD_DIVIDER EQU 0x402a0004 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_SUBFR_DIV__OFFSET +CYFLD_LCD_SUBFR_DIV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_SUBFR_DIV__SIZE +CYFLD_LCD_SUBFR_DIV__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DEAD_DIV__OFFSET +CYFLD_LCD_DEAD_DIV__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DEAD_DIV__SIZE +CYFLD_LCD_DEAD_DIV__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_LCD_CONTROL +CYREG_LCD_CONTROL EQU 0x402a0008 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN__OFFSET +CYFLD_LCD_LS_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN__SIZE +CYFLD_LCD_LS_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_HS_EN__OFFSET +CYFLD_LCD_HS_EN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_HS_EN__SIZE +CYFLD_LCD_HS_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LCD_MODE__OFFSET +CYFLD_LCD_LCD_MODE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LCD_MODE__SIZE +CYFLD_LCD_LCD_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_LCD_MODE_LS +CYVAL_LCD_LCD_MODE_LS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_LCD_MODE_HS +CYVAL_LCD_LCD_MODE_HS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_TYPE__OFFSET +CYFLD_LCD_TYPE__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_TYPE__SIZE +CYFLD_LCD_TYPE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_TYPE_TYPE_A +CYVAL_LCD_TYPE_TYPE_A EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_TYPE_TYPE_B +CYVAL_LCD_TYPE_TYPE_B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_OP_MODE__OFFSET +CYFLD_LCD_OP_MODE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_OP_MODE__SIZE +CYFLD_LCD_OP_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_OP_MODE_PWM +CYVAL_LCD_OP_MODE_PWM EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_OP_MODE_CORRELATION +CYVAL_LCD_OP_MODE_CORRELATION EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_BIAS__OFFSET +CYFLD_LCD_BIAS__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_BIAS__SIZE +CYFLD_LCD_BIAS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_HALF +CYVAL_LCD_BIAS_HALF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_THIRD +CYVAL_LCD_BIAS_THIRD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_FOURTH +CYVAL_LCD_BIAS_FOURTH EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LCD_BIAS_FIFTH +CYVAL_LCD_BIAS_FIFTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_COM_NUM__OFFSET +CYFLD_LCD_COM_NUM__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_COM_NUM__SIZE +CYFLD_LCD_COM_NUM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN_STAT__OFFSET +CYFLD_LCD_LS_EN_STAT__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_LCD_LS_EN_STAT__SIZE +CYFLD_LCD_LS_EN_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA00 +CYREG_LCD_DATA00 EQU 0x402a0100 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DATA__OFFSET +CYFLD_LCD_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LCD_DATA__SIZE +CYFLD_LCD_DATA__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA01 +CYREG_LCD_DATA01 EQU 0x402a0104 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA02 +CYREG_LCD_DATA02 EQU 0x402a0108 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA03 +CYREG_LCD_DATA03 EQU 0x402a010c + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA04 +CYREG_LCD_DATA04 EQU 0x402a0110 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA05 +CYREG_LCD_DATA05 EQU 0x402a0114 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA06 +CYREG_LCD_DATA06 EQU 0x402a0118 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA07 +CYREG_LCD_DATA07 EQU 0x402a011c + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA10 +CYREG_LCD_DATA10 EQU 0x402a0200 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA11 +CYREG_LCD_DATA11 EQU 0x402a0204 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA12 +CYREG_LCD_DATA12 EQU 0x402a0208 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA13 +CYREG_LCD_DATA13 EQU 0x402a020c + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA14 +CYREG_LCD_DATA14 EQU 0x402a0210 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA15 +CYREG_LCD_DATA15 EQU 0x402a0214 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA16 +CYREG_LCD_DATA16 EQU 0x402a0218 + ENDIF + IF :LNOT::DEF:CYREG_LCD_DATA17 +CYREG_LCD_DATA17 EQU 0x402a021c + ENDIF + IF :LNOT::DEF:CYDEV_LPCOMP_BASE +CYDEV_LPCOMP_BASE EQU 0x402b0000 + ENDIF + IF :LNOT::DEF:CYDEV_LPCOMP_SIZE +CYDEV_LPCOMP_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_ID +CYREG_LPCOMP_ID EQU 0x402b0000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ID__OFFSET +CYFLD_LPCOMP_ID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ID__SIZE +CYFLD_LPCOMP_ID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_REVISION__OFFSET +CYFLD_LPCOMP_REVISION__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_REVISION__SIZE +CYFLD_LPCOMP_REVISION__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_CONFIG +CYREG_LPCOMP_CONFIG EQU 0x402b0004 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE1__OFFSET +CYFLD_LPCOMP_MODE1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE1__SIZE +CYFLD_LPCOMP_MODE1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE1_SLOW +CYVAL_LPCOMP_MODE1_SLOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE1_FAST +CYVAL_LPCOMP_MODE1_FAST EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE1_ULP +CYVAL_LPCOMP_MODE1_ULP EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST1__OFFSET +CYFLD_LPCOMP_HYST1__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST1__SIZE +CYFLD_LPCOMP_HYST1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER1__OFFSET +CYFLD_LPCOMP_FILTER1__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER1__SIZE +CYFLD_LPCOMP_FILTER1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE1__OFFSET +CYFLD_LPCOMP_INTTYPE1__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE1__SIZE +CYFLD_LPCOMP_INTTYPE1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_DISABLE +CYVAL_LPCOMP_INTTYPE1_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_RISING +CYVAL_LPCOMP_INTTYPE1_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_FALLING +CYVAL_LPCOMP_INTTYPE1_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE1_BOTH +CYVAL_LPCOMP_INTTYPE1_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT1__OFFSET +CYFLD_LPCOMP_OUT1__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT1__SIZE +CYFLD_LPCOMP_OUT1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE1__OFFSET +CYFLD_LPCOMP_ENABLE1__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE1__SIZE +CYFLD_LPCOMP_ENABLE1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE2__OFFSET +CYFLD_LPCOMP_MODE2__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_MODE2__SIZE +CYFLD_LPCOMP_MODE2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE2_SLOW +CYVAL_LPCOMP_MODE2_SLOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE2_FAST +CYVAL_LPCOMP_MODE2_FAST EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_MODE2_ULP +CYVAL_LPCOMP_MODE2_ULP EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST2__OFFSET +CYFLD_LPCOMP_HYST2__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_HYST2__SIZE +CYFLD_LPCOMP_HYST2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER2__OFFSET +CYFLD_LPCOMP_FILTER2__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_FILTER2__SIZE +CYFLD_LPCOMP_FILTER2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE2__OFFSET +CYFLD_LPCOMP_INTTYPE2__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_INTTYPE2__SIZE +CYFLD_LPCOMP_INTTYPE2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_DISABLE +CYVAL_LPCOMP_INTTYPE2_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_RISING +CYVAL_LPCOMP_INTTYPE2_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_FALLING +CYVAL_LPCOMP_INTTYPE2_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_LPCOMP_INTTYPE2_BOTH +CYVAL_LPCOMP_INTTYPE2_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT2__OFFSET +CYFLD_LPCOMP_OUT2__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_OUT2__SIZE +CYFLD_LPCOMP_OUT2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE2__OFFSET +CYFLD_LPCOMP_ENABLE2__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_ENABLE2__SIZE +CYFLD_LPCOMP_ENABLE2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_DSI_BYPASS1__OFFSET +CYFLD_LPCOMP_DSI_BYPASS1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_DSI_BYPASS1__SIZE +CYFLD_LPCOMP_DSI_BYPASS1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_DSI_LEVEL1__OFFSET +CYFLD_LPCOMP_DSI_LEVEL1__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_DSI_LEVEL1__SIZE +CYFLD_LPCOMP_DSI_LEVEL1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_DSI_BYPASS2__OFFSET +CYFLD_LPCOMP_DSI_BYPASS2__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_DSI_BYPASS2__SIZE +CYFLD_LPCOMP_DSI_BYPASS2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_DSI_LEVEL2__OFFSET +CYFLD_LPCOMP_DSI_LEVEL2__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_DSI_LEVEL2__SIZE +CYFLD_LPCOMP_DSI_LEVEL2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_DFT +CYREG_LPCOMP_DFT EQU 0x402b0008 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_CAL_EN__OFFSET +CYFLD_LPCOMP_CAL_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_CAL_EN__SIZE +CYFLD_LPCOMP_CAL_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_BYPASS__OFFSET +CYFLD_LPCOMP_BYPASS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_BYPASS__SIZE +CYFLD_LPCOMP_BYPASS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_INTR +CYREG_LPCOMP_INTR EQU 0x402b0010 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1__OFFSET +CYFLD_LPCOMP_COMP1__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1__SIZE +CYFLD_LPCOMP_COMP1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2__OFFSET +CYFLD_LPCOMP_COMP2__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2__SIZE +CYFLD_LPCOMP_COMP2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_INTR_SET +CYREG_LPCOMP_INTR_SET EQU 0x402b0014 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_INTR_MASK +CYREG_LPCOMP_INTR_MASK EQU 0x402b0018 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_MASK__OFFSET +CYFLD_LPCOMP_COMP1_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_MASK__SIZE +CYFLD_LPCOMP_COMP1_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_MASK__OFFSET +CYFLD_LPCOMP_COMP2_MASK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_MASK__SIZE +CYFLD_LPCOMP_COMP2_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_INTR_MASKED +CYREG_LPCOMP_INTR_MASKED EQU 0x402b001c + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_MASKED__OFFSET +CYFLD_LPCOMP_COMP1_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_MASKED__SIZE +CYFLD_LPCOMP_COMP1_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_MASKED__OFFSET +CYFLD_LPCOMP_COMP2_MASKED__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_MASKED__SIZE +CYFLD_LPCOMP_COMP2_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM1 +CYREG_LPCOMP_TRIM1 EQU 0x402bff00 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMA__OFFSET +CYFLD_LPCOMP_COMP1_TRIMA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMA__SIZE +CYFLD_LPCOMP_COMP1_TRIMA__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM2 +CYREG_LPCOMP_TRIM2 EQU 0x402bff04 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMB__OFFSET +CYFLD_LPCOMP_COMP1_TRIMB__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP1_TRIMB__SIZE +CYFLD_LPCOMP_COMP1_TRIMB__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM3 +CYREG_LPCOMP_TRIM3 EQU 0x402bff08 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMA__OFFSET +CYFLD_LPCOMP_COMP2_TRIMA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMA__SIZE +CYFLD_LPCOMP_COMP2_TRIMA__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LPCOMP_TRIM4 +CYREG_LPCOMP_TRIM4 EQU 0x402bff0c + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMB__OFFSET +CYFLD_LPCOMP_COMP2_TRIMB__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_LPCOMP_COMP2_TRIMB__SIZE +CYFLD_LPCOMP_COMP2_TRIMB__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_CRYPTO_BASE +CYDEV_CRYPTO_BASE EQU 0x402c0000 + ENDIF + IF :LNOT::DEF:CYDEV_CRYPTO_SIZE +CYDEV_CRYPTO_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_CTL +CYREG_CRYPTO_CTL EQU 0x402c0000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_OPCODE__OFFSET +CYFLD_CRYPTO_OPCODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_OPCODE__SIZE +CYFLD_CRYPTO_OPCODE__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_CRYPTO_OPCODE_AES_FORWARD +CYVAL_CRYPTO_OPCODE_AES_FORWARD EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CRYPTO_OPCODE_AES_INVERSE +CYVAL_CRYPTO_OPCODE_AES_INVERSE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CRYPTO_OPCODE_SHA +CYVAL_CRYPTO_OPCODE_SHA EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYVAL_CRYPTO_OPCODE_CRC +CYVAL_CRYPTO_OPCODE_CRC EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_ENABLED__OFFSET +CYFLD_CRYPTO_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_ENABLED__SIZE +CYFLD_CRYPTO_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_STATUS +CYREG_CRYPTO_STATUS EQU 0x402c0004 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_BUSY__OFFSET +CYFLD_CRYPTO_BUSY__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_BUSY__SIZE +CYFLD_CRYPTO_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_CMD +CYREG_CRYPTO_CMD EQU 0x402c0008 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START__OFFSET +CYFLD_CRYPTO_START__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START__SIZE +CYFLD_CRYPTO_START__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_CTL0 +CYREG_CRYPTO_TR_CTL0 EQU 0x402c0280 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__OFFSET +CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__SIZE +CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_RED_CLOCK_DIV__OFFSET +CYFLD_CRYPTO_RED_CLOCK_DIV__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_RED_CLOCK_DIV__SIZE +CYFLD_CRYPTO_RED_CLOCK_DIV__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_INIT_DELAY__OFFSET +CYFLD_CRYPTO_INIT_DELAY__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_INIT_DELAY__SIZE +CYFLD_CRYPTO_INIT_DELAY__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_VON_NEUMANN_CORR__OFFSET +CYFLD_CRYPTO_VON_NEUMANN_CORR__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_VON_NEUMANN_CORR__SIZE +CYFLD_CRYPTO_VON_NEUMANN_CORR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_STOP_ON_AP_DETECT__OFFSET +CYFLD_CRYPTO_STOP_ON_AP_DETECT__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_STOP_ON_AP_DETECT__SIZE +CYFLD_CRYPTO_STOP_ON_AP_DETECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_STOP_ON_RC_DETECT__OFFSET +CYFLD_CRYPTO_STOP_ON_RC_DETECT__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_STOP_ON_RC_DETECT__SIZE +CYFLD_CRYPTO_STOP_ON_RC_DETECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_CTL1 +CYREG_CRYPTO_TR_CTL1 EQU 0x402c0284 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_DATA_BIT_SIZE__OFFSET +CYFLD_CRYPTO_DATA_BIT_SIZE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_DATA_BIT_SIZE__SIZE +CYFLD_CRYPTO_DATA_BIT_SIZE__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_RESULT0 +CYREG_CRYPTO_TR_RESULT0 EQU 0x402c0288 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_DATA32__OFFSET +CYFLD_CRYPTO_DATA32__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_DATA32__SIZE +CYFLD_CRYPTO_DATA32__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_RESULT1 +CYREG_CRYPTO_TR_RESULT1 EQU 0x402c028c + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_CMD +CYREG_CRYPTO_TR_CMD EQU 0x402c0290 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_RO11__OFFSET +CYFLD_CRYPTO_START_RO11__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_RO11__SIZE +CYFLD_CRYPTO_START_RO11__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_RO15__OFFSET +CYFLD_CRYPTO_START_RO15__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_RO15__SIZE +CYFLD_CRYPTO_START_RO15__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_GARO15__OFFSET +CYFLD_CRYPTO_START_GARO15__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_GARO15__SIZE +CYFLD_CRYPTO_START_GARO15__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_GARO31__OFFSET +CYFLD_CRYPTO_START_GARO31__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_GARO31__SIZE +CYFLD_CRYPTO_START_GARO31__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_FIRO15__OFFSET +CYFLD_CRYPTO_START_FIRO15__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_FIRO15__SIZE +CYFLD_CRYPTO_START_FIRO15__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_FIRO31__OFFSET +CYFLD_CRYPTO_START_FIRO31__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_FIRO31__SIZE +CYFLD_CRYPTO_START_FIRO31__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_GARO_CTL +CYREG_CRYPTO_TR_GARO_CTL EQU 0x402c02a0 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_POLYNOMIAL31__OFFSET +CYFLD_CRYPTO_POLYNOMIAL31__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_POLYNOMIAL31__SIZE +CYFLD_CRYPTO_POLYNOMIAL31__SIZE EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_FIRO_CTL +CYREG_CRYPTO_TR_FIRO_CTL EQU 0x402c02a4 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_MON_CTL +CYREG_CRYPTO_TR_MON_CTL EQU 0x402c02c0 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_BITSTREAM_SEL__OFFSET +CYFLD_CRYPTO_BITSTREAM_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_BITSTREAM_SEL__SIZE +CYFLD_CRYPTO_BITSTREAM_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_MON_CMD +CYREG_CRYPTO_TR_MON_CMD EQU 0x402c02c8 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_AP__OFFSET +CYFLD_CRYPTO_START_AP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_AP__SIZE +CYFLD_CRYPTO_START_AP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_RC__OFFSET +CYFLD_CRYPTO_START_RC__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_START_RC__SIZE +CYFLD_CRYPTO_START_RC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_MON_RC_CTL +CYREG_CRYPTO_TR_MON_RC_CTL EQU 0x402c02d0 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_CUTOFF_COUNT8__OFFSET +CYFLD_CRYPTO_CUTOFF_COUNT8__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_CUTOFF_COUNT8__SIZE +CYFLD_CRYPTO_CUTOFF_COUNT8__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_MON_RC_STATUS0 +CYREG_CRYPTO_TR_MON_RC_STATUS0 EQU 0x402c02d8 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_BIT__OFFSET +CYFLD_CRYPTO_BIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_BIT__SIZE +CYFLD_CRYPTO_BIT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_MON_RC_STATUS1 +CYREG_CRYPTO_TR_MON_RC_STATUS1 EQU 0x402c02dc + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_REP_COUNT__OFFSET +CYFLD_CRYPTO_REP_COUNT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_REP_COUNT__SIZE +CYFLD_CRYPTO_REP_COUNT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_MON_AP_CTL +CYREG_CRYPTO_TR_MON_AP_CTL EQU 0x402c02e0 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_CUTOFF_COUNT16__OFFSET +CYFLD_CRYPTO_CUTOFF_COUNT16__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_CUTOFF_COUNT16__SIZE +CYFLD_CRYPTO_CUTOFF_COUNT16__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_WINDOW_SIZE__OFFSET +CYFLD_CRYPTO_WINDOW_SIZE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_WINDOW_SIZE__SIZE +CYFLD_CRYPTO_WINDOW_SIZE__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_MON_AP_STATUS0 +CYREG_CRYPTO_TR_MON_AP_STATUS0 EQU 0x402c02e8 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_TR_MON_AP_STATUS1 +CYREG_CRYPTO_TR_MON_AP_STATUS1 EQU 0x402c02ec + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_OCC_COUNT__OFFSET +CYFLD_CRYPTO_OCC_COUNT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_OCC_COUNT__SIZE +CYFLD_CRYPTO_OCC_COUNT__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_WINDOW_INDEX__OFFSET +CYFLD_CRYPTO_WINDOW_INDEX__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_WINDOW_INDEX__SIZE +CYFLD_CRYPTO_WINDOW_INDEX__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_INTR +CYREG_CRYPTO_INTR EQU 0x402c07c0 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_DONE__OFFSET +CYFLD_CRYPTO_DONE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_DONE__SIZE +CYFLD_CRYPTO_DONE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_ACCESS_ERROR__OFFSET +CYFLD_CRYPTO_ACCESS_ERROR__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_ACCESS_ERROR__SIZE +CYFLD_CRYPTO_ACCESS_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_TR_INITIALIZED__OFFSET +CYFLD_CRYPTO_TR_INITIALIZED__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_TR_INITIALIZED__SIZE +CYFLD_CRYPTO_TR_INITIALIZED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_TR_DATA_AVAILABLE__OFFSET +CYFLD_CRYPTO_TR_DATA_AVAILABLE__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_TR_DATA_AVAILABLE__SIZE +CYFLD_CRYPTO_TR_DATA_AVAILABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_TR_AP_DETECT__OFFSET +CYFLD_CRYPTO_TR_AP_DETECT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_TR_AP_DETECT__SIZE +CYFLD_CRYPTO_TR_AP_DETECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_TR_RC_DETECT__OFFSET +CYFLD_CRYPTO_TR_RC_DETECT__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_TR_RC_DETECT__SIZE +CYFLD_CRYPTO_TR_RC_DETECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_INTR_SET +CYREG_CRYPTO_INTR_SET EQU 0x402c07c4 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_INTR_MASK +CYREG_CRYPTO_INTR_MASK EQU 0x402c07c8 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_INTR_MASKED +CYREG_CRYPTO_INTR_MASKED EQU 0x402c07cc + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF0 +CYREG_CRYPTO_MEM_BUFF0 EQU 0x402c0800 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF1 +CYREG_CRYPTO_MEM_BUFF1 EQU 0x402c0804 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF2 +CYREG_CRYPTO_MEM_BUFF2 EQU 0x402c0808 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF3 +CYREG_CRYPTO_MEM_BUFF3 EQU 0x402c080c + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF4 +CYREG_CRYPTO_MEM_BUFF4 EQU 0x402c0810 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF5 +CYREG_CRYPTO_MEM_BUFF5 EQU 0x402c0814 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF6 +CYREG_CRYPTO_MEM_BUFF6 EQU 0x402c0818 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF7 +CYREG_CRYPTO_MEM_BUFF7 EQU 0x402c081c + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF8 +CYREG_CRYPTO_MEM_BUFF8 EQU 0x402c0820 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF9 +CYREG_CRYPTO_MEM_BUFF9 EQU 0x402c0824 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF10 +CYREG_CRYPTO_MEM_BUFF10 EQU 0x402c0828 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF11 +CYREG_CRYPTO_MEM_BUFF11 EQU 0x402c082c + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF12 +CYREG_CRYPTO_MEM_BUFF12 EQU 0x402c0830 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF13 +CYREG_CRYPTO_MEM_BUFF13 EQU 0x402c0834 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF14 +CYREG_CRYPTO_MEM_BUFF14 EQU 0x402c0838 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF15 +CYREG_CRYPTO_MEM_BUFF15 EQU 0x402c083c + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF16 +CYREG_CRYPTO_MEM_BUFF16 EQU 0x402c0840 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF17 +CYREG_CRYPTO_MEM_BUFF17 EQU 0x402c0844 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF18 +CYREG_CRYPTO_MEM_BUFF18 EQU 0x402c0848 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF19 +CYREG_CRYPTO_MEM_BUFF19 EQU 0x402c084c + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF20 +CYREG_CRYPTO_MEM_BUFF20 EQU 0x402c0850 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF21 +CYREG_CRYPTO_MEM_BUFF21 EQU 0x402c0854 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF22 +CYREG_CRYPTO_MEM_BUFF22 EQU 0x402c0858 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF23 +CYREG_CRYPTO_MEM_BUFF23 EQU 0x402c085c + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF24 +CYREG_CRYPTO_MEM_BUFF24 EQU 0x402c0860 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF25 +CYREG_CRYPTO_MEM_BUFF25 EQU 0x402c0864 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF26 +CYREG_CRYPTO_MEM_BUFF26 EQU 0x402c0868 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF27 +CYREG_CRYPTO_MEM_BUFF27 EQU 0x402c086c + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF28 +CYREG_CRYPTO_MEM_BUFF28 EQU 0x402c0870 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF29 +CYREG_CRYPTO_MEM_BUFF29 EQU 0x402c0874 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF30 +CYREG_CRYPTO_MEM_BUFF30 EQU 0x402c0878 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF31 +CYREG_CRYPTO_MEM_BUFF31 EQU 0x402c087c + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF32 +CYREG_CRYPTO_MEM_BUFF32 EQU 0x402c0880 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF33 +CYREG_CRYPTO_MEM_BUFF33 EQU 0x402c0884 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF34 +CYREG_CRYPTO_MEM_BUFF34 EQU 0x402c0888 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF35 +CYREG_CRYPTO_MEM_BUFF35 EQU 0x402c088c + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF36 +CYREG_CRYPTO_MEM_BUFF36 EQU 0x402c0890 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF37 +CYREG_CRYPTO_MEM_BUFF37 EQU 0x402c0894 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF38 +CYREG_CRYPTO_MEM_BUFF38 EQU 0x402c0898 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF39 +CYREG_CRYPTO_MEM_BUFF39 EQU 0x402c089c + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF40 +CYREG_CRYPTO_MEM_BUFF40 EQU 0x402c08a0 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF41 +CYREG_CRYPTO_MEM_BUFF41 EQU 0x402c08a4 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF42 +CYREG_CRYPTO_MEM_BUFF42 EQU 0x402c08a8 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF43 +CYREG_CRYPTO_MEM_BUFF43 EQU 0x402c08ac + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF44 +CYREG_CRYPTO_MEM_BUFF44 EQU 0x402c08b0 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF45 +CYREG_CRYPTO_MEM_BUFF45 EQU 0x402c08b4 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF46 +CYREG_CRYPTO_MEM_BUFF46 EQU 0x402c08b8 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF47 +CYREG_CRYPTO_MEM_BUFF47 EQU 0x402c08bc + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF48 +CYREG_CRYPTO_MEM_BUFF48 EQU 0x402c08c0 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF49 +CYREG_CRYPTO_MEM_BUFF49 EQU 0x402c08c4 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF50 +CYREG_CRYPTO_MEM_BUFF50 EQU 0x402c08c8 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF51 +CYREG_CRYPTO_MEM_BUFF51 EQU 0x402c08cc + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF52 +CYREG_CRYPTO_MEM_BUFF52 EQU 0x402c08d0 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF53 +CYREG_CRYPTO_MEM_BUFF53 EQU 0x402c08d4 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF54 +CYREG_CRYPTO_MEM_BUFF54 EQU 0x402c08d8 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF55 +CYREG_CRYPTO_MEM_BUFF55 EQU 0x402c08dc + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF56 +CYREG_CRYPTO_MEM_BUFF56 EQU 0x402c08e0 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF57 +CYREG_CRYPTO_MEM_BUFF57 EQU 0x402c08e4 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF58 +CYREG_CRYPTO_MEM_BUFF58 EQU 0x402c08e8 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF59 +CYREG_CRYPTO_MEM_BUFF59 EQU 0x402c08ec + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF60 +CYREG_CRYPTO_MEM_BUFF60 EQU 0x402c08f0 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF61 +CYREG_CRYPTO_MEM_BUFF61 EQU 0x402c08f4 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF62 +CYREG_CRYPTO_MEM_BUFF62 EQU 0x402c08f8 + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_MEM_BUFF63 +CYREG_CRYPTO_MEM_BUFF63 EQU 0x402c08fc + ENDIF + IF :LNOT::DEF:CYREG_CRYPTO_PRIV_BUF +CYREG_CRYPTO_PRIV_BUF EQU 0x402cff00 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_BUF_PRIV_LIMIT__OFFSET +CYFLD_CRYPTO_BUF_PRIV_LIMIT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CRYPTO_BUF_PRIV_LIMIT__SIZE +CYFLD_CRYPTO_BUF_PRIV_LIMIT__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_BASE +CYDEV_CAN_BASE EQU 0x402e0000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_SIZE +CYDEV_CAN_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_CAN_INT_STATUS +CYREG_CAN_INT_STATUS EQU 0x402e0000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ARB_LOSS__OFFSET +CYFLD_CAN_ARB_LOSS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ARB_LOSS__SIZE +CYFLD_CAN_ARB_LOSS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_OVR_LOAD__OFFSET +CYFLD_CAN_OVR_LOAD__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_OVR_LOAD__SIZE +CYFLD_CAN_OVR_LOAD__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_BIT_ERR__OFFSET +CYFLD_CAN_BIT_ERR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_BIT_ERR__SIZE +CYFLD_CAN_BIT_ERR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_STUFF_ERR__OFFSET +CYFLD_CAN_STUFF_ERR__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_STUFF_ERR__SIZE +CYFLD_CAN_STUFF_ERR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ACK_ERR__OFFSET +CYFLD_CAN_ACK_ERR__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ACK_ERR__SIZE +CYFLD_CAN_ACK_ERR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_FORM_ERR__OFFSET +CYFLD_CAN_FORM_ERR__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_FORM_ERR__SIZE +CYFLD_CAN_FORM_ERR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CRC_ERR__OFFSET +CYFLD_CAN_CRC_ERR__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CRC_ERR__SIZE +CYFLD_CAN_CRC_ERR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_BUS_OFF__OFFSET +CYFLD_CAN_BUS_OFF__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_BUS_OFF__SIZE +CYFLD_CAN_BUS_OFF__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX_MSG_LOSS__OFFSET +CYFLD_CAN_RX_MSG_LOSS__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX_MSG_LOSS__SIZE +CYFLD_CAN_RX_MSG_LOSS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX_MSG__OFFSET +CYFLD_CAN_TX_MSG__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX_MSG__SIZE +CYFLD_CAN_TX_MSG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX_MSG__OFFSET +CYFLD_CAN_RX_MSG__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX_MSG__SIZE +CYFLD_CAN_RX_MSG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RTR_MSG__OFFSET +CYFLD_CAN_RTR_MSG__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RTR_MSG__SIZE +CYFLD_CAN_RTR_MSG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_STUCK_AT_0__OFFSET +CYFLD_CAN_STUCK_AT_0__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CAN_STUCK_AT_0__SIZE +CYFLD_CAN_STUCK_AT_0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SST_FAILURE__OFFSET +CYFLD_CAN_SST_FAILURE__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SST_FAILURE__SIZE +CYFLD_CAN_SST_FAILURE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CAN_INT_EBL +CYREG_CAN_INT_EBL EQU 0x402e0004 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_GLOBAL_INT_ENBL__OFFSET +CYFLD_CAN_GLOBAL_INT_ENBL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_GLOBAL_INT_ENBL__SIZE +CYFLD_CAN_GLOBAL_INT_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ARB_LOSS_ENBL__OFFSET +CYFLD_CAN_ARB_LOSS_ENBL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ARB_LOSS_ENBL__SIZE +CYFLD_CAN_ARB_LOSS_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_OVR_LOAD_ENBL__OFFSET +CYFLD_CAN_OVR_LOAD_ENBL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_OVR_LOAD_ENBL__SIZE +CYFLD_CAN_OVR_LOAD_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_BIT_ERR_ENBL__OFFSET +CYFLD_CAN_BIT_ERR_ENBL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_BIT_ERR_ENBL__SIZE +CYFLD_CAN_BIT_ERR_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_STUFF_ERR_ENBL__OFFSET +CYFLD_CAN_STUFF_ERR_ENBL__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_STUFF_ERR_ENBL__SIZE +CYFLD_CAN_STUFF_ERR_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ACK_ERR_ENBL__OFFSET +CYFLD_CAN_ACK_ERR_ENBL__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ACK_ERR_ENBL__SIZE +CYFLD_CAN_ACK_ERR_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_FORM_ERR_ENBL__OFFSET +CYFLD_CAN_FORM_ERR_ENBL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_FORM_ERR_ENBL__SIZE +CYFLD_CAN_FORM_ERR_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CRC_ERR_ENBL__OFFSET +CYFLD_CAN_CRC_ERR_ENBL__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CRC_ERR_ENBL__SIZE +CYFLD_CAN_CRC_ERR_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_BUS_OFF_ENBL__OFFSET +CYFLD_CAN_BUS_OFF_ENBL__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_BUS_OFF_ENBL__SIZE +CYFLD_CAN_BUS_OFF_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX_MSG_ENBL__OFFSET +CYFLD_CAN_TX_MSG_ENBL__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX_MSG_ENBL__SIZE +CYFLD_CAN_TX_MSG_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX_MSG_ENBl__OFFSET +CYFLD_CAN_RX_MSG_ENBl__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX_MSG_ENBl__SIZE +CYFLD_CAN_RX_MSG_ENBl__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RTR_MSG_ENBL__OFFSET +CYFLD_CAN_RTR_MSG_ENBL__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RTR_MSG_ENBL__SIZE +CYFLD_CAN_RTR_MSG_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_STUCK_AT_0_ENBL__OFFSET +CYFLD_CAN_STUCK_AT_0_ENBL__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CAN_STUCK_AT_0_ENBL__SIZE +CYFLD_CAN_STUCK_AT_0_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SST_FAILURE_ENBL__OFFSET +CYFLD_CAN_SST_FAILURE_ENBL__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SST_FAILURE_ENBL__SIZE +CYFLD_CAN_SST_FAILURE_ENBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CAN_BUFFER_STATUS +CYREG_CAN_BUFFER_STATUS EQU 0x402e0008 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX0_MSG_AV__OFFSET +CYFLD_CAN_RX0_MSG_AV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX0_MSG_AV__SIZE +CYFLD_CAN_RX0_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX1_MSG_AV__OFFSET +CYFLD_CAN_RX1_MSG_AV__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX1_MSG_AV__SIZE +CYFLD_CAN_RX1_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX2_MSG_AV__OFFSET +CYFLD_CAN_RX2_MSG_AV__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX2_MSG_AV__SIZE +CYFLD_CAN_RX2_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX3_MSG_AV__OFFSET +CYFLD_CAN_RX3_MSG_AV__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX3_MSG_AV__SIZE +CYFLD_CAN_RX3_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX4_MSG_AV__OFFSET +CYFLD_CAN_RX4_MSG_AV__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX4_MSG_AV__SIZE +CYFLD_CAN_RX4_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX5_MSG_AV__OFFSET +CYFLD_CAN_RX5_MSG_AV__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX5_MSG_AV__SIZE +CYFLD_CAN_RX5_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX6_MSG_AV__OFFSET +CYFLD_CAN_RX6_MSG_AV__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX6_MSG_AV__SIZE +CYFLD_CAN_RX6_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX7_MSG_AV__OFFSET +CYFLD_CAN_RX7_MSG_AV__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX7_MSG_AV__SIZE +CYFLD_CAN_RX7_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX8_MSG_AV__OFFSET +CYFLD_CAN_RX8_MSG_AV__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX8_MSG_AV__SIZE +CYFLD_CAN_RX8_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX9_MSG_AV__OFFSET +CYFLD_CAN_RX9_MSG_AV__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX9_MSG_AV__SIZE +CYFLD_CAN_RX9_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX10_MSG_AV__OFFSET +CYFLD_CAN_RX10_MSG_AV__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX10_MSG_AV__SIZE +CYFLD_CAN_RX10_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX11_MSG_AV__OFFSET +CYFLD_CAN_RX11_MSG_AV__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX11_MSG_AV__SIZE +CYFLD_CAN_RX11_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX12_MSG_AV__OFFSET +CYFLD_CAN_RX12_MSG_AV__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX12_MSG_AV__SIZE +CYFLD_CAN_RX12_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX13_MSG_AV__OFFSET +CYFLD_CAN_RX13_MSG_AV__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX13_MSG_AV__SIZE +CYFLD_CAN_RX13_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX14_MSG_AV__OFFSET +CYFLD_CAN_RX14_MSG_AV__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX14_MSG_AV__SIZE +CYFLD_CAN_RX14_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX15_MSG_AV__OFFSET +CYFLD_CAN_RX15_MSG_AV__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX15_MSG_AV__SIZE +CYFLD_CAN_RX15_MSG_AV__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX0_REQ_PEND__OFFSET +CYFLD_CAN_TX0_REQ_PEND__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX0_REQ_PEND__SIZE +CYFLD_CAN_TX0_REQ_PEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX1_REQ_PEND__OFFSET +CYFLD_CAN_TX1_REQ_PEND__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX1_REQ_PEND__SIZE +CYFLD_CAN_TX1_REQ_PEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX2_REQ_PEND__OFFSET +CYFLD_CAN_TX2_REQ_PEND__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX2_REQ_PEND__SIZE +CYFLD_CAN_TX2_REQ_PEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX3_REQ_PEND__OFFSET +CYFLD_CAN_TX3_REQ_PEND__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX3_REQ_PEND__SIZE +CYFLD_CAN_TX3_REQ_PEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX4_REQ_PEND__OFFSET +CYFLD_CAN_TX4_REQ_PEND__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX4_REQ_PEND__SIZE +CYFLD_CAN_TX4_REQ_PEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX5_REQ_PEND__OFFSET +CYFLD_CAN_TX5_REQ_PEND__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX5_REQ_PEND__SIZE +CYFLD_CAN_TX5_REQ_PEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX6_REQ_PEND__OFFSET +CYFLD_CAN_TX6_REQ_PEND__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX6_REQ_PEND__SIZE +CYFLD_CAN_TX6_REQ_PEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX7_REQ_PEND__OFFSET +CYFLD_CAN_TX7_REQ_PEND__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX7_REQ_PEND__SIZE +CYFLD_CAN_TX7_REQ_PEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CAN_ERROR_STATUS +CYREG_CAN_ERROR_STATUS EQU 0x402e000c + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX_ERR_CNT__OFFSET +CYFLD_CAN_TX_ERR_CNT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX_ERR_CNT__SIZE +CYFLD_CAN_TX_ERR_CNT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX_ERR_CNT__OFFSET +CYFLD_CAN_RX_ERR_CNT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX_ERR_CNT__SIZE +CYFLD_CAN_RX_ERR_CNT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ERROR_STATE__OFFSET +CYFLD_CAN_ERROR_STATE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ERROR_STATE__SIZE +CYFLD_CAN_ERROR_STATE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TXGTE96__OFFSET +CYFLD_CAN_TXGTE96__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TXGTE96__SIZE +CYFLD_CAN_TXGTE96__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RXGTE96__OFFSET +CYFLD_CAN_RXGTE96__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RXGTE96__SIZE +CYFLD_CAN_RXGTE96__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CAN_COMMAND +CYREG_CAN_COMMAND EQU 0x402e0010 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RUN__OFFSET +CYFLD_CAN_RUN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RUN__SIZE +CYFLD_CAN_RUN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_LISTEN__OFFSET +CYFLD_CAN_LISTEN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_LISTEN__SIZE +CYFLD_CAN_LISTEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_LOOPBACK_TEST__OFFSET +CYFLD_CAN_LOOPBACK_TEST__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_LOOPBACK_TEST__SIZE +CYFLD_CAN_LOOPBACK_TEST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SRAM_TEST__OFFSET +CYFLD_CAN_SRAM_TEST__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SRAM_TEST__SIZE +CYFLD_CAN_SRAM_TEST__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_IP_REV_NUMBER__OFFSET +CYFLD_CAN_IP_REV_NUMBER__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_IP_REV_NUMBER__SIZE +CYFLD_CAN_IP_REV_NUMBER__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_IP_MINOR_VERSION__OFFSET +CYFLD_CAN_IP_MINOR_VERSION__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_IP_MINOR_VERSION__SIZE +CYFLD_CAN_IP_MINOR_VERSION__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_IP_MAJOR_VERSION__OFFSET +CYFLD_CAN_IP_MAJOR_VERSION__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CAN_IP_MAJOR_VERSION__SIZE +CYFLD_CAN_IP_MAJOR_VERSION__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CONFIG +CYREG_CAN_CONFIG EQU 0x402e0014 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_EDGE_MODE__OFFSET +CYFLD_CAN_EDGE_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_EDGE_MODE__SIZE +CYFLD_CAN_EDGE_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SAMPLING_MODE__OFFSET +CYFLD_CAN_SAMPLING_MODE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SAMPLING_MODE__SIZE +CYFLD_CAN_SAMPLING_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CFG_SJW__OFFSET +CYFLD_CAN_CFG_SJW__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CFG_SJW__SIZE +CYFLD_CAN_CFG_SJW__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_AUTO_RESTART__OFFSET +CYFLD_CAN_AUTO_RESTART__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_AUTO_RESTART__SIZE +CYFLD_CAN_AUTO_RESTART__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CFG_TSEG2__OFFSET +CYFLD_CAN_CFG_TSEG2__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CFG_TSEG2__SIZE +CYFLD_CAN_CFG_TSEG2__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CFG_TSEG1__OFFSET +CYFLD_CAN_CFG_TSEG1__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CFG_TSEG1__SIZE +CYFLD_CAN_CFG_TSEG1__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CFG_ARBITER__OFFSET +CYFLD_CAN_CFG_ARBITER__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CFG_ARBITER__SIZE +CYFLD_CAN_CFG_ARBITER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SWAP_ENDIAN__OFFSET +CYFLD_CAN_SWAP_ENDIAN__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SWAP_ENDIAN__SIZE +CYFLD_CAN_SWAP_ENDIAN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ECR_MODE__OFFSET +CYFLD_CAN_ECR_MODE__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ECR_MODE__SIZE +CYFLD_CAN_ECR_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CFG_BITRATE__OFFSET +CYFLD_CAN_CFG_BITRATE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CFG_BITRATE__SIZE +CYFLD_CAN_CFG_BITRATE__SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_CAN_ECR +CYREG_CAN_ECR EQU 0x402e0018 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ECR_STATUS__OFFSET +CYFLD_CAN_ECR_STATUS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ECR_STATUS__SIZE +CYFLD_CAN_ECR_STATUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ERROR_TYPE__OFFSET +CYFLD_CAN_ERROR_TYPE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_ERROR_TYPE__SIZE +CYFLD_CAN_ERROR_TYPE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX_MODE__OFFSET +CYFLD_CAN_RX_MODE__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_RX_MODE__SIZE +CYFLD_CAN_RX_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX_MODE__OFFSET +CYFLD_CAN_TX_MODE__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TX_MODE__SIZE +CYFLD_CAN_TX_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_BIT__OFFSET +CYFLD_CAN_BIT__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_BIT__SIZE +CYFLD_CAN_BIT__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_Field__OFFSET +CYFLD_CAN_Field__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CAN_Field__SIZE +CYFLD_CAN_Field__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX0_BASE +CYDEV_CAN_CAN_TX0_BASE EQU 0x402e0020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX0_SIZE +CYDEV_CAN_CAN_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX0_CONTROL +CYREG_CAN_CAN_TX0_CONTROL EQU 0x402e0020 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_TX_REQ__OFFSET +CYFLD_CAN_CAN_TX_TX_REQ__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_TX_REQ__SIZE +CYFLD_CAN_CAN_TX_TX_REQ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_TX_ABORT__OFFSET +CYFLD_CAN_CAN_TX_TX_ABORT__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_TX_ABORT__SIZE +CYFLD_CAN_CAN_TX_TX_ABORT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_TX_INT_EBL__OFFSET +CYFLD_CAN_CAN_TX_TX_INT_EBL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_TX_INT_EBL__SIZE +CYFLD_CAN_CAN_TX_TX_INT_EBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_WPNL__OFFSET +CYFLD_CAN_CAN_TX_WPNL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_WPNL__SIZE +CYFLD_CAN_CAN_TX_WPNL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_DLC__OFFSET +CYFLD_CAN_CAN_TX_DLC__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_DLC__SIZE +CYFLD_CAN_CAN_TX_DLC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_IDE__OFFSET +CYFLD_CAN_CAN_TX_IDE__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_IDE__SIZE +CYFLD_CAN_CAN_TX_IDE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_RTR__OFFSET +CYFLD_CAN_CAN_TX_RTR__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_RTR__SIZE +CYFLD_CAN_CAN_TX_RTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_WPNH__OFFSET +CYFLD_CAN_CAN_TX_WPNH__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_WPNH__SIZE +CYFLD_CAN_CAN_TX_WPNH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX0_ID +CYREG_CAN_CAN_TX0_ID EQU 0x402e0024 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_ID__OFFSET +CYFLD_CAN_CAN_TX_ID__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_ID__SIZE +CYFLD_CAN_CAN_TX_ID__SIZE EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX0_DATA_HIGH +CYREG_CAN_CAN_TX0_DATA_HIGH EQU 0x402e0028 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_DATA__OFFSET +CYFLD_CAN_CAN_TX_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_TX_DATA__SIZE +CYFLD_CAN_CAN_TX_DATA__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX0_DATA_LOW +CYREG_CAN_CAN_TX0_DATA_LOW EQU 0x402e002c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX1_BASE +CYDEV_CAN_CAN_TX1_BASE EQU 0x402e0030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX1_SIZE +CYDEV_CAN_CAN_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX1_CONTROL +CYREG_CAN_CAN_TX1_CONTROL EQU 0x402e0030 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX1_ID +CYREG_CAN_CAN_TX1_ID EQU 0x402e0034 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX1_DATA_HIGH +CYREG_CAN_CAN_TX1_DATA_HIGH EQU 0x402e0038 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX1_DATA_LOW +CYREG_CAN_CAN_TX1_DATA_LOW EQU 0x402e003c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX2_BASE +CYDEV_CAN_CAN_TX2_BASE EQU 0x402e0040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX2_SIZE +CYDEV_CAN_CAN_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX2_CONTROL +CYREG_CAN_CAN_TX2_CONTROL EQU 0x402e0040 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX2_ID +CYREG_CAN_CAN_TX2_ID EQU 0x402e0044 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX2_DATA_HIGH +CYREG_CAN_CAN_TX2_DATA_HIGH EQU 0x402e0048 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX2_DATA_LOW +CYREG_CAN_CAN_TX2_DATA_LOW EQU 0x402e004c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX3_BASE +CYDEV_CAN_CAN_TX3_BASE EQU 0x402e0050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX3_SIZE +CYDEV_CAN_CAN_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX3_CONTROL +CYREG_CAN_CAN_TX3_CONTROL EQU 0x402e0050 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX3_ID +CYREG_CAN_CAN_TX3_ID EQU 0x402e0054 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX3_DATA_HIGH +CYREG_CAN_CAN_TX3_DATA_HIGH EQU 0x402e0058 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX3_DATA_LOW +CYREG_CAN_CAN_TX3_DATA_LOW EQU 0x402e005c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX4_BASE +CYDEV_CAN_CAN_TX4_BASE EQU 0x402e0060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX4_SIZE +CYDEV_CAN_CAN_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX4_CONTROL +CYREG_CAN_CAN_TX4_CONTROL EQU 0x402e0060 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX4_ID +CYREG_CAN_CAN_TX4_ID EQU 0x402e0064 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX4_DATA_HIGH +CYREG_CAN_CAN_TX4_DATA_HIGH EQU 0x402e0068 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX4_DATA_LOW +CYREG_CAN_CAN_TX4_DATA_LOW EQU 0x402e006c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX5_BASE +CYDEV_CAN_CAN_TX5_BASE EQU 0x402e0070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX5_SIZE +CYDEV_CAN_CAN_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX5_CONTROL +CYREG_CAN_CAN_TX5_CONTROL EQU 0x402e0070 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX5_ID +CYREG_CAN_CAN_TX5_ID EQU 0x402e0074 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX5_DATA_HIGH +CYREG_CAN_CAN_TX5_DATA_HIGH EQU 0x402e0078 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX5_DATA_LOW +CYREG_CAN_CAN_TX5_DATA_LOW EQU 0x402e007c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX6_BASE +CYDEV_CAN_CAN_TX6_BASE EQU 0x402e0080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX6_SIZE +CYDEV_CAN_CAN_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX6_CONTROL +CYREG_CAN_CAN_TX6_CONTROL EQU 0x402e0080 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX6_ID +CYREG_CAN_CAN_TX6_ID EQU 0x402e0084 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX6_DATA_HIGH +CYREG_CAN_CAN_TX6_DATA_HIGH EQU 0x402e0088 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX6_DATA_LOW +CYREG_CAN_CAN_TX6_DATA_LOW EQU 0x402e008c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX7_BASE +CYDEV_CAN_CAN_TX7_BASE EQU 0x402e0090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_TX7_SIZE +CYDEV_CAN_CAN_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX7_CONTROL +CYREG_CAN_CAN_TX7_CONTROL EQU 0x402e0090 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX7_ID +CYREG_CAN_CAN_TX7_ID EQU 0x402e0094 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX7_DATA_HIGH +CYREG_CAN_CAN_TX7_DATA_HIGH EQU 0x402e0098 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_TX7_DATA_LOW +CYREG_CAN_CAN_TX7_DATA_LOW EQU 0x402e009c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX0_BASE +CYDEV_CAN_CAN_RX0_BASE EQU 0x402e00a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX0_SIZE +CYDEV_CAN_CAN_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX0_CONTROL +CYREG_CAN_CAN_RX0_CONTROL EQU 0x402e00a0 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__OFFSET +CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__SIZE +CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__OFFSET +CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__SIZE +CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RTR_ABORT__OFFSET +CYFLD_CAN_CAN_RX_RTR_ABORT__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RTR_ABORT__SIZE +CYFLD_CAN_CAN_RX_RTR_ABORT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_BUFFER_EN__OFFSET +CYFLD_CAN_CAN_RX_BUFFER_EN__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_BUFFER_EN__SIZE +CYFLD_CAN_CAN_RX_BUFFER_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RTR_REPLY__OFFSET +CYFLD_CAN_CAN_RX_RTR_REPLY__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RTR_REPLY__SIZE +CYFLD_CAN_CAN_RX_RTR_REPLY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RX_INT_EBL__OFFSET +CYFLD_CAN_CAN_RX_RX_INT_EBL__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RX_INT_EBL__SIZE +CYFLD_CAN_CAN_RX_RX_INT_EBL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_LINK_FLAG__OFFSET +CYFLD_CAN_CAN_RX_LINK_FLAG__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_LINK_FLAG__SIZE +CYFLD_CAN_CAN_RX_LINK_FLAG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_WPNL__OFFSET +CYFLD_CAN_CAN_RX_WPNL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_WPNL__SIZE +CYFLD_CAN_CAN_RX_WPNL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_DLC__OFFSET +CYFLD_CAN_CAN_RX_DLC__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_DLC__SIZE +CYFLD_CAN_CAN_RX_DLC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_IDE_FMT__OFFSET +CYFLD_CAN_CAN_RX_IDE_FMT__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_IDE_FMT__SIZE +CYFLD_CAN_CAN_RX_IDE_FMT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RTR_MSG__OFFSET +CYFLD_CAN_CAN_RX_RTR_MSG__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RTR_MSG__SIZE +CYFLD_CAN_CAN_RX_RTR_MSG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_WPNH__OFFSET +CYFLD_CAN_CAN_RX_WPNH__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_WPNH__SIZE +CYFLD_CAN_CAN_RX_WPNH__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX0_ID +CYREG_CAN_CAN_RX0_ID EQU 0x402e00a4 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_ID__OFFSET +CYFLD_CAN_CAN_RX_ID__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_ID__SIZE +CYFLD_CAN_CAN_RX_ID__SIZE EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX0_DATA_HIGH +CYREG_CAN_CAN_RX0_DATA_HIGH EQU 0x402e00a8 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_DATA__OFFSET +CYFLD_CAN_CAN_RX_DATA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_DATA__SIZE +CYFLD_CAN_CAN_RX_DATA__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX0_DATA_LOW +CYREG_CAN_CAN_RX0_DATA_LOW EQU 0x402e00ac + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX0_AMR +CYREG_CAN_CAN_RX0_AMR EQU 0x402e00b0 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RTR__OFFSET +CYFLD_CAN_CAN_RX_RTR__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_RTR__SIZE +CYFLD_CAN_CAN_RX_RTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_IDE__OFFSET +CYFLD_CAN_CAN_RX_IDE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_IDE__SIZE +CYFLD_CAN_CAN_RX_IDE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX0_ACR +CYREG_CAN_CAN_RX0_ACR EQU 0x402e00b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX0_AMR_DATA +CYREG_CAN_CAN_RX0_AMR_DATA EQU 0x402e00b8 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_DATAL__OFFSET +CYFLD_CAN_CAN_RX_DATAL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_CAN_RX_DATAL__SIZE +CYFLD_CAN_CAN_RX_DATAL__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX0_ACR_DATA +CYREG_CAN_CAN_RX0_ACR_DATA EQU 0x402e00bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX1_BASE +CYDEV_CAN_CAN_RX1_BASE EQU 0x402e00c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX1_SIZE +CYDEV_CAN_CAN_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX1_CONTROL +CYREG_CAN_CAN_RX1_CONTROL EQU 0x402e00c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX1_ID +CYREG_CAN_CAN_RX1_ID EQU 0x402e00c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX1_DATA_HIGH +CYREG_CAN_CAN_RX1_DATA_HIGH EQU 0x402e00c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX1_DATA_LOW +CYREG_CAN_CAN_RX1_DATA_LOW EQU 0x402e00cc + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX1_AMR +CYREG_CAN_CAN_RX1_AMR EQU 0x402e00d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX1_ACR +CYREG_CAN_CAN_RX1_ACR EQU 0x402e00d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX1_AMR_DATA +CYREG_CAN_CAN_RX1_AMR_DATA EQU 0x402e00d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX1_ACR_DATA +CYREG_CAN_CAN_RX1_ACR_DATA EQU 0x402e00dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX2_BASE +CYDEV_CAN_CAN_RX2_BASE EQU 0x402e00e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX2_SIZE +CYDEV_CAN_CAN_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX2_CONTROL +CYREG_CAN_CAN_RX2_CONTROL EQU 0x402e00e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX2_ID +CYREG_CAN_CAN_RX2_ID EQU 0x402e00e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX2_DATA_HIGH +CYREG_CAN_CAN_RX2_DATA_HIGH EQU 0x402e00e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX2_DATA_LOW +CYREG_CAN_CAN_RX2_DATA_LOW EQU 0x402e00ec + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX2_AMR +CYREG_CAN_CAN_RX2_AMR EQU 0x402e00f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX2_ACR +CYREG_CAN_CAN_RX2_ACR EQU 0x402e00f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX2_AMR_DATA +CYREG_CAN_CAN_RX2_AMR_DATA EQU 0x402e00f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX2_ACR_DATA +CYREG_CAN_CAN_RX2_ACR_DATA EQU 0x402e00fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX3_BASE +CYDEV_CAN_CAN_RX3_BASE EQU 0x402e0100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX3_SIZE +CYDEV_CAN_CAN_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX3_CONTROL +CYREG_CAN_CAN_RX3_CONTROL EQU 0x402e0100 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX3_ID +CYREG_CAN_CAN_RX3_ID EQU 0x402e0104 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX3_DATA_HIGH +CYREG_CAN_CAN_RX3_DATA_HIGH EQU 0x402e0108 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX3_DATA_LOW +CYREG_CAN_CAN_RX3_DATA_LOW EQU 0x402e010c + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX3_AMR +CYREG_CAN_CAN_RX3_AMR EQU 0x402e0110 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX3_ACR +CYREG_CAN_CAN_RX3_ACR EQU 0x402e0114 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX3_AMR_DATA +CYREG_CAN_CAN_RX3_AMR_DATA EQU 0x402e0118 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX3_ACR_DATA +CYREG_CAN_CAN_RX3_ACR_DATA EQU 0x402e011c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX4_BASE +CYDEV_CAN_CAN_RX4_BASE EQU 0x402e0120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX4_SIZE +CYDEV_CAN_CAN_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX4_CONTROL +CYREG_CAN_CAN_RX4_CONTROL EQU 0x402e0120 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX4_ID +CYREG_CAN_CAN_RX4_ID EQU 0x402e0124 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX4_DATA_HIGH +CYREG_CAN_CAN_RX4_DATA_HIGH EQU 0x402e0128 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX4_DATA_LOW +CYREG_CAN_CAN_RX4_DATA_LOW EQU 0x402e012c + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX4_AMR +CYREG_CAN_CAN_RX4_AMR EQU 0x402e0130 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX4_ACR +CYREG_CAN_CAN_RX4_ACR EQU 0x402e0134 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX4_AMR_DATA +CYREG_CAN_CAN_RX4_AMR_DATA EQU 0x402e0138 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX4_ACR_DATA +CYREG_CAN_CAN_RX4_ACR_DATA EQU 0x402e013c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX5_BASE +CYDEV_CAN_CAN_RX5_BASE EQU 0x402e0140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX5_SIZE +CYDEV_CAN_CAN_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX5_CONTROL +CYREG_CAN_CAN_RX5_CONTROL EQU 0x402e0140 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX5_ID +CYREG_CAN_CAN_RX5_ID EQU 0x402e0144 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX5_DATA_HIGH +CYREG_CAN_CAN_RX5_DATA_HIGH EQU 0x402e0148 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX5_DATA_LOW +CYREG_CAN_CAN_RX5_DATA_LOW EQU 0x402e014c + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX5_AMR +CYREG_CAN_CAN_RX5_AMR EQU 0x402e0150 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX5_ACR +CYREG_CAN_CAN_RX5_ACR EQU 0x402e0154 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX5_AMR_DATA +CYREG_CAN_CAN_RX5_AMR_DATA EQU 0x402e0158 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX5_ACR_DATA +CYREG_CAN_CAN_RX5_ACR_DATA EQU 0x402e015c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX6_BASE +CYDEV_CAN_CAN_RX6_BASE EQU 0x402e0160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX6_SIZE +CYDEV_CAN_CAN_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX6_CONTROL +CYREG_CAN_CAN_RX6_CONTROL EQU 0x402e0160 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX6_ID +CYREG_CAN_CAN_RX6_ID EQU 0x402e0164 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX6_DATA_HIGH +CYREG_CAN_CAN_RX6_DATA_HIGH EQU 0x402e0168 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX6_DATA_LOW +CYREG_CAN_CAN_RX6_DATA_LOW EQU 0x402e016c + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX6_AMR +CYREG_CAN_CAN_RX6_AMR EQU 0x402e0170 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX6_ACR +CYREG_CAN_CAN_RX6_ACR EQU 0x402e0174 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX6_AMR_DATA +CYREG_CAN_CAN_RX6_AMR_DATA EQU 0x402e0178 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX6_ACR_DATA +CYREG_CAN_CAN_RX6_ACR_DATA EQU 0x402e017c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX7_BASE +CYDEV_CAN_CAN_RX7_BASE EQU 0x402e0180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX7_SIZE +CYDEV_CAN_CAN_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX7_CONTROL +CYREG_CAN_CAN_RX7_CONTROL EQU 0x402e0180 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX7_ID +CYREG_CAN_CAN_RX7_ID EQU 0x402e0184 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX7_DATA_HIGH +CYREG_CAN_CAN_RX7_DATA_HIGH EQU 0x402e0188 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX7_DATA_LOW +CYREG_CAN_CAN_RX7_DATA_LOW EQU 0x402e018c + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX7_AMR +CYREG_CAN_CAN_RX7_AMR EQU 0x402e0190 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX7_ACR +CYREG_CAN_CAN_RX7_ACR EQU 0x402e0194 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX7_AMR_DATA +CYREG_CAN_CAN_RX7_AMR_DATA EQU 0x402e0198 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX7_ACR_DATA +CYREG_CAN_CAN_RX7_ACR_DATA EQU 0x402e019c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX8_BASE +CYDEV_CAN_CAN_RX8_BASE EQU 0x402e01a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX8_SIZE +CYDEV_CAN_CAN_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX8_CONTROL +CYREG_CAN_CAN_RX8_CONTROL EQU 0x402e01a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX8_ID +CYREG_CAN_CAN_RX8_ID EQU 0x402e01a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX8_DATA_HIGH +CYREG_CAN_CAN_RX8_DATA_HIGH EQU 0x402e01a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX8_DATA_LOW +CYREG_CAN_CAN_RX8_DATA_LOW EQU 0x402e01ac + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX8_AMR +CYREG_CAN_CAN_RX8_AMR EQU 0x402e01b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX8_ACR +CYREG_CAN_CAN_RX8_ACR EQU 0x402e01b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX8_AMR_DATA +CYREG_CAN_CAN_RX8_AMR_DATA EQU 0x402e01b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX8_ACR_DATA +CYREG_CAN_CAN_RX8_ACR_DATA EQU 0x402e01bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX9_BASE +CYDEV_CAN_CAN_RX9_BASE EQU 0x402e01c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX9_SIZE +CYDEV_CAN_CAN_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX9_CONTROL +CYREG_CAN_CAN_RX9_CONTROL EQU 0x402e01c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX9_ID +CYREG_CAN_CAN_RX9_ID EQU 0x402e01c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX9_DATA_HIGH +CYREG_CAN_CAN_RX9_DATA_HIGH EQU 0x402e01c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX9_DATA_LOW +CYREG_CAN_CAN_RX9_DATA_LOW EQU 0x402e01cc + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX9_AMR +CYREG_CAN_CAN_RX9_AMR EQU 0x402e01d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX9_ACR +CYREG_CAN_CAN_RX9_ACR EQU 0x402e01d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX9_AMR_DATA +CYREG_CAN_CAN_RX9_AMR_DATA EQU 0x402e01d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX9_ACR_DATA +CYREG_CAN_CAN_RX9_ACR_DATA EQU 0x402e01dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX10_BASE +CYDEV_CAN_CAN_RX10_BASE EQU 0x402e01e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX10_SIZE +CYDEV_CAN_CAN_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX10_CONTROL +CYREG_CAN_CAN_RX10_CONTROL EQU 0x402e01e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX10_ID +CYREG_CAN_CAN_RX10_ID EQU 0x402e01e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX10_DATA_HIGH +CYREG_CAN_CAN_RX10_DATA_HIGH EQU 0x402e01e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX10_DATA_LOW +CYREG_CAN_CAN_RX10_DATA_LOW EQU 0x402e01ec + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX10_AMR +CYREG_CAN_CAN_RX10_AMR EQU 0x402e01f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX10_ACR +CYREG_CAN_CAN_RX10_ACR EQU 0x402e01f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX10_AMR_DATA +CYREG_CAN_CAN_RX10_AMR_DATA EQU 0x402e01f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX10_ACR_DATA +CYREG_CAN_CAN_RX10_ACR_DATA EQU 0x402e01fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX11_BASE +CYDEV_CAN_CAN_RX11_BASE EQU 0x402e0200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX11_SIZE +CYDEV_CAN_CAN_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX11_CONTROL +CYREG_CAN_CAN_RX11_CONTROL EQU 0x402e0200 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX11_ID +CYREG_CAN_CAN_RX11_ID EQU 0x402e0204 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX11_DATA_HIGH +CYREG_CAN_CAN_RX11_DATA_HIGH EQU 0x402e0208 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX11_DATA_LOW +CYREG_CAN_CAN_RX11_DATA_LOW EQU 0x402e020c + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX11_AMR +CYREG_CAN_CAN_RX11_AMR EQU 0x402e0210 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX11_ACR +CYREG_CAN_CAN_RX11_ACR EQU 0x402e0214 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX11_AMR_DATA +CYREG_CAN_CAN_RX11_AMR_DATA EQU 0x402e0218 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX11_ACR_DATA +CYREG_CAN_CAN_RX11_ACR_DATA EQU 0x402e021c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX12_BASE +CYDEV_CAN_CAN_RX12_BASE EQU 0x402e0220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX12_SIZE +CYDEV_CAN_CAN_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX12_CONTROL +CYREG_CAN_CAN_RX12_CONTROL EQU 0x402e0220 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX12_ID +CYREG_CAN_CAN_RX12_ID EQU 0x402e0224 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX12_DATA_HIGH +CYREG_CAN_CAN_RX12_DATA_HIGH EQU 0x402e0228 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX12_DATA_LOW +CYREG_CAN_CAN_RX12_DATA_LOW EQU 0x402e022c + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX12_AMR +CYREG_CAN_CAN_RX12_AMR EQU 0x402e0230 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX12_ACR +CYREG_CAN_CAN_RX12_ACR EQU 0x402e0234 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX12_AMR_DATA +CYREG_CAN_CAN_RX12_AMR_DATA EQU 0x402e0238 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX12_ACR_DATA +CYREG_CAN_CAN_RX12_ACR_DATA EQU 0x402e023c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX13_BASE +CYDEV_CAN_CAN_RX13_BASE EQU 0x402e0240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX13_SIZE +CYDEV_CAN_CAN_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX13_CONTROL +CYREG_CAN_CAN_RX13_CONTROL EQU 0x402e0240 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX13_ID +CYREG_CAN_CAN_RX13_ID EQU 0x402e0244 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX13_DATA_HIGH +CYREG_CAN_CAN_RX13_DATA_HIGH EQU 0x402e0248 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX13_DATA_LOW +CYREG_CAN_CAN_RX13_DATA_LOW EQU 0x402e024c + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX13_AMR +CYREG_CAN_CAN_RX13_AMR EQU 0x402e0250 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX13_ACR +CYREG_CAN_CAN_RX13_ACR EQU 0x402e0254 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX13_AMR_DATA +CYREG_CAN_CAN_RX13_AMR_DATA EQU 0x402e0258 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX13_ACR_DATA +CYREG_CAN_CAN_RX13_ACR_DATA EQU 0x402e025c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX14_BASE +CYDEV_CAN_CAN_RX14_BASE EQU 0x402e0260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX14_SIZE +CYDEV_CAN_CAN_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX14_CONTROL +CYREG_CAN_CAN_RX14_CONTROL EQU 0x402e0260 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX14_ID +CYREG_CAN_CAN_RX14_ID EQU 0x402e0264 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX14_DATA_HIGH +CYREG_CAN_CAN_RX14_DATA_HIGH EQU 0x402e0268 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX14_DATA_LOW +CYREG_CAN_CAN_RX14_DATA_LOW EQU 0x402e026c + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX14_AMR +CYREG_CAN_CAN_RX14_AMR EQU 0x402e0270 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX14_ACR +CYREG_CAN_CAN_RX14_ACR EQU 0x402e0274 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX14_AMR_DATA +CYREG_CAN_CAN_RX14_AMR_DATA EQU 0x402e0278 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX14_ACR_DATA +CYREG_CAN_CAN_RX14_ACR_DATA EQU 0x402e027c + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX15_BASE +CYDEV_CAN_CAN_RX15_BASE EQU 0x402e0280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN_CAN_RX15_SIZE +CYDEV_CAN_CAN_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX15_CONTROL +CYREG_CAN_CAN_RX15_CONTROL EQU 0x402e0280 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX15_ID +CYREG_CAN_CAN_RX15_ID EQU 0x402e0284 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX15_DATA_HIGH +CYREG_CAN_CAN_RX15_DATA_HIGH EQU 0x402e0288 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX15_DATA_LOW +CYREG_CAN_CAN_RX15_DATA_LOW EQU 0x402e028c + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX15_AMR +CYREG_CAN_CAN_RX15_AMR EQU 0x402e0290 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX15_ACR +CYREG_CAN_CAN_RX15_ACR EQU 0x402e0294 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX15_AMR_DATA +CYREG_CAN_CAN_RX15_AMR_DATA EQU 0x402e0298 + ENDIF + IF :LNOT::DEF:CYREG_CAN_CAN_RX15_ACR_DATA +CYREG_CAN_CAN_RX15_ACR_DATA EQU 0x402e029c + ENDIF + IF :LNOT::DEF:CYREG_CAN_CNTL +CYREG_CAN_CNTL EQU 0x402e0400 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TT_ENABLE__OFFSET +CYFLD_CAN_TT_ENABLE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TT_ENABLE__SIZE +CYFLD_CAN_TT_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_IP_ENABLE__OFFSET +CYFLD_CAN_IP_ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CAN_IP_ENABLE__SIZE +CYFLD_CAN_IP_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CAN_TTCAN_COUNTER +CYREG_CAN_TTCAN_COUNTER EQU 0x402e0404 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_LOCAL_TIME__OFFSET +CYFLD_CAN_LOCAL_TIME__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_LOCAL_TIME__SIZE +CYFLD_CAN_LOCAL_TIME__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_TTCAN_COMPARE +CYREG_CAN_TTCAN_COMPARE EQU 0x402e0408 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TIME_MARK__OFFSET +CYFLD_CAN_TIME_MARK__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TIME_MARK__SIZE +CYFLD_CAN_TIME_MARK__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_TTCAN_CAPTURE +CYREG_CAN_TTCAN_CAPTURE EQU 0x402e040c + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SYNC_MARK__OFFSET +CYFLD_CAN_SYNC_MARK__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_SYNC_MARK__SIZE +CYFLD_CAN_SYNC_MARK__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN_TTCAN_TIMING +CYREG_CAN_TTCAN_TIMING EQU 0x402e0410 + ENDIF + IF :LNOT::DEF:CYREG_CAN_INTR_CAN +CYREG_CAN_INTR_CAN EQU 0x402e0414 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_INT_STATUS__OFFSET +CYFLD_CAN_INT_STATUS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_INT_STATUS__SIZE +CYFLD_CAN_INT_STATUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TT_COMPARE__OFFSET +CYFLD_CAN_TT_COMPARE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TT_COMPARE__SIZE +CYFLD_CAN_TT_COMPARE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TT_CAPTURE__OFFSET +CYFLD_CAN_TT_CAPTURE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CAN_TT_CAPTURE__SIZE +CYFLD_CAN_TT_CAPTURE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CAN_INTR_CAN_SET +CYREG_CAN_INTR_CAN_SET EQU 0x402e0418 + ENDIF + IF :LNOT::DEF:CYREG_CAN_INTR_CAN_MASK +CYREG_CAN_INTR_CAN_MASK EQU 0x402e041c + ENDIF + IF :LNOT::DEF:CYREG_CAN_INTR_CAN_MASKED +CYREG_CAN_INTR_CAN_MASKED EQU 0x402e0420 + ENDIF + IF :LNOT::DEF:CYDEV_EXCO_BASE +CYDEV_EXCO_BASE EQU 0x402f0000 + ENDIF + IF :LNOT::DEF:CYDEV_EXCO_SIZE +CYDEV_EXCO_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_EXCO_CLK_SELECT +CYREG_EXCO_CLK_SELECT EQU 0x402f0000 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_CLK_SELECT__OFFSET +CYFLD_EXCO_CLK_SELECT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_CLK_SELECT__SIZE +CYFLD_EXCO_CLK_SELECT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_REF_SEL__OFFSET +CYFLD_EXCO_REF_SEL__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_REF_SEL__SIZE +CYFLD_EXCO_REF_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_EXCO_ECO_CONFIG +CYREG_EXCO_ECO_CONFIG EQU 0x402f0008 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_CLK_EN__OFFSET +CYFLD_EXCO_CLK_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_CLK_EN__SIZE +CYFLD_EXCO_CLK_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_AGC_EN__OFFSET +CYFLD_EXCO_AGC_EN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_AGC_EN__SIZE +CYFLD_EXCO_AGC_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_ENABLE__OFFSET +CYFLD_EXCO_ENABLE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_ENABLE__SIZE +CYFLD_EXCO_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_EXCO_ECO_STATUS +CYREG_EXCO_ECO_STATUS EQU 0x402f000c + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_WATCHDOG_ERROR__OFFSET +CYFLD_EXCO_WATCHDOG_ERROR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_WATCHDOG_ERROR__SIZE +CYFLD_EXCO_WATCHDOG_ERROR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_EXCO_PLL_CONFIG +CYREG_EXCO_PLL_CONFIG EQU 0x402f0014 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_FEEDBACK_DIV__OFFSET +CYFLD_EXCO_FEEDBACK_DIV__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_FEEDBACK_DIV__SIZE +CYFLD_EXCO_FEEDBACK_DIV__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_REFERENCE_DIV__OFFSET +CYFLD_EXCO_REFERENCE_DIV__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_REFERENCE_DIV__SIZE +CYFLD_EXCO_REFERENCE_DIV__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_OUTPUT_DIV__OFFSET +CYFLD_EXCO_OUTPUT_DIV__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_OUTPUT_DIV__SIZE +CYFLD_EXCO_OUTPUT_DIV__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_OUTPUT_DIV_PASS +CYVAL_EXCO_OUTPUT_DIV_PASS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_OUTPUT_DIV_DIV2 +CYVAL_EXCO_OUTPUT_DIV_DIV2 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_OUTPUT_DIV_DIV4 +CYVAL_EXCO_OUTPUT_DIV_DIV4 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_OUTPUT_DIV_DIV8 +CYVAL_EXCO_OUTPUT_DIV_DIV8 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_ICP_SEL__OFFSET +CYFLD_EXCO_ICP_SEL__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_ICP_SEL__SIZE +CYFLD_EXCO_ICP_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_BYPASS_SEL__OFFSET +CYFLD_EXCO_BYPASS_SEL__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_BYPASS_SEL__SIZE +CYFLD_EXCO_BYPASS_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_BYPASS_SEL_AUTO +CYVAL_EXCO_BYPASS_SEL_AUTO EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_BYPASS_SEL_AUTO1 +CYVAL_EXCO_BYPASS_SEL_AUTO1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_BYPASS_SEL_PLL_REF +CYVAL_EXCO_BYPASS_SEL_PLL_REF EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_BYPASS_SEL_PLL_OUT +CYVAL_EXCO_BYPASS_SEL_PLL_OUT EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_ISOLATE_N__OFFSET +CYFLD_EXCO_ISOLATE_N__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_ISOLATE_N__SIZE +CYFLD_EXCO_ISOLATE_N__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_EXCO_PLL_STATUS +CYREG_EXCO_PLL_STATUS EQU 0x402f0018 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_LOCKED__OFFSET +CYFLD_EXCO_LOCKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_LOCKED__SIZE +CYFLD_EXCO_LOCKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_EXCO_PLL_TEST +CYREG_EXCO_PLL_TEST EQU 0x402f001c + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_TEST_MODE__OFFSET +CYFLD_EXCO_TEST_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_TEST_MODE__SIZE +CYFLD_EXCO_TEST_MODE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_TEST_MODE_NORMAL +CYVAL_EXCO_TEST_MODE_NORMAL EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_TEST_MODE_TEST_VC_LKG +CYVAL_EXCO_TEST_MODE_TEST_VC_LKG EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_TEST_MODE_TEST_CP_DN +CYVAL_EXCO_TEST_MODE_TEST_CP_DN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_TEST_MODE_TEST_CP_UP +CYVAL_EXCO_TEST_MODE_TEST_CP_UP EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_TEST_MODE_USER_EXT_FL +CYVAL_EXCO_TEST_MODE_USER_EXT_FL EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_TEST_MODE_TEST_CTR_PQ +CYVAL_EXCO_TEST_MODE_TEST_CTR_PQ EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_TEST_MODE_TEST_LD_DLY +CYVAL_EXCO_TEST_MODE_TEST_LD_DLY EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_TEST_MODE_TEST_CTR_ALT +CYVAL_EXCO_TEST_MODE_TEST_CTR_ALT EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_FAST_LOCK_EN__OFFSET +CYFLD_EXCO_FAST_LOCK_EN__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_FAST_LOCK_EN__SIZE +CYFLD_EXCO_FAST_LOCK_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_UNLOCK_OCCURRED__OFFSET +CYFLD_EXCO_UNLOCK_OCCURRED__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_UNLOCK_OCCURRED__SIZE +CYFLD_EXCO_UNLOCK_OCCURRED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_EXCO_EXCO_PGM_CLK +CYREG_EXCO_EXCO_PGM_CLK EQU 0x402f0020 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_CLK_ECO__OFFSET +CYFLD_EXCO_CLK_ECO__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_CLK_ECO__SIZE +CYFLD_EXCO_CLK_ECO__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_CLK_PLL0_IN__OFFSET +CYFLD_EXCO_CLK_PLL0_IN__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_CLK_PLL0_IN__SIZE +CYFLD_EXCO_CLK_PLL0_IN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_CLK_PLL0_OUT__OFFSET +CYFLD_EXCO_CLK_PLL0_OUT__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_CLK_PLL0_OUT__SIZE +CYFLD_EXCO_CLK_PLL0_OUT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_EN_CLK_PLL0__OFFSET +CYFLD_EXCO_EN_CLK_PLL0__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_EN_CLK_PLL0__SIZE +CYFLD_EXCO_EN_CLK_PLL0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_EXCO_ECO_TRIM0 +CYREG_EXCO_ECO_TRIM0 EQU 0x402fff00 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_WDTRIM__OFFSET +CYFLD_EXCO_WDTRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_WDTRIM__SIZE +CYFLD_EXCO_WDTRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_ATRIM__OFFSET +CYFLD_EXCO_ATRIM__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_ATRIM__SIZE +CYFLD_EXCO_ATRIM__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_EXCO_ECO_TRIM1 +CYREG_EXCO_ECO_TRIM1 EQU 0x402fff04 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_FTRIM__OFFSET +CYFLD_EXCO_FTRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_FTRIM__SIZE +CYFLD_EXCO_FTRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_RTRIM__OFFSET +CYFLD_EXCO_RTRIM__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_RTRIM__SIZE +CYFLD_EXCO_RTRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_GTRIM__OFFSET +CYFLD_EXCO_GTRIM__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_GTRIM__SIZE +CYFLD_EXCO_GTRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_EXCO_ECO_TRIM2 +CYREG_EXCO_ECO_TRIM2 EQU 0x402fff08 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_ITRIM__OFFSET +CYFLD_EXCO_ITRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_ITRIM__SIZE +CYFLD_EXCO_ITRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_EXCO_PLL_TRIM +CYREG_EXCO_PLL_TRIM EQU 0x402fff0c + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_VCO_GAIN__OFFSET +CYFLD_EXCO_VCO_GAIN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_VCO_GAIN__SIZE +CYFLD_EXCO_VCO_GAIN__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_LOCK_WINDOW__OFFSET +CYFLD_EXCO_LOCK_WINDOW__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_LOCK_WINDOW__SIZE +CYFLD_EXCO_LOCK_WINDOW__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_LOCK_WINDOW_DELAY_25NS +CYVAL_EXCO_LOCK_WINDOW_DELAY_25NS EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_LOCK_WINDOW_DELAY_50NS +CYVAL_EXCO_LOCK_WINDOW_DELAY_50NS EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_LOCK_WINDOW_DELAY_75NS +CYVAL_EXCO_LOCK_WINDOW_DELAY_75NS EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_LOCK_WINDOW_DELAY_100NS +CYVAL_EXCO_LOCK_WINDOW_DELAY_100NS EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_LOCK_DELAY__OFFSET +CYFLD_EXCO_LOCK_DELAY__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_EXCO_LOCK_DELAY__SIZE +CYFLD_EXCO_LOCK_DELAY__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_LOCK_DELAY_PFD_CLK_16 +CYVAL_EXCO_LOCK_DELAY_PFD_CLK_16 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_LOCK_DELAY_PFD_CLK_32 +CYVAL_EXCO_LOCK_DELAY_PFD_CLK_32 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_LOCK_DELAY_PFD_CLK_48 +CYVAL_EXCO_LOCK_DELAY_PFD_CLK_48 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_EXCO_LOCK_DELAY_PFD_CLK_64 +CYVAL_EXCO_LOCK_DELAY_PFD_CLK_64 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CTBM0_BASE +CYDEV_CTBM0_BASE EQU 0x40300000 + ENDIF + IF :LNOT::DEF:CYDEV_CTBM0_SIZE +CYDEV_CTBM0_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_CTB_CTRL +CYREG_CTBM0_CTB_CTRL EQU 0x40300000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DEEPSLEEP_ON__OFFSET +CYFLD_CTBM_DEEPSLEEP_ON__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DEEPSLEEP_ON__SIZE +CYFLD_CTBM_DEEPSLEEP_ON__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_ENABLED__OFFSET +CYFLD_CTBM_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_ENABLED__SIZE +CYFLD_CTBM_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA_RES0_CTRL +CYREG_CTBM0_OA_RES0_CTRL EQU 0x40300004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PWR_MODE__OFFSET +CYFLD_CTBM_OA0_PWR_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PWR_MODE__SIZE +CYFLD_CTBM_OA0_PWR_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_PWR_MODE_OFF +CYVAL_CTBM_OA0_PWR_MODE_OFF EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_PWR_MODE_LOW +CYVAL_CTBM_OA0_PWR_MODE_LOW EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_PWR_MODE_MEDIUM +CYVAL_CTBM_OA0_PWR_MODE_MEDIUM EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_PWR_MODE_HIGH +CYVAL_CTBM_OA0_PWR_MODE_HIGH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET +CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE +CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_EN__OFFSET +CYFLD_CTBM_OA0_COMP_EN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_EN__SIZE +CYFLD_CTBM_OA0_COMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_HYST_EN__OFFSET +CYFLD_CTBM_OA0_HYST_EN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_HYST_EN__SIZE +CYFLD_CTBM_OA0_HYST_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET +CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE +CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_DSI_LEVEL__OFFSET +CYFLD_CTBM_OA0_DSI_LEVEL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_DSI_LEVEL__SIZE +CYFLD_CTBM_OA0_DSI_LEVEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMPINT__OFFSET +CYFLD_CTBM_OA0_COMPINT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMPINT__SIZE +CYFLD_CTBM_OA0_COMPINT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_DISABLE +CYVAL_CTBM_OA0_COMPINT_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_RISING +CYVAL_CTBM_OA0_COMPINT_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_FALLING +CYVAL_CTBM_OA0_COMPINT_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA0_COMPINT_BOTH +CYVAL_CTBM_OA0_COMPINT_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PUMP_EN__OFFSET +CYFLD_CTBM_OA0_PUMP_EN__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_PUMP_EN__SIZE +CYFLD_CTBM_OA0_PUMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA_RES1_CTRL +CYREG_CTBM0_OA_RES1_CTRL EQU 0x40300008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PWR_MODE__OFFSET +CYFLD_CTBM_OA1_PWR_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PWR_MODE__SIZE +CYFLD_CTBM_OA1_PWR_MODE__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET +CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE +CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_EN__OFFSET +CYFLD_CTBM_OA1_COMP_EN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_EN__SIZE +CYFLD_CTBM_OA1_COMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_HYST_EN__OFFSET +CYFLD_CTBM_OA1_HYST_EN__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_HYST_EN__SIZE +CYFLD_CTBM_OA1_HYST_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET +CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE +CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_DSI_LEVEL__OFFSET +CYFLD_CTBM_OA1_DSI_LEVEL__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_DSI_LEVEL__SIZE +CYFLD_CTBM_OA1_DSI_LEVEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMPINT__OFFSET +CYFLD_CTBM_OA1_COMPINT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMPINT__SIZE +CYFLD_CTBM_OA1_COMPINT__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_DISABLE +CYVAL_CTBM_OA1_COMPINT_DISABLE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_RISING +CYVAL_CTBM_OA1_COMPINT_RISING EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_FALLING +CYVAL_CTBM_OA1_COMPINT_FALLING EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_CTBM_OA1_COMPINT_BOTH +CYVAL_CTBM_OA1_COMPINT_BOTH EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PUMP_EN__OFFSET +CYFLD_CTBM_OA1_PUMP_EN__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_PUMP_EN__SIZE +CYFLD_CTBM_OA1_PUMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_COMP_STAT +CYREG_CTBM0_COMP_STAT EQU 0x4030000c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP__OFFSET +CYFLD_CTBM_OA0_COMP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP__SIZE +CYFLD_CTBM_OA0_COMP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP__OFFSET +CYFLD_CTBM_OA1_COMP__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP__SIZE +CYFLD_CTBM_OA1_COMP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_INTR +CYREG_CTBM0_INTR EQU 0x40300020 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0__OFFSET +CYFLD_CTBM_COMP0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0__SIZE +CYFLD_CTBM_COMP0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1__OFFSET +CYFLD_CTBM_COMP1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1__SIZE +CYFLD_CTBM_COMP1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_INTR_SET +CYREG_CTBM0_INTR_SET EQU 0x40300024 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_SET__OFFSET +CYFLD_CTBM_COMP0_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_SET__SIZE +CYFLD_CTBM_COMP0_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_SET__OFFSET +CYFLD_CTBM_COMP1_SET__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_SET__SIZE +CYFLD_CTBM_COMP1_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_INTR_MASK +CYREG_CTBM0_INTR_MASK EQU 0x40300028 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASK__OFFSET +CYFLD_CTBM_COMP0_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASK__SIZE +CYFLD_CTBM_COMP0_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASK__OFFSET +CYFLD_CTBM_COMP1_MASK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASK__SIZE +CYFLD_CTBM_COMP1_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_INTR_MASKED +CYREG_CTBM0_INTR_MASKED EQU 0x4030002c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASKED__OFFSET +CYFLD_CTBM_COMP0_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP0_MASKED__SIZE +CYFLD_CTBM_COMP0_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASKED__OFFSET +CYFLD_CTBM_COMP1_MASKED__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_COMP1_MASKED__SIZE +CYFLD_CTBM_COMP1_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_DFT_CTRL +CYREG_CTBM0_DFT_CTRL EQU 0x40300030 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_MODE__OFFSET +CYFLD_CTBM_DFT_MODE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_MODE__SIZE +CYFLD_CTBM_DFT_MODE__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_EN__OFFSET +CYFLD_CTBM_DFT_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_DFT_EN__SIZE +CYFLD_CTBM_DFT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA0_SW +CYREG_CTBM0_OA0_SW EQU 0x40300080 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A00__OFFSET +CYFLD_CTBM_OA0P_A00__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A00__SIZE +CYFLD_CTBM_OA0P_A00__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A20__OFFSET +CYFLD_CTBM_OA0P_A20__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A20__SIZE +CYFLD_CTBM_OA0P_A20__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A30__OFFSET +CYFLD_CTBM_OA0P_A30__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0P_A30__SIZE +CYFLD_CTBM_OA0P_A30__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A11__OFFSET +CYFLD_CTBM_OA0M_A11__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A11__SIZE +CYFLD_CTBM_OA0M_A11__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A81__OFFSET +CYFLD_CTBM_OA0M_A81__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0M_A81__SIZE +CYFLD_CTBM_OA0M_A81__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51__OFFSET +CYFLD_CTBM_OA0O_D51__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51__SIZE +CYFLD_CTBM_OA0O_D51__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D81__OFFSET +CYFLD_CTBM_OA0O_D81__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D81__SIZE +CYFLD_CTBM_OA0O_D81__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA0_SW_CLEAR +CYREG_CTBM0_OA0_SW_CLEAR EQU 0x40300084 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA1_SW +CYREG_CTBM0_OA1_SW EQU 0x40300088 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A03__OFFSET +CYFLD_CTBM_OA1P_A03__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A03__SIZE +CYFLD_CTBM_OA1P_A03__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A13__OFFSET +CYFLD_CTBM_OA1P_A13__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A13__SIZE +CYFLD_CTBM_OA1P_A13__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A43__OFFSET +CYFLD_CTBM_OA1P_A43__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1P_A43__SIZE +CYFLD_CTBM_OA1P_A43__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A22__OFFSET +CYFLD_CTBM_OA1M_A22__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A22__SIZE +CYFLD_CTBM_OA1M_A22__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A82__OFFSET +CYFLD_CTBM_OA1M_A82__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1M_A82__SIZE +CYFLD_CTBM_OA1M_A82__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52__OFFSET +CYFLD_CTBM_OA1O_D52__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52__SIZE +CYFLD_CTBM_OA1O_D52__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62__OFFSET +CYFLD_CTBM_OA1O_D62__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62__SIZE +CYFLD_CTBM_OA1O_D62__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D82__OFFSET +CYFLD_CTBM_OA1O_D82__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D82__SIZE +CYFLD_CTBM_OA1O_D82__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA1_SW_CLEAR +CYREG_CTBM0_OA1_SW_CLEAR EQU 0x4030008c + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_CTB_SW_HW_CTRL +CYREG_CTBM0_CTB_SW_HW_CTRL EQU 0x403000c0 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P2_HW_CTRL__OFFSET +CYFLD_CTBM_P2_HW_CTRL__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P2_HW_CTRL__SIZE +CYFLD_CTBM_P2_HW_CTRL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P3_HW_CTRL__OFFSET +CYFLD_CTBM_P3_HW_CTRL__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_P3_HW_CTRL__SIZE +CYFLD_CTBM_P3_HW_CTRL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_CTB_SW_STATUS +CYREG_CTBM0_CTB_SW_STATUS EQU 0x403000c4 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51_STAT__OFFSET +CYFLD_CTBM_OA0O_D51_STAT__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0O_D51_STAT__SIZE +CYFLD_CTBM_OA0O_D51_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52_STAT__OFFSET +CYFLD_CTBM_OA1O_D52_STAT__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D52_STAT__SIZE +CYFLD_CTBM_OA1O_D52_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62_STAT__OFFSET +CYFLD_CTBM_OA1O_D62_STAT__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1O_D62_STAT__SIZE +CYFLD_CTBM_OA1O_D62_STAT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA0_OFFSET_TRIM +CYREG_CTBM0_OA0_OFFSET_TRIM EQU 0x40300f00 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA0_SLOPE_OFFSET_TRIM +CYREG_CTBM0_OA0_SLOPE_OFFSET_TRIM EQU 0x40300f04 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA0_COMP_TRIM +CYREG_CTBM0_OA0_COMP_TRIM EQU 0x40300f08 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_TRIM__OFFSET +CYFLD_CTBM_OA0_COMP_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA0_COMP_TRIM__SIZE +CYFLD_CTBM_OA0_COMP_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA1_OFFSET_TRIM +CYREG_CTBM0_OA1_OFFSET_TRIM EQU 0x40300f0c + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA1_SLOPE_OFFSET_TRIM +CYREG_CTBM0_OA1_SLOPE_OFFSET_TRIM EQU 0x40300f10 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET +CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE +CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_CTBM0_OA1_COMP_TRIM +CYREG_CTBM0_OA1_COMP_TRIM EQU 0x40300f14 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_TRIM__OFFSET +CYFLD_CTBM_OA1_COMP_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CTBM_OA1_COMP_TRIM__SIZE +CYFLD_CTBM_OA1_COMP_TRIM__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_SAR_BASE +CYDEV_SAR_BASE EQU 0x403a0000 + ENDIF + IF :LNOT::DEF:CYDEV_SAR_SIZE +CYDEV_SAR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CTRL +CYREG_SAR_CTRL EQU 0x403a0000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_SEL__OFFSET +CYFLD_SAR_VREF_SEL__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_SEL__SIZE +CYFLD_SAR_VREF_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF0 +CYVAL_SAR_VREF_SEL_VREF0 EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF1 +CYVAL_SAR_VREF_SEL_VREF1 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF2 +CYVAL_SAR_VREF_SEL_VREF2 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF_AROUTE +CYVAL_SAR_VREF_SEL_VREF_AROUTE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VBGR +CYVAL_SAR_VREF_SEL_VBGR EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VREF_EXT +CYVAL_SAR_VREF_SEL_VREF_EXT EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VDDA_DIV_2 +CYVAL_SAR_VREF_SEL_VDDA_DIV_2 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_VREF_SEL_VDDA +CYVAL_SAR_VREF_SEL_VDDA EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET +CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_VREF_BYP_CAP_EN__SIZE +CYFLD_SAR_VREF_BYP_CAP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_NEG_SEL__OFFSET +CYFLD_SAR_NEG_SEL__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_NEG_SEL__SIZE +CYFLD_SAR_NEG_SEL__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_VSSA_KELVIN +CYVAL_SAR_NEG_SEL_VSSA_KELVIN EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_ART_VSSA +CYVAL_SAR_NEG_SEL_ART_VSSA EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P1 +CYVAL_SAR_NEG_SEL_P1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P3 +CYVAL_SAR_NEG_SEL_P3 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P5 +CYVAL_SAR_NEG_SEL_P5 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_P7 +CYVAL_SAR_NEG_SEL_P7 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_ACORE +CYVAL_SAR_NEG_SEL_ACORE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_NEG_SEL_VREF +CYVAL_SAR_NEG_SEL_VREF EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET +CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE +CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PWR_CTRL_VREF__OFFSET +CYFLD_SAR_PWR_CTRL_VREF__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PWR_CTRL_VREF__SIZE +CYFLD_SAR_PWR_CTRL_VREF__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR +CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR +CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR +CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR +CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SPARE__OFFSET +CYFLD_SAR_SPARE__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SPARE__SIZE +CYFLD_SAR_SPARE__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_BOOSTPUMP_EN__OFFSET +CYFLD_SAR_BOOSTPUMP_EN__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_BOOSTPUMP_EN__SIZE +CYFLD_SAR_BOOSTPUMP_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ICONT_LV__OFFSET +CYFLD_SAR_ICONT_LV__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ICONT_LV__SIZE +CYFLD_SAR_ICONT_LV__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_NORMAL_PWR +CYVAL_SAR_ICONT_LV_NORMAL_PWR EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_HALF_PWR +CYVAL_SAR_ICONT_LV_HALF_PWR EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_MORE_PWR +CYVAL_SAR_ICONT_LV_MORE_PWR EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_ICONT_LV_QUARTER_PWR +CYVAL_SAR_ICONT_LV_QUARTER_PWR EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DEEPSLEEP_ON__OFFSET +CYFLD_SAR_DEEPSLEEP_ON__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DEEPSLEEP_ON__SIZE +CYFLD_SAR_DEEPSLEEP_ON__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET +CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_CONFIG__SIZE +CYFLD_SAR_DSI_SYNC_CONFIG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_MODE__OFFSET +CYFLD_SAR_DSI_MODE__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_MODE__SIZE +CYFLD_SAR_DSI_MODE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SWITCH_DISABLE__OFFSET +CYFLD_SAR_SWITCH_DISABLE__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SWITCH_DISABLE__SIZE +CYFLD_SAR_SWITCH_DISABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ENABLED__OFFSET +CYFLD_SAR_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ENABLED__SIZE +CYFLD_SAR_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SAMPLE_CTRL +CYREG_SAR_SAMPLE_CTRL EQU 0x403a0004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SUB_RESOLUTION__OFFSET +CYFLD_SAR_SUB_RESOLUTION__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SUB_RESOLUTION__SIZE +CYFLD_SAR_SUB_RESOLUTION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SUB_RESOLUTION_8B +CYVAL_SAR_SUB_RESOLUTION_8B EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SUB_RESOLUTION_10B +CYVAL_SAR_SUB_RESOLUTION_10B EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_LEFT_ALIGN__OFFSET +CYFLD_SAR_LEFT_ALIGN__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_LEFT_ALIGN__SIZE +CYFLD_SAR_LEFT_ALIGN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET +CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE +CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED +CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED +CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET +CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE +CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED +CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED +CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_CNT__OFFSET +CYFLD_SAR_AVG_CNT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_CNT__SIZE +CYFLD_SAR_AVG_CNT__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_SHIFT__OFFSET +CYFLD_SAR_AVG_SHIFT__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_SHIFT__SIZE +CYFLD_SAR_AVG_SHIFT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CONTINUOUS__OFFSET +CYFLD_SAR_CONTINUOUS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CONTINUOUS__SIZE +CYFLD_SAR_CONTINUOUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_EN__OFFSET +CYFLD_SAR_DSI_TRIGGER_EN__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_EN__SIZE +CYFLD_SAR_DSI_TRIGGER_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET +CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE +CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET +CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE +CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET +CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_DSI_OUT_EN__SIZE +CYFLD_SAR_EOS_DSI_OUT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SAMPLE_TIME01 +CYREG_SAR_SAMPLE_TIME01 EQU 0x403a0010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME0__OFFSET +CYFLD_SAR_SAMPLE_TIME0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME0__SIZE +CYFLD_SAR_SAMPLE_TIME0__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME1__OFFSET +CYFLD_SAR_SAMPLE_TIME1__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME1__SIZE +CYFLD_SAR_SAMPLE_TIME1__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_SAR_SAMPLE_TIME23 +CYREG_SAR_SAMPLE_TIME23 EQU 0x403a0014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME2__OFFSET +CYFLD_SAR_SAMPLE_TIME2__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME2__SIZE +CYFLD_SAR_SAMPLE_TIME2__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME3__OFFSET +CYFLD_SAR_SAMPLE_TIME3__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME3__SIZE +CYFLD_SAR_SAMPLE_TIME3__SIZE EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_THRES +CYREG_SAR_RANGE_THRES EQU 0x403a0018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_LOW__OFFSET +CYFLD_SAR_RANGE_LOW__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_LOW__SIZE +CYFLD_SAR_RANGE_LOW__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_HIGH__OFFSET +CYFLD_SAR_RANGE_HIGH__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_HIGH__SIZE +CYFLD_SAR_RANGE_HIGH__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_COND +CYREG_SAR_RANGE_COND EQU 0x403a001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_COND__OFFSET +CYFLD_SAR_RANGE_COND__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_COND__SIZE +CYFLD_SAR_RANGE_COND__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_BELOW +CYVAL_SAR_RANGE_COND_BELOW EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_INSIDE +CYVAL_SAR_RANGE_COND_INSIDE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_ABOVE +CYVAL_SAR_RANGE_COND_ABOVE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RANGE_COND_OUTSIDE +CYVAL_SAR_RANGE_COND_OUTSIDE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_EN +CYREG_SAR_CHAN_EN EQU 0x403a0020 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_EN__OFFSET +CYFLD_SAR_CHAN_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_EN__SIZE +CYFLD_SAR_CHAN_EN__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_START_CTRL +CYREG_SAR_START_CTRL EQU 0x403a0024 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_TRIGGER__OFFSET +CYFLD_SAR_FW_TRIGGER__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_TRIGGER__SIZE +CYFLD_SAR_FW_TRIGGER__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_DFT_CTRL +CYREG_SAR_DFT_CTRL EQU 0x403a0030 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DLY_INC__OFFSET +CYFLD_SAR_DLY_INC__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DLY_INC__SIZE +CYFLD_SAR_DLY_INC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_HIZ__OFFSET +CYFLD_SAR_HIZ__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_HIZ__SIZE +CYFLD_SAR_HIZ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_INC__OFFSET +CYFLD_SAR_DFT_INC__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_INC__SIZE +CYFLD_SAR_DFT_INC__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_OUTC__OFFSET +CYFLD_SAR_DFT_OUTC__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DFT_OUTC__SIZE +CYFLD_SAR_DFT_OUTC__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SEL_CSEL_DFT__OFFSET +CYFLD_SAR_SEL_CSEL_DFT__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SEL_CSEL_DFT__SIZE +CYFLD_SAR_SEL_CSEL_DFT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EN_CSEL_DFT__OFFSET +CYFLD_SAR_EN_CSEL_DFT__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EN_CSEL_DFT__SIZE +CYFLD_SAR_EN_CSEL_DFT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DCEN__OFFSET +CYFLD_SAR_DCEN__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DCEN__SIZE +CYFLD_SAR_DCEN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ADFT_OVERRIDE__OFFSET +CYFLD_SAR_ADFT_OVERRIDE__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_ADFT_OVERRIDE__SIZE +CYFLD_SAR_ADFT_OVERRIDE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG0 +CYREG_SAR_CHAN_CONFIG0 EQU 0x403a0080 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PIN_ADDR__OFFSET +CYFLD_SAR_PIN_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PIN_ADDR__SIZE +CYFLD_SAR_PIN_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PORT_ADDR__OFFSET +CYFLD_SAR_PORT_ADDR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_PORT_ADDR__SIZE +CYFLD_SAR_PORT_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_SARMUX +CYVAL_SAR_PORT_ADDR_SARMUX EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB0 +CYVAL_SAR_PORT_ADDR_CTB0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB1 +CYVAL_SAR_PORT_ADDR_CTB1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB2 +CYVAL_SAR_PORT_ADDR_CTB2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_CTB3 +CYVAL_SAR_PORT_ADDR_CTB3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_AROUTE_VIRT2 +CYVAL_SAR_PORT_ADDR_AROUTE_VIRT2 EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_AROUTE_VIRT1 +CYVAL_SAR_PORT_ADDR_AROUTE_VIRT1 EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_PORT_ADDR_SARMUX_VIRT +CYVAL_SAR_PORT_ADDR_SARMUX_VIRT EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_EN__OFFSET +CYFLD_SAR_DIFFERENTIAL_EN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DIFFERENTIAL_EN__SIZE +CYFLD_SAR_DIFFERENTIAL_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESOLUTION__OFFSET +CYFLD_SAR_RESOLUTION__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESOLUTION__SIZE +CYFLD_SAR_RESOLUTION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RESOLUTION_MAXRES +CYVAL_SAR_RESOLUTION_MAXRES EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_RESOLUTION_SUBRES +CYVAL_SAR_RESOLUTION_SUBRES EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_EN__OFFSET +CYFLD_SAR_AVG_EN__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_AVG_EN__SIZE +CYFLD_SAR_AVG_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET +CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SAMPLE_TIME_SEL__SIZE +CYFLD_SAR_SAMPLE_TIME_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_OUT_EN__OFFSET +CYFLD_SAR_DSI_OUT_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_OUT_EN__SIZE +CYFLD_SAR_DSI_OUT_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG1 +CYREG_SAR_CHAN_CONFIG1 EQU 0x403a0084 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG2 +CYREG_SAR_CHAN_CONFIG2 EQU 0x403a0088 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG3 +CYREG_SAR_CHAN_CONFIG3 EQU 0x403a008c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG4 +CYREG_SAR_CHAN_CONFIG4 EQU 0x403a0090 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG5 +CYREG_SAR_CHAN_CONFIG5 EQU 0x403a0094 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG6 +CYREG_SAR_CHAN_CONFIG6 EQU 0x403a0098 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG7 +CYREG_SAR_CHAN_CONFIG7 EQU 0x403a009c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG8 +CYREG_SAR_CHAN_CONFIG8 EQU 0x403a00a0 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG9 +CYREG_SAR_CHAN_CONFIG9 EQU 0x403a00a4 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG10 +CYREG_SAR_CHAN_CONFIG10 EQU 0x403a00a8 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG11 +CYREG_SAR_CHAN_CONFIG11 EQU 0x403a00ac + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG12 +CYREG_SAR_CHAN_CONFIG12 EQU 0x403a00b0 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG13 +CYREG_SAR_CHAN_CONFIG13 EQU 0x403a00b4 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG14 +CYREG_SAR_CHAN_CONFIG14 EQU 0x403a00b8 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_CONFIG15 +CYREG_SAR_CHAN_CONFIG15 EQU 0x403a00bc + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK0 +CYREG_SAR_CHAN_WORK0 EQU 0x403a0100 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WORK__OFFSET +CYFLD_SAR_WORK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WORK__SIZE +CYFLD_SAR_WORK__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET +CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE +CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK1 +CYREG_SAR_CHAN_WORK1 EQU 0x403a0104 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK2 +CYREG_SAR_CHAN_WORK2 EQU 0x403a0108 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK3 +CYREG_SAR_CHAN_WORK3 EQU 0x403a010c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK4 +CYREG_SAR_CHAN_WORK4 EQU 0x403a0110 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK5 +CYREG_SAR_CHAN_WORK5 EQU 0x403a0114 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK6 +CYREG_SAR_CHAN_WORK6 EQU 0x403a0118 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK7 +CYREG_SAR_CHAN_WORK7 EQU 0x403a011c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK8 +CYREG_SAR_CHAN_WORK8 EQU 0x403a0120 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK9 +CYREG_SAR_CHAN_WORK9 EQU 0x403a0124 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK10 +CYREG_SAR_CHAN_WORK10 EQU 0x403a0128 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK11 +CYREG_SAR_CHAN_WORK11 EQU 0x403a012c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK12 +CYREG_SAR_CHAN_WORK12 EQU 0x403a0130 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK13 +CYREG_SAR_CHAN_WORK13 EQU 0x403a0134 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK14 +CYREG_SAR_CHAN_WORK14 EQU 0x403a0138 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK15 +CYREG_SAR_CHAN_WORK15 EQU 0x403a013c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT0 +CYREG_SAR_CHAN_RESULT0 EQU 0x403a0180 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESULT__OFFSET +CYFLD_SAR_RESULT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RESULT__SIZE +CYFLD_SAR_RESULT__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR_MIR__OFFSET +CYFLD_SAR_SATURATE_INTR_MIR__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR_MIR__SIZE +CYFLD_SAR_SATURATE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR_MIR__OFFSET +CYFLD_SAR_RANGE_INTR_MIR__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR_MIR__SIZE +CYFLD_SAR_RANGE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET +CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE +CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT1 +CYREG_SAR_CHAN_RESULT1 EQU 0x403a0184 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT2 +CYREG_SAR_CHAN_RESULT2 EQU 0x403a0188 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT3 +CYREG_SAR_CHAN_RESULT3 EQU 0x403a018c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT4 +CYREG_SAR_CHAN_RESULT4 EQU 0x403a0190 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT5 +CYREG_SAR_CHAN_RESULT5 EQU 0x403a0194 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT6 +CYREG_SAR_CHAN_RESULT6 EQU 0x403a0198 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT7 +CYREG_SAR_CHAN_RESULT7 EQU 0x403a019c + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT8 +CYREG_SAR_CHAN_RESULT8 EQU 0x403a01a0 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT9 +CYREG_SAR_CHAN_RESULT9 EQU 0x403a01a4 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT10 +CYREG_SAR_CHAN_RESULT10 EQU 0x403a01a8 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT11 +CYREG_SAR_CHAN_RESULT11 EQU 0x403a01ac + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT12 +CYREG_SAR_CHAN_RESULT12 EQU 0x403a01b0 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT13 +CYREG_SAR_CHAN_RESULT13 EQU 0x403a01b4 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT14 +CYREG_SAR_CHAN_RESULT14 EQU 0x403a01b8 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT15 +CYREG_SAR_CHAN_RESULT15 EQU 0x403a01bc + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_WORK_VALID +CYREG_SAR_CHAN_WORK_VALID EQU 0x403a0200 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID__OFFSET +CYFLD_SAR_CHAN_WORK_VALID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_WORK_VALID__SIZE +CYFLD_SAR_CHAN_WORK_VALID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_CHAN_RESULT_VALID +CYREG_SAR_CHAN_RESULT_VALID EQU 0x403a0204 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID__OFFSET +CYFLD_SAR_CHAN_RESULT_VALID__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CHAN_RESULT_VALID__SIZE +CYFLD_SAR_CHAN_RESULT_VALID__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_STATUS +CYREG_SAR_STATUS EQU 0x403a0208 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_CHAN__OFFSET +CYFLD_SAR_CUR_CHAN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_CHAN__SIZE +CYFLD_SAR_CUR_CHAN__SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SW_VREF_NEG__OFFSET +CYFLD_SAR_SW_VREF_NEG__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SW_VREF_NEG__SIZE +CYFLD_SAR_SW_VREF_NEG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_BUSY__OFFSET +CYFLD_SAR_BUSY__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_BUSY__SIZE +CYFLD_SAR_BUSY__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_AVG_STAT +CYREG_SAR_AVG_STAT EQU 0x403a020c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_ACCU__OFFSET +CYFLD_SAR_CUR_AVG_ACCU__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_ACCU__SIZE +CYFLD_SAR_CUR_AVG_ACCU__SIZE EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_CNT__OFFSET +CYFLD_SAR_CUR_AVG_CNT__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CUR_AVG_CNT__SIZE +CYFLD_SAR_CUR_AVG_CNT__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR +CYREG_SAR_INTR EQU 0x403a0210 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_INTR__OFFSET +CYFLD_SAR_EOS_INTR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_INTR__SIZE +CYFLD_SAR_EOS_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_INTR__OFFSET +CYFLD_SAR_OVERFLOW_INTR__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_INTR__SIZE +CYFLD_SAR_OVERFLOW_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_INTR__OFFSET +CYFLD_SAR_FW_COLLISION_INTR__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_INTR__SIZE +CYFLD_SAR_FW_COLLISION_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_INTR__OFFSET +CYFLD_SAR_DSI_COLLISION_INTR__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_INTR__SIZE +CYFLD_SAR_DSI_COLLISION_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR__OFFSET +CYFLD_SAR_INJ_EOC_INTR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR__SIZE +CYFLD_SAR_INJ_EOC_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR__OFFSET +CYFLD_SAR_INJ_SATURATE_INTR__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR__SIZE +CYFLD_SAR_INJ_SATURATE_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR__OFFSET +CYFLD_SAR_INJ_RANGE_INTR__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR__SIZE +CYFLD_SAR_INJ_RANGE_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR__OFFSET +CYFLD_SAR_INJ_COLLISION_INTR__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR__SIZE +CYFLD_SAR_INJ_COLLISION_INTR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_SET +CYREG_SAR_INTR_SET EQU 0x403a0214 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_SET__OFFSET +CYFLD_SAR_EOS_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_SET__SIZE +CYFLD_SAR_EOS_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_SET__OFFSET +CYFLD_SAR_OVERFLOW_SET__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_SET__SIZE +CYFLD_SAR_OVERFLOW_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_SET__OFFSET +CYFLD_SAR_FW_COLLISION_SET__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_SET__SIZE +CYFLD_SAR_FW_COLLISION_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_SET__OFFSET +CYFLD_SAR_DSI_COLLISION_SET__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_SET__SIZE +CYFLD_SAR_DSI_COLLISION_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_SET__OFFSET +CYFLD_SAR_INJ_EOC_SET__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_SET__SIZE +CYFLD_SAR_INJ_EOC_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_SET__OFFSET +CYFLD_SAR_INJ_SATURATE_SET__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_SET__SIZE +CYFLD_SAR_INJ_SATURATE_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_SET__OFFSET +CYFLD_SAR_INJ_RANGE_SET__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_SET__SIZE +CYFLD_SAR_INJ_RANGE_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_SET__OFFSET +CYFLD_SAR_INJ_COLLISION_SET__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_SET__SIZE +CYFLD_SAR_INJ_COLLISION_SET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_MASK +CYREG_SAR_INTR_MASK EQU 0x403a0218 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASK__OFFSET +CYFLD_SAR_EOS_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASK__SIZE +CYFLD_SAR_EOS_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASK__OFFSET +CYFLD_SAR_OVERFLOW_MASK__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASK__SIZE +CYFLD_SAR_OVERFLOW_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASK__OFFSET +CYFLD_SAR_FW_COLLISION_MASK__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASK__SIZE +CYFLD_SAR_FW_COLLISION_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASK__OFFSET +CYFLD_SAR_DSI_COLLISION_MASK__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASK__SIZE +CYFLD_SAR_DSI_COLLISION_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASK__OFFSET +CYFLD_SAR_INJ_EOC_MASK__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASK__SIZE +CYFLD_SAR_INJ_EOC_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASK__OFFSET +CYFLD_SAR_INJ_SATURATE_MASK__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASK__SIZE +CYFLD_SAR_INJ_SATURATE_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASK__OFFSET +CYFLD_SAR_INJ_RANGE_MASK__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASK__SIZE +CYFLD_SAR_INJ_RANGE_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASK__OFFSET +CYFLD_SAR_INJ_COLLISION_MASK__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASK__SIZE +CYFLD_SAR_INJ_COLLISION_MASK__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_MASKED +CYREG_SAR_INTR_MASKED EQU 0x403a021c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED__OFFSET +CYFLD_SAR_EOS_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED__SIZE +CYFLD_SAR_EOS_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED__OFFSET +CYFLD_SAR_OVERFLOW_MASKED__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED__SIZE +CYFLD_SAR_OVERFLOW_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED__OFFSET +CYFLD_SAR_FW_COLLISION_MASKED__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED__SIZE +CYFLD_SAR_FW_COLLISION_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET +CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED__SIZE +CYFLD_SAR_DSI_COLLISION_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED__OFFSET +CYFLD_SAR_INJ_EOC_MASKED__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED__SIZE +CYFLD_SAR_INJ_EOC_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET +CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED__SIZE +CYFLD_SAR_INJ_SATURATE_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED__OFFSET +CYFLD_SAR_INJ_RANGE_MASKED__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED__SIZE +CYFLD_SAR_INJ_RANGE_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET +CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED__SIZE +CYFLD_SAR_INJ_COLLISION_MASKED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR +CYREG_SAR_SATURATE_INTR EQU 0x403a0220 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR__OFFSET +CYFLD_SAR_SATURATE_INTR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_INTR__SIZE +CYFLD_SAR_SATURATE_INTR__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR_SET +CYREG_SAR_SATURATE_INTR_SET EQU 0x403a0224 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_SET__OFFSET +CYFLD_SAR_SATURATE_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_SET__SIZE +CYFLD_SAR_SATURATE_SET__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR_MASK +CYREG_SAR_SATURATE_INTR_MASK EQU 0x403a0228 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASK__OFFSET +CYFLD_SAR_SATURATE_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASK__SIZE +CYFLD_SAR_SATURATE_MASK__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_SATURATE_INTR_MASKED +CYREG_SAR_SATURATE_INTR_MASKED EQU 0x403a022c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED__OFFSET +CYFLD_SAR_SATURATE_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED__SIZE +CYFLD_SAR_SATURATE_MASKED__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR +CYREG_SAR_RANGE_INTR EQU 0x403a0230 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR__OFFSET +CYFLD_SAR_RANGE_INTR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_INTR__SIZE +CYFLD_SAR_RANGE_INTR__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR_SET +CYREG_SAR_RANGE_INTR_SET EQU 0x403a0234 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_SET__OFFSET +CYFLD_SAR_RANGE_SET__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_SET__SIZE +CYFLD_SAR_RANGE_SET__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR_MASK +CYREG_SAR_RANGE_INTR_MASK EQU 0x403a0238 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASK__OFFSET +CYFLD_SAR_RANGE_MASK__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASK__SIZE +CYFLD_SAR_RANGE_MASK__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_RANGE_INTR_MASKED +CYREG_SAR_RANGE_INTR_MASKED EQU 0x403a023c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED__OFFSET +CYFLD_SAR_RANGE_MASKED__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED__SIZE +CYFLD_SAR_RANGE_MASKED__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INTR_CAUSE +CYREG_SAR_INTR_CAUSE EQU 0x403a0240 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED_MIR__OFFSET +CYFLD_SAR_EOS_MASKED_MIR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_EOS_MASKED_MIR__SIZE +CYFLD_SAR_EOS_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET +CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE +CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET +CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE +CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET +CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE +CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE +CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE +CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE +CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET +CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE +CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED_RED__OFFSET +CYFLD_SAR_SATURATE_MASKED_RED__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_SATURATE_MASKED_RED__SIZE +CYFLD_SAR_SATURATE_MASKED_RED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED_RED__OFFSET +CYFLD_SAR_RANGE_MASKED_RED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_RANGE_MASKED_RED__SIZE +CYFLD_SAR_RANGE_MASKED_RED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INJ_CHAN_CONFIG +CYREG_SAR_INJ_CHAN_CONFIG EQU 0x403a0280 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PIN_ADDR__OFFSET +CYFLD_SAR_INJ_PIN_ADDR__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PIN_ADDR__SIZE +CYFLD_SAR_INJ_PIN_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PORT_ADDR__OFFSET +CYFLD_SAR_INJ_PORT_ADDR__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_PORT_ADDR__SIZE +CYFLD_SAR_INJ_PORT_ADDR__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_SARMUX +CYVAL_SAR_INJ_PORT_ADDR_SARMUX EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB0 +CYVAL_SAR_INJ_PORT_ADDR_CTB0 EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB1 +CYVAL_SAR_INJ_PORT_ADDR_CTB1 EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB2 +CYVAL_SAR_INJ_PORT_ADDR_CTB2 EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_CTB3 +CYVAL_SAR_INJ_PORT_ADDR_CTB3 EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT +CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT +CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET +CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE +CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESOLUTION__OFFSET +CYFLD_SAR_INJ_RESOLUTION__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESOLUTION__SIZE +CYFLD_SAR_INJ_RESOLUTION__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_RESOLUTION_12B +CYVAL_SAR_INJ_RESOLUTION_12B EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_INJ_RESOLUTION_SUBRES +CYVAL_SAR_INJ_RESOLUTION_SUBRES EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_AVG_EN__OFFSET +CYFLD_SAR_INJ_AVG_EN__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_AVG_EN__SIZE +CYFLD_SAR_INJ_AVG_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET +CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE +CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_TAILGATING__OFFSET +CYFLD_SAR_INJ_TAILGATING__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_TAILGATING__SIZE +CYFLD_SAR_INJ_TAILGATING__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_START_EN__OFFSET +CYFLD_SAR_INJ_START_EN__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_START_EN__SIZE +CYFLD_SAR_INJ_START_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_INJ_RESULT +CYREG_SAR_INJ_RESULT EQU 0x403a0290 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESULT__OFFSET +CYFLD_SAR_INJ_RESULT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RESULT__SIZE +CYFLD_SAR_INJ_RESULT__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET +CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE +CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET +CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE +CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET +CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE +CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET +CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE +CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH0 +CYREG_SAR_MUX_SWITCH0 EQU 0x403a0300 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE +CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET EQU 0x0000000a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE +CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE +CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE +CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE +CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET +CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE +CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET +CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE +CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET +CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE +CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET +CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE +CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET +CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET EQU 0x0000001d + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE +CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_CLEAR0 +CYREG_SAR_MUX_SWITCH_CLEAR0 EQU 0x403a0304 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH1 +CYREG_SAR_MUX_SWITCH1 EQU 0x403a0308 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET +CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE +CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET +CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE +CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET +CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE +CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET +CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE +CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_CLEAR1 +CYREG_SAR_MUX_SWITCH_CLEAR1 EQU 0x403a030c + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_HW_CTRL +CYREG_SAR_MUX_SWITCH_HW_CTRL EQU 0x403a0340 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P0__SIZE +CYFLD_SAR_MUX_HW_CTRL_P0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P1__SIZE +CYFLD_SAR_MUX_HW_CTRL_P1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P2__SIZE +CYFLD_SAR_MUX_HW_CTRL_P2__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P3__SIZE +CYFLD_SAR_MUX_HW_CTRL_P3__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P4__SIZE +CYFLD_SAR_MUX_HW_CTRL_P4__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P5__SIZE +CYFLD_SAR_MUX_HW_CTRL_P5__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P6__SIZE +CYFLD_SAR_MUX_HW_CTRL_P6__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET +CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_P7__SIZE +CYFLD_SAR_MUX_HW_CTRL_P7__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET +CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE +CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET +CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET EQU 0x00000011 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE +CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET EQU 0x00000012 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET EQU 0x00000013 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE +CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET +CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE +CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET +CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE +CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_MUX_SWITCH_STATUS +CYREG_SAR_MUX_SWITCH_STATUS EQU 0x403a0348 + ENDIF + IF :LNOT::DEF:CYREG_SAR_PUMP_CTRL +CYREG_SAR_PUMP_CTRL EQU 0x403a0380 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CLOCK_SEL__OFFSET +CYFLD_SAR_CLOCK_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CLOCK_SEL__SIZE +CYFLD_SAR_CLOCK_SEL__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_ANA_TRIM +CYREG_SAR_ANA_TRIM EQU 0x403a0f00 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CAP_TRIM__OFFSET +CYFLD_SAR_CAP_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_CAP_TRIM__SIZE +CYFLD_SAR_CAP_TRIM__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_TRIMUNIT__OFFSET +CYFLD_SAR_TRIMUNIT__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_TRIMUNIT__SIZE +CYFLD_SAR_TRIMUNIT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR_WOUNDING +CYREG_SAR_WOUNDING EQU 0x403a0f04 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WOUND_RESOLUTION__OFFSET +CYFLD_SAR_WOUND_RESOLUTION__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_SAR_WOUND_RESOLUTION__SIZE +CYFLD_SAR_WOUND_RESOLUTION__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_12BIT +CYVAL_SAR_WOUND_RESOLUTION_12BIT EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_10BIT +CYVAL_SAR_WOUND_RESOLUTION_10BIT EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_8BIT +CYVAL_SAR_WOUND_RESOLUTION_8BIT EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO +CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_PASS_BASE +CYDEV_PASS_BASE EQU 0x403f0000 + ENDIF + IF :LNOT::DEF:CYDEV_PASS_SIZE +CYDEV_PASS_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYREG_PASS_INTR_CAUSE +CYREG_PASS_INTR_CAUSE EQU 0x403f0000 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_CTB0_INT__OFFSET +CYFLD_PASS_CTB0_INT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_CTB0_INT__SIZE +CYFLD_PASS_CTB0_INT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PASS_DFT_CTRL +CYREG_PASS_DFT_CTRL EQU 0x403f0030 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_ADFT_RES_EN__OFFSET +CYFLD_PASS_DSAB_ADFT_RES_EN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_ADFT_RES_EN__SIZE +CYFLD_PASS_DSAB_ADFT_RES_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PASS_PASS_CTRL +CYREG_PASS_PASS_CTRL EQU 0x403f0108 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_PMPCLK_BYP__OFFSET +CYFLD_PASS_PMPCLK_BYP__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_PMPCLK_BYP__SIZE +CYFLD_PASS_PMPCLK_BYP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_PMPCLK_SRC__OFFSET +CYFLD_PASS_PMPCLK_SRC__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_PMPCLK_SRC__SIZE +CYFLD_PASS_PMPCLK_SRC__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_RMB_BITS__OFFSET +CYFLD_PASS_RMB_BITS__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_RMB_BITS__SIZE +CYFLD_PASS_RMB_BITS__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PASS_DSAB_BASE +CYDEV_PASS_DSAB_BASE EQU 0x403f0e00 + ENDIF + IF :LNOT::DEF:CYDEV_PASS_DSAB_SIZE +CYDEV_PASS_DSAB_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_PASS_DSAB_DSAB_CTRL +CYREG_PASS_DSAB_DSAB_CTRL EQU 0x403f0e00 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_CURRENT_SEL__OFFSET +CYFLD_PASS_DSAB_CURRENT_SEL__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_CURRENT_SEL__SIZE +CYFLD_PASS_DSAB_CURRENT_SEL__SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_SEL_OUT__OFFSET +CYFLD_PASS_DSAB_SEL_OUT__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_SEL_OUT__SIZE +CYFLD_PASS_DSAB_SEL_OUT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_REF_SWAP_EN__OFFSET +CYFLD_PASS_DSAB_REF_SWAP_EN__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_REF_SWAP_EN__SIZE +CYFLD_PASS_DSAB_REF_SWAP_EN__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_BYPASS_MODE_EN__OFFSET +CYFLD_PASS_DSAB_BYPASS_MODE_EN__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_BYPASS_MODE_EN__SIZE +CYFLD_PASS_DSAB_BYPASS_MODE_EN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_STARTUP_RM__OFFSET +CYFLD_PASS_DSAB_STARTUP_RM__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_STARTUP_RM__SIZE +CYFLD_PASS_DSAB_STARTUP_RM__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_ENABLED__OFFSET +CYFLD_PASS_DSAB_ENABLED__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_ENABLED__SIZE +CYFLD_PASS_DSAB_ENABLED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PASS_DSAB_DSAB_DFT +CYREG_PASS_DSAB_DSAB_DFT EQU 0x403f0e04 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_EN_DFT__OFFSET +CYFLD_PASS_DSAB_EN_DFT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_EN_DFT__SIZE +CYFLD_PASS_DSAB_EN_DFT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_PASS_DSAB_TRIM +CYREG_PASS_DSAB_TRIM EQU 0x403f0f00 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_IBIAS_TRIM__OFFSET +CYFLD_PASS_IBIAS_TRIM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_IBIAS_TRIM__SIZE +CYFLD_PASS_IBIAS_TRIM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_RMB_BITS__OFFSET +CYFLD_PASS_DSAB_RMB_BITS__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_PASS_DSAB_RMB_BITS__SIZE +CYFLD_PASS_DSAB_RMB_BITS__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_CM0P_BASE +CYDEV_CM0P_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_CM0P_SIZE +CYDEV_CM0P_SIZE EQU 0x00100000 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_DWT_PID4 +CYREG_CM0P_DWT_PID4 EQU 0xe0001fd0 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VALUE__OFFSET +CYFLD_CM0P_VALUE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VALUE__SIZE +CYFLD_CM0P_VALUE__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_DWT_PID0 +CYREG_CM0P_DWT_PID0 EQU 0xe0001fe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_DWT_PID1 +CYREG_CM0P_DWT_PID1 EQU 0xe0001fe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_DWT_PID2 +CYREG_CM0P_DWT_PID2 EQU 0xe0001fe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_DWT_PID3 +CYREG_CM0P_DWT_PID3 EQU 0xe0001fec + ENDIF + IF :LNOT::DEF:CYREG_CM0P_DWT_CID0 +CYREG_CM0P_DWT_CID0 EQU 0xe0001ff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_DWT_CID1 +CYREG_CM0P_DWT_CID1 EQU 0xe0001ff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_DWT_CID2 +CYREG_CM0P_DWT_CID2 EQU 0xe0001ff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_DWT_CID3 +CYREG_CM0P_DWT_CID3 EQU 0xe0001ffc + ENDIF + IF :LNOT::DEF:CYREG_CM0P_BP_PID4 +CYREG_CM0P_BP_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_BP_PID0 +CYREG_CM0P_BP_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_BP_PID1 +CYREG_CM0P_BP_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_BP_PID2 +CYREG_CM0P_BP_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_BP_PID3 +CYREG_CM0P_BP_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYREG_CM0P_BP_CID0 +CYREG_CM0P_BP_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_BP_CID1 +CYREG_CM0P_BP_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_BP_CID2 +CYREG_CM0P_BP_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_BP_CID3 +CYREG_CM0P_BP_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SYST_CSR +CYREG_CM0P_SYST_CSR EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_ENABLE__OFFSET +CYFLD_CM0P_ENABLE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_ENABLE__SIZE +CYFLD_CM0P_ENABLE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_TICKINT__OFFSET +CYFLD_CM0P_TICKINT__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_TICKINT__SIZE +CYFLD_CM0P_TICKINT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_CLKSOURCE__OFFSET +CYFLD_CM0P_CLKSOURCE__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_CLKSOURCE__SIZE +CYFLD_CM0P_CLKSOURCE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_COUNTFLAG__OFFSET +CYFLD_CM0P_COUNTFLAG__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_COUNTFLAG__SIZE +CYFLD_CM0P_COUNTFLAG__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SYST_RVR +CYREG_CM0P_SYST_RVR EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_RELOAD__OFFSET +CYFLD_CM0P_RELOAD__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_RELOAD__SIZE +CYFLD_CM0P_RELOAD__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SYST_CVR +CYREG_CM0P_SYST_CVR EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_CURRENT__OFFSET +CYFLD_CM0P_CURRENT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_CURRENT__SIZE +CYFLD_CM0P_CURRENT__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SYST_CALIB +CYREG_CM0P_SYST_CALIB EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_TENMS__OFFSET +CYFLD_CM0P_TENMS__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_TENMS__SIZE +CYFLD_CM0P_TENMS__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SKEW__OFFSET +CYFLD_CM0P_SKEW__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SKEW__SIZE +CYFLD_CM0P_SKEW__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_NOREF__OFFSET +CYFLD_CM0P_NOREF__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_NOREF__SIZE +CYFLD_CM0P_NOREF__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ISER +CYREG_CM0P_ISER EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SETENA__OFFSET +CYFLD_CM0P_SETENA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SETENA__SIZE +CYFLD_CM0P_SETENA__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ICER +CYREG_CM0P_ICER EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_CLRENA__OFFSET +CYFLD_CM0P_CLRENA__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_CLRENA__SIZE +CYFLD_CM0P_CLRENA__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ISPR +CYREG_CM0P_ISPR EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SETPEND__OFFSET +CYFLD_CM0P_SETPEND__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SETPEND__SIZE +CYFLD_CM0P_SETPEND__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ICPR +CYREG_CM0P_ICPR EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_CLRPEND__OFFSET +CYFLD_CM0P_CLRPEND__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_CLRPEND__SIZE +CYFLD_CM0P_CLRPEND__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_IPR0 +CYREG_CM0P_IPR0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_N0__OFFSET +CYFLD_CM0P_PRI_N0__OFFSET EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_N0__SIZE +CYFLD_CM0P_PRI_N0__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_N1__OFFSET +CYFLD_CM0P_PRI_N1__OFFSET EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_N1__SIZE +CYFLD_CM0P_PRI_N1__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_N2__OFFSET +CYFLD_CM0P_PRI_N2__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_N2__SIZE +CYFLD_CM0P_PRI_N2__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_N3__OFFSET +CYFLD_CM0P_PRI_N3__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_N3__SIZE +CYFLD_CM0P_PRI_N3__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_IPR1 +CYREG_CM0P_IPR1 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_IPR2 +CYREG_CM0P_IPR2 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_IPR3 +CYREG_CM0P_IPR3 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYREG_CM0P_IPR4 +CYREG_CM0P_IPR4 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_IPR5 +CYREG_CM0P_IPR5 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_IPR6 +CYREG_CM0P_IPR6 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_IPR7 +CYREG_CM0P_IPR7 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYREG_CM0P_CPUID +CYREG_CM0P_CPUID EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_REVISION__OFFSET +CYFLD_CM0P_REVISION__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_REVISION__SIZE +CYFLD_CM0P_REVISION__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PARTNO__OFFSET +CYFLD_CM0P_PARTNO__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PARTNO__SIZE +CYFLD_CM0P_PARTNO__SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_CONSTANT__OFFSET +CYFLD_CM0P_CONSTANT__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_CONSTANT__SIZE +CYFLD_CM0P_CONSTANT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VARIANT__OFFSET +CYFLD_CM0P_VARIANT__OFFSET EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VARIANT__SIZE +CYFLD_CM0P_VARIANT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_IMPLEMENTER__OFFSET +CYFLD_CM0P_IMPLEMENTER__OFFSET EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_IMPLEMENTER__SIZE +CYFLD_CM0P_IMPLEMENTER__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ICSR +CYREG_CM0P_ICSR EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VECTACTIVE__OFFSET +CYFLD_CM0P_VECTACTIVE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VECTACTIVE__SIZE +CYFLD_CM0P_VECTACTIVE__SIZE EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VECTPENDING__OFFSET +CYFLD_CM0P_VECTPENDING__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VECTPENDING__SIZE +CYFLD_CM0P_VECTPENDING__SIZE EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_ISRPENDING__OFFSET +CYFLD_CM0P_ISRPENDING__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_ISRPENDING__SIZE +CYFLD_CM0P_ISRPENDING__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_ISRPREEMPT__OFFSET +CYFLD_CM0P_ISRPREEMPT__OFFSET EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_ISRPREEMPT__SIZE +CYFLD_CM0P_ISRPREEMPT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PENDSTCLR__OFFSET +CYFLD_CM0P_PENDSTCLR__OFFSET EQU 0x00000019 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PENDSTCLR__SIZE +CYFLD_CM0P_PENDSTCLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PENDSTSETb__OFFSET +CYFLD_CM0P_PENDSTSETb__OFFSET EQU 0x0000001a + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PENDSTSETb__SIZE +CYFLD_CM0P_PENDSTSETb__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PENDSVCLR__OFFSET +CYFLD_CM0P_PENDSVCLR__OFFSET EQU 0x0000001b + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PENDSVCLR__SIZE +CYFLD_CM0P_PENDSVCLR__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PENDSVSET__OFFSET +CYFLD_CM0P_PENDSVSET__OFFSET EQU 0x0000001c + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PENDSVSET__SIZE +CYFLD_CM0P_PENDSVSET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_NMIPENDSET__OFFSET +CYFLD_CM0P_NMIPENDSET__OFFSET EQU 0x0000001f + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_NMIPENDSET__SIZE +CYFLD_CM0P_NMIPENDSET__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_VTOR +CYREG_CM0P_VTOR EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_TBLOFF__OFFSET +CYFLD_CM0P_TBLOFF__OFFSET EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_TBLOFF__SIZE +CYFLD_CM0P_TBLOFF__SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_AIRCR +CYREG_CM0P_AIRCR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VECTCLRACTIVE__OFFSET +CYFLD_CM0P_VECTCLRACTIVE__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VECTCLRACTIVE__SIZE +CYFLD_CM0P_VECTCLRACTIVE__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SYSRESETREQ__OFFSET +CYFLD_CM0P_SYSRESETREQ__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SYSRESETREQ__SIZE +CYFLD_CM0P_SYSRESETREQ__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_ENDIANNESS__OFFSET +CYFLD_CM0P_ENDIANNESS__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_ENDIANNESS__SIZE +CYFLD_CM0P_ENDIANNESS__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VECTKEY__OFFSET +CYFLD_CM0P_VECTKEY__OFFSET EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_VECTKEY__SIZE +CYFLD_CM0P_VECTKEY__SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SCR +CYREG_CM0P_SCR EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SLEEPONEXIT__OFFSET +CYFLD_CM0P_SLEEPONEXIT__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SLEEPONEXIT__SIZE +CYFLD_CM0P_SLEEPONEXIT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SLEEPDEEP__OFFSET +CYFLD_CM0P_SLEEPDEEP__OFFSET EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SLEEPDEEP__SIZE +CYFLD_CM0P_SLEEPDEEP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SEVONPEND__OFFSET +CYFLD_CM0P_SEVONPEND__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SEVONPEND__SIZE +CYFLD_CM0P_SEVONPEND__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_CCR +CYREG_CM0P_CCR EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_UNALIGN_TRP__OFFSET +CYFLD_CM0P_UNALIGN_TRP__OFFSET EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_UNALIGN_TRP__SIZE +CYFLD_CM0P_UNALIGN_TRP__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_STKALIGN__OFFSET +CYFLD_CM0P_STKALIGN__OFFSET EQU 0x00000009 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_STKALIGN__SIZE +CYFLD_CM0P_STKALIGN__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SHPR2 +CYREG_CM0P_SHPR2 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_11__OFFSET +CYFLD_CM0P_PRI_11__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_11__SIZE +CYFLD_CM0P_PRI_11__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SHPR3 +CYREG_CM0P_SHPR3 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_14__OFFSET +CYFLD_CM0P_PRI_14__OFFSET EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_14__SIZE +CYFLD_CM0P_PRI_14__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_15__OFFSET +CYFLD_CM0P_PRI_15__OFFSET EQU 0x0000001e + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_PRI_15__SIZE +CYFLD_CM0P_PRI_15__SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SHCSR +CYREG_CM0P_SHCSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SVCALLPENDED__OFFSET +CYFLD_CM0P_SVCALLPENDED__OFFSET EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYFLD_CM0P_SVCALLPENDED__SIZE +CYFLD_CM0P_SVCALLPENDED__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SCS_PID4 +CYREG_CM0P_SCS_PID4 EQU 0xe000efd0 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SCS_PID0 +CYREG_CM0P_SCS_PID0 EQU 0xe000efe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SCS_PID1 +CYREG_CM0P_SCS_PID1 EQU 0xe000efe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SCS_PID2 +CYREG_CM0P_SCS_PID2 EQU 0xe000efe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SCS_PID3 +CYREG_CM0P_SCS_PID3 EQU 0xe000efec + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SCS_CID0 +CYREG_CM0P_SCS_CID0 EQU 0xe000eff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SCS_CID1 +CYREG_CM0P_SCS_CID1 EQU 0xe000eff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SCS_CID2 +CYREG_CM0P_SCS_CID2 EQU 0xe000eff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_SCS_CID3 +CYREG_CM0P_SCS_CID3 EQU 0xe000effc + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_SCS +CYREG_CM0P_ROM_SCS EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_DWT +CYREG_CM0P_ROM_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_BPU +CYREG_CM0P_ROM_BPU EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_END +CYREG_CM0P_ROM_END EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_CSMT +CYREG_CM0P_ROM_CSMT EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_PID4 +CYREG_CM0P_ROM_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_PID0 +CYREG_CM0P_ROM_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_PID1 +CYREG_CM0P_ROM_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_PID2 +CYREG_CM0P_ROM_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_PID3 +CYREG_CM0P_ROM_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_CID0 +CYREG_CM0P_ROM_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_CID1 +CYREG_CM0P_ROM_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_CID2 +CYREG_CM0P_ROM_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYREG_CM0P_ROM_CID3 +CYREG_CM0P_ROM_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_ROMTABLE_BASE +CYDEV_ROMTABLE_BASE EQU 0xf0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ROMTABLE_SIZE +CYDEV_ROMTABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_ADDR +CYREG_ROMTABLE_ADDR EQU 0xf0000000 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_PRESENT__OFFSET +CYFLD_ROMTABLE_PRESENT__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_PRESENT__SIZE +CYFLD_ROMTABLE_PRESENT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_FORMAT_32BIT__OFFSET +CYFLD_ROMTABLE_FORMAT_32BIT__OFFSET EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_FORMAT_32BIT__SIZE +CYFLD_ROMTABLE_FORMAT_32BIT__SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_ADDR_OFFSET__OFFSET +CYFLD_ROMTABLE_ADDR_OFFSET__OFFSET EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_ADDR_OFFSET__SIZE +CYFLD_ROMTABLE_ADDR_OFFSET__SIZE EQU 0x00000014 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_DID +CYREG_ROMTABLE_DID EQU 0xf0000fcc + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_VALUE__OFFSET +CYFLD_ROMTABLE_VALUE__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_VALUE__SIZE +CYFLD_ROMTABLE_VALUE__SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_PID4 +CYREG_ROMTABLE_PID4 EQU 0xf0000fd0 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_JEP_CONTINUATION__OFFSET +CYFLD_ROMTABLE_JEP_CONTINUATION__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_JEP_CONTINUATION__SIZE +CYFLD_ROMTABLE_JEP_CONTINUATION__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_COUNT__OFFSET +CYFLD_ROMTABLE_COUNT__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_COUNT__SIZE +CYFLD_ROMTABLE_COUNT__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_PID5 +CYREG_ROMTABLE_PID5 EQU 0xf0000fd4 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_PID6 +CYREG_ROMTABLE_PID6 EQU 0xf0000fd8 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_PID7 +CYREG_ROMTABLE_PID7 EQU 0xf0000fdc + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_PID0 +CYREG_ROMTABLE_PID0 EQU 0xf0000fe0 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_PN_MIN__OFFSET +CYFLD_ROMTABLE_PN_MIN__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_PN_MIN__SIZE +CYFLD_ROMTABLE_PN_MIN__SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_PID1 +CYREG_ROMTABLE_PID1 EQU 0xf0000fe4 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_PN_MAJ__OFFSET +CYFLD_ROMTABLE_PN_MAJ__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_PN_MAJ__SIZE +CYFLD_ROMTABLE_PN_MAJ__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_JEPID_MIN__OFFSET +CYFLD_ROMTABLE_JEPID_MIN__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_JEPID_MIN__SIZE +CYFLD_ROMTABLE_JEPID_MIN__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_PID2 +CYREG_ROMTABLE_PID2 EQU 0xf0000fe8 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_JEPID_MAJ__OFFSET +CYFLD_ROMTABLE_JEPID_MAJ__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_JEPID_MAJ__SIZE +CYFLD_ROMTABLE_JEPID_MAJ__SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_REV__OFFSET +CYFLD_ROMTABLE_REV__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_REV__SIZE +CYFLD_ROMTABLE_REV__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_PID3 +CYREG_ROMTABLE_PID3 EQU 0xf0000fec + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_CM__OFFSET +CYFLD_ROMTABLE_CM__OFFSET EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_CM__SIZE +CYFLD_ROMTABLE_CM__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_REV_AND__OFFSET +CYFLD_ROMTABLE_REV_AND__OFFSET EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYFLD_ROMTABLE_REV_AND__SIZE +CYFLD_ROMTABLE_REV_AND__SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_CID0 +CYREG_ROMTABLE_CID0 EQU 0xf0000ff0 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_CID1 +CYREG_ROMTABLE_CID1 EQU 0xf0000ff4 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_CID2 +CYREG_ROMTABLE_CID2 EQU 0xf0000ff8 + ENDIF + IF :LNOT::DEF:CYREG_ROMTABLE_CID3 +CYREG_ROMTABLE_CID3 EQU 0xf0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + END diff --git a/cores/asr650x/projects/PSoC4/cydisabledsheets.h b/cores/asr650x/projects/PSoC4/cydisabledsheets.h new file mode 100644 index 00000000..81788739 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cydisabledsheets.h @@ -0,0 +1,5 @@ +#ifndef INCLUDED_CYDISABLEDSHEETS_H +#define INCLUDED_CYDISABLEDSHEETS_H + + +#endif /* INCLUDED_CYDISABLEDSHEETS_H */ diff --git a/cores/asr650x/projects/PSoC4/cyfitter.h b/cores/asr650x/projects/PSoC4/cyfitter.h new file mode 100644 index 00000000..15457a22 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cyfitter.h @@ -0,0 +1,582 @@ +/******************************************************************************* +* File Name: cyfitter.h +* +* PSoC Creator 4.2 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef INCLUDED_CYFITTER_H +#define INCLUDED_CYFITTER_H +#include "cydevice_trm.h" + +/* SPI_1 */ +#define SPI_1_miso_m__0__DR CYREG_GPIO_PRT4_DR +#define SPI_1_miso_m__0__DR_CLR CYREG_GPIO_PRT4_DR_CLR +#define SPI_1_miso_m__0__DR_INV CYREG_GPIO_PRT4_DR_INV +#define SPI_1_miso_m__0__DR_SET CYREG_GPIO_PRT4_DR_SET +#define SPI_1_miso_m__0__HSIOM CYREG_HSIOM_PORT_SEL4 +#define SPI_1_miso_m__0__HSIOM_GPIO 0u +#define SPI_1_miso_m__0__HSIOM_I2C 14u +#define SPI_1_miso_m__0__HSIOM_I2C_SDA 14u +#define SPI_1_miso_m__0__HSIOM_MASK 0x000000F0u +#define SPI_1_miso_m__0__HSIOM_SHIFT 4u +#define SPI_1_miso_m__0__HSIOM_SPI 15u +#define SPI_1_miso_m__0__HSIOM_SPI_MISO 15u +#define SPI_1_miso_m__0__HSIOM_UART 9u +#define SPI_1_miso_m__0__HSIOM_UART_TX 9u +#define SPI_1_miso_m__0__INTCFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_miso_m__0__INTR CYREG_GPIO_PRT4_INTR +#define SPI_1_miso_m__0__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_miso_m__0__INTSTAT CYREG_GPIO_PRT4_INTR +#define SPI_1_miso_m__0__MASK 0x02u +#define SPI_1_miso_m__0__PC CYREG_GPIO_PRT4_PC +#define SPI_1_miso_m__0__PC2 CYREG_GPIO_PRT4_PC2 +#define SPI_1_miso_m__0__PORT 4u +#define SPI_1_miso_m__0__PS CYREG_GPIO_PRT4_PS +#define SPI_1_miso_m__0__SHIFT 1u +#define SPI_1_miso_m__DR CYREG_GPIO_PRT4_DR +#define SPI_1_miso_m__DR_CLR CYREG_GPIO_PRT4_DR_CLR +#define SPI_1_miso_m__DR_INV CYREG_GPIO_PRT4_DR_INV +#define SPI_1_miso_m__DR_SET CYREG_GPIO_PRT4_DR_SET +#define SPI_1_miso_m__INTCFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_miso_m__INTR CYREG_GPIO_PRT4_INTR +#define SPI_1_miso_m__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_miso_m__INTSTAT CYREG_GPIO_PRT4_INTR +#define SPI_1_miso_m__MASK 0x02u +#define SPI_1_miso_m__PC CYREG_GPIO_PRT4_PC +#define SPI_1_miso_m__PC2 CYREG_GPIO_PRT4_PC2 +#define SPI_1_miso_m__PORT 4u +#define SPI_1_miso_m__PS CYREG_GPIO_PRT4_PS +#define SPI_1_miso_m__SHIFT 1u +#define SPI_1_mosi_m__0__DR CYREG_GPIO_PRT4_DR +#define SPI_1_mosi_m__0__DR_CLR CYREG_GPIO_PRT4_DR_CLR +#define SPI_1_mosi_m__0__DR_INV CYREG_GPIO_PRT4_DR_INV +#define SPI_1_mosi_m__0__DR_SET CYREG_GPIO_PRT4_DR_SET +#define SPI_1_mosi_m__0__HSIOM CYREG_HSIOM_PORT_SEL4 +#define SPI_1_mosi_m__0__HSIOM_GPIO 0u +#define SPI_1_mosi_m__0__HSIOM_I2C 14u +#define SPI_1_mosi_m__0__HSIOM_I2C_SCL 14u +#define SPI_1_mosi_m__0__HSIOM_MASK 0x0000000Fu +#define SPI_1_mosi_m__0__HSIOM_SHIFT 0u +#define SPI_1_mosi_m__0__HSIOM_SPI 15u +#define SPI_1_mosi_m__0__HSIOM_SPI_MOSI 15u +#define SPI_1_mosi_m__0__HSIOM_UART 9u +#define SPI_1_mosi_m__0__HSIOM_UART_RX 9u +#define SPI_1_mosi_m__0__INTCFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_mosi_m__0__INTR CYREG_GPIO_PRT4_INTR +#define SPI_1_mosi_m__0__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_mosi_m__0__INTSTAT CYREG_GPIO_PRT4_INTR +#define SPI_1_mosi_m__0__MASK 0x01u +#define SPI_1_mosi_m__0__PC CYREG_GPIO_PRT4_PC +#define SPI_1_mosi_m__0__PC2 CYREG_GPIO_PRT4_PC2 +#define SPI_1_mosi_m__0__PORT 4u +#define SPI_1_mosi_m__0__PS CYREG_GPIO_PRT4_PS +#define SPI_1_mosi_m__0__SHIFT 0u +#define SPI_1_mosi_m__DR CYREG_GPIO_PRT4_DR +#define SPI_1_mosi_m__DR_CLR CYREG_GPIO_PRT4_DR_CLR +#define SPI_1_mosi_m__DR_INV CYREG_GPIO_PRT4_DR_INV +#define SPI_1_mosi_m__DR_SET CYREG_GPIO_PRT4_DR_SET +#define SPI_1_mosi_m__INTCFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_mosi_m__INTR CYREG_GPIO_PRT4_INTR +#define SPI_1_mosi_m__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_mosi_m__INTSTAT CYREG_GPIO_PRT4_INTR +#define SPI_1_mosi_m__MASK 0x01u +#define SPI_1_mosi_m__PC CYREG_GPIO_PRT4_PC +#define SPI_1_mosi_m__PC2 CYREG_GPIO_PRT4_PC2 +#define SPI_1_mosi_m__PORT 4u +#define SPI_1_mosi_m__PS CYREG_GPIO_PRT4_PS +#define SPI_1_mosi_m__SHIFT 0u +#define SPI_1_SCB__CTRL CYREG_SCB0_CTRL +#define SPI_1_SCB__EZ_DATA0 CYREG_SCB0_EZ_DATA0 +#define SPI_1_SCB__EZ_DATA1 CYREG_SCB0_EZ_DATA1 +#define SPI_1_SCB__EZ_DATA10 CYREG_SCB0_EZ_DATA10 +#define SPI_1_SCB__EZ_DATA11 CYREG_SCB0_EZ_DATA11 +#define SPI_1_SCB__EZ_DATA12 CYREG_SCB0_EZ_DATA12 +#define SPI_1_SCB__EZ_DATA13 CYREG_SCB0_EZ_DATA13 +#define SPI_1_SCB__EZ_DATA14 CYREG_SCB0_EZ_DATA14 +#define SPI_1_SCB__EZ_DATA15 CYREG_SCB0_EZ_DATA15 +#define SPI_1_SCB__EZ_DATA16 CYREG_SCB0_EZ_DATA16 +#define SPI_1_SCB__EZ_DATA17 CYREG_SCB0_EZ_DATA17 +#define SPI_1_SCB__EZ_DATA18 CYREG_SCB0_EZ_DATA18 +#define SPI_1_SCB__EZ_DATA19 CYREG_SCB0_EZ_DATA19 +#define SPI_1_SCB__EZ_DATA2 CYREG_SCB0_EZ_DATA2 +#define SPI_1_SCB__EZ_DATA20 CYREG_SCB0_EZ_DATA20 +#define SPI_1_SCB__EZ_DATA21 CYREG_SCB0_EZ_DATA21 +#define SPI_1_SCB__EZ_DATA22 CYREG_SCB0_EZ_DATA22 +#define SPI_1_SCB__EZ_DATA23 CYREG_SCB0_EZ_DATA23 +#define SPI_1_SCB__EZ_DATA24 CYREG_SCB0_EZ_DATA24 +#define SPI_1_SCB__EZ_DATA25 CYREG_SCB0_EZ_DATA25 +#define SPI_1_SCB__EZ_DATA26 CYREG_SCB0_EZ_DATA26 +#define SPI_1_SCB__EZ_DATA27 CYREG_SCB0_EZ_DATA27 +#define SPI_1_SCB__EZ_DATA28 CYREG_SCB0_EZ_DATA28 +#define SPI_1_SCB__EZ_DATA29 CYREG_SCB0_EZ_DATA29 +#define SPI_1_SCB__EZ_DATA3 CYREG_SCB0_EZ_DATA3 +#define SPI_1_SCB__EZ_DATA30 CYREG_SCB0_EZ_DATA30 +#define SPI_1_SCB__EZ_DATA31 CYREG_SCB0_EZ_DATA31 +#define SPI_1_SCB__EZ_DATA4 CYREG_SCB0_EZ_DATA4 +#define SPI_1_SCB__EZ_DATA5 CYREG_SCB0_EZ_DATA5 +#define SPI_1_SCB__EZ_DATA6 CYREG_SCB0_EZ_DATA6 +#define SPI_1_SCB__EZ_DATA7 CYREG_SCB0_EZ_DATA7 +#define SPI_1_SCB__EZ_DATA8 CYREG_SCB0_EZ_DATA8 +#define SPI_1_SCB__EZ_DATA9 CYREG_SCB0_EZ_DATA9 +#define SPI_1_SCB__I2C_CFG CYREG_SCB0_I2C_CFG +#define SPI_1_SCB__I2C_CTRL CYREG_SCB0_I2C_CTRL +#define SPI_1_SCB__I2C_M_CMD CYREG_SCB0_I2C_M_CMD +#define SPI_1_SCB__I2C_S_CMD CYREG_SCB0_I2C_S_CMD +#define SPI_1_SCB__I2C_STATUS CYREG_SCB0_I2C_STATUS +#define SPI_1_SCB__INTR_CAUSE CYREG_SCB0_INTR_CAUSE +#define SPI_1_SCB__INTR_I2C_EC CYREG_SCB0_INTR_I2C_EC +#define SPI_1_SCB__INTR_I2C_EC_MASK CYREG_SCB0_INTR_I2C_EC_MASK +#define SPI_1_SCB__INTR_I2C_EC_MASKED CYREG_SCB0_INTR_I2C_EC_MASKED +#define SPI_1_SCB__INTR_M CYREG_SCB0_INTR_M +#define SPI_1_SCB__INTR_M_MASK CYREG_SCB0_INTR_M_MASK +#define SPI_1_SCB__INTR_M_MASKED CYREG_SCB0_INTR_M_MASKED +#define SPI_1_SCB__INTR_M_SET CYREG_SCB0_INTR_M_SET +#define SPI_1_SCB__INTR_RX CYREG_SCB0_INTR_RX +#define SPI_1_SCB__INTR_RX_MASK CYREG_SCB0_INTR_RX_MASK +#define SPI_1_SCB__INTR_RX_MASKED CYREG_SCB0_INTR_RX_MASKED +#define SPI_1_SCB__INTR_RX_SET CYREG_SCB0_INTR_RX_SET +#define SPI_1_SCB__INTR_S CYREG_SCB0_INTR_S +#define SPI_1_SCB__INTR_S_MASK CYREG_SCB0_INTR_S_MASK +#define SPI_1_SCB__INTR_S_MASKED CYREG_SCB0_INTR_S_MASKED +#define SPI_1_SCB__INTR_S_SET CYREG_SCB0_INTR_S_SET +#define SPI_1_SCB__INTR_SPI_EC CYREG_SCB0_INTR_SPI_EC +#define SPI_1_SCB__INTR_SPI_EC_MASK CYREG_SCB0_INTR_SPI_EC_MASK +#define SPI_1_SCB__INTR_SPI_EC_MASKED CYREG_SCB0_INTR_SPI_EC_MASKED +#define SPI_1_SCB__INTR_TX CYREG_SCB0_INTR_TX +#define SPI_1_SCB__INTR_TX_MASK CYREG_SCB0_INTR_TX_MASK +#define SPI_1_SCB__INTR_TX_MASKED CYREG_SCB0_INTR_TX_MASKED +#define SPI_1_SCB__INTR_TX_SET CYREG_SCB0_INTR_TX_SET +#define SPI_1_SCB__RX_CTRL CYREG_SCB0_RX_CTRL +#define SPI_1_SCB__RX_FIFO_CTRL CYREG_SCB0_RX_FIFO_CTRL +#define SPI_1_SCB__RX_FIFO_RD CYREG_SCB0_RX_FIFO_RD +#define SPI_1_SCB__RX_FIFO_RD_SILENT CYREG_SCB0_RX_FIFO_RD_SILENT +#define SPI_1_SCB__RX_FIFO_STATUS CYREG_SCB0_RX_FIFO_STATUS +#define SPI_1_SCB__RX_MATCH CYREG_SCB0_RX_MATCH +#define SPI_1_SCB__SPI_CTRL CYREG_SCB0_SPI_CTRL +#define SPI_1_SCB__SPI_STATUS CYREG_SCB0_SPI_STATUS +#define SPI_1_SCB__SS0_POSISTION 0u +#define SPI_1_SCB__SS1_POSISTION 1u +#define SPI_1_SCB__SS2_POSISTION 2u +#define SPI_1_SCB__SS3_POSISTION 3u +#define SPI_1_SCB__STATUS CYREG_SCB0_STATUS +#define SPI_1_SCB__TX_CTRL CYREG_SCB0_TX_CTRL +#define SPI_1_SCB__TX_FIFO_CTRL CYREG_SCB0_TX_FIFO_CTRL +#define SPI_1_SCB__TX_FIFO_STATUS CYREG_SCB0_TX_FIFO_STATUS +#define SPI_1_SCB__TX_FIFO_WR CYREG_SCB0_TX_FIFO_WR +#define SPI_1_SCB__UART_CTRL CYREG_SCB0_UART_CTRL +#define SPI_1_SCB__UART_FLOW_CTRL CYREG_SCB0_UART_FLOW_CTRL +#define SPI_1_SCB__UART_RX_CTRL CYREG_SCB0_UART_RX_CTRL +#define SPI_1_SCB__UART_RX_STATUS CYREG_SCB0_UART_RX_STATUS +#define SPI_1_SCB__UART_TX_CTRL CYREG_SCB0_UART_TX_CTRL +#define SPI_1_SCBCLK__CTRL_REGISTER CYREG_PERI_PCLK_CTL0 +#define SPI_1_SCBCLK__DIV_ID 0x00000040u +#define SPI_1_SCBCLK__DIV_REGISTER CYREG_PERI_DIV_16_CTL0 +#define SPI_1_SCBCLK__PA_DIV_ID 0x000000FFu +#define SPI_1_sclk_m__0__DR CYREG_GPIO_PRT4_DR +#define SPI_1_sclk_m__0__DR_CLR CYREG_GPIO_PRT4_DR_CLR +#define SPI_1_sclk_m__0__DR_INV CYREG_GPIO_PRT4_DR_INV +#define SPI_1_sclk_m__0__DR_SET CYREG_GPIO_PRT4_DR_SET +#define SPI_1_sclk_m__0__HSIOM CYREG_HSIOM_PORT_SEL4 +#define SPI_1_sclk_m__0__HSIOM_GPIO 0u +#define SPI_1_sclk_m__0__HSIOM_MASK 0x00000F00u +#define SPI_1_sclk_m__0__HSIOM_SHIFT 8u +#define SPI_1_sclk_m__0__HSIOM_SPI 15u +#define SPI_1_sclk_m__0__HSIOM_SPI_CLK 15u +#define SPI_1_sclk_m__0__HSIOM_UART 9u +#define SPI_1_sclk_m__0__HSIOM_UART_CTS 9u +#define SPI_1_sclk_m__0__INTCFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_sclk_m__0__INTR CYREG_GPIO_PRT4_INTR +#define SPI_1_sclk_m__0__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_sclk_m__0__INTSTAT CYREG_GPIO_PRT4_INTR +#define SPI_1_sclk_m__0__MASK 0x04u +#define SPI_1_sclk_m__0__PC CYREG_GPIO_PRT4_PC +#define SPI_1_sclk_m__0__PC2 CYREG_GPIO_PRT4_PC2 +#define SPI_1_sclk_m__0__PORT 4u +#define SPI_1_sclk_m__0__PS CYREG_GPIO_PRT4_PS +#define SPI_1_sclk_m__0__SHIFT 2u +#define SPI_1_sclk_m__DR CYREG_GPIO_PRT4_DR +#define SPI_1_sclk_m__DR_CLR CYREG_GPIO_PRT4_DR_CLR +#define SPI_1_sclk_m__DR_INV CYREG_GPIO_PRT4_DR_INV +#define SPI_1_sclk_m__DR_SET CYREG_GPIO_PRT4_DR_SET +#define SPI_1_sclk_m__INTCFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_sclk_m__INTR CYREG_GPIO_PRT4_INTR +#define SPI_1_sclk_m__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG +#define SPI_1_sclk_m__INTSTAT CYREG_GPIO_PRT4_INTR +#define SPI_1_sclk_m__MASK 0x04u +#define SPI_1_sclk_m__PC CYREG_GPIO_PRT4_PC +#define SPI_1_sclk_m__PC2 CYREG_GPIO_PRT4_PC2 +#define SPI_1_sclk_m__PORT 4u +#define SPI_1_sclk_m__PS CYREG_GPIO_PRT4_PS +#define SPI_1_sclk_m__SHIFT 2u + +/* UART_1 */ +#define UART_1_rx_wake__0__DR CYREG_GPIO_PRT3_DR +#define UART_1_rx_wake__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR +#define UART_1_rx_wake__0__DR_INV CYREG_GPIO_PRT3_DR_INV +#define UART_1_rx_wake__0__DR_SET CYREG_GPIO_PRT3_DR_SET +#define UART_1_rx_wake__0__HSIOM CYREG_HSIOM_PORT_SEL3 +#define UART_1_rx_wake__0__HSIOM_GPIO 0u +#define UART_1_rx_wake__0__HSIOM_I2C 14u +#define UART_1_rx_wake__0__HSIOM_I2C_SCL 14u +#define UART_1_rx_wake__0__HSIOM_MASK 0x0000000Fu +#define UART_1_rx_wake__0__HSIOM_SHIFT 0u +#define UART_1_rx_wake__0__HSIOM_SPI 15u +#define UART_1_rx_wake__0__HSIOM_SPI_MOSI 15u +#define UART_1_rx_wake__0__HSIOM_UART 9u +#define UART_1_rx_wake__0__HSIOM_UART_RX 9u +#define UART_1_rx_wake__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG +#define UART_1_rx_wake__0__INTR CYREG_GPIO_PRT3_INTR +#define UART_1_rx_wake__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG +#define UART_1_rx_wake__0__INTSTAT CYREG_GPIO_PRT3_INTR +#define UART_1_rx_wake__0__MASK 0x01u +#define UART_1_rx_wake__0__PC CYREG_GPIO_PRT3_PC +#define UART_1_rx_wake__0__PC2 CYREG_GPIO_PRT3_PC2 +#define UART_1_rx_wake__0__PORT 3u +#define UART_1_rx_wake__0__PS CYREG_GPIO_PRT3_PS +#define UART_1_rx_wake__0__SHIFT 0u +#define UART_1_rx_wake__DR CYREG_GPIO_PRT3_DR +#define UART_1_rx_wake__DR_CLR CYREG_GPIO_PRT3_DR_CLR +#define UART_1_rx_wake__DR_INV CYREG_GPIO_PRT3_DR_INV +#define UART_1_rx_wake__DR_SET CYREG_GPIO_PRT3_DR_SET +#define UART_1_rx_wake__INTCFG CYREG_GPIO_PRT3_INTR_CFG +#define UART_1_rx_wake__INTR CYREG_GPIO_PRT3_INTR +#define UART_1_rx_wake__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG +#define UART_1_rx_wake__INTSTAT CYREG_GPIO_PRT3_INTR +#define UART_1_rx_wake__MASK 0x01u +#define UART_1_rx_wake__PC CYREG_GPIO_PRT3_PC +#define UART_1_rx_wake__PC2 CYREG_GPIO_PRT3_PC2 +#define UART_1_rx_wake__PORT 3u +#define UART_1_rx_wake__PS CYREG_GPIO_PRT3_PS +#define UART_1_rx_wake__SHIFT 0u +#define UART_1_rx_wake__SNAP CYREG_GPIO_PRT3_INTR +#define UART_1_RX_WAKEUP_IRQ__INTC_CLR_EN_REG CYREG_CM0P_ICER +#define UART_1_RX_WAKEUP_IRQ__INTC_CLR_PD_REG CYREG_CM0P_ICPR +#define UART_1_RX_WAKEUP_IRQ__INTC_MASK 0x08u +#define UART_1_RX_WAKEUP_IRQ__INTC_NUMBER 3u +#define UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_MASK 0xC0000000u +#define UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_NUM 3u +#define UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_REG CYREG_CM0P_IPR0 +#define UART_1_RX_WAKEUP_IRQ__INTC_SET_EN_REG CYREG_CM0P_ISER +#define UART_1_RX_WAKEUP_IRQ__INTC_SET_PD_REG CYREG_CM0P_ISPR +#define UART_1_SCB__CTRL CYREG_SCB1_CTRL +#define UART_1_SCB__EZ_DATA0 CYREG_SCB1_EZ_DATA0 +#define UART_1_SCB__EZ_DATA1 CYREG_SCB1_EZ_DATA1 +#define UART_1_SCB__EZ_DATA10 CYREG_SCB1_EZ_DATA10 +#define UART_1_SCB__EZ_DATA11 CYREG_SCB1_EZ_DATA11 +#define UART_1_SCB__EZ_DATA12 CYREG_SCB1_EZ_DATA12 +#define UART_1_SCB__EZ_DATA13 CYREG_SCB1_EZ_DATA13 +#define UART_1_SCB__EZ_DATA14 CYREG_SCB1_EZ_DATA14 +#define UART_1_SCB__EZ_DATA15 CYREG_SCB1_EZ_DATA15 +#define UART_1_SCB__EZ_DATA16 CYREG_SCB1_EZ_DATA16 +#define UART_1_SCB__EZ_DATA17 CYREG_SCB1_EZ_DATA17 +#define UART_1_SCB__EZ_DATA18 CYREG_SCB1_EZ_DATA18 +#define UART_1_SCB__EZ_DATA19 CYREG_SCB1_EZ_DATA19 +#define UART_1_SCB__EZ_DATA2 CYREG_SCB1_EZ_DATA2 +#define UART_1_SCB__EZ_DATA20 CYREG_SCB1_EZ_DATA20 +#define UART_1_SCB__EZ_DATA21 CYREG_SCB1_EZ_DATA21 +#define UART_1_SCB__EZ_DATA22 CYREG_SCB1_EZ_DATA22 +#define UART_1_SCB__EZ_DATA23 CYREG_SCB1_EZ_DATA23 +#define UART_1_SCB__EZ_DATA24 CYREG_SCB1_EZ_DATA24 +#define UART_1_SCB__EZ_DATA25 CYREG_SCB1_EZ_DATA25 +#define UART_1_SCB__EZ_DATA26 CYREG_SCB1_EZ_DATA26 +#define UART_1_SCB__EZ_DATA27 CYREG_SCB1_EZ_DATA27 +#define UART_1_SCB__EZ_DATA28 CYREG_SCB1_EZ_DATA28 +#define UART_1_SCB__EZ_DATA29 CYREG_SCB1_EZ_DATA29 +#define UART_1_SCB__EZ_DATA3 CYREG_SCB1_EZ_DATA3 +#define UART_1_SCB__EZ_DATA30 CYREG_SCB1_EZ_DATA30 +#define UART_1_SCB__EZ_DATA31 CYREG_SCB1_EZ_DATA31 +#define UART_1_SCB__EZ_DATA4 CYREG_SCB1_EZ_DATA4 +#define UART_1_SCB__EZ_DATA5 CYREG_SCB1_EZ_DATA5 +#define UART_1_SCB__EZ_DATA6 CYREG_SCB1_EZ_DATA6 +#define UART_1_SCB__EZ_DATA7 CYREG_SCB1_EZ_DATA7 +#define UART_1_SCB__EZ_DATA8 CYREG_SCB1_EZ_DATA8 +#define UART_1_SCB__EZ_DATA9 CYREG_SCB1_EZ_DATA9 +#define UART_1_SCB__I2C_CFG CYREG_SCB1_I2C_CFG +#define UART_1_SCB__I2C_CTRL CYREG_SCB1_I2C_CTRL +#define UART_1_SCB__I2C_M_CMD CYREG_SCB1_I2C_M_CMD +#define UART_1_SCB__I2C_S_CMD CYREG_SCB1_I2C_S_CMD +#define UART_1_SCB__I2C_STATUS CYREG_SCB1_I2C_STATUS +#define UART_1_SCB__INTR_CAUSE CYREG_SCB1_INTR_CAUSE +#define UART_1_SCB__INTR_I2C_EC CYREG_SCB1_INTR_I2C_EC +#define UART_1_SCB__INTR_I2C_EC_MASK CYREG_SCB1_INTR_I2C_EC_MASK +#define UART_1_SCB__INTR_I2C_EC_MASKED CYREG_SCB1_INTR_I2C_EC_MASKED +#define UART_1_SCB__INTR_M CYREG_SCB1_INTR_M +#define UART_1_SCB__INTR_M_MASK CYREG_SCB1_INTR_M_MASK +#define UART_1_SCB__INTR_M_MASKED CYREG_SCB1_INTR_M_MASKED +#define UART_1_SCB__INTR_M_SET CYREG_SCB1_INTR_M_SET +#define UART_1_SCB__INTR_RX CYREG_SCB1_INTR_RX +#define UART_1_SCB__INTR_RX_MASK CYREG_SCB1_INTR_RX_MASK +#define UART_1_SCB__INTR_RX_MASKED CYREG_SCB1_INTR_RX_MASKED +#define UART_1_SCB__INTR_RX_SET CYREG_SCB1_INTR_RX_SET +#define UART_1_SCB__INTR_S CYREG_SCB1_INTR_S +#define UART_1_SCB__INTR_S_MASK CYREG_SCB1_INTR_S_MASK +#define UART_1_SCB__INTR_S_MASKED CYREG_SCB1_INTR_S_MASKED +#define UART_1_SCB__INTR_S_SET CYREG_SCB1_INTR_S_SET +#define UART_1_SCB__INTR_SPI_EC CYREG_SCB1_INTR_SPI_EC +#define UART_1_SCB__INTR_SPI_EC_MASK CYREG_SCB1_INTR_SPI_EC_MASK +#define UART_1_SCB__INTR_SPI_EC_MASKED CYREG_SCB1_INTR_SPI_EC_MASKED +#define UART_1_SCB__INTR_TX CYREG_SCB1_INTR_TX +#define UART_1_SCB__INTR_TX_MASK CYREG_SCB1_INTR_TX_MASK +#define UART_1_SCB__INTR_TX_MASKED CYREG_SCB1_INTR_TX_MASKED +#define UART_1_SCB__INTR_TX_SET CYREG_SCB1_INTR_TX_SET +#define UART_1_SCB__RX_CTRL CYREG_SCB1_RX_CTRL +#define UART_1_SCB__RX_FIFO_CTRL CYREG_SCB1_RX_FIFO_CTRL +#define UART_1_SCB__RX_FIFO_RD CYREG_SCB1_RX_FIFO_RD +#define UART_1_SCB__RX_FIFO_RD_SILENT CYREG_SCB1_RX_FIFO_RD_SILENT +#define UART_1_SCB__RX_FIFO_STATUS CYREG_SCB1_RX_FIFO_STATUS +#define UART_1_SCB__RX_MATCH CYREG_SCB1_RX_MATCH +#define UART_1_SCB__SPI_CTRL CYREG_SCB1_SPI_CTRL +#define UART_1_SCB__SPI_STATUS CYREG_SCB1_SPI_STATUS +#define UART_1_SCB__SS0_POSISTION 0u +#define UART_1_SCB__SS1_POSISTION 1u +#define UART_1_SCB__SS2_POSISTION 2u +#define UART_1_SCB__SS3_POSISTION 3u +#define UART_1_SCB__STATUS CYREG_SCB1_STATUS +#define UART_1_SCB__TX_CTRL CYREG_SCB1_TX_CTRL +#define UART_1_SCB__TX_FIFO_CTRL CYREG_SCB1_TX_FIFO_CTRL +#define UART_1_SCB__TX_FIFO_STATUS CYREG_SCB1_TX_FIFO_STATUS +#define UART_1_SCB__TX_FIFO_WR CYREG_SCB1_TX_FIFO_WR +#define UART_1_SCB__UART_CTRL CYREG_SCB1_UART_CTRL +#define UART_1_SCB__UART_FLOW_CTRL CYREG_SCB1_UART_FLOW_CTRL +#define UART_1_SCB__UART_RX_CTRL CYREG_SCB1_UART_RX_CTRL +#define UART_1_SCB__UART_RX_STATUS CYREG_SCB1_UART_RX_STATUS +#define UART_1_SCB__UART_TX_CTRL CYREG_SCB1_UART_TX_CTRL +#define UART_1_SCB_IRQ__INTC_CLR_EN_REG CYREG_CM0P_ICER +#define UART_1_SCB_IRQ__INTC_CLR_PD_REG CYREG_CM0P_ICPR +#define UART_1_SCB_IRQ__INTC_MASK 0x100u +#define UART_1_SCB_IRQ__INTC_NUMBER 8u +#define UART_1_SCB_IRQ__INTC_PRIOR_MASK 0xC0u +#define UART_1_SCB_IRQ__INTC_PRIOR_NUM 0u +#define UART_1_SCB_IRQ__INTC_PRIOR_REG CYREG_CM0P_IPR2 +#define UART_1_SCB_IRQ__INTC_SET_EN_REG CYREG_CM0P_ISER +#define UART_1_SCB_IRQ__INTC_SET_PD_REG CYREG_CM0P_ISPR +#define UART_1_SCBCLK__CTRL_REGISTER CYREG_PERI_PCLK_CTL1 +#define UART_1_SCBCLK__DIV_ID 0x00000044u +#define UART_1_SCBCLK__DIV_REGISTER CYREG_PERI_DIV_16_CTL4 +#define UART_1_SCBCLK__PA_DIV_ID 0x000000FFu +#define UART_1_tx__0__DR CYREG_GPIO_PRT3_DR +#define UART_1_tx__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR +#define UART_1_tx__0__DR_INV CYREG_GPIO_PRT3_DR_INV +#define UART_1_tx__0__DR_SET CYREG_GPIO_PRT3_DR_SET +#define UART_1_tx__0__HSIOM CYREG_HSIOM_PORT_SEL3 +#define UART_1_tx__0__HSIOM_GPIO 0u +#define UART_1_tx__0__HSIOM_I2C 14u +#define UART_1_tx__0__HSIOM_I2C_SDA 14u +#define UART_1_tx__0__HSIOM_MASK 0x000000F0u +#define UART_1_tx__0__HSIOM_SHIFT 4u +#define UART_1_tx__0__HSIOM_SPI 15u +#define UART_1_tx__0__HSIOM_SPI_MISO 15u +#define UART_1_tx__0__HSIOM_UART 9u +#define UART_1_tx__0__HSIOM_UART_TX 9u +#define UART_1_tx__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG +#define UART_1_tx__0__INTR CYREG_GPIO_PRT3_INTR +#define UART_1_tx__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG +#define UART_1_tx__0__INTSTAT CYREG_GPIO_PRT3_INTR +#define UART_1_tx__0__MASK 0x02u +#define UART_1_tx__0__PC CYREG_GPIO_PRT3_PC +#define UART_1_tx__0__PC2 CYREG_GPIO_PRT3_PC2 +#define UART_1_tx__0__PORT 3u +#define UART_1_tx__0__PS CYREG_GPIO_PRT3_PS +#define UART_1_tx__0__SHIFT 1u +#define UART_1_tx__DR CYREG_GPIO_PRT3_DR +#define UART_1_tx__DR_CLR CYREG_GPIO_PRT3_DR_CLR +#define UART_1_tx__DR_INV CYREG_GPIO_PRT3_DR_INV +#define UART_1_tx__DR_SET CYREG_GPIO_PRT3_DR_SET +#define UART_1_tx__INTCFG CYREG_GPIO_PRT3_INTR_CFG +#define UART_1_tx__INTR CYREG_GPIO_PRT3_INTR +#define UART_1_tx__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG +#define UART_1_tx__INTSTAT CYREG_GPIO_PRT3_INTR +#define UART_1_tx__MASK 0x02u +#define UART_1_tx__PC CYREG_GPIO_PRT3_PC +#define UART_1_tx__PC2 CYREG_GPIO_PRT3_PC2 +#define UART_1_tx__PORT 3u +#define UART_1_tx__PS CYREG_GPIO_PRT3_PS +#define UART_1_tx__SHIFT 1u + +/* Miscellaneous */ +#define CY_PROJECT_NAME "lorawan" +#define CY_VERSION "PSoC Creator 4.2" +#define CYDEV_BANDGAP_VOLTAGE 1.200 +#define CYDEV_BCLK__HFCLK__HZ 48000000U +#define CYDEV_BCLK__HFCLK__KHZ 48000U +#define CYDEV_BCLK__HFCLK__MHZ 48U +#define CYDEV_BCLK__SYSCLK__HZ 48000000U +#define CYDEV_BCLK__SYSCLK__KHZ 48000U +#define CYDEV_BCLK__SYSCLK__MHZ 48U +#define CYDEV_CHIP_DIE_LEOPARD 1u +#define CYDEV_CHIP_DIE_PSOC4A 18u +#define CYDEV_CHIP_DIE_PSOC5LP 2u +#define CYDEV_CHIP_DIE_PSOC5TM 3u +#define CYDEV_CHIP_DIE_TMA4 4u +#define CYDEV_CHIP_DIE_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_FM0P 5u +#define CYDEV_CHIP_FAMILY_FM3 6u +#define CYDEV_CHIP_FAMILY_FM4 7u +#define CYDEV_CHIP_FAMILY_PSOC3 1u +#define CYDEV_CHIP_FAMILY_PSOC4 2u +#define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_FAMILY_PSOC6 4u +#define CYDEV_CHIP_FAMILY_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4 +#define CYDEV_CHIP_JTAG_ID 0x256A11B5u +#define CYDEV_CHIP_MEMBER_3A 1u +#define CYDEV_CHIP_MEMBER_4A 18u +#define CYDEV_CHIP_MEMBER_4D 13u +#define CYDEV_CHIP_MEMBER_4E 6u +#define CYDEV_CHIP_MEMBER_4F 19u +#define CYDEV_CHIP_MEMBER_4G 4u +#define CYDEV_CHIP_MEMBER_4H 17u +#define CYDEV_CHIP_MEMBER_4I 23u +#define CYDEV_CHIP_MEMBER_4J 14u +#define CYDEV_CHIP_MEMBER_4K 15u +#define CYDEV_CHIP_MEMBER_4L 22u +#define CYDEV_CHIP_MEMBER_4M 21u +#define CYDEV_CHIP_MEMBER_4N 10u +#define CYDEV_CHIP_MEMBER_4O 7u +#define CYDEV_CHIP_MEMBER_4P 20u +#define CYDEV_CHIP_MEMBER_4Q 12u +#define CYDEV_CHIP_MEMBER_4R 8u +#define CYDEV_CHIP_MEMBER_4S 11u +#define CYDEV_CHIP_MEMBER_4T 9u +#define CYDEV_CHIP_MEMBER_4U 5u +#define CYDEV_CHIP_MEMBER_4V 16u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_5B 2u +#define CYDEV_CHIP_MEMBER_6A 24u +#define CYDEV_CHIP_MEMBER_FM3 28u +#define CYDEV_CHIP_MEMBER_FM4 29u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u +#define CYDEV_CHIP_MEMBER_UNKNOWN 0u +#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4V +#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED +#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT +#define CYDEV_CHIP_REV_LEOPARD_ES1 0u +#define CYDEV_CHIP_REV_LEOPARD_ES2 1u +#define CYDEV_CHIP_REV_LEOPARD_ES3 3u +#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u +#define CYDEV_CHIP_REV_PSOC4A_ES0 17u +#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u +#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u +#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u +#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u +#define CYDEV_CHIP_REV_TMA4_ES 17u +#define CYDEV_CHIP_REV_TMA4_ES2 33u +#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_3A_ES1 0u +#define CYDEV_CHIP_REVISION_3A_ES2 1u +#define CYDEV_CHIP_REVISION_3A_ES3 3u +#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u +#define CYDEV_CHIP_REVISION_4A_ES0 17u +#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u +#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u +#define CYDEV_CHIP_REVISION_4G_ES 17u +#define CYDEV_CHIP_REVISION_4G_ES2 33u +#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_5A_ES0 0u +#define CYDEV_CHIP_REVISION_5A_ES1 1u +#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u +#define CYDEV_CHIP_REVISION_5B_ES0 0u +#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_6A_ES 17u +#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u +#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u +#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4V_PRODUCTION +#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED +#define CYDEV_CONFIG_READ_ACCELERATOR 1 +#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0 +#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1 +#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2 +#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_Disallowed +#define CYDEV_CONFIGURATION_COMPRESSED 1 +#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0 +#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED +#define CYDEV_CONFIGURATION_MODE_DMA 2 +#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1 +#define CYDEV_DEBUG_PROTECT_KILL 4 +#define CYDEV_DEBUG_PROTECT_OPEN 1 +#define CYDEV_DEBUG_PROTECT_PROTECTED 2 +#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_PROTECTED +#define CYDEV_DEBUGGING_DPS_Disable 3 +#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_Disable +#define CYDEV_DEBUGGING_DPS_SWD 2 +#define CYDEV_DEBUGGING_ENABLE 0 +#define CYDEV_DFT_SELECT_CLK0 8u +#define CYDEV_DFT_SELECT_CLK1 9u +#define CYDEV_DMA_CHANNELS_AVAILABLE 8 +#define CYDEV_HEAP_SIZE 0x1000 +#define CYDEV_IMO_TRIMMED_BY_USB 0u +#define CYDEV_IMO_TRIMMED_BY_WCO 1u +#define CYDEV_INTR_NUMBER_DMA 14u +#define CYDEV_IS_EXPORTING_CODE 0 +#define CYDEV_IS_IMPORTING_CODE 0 +#define CYDEV_PROJ_TYPE 2 +#define CYDEV_PROJ_TYPE_BOOTLOADER 1 +#define CYDEV_PROJ_TYPE_LAUNCHER 5 +#define CYDEV_PROJ_TYPE_LOADABLE 2 +#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4 +#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3 +#define CYDEV_PROJ_TYPE_STANDARD 0 +#define CYDEV_STACK_SIZE 0x0800 +#define CYDEV_USE_BUNDLED_CMSIS 1 +#define CYDEV_VARIABLE_VDDA 1 +#define CYDEV_VDDA 3.3 +#define CYDEV_VDDA_MV 3300 +#define CYDEV_VDDD 3.3 +#define CYDEV_VDDD_MV 3300 +#define CYDEV_WDT_GENERATE_ISR 1u +#define CYIPBLOCK_m0s8cpussv3_VERSION 1 +#define CYIPBLOCK_m0s8crypto_VERSION 2 +#define CYIPBLOCK_m0s8csdv2_VERSION 2 +#define CYIPBLOCK_m0s8exco_VERSION 1 +#define CYIPBLOCK_m0s8ioss_VERSION 1 +#define CYIPBLOCK_m0s8lcd_VERSION 2 +#define CYIPBLOCK_m0s8lpcomp_VERSION 2 +#define CYIPBLOCK_m0s8pass4a_VERSION 1 +#define CYIPBLOCK_m0s8peri_VERSION 1 +#define CYIPBLOCK_m0s8scb_VERSION 2 +#define CYIPBLOCK_m0s8tcpwm_VERSION 2 +#define CYIPBLOCK_m0s8wco_VERSION 1 +#define CYIPBLOCK_s8srsslt_VERSION 1 +#define DMA_CHANNELS_USED__MASK 0u +#define CYDEV_BOOTLOADER_ENABLE 0 + +#endif /* INCLUDED_CYFITTER_H */ diff --git a/cores/asr650x/projects/PSoC4/cyfitter_cfg.h b/cores/asr650x/projects/PSoC4/cyfitter_cfg.h new file mode 100644 index 00000000..c5ca4c78 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cyfitter_cfg.h @@ -0,0 +1,29 @@ +/******************************************************************************* +* File Name: cyfitter_cfg.h +* +* PSoC Creator 4.2 +* +* Description: +* This file provides basic startup and mux configuration settings +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef CYFITTER_CFG_H +#define CYFITTER_CFG_H + +#include "cytypes.h" + +extern void cyfitter_cfg(void); + +/* Analog Set/Unset methods */ + + +#endif /* CYFITTER_CFG_H */ + +/*[]*/ diff --git a/cores/asr650x/projects/PSoC4/cyfittergnu.inc b/cores/asr650x/projects/PSoC4/cyfittergnu.inc new file mode 100644 index 00000000..64e02ae4 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cyfittergnu.inc @@ -0,0 +1,576 @@ +/******************************************************************************* +* File Name: cyfittergnu.inc +* +* PSoC Creator 4.2 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.ifndef INCLUDED_CYFITTERGNU_INC +.set INCLUDED_CYFITTERGNU_INC, 1 +.include "cydevicegnu_trm.inc" + +/* SPI_1 */ +.set SPI_1_miso_m__0__DR, CYREG_GPIO_PRT4_DR +.set SPI_1_miso_m__0__DR_CLR, CYREG_GPIO_PRT4_DR_CLR +.set SPI_1_miso_m__0__DR_INV, CYREG_GPIO_PRT4_DR_INV +.set SPI_1_miso_m__0__DR_SET, CYREG_GPIO_PRT4_DR_SET +.set SPI_1_miso_m__0__HSIOM, CYREG_HSIOM_PORT_SEL4 +.set SPI_1_miso_m__0__HSIOM_GPIO, 0 +.set SPI_1_miso_m__0__HSIOM_I2C, 14 +.set SPI_1_miso_m__0__HSIOM_I2C_SDA, 14 +.set SPI_1_miso_m__0__HSIOM_MASK, 0x000000F0 +.set SPI_1_miso_m__0__HSIOM_SHIFT, 4 +.set SPI_1_miso_m__0__HSIOM_SPI, 15 +.set SPI_1_miso_m__0__HSIOM_SPI_MISO, 15 +.set SPI_1_miso_m__0__HSIOM_UART, 9 +.set SPI_1_miso_m__0__HSIOM_UART_TX, 9 +.set SPI_1_miso_m__0__INTCFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_miso_m__0__INTR, CYREG_GPIO_PRT4_INTR +.set SPI_1_miso_m__0__INTR_CFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_miso_m__0__INTSTAT, CYREG_GPIO_PRT4_INTR +.set SPI_1_miso_m__0__MASK, 0x02 +.set SPI_1_miso_m__0__PC, CYREG_GPIO_PRT4_PC +.set SPI_1_miso_m__0__PC2, CYREG_GPIO_PRT4_PC2 +.set SPI_1_miso_m__0__PORT, 4 +.set SPI_1_miso_m__0__PS, CYREG_GPIO_PRT4_PS +.set SPI_1_miso_m__0__SHIFT, 1 +.set SPI_1_miso_m__DR, CYREG_GPIO_PRT4_DR +.set SPI_1_miso_m__DR_CLR, CYREG_GPIO_PRT4_DR_CLR +.set SPI_1_miso_m__DR_INV, CYREG_GPIO_PRT4_DR_INV +.set SPI_1_miso_m__DR_SET, CYREG_GPIO_PRT4_DR_SET +.set SPI_1_miso_m__INTCFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_miso_m__INTR, CYREG_GPIO_PRT4_INTR +.set SPI_1_miso_m__INTR_CFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_miso_m__INTSTAT, CYREG_GPIO_PRT4_INTR +.set SPI_1_miso_m__MASK, 0x02 +.set SPI_1_miso_m__PC, CYREG_GPIO_PRT4_PC +.set SPI_1_miso_m__PC2, CYREG_GPIO_PRT4_PC2 +.set SPI_1_miso_m__PORT, 4 +.set SPI_1_miso_m__PS, CYREG_GPIO_PRT4_PS +.set SPI_1_miso_m__SHIFT, 1 +.set SPI_1_mosi_m__0__DR, CYREG_GPIO_PRT4_DR +.set SPI_1_mosi_m__0__DR_CLR, CYREG_GPIO_PRT4_DR_CLR +.set SPI_1_mosi_m__0__DR_INV, CYREG_GPIO_PRT4_DR_INV +.set SPI_1_mosi_m__0__DR_SET, CYREG_GPIO_PRT4_DR_SET +.set SPI_1_mosi_m__0__HSIOM, CYREG_HSIOM_PORT_SEL4 +.set SPI_1_mosi_m__0__HSIOM_GPIO, 0 +.set SPI_1_mosi_m__0__HSIOM_I2C, 14 +.set SPI_1_mosi_m__0__HSIOM_I2C_SCL, 14 +.set SPI_1_mosi_m__0__HSIOM_MASK, 0x0000000F +.set SPI_1_mosi_m__0__HSIOM_SHIFT, 0 +.set SPI_1_mosi_m__0__HSIOM_SPI, 15 +.set SPI_1_mosi_m__0__HSIOM_SPI_MOSI, 15 +.set SPI_1_mosi_m__0__HSIOM_UART, 9 +.set SPI_1_mosi_m__0__HSIOM_UART_RX, 9 +.set SPI_1_mosi_m__0__INTCFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_mosi_m__0__INTR, CYREG_GPIO_PRT4_INTR +.set SPI_1_mosi_m__0__INTR_CFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_mosi_m__0__INTSTAT, CYREG_GPIO_PRT4_INTR +.set SPI_1_mosi_m__0__MASK, 0x01 +.set SPI_1_mosi_m__0__PC, CYREG_GPIO_PRT4_PC +.set SPI_1_mosi_m__0__PC2, CYREG_GPIO_PRT4_PC2 +.set SPI_1_mosi_m__0__PORT, 4 +.set SPI_1_mosi_m__0__PS, CYREG_GPIO_PRT4_PS +.set SPI_1_mosi_m__0__SHIFT, 0 +.set SPI_1_mosi_m__DR, CYREG_GPIO_PRT4_DR +.set SPI_1_mosi_m__DR_CLR, CYREG_GPIO_PRT4_DR_CLR +.set SPI_1_mosi_m__DR_INV, CYREG_GPIO_PRT4_DR_INV +.set SPI_1_mosi_m__DR_SET, CYREG_GPIO_PRT4_DR_SET +.set SPI_1_mosi_m__INTCFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_mosi_m__INTR, CYREG_GPIO_PRT4_INTR +.set SPI_1_mosi_m__INTR_CFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_mosi_m__INTSTAT, CYREG_GPIO_PRT4_INTR +.set SPI_1_mosi_m__MASK, 0x01 +.set SPI_1_mosi_m__PC, CYREG_GPIO_PRT4_PC +.set SPI_1_mosi_m__PC2, CYREG_GPIO_PRT4_PC2 +.set SPI_1_mosi_m__PORT, 4 +.set SPI_1_mosi_m__PS, CYREG_GPIO_PRT4_PS +.set SPI_1_mosi_m__SHIFT, 0 +.set SPI_1_SCB__CTRL, CYREG_SCB0_CTRL +.set SPI_1_SCB__EZ_DATA0, CYREG_SCB0_EZ_DATA0 +.set SPI_1_SCB__EZ_DATA1, CYREG_SCB0_EZ_DATA1 +.set SPI_1_SCB__EZ_DATA10, CYREG_SCB0_EZ_DATA10 +.set SPI_1_SCB__EZ_DATA11, CYREG_SCB0_EZ_DATA11 +.set SPI_1_SCB__EZ_DATA12, CYREG_SCB0_EZ_DATA12 +.set SPI_1_SCB__EZ_DATA13, CYREG_SCB0_EZ_DATA13 +.set SPI_1_SCB__EZ_DATA14, CYREG_SCB0_EZ_DATA14 +.set SPI_1_SCB__EZ_DATA15, CYREG_SCB0_EZ_DATA15 +.set SPI_1_SCB__EZ_DATA16, CYREG_SCB0_EZ_DATA16 +.set SPI_1_SCB__EZ_DATA17, CYREG_SCB0_EZ_DATA17 +.set SPI_1_SCB__EZ_DATA18, CYREG_SCB0_EZ_DATA18 +.set SPI_1_SCB__EZ_DATA19, CYREG_SCB0_EZ_DATA19 +.set SPI_1_SCB__EZ_DATA2, CYREG_SCB0_EZ_DATA2 +.set SPI_1_SCB__EZ_DATA20, CYREG_SCB0_EZ_DATA20 +.set SPI_1_SCB__EZ_DATA21, CYREG_SCB0_EZ_DATA21 +.set SPI_1_SCB__EZ_DATA22, CYREG_SCB0_EZ_DATA22 +.set SPI_1_SCB__EZ_DATA23, CYREG_SCB0_EZ_DATA23 +.set SPI_1_SCB__EZ_DATA24, CYREG_SCB0_EZ_DATA24 +.set SPI_1_SCB__EZ_DATA25, CYREG_SCB0_EZ_DATA25 +.set SPI_1_SCB__EZ_DATA26, CYREG_SCB0_EZ_DATA26 +.set SPI_1_SCB__EZ_DATA27, CYREG_SCB0_EZ_DATA27 +.set SPI_1_SCB__EZ_DATA28, CYREG_SCB0_EZ_DATA28 +.set SPI_1_SCB__EZ_DATA29, CYREG_SCB0_EZ_DATA29 +.set SPI_1_SCB__EZ_DATA3, CYREG_SCB0_EZ_DATA3 +.set SPI_1_SCB__EZ_DATA30, CYREG_SCB0_EZ_DATA30 +.set SPI_1_SCB__EZ_DATA31, CYREG_SCB0_EZ_DATA31 +.set SPI_1_SCB__EZ_DATA4, CYREG_SCB0_EZ_DATA4 +.set SPI_1_SCB__EZ_DATA5, CYREG_SCB0_EZ_DATA5 +.set SPI_1_SCB__EZ_DATA6, CYREG_SCB0_EZ_DATA6 +.set SPI_1_SCB__EZ_DATA7, CYREG_SCB0_EZ_DATA7 +.set SPI_1_SCB__EZ_DATA8, CYREG_SCB0_EZ_DATA8 +.set SPI_1_SCB__EZ_DATA9, CYREG_SCB0_EZ_DATA9 +.set SPI_1_SCB__I2C_CFG, CYREG_SCB0_I2C_CFG +.set SPI_1_SCB__I2C_CTRL, CYREG_SCB0_I2C_CTRL +.set SPI_1_SCB__I2C_M_CMD, CYREG_SCB0_I2C_M_CMD +.set SPI_1_SCB__I2C_S_CMD, CYREG_SCB0_I2C_S_CMD +.set SPI_1_SCB__I2C_STATUS, CYREG_SCB0_I2C_STATUS +.set SPI_1_SCB__INTR_CAUSE, CYREG_SCB0_INTR_CAUSE +.set SPI_1_SCB__INTR_I2C_EC, CYREG_SCB0_INTR_I2C_EC +.set SPI_1_SCB__INTR_I2C_EC_MASK, CYREG_SCB0_INTR_I2C_EC_MASK +.set SPI_1_SCB__INTR_I2C_EC_MASKED, CYREG_SCB0_INTR_I2C_EC_MASKED +.set SPI_1_SCB__INTR_M, CYREG_SCB0_INTR_M +.set SPI_1_SCB__INTR_M_MASK, CYREG_SCB0_INTR_M_MASK +.set SPI_1_SCB__INTR_M_MASKED, CYREG_SCB0_INTR_M_MASKED +.set SPI_1_SCB__INTR_M_SET, CYREG_SCB0_INTR_M_SET +.set SPI_1_SCB__INTR_RX, CYREG_SCB0_INTR_RX +.set SPI_1_SCB__INTR_RX_MASK, CYREG_SCB0_INTR_RX_MASK +.set SPI_1_SCB__INTR_RX_MASKED, CYREG_SCB0_INTR_RX_MASKED +.set SPI_1_SCB__INTR_RX_SET, CYREG_SCB0_INTR_RX_SET +.set SPI_1_SCB__INTR_S, CYREG_SCB0_INTR_S +.set SPI_1_SCB__INTR_S_MASK, CYREG_SCB0_INTR_S_MASK +.set SPI_1_SCB__INTR_S_MASKED, CYREG_SCB0_INTR_S_MASKED +.set SPI_1_SCB__INTR_S_SET, CYREG_SCB0_INTR_S_SET +.set SPI_1_SCB__INTR_SPI_EC, CYREG_SCB0_INTR_SPI_EC +.set SPI_1_SCB__INTR_SPI_EC_MASK, CYREG_SCB0_INTR_SPI_EC_MASK +.set SPI_1_SCB__INTR_SPI_EC_MASKED, CYREG_SCB0_INTR_SPI_EC_MASKED +.set SPI_1_SCB__INTR_TX, CYREG_SCB0_INTR_TX +.set SPI_1_SCB__INTR_TX_MASK, CYREG_SCB0_INTR_TX_MASK +.set SPI_1_SCB__INTR_TX_MASKED, CYREG_SCB0_INTR_TX_MASKED +.set SPI_1_SCB__INTR_TX_SET, CYREG_SCB0_INTR_TX_SET +.set SPI_1_SCB__RX_CTRL, CYREG_SCB0_RX_CTRL +.set SPI_1_SCB__RX_FIFO_CTRL, CYREG_SCB0_RX_FIFO_CTRL +.set SPI_1_SCB__RX_FIFO_RD, CYREG_SCB0_RX_FIFO_RD +.set SPI_1_SCB__RX_FIFO_RD_SILENT, CYREG_SCB0_RX_FIFO_RD_SILENT +.set SPI_1_SCB__RX_FIFO_STATUS, CYREG_SCB0_RX_FIFO_STATUS +.set SPI_1_SCB__RX_MATCH, CYREG_SCB0_RX_MATCH +.set SPI_1_SCB__SPI_CTRL, CYREG_SCB0_SPI_CTRL +.set SPI_1_SCB__SPI_STATUS, CYREG_SCB0_SPI_STATUS +.set SPI_1_SCB__SS0_POSISTION, 0 +.set SPI_1_SCB__SS1_POSISTION, 1 +.set SPI_1_SCB__SS2_POSISTION, 2 +.set SPI_1_SCB__SS3_POSISTION, 3 +.set SPI_1_SCB__STATUS, CYREG_SCB0_STATUS +.set SPI_1_SCB__TX_CTRL, CYREG_SCB0_TX_CTRL +.set SPI_1_SCB__TX_FIFO_CTRL, CYREG_SCB0_TX_FIFO_CTRL +.set SPI_1_SCB__TX_FIFO_STATUS, CYREG_SCB0_TX_FIFO_STATUS +.set SPI_1_SCB__TX_FIFO_WR, CYREG_SCB0_TX_FIFO_WR +.set SPI_1_SCB__UART_CTRL, CYREG_SCB0_UART_CTRL +.set SPI_1_SCB__UART_FLOW_CTRL, CYREG_SCB0_UART_FLOW_CTRL +.set SPI_1_SCB__UART_RX_CTRL, CYREG_SCB0_UART_RX_CTRL +.set SPI_1_SCB__UART_RX_STATUS, CYREG_SCB0_UART_RX_STATUS +.set SPI_1_SCB__UART_TX_CTRL, CYREG_SCB0_UART_TX_CTRL +.set SPI_1_SCBCLK__CTRL_REGISTER, CYREG_PERI_PCLK_CTL0 +.set SPI_1_SCBCLK__DIV_ID, 0x00000040 +.set SPI_1_SCBCLK__DIV_REGISTER, CYREG_PERI_DIV_16_CTL0 +.set SPI_1_SCBCLK__PA_DIV_ID, 0x000000FF +.set SPI_1_sclk_m__0__DR, CYREG_GPIO_PRT4_DR +.set SPI_1_sclk_m__0__DR_CLR, CYREG_GPIO_PRT4_DR_CLR +.set SPI_1_sclk_m__0__DR_INV, CYREG_GPIO_PRT4_DR_INV +.set SPI_1_sclk_m__0__DR_SET, CYREG_GPIO_PRT4_DR_SET +.set SPI_1_sclk_m__0__HSIOM, CYREG_HSIOM_PORT_SEL4 +.set SPI_1_sclk_m__0__HSIOM_GPIO, 0 +.set SPI_1_sclk_m__0__HSIOM_MASK, 0x00000F00 +.set SPI_1_sclk_m__0__HSIOM_SHIFT, 8 +.set SPI_1_sclk_m__0__HSIOM_SPI, 15 +.set SPI_1_sclk_m__0__HSIOM_SPI_CLK, 15 +.set SPI_1_sclk_m__0__HSIOM_UART, 9 +.set SPI_1_sclk_m__0__HSIOM_UART_CTS, 9 +.set SPI_1_sclk_m__0__INTCFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_sclk_m__0__INTR, CYREG_GPIO_PRT4_INTR +.set SPI_1_sclk_m__0__INTR_CFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_sclk_m__0__INTSTAT, CYREG_GPIO_PRT4_INTR +.set SPI_1_sclk_m__0__MASK, 0x04 +.set SPI_1_sclk_m__0__PC, CYREG_GPIO_PRT4_PC +.set SPI_1_sclk_m__0__PC2, CYREG_GPIO_PRT4_PC2 +.set SPI_1_sclk_m__0__PORT, 4 +.set SPI_1_sclk_m__0__PS, CYREG_GPIO_PRT4_PS +.set SPI_1_sclk_m__0__SHIFT, 2 +.set SPI_1_sclk_m__DR, CYREG_GPIO_PRT4_DR +.set SPI_1_sclk_m__DR_CLR, CYREG_GPIO_PRT4_DR_CLR +.set SPI_1_sclk_m__DR_INV, CYREG_GPIO_PRT4_DR_INV +.set SPI_1_sclk_m__DR_SET, CYREG_GPIO_PRT4_DR_SET +.set SPI_1_sclk_m__INTCFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_sclk_m__INTR, CYREG_GPIO_PRT4_INTR +.set SPI_1_sclk_m__INTR_CFG, CYREG_GPIO_PRT4_INTR_CFG +.set SPI_1_sclk_m__INTSTAT, CYREG_GPIO_PRT4_INTR +.set SPI_1_sclk_m__MASK, 0x04 +.set SPI_1_sclk_m__PC, CYREG_GPIO_PRT4_PC +.set SPI_1_sclk_m__PC2, CYREG_GPIO_PRT4_PC2 +.set SPI_1_sclk_m__PORT, 4 +.set SPI_1_sclk_m__PS, CYREG_GPIO_PRT4_PS +.set SPI_1_sclk_m__SHIFT, 2 + +/* UART_1 */ +.set UART_1_rx_wake__0__DR, CYREG_GPIO_PRT3_DR +.set UART_1_rx_wake__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR +.set UART_1_rx_wake__0__DR_INV, CYREG_GPIO_PRT3_DR_INV +.set UART_1_rx_wake__0__DR_SET, CYREG_GPIO_PRT3_DR_SET +.set UART_1_rx_wake__0__HSIOM, CYREG_HSIOM_PORT_SEL3 +.set UART_1_rx_wake__0__HSIOM_GPIO, 0 +.set UART_1_rx_wake__0__HSIOM_I2C, 14 +.set UART_1_rx_wake__0__HSIOM_I2C_SCL, 14 +.set UART_1_rx_wake__0__HSIOM_MASK, 0x0000000F +.set UART_1_rx_wake__0__HSIOM_SHIFT, 0 +.set UART_1_rx_wake__0__HSIOM_SPI, 15 +.set UART_1_rx_wake__0__HSIOM_SPI_MOSI, 15 +.set UART_1_rx_wake__0__HSIOM_UART, 9 +.set UART_1_rx_wake__0__HSIOM_UART_RX, 9 +.set UART_1_rx_wake__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG +.set UART_1_rx_wake__0__INTR, CYREG_GPIO_PRT3_INTR +.set UART_1_rx_wake__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG +.set UART_1_rx_wake__0__INTSTAT, CYREG_GPIO_PRT3_INTR +.set UART_1_rx_wake__0__MASK, 0x01 +.set UART_1_rx_wake__0__PC, CYREG_GPIO_PRT3_PC +.set UART_1_rx_wake__0__PC2, CYREG_GPIO_PRT3_PC2 +.set UART_1_rx_wake__0__PORT, 3 +.set UART_1_rx_wake__0__PS, CYREG_GPIO_PRT3_PS +.set UART_1_rx_wake__0__SHIFT, 0 +.set UART_1_rx_wake__DR, CYREG_GPIO_PRT3_DR +.set UART_1_rx_wake__DR_CLR, CYREG_GPIO_PRT3_DR_CLR +.set UART_1_rx_wake__DR_INV, CYREG_GPIO_PRT3_DR_INV +.set UART_1_rx_wake__DR_SET, CYREG_GPIO_PRT3_DR_SET +.set UART_1_rx_wake__INTCFG, CYREG_GPIO_PRT3_INTR_CFG +.set UART_1_rx_wake__INTR, CYREG_GPIO_PRT3_INTR +.set UART_1_rx_wake__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG +.set UART_1_rx_wake__INTSTAT, CYREG_GPIO_PRT3_INTR +.set UART_1_rx_wake__MASK, 0x01 +.set UART_1_rx_wake__PC, CYREG_GPIO_PRT3_PC +.set UART_1_rx_wake__PC2, CYREG_GPIO_PRT3_PC2 +.set UART_1_rx_wake__PORT, 3 +.set UART_1_rx_wake__PS, CYREG_GPIO_PRT3_PS +.set UART_1_rx_wake__SHIFT, 0 +.set UART_1_rx_wake__SNAP, CYREG_GPIO_PRT3_INTR +.set UART_1_RX_WAKEUP_IRQ__INTC_CLR_EN_REG, CYREG_CM0P_ICER +.set UART_1_RX_WAKEUP_IRQ__INTC_CLR_PD_REG, CYREG_CM0P_ICPR +.set UART_1_RX_WAKEUP_IRQ__INTC_MASK, 0x08 +.set UART_1_RX_WAKEUP_IRQ__INTC_NUMBER, 3 +.set UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_MASK, 0xC0000000 +.set UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_NUM, 3 +.set UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_REG, CYREG_CM0P_IPR0 +.set UART_1_RX_WAKEUP_IRQ__INTC_SET_EN_REG, CYREG_CM0P_ISER +.set UART_1_RX_WAKEUP_IRQ__INTC_SET_PD_REG, CYREG_CM0P_ISPR +.set UART_1_SCB__CTRL, CYREG_SCB1_CTRL +.set UART_1_SCB__EZ_DATA0, CYREG_SCB1_EZ_DATA0 +.set UART_1_SCB__EZ_DATA1, CYREG_SCB1_EZ_DATA1 +.set UART_1_SCB__EZ_DATA10, CYREG_SCB1_EZ_DATA10 +.set UART_1_SCB__EZ_DATA11, CYREG_SCB1_EZ_DATA11 +.set UART_1_SCB__EZ_DATA12, CYREG_SCB1_EZ_DATA12 +.set UART_1_SCB__EZ_DATA13, CYREG_SCB1_EZ_DATA13 +.set UART_1_SCB__EZ_DATA14, CYREG_SCB1_EZ_DATA14 +.set UART_1_SCB__EZ_DATA15, CYREG_SCB1_EZ_DATA15 +.set UART_1_SCB__EZ_DATA16, CYREG_SCB1_EZ_DATA16 +.set UART_1_SCB__EZ_DATA17, CYREG_SCB1_EZ_DATA17 +.set UART_1_SCB__EZ_DATA18, CYREG_SCB1_EZ_DATA18 +.set UART_1_SCB__EZ_DATA19, CYREG_SCB1_EZ_DATA19 +.set UART_1_SCB__EZ_DATA2, CYREG_SCB1_EZ_DATA2 +.set UART_1_SCB__EZ_DATA20, CYREG_SCB1_EZ_DATA20 +.set UART_1_SCB__EZ_DATA21, CYREG_SCB1_EZ_DATA21 +.set UART_1_SCB__EZ_DATA22, CYREG_SCB1_EZ_DATA22 +.set UART_1_SCB__EZ_DATA23, CYREG_SCB1_EZ_DATA23 +.set UART_1_SCB__EZ_DATA24, CYREG_SCB1_EZ_DATA24 +.set UART_1_SCB__EZ_DATA25, CYREG_SCB1_EZ_DATA25 +.set UART_1_SCB__EZ_DATA26, CYREG_SCB1_EZ_DATA26 +.set UART_1_SCB__EZ_DATA27, CYREG_SCB1_EZ_DATA27 +.set UART_1_SCB__EZ_DATA28, CYREG_SCB1_EZ_DATA28 +.set UART_1_SCB__EZ_DATA29, CYREG_SCB1_EZ_DATA29 +.set UART_1_SCB__EZ_DATA3, CYREG_SCB1_EZ_DATA3 +.set UART_1_SCB__EZ_DATA30, CYREG_SCB1_EZ_DATA30 +.set UART_1_SCB__EZ_DATA31, CYREG_SCB1_EZ_DATA31 +.set UART_1_SCB__EZ_DATA4, CYREG_SCB1_EZ_DATA4 +.set UART_1_SCB__EZ_DATA5, CYREG_SCB1_EZ_DATA5 +.set UART_1_SCB__EZ_DATA6, CYREG_SCB1_EZ_DATA6 +.set UART_1_SCB__EZ_DATA7, CYREG_SCB1_EZ_DATA7 +.set UART_1_SCB__EZ_DATA8, CYREG_SCB1_EZ_DATA8 +.set UART_1_SCB__EZ_DATA9, CYREG_SCB1_EZ_DATA9 +.set UART_1_SCB__I2C_CFG, CYREG_SCB1_I2C_CFG +.set UART_1_SCB__I2C_CTRL, CYREG_SCB1_I2C_CTRL +.set UART_1_SCB__I2C_M_CMD, CYREG_SCB1_I2C_M_CMD +.set UART_1_SCB__I2C_S_CMD, CYREG_SCB1_I2C_S_CMD +.set UART_1_SCB__I2C_STATUS, CYREG_SCB1_I2C_STATUS +.set UART_1_SCB__INTR_CAUSE, CYREG_SCB1_INTR_CAUSE +.set UART_1_SCB__INTR_I2C_EC, CYREG_SCB1_INTR_I2C_EC +.set UART_1_SCB__INTR_I2C_EC_MASK, CYREG_SCB1_INTR_I2C_EC_MASK +.set UART_1_SCB__INTR_I2C_EC_MASKED, CYREG_SCB1_INTR_I2C_EC_MASKED +.set UART_1_SCB__INTR_M, CYREG_SCB1_INTR_M +.set UART_1_SCB__INTR_M_MASK, CYREG_SCB1_INTR_M_MASK +.set UART_1_SCB__INTR_M_MASKED, CYREG_SCB1_INTR_M_MASKED +.set UART_1_SCB__INTR_M_SET, CYREG_SCB1_INTR_M_SET +.set UART_1_SCB__INTR_RX, CYREG_SCB1_INTR_RX +.set UART_1_SCB__INTR_RX_MASK, CYREG_SCB1_INTR_RX_MASK +.set UART_1_SCB__INTR_RX_MASKED, CYREG_SCB1_INTR_RX_MASKED +.set UART_1_SCB__INTR_RX_SET, CYREG_SCB1_INTR_RX_SET +.set UART_1_SCB__INTR_S, CYREG_SCB1_INTR_S +.set UART_1_SCB__INTR_S_MASK, CYREG_SCB1_INTR_S_MASK +.set UART_1_SCB__INTR_S_MASKED, CYREG_SCB1_INTR_S_MASKED +.set UART_1_SCB__INTR_S_SET, CYREG_SCB1_INTR_S_SET +.set UART_1_SCB__INTR_SPI_EC, CYREG_SCB1_INTR_SPI_EC +.set UART_1_SCB__INTR_SPI_EC_MASK, CYREG_SCB1_INTR_SPI_EC_MASK +.set UART_1_SCB__INTR_SPI_EC_MASKED, CYREG_SCB1_INTR_SPI_EC_MASKED +.set UART_1_SCB__INTR_TX, CYREG_SCB1_INTR_TX +.set UART_1_SCB__INTR_TX_MASK, CYREG_SCB1_INTR_TX_MASK +.set UART_1_SCB__INTR_TX_MASKED, CYREG_SCB1_INTR_TX_MASKED +.set UART_1_SCB__INTR_TX_SET, CYREG_SCB1_INTR_TX_SET +.set UART_1_SCB__RX_CTRL, CYREG_SCB1_RX_CTRL +.set UART_1_SCB__RX_FIFO_CTRL, CYREG_SCB1_RX_FIFO_CTRL +.set UART_1_SCB__RX_FIFO_RD, CYREG_SCB1_RX_FIFO_RD +.set UART_1_SCB__RX_FIFO_RD_SILENT, CYREG_SCB1_RX_FIFO_RD_SILENT +.set UART_1_SCB__RX_FIFO_STATUS, CYREG_SCB1_RX_FIFO_STATUS +.set UART_1_SCB__RX_MATCH, CYREG_SCB1_RX_MATCH +.set UART_1_SCB__SPI_CTRL, CYREG_SCB1_SPI_CTRL +.set UART_1_SCB__SPI_STATUS, CYREG_SCB1_SPI_STATUS +.set UART_1_SCB__SS0_POSISTION, 0 +.set UART_1_SCB__SS1_POSISTION, 1 +.set UART_1_SCB__SS2_POSISTION, 2 +.set UART_1_SCB__SS3_POSISTION, 3 +.set UART_1_SCB__STATUS, CYREG_SCB1_STATUS +.set UART_1_SCB__TX_CTRL, CYREG_SCB1_TX_CTRL +.set UART_1_SCB__TX_FIFO_CTRL, CYREG_SCB1_TX_FIFO_CTRL +.set UART_1_SCB__TX_FIFO_STATUS, CYREG_SCB1_TX_FIFO_STATUS +.set UART_1_SCB__TX_FIFO_WR, CYREG_SCB1_TX_FIFO_WR +.set UART_1_SCB__UART_CTRL, CYREG_SCB1_UART_CTRL +.set UART_1_SCB__UART_FLOW_CTRL, CYREG_SCB1_UART_FLOW_CTRL +.set UART_1_SCB__UART_RX_CTRL, CYREG_SCB1_UART_RX_CTRL +.set UART_1_SCB__UART_RX_STATUS, CYREG_SCB1_UART_RX_STATUS +.set UART_1_SCB__UART_TX_CTRL, CYREG_SCB1_UART_TX_CTRL +.set UART_1_SCB_IRQ__INTC_CLR_EN_REG, CYREG_CM0P_ICER +.set UART_1_SCB_IRQ__INTC_CLR_PD_REG, CYREG_CM0P_ICPR +.set UART_1_SCB_IRQ__INTC_MASK, 0x100 +.set UART_1_SCB_IRQ__INTC_NUMBER, 8 +.set UART_1_SCB_IRQ__INTC_PRIOR_MASK, 0xC0 +.set UART_1_SCB_IRQ__INTC_PRIOR_NUM, 0 +.set UART_1_SCB_IRQ__INTC_PRIOR_REG, CYREG_CM0P_IPR2 +.set UART_1_SCB_IRQ__INTC_SET_EN_REG, CYREG_CM0P_ISER +.set UART_1_SCB_IRQ__INTC_SET_PD_REG, CYREG_CM0P_ISPR +.set UART_1_SCBCLK__CTRL_REGISTER, CYREG_PERI_PCLK_CTL1 +.set UART_1_SCBCLK__DIV_ID, 0x00000041 +.set UART_1_SCBCLK__DIV_REGISTER, CYREG_PERI_DIV_16_CTL1 +.set UART_1_SCBCLK__PA_DIV_ID, 0x000000FF +.set UART_1_tx__0__DR, CYREG_GPIO_PRT3_DR +.set UART_1_tx__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR +.set UART_1_tx__0__DR_INV, CYREG_GPIO_PRT3_DR_INV +.set UART_1_tx__0__DR_SET, CYREG_GPIO_PRT3_DR_SET +.set UART_1_tx__0__HSIOM, CYREG_HSIOM_PORT_SEL3 +.set UART_1_tx__0__HSIOM_GPIO, 0 +.set UART_1_tx__0__HSIOM_I2C, 14 +.set UART_1_tx__0__HSIOM_I2C_SDA, 14 +.set UART_1_tx__0__HSIOM_MASK, 0x000000F0 +.set UART_1_tx__0__HSIOM_SHIFT, 4 +.set UART_1_tx__0__HSIOM_SPI, 15 +.set UART_1_tx__0__HSIOM_SPI_MISO, 15 +.set UART_1_tx__0__HSIOM_UART, 9 +.set UART_1_tx__0__HSIOM_UART_TX, 9 +.set UART_1_tx__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG +.set UART_1_tx__0__INTR, CYREG_GPIO_PRT3_INTR +.set UART_1_tx__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG +.set UART_1_tx__0__INTSTAT, CYREG_GPIO_PRT3_INTR +.set UART_1_tx__0__MASK, 0x02 +.set UART_1_tx__0__PC, CYREG_GPIO_PRT3_PC +.set UART_1_tx__0__PC2, CYREG_GPIO_PRT3_PC2 +.set UART_1_tx__0__PORT, 3 +.set UART_1_tx__0__PS, CYREG_GPIO_PRT3_PS +.set UART_1_tx__0__SHIFT, 1 +.set UART_1_tx__DR, CYREG_GPIO_PRT3_DR +.set UART_1_tx__DR_CLR, CYREG_GPIO_PRT3_DR_CLR +.set UART_1_tx__DR_INV, CYREG_GPIO_PRT3_DR_INV +.set UART_1_tx__DR_SET, CYREG_GPIO_PRT3_DR_SET +.set UART_1_tx__INTCFG, CYREG_GPIO_PRT3_INTR_CFG +.set UART_1_tx__INTR, CYREG_GPIO_PRT3_INTR +.set UART_1_tx__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG +.set UART_1_tx__INTSTAT, CYREG_GPIO_PRT3_INTR +.set UART_1_tx__MASK, 0x02 +.set UART_1_tx__PC, CYREG_GPIO_PRT3_PC +.set UART_1_tx__PC2, CYREG_GPIO_PRT3_PC2 +.set UART_1_tx__PORT, 3 +.set UART_1_tx__PS, CYREG_GPIO_PRT3_PS +.set UART_1_tx__SHIFT, 1 + +/* Miscellaneous */ +.set CYDEV_BCLK__HFCLK__HZ, 24000000 +.set CYDEV_BCLK__HFCLK__KHZ, 24000 +.set CYDEV_BCLK__HFCLK__MHZ, 24 +.set CYDEV_BCLK__SYSCLK__HZ, 24000000 +.set CYDEV_BCLK__SYSCLK__KHZ, 24000 +.set CYDEV_BCLK__SYSCLK__MHZ, 24 +.set CYDEV_CHIP_DIE_LEOPARD, 1 +.set CYDEV_CHIP_DIE_PSOC4A, 18 +.set CYDEV_CHIP_DIE_PSOC5LP, 2 +.set CYDEV_CHIP_DIE_PSOC5TM, 3 +.set CYDEV_CHIP_DIE_TMA4, 4 +.set CYDEV_CHIP_DIE_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_FM0P, 5 +.set CYDEV_CHIP_FAMILY_FM3, 6 +.set CYDEV_CHIP_FAMILY_FM4, 7 +.set CYDEV_CHIP_FAMILY_PSOC3, 1 +.set CYDEV_CHIP_FAMILY_PSOC4, 2 +.set CYDEV_CHIP_FAMILY_PSOC5, 3 +.set CYDEV_CHIP_FAMILY_PSOC6, 4 +.set CYDEV_CHIP_FAMILY_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC4 +.set CYDEV_CHIP_JTAG_ID, 0x256A11B5 +.set CYDEV_CHIP_MEMBER_3A, 1 +.set CYDEV_CHIP_MEMBER_4A, 18 +.set CYDEV_CHIP_MEMBER_4D, 13 +.set CYDEV_CHIP_MEMBER_4E, 6 +.set CYDEV_CHIP_MEMBER_4F, 19 +.set CYDEV_CHIP_MEMBER_4G, 4 +.set CYDEV_CHIP_MEMBER_4H, 17 +.set CYDEV_CHIP_MEMBER_4I, 23 +.set CYDEV_CHIP_MEMBER_4J, 14 +.set CYDEV_CHIP_MEMBER_4K, 15 +.set CYDEV_CHIP_MEMBER_4L, 22 +.set CYDEV_CHIP_MEMBER_4M, 21 +.set CYDEV_CHIP_MEMBER_4N, 10 +.set CYDEV_CHIP_MEMBER_4O, 7 +.set CYDEV_CHIP_MEMBER_4P, 20 +.set CYDEV_CHIP_MEMBER_4Q, 12 +.set CYDEV_CHIP_MEMBER_4R, 8 +.set CYDEV_CHIP_MEMBER_4S, 11 +.set CYDEV_CHIP_MEMBER_4T, 9 +.set CYDEV_CHIP_MEMBER_4U, 5 +.set CYDEV_CHIP_MEMBER_4V, 16 +.set CYDEV_CHIP_MEMBER_5A, 3 +.set CYDEV_CHIP_MEMBER_5B, 2 +.set CYDEV_CHIP_MEMBER_6A, 24 +.set CYDEV_CHIP_MEMBER_FM3, 28 +.set CYDEV_CHIP_MEMBER_FM4, 29 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 25 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 26 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 27 +.set CYDEV_CHIP_MEMBER_UNKNOWN, 0 +.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_4V +.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED +.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT +.set CYDEV_CHIP_REV_LEOPARD_ES1, 0 +.set CYDEV_CHIP_REV_LEOPARD_ES2, 1 +.set CYDEV_CHIP_REV_LEOPARD_ES3, 3 +.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 +.set CYDEV_CHIP_REV_PSOC4A_ES0, 17 +.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 +.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 +.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1 +.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1 +.set CYDEV_CHIP_REV_TMA4_ES, 17 +.set CYDEV_CHIP_REV_TMA4_ES2, 33 +.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_3A_ES1, 0 +.set CYDEV_CHIP_REVISION_3A_ES2, 1 +.set CYDEV_CHIP_REVISION_3A_ES3, 3 +.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 +.set CYDEV_CHIP_REVISION_4A_ES0, 17 +.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0 +.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0 +.set CYDEV_CHIP_REVISION_4G_ES, 17 +.set CYDEV_CHIP_REVISION_4G_ES2, 33 +.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_5A_ES0, 0 +.set CYDEV_CHIP_REVISION_5A_ES1, 1 +.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 +.set CYDEV_CHIP_REVISION_5B_ES0, 0 +.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_6A_ES, 17 +.set CYDEV_CHIP_REVISION_6A_NO_UDB, 33 +.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 33 +.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_4V_PRODUCTION +.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED +.set CYDEV_CONFIG_READ_ACCELERATOR, 1 +.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 +.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 +.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 +.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_Disallowed +.set CYDEV_CONFIGURATION_COMPRESSED, 1 +.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 +.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED +.set CYDEV_CONFIGURATION_MODE_DMA, 2 +.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 +.set CYDEV_DEBUG_PROTECT_KILL, 4 +.set CYDEV_DEBUG_PROTECT_OPEN, 1 +.set CYDEV_DEBUG_PROTECT_PROTECTED, 2 +.set CYDEV_DEBUG_PROTECT, CYDEV_DEBUG_PROTECT_PROTECTED +.set CYDEV_DEBUGGING_DPS_Disable, 3 +.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_Disable +.set CYDEV_DEBUGGING_DPS_SWD, 2 +.set CYDEV_DEBUGGING_ENABLE, 0 +.set CYDEV_DFT_SELECT_CLK0, 8 +.set CYDEV_DFT_SELECT_CLK1, 9 +.set CYDEV_DMA_CHANNELS_AVAILABLE, 8 +.set CYDEV_HEAP_SIZE, 0x1000 +.set CYDEV_IMO_TRIMMED_BY_USB, 0 +.set CYDEV_IMO_TRIMMED_BY_WCO, 0 +.set CYDEV_INTR_NUMBER_DMA, 14 +.set CYDEV_IS_EXPORTING_CODE, 0 +.set CYDEV_IS_IMPORTING_CODE, 0 +.set CYDEV_PROJ_TYPE, 2 +.set CYDEV_PROJ_TYPE_BOOTLOADER, 1 +.set CYDEV_PROJ_TYPE_LAUNCHER, 5 +.set CYDEV_PROJ_TYPE_LOADABLE, 2 +.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4 +.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 +.set CYDEV_PROJ_TYPE_STANDARD, 0 +.set CYDEV_STACK_SIZE, 0x0800 +.set CYDEV_USE_BUNDLED_CMSIS, 1 +.set CYDEV_VARIABLE_VDDA, 1 +.set CYDEV_VDDA_MV, 3300 +.set CYDEV_VDDD_MV, 3300 +.set CYDEV_WDT_GENERATE_ISR, 1 +.set CYIPBLOCK_m0s8cpussv3_VERSION, 1 +.set CYIPBLOCK_m0s8crypto_VERSION, 2 +.set CYIPBLOCK_m0s8csdv2_VERSION, 2 +.set CYIPBLOCK_m0s8exco_VERSION, 1 +.set CYIPBLOCK_m0s8ioss_VERSION, 1 +.set CYIPBLOCK_m0s8lcd_VERSION, 2 +.set CYIPBLOCK_m0s8lpcomp_VERSION, 2 +.set CYIPBLOCK_m0s8pass4a_VERSION, 1 +.set CYIPBLOCK_m0s8peri_VERSION, 1 +.set CYIPBLOCK_m0s8scb_VERSION, 2 +.set CYIPBLOCK_m0s8tcpwm_VERSION, 2 +.set CYIPBLOCK_m0s8wco_VERSION, 1 +.set CYIPBLOCK_s8srsslt_VERSION, 1 +.set DMA_CHANNELS_USED__MASK, 0 +.set CYDEV_BOOTLOADER_ENABLE, 0 +.endif diff --git a/cores/asr650x/projects/PSoC4/cyfitteriar.inc b/cores/asr650x/projects/PSoC4/cyfitteriar.inc new file mode 100644 index 00000000..cf75226e --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cyfitteriar.inc @@ -0,0 +1,576 @@ +; +; File Name: cyfitteriar.inc +; +; PSoC Creator 4.2 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#ifndef INCLUDED_CYFITTERIAR_INC +#define INCLUDED_CYFITTERIAR_INC + INCLUDE cydeviceiar_trm.inc + +/* SPI_1 */ +SPI_1_miso_m__0__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_miso_m__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_miso_m__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_miso_m__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_miso_m__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4 +SPI_1_miso_m__0__HSIOM_GPIO EQU 0 +SPI_1_miso_m__0__HSIOM_I2C EQU 14 +SPI_1_miso_m__0__HSIOM_I2C_SDA EQU 14 +SPI_1_miso_m__0__HSIOM_MASK EQU 0x000000F0 +SPI_1_miso_m__0__HSIOM_SHIFT EQU 4 +SPI_1_miso_m__0__HSIOM_SPI EQU 15 +SPI_1_miso_m__0__HSIOM_SPI_MISO EQU 15 +SPI_1_miso_m__0__HSIOM_UART EQU 9 +SPI_1_miso_m__0__HSIOM_UART_TX EQU 9 +SPI_1_miso_m__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_miso_m__0__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_miso_m__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_miso_m__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_miso_m__0__MASK EQU 0x02 +SPI_1_miso_m__0__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_miso_m__0__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_miso_m__0__PORT EQU 4 +SPI_1_miso_m__0__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_miso_m__0__SHIFT EQU 1 +SPI_1_miso_m__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_miso_m__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_miso_m__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_miso_m__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_miso_m__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_miso_m__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_miso_m__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_miso_m__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_miso_m__MASK EQU 0x02 +SPI_1_miso_m__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_miso_m__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_miso_m__PORT EQU 4 +SPI_1_miso_m__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_miso_m__SHIFT EQU 1 +SPI_1_mosi_m__0__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_mosi_m__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_mosi_m__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_mosi_m__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_mosi_m__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4 +SPI_1_mosi_m__0__HSIOM_GPIO EQU 0 +SPI_1_mosi_m__0__HSIOM_I2C EQU 14 +SPI_1_mosi_m__0__HSIOM_I2C_SCL EQU 14 +SPI_1_mosi_m__0__HSIOM_MASK EQU 0x0000000F +SPI_1_mosi_m__0__HSIOM_SHIFT EQU 0 +SPI_1_mosi_m__0__HSIOM_SPI EQU 15 +SPI_1_mosi_m__0__HSIOM_SPI_MOSI EQU 15 +SPI_1_mosi_m__0__HSIOM_UART EQU 9 +SPI_1_mosi_m__0__HSIOM_UART_RX EQU 9 +SPI_1_mosi_m__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_mosi_m__0__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_mosi_m__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_mosi_m__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_mosi_m__0__MASK EQU 0x01 +SPI_1_mosi_m__0__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_mosi_m__0__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_mosi_m__0__PORT EQU 4 +SPI_1_mosi_m__0__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_mosi_m__0__SHIFT EQU 0 +SPI_1_mosi_m__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_mosi_m__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_mosi_m__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_mosi_m__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_mosi_m__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_mosi_m__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_mosi_m__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_mosi_m__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_mosi_m__MASK EQU 0x01 +SPI_1_mosi_m__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_mosi_m__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_mosi_m__PORT EQU 4 +SPI_1_mosi_m__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_mosi_m__SHIFT EQU 0 +SPI_1_SCB__CTRL EQU CYREG_SCB0_CTRL +SPI_1_SCB__EZ_DATA0 EQU CYREG_SCB0_EZ_DATA0 +SPI_1_SCB__EZ_DATA1 EQU CYREG_SCB0_EZ_DATA1 +SPI_1_SCB__EZ_DATA10 EQU CYREG_SCB0_EZ_DATA10 +SPI_1_SCB__EZ_DATA11 EQU CYREG_SCB0_EZ_DATA11 +SPI_1_SCB__EZ_DATA12 EQU CYREG_SCB0_EZ_DATA12 +SPI_1_SCB__EZ_DATA13 EQU CYREG_SCB0_EZ_DATA13 +SPI_1_SCB__EZ_DATA14 EQU CYREG_SCB0_EZ_DATA14 +SPI_1_SCB__EZ_DATA15 EQU CYREG_SCB0_EZ_DATA15 +SPI_1_SCB__EZ_DATA16 EQU CYREG_SCB0_EZ_DATA16 +SPI_1_SCB__EZ_DATA17 EQU CYREG_SCB0_EZ_DATA17 +SPI_1_SCB__EZ_DATA18 EQU CYREG_SCB0_EZ_DATA18 +SPI_1_SCB__EZ_DATA19 EQU CYREG_SCB0_EZ_DATA19 +SPI_1_SCB__EZ_DATA2 EQU CYREG_SCB0_EZ_DATA2 +SPI_1_SCB__EZ_DATA20 EQU CYREG_SCB0_EZ_DATA20 +SPI_1_SCB__EZ_DATA21 EQU CYREG_SCB0_EZ_DATA21 +SPI_1_SCB__EZ_DATA22 EQU CYREG_SCB0_EZ_DATA22 +SPI_1_SCB__EZ_DATA23 EQU CYREG_SCB0_EZ_DATA23 +SPI_1_SCB__EZ_DATA24 EQU CYREG_SCB0_EZ_DATA24 +SPI_1_SCB__EZ_DATA25 EQU CYREG_SCB0_EZ_DATA25 +SPI_1_SCB__EZ_DATA26 EQU CYREG_SCB0_EZ_DATA26 +SPI_1_SCB__EZ_DATA27 EQU CYREG_SCB0_EZ_DATA27 +SPI_1_SCB__EZ_DATA28 EQU CYREG_SCB0_EZ_DATA28 +SPI_1_SCB__EZ_DATA29 EQU CYREG_SCB0_EZ_DATA29 +SPI_1_SCB__EZ_DATA3 EQU CYREG_SCB0_EZ_DATA3 +SPI_1_SCB__EZ_DATA30 EQU CYREG_SCB0_EZ_DATA30 +SPI_1_SCB__EZ_DATA31 EQU CYREG_SCB0_EZ_DATA31 +SPI_1_SCB__EZ_DATA4 EQU CYREG_SCB0_EZ_DATA4 +SPI_1_SCB__EZ_DATA5 EQU CYREG_SCB0_EZ_DATA5 +SPI_1_SCB__EZ_DATA6 EQU CYREG_SCB0_EZ_DATA6 +SPI_1_SCB__EZ_DATA7 EQU CYREG_SCB0_EZ_DATA7 +SPI_1_SCB__EZ_DATA8 EQU CYREG_SCB0_EZ_DATA8 +SPI_1_SCB__EZ_DATA9 EQU CYREG_SCB0_EZ_DATA9 +SPI_1_SCB__I2C_CFG EQU CYREG_SCB0_I2C_CFG +SPI_1_SCB__I2C_CTRL EQU CYREG_SCB0_I2C_CTRL +SPI_1_SCB__I2C_M_CMD EQU CYREG_SCB0_I2C_M_CMD +SPI_1_SCB__I2C_S_CMD EQU CYREG_SCB0_I2C_S_CMD +SPI_1_SCB__I2C_STATUS EQU CYREG_SCB0_I2C_STATUS +SPI_1_SCB__INTR_CAUSE EQU CYREG_SCB0_INTR_CAUSE +SPI_1_SCB__INTR_I2C_EC EQU CYREG_SCB0_INTR_I2C_EC +SPI_1_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB0_INTR_I2C_EC_MASK +SPI_1_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB0_INTR_I2C_EC_MASKED +SPI_1_SCB__INTR_M EQU CYREG_SCB0_INTR_M +SPI_1_SCB__INTR_M_MASK EQU CYREG_SCB0_INTR_M_MASK +SPI_1_SCB__INTR_M_MASKED EQU CYREG_SCB0_INTR_M_MASKED +SPI_1_SCB__INTR_M_SET EQU CYREG_SCB0_INTR_M_SET +SPI_1_SCB__INTR_RX EQU CYREG_SCB0_INTR_RX +SPI_1_SCB__INTR_RX_MASK EQU CYREG_SCB0_INTR_RX_MASK +SPI_1_SCB__INTR_RX_MASKED EQU CYREG_SCB0_INTR_RX_MASKED +SPI_1_SCB__INTR_RX_SET EQU CYREG_SCB0_INTR_RX_SET +SPI_1_SCB__INTR_S EQU CYREG_SCB0_INTR_S +SPI_1_SCB__INTR_S_MASK EQU CYREG_SCB0_INTR_S_MASK +SPI_1_SCB__INTR_S_MASKED EQU CYREG_SCB0_INTR_S_MASKED +SPI_1_SCB__INTR_S_SET EQU CYREG_SCB0_INTR_S_SET +SPI_1_SCB__INTR_SPI_EC EQU CYREG_SCB0_INTR_SPI_EC +SPI_1_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB0_INTR_SPI_EC_MASK +SPI_1_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB0_INTR_SPI_EC_MASKED +SPI_1_SCB__INTR_TX EQU CYREG_SCB0_INTR_TX +SPI_1_SCB__INTR_TX_MASK EQU CYREG_SCB0_INTR_TX_MASK +SPI_1_SCB__INTR_TX_MASKED EQU CYREG_SCB0_INTR_TX_MASKED +SPI_1_SCB__INTR_TX_SET EQU CYREG_SCB0_INTR_TX_SET +SPI_1_SCB__RX_CTRL EQU CYREG_SCB0_RX_CTRL +SPI_1_SCB__RX_FIFO_CTRL EQU CYREG_SCB0_RX_FIFO_CTRL +SPI_1_SCB__RX_FIFO_RD EQU CYREG_SCB0_RX_FIFO_RD +SPI_1_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB0_RX_FIFO_RD_SILENT +SPI_1_SCB__RX_FIFO_STATUS EQU CYREG_SCB0_RX_FIFO_STATUS +SPI_1_SCB__RX_MATCH EQU CYREG_SCB0_RX_MATCH +SPI_1_SCB__SPI_CTRL EQU CYREG_SCB0_SPI_CTRL +SPI_1_SCB__SPI_STATUS EQU CYREG_SCB0_SPI_STATUS +SPI_1_SCB__SS0_POSISTION EQU 0 +SPI_1_SCB__SS1_POSISTION EQU 1 +SPI_1_SCB__SS2_POSISTION EQU 2 +SPI_1_SCB__SS3_POSISTION EQU 3 +SPI_1_SCB__STATUS EQU CYREG_SCB0_STATUS +SPI_1_SCB__TX_CTRL EQU CYREG_SCB0_TX_CTRL +SPI_1_SCB__TX_FIFO_CTRL EQU CYREG_SCB0_TX_FIFO_CTRL +SPI_1_SCB__TX_FIFO_STATUS EQU CYREG_SCB0_TX_FIFO_STATUS +SPI_1_SCB__TX_FIFO_WR EQU CYREG_SCB0_TX_FIFO_WR +SPI_1_SCB__UART_CTRL EQU CYREG_SCB0_UART_CTRL +SPI_1_SCB__UART_FLOW_CTRL EQU CYREG_SCB0_UART_FLOW_CTRL +SPI_1_SCB__UART_RX_CTRL EQU CYREG_SCB0_UART_RX_CTRL +SPI_1_SCB__UART_RX_STATUS EQU CYREG_SCB0_UART_RX_STATUS +SPI_1_SCB__UART_TX_CTRL EQU CYREG_SCB0_UART_TX_CTRL +SPI_1_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL0 +SPI_1_SCBCLK__DIV_ID EQU 0x00000040 +SPI_1_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL0 +SPI_1_SCBCLK__PA_DIV_ID EQU 0x000000FF +SPI_1_sclk_m__0__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_sclk_m__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_sclk_m__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_sclk_m__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_sclk_m__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4 +SPI_1_sclk_m__0__HSIOM_GPIO EQU 0 +SPI_1_sclk_m__0__HSIOM_MASK EQU 0x00000F00 +SPI_1_sclk_m__0__HSIOM_SHIFT EQU 8 +SPI_1_sclk_m__0__HSIOM_SPI EQU 15 +SPI_1_sclk_m__0__HSIOM_SPI_CLK EQU 15 +SPI_1_sclk_m__0__HSIOM_UART EQU 9 +SPI_1_sclk_m__0__HSIOM_UART_CTS EQU 9 +SPI_1_sclk_m__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_sclk_m__0__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_sclk_m__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_sclk_m__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_sclk_m__0__MASK EQU 0x04 +SPI_1_sclk_m__0__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_sclk_m__0__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_sclk_m__0__PORT EQU 4 +SPI_1_sclk_m__0__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_sclk_m__0__SHIFT EQU 2 +SPI_1_sclk_m__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_sclk_m__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_sclk_m__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_sclk_m__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_sclk_m__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_sclk_m__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_sclk_m__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_sclk_m__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_sclk_m__MASK EQU 0x04 +SPI_1_sclk_m__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_sclk_m__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_sclk_m__PORT EQU 4 +SPI_1_sclk_m__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_sclk_m__SHIFT EQU 2 + +/* UART_1 */ +UART_1_rx_wake__0__DR EQU CYREG_GPIO_PRT3_DR +UART_1_rx_wake__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR +UART_1_rx_wake__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV +UART_1_rx_wake__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET +UART_1_rx_wake__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3 +UART_1_rx_wake__0__HSIOM_GPIO EQU 0 +UART_1_rx_wake__0__HSIOM_I2C EQU 14 +UART_1_rx_wake__0__HSIOM_I2C_SCL EQU 14 +UART_1_rx_wake__0__HSIOM_MASK EQU 0x0000000F +UART_1_rx_wake__0__HSIOM_SHIFT EQU 0 +UART_1_rx_wake__0__HSIOM_SPI EQU 15 +UART_1_rx_wake__0__HSIOM_SPI_MOSI EQU 15 +UART_1_rx_wake__0__HSIOM_UART EQU 9 +UART_1_rx_wake__0__HSIOM_UART_RX EQU 9 +UART_1_rx_wake__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_rx_wake__0__INTR EQU CYREG_GPIO_PRT3_INTR +UART_1_rx_wake__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_rx_wake__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR +UART_1_rx_wake__0__MASK EQU 0x01 +UART_1_rx_wake__0__PC EQU CYREG_GPIO_PRT3_PC +UART_1_rx_wake__0__PC2 EQU CYREG_GPIO_PRT3_PC2 +UART_1_rx_wake__0__PORT EQU 3 +UART_1_rx_wake__0__PS EQU CYREG_GPIO_PRT3_PS +UART_1_rx_wake__0__SHIFT EQU 0 +UART_1_rx_wake__DR EQU CYREG_GPIO_PRT3_DR +UART_1_rx_wake__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR +UART_1_rx_wake__DR_INV EQU CYREG_GPIO_PRT3_DR_INV +UART_1_rx_wake__DR_SET EQU CYREG_GPIO_PRT3_DR_SET +UART_1_rx_wake__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_rx_wake__INTR EQU CYREG_GPIO_PRT3_INTR +UART_1_rx_wake__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_rx_wake__INTSTAT EQU CYREG_GPIO_PRT3_INTR +UART_1_rx_wake__MASK EQU 0x01 +UART_1_rx_wake__PC EQU CYREG_GPIO_PRT3_PC +UART_1_rx_wake__PC2 EQU CYREG_GPIO_PRT3_PC2 +UART_1_rx_wake__PORT EQU 3 +UART_1_rx_wake__PS EQU CYREG_GPIO_PRT3_PS +UART_1_rx_wake__SHIFT EQU 0 +UART_1_rx_wake__SNAP EQU CYREG_GPIO_PRT3_INTR +UART_1_RX_WAKEUP_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER +UART_1_RX_WAKEUP_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR +UART_1_RX_WAKEUP_IRQ__INTC_MASK EQU 0x08 +UART_1_RX_WAKEUP_IRQ__INTC_NUMBER EQU 3 +UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_MASK EQU 0xC0000000 +UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_NUM EQU 3 +UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_REG EQU CYREG_CM0P_IPR0 +UART_1_RX_WAKEUP_IRQ__INTC_SET_EN_REG EQU CYREG_CM0P_ISER +UART_1_RX_WAKEUP_IRQ__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR +UART_1_SCB__CTRL EQU CYREG_SCB1_CTRL +UART_1_SCB__EZ_DATA0 EQU CYREG_SCB1_EZ_DATA0 +UART_1_SCB__EZ_DATA1 EQU CYREG_SCB1_EZ_DATA1 +UART_1_SCB__EZ_DATA10 EQU CYREG_SCB1_EZ_DATA10 +UART_1_SCB__EZ_DATA11 EQU CYREG_SCB1_EZ_DATA11 +UART_1_SCB__EZ_DATA12 EQU CYREG_SCB1_EZ_DATA12 +UART_1_SCB__EZ_DATA13 EQU CYREG_SCB1_EZ_DATA13 +UART_1_SCB__EZ_DATA14 EQU CYREG_SCB1_EZ_DATA14 +UART_1_SCB__EZ_DATA15 EQU CYREG_SCB1_EZ_DATA15 +UART_1_SCB__EZ_DATA16 EQU CYREG_SCB1_EZ_DATA16 +UART_1_SCB__EZ_DATA17 EQU CYREG_SCB1_EZ_DATA17 +UART_1_SCB__EZ_DATA18 EQU CYREG_SCB1_EZ_DATA18 +UART_1_SCB__EZ_DATA19 EQU CYREG_SCB1_EZ_DATA19 +UART_1_SCB__EZ_DATA2 EQU CYREG_SCB1_EZ_DATA2 +UART_1_SCB__EZ_DATA20 EQU CYREG_SCB1_EZ_DATA20 +UART_1_SCB__EZ_DATA21 EQU CYREG_SCB1_EZ_DATA21 +UART_1_SCB__EZ_DATA22 EQU CYREG_SCB1_EZ_DATA22 +UART_1_SCB__EZ_DATA23 EQU CYREG_SCB1_EZ_DATA23 +UART_1_SCB__EZ_DATA24 EQU CYREG_SCB1_EZ_DATA24 +UART_1_SCB__EZ_DATA25 EQU CYREG_SCB1_EZ_DATA25 +UART_1_SCB__EZ_DATA26 EQU CYREG_SCB1_EZ_DATA26 +UART_1_SCB__EZ_DATA27 EQU CYREG_SCB1_EZ_DATA27 +UART_1_SCB__EZ_DATA28 EQU CYREG_SCB1_EZ_DATA28 +UART_1_SCB__EZ_DATA29 EQU CYREG_SCB1_EZ_DATA29 +UART_1_SCB__EZ_DATA3 EQU CYREG_SCB1_EZ_DATA3 +UART_1_SCB__EZ_DATA30 EQU CYREG_SCB1_EZ_DATA30 +UART_1_SCB__EZ_DATA31 EQU CYREG_SCB1_EZ_DATA31 +UART_1_SCB__EZ_DATA4 EQU CYREG_SCB1_EZ_DATA4 +UART_1_SCB__EZ_DATA5 EQU CYREG_SCB1_EZ_DATA5 +UART_1_SCB__EZ_DATA6 EQU CYREG_SCB1_EZ_DATA6 +UART_1_SCB__EZ_DATA7 EQU CYREG_SCB1_EZ_DATA7 +UART_1_SCB__EZ_DATA8 EQU CYREG_SCB1_EZ_DATA8 +UART_1_SCB__EZ_DATA9 EQU CYREG_SCB1_EZ_DATA9 +UART_1_SCB__I2C_CFG EQU CYREG_SCB1_I2C_CFG +UART_1_SCB__I2C_CTRL EQU CYREG_SCB1_I2C_CTRL +UART_1_SCB__I2C_M_CMD EQU CYREG_SCB1_I2C_M_CMD +UART_1_SCB__I2C_S_CMD EQU CYREG_SCB1_I2C_S_CMD +UART_1_SCB__I2C_STATUS EQU CYREG_SCB1_I2C_STATUS +UART_1_SCB__INTR_CAUSE EQU CYREG_SCB1_INTR_CAUSE +UART_1_SCB__INTR_I2C_EC EQU CYREG_SCB1_INTR_I2C_EC +UART_1_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB1_INTR_I2C_EC_MASK +UART_1_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB1_INTR_I2C_EC_MASKED +UART_1_SCB__INTR_M EQU CYREG_SCB1_INTR_M +UART_1_SCB__INTR_M_MASK EQU CYREG_SCB1_INTR_M_MASK +UART_1_SCB__INTR_M_MASKED EQU CYREG_SCB1_INTR_M_MASKED +UART_1_SCB__INTR_M_SET EQU CYREG_SCB1_INTR_M_SET +UART_1_SCB__INTR_RX EQU CYREG_SCB1_INTR_RX +UART_1_SCB__INTR_RX_MASK EQU CYREG_SCB1_INTR_RX_MASK +UART_1_SCB__INTR_RX_MASKED EQU CYREG_SCB1_INTR_RX_MASKED +UART_1_SCB__INTR_RX_SET EQU CYREG_SCB1_INTR_RX_SET +UART_1_SCB__INTR_S EQU CYREG_SCB1_INTR_S +UART_1_SCB__INTR_S_MASK EQU CYREG_SCB1_INTR_S_MASK +UART_1_SCB__INTR_S_MASKED EQU CYREG_SCB1_INTR_S_MASKED +UART_1_SCB__INTR_S_SET EQU CYREG_SCB1_INTR_S_SET +UART_1_SCB__INTR_SPI_EC EQU CYREG_SCB1_INTR_SPI_EC +UART_1_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB1_INTR_SPI_EC_MASK +UART_1_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB1_INTR_SPI_EC_MASKED +UART_1_SCB__INTR_TX EQU CYREG_SCB1_INTR_TX +UART_1_SCB__INTR_TX_MASK EQU CYREG_SCB1_INTR_TX_MASK +UART_1_SCB__INTR_TX_MASKED EQU CYREG_SCB1_INTR_TX_MASKED +UART_1_SCB__INTR_TX_SET EQU CYREG_SCB1_INTR_TX_SET +UART_1_SCB__RX_CTRL EQU CYREG_SCB1_RX_CTRL +UART_1_SCB__RX_FIFO_CTRL EQU CYREG_SCB1_RX_FIFO_CTRL +UART_1_SCB__RX_FIFO_RD EQU CYREG_SCB1_RX_FIFO_RD +UART_1_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB1_RX_FIFO_RD_SILENT +UART_1_SCB__RX_FIFO_STATUS EQU CYREG_SCB1_RX_FIFO_STATUS +UART_1_SCB__RX_MATCH EQU CYREG_SCB1_RX_MATCH +UART_1_SCB__SPI_CTRL EQU CYREG_SCB1_SPI_CTRL +UART_1_SCB__SPI_STATUS EQU CYREG_SCB1_SPI_STATUS +UART_1_SCB__SS0_POSISTION EQU 0 +UART_1_SCB__SS1_POSISTION EQU 1 +UART_1_SCB__SS2_POSISTION EQU 2 +UART_1_SCB__SS3_POSISTION EQU 3 +UART_1_SCB__STATUS EQU CYREG_SCB1_STATUS +UART_1_SCB__TX_CTRL EQU CYREG_SCB1_TX_CTRL +UART_1_SCB__TX_FIFO_CTRL EQU CYREG_SCB1_TX_FIFO_CTRL +UART_1_SCB__TX_FIFO_STATUS EQU CYREG_SCB1_TX_FIFO_STATUS +UART_1_SCB__TX_FIFO_WR EQU CYREG_SCB1_TX_FIFO_WR +UART_1_SCB__UART_CTRL EQU CYREG_SCB1_UART_CTRL +UART_1_SCB__UART_FLOW_CTRL EQU CYREG_SCB1_UART_FLOW_CTRL +UART_1_SCB__UART_RX_CTRL EQU CYREG_SCB1_UART_RX_CTRL +UART_1_SCB__UART_RX_STATUS EQU CYREG_SCB1_UART_RX_STATUS +UART_1_SCB__UART_TX_CTRL EQU CYREG_SCB1_UART_TX_CTRL +UART_1_SCB_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER +UART_1_SCB_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR +UART_1_SCB_IRQ__INTC_MASK EQU 0x100 +UART_1_SCB_IRQ__INTC_NUMBER EQU 8 +UART_1_SCB_IRQ__INTC_PRIOR_MASK EQU 0xC0 +UART_1_SCB_IRQ__INTC_PRIOR_NUM EQU 0 +UART_1_SCB_IRQ__INTC_PRIOR_REG EQU CYREG_CM0P_IPR2 +UART_1_SCB_IRQ__INTC_SET_EN_REG EQU CYREG_CM0P_ISER +UART_1_SCB_IRQ__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR +UART_1_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL1 +UART_1_SCBCLK__DIV_ID EQU 0x00000041 +UART_1_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL1 +UART_1_SCBCLK__PA_DIV_ID EQU 0x000000FF +UART_1_tx__0__DR EQU CYREG_GPIO_PRT3_DR +UART_1_tx__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR +UART_1_tx__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV +UART_1_tx__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET +UART_1_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3 +UART_1_tx__0__HSIOM_GPIO EQU 0 +UART_1_tx__0__HSIOM_I2C EQU 14 +UART_1_tx__0__HSIOM_I2C_SDA EQU 14 +UART_1_tx__0__HSIOM_MASK EQU 0x000000F0 +UART_1_tx__0__HSIOM_SHIFT EQU 4 +UART_1_tx__0__HSIOM_SPI EQU 15 +UART_1_tx__0__HSIOM_SPI_MISO EQU 15 +UART_1_tx__0__HSIOM_UART EQU 9 +UART_1_tx__0__HSIOM_UART_TX EQU 9 +UART_1_tx__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_tx__0__INTR EQU CYREG_GPIO_PRT3_INTR +UART_1_tx__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_tx__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR +UART_1_tx__0__MASK EQU 0x02 +UART_1_tx__0__PC EQU CYREG_GPIO_PRT3_PC +UART_1_tx__0__PC2 EQU CYREG_GPIO_PRT3_PC2 +UART_1_tx__0__PORT EQU 3 +UART_1_tx__0__PS EQU CYREG_GPIO_PRT3_PS +UART_1_tx__0__SHIFT EQU 1 +UART_1_tx__DR EQU CYREG_GPIO_PRT3_DR +UART_1_tx__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR +UART_1_tx__DR_INV EQU CYREG_GPIO_PRT3_DR_INV +UART_1_tx__DR_SET EQU CYREG_GPIO_PRT3_DR_SET +UART_1_tx__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_tx__INTR EQU CYREG_GPIO_PRT3_INTR +UART_1_tx__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_tx__INTSTAT EQU CYREG_GPIO_PRT3_INTR +UART_1_tx__MASK EQU 0x02 +UART_1_tx__PC EQU CYREG_GPIO_PRT3_PC +UART_1_tx__PC2 EQU CYREG_GPIO_PRT3_PC2 +UART_1_tx__PORT EQU 3 +UART_1_tx__PS EQU CYREG_GPIO_PRT3_PS +UART_1_tx__SHIFT EQU 1 + +/* Miscellaneous */ +CYDEV_BCLK__HFCLK__HZ EQU 24000000 +CYDEV_BCLK__HFCLK__KHZ EQU 24000 +CYDEV_BCLK__HFCLK__MHZ EQU 24 +CYDEV_BCLK__SYSCLK__HZ EQU 24000000 +CYDEV_BCLK__SYSCLK__KHZ EQU 24000 +CYDEV_BCLK__SYSCLK__MHZ EQU 24 +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4 +CYDEV_CHIP_JTAG_ID EQU 0x256A11B5 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4V +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 +CYDEV_CHIP_REV_TMA4_ES EQU 17 +CYDEV_CHIP_REV_TMA4_ES2 EQU 33 +CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 +CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0 +CYDEV_CHIP_REVISION_4G_ES EQU 17 +CYDEV_CHIP_REVISION_4G_ES2 EQU 33 +CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4V_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED +CYDEV_CONFIG_READ_ACCELERATOR EQU 1 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_Disallowed +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_DEBUG_PROTECT_KILL EQU 4 +CYDEV_DEBUG_PROTECT_OPEN EQU 1 +CYDEV_DEBUG_PROTECT_PROTECTED EQU 2 +CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_PROTECTED +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_Disable +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_ENABLE EQU 0 +CYDEV_DFT_SELECT_CLK0 EQU 8 +CYDEV_DFT_SELECT_CLK1 EQU 9 +CYDEV_DMA_CHANNELS_AVAILABLE EQU 8 +CYDEV_HEAP_SIZE EQU 0x1000 +CYDEV_IMO_TRIMMED_BY_USB EQU 0 +CYDEV_IMO_TRIMMED_BY_WCO EQU 0 +CYDEV_INTR_NUMBER_DMA EQU 14 +CYDEV_IS_EXPORTING_CODE EQU 0 +CYDEV_IS_IMPORTING_CODE EQU 0 +CYDEV_PROJ_TYPE EQU 2 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LAUNCHER EQU 5 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_STACK_SIZE EQU 0x0800 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 1 +CYDEV_VDDA_MV EQU 3300 +CYDEV_VDDD_MV EQU 3300 +CYDEV_WDT_GENERATE_ISR EQU 1 +CYIPBLOCK_m0s8cpussv3_VERSION EQU 1 +CYIPBLOCK_m0s8crypto_VERSION EQU 2 +CYIPBLOCK_m0s8csdv2_VERSION EQU 2 +CYIPBLOCK_m0s8exco_VERSION EQU 1 +CYIPBLOCK_m0s8ioss_VERSION EQU 1 +CYIPBLOCK_m0s8lcd_VERSION EQU 2 +CYIPBLOCK_m0s8lpcomp_VERSION EQU 2 +CYIPBLOCK_m0s8pass4a_VERSION EQU 1 +CYIPBLOCK_m0s8peri_VERSION EQU 1 +CYIPBLOCK_m0s8scb_VERSION EQU 2 +CYIPBLOCK_m0s8tcpwm_VERSION EQU 2 +CYIPBLOCK_m0s8wco_VERSION EQU 1 +CYIPBLOCK_s8srsslt_VERSION EQU 1 +DMA_CHANNELS_USED__MASK EQU 0 +CYDEV_BOOTLOADER_ENABLE EQU 0 + +#endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/cores/asr650x/projects/PSoC4/cyfitterrv.inc b/cores/asr650x/projects/PSoC4/cyfitterrv.inc new file mode 100644 index 00000000..fe8e531a --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cyfitterrv.inc @@ -0,0 +1,576 @@ +; +; File Name: cyfitterrv.inc +; +; PSoC Creator 4.2 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC +INCLUDED_CYFITTERRV_INC EQU 1 + GET cydevicerv_trm.inc + +; SPI_1 +SPI_1_miso_m__0__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_miso_m__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_miso_m__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_miso_m__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_miso_m__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4 +SPI_1_miso_m__0__HSIOM_GPIO EQU 0 +SPI_1_miso_m__0__HSIOM_I2C EQU 14 +SPI_1_miso_m__0__HSIOM_I2C_SDA EQU 14 +SPI_1_miso_m__0__HSIOM_MASK EQU 0x000000F0 +SPI_1_miso_m__0__HSIOM_SHIFT EQU 4 +SPI_1_miso_m__0__HSIOM_SPI EQU 15 +SPI_1_miso_m__0__HSIOM_SPI_MISO EQU 15 +SPI_1_miso_m__0__HSIOM_UART EQU 9 +SPI_1_miso_m__0__HSIOM_UART_TX EQU 9 +SPI_1_miso_m__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_miso_m__0__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_miso_m__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_miso_m__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_miso_m__0__MASK EQU 0x02 +SPI_1_miso_m__0__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_miso_m__0__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_miso_m__0__PORT EQU 4 +SPI_1_miso_m__0__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_miso_m__0__SHIFT EQU 1 +SPI_1_miso_m__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_miso_m__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_miso_m__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_miso_m__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_miso_m__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_miso_m__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_miso_m__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_miso_m__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_miso_m__MASK EQU 0x02 +SPI_1_miso_m__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_miso_m__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_miso_m__PORT EQU 4 +SPI_1_miso_m__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_miso_m__SHIFT EQU 1 +SPI_1_mosi_m__0__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_mosi_m__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_mosi_m__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_mosi_m__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_mosi_m__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4 +SPI_1_mosi_m__0__HSIOM_GPIO EQU 0 +SPI_1_mosi_m__0__HSIOM_I2C EQU 14 +SPI_1_mosi_m__0__HSIOM_I2C_SCL EQU 14 +SPI_1_mosi_m__0__HSIOM_MASK EQU 0x0000000F +SPI_1_mosi_m__0__HSIOM_SHIFT EQU 0 +SPI_1_mosi_m__0__HSIOM_SPI EQU 15 +SPI_1_mosi_m__0__HSIOM_SPI_MOSI EQU 15 +SPI_1_mosi_m__0__HSIOM_UART EQU 9 +SPI_1_mosi_m__0__HSIOM_UART_RX EQU 9 +SPI_1_mosi_m__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_mosi_m__0__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_mosi_m__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_mosi_m__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_mosi_m__0__MASK EQU 0x01 +SPI_1_mosi_m__0__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_mosi_m__0__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_mosi_m__0__PORT EQU 4 +SPI_1_mosi_m__0__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_mosi_m__0__SHIFT EQU 0 +SPI_1_mosi_m__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_mosi_m__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_mosi_m__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_mosi_m__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_mosi_m__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_mosi_m__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_mosi_m__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_mosi_m__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_mosi_m__MASK EQU 0x01 +SPI_1_mosi_m__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_mosi_m__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_mosi_m__PORT EQU 4 +SPI_1_mosi_m__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_mosi_m__SHIFT EQU 0 +SPI_1_SCB__CTRL EQU CYREG_SCB0_CTRL +SPI_1_SCB__EZ_DATA0 EQU CYREG_SCB0_EZ_DATA0 +SPI_1_SCB__EZ_DATA1 EQU CYREG_SCB0_EZ_DATA1 +SPI_1_SCB__EZ_DATA10 EQU CYREG_SCB0_EZ_DATA10 +SPI_1_SCB__EZ_DATA11 EQU CYREG_SCB0_EZ_DATA11 +SPI_1_SCB__EZ_DATA12 EQU CYREG_SCB0_EZ_DATA12 +SPI_1_SCB__EZ_DATA13 EQU CYREG_SCB0_EZ_DATA13 +SPI_1_SCB__EZ_DATA14 EQU CYREG_SCB0_EZ_DATA14 +SPI_1_SCB__EZ_DATA15 EQU CYREG_SCB0_EZ_DATA15 +SPI_1_SCB__EZ_DATA16 EQU CYREG_SCB0_EZ_DATA16 +SPI_1_SCB__EZ_DATA17 EQU CYREG_SCB0_EZ_DATA17 +SPI_1_SCB__EZ_DATA18 EQU CYREG_SCB0_EZ_DATA18 +SPI_1_SCB__EZ_DATA19 EQU CYREG_SCB0_EZ_DATA19 +SPI_1_SCB__EZ_DATA2 EQU CYREG_SCB0_EZ_DATA2 +SPI_1_SCB__EZ_DATA20 EQU CYREG_SCB0_EZ_DATA20 +SPI_1_SCB__EZ_DATA21 EQU CYREG_SCB0_EZ_DATA21 +SPI_1_SCB__EZ_DATA22 EQU CYREG_SCB0_EZ_DATA22 +SPI_1_SCB__EZ_DATA23 EQU CYREG_SCB0_EZ_DATA23 +SPI_1_SCB__EZ_DATA24 EQU CYREG_SCB0_EZ_DATA24 +SPI_1_SCB__EZ_DATA25 EQU CYREG_SCB0_EZ_DATA25 +SPI_1_SCB__EZ_DATA26 EQU CYREG_SCB0_EZ_DATA26 +SPI_1_SCB__EZ_DATA27 EQU CYREG_SCB0_EZ_DATA27 +SPI_1_SCB__EZ_DATA28 EQU CYREG_SCB0_EZ_DATA28 +SPI_1_SCB__EZ_DATA29 EQU CYREG_SCB0_EZ_DATA29 +SPI_1_SCB__EZ_DATA3 EQU CYREG_SCB0_EZ_DATA3 +SPI_1_SCB__EZ_DATA30 EQU CYREG_SCB0_EZ_DATA30 +SPI_1_SCB__EZ_DATA31 EQU CYREG_SCB0_EZ_DATA31 +SPI_1_SCB__EZ_DATA4 EQU CYREG_SCB0_EZ_DATA4 +SPI_1_SCB__EZ_DATA5 EQU CYREG_SCB0_EZ_DATA5 +SPI_1_SCB__EZ_DATA6 EQU CYREG_SCB0_EZ_DATA6 +SPI_1_SCB__EZ_DATA7 EQU CYREG_SCB0_EZ_DATA7 +SPI_1_SCB__EZ_DATA8 EQU CYREG_SCB0_EZ_DATA8 +SPI_1_SCB__EZ_DATA9 EQU CYREG_SCB0_EZ_DATA9 +SPI_1_SCB__I2C_CFG EQU CYREG_SCB0_I2C_CFG +SPI_1_SCB__I2C_CTRL EQU CYREG_SCB0_I2C_CTRL +SPI_1_SCB__I2C_M_CMD EQU CYREG_SCB0_I2C_M_CMD +SPI_1_SCB__I2C_S_CMD EQU CYREG_SCB0_I2C_S_CMD +SPI_1_SCB__I2C_STATUS EQU CYREG_SCB0_I2C_STATUS +SPI_1_SCB__INTR_CAUSE EQU CYREG_SCB0_INTR_CAUSE +SPI_1_SCB__INTR_I2C_EC EQU CYREG_SCB0_INTR_I2C_EC +SPI_1_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB0_INTR_I2C_EC_MASK +SPI_1_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB0_INTR_I2C_EC_MASKED +SPI_1_SCB__INTR_M EQU CYREG_SCB0_INTR_M +SPI_1_SCB__INTR_M_MASK EQU CYREG_SCB0_INTR_M_MASK +SPI_1_SCB__INTR_M_MASKED EQU CYREG_SCB0_INTR_M_MASKED +SPI_1_SCB__INTR_M_SET EQU CYREG_SCB0_INTR_M_SET +SPI_1_SCB__INTR_RX EQU CYREG_SCB0_INTR_RX +SPI_1_SCB__INTR_RX_MASK EQU CYREG_SCB0_INTR_RX_MASK +SPI_1_SCB__INTR_RX_MASKED EQU CYREG_SCB0_INTR_RX_MASKED +SPI_1_SCB__INTR_RX_SET EQU CYREG_SCB0_INTR_RX_SET +SPI_1_SCB__INTR_S EQU CYREG_SCB0_INTR_S +SPI_1_SCB__INTR_S_MASK EQU CYREG_SCB0_INTR_S_MASK +SPI_1_SCB__INTR_S_MASKED EQU CYREG_SCB0_INTR_S_MASKED +SPI_1_SCB__INTR_S_SET EQU CYREG_SCB0_INTR_S_SET +SPI_1_SCB__INTR_SPI_EC EQU CYREG_SCB0_INTR_SPI_EC +SPI_1_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB0_INTR_SPI_EC_MASK +SPI_1_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB0_INTR_SPI_EC_MASKED +SPI_1_SCB__INTR_TX EQU CYREG_SCB0_INTR_TX +SPI_1_SCB__INTR_TX_MASK EQU CYREG_SCB0_INTR_TX_MASK +SPI_1_SCB__INTR_TX_MASKED EQU CYREG_SCB0_INTR_TX_MASKED +SPI_1_SCB__INTR_TX_SET EQU CYREG_SCB0_INTR_TX_SET +SPI_1_SCB__RX_CTRL EQU CYREG_SCB0_RX_CTRL +SPI_1_SCB__RX_FIFO_CTRL EQU CYREG_SCB0_RX_FIFO_CTRL +SPI_1_SCB__RX_FIFO_RD EQU CYREG_SCB0_RX_FIFO_RD +SPI_1_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB0_RX_FIFO_RD_SILENT +SPI_1_SCB__RX_FIFO_STATUS EQU CYREG_SCB0_RX_FIFO_STATUS +SPI_1_SCB__RX_MATCH EQU CYREG_SCB0_RX_MATCH +SPI_1_SCB__SPI_CTRL EQU CYREG_SCB0_SPI_CTRL +SPI_1_SCB__SPI_STATUS EQU CYREG_SCB0_SPI_STATUS +SPI_1_SCB__SS0_POSISTION EQU 0 +SPI_1_SCB__SS1_POSISTION EQU 1 +SPI_1_SCB__SS2_POSISTION EQU 2 +SPI_1_SCB__SS3_POSISTION EQU 3 +SPI_1_SCB__STATUS EQU CYREG_SCB0_STATUS +SPI_1_SCB__TX_CTRL EQU CYREG_SCB0_TX_CTRL +SPI_1_SCB__TX_FIFO_CTRL EQU CYREG_SCB0_TX_FIFO_CTRL +SPI_1_SCB__TX_FIFO_STATUS EQU CYREG_SCB0_TX_FIFO_STATUS +SPI_1_SCB__TX_FIFO_WR EQU CYREG_SCB0_TX_FIFO_WR +SPI_1_SCB__UART_CTRL EQU CYREG_SCB0_UART_CTRL +SPI_1_SCB__UART_FLOW_CTRL EQU CYREG_SCB0_UART_FLOW_CTRL +SPI_1_SCB__UART_RX_CTRL EQU CYREG_SCB0_UART_RX_CTRL +SPI_1_SCB__UART_RX_STATUS EQU CYREG_SCB0_UART_RX_STATUS +SPI_1_SCB__UART_TX_CTRL EQU CYREG_SCB0_UART_TX_CTRL +SPI_1_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL0 +SPI_1_SCBCLK__DIV_ID EQU 0x00000040 +SPI_1_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL0 +SPI_1_SCBCLK__PA_DIV_ID EQU 0x000000FF +SPI_1_sclk_m__0__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_sclk_m__0__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_sclk_m__0__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_sclk_m__0__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_sclk_m__0__HSIOM EQU CYREG_HSIOM_PORT_SEL4 +SPI_1_sclk_m__0__HSIOM_GPIO EQU 0 +SPI_1_sclk_m__0__HSIOM_MASK EQU 0x00000F00 +SPI_1_sclk_m__0__HSIOM_SHIFT EQU 8 +SPI_1_sclk_m__0__HSIOM_SPI EQU 15 +SPI_1_sclk_m__0__HSIOM_SPI_CLK EQU 15 +SPI_1_sclk_m__0__HSIOM_UART EQU 9 +SPI_1_sclk_m__0__HSIOM_UART_CTS EQU 9 +SPI_1_sclk_m__0__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_sclk_m__0__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_sclk_m__0__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_sclk_m__0__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_sclk_m__0__MASK EQU 0x04 +SPI_1_sclk_m__0__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_sclk_m__0__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_sclk_m__0__PORT EQU 4 +SPI_1_sclk_m__0__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_sclk_m__0__SHIFT EQU 2 +SPI_1_sclk_m__DR EQU CYREG_GPIO_PRT4_DR +SPI_1_sclk_m__DR_CLR EQU CYREG_GPIO_PRT4_DR_CLR +SPI_1_sclk_m__DR_INV EQU CYREG_GPIO_PRT4_DR_INV +SPI_1_sclk_m__DR_SET EQU CYREG_GPIO_PRT4_DR_SET +SPI_1_sclk_m__INTCFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_sclk_m__INTR EQU CYREG_GPIO_PRT4_INTR +SPI_1_sclk_m__INTR_CFG EQU CYREG_GPIO_PRT4_INTR_CFG +SPI_1_sclk_m__INTSTAT EQU CYREG_GPIO_PRT4_INTR +SPI_1_sclk_m__MASK EQU 0x04 +SPI_1_sclk_m__PC EQU CYREG_GPIO_PRT4_PC +SPI_1_sclk_m__PC2 EQU CYREG_GPIO_PRT4_PC2 +SPI_1_sclk_m__PORT EQU 4 +SPI_1_sclk_m__PS EQU CYREG_GPIO_PRT4_PS +SPI_1_sclk_m__SHIFT EQU 2 + +; UART_1 +UART_1_rx_wake__0__DR EQU CYREG_GPIO_PRT3_DR +UART_1_rx_wake__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR +UART_1_rx_wake__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV +UART_1_rx_wake__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET +UART_1_rx_wake__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3 +UART_1_rx_wake__0__HSIOM_GPIO EQU 0 +UART_1_rx_wake__0__HSIOM_I2C EQU 14 +UART_1_rx_wake__0__HSIOM_I2C_SCL EQU 14 +UART_1_rx_wake__0__HSIOM_MASK EQU 0x0000000F +UART_1_rx_wake__0__HSIOM_SHIFT EQU 0 +UART_1_rx_wake__0__HSIOM_SPI EQU 15 +UART_1_rx_wake__0__HSIOM_SPI_MOSI EQU 15 +UART_1_rx_wake__0__HSIOM_UART EQU 9 +UART_1_rx_wake__0__HSIOM_UART_RX EQU 9 +UART_1_rx_wake__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_rx_wake__0__INTR EQU CYREG_GPIO_PRT3_INTR +UART_1_rx_wake__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_rx_wake__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR +UART_1_rx_wake__0__MASK EQU 0x01 +UART_1_rx_wake__0__PC EQU CYREG_GPIO_PRT3_PC +UART_1_rx_wake__0__PC2 EQU CYREG_GPIO_PRT3_PC2 +UART_1_rx_wake__0__PORT EQU 3 +UART_1_rx_wake__0__PS EQU CYREG_GPIO_PRT3_PS +UART_1_rx_wake__0__SHIFT EQU 0 +UART_1_rx_wake__DR EQU CYREG_GPIO_PRT3_DR +UART_1_rx_wake__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR +UART_1_rx_wake__DR_INV EQU CYREG_GPIO_PRT3_DR_INV +UART_1_rx_wake__DR_SET EQU CYREG_GPIO_PRT3_DR_SET +UART_1_rx_wake__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_rx_wake__INTR EQU CYREG_GPIO_PRT3_INTR +UART_1_rx_wake__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_rx_wake__INTSTAT EQU CYREG_GPIO_PRT3_INTR +UART_1_rx_wake__MASK EQU 0x01 +UART_1_rx_wake__PC EQU CYREG_GPIO_PRT3_PC +UART_1_rx_wake__PC2 EQU CYREG_GPIO_PRT3_PC2 +UART_1_rx_wake__PORT EQU 3 +UART_1_rx_wake__PS EQU CYREG_GPIO_PRT3_PS +UART_1_rx_wake__SHIFT EQU 0 +UART_1_rx_wake__SNAP EQU CYREG_GPIO_PRT3_INTR +UART_1_RX_WAKEUP_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER +UART_1_RX_WAKEUP_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR +UART_1_RX_WAKEUP_IRQ__INTC_MASK EQU 0x08 +UART_1_RX_WAKEUP_IRQ__INTC_NUMBER EQU 3 +UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_MASK EQU 0xC0000000 +UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_NUM EQU 3 +UART_1_RX_WAKEUP_IRQ__INTC_PRIOR_REG EQU CYREG_CM0P_IPR0 +UART_1_RX_WAKEUP_IRQ__INTC_SET_EN_REG EQU CYREG_CM0P_ISER +UART_1_RX_WAKEUP_IRQ__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR +UART_1_SCB__CTRL EQU CYREG_SCB1_CTRL +UART_1_SCB__EZ_DATA0 EQU CYREG_SCB1_EZ_DATA0 +UART_1_SCB__EZ_DATA1 EQU CYREG_SCB1_EZ_DATA1 +UART_1_SCB__EZ_DATA10 EQU CYREG_SCB1_EZ_DATA10 +UART_1_SCB__EZ_DATA11 EQU CYREG_SCB1_EZ_DATA11 +UART_1_SCB__EZ_DATA12 EQU CYREG_SCB1_EZ_DATA12 +UART_1_SCB__EZ_DATA13 EQU CYREG_SCB1_EZ_DATA13 +UART_1_SCB__EZ_DATA14 EQU CYREG_SCB1_EZ_DATA14 +UART_1_SCB__EZ_DATA15 EQU CYREG_SCB1_EZ_DATA15 +UART_1_SCB__EZ_DATA16 EQU CYREG_SCB1_EZ_DATA16 +UART_1_SCB__EZ_DATA17 EQU CYREG_SCB1_EZ_DATA17 +UART_1_SCB__EZ_DATA18 EQU CYREG_SCB1_EZ_DATA18 +UART_1_SCB__EZ_DATA19 EQU CYREG_SCB1_EZ_DATA19 +UART_1_SCB__EZ_DATA2 EQU CYREG_SCB1_EZ_DATA2 +UART_1_SCB__EZ_DATA20 EQU CYREG_SCB1_EZ_DATA20 +UART_1_SCB__EZ_DATA21 EQU CYREG_SCB1_EZ_DATA21 +UART_1_SCB__EZ_DATA22 EQU CYREG_SCB1_EZ_DATA22 +UART_1_SCB__EZ_DATA23 EQU CYREG_SCB1_EZ_DATA23 +UART_1_SCB__EZ_DATA24 EQU CYREG_SCB1_EZ_DATA24 +UART_1_SCB__EZ_DATA25 EQU CYREG_SCB1_EZ_DATA25 +UART_1_SCB__EZ_DATA26 EQU CYREG_SCB1_EZ_DATA26 +UART_1_SCB__EZ_DATA27 EQU CYREG_SCB1_EZ_DATA27 +UART_1_SCB__EZ_DATA28 EQU CYREG_SCB1_EZ_DATA28 +UART_1_SCB__EZ_DATA29 EQU CYREG_SCB1_EZ_DATA29 +UART_1_SCB__EZ_DATA3 EQU CYREG_SCB1_EZ_DATA3 +UART_1_SCB__EZ_DATA30 EQU CYREG_SCB1_EZ_DATA30 +UART_1_SCB__EZ_DATA31 EQU CYREG_SCB1_EZ_DATA31 +UART_1_SCB__EZ_DATA4 EQU CYREG_SCB1_EZ_DATA4 +UART_1_SCB__EZ_DATA5 EQU CYREG_SCB1_EZ_DATA5 +UART_1_SCB__EZ_DATA6 EQU CYREG_SCB1_EZ_DATA6 +UART_1_SCB__EZ_DATA7 EQU CYREG_SCB1_EZ_DATA7 +UART_1_SCB__EZ_DATA8 EQU CYREG_SCB1_EZ_DATA8 +UART_1_SCB__EZ_DATA9 EQU CYREG_SCB1_EZ_DATA9 +UART_1_SCB__I2C_CFG EQU CYREG_SCB1_I2C_CFG +UART_1_SCB__I2C_CTRL EQU CYREG_SCB1_I2C_CTRL +UART_1_SCB__I2C_M_CMD EQU CYREG_SCB1_I2C_M_CMD +UART_1_SCB__I2C_S_CMD EQU CYREG_SCB1_I2C_S_CMD +UART_1_SCB__I2C_STATUS EQU CYREG_SCB1_I2C_STATUS +UART_1_SCB__INTR_CAUSE EQU CYREG_SCB1_INTR_CAUSE +UART_1_SCB__INTR_I2C_EC EQU CYREG_SCB1_INTR_I2C_EC +UART_1_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB1_INTR_I2C_EC_MASK +UART_1_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB1_INTR_I2C_EC_MASKED +UART_1_SCB__INTR_M EQU CYREG_SCB1_INTR_M +UART_1_SCB__INTR_M_MASK EQU CYREG_SCB1_INTR_M_MASK +UART_1_SCB__INTR_M_MASKED EQU CYREG_SCB1_INTR_M_MASKED +UART_1_SCB__INTR_M_SET EQU CYREG_SCB1_INTR_M_SET +UART_1_SCB__INTR_RX EQU CYREG_SCB1_INTR_RX +UART_1_SCB__INTR_RX_MASK EQU CYREG_SCB1_INTR_RX_MASK +UART_1_SCB__INTR_RX_MASKED EQU CYREG_SCB1_INTR_RX_MASKED +UART_1_SCB__INTR_RX_SET EQU CYREG_SCB1_INTR_RX_SET +UART_1_SCB__INTR_S EQU CYREG_SCB1_INTR_S +UART_1_SCB__INTR_S_MASK EQU CYREG_SCB1_INTR_S_MASK +UART_1_SCB__INTR_S_MASKED EQU CYREG_SCB1_INTR_S_MASKED +UART_1_SCB__INTR_S_SET EQU CYREG_SCB1_INTR_S_SET +UART_1_SCB__INTR_SPI_EC EQU CYREG_SCB1_INTR_SPI_EC +UART_1_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB1_INTR_SPI_EC_MASK +UART_1_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB1_INTR_SPI_EC_MASKED +UART_1_SCB__INTR_TX EQU CYREG_SCB1_INTR_TX +UART_1_SCB__INTR_TX_MASK EQU CYREG_SCB1_INTR_TX_MASK +UART_1_SCB__INTR_TX_MASKED EQU CYREG_SCB1_INTR_TX_MASKED +UART_1_SCB__INTR_TX_SET EQU CYREG_SCB1_INTR_TX_SET +UART_1_SCB__RX_CTRL EQU CYREG_SCB1_RX_CTRL +UART_1_SCB__RX_FIFO_CTRL EQU CYREG_SCB1_RX_FIFO_CTRL +UART_1_SCB__RX_FIFO_RD EQU CYREG_SCB1_RX_FIFO_RD +UART_1_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB1_RX_FIFO_RD_SILENT +UART_1_SCB__RX_FIFO_STATUS EQU CYREG_SCB1_RX_FIFO_STATUS +UART_1_SCB__RX_MATCH EQU CYREG_SCB1_RX_MATCH +UART_1_SCB__SPI_CTRL EQU CYREG_SCB1_SPI_CTRL +UART_1_SCB__SPI_STATUS EQU CYREG_SCB1_SPI_STATUS +UART_1_SCB__SS0_POSISTION EQU 0 +UART_1_SCB__SS1_POSISTION EQU 1 +UART_1_SCB__SS2_POSISTION EQU 2 +UART_1_SCB__SS3_POSISTION EQU 3 +UART_1_SCB__STATUS EQU CYREG_SCB1_STATUS +UART_1_SCB__TX_CTRL EQU CYREG_SCB1_TX_CTRL +UART_1_SCB__TX_FIFO_CTRL EQU CYREG_SCB1_TX_FIFO_CTRL +UART_1_SCB__TX_FIFO_STATUS EQU CYREG_SCB1_TX_FIFO_STATUS +UART_1_SCB__TX_FIFO_WR EQU CYREG_SCB1_TX_FIFO_WR +UART_1_SCB__UART_CTRL EQU CYREG_SCB1_UART_CTRL +UART_1_SCB__UART_FLOW_CTRL EQU CYREG_SCB1_UART_FLOW_CTRL +UART_1_SCB__UART_RX_CTRL EQU CYREG_SCB1_UART_RX_CTRL +UART_1_SCB__UART_RX_STATUS EQU CYREG_SCB1_UART_RX_STATUS +UART_1_SCB__UART_TX_CTRL EQU CYREG_SCB1_UART_TX_CTRL +UART_1_SCB_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0P_ICER +UART_1_SCB_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0P_ICPR +UART_1_SCB_IRQ__INTC_MASK EQU 0x100 +UART_1_SCB_IRQ__INTC_NUMBER EQU 8 +UART_1_SCB_IRQ__INTC_PRIOR_MASK EQU 0xC0 +UART_1_SCB_IRQ__INTC_PRIOR_NUM EQU 0 +UART_1_SCB_IRQ__INTC_PRIOR_REG EQU CYREG_CM0P_IPR2 +UART_1_SCB_IRQ__INTC_SET_EN_REG EQU CYREG_CM0P_ISER +UART_1_SCB_IRQ__INTC_SET_PD_REG EQU CYREG_CM0P_ISPR +UART_1_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL1 +UART_1_SCBCLK__DIV_ID EQU 0x00000041 +UART_1_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL1 +UART_1_SCBCLK__PA_DIV_ID EQU 0x000000FF +UART_1_tx__0__DR EQU CYREG_GPIO_PRT3_DR +UART_1_tx__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR +UART_1_tx__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV +UART_1_tx__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET +UART_1_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3 +UART_1_tx__0__HSIOM_GPIO EQU 0 +UART_1_tx__0__HSIOM_I2C EQU 14 +UART_1_tx__0__HSIOM_I2C_SDA EQU 14 +UART_1_tx__0__HSIOM_MASK EQU 0x000000F0 +UART_1_tx__0__HSIOM_SHIFT EQU 4 +UART_1_tx__0__HSIOM_SPI EQU 15 +UART_1_tx__0__HSIOM_SPI_MISO EQU 15 +UART_1_tx__0__HSIOM_UART EQU 9 +UART_1_tx__0__HSIOM_UART_TX EQU 9 +UART_1_tx__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_tx__0__INTR EQU CYREG_GPIO_PRT3_INTR +UART_1_tx__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_tx__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR +UART_1_tx__0__MASK EQU 0x02 +UART_1_tx__0__PC EQU CYREG_GPIO_PRT3_PC +UART_1_tx__0__PC2 EQU CYREG_GPIO_PRT3_PC2 +UART_1_tx__0__PORT EQU 3 +UART_1_tx__0__PS EQU CYREG_GPIO_PRT3_PS +UART_1_tx__0__SHIFT EQU 1 +UART_1_tx__DR EQU CYREG_GPIO_PRT3_DR +UART_1_tx__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR +UART_1_tx__DR_INV EQU CYREG_GPIO_PRT3_DR_INV +UART_1_tx__DR_SET EQU CYREG_GPIO_PRT3_DR_SET +UART_1_tx__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_tx__INTR EQU CYREG_GPIO_PRT3_INTR +UART_1_tx__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG +UART_1_tx__INTSTAT EQU CYREG_GPIO_PRT3_INTR +UART_1_tx__MASK EQU 0x02 +UART_1_tx__PC EQU CYREG_GPIO_PRT3_PC +UART_1_tx__PC2 EQU CYREG_GPIO_PRT3_PC2 +UART_1_tx__PORT EQU 3 +UART_1_tx__PS EQU CYREG_GPIO_PRT3_PS +UART_1_tx__SHIFT EQU 1 + +; Miscellaneous +CYDEV_BCLK__HFCLK__HZ EQU 24000000 +CYDEV_BCLK__HFCLK__KHZ EQU 24000 +CYDEV_BCLK__HFCLK__MHZ EQU 24 +CYDEV_BCLK__SYSCLK__HZ EQU 24000000 +CYDEV_BCLK__SYSCLK__KHZ EQU 24000 +CYDEV_BCLK__SYSCLK__MHZ EQU 24 +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4 +CYDEV_CHIP_JTAG_ID EQU 0x256A11B5 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4V +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 +CYDEV_CHIP_REV_TMA4_ES EQU 17 +CYDEV_CHIP_REV_TMA4_ES2 EQU 33 +CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 +CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0 +CYDEV_CHIP_REVISION_4G_ES EQU 17 +CYDEV_CHIP_REVISION_4G_ES2 EQU 33 +CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4V_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED +CYDEV_CONFIG_READ_ACCELERATOR EQU 1 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_Disallowed +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_DEBUG_PROTECT_KILL EQU 4 +CYDEV_DEBUG_PROTECT_OPEN EQU 1 +CYDEV_DEBUG_PROTECT_PROTECTED EQU 2 +CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_PROTECTED +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_Disable +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_ENABLE EQU 0 +CYDEV_DFT_SELECT_CLK0 EQU 8 +CYDEV_DFT_SELECT_CLK1 EQU 9 +CYDEV_DMA_CHANNELS_AVAILABLE EQU 8 +CYDEV_HEAP_SIZE EQU 0x1000 +CYDEV_IMO_TRIMMED_BY_USB EQU 0 +CYDEV_IMO_TRIMMED_BY_WCO EQU 0 +CYDEV_INTR_NUMBER_DMA EQU 14 +CYDEV_IS_EXPORTING_CODE EQU 0 +CYDEV_IS_IMPORTING_CODE EQU 0 +CYDEV_PROJ_TYPE EQU 2 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LAUNCHER EQU 5 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_STACK_SIZE EQU 0x0800 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 1 +CYDEV_VDDA_MV EQU 3300 +CYDEV_VDDD_MV EQU 3300 +CYDEV_WDT_GENERATE_ISR EQU 1 +CYIPBLOCK_m0s8cpussv3_VERSION EQU 1 +CYIPBLOCK_m0s8crypto_VERSION EQU 2 +CYIPBLOCK_m0s8csdv2_VERSION EQU 2 +CYIPBLOCK_m0s8exco_VERSION EQU 1 +CYIPBLOCK_m0s8ioss_VERSION EQU 1 +CYIPBLOCK_m0s8lcd_VERSION EQU 2 +CYIPBLOCK_m0s8lpcomp_VERSION EQU 2 +CYIPBLOCK_m0s8pass4a_VERSION EQU 1 +CYIPBLOCK_m0s8peri_VERSION EQU 1 +CYIPBLOCK_m0s8scb_VERSION EQU 2 +CYIPBLOCK_m0s8tcpwm_VERSION EQU 2 +CYIPBLOCK_m0s8wco_VERSION EQU 1 +CYIPBLOCK_s8srsslt_VERSION EQU 1 +DMA_CHANNELS_USED__MASK EQU 0 +CYDEV_BOOTLOADER_ENABLE EQU 0 + ENDIF + END diff --git a/cores/asr650x/projects/PSoC4/cymetadata.c b/cores/asr650x/projects/PSoC4/cymetadata.c new file mode 100644 index 00000000..10501182 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cymetadata.c @@ -0,0 +1,40 @@ +/******************************************************************************* +* File Name: cymetadata.c +* +* PSoC Creator 4.2 +* +* Description: +* This file defines all extra memory spaces that need to be included. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#include "stdint.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_LOADABLE_META_SECTION +#define CY_LOADABLE_META_SECTION __attribute__ ((__section__(".cyloadablemeta"), used)) +#endif +CY_LOADABLE_META_SECTION +#elif defined(__ICCARM__) +#pragma location=".cyloadablemeta" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_loadable[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; diff --git a/cores/asr650x/projects/PSoC4/cypins.h b/cores/asr650x/projects/PSoC4/cypins.h new file mode 100644 index 00000000..53a0b29c --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cypins.h @@ -0,0 +1,324 @@ +/******************************************************************************* +* \file cypins.h +* \version 5.70 +* +* \brief This file contains the function prototypes and constants used for +* port/pin in access and control. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPINS_H) +#define CY_BOOT_CYPINS_H + +#include "cytypes.h" + +/** +* \addtogroup group_pins Pins +* \brief For PSoC 4, there are status registers, data output registers, and port +configuration registers only, so the macro takes two arguments: port register +and pin number. Each port has these registers addresses defined: +CYREG_PRTx_DR +CYREG_PRTx_PS +CYREG_PRTx_PC + +The x is the port number, and the second argument is the pin number. + +* @{ +*/ + +/** @} group_pins */ + + +/************************************** +* Register Constants +**************************************/ + + +#define CY_SYS_PINS_PC_DATAOUT ((uint32) 0x01u) +#define CY_SYS_PINS_PC_DRIVE_MODE_BITS ((uint32) 0x03u) +#define CY_SYS_PINS_PC_DRIVE_MODE_MASK ((uint32) 0x07u) + + +/************************************** +* API Parameter Constants +**************************************/ + +/* SetPinDriveMode */ +#define CY_SYS_PINS_DM_ALG_HIZ ((uint32) 0x00u) +#define CY_SYS_PINS_DM_DIG_HIZ ((uint32) 0x01u) +#define CY_SYS_PINS_DM_RES_UP ((uint32) 0x02u) +#define CY_SYS_PINS_DM_RES_DWN ((uint32) 0x03u) +#define CY_SYS_PINS_DM_OD_LO ((uint32) 0x04u) +#define CY_SYS_PINS_DM_OD_HI ((uint32) 0x05u) +#define CY_SYS_PINS_DM_STRONG ((uint32) 0x06u) +#define CY_SYS_PINS_DM_RES_UPDWN ((uint32) 0x07u) + + +/************************************** +* Compatibility Macros +**************************************/ + +#if(CY_IP_HOBTO_DEVICE) + #define CYREG_PRT0_DR (CYREG_GPIO_PRT0_DR) + #define CYREG_PRT0_PS (CYREG_GPIO_PRT0_PS) + #define CYREG_PRT0_PC (CYREG_GPIO_PRT0_PC) + + #define CYREG_PRT1_DR (CYREG_GPIO_PRT1_DR) + #define CYREG_PRT1_PS (CYREG_GPIO_PRT1_PS) + #define CYREG_PRT1_PC (CYREG_GPIO_PRT1_PC) + + #define CYREG_PRT2_DR (CYREG_GPIO_PRT2_DR) + #define CYREG_PRT2_PS (CYREG_GPIO_PRT2_PS) + #define CYREG_PRT2_PC (CYREG_GPIO_PRT2_PC) + + #define CYREG_PRT3_DR (CYREG_GPIO_PRT3_DR) + #define CYREG_PRT3_PS (CYREG_GPIO_PRT3_PS) + #define CYREG_PRT3_PC (CYREG_GPIO_PRT3_PC) + + #define CYREG_PRT4_DR (CYREG_GPIO_PRT4_DR) + #define CYREG_PRT4_PS (CYREG_GPIO_PRT4_PS) + #define CYREG_PRT4_PC (CYREG_GPIO_PRT4_PC) + + #define CYREG_PRT5_DR (CYREG_GPIO_PRT5_DR) + #define CYREG_PRT5_PS (CYREG_GPIO_PRT5_PS) + #define CYREG_PRT5_PC (CYREG_GPIO_PRT5_PC) + + #define CYREG_PRT6_DR (CYREG_GPIO_PRT6_DR) + #define CYREG_PRT6_PS (CYREG_GPIO_PRT6_PS) + #define CYREG_PRT6_PC (CYREG_GPIO_PRT6_PC) + + #define CYREG_PRT7_DR (CYREG_GPIO_PRT7_DR) + #define CYREG_PRT7_PS (CYREG_GPIO_PRT7_PS) + #define CYREG_PRT7_PC (CYREG_GPIO_PRT7_PC) + + #define CYREG_PRT8_DR (CYREG_GPIO_PRT8_DR) + #define CYREG_PRT8_PS (CYREG_GPIO_PRT8_PS) + #define CYREG_PRT8_PC (CYREG_GPIO_PRT8_PC) + + #define CYREG_PRT9_DR (CYREG_GPIO_PRT9_DR) + #define CYREG_PRT9_PS (CYREG_GPIO_PRT9_PS) + #define CYREG_PRT9_PC (CYREG_GPIO_PRT9_PC) + + #define CYREG_PRT10_DR (CYREG_GPIO_PRT10_DR) + #define CYREG_PRT10_PS (CYREG_GPIO_PRT10_PS) + #define CYREG_PRT10_PC (CYREG_GPIO_PRT10_PC) + + #define CYREG_PRT11_DR (CYREG_GPIO_PRT11_DR) + #define CYREG_PRT11_PS (CYREG_GPIO_PRT11_PS) + #define CYREG_PRT11_PC (CYREG_GPIO_PRT11_PC) + + #define CYREG_PRT12_DR (CYREG_GPIO_PRT12_DR) + #define CYREG_PRT12_PS (CYREG_GPIO_PRT12_PS) + #define CYREG_PRT12_PC (CYREG_GPIO_PRT12_PC) + + #define CYREG_PRT13_DR (CYREG_GPIO_PRT13_DR) + #define CYREG_PRT13_PS (CYREG_GPIO_PRT13_PS) + #define CYREG_PRT13_PC (CYREG_GPIO_PRT13_PC) + + #define CYREG_PRT14_DR (CYREG_GPIO_PRT14_DR) + #define CYREG_PRT14_PS (CYREG_GPIO_PRT14_PS) + #define CYREG_PRT14_PC (CYREG_GPIO_PRT14_PC) + + #define CYREG_PRT15_DR (CYREG_GPIO_PRT15_DR) + #define CYREG_PRT15_PS (CYREG_GPIO_PRT15_PS) + #define CYREG_PRT15_PC (CYREG_GPIO_PRT15_PC) + +#else + + #define CYREG_GPIO_PRT0_DR (CYREG_PRT0_DR) + #define CYREG_GPIO_PRT0_PS (CYREG_PRT0_PS) + #define CYREG_GPIO_PRT0_PC (CYREG_PRT0_PC) + + #define CYREG_GPIO_PRT1_DR (CYREG_PRT1_DR) + #define CYREG_GPIO_PRT1_PS (CYREG_PRT1_PS) + #define CYREG_GPIO_PRT1_PC (CYREG_PRT1_PC) + + #define CYREG_GPIO_PRT2_DR (CYREG_PRT2_DR) + #define CYREG_GPIO_PRT2_PS (CYREG_PRT2_PS) + #define CYREG_GPIO_PRT2_PC (CYREG_PRT2_PC) + + #define CYREG_GPIO_PRT3_DR (CYREG_PRT3_DR) + #define CYREG_GPIO_PRT3_PS (CYREG_PRT3_PS) + #define CYREG_GPIO_PRT3_PC (CYREG_PRT3_PC) + + #define CYREG_GPIO_PRT4_DR (CYREG_PRT4_DR) + #define CYREG_GPIO_PRT4_PS (CYREG_PRT4_PS) + #define CYREG_GPIO_PRT4_PC (CYREG_PRT4_PC) +#endif /* (CY_IP_HOBTO_DEVICE) */ + + +/************************************** +* Pin API Macros +**************************************/ + +/** +* \defgroup group_pins Pins +* @{ +*/ + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_READ_PIN +****************************************************************************//** +* +* Reads the current value on the pin (pin state, PS). +* +* \param portPS Address of the port pin status register (uint32). Definitions +* for each port are provided in the cydevice_trm.h file in the form: +* CYREG_GPIO_PRTx_PS, where x is a port number. The actual number depends on the +* selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected +* device. +* +* \return Zero - logic low, non-zero - logic high. +* +*******************************************************************************/ +#define CY_SYS_PINS_READ_PIN(portPS, pin) \ + (( *(reg32 *)(portPS) >> (pin)) & CY_SYS_PINS_PC_DATAOUT) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_SET_PIN +****************************************************************************//** +* +* Set the output value for the pin (data register, DR) to a logic high. +* Note that this only has an effect for pins configured as software pins that +* are not driven by hardware. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param portDR Address of the port output pin data register (uint32). +* Definitions for each port are provided in the cydevice_trm.h file in the +* form: CYREG_GPIO_PRTx_PS, where x is a port number. The actual number depends +* on the selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected +* device. +* +*******************************************************************************/ +#define CY_SYS_PINS_SET_PIN(portDR, pin) \ + ( *(reg32 *)(portDR) |= (CY_SYS_PINS_PC_DATAOUT << (pin)) ) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_CLEAR_PIN +****************************************************************************//** +* +* This macro sets the state of the specified pin to zero. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param portDR Address of the port output pin data register (uint32). +* Definitions for each port are provided in the cydevice_trm.h file in the +* form: CYREG_GPIO_PRTx_PS, where x is a port number. The actual number +* depends on the selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected device. +* +*******************************************************************************/ +#define CY_SYS_PINS_CLEAR_PIN(portDR, pin) \ + ( *(reg32 *)(portDR) &= ~(CY_SYS_PINS_PC_DATAOUT << (pin)) ) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_SET_DRIVE_MODE +****************************************************************************//** +* +* Sets the drive mode for the pin (DM). +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param portPC: Address of the port configuration register (uint32). +* Definitions for each port are provided in the cydevice_trm.h file in the +* form: CYREG_GPIO_PRTx_PS, where x is a port number. The actual number +* depends on the selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected device. +* +* \param mode Desired drive mode. +* +* Define Source +* CY_SYS_PINS_DM_ALG_HIZ Analog HiZ +* CY_SYS_PINS_DM_DIG_HIZ Digital HiZ +* CY_SYS_PINS_DM_RES_UP Resistive pull up +* CY_SYS_PINS_DM_RES_DWN Resistive pull down +* CY_SYS_PINS_DM_OD_LO Open drain - drive low +* CY_SYS_PINS_DM_OD_HI Open drain - drive high +* CY_SYS_PINS_DM_STRONG Strong CMOS Output +* CY_SYS_PINS_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CY_SYS_PINS_SET_DRIVE_MODE(portPC, pin, mode) \ + ( *(reg32 *)(portPC) = (*(reg32 *)(portPC) & \ + ~(CY_SYS_PINS_PC_DRIVE_MODE_MASK << ((pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS))) | \ + ((mode) << ((pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS))) + + +/******************************************************************************* +* Macro Name: CY_SYS_PINS_READ_DRIVE_MODE +****************************************************************************//** +* +* Reads the drive mode for the pin (DM). +* +* \param portPC Address of the port configuration register (uint32). Definitions +* for each port are provided in the cydevice_trm.h file in the form: +* CYREG_GPIO_PRTx_PS, where x is a port number. The actual number depends on the +* selected device. +* +* \param pin The pin number 0 - 7. The actual number depends on the selected +* device. +* +* \return mode Current drive mode for the pin: +* - CY_SYS_PINS_DM_ALG_HIZ Analog HiZ +* - CY_SYS_PINS_DM_DIG_HIZ Digital HiZ +* - CY_SYS_PINS_DM_RES_UP Resistive pull up +* - CY_SYS_PINS_DM_RES_DWN Resistive pull down +* - CY_SYS_PINS_DM_OD_LO Open drain - drive low +* - CY_SYS_PINS_DM_OD_HI Open drain - drive high +* - CY_SYS_PINS_DM_STRONG Strong CMOS Output +* - CY_SYS_PINS_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CY_SYS_PINS_READ_DRIVE_MODE(portPC, pin) \ + (( *(reg32 *)(portPC) & \ + (CY_SYS_PINS_PC_DRIVE_MODE_MASK << ((pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS)) ) >> \ + (pin) * CY_SYS_PINS_PC_DRIVE_MODE_BITS) + +/** @} group_pins */ + +/* Defines function macros for mapping PSoC 4 per-pin functions to PSoC 3/5LP style functions */ +#define CyPins_ReadPin(name) (CY_SYS_PINS_READ_PIN (name ## _PS, name ## _SHIFT)) +#define CyPins_SetPin(name) (CY_SYS_PINS_SET_PIN (name ## _DR, name ## _SHIFT)) +#define CyPins_ClearPin(name) (CY_SYS_PINS_CLEAR_PIN (name ## _DR, name ## _SHIFT)) +#define CyPins_SetPinDriveMode(name, mode) (CY_SYS_PINS_SET_DRIVE_MODE (name ## _PC, name ## _SHIFT, mode)) +#define CyPins_ReadPinDriveMode(name) (CY_SYS_PINS_READ_DRIVE_MODE(name ## _PC, name ## _SHIFT)) + + +#endif /* (CY_BOOT_CYPINS_H) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/cytypes.h b/cores/asr650x/projects/PSoC4/cytypes.h new file mode 100644 index 00000000..0579aa22 --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cytypes.h @@ -0,0 +1,1496 @@ +/***************************************************************************//** +* \file cytypes.h +* \version 5.70 +* +* \brief CyTypes provides register access macros and approved types for use in +* firmware. +* +* \note Due to endiannesses of the hardware and some compilers, the register +* access macros for big endian compilers use some library calls to arrange +* data the correct way. +* +* Register Access macros and functions perform their operations on an +* input of the type pointer to void. The arguments passed to it should be +* pointers to the type associated with the register size. +* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYTYPES_H) +#define CY_BOOT_CYTYPES_H + +#if defined(__C51__) + #include +#endif /* (__C51__) */ + +/* ARM and C99 or later */ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) + #include +#endif /* (__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */ + +#include "cyfitter.h" + + +#if defined( __ICCARM__ ) + /* Suppress warning for multiple volatile variables in an expression. */ + /* This is common in component code and usage is not order dependent. */ + #pragma diag_suppress=Pa082 +#endif /* defined( __ICCARM__ ) */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + + +/******************************************************************************* +* FAMILY encodes the overall architectural family +*******************************************************************************/ +#define CY_PSOC3 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) +#define CY_PSOC4 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) +#define CY_PSOC5 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5) + + +/******************************************************************************* +* MEMBER encodes both the family and the detailed architecture +*******************************************************************************/ +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4_4000 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) +#else + #define CY_PSOC4_4000 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4D */ + +#define CY_PSOC4_4100 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#define CY_PSOC4_4200 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) + +#ifdef CYDEV_CHIP_MEMBER_4F + #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) + #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) +#else + #define CY_PSOC4_4100BL (0u != 0u) + #define CY_PSOC4_4200BL (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4F */ + +#ifdef CYDEV_CHIP_MEMBER_4M + #define CY_PSOC4_4100M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) + #define CY_PSOC4_4200M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) +#else + #define CY_PSOC4_4100M (0u != 0u) + #define CY_PSOC4_4200M (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4M */ + +#ifdef CYDEV_CHIP_MEMBER_4H + #define CY_PSOC4_4200D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4H) +#else + #define CY_PSOC4_4200D (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4H */ + +#ifdef CYDEV_CHIP_MEMBER_4L + #define CY_PSOC4_4200L (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4L) +#else + #define CY_PSOC4_4200L (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4L */ + +#ifdef CYDEV_CHIP_MEMBER_4U + #define CY_PSOC4_4000U (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4U) +#else + #define CY_PSOC4_4000U (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4U */ + +#ifdef CYDEV_CHIP_MEMBER_4J + #define CY_PSOC4_4000S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4J) +#else + #define CY_PSOC4_4000S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4J */ + +#ifdef CYDEV_CHIP_MEMBER_4K + #define CY_PSOC4_4100S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4K) +#else + #define CY_PSOC4_4100S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4K */ + +#ifdef CYDEV_CHIP_MEMBER_4I + #define CY_PSOC4_4400 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4I) +#else + #define CY_PSOC4_4400 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4I */ + +#ifdef CYDEV_CHIP_MEMBER_4E + #define CY_CCG2 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4E) +#else + #define CY_CCG2 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4E */ + +#ifdef CYDEV_CHIP_MEMBER_4O + #define CY_CCG3 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4O) +#else + #define CY_CCG3 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4O */ + +#ifdef CYDEV_CHIP_MEMBER_4R + #define CY_CCG3PA (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4R) +#else + #define CY_CCG3PA (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4R */ + +#ifdef CYDEV_CHIP_MEMBER_4N + #define CY_CCG4 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4N) +#else + #define CY_CCG4 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4N */ + +#ifdef CYDEV_CHIP_MEMBER_4S + #define CY_CCG5 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4S) +#else + #define CY_CCG5 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4S */ + +#ifdef CYDEV_CHIP_MEMBER_4P + #define CY_PSOC4_4100BLII (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4P) + #define CY_PSOC4_4200BLII (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4P) +#else + #define CY_PSOC4_4100BLII (0u != 0u) + #define CY_PSOC4_4200BLII (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4P */ + +#ifdef CYDEV_CHIP_MEMBER_4V + #define CY_PSOC4_4100MS (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4V) + #define CY_PSOC4_4100MS (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4V) +#else + #define CY_PSOC4_4100MS (0u != 0u) + #define CY_PSOC4_4100MS (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4V */ + +#define CY_IP_HOBTO_DEVICE (!(0 == 1)) + + +/******************************************************************************* +* IP blocks +*******************************************************************************/ +#if (CY_PSOC4) + + /* Using SRSSv2 or SRS-Lite */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_SRSSV2 (0 != 0) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #else + #define CY_IP_SRSSV2 (0 == 0) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSSV3 (1 == 1) + #define CY_IP_CPUSSV2 (0 == 1) + #define CY_IP_CPUSS (0 == 1) + #else + #define CY_IP_CPUSSV3 (0 != 0) + #define CY_IP_CPUSSV2 (0 != 0) + #define CY_IP_CPUSS (0 == 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* CM0 present or CM0+ present (1=CM0, 0=CM0+) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_CPUSS_CM0 (0 == 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_CPUSS_CM0 (0 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #define CY_IP_CPUSS_CM0PLUS (!CY_IP_CPUSS_CM0) + #else + #define CY_IP_CPUSS_CM0 (0 == 0) + #define CY_IP_CPUSS_CM0PLUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash memory present or not (1=Flash present, 0=Flash not present) */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSS_FLASHC_PRESENT (0 == 0) + #else + #define CY_IP_CPUSS_FLASHC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Product uses FLASH-Lite or regular FLASH */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FM (-1 == 0) + #define CY_IP_FMLT (-1 == 1) + #define CY_IP_FS (-1 == 2) + #define CY_IP_FSLT (-1 == 3) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FM (3 == 0) + #define CY_IP_FMLT (3 == 1) + #define CY_IP_FS (3 == 2) + #define CY_IP_FSLT (3 == 3) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */ + #define CY_IP_FMLT (0 != 0) /* FLASH-Lite */ + #define CY_IP_FS (0 != 0) /* FS */ + #define CY_IP_FSLT (0 != 0) /* FSLT */ + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Enable simultaneous execution/programming in multi-macro devices */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_PARALLEL_PGM_EN (0 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_PARALLEL_PGM_EN (0u != 0u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Number of Flash macros used in the device (0, 1 or 2) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_MACROS (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_MACROS (1u) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_MACROS (1u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Number of interrupt request inputs to CM0 */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_INT_NR (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_INT_NR (28u) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_INT_NR (32u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Presence of the BLESS IP block */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_BLESS (0 != 0) + #define CY_IP_BLESSV3 (CYIPBLOCK_m0s8bless_VERSION == 3) + #else + #define CY_IP_BLESS (0 != 0) + #define CY_IP_BLESSV3 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_USBDEV (0 != 0) + #else + #define CY_IP_USBDEV (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /*************************************************************************** + * Devices with the SPCIF_SYNCHRONOUS parameter set to one will not use + * the 36MHz Oscillator for Flash operation. Instead, flash write function + * ensures that the charge pump clock and the higher frequency clock (HFCLK) + * are set to the IMO at 48MHz prior to writing the flash. + ***************************************************************************/ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_SPCIF_SYNCHRONOUS (1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SPCIF_SYNCHRONOUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Watch Crystal Oscillator (WCO) is present (32kHz) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #if (CY_IP_BLESSV3) + #define CY_IP_WCO_WCOV2 (0 == 0) + #define CY_IP_WCO_BLESS (0 != 0) + #else + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_BLESS (0 == 0) + #endif + #else + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (1 == 1) + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_SRSSV2 (-1 == 1) + #endif /* (CY_IP_BLESS) */ + #else + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_WCOV2 (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_WCO (CY_IP_WCO_BLESS || CY_IP_WCO_WCO || CY_IP_WCO_WCOV2 || CY_IP_WCO_SRSSV2) + + /* External Crystal Oscillator is present (high frequency) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #define CY_IP_ECO_SRSSLT (0 != 0) + + #if (CY_IP_BLESSV3) + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 == 0) + #else + #define CY_IP_ECO_BLESS (0 == 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #endif + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #define CY_IP_ECO_SRSSV2 (-1 == 1) + #define CY_IP_ECO_SRSSLT ((1 != 0) && (1 != 0)) + #endif /* (CY_IP_BLESS) */ + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_BLESSV3 (0 != 0) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #define CY_IP_ECO_SRSSLT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_ECO (CY_IP_ECO_BLESS || CY_IP_ECO_SRSSV2 || CY_IP_ECO_BLESSV3 || CY_IP_ECO_SRSSLT) + + /* PLL is present */ + #if (CY_IP_HOBTO_DEVICE) + #if(CY_IP_SRSSV2) + #define CY_IP_PLL ((-1 != 0) || \ + (-1 != 0)) + + #define CY_IP_PLL_NR (-1u + \ + -1u) + + #elif (CY_IP_SRSSLT) + #define CY_IP_PLL (1 == 1) + + #define CY_IP_PLL_NR (1) + #else + #define CY_IP_PLL (0 != 0) + #define CY_IP_PLL_NR (0) + #endif /* (CY_IP_SRSSV2) */ + #else + #define CY_IP_PLL (0 != 0) + #define CY_IP_PLL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Clock Source clk_lf implemented in SysTick Counter. When 0, not implemented, 1=implemented */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_SYSTICK_LFCLK_SOURCE (1 != 0) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash Macro 0 has extra rows */ + #if (CY_IP_HOBTO_DEVICE) + #ifdef CYREG_SFLASH_MACRO_0_FREE_SFLASH0 + #define CY_SFLASH_XTRA_ROWS (0 == 0) + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* CYREG_SFLASH_MACRO_0_FREE_SFLASH0 */ + + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + #if (CY_IP_USBDEV) + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 != 0) + #endif /* (CY_IP_USBDEV) */ + + + #if (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 != 0) + #endif /* (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) */ + + + /* DW/DMA Controller present (0=No, 1=Yes) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_DMAC_PRESENT (-1 == 1) + #else + #define CY_IP_DMAC_PRESENT (1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_DMAC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_PASS (0 == 1) + #else + #define CY_IP_PASS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + + /* Number of external slave ports on System Interconnect */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SL_NR (-1) + #else + #define CY_IP_SL_NR (3) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + +#else + + #if (CY_PSOC3) + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #else /* PSoC 5LP */ + #define CY_SYSTICK_LFCLK_SOURCE (0 == 0) + #endif /* (CY_PSOC3) */ + +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* The components version defines. Available started from cy_boot 4.20 +* Use the following construction in order to identify cy_boot version: +* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20) +*******************************************************************************/ +#define CY_BOOT_4_20 (420u) +#define CY_BOOT_5_0 (500u) +#define CY_BOOT_5_10 (510u) +#define CY_BOOT_5_20 (520u) +#define CY_BOOT_5_30 (530u) +#define CY_BOOT_5_40 (540u) +#define CY_BOOT_5_50 (550u) +#define CY_BOOT_5_60 (560u) +#define CY_BOOT_5_70 (570u) +#define CY_BOOT_VERSION (CY_BOOT_5_70) + + +/******************************************************************************* +* Base Types. Acceptable types from MISRA-C specifying signedness and size. +*******************************************************************************/ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef float float32; + +#if(!CY_PSOC3) + + typedef double float64; + typedef long long int64; + typedef unsigned long long uint64; + +#endif /* (!CY_PSOC3) */ + +/* Signed or unsigned depending on compiler selection */ +typedef char char8; + + +/******************************************************************************* +* Memory address functions prototypes +*******************************************************************************/ +#if(CY_PSOC3) + + /*************************************************************************** + * Prototypes for absolute memory address functions (cymem.a51) with built-in + * endian conversion. These functions should be called through the + * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros. + ***************************************************************************/ + extern uint8 cyread8 (const volatile void far *addr); + extern void cywrite8 (volatile void far *addr, uint8 value); + + extern uint16 cyread16 (const volatile void far *addr); + extern uint16 cyread16_nodpx(const volatile void far *addr); + + extern void cywrite16 (volatile void far *addr, uint16 value); + extern void cywrite16_nodpx(volatile void far *addr, uint16 value); + + extern uint32 cyread24 (const volatile void far *addr); + extern uint32 cyread24_nodpx(const volatile void far *addr); + + extern void cywrite24 (volatile void far *addr, uint32 value); + extern void cywrite24_nodpx(volatile void far *addr, uint32 value); + + extern uint32 cyread32 (const volatile void far *addr); + extern uint32 cyread32_nodpx(const volatile void far *addr); + + extern void cywrite32 (volatile void far *addr, uint32 value); + extern void cywrite32_nodpx(volatile void far *addr, uint32 value); + + + /*************************************************************************** + * Memory access routines from cymem.a51 for the generated device + * configuration code. These functions may be subject to change in future + * revisions of the cy_boot component and they are not available for all + * devices. Most code should use memset or memcpy instead. + ***************************************************************************/ + void cymemzero(void far *addr, uint16 size); + void cyconfigcpy(uint16 size, const void far *src, void far *dest) large; + void cyconfigcpycode(uint16 size, const void code *src, void far *dest); + + #define CYCONFIGCPY_DECLARED (1) + +#else + + /* Prototype for function to set 24-bit register. Located at cyutils.c */ + extern void CySetReg24(uint32 volatile * addr, uint32 value); + + #if(CY_PSOC4) + + extern uint32 CyGetReg24(uint32 const volatile * addr); + + #endif /* (CY_PSOC4) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Memory model definitions. To allow code to be 8051-ARM agnostic. +*******************************************************************************/ +#if(CY_PSOC3) + + #define CYBDATA bdata + #define CYBIT bit + #define CYCODE code + #define CYCOMPACT compact + #define CYDATA data + #define CYFAR far + #define CYIDATA idata + #define CYLARGE large + #define CYPDATA pdata + #define CYREENTRANT reentrant + #define CYSMALL small + #define CYXDATA xdata + #define XDATA xdata + + #define CY_NOINIT + +#else + + #define CYBDATA + #define CYBIT uint8 + #define CYCODE + #define CYCOMPACT + #define CYDATA + #define CYFAR + #define CYIDATA + #define CYLARGE + #define CYPDATA + #define CYREENTRANT + #define CYSMALL + #define CYXDATA + #define XDATA + + #if defined(__ARMCC_VERSION) + + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + + /* Specifies a minimum alignment (in bytes) for variables of the + * specified type. + */ + #define CY_ALIGN(align) __align(align) + + + /* Attached to an enum, struct, or union type definition, specified that + * the minimum required memory be used to represent the type. + */ + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE __inline + #elif defined (__GNUC__) + + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_ALIGN(align) __attribute__ ((aligned(align))) + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE inline + #elif defined (__ICCARM__) + + #define CY_NOINIT __no_init + #define CY_NORETURN __noreturn + #define CY_PACKED __packed + #define CY_PACKED_ATTR + #define CY_INLINE inline + #endif /* (__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC3) + + /* 8051 naturally returns 8 bit value. */ + typedef unsigned char cystatus; + +#else + + /* ARM naturally returns 32 bit value. */ + typedef unsigned long cystatus; + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Hardware Register Types. +*******************************************************************************/ +typedef volatile uint8 CYXDATA reg8; +typedef volatile uint16 CYXDATA reg16; +typedef volatile uint32 CYXDATA reg32; + + +/******************************************************************************* +* Interrupt Types and Macros +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_ISR(FuncName) void FuncName (void) interrupt 0 + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (CYCODE * cyisraddress)(void); + +#else + + #define CY_ISR(FuncName) void FuncName (void) + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (* cyisraddress)(void); + + #if defined (__ICCARM__) + typedef union { cyisraddress __fun; void * __ptr; } intvec_elem; + #endif /* defined (__ICCARM__) */ + +#endif /* (CY_PSOC3) */ + + +#define CY_M_PI (3.14159265358979323846264338327) + + +/** +* \addtogroup group_register_access +A library of macros provides read and write access to the registers of the device. These macros are used with the +defined values made available in the generated cydevice_trm.h and cyfitter.h files. Access to registers should be made +using these macros and not the functions that are used to implement the macros. This allows for device independent code +generation. + +The PSoC 4 processor architecture use little endian ordering. + +SRAM and Flash storage in all architectures is done using the endianness of the architecture and compilers. However, +the registers in all these chips are laid out in little endian order. These macros allow register accesses to match this +little endian ordering. If you perform operations on multi-byte registers without using these macros, you must consider +the byte ordering of the specific architecture. Examples include usage of DMA to transfer between memory and registers, +as well as function calls that are passed an array of bytes in memory. + +The PSoC 4 requires these accesses to be aligned to the width of the transaction. + +The PSoC 4 requires peripheral register accesses to match the hardware register size. Otherwise, the peripheral might +ignore the transfer and Hard Fault exception will be generated. + +*/ + +/** @} group_register_access */ + + +/** +* \addtogroup group_register_access_macros Register Access +* \ingroup group_register_access +* @{ +*/ + +#if(CY_PSOC3) + /******************************************************************************* + * Macro Name: CY_GET_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + + /******************************************************************************* + * Macro Name: CY_GET_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value) + + + /******************************************************************************* + * Macro Name: CY_GET_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * Identical to \ref CY_GET_REG8 for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * Identical to \ref CY_SET_REG8 for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) + +#else + + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) (*((const reg16 *)(addr))) + #define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value)) + + + #define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value)) + #if(CY_PSOC4) + #define CY_GET_REG24(addr) CyGetReg24((const reg32 *) (addr)) + #else + #define CY_GET_REG24(addr) (*((const reg32 *)(addr)) & 0x00FFFFFFu) + #endif /* (CY_PSOC4) */ + + + #define CY_GET_REG32(addr) (*((const reg32 *)(addr))) + #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value)) + + /* To allow code to be 8051-ARM agnostic. */ + #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr) + #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value) + + #define CY_GET_XTND_REG16(addr) CY_GET_REG16(addr) + #define CY_SET_XTND_REG16(addr, value) CY_SET_REG16(addr, value) + + #define CY_GET_XTND_REG24(addr) CY_GET_REG24(addr) + #define CY_SET_XTND_REG24(addr, value) CY_SET_REG24(addr, value) + + #define CY_GET_XTND_REG32(addr) CY_GET_REG32(addr) + #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value) + +#endif /* (CY_PSOC3) */ +/** @} group_register_access_macros */ + + +/** +* \addtogroup group_register_access_bits Bit Manipulation +* \ingroup group_register_access +* @{ +*/ + +#if(CY_PSOC4) + + /******************************************************************************* + * Macro Name: CY_GET_FIELD_MASK(regSize, bitFieldName) + ****************************************************************************//** + * + * Returns the bit field mask for the specified register size and bit field + * name. + * + * \param regSize Size of the register in bits. + * \param bitFieldName Fully qualified name of the bit field. The biFieldName + * is automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * \return Returns the bit mask. + * + *******************************************************************************/ + #define CY_GET_FIELD_MASK(regSize, bitFieldName) \ + ((((uint ## regSize) 0xFFFFFFFFu << ((uint32)(regSize) - bitFieldName ## __SIZE - bitFieldName ## __OFFSET)) >>\ + ((uint32)(regSize) - bitFieldName ## __SIZE)) << bitFieldName ## __OFFSET) + + + /******************************************************************************* + * Macro Name: CY_GET_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register will remain uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on 32-bit and 16-bit width registers will generate a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG8_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG8((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG8_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 8-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers, generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG8_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG8((registerName), \ + ((CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)) | \ + (((uint8)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG8_FIELD(registerName, bitFieldName) \ + (CY_SET_REG8((registerName), (CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hardfault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG16_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG16((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 16-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerNam The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG16_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG16((registerName), \ + ((CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)) | \ + (((uint16)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG16_FIELD(registerName, bitFieldName)\ + (CY_SET_REG16((registerName), (CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The Fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields, please, refer to + * a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, otherwise. + * The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG32_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG32((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 32-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_SET_REG32_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG32((registerName), \ + ((CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)) | \ + (((uint32)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG32_FIELD(registerName, bitFieldName) \ + (CY_SET_REG32((registerName), (CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_FIELD(regValue, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_FIELD(regValue, bitFieldName) \ + (((regValue) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_FIELD(regValue, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value within a given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads and \ref CY_SET_REG32 for atomic writes. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to the respective PSoC family register TRM. + * + *******************************************************************************/ + #define CY_SET_FIELD(regValue, bitFieldName, value) \ + ((regValue) = \ + ((((uint32)(value) & (~(0xFFFFFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET)) | \ + ((uint32)(regValue) & (((~(0xFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET))) + +#endif /* (CY_PSOC4) */ + +/** @} group_register_access_bits */ + + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/* Get 8 bits of 16 bit value. */ +#define LO8(x) ((uint8) ((x) & 0xFFu)) +#define HI8(x) ((uint8) ((uint16)(x) >> 8)) + +/* Get 16 bits of 32 bit value. */ +#define LO16(x) ((uint16) ((x) & 0xFFFFu)) +#define HI16(x) ((uint16) ((uint32)(x) >> 16)) + +/* Swap the byte ordering of 32 bit value */ +#define CYSWAP_ENDIAN32(x) \ + ((uint32)((((x) >> 24) & 0x000000FFu) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) + +/* Swap the byte ordering of 16 bit value */ +#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | (((x) >> 8) & 0x00FFu))) + + +/******************************************************************************* +* Defines the standard return values used in PSoC content. A function is +* not limited to these return values but can use them when returning standard +* error values. Return values can be overloaded if documented in the function +* header. On the 8051 a function can use a larger return type but still use the +* defined return codes. +* +* Zero is successful, all other values indicate some form of failure. 1 - 0x7F - +* standard defined values; 0x80 - ... - user or content defined values. +*******************************************************************************/ +#define CYRET_SUCCESS (0x00u) /* Successful */ +#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */ +#define CYRET_MEMORY (0x03u) /* Memory related failure */ +#define CYRET_LOCKED (0x04u) /* Resource lock failure */ +#define CYRET_EMPTY (0x05u) /* No more objects available */ +#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08u) /* Operation completed */ +#define CYRET_CANCELED (0x09u) /* Operation canceled */ +#define CYRET_TIMEOUT (0x10u) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */ + + +/******************************************************************************* +* Intrinsic Defines: Processor NOP instruction +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_NOP _nop_() + +#else + + #if defined(__ARMCC_VERSION) + + /* RealView */ + #define CY_NOP __nop() + + #else + + /* GCC */ + #define CY_NOP __asm("NOP\n") + + #endif /* defined(__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 5.10 +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CY_IP_S8FS CY_IP_FS + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 3.10 +*******************************************************************************/ +#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#define CY_UDB_V1 (!CY_UDB_V0) +#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) + #define CY_PSOC4SF (CY_PSOC4D) +#else + #define CY_PSOC4D (0u != 0u) + #define CY_PSOC4SF (CY_PSOC4D) +#endif /* CYDEV_CHIP_MEMBER_4D */ +#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#ifdef CYDEV_CHIP_MEMBER_5B + #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B) +#else + #define CY_PSOC5LP (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_5B */ + +#if (!CY_PSOC4) + + /* Device is PSoC 3 and the revision is ES2 or earlier */ + #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2)) + + /* Device is PSoC 3 and the revision is ES3 or later */ + #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3)) + + /* Device is PSoC 5 and the revision is ES1 or earlier */ + #define CY_PSOC5_ES1 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1)) + + /* Device is PSoC 5 and the revision is ES2 or later */ + #define CY_PSOC5_ES2 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1)) + +#endif /* (!CY_PSOC4) */ + +#endif /* CY_BOOT_CYTYPES_H */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/cyutils.c b/cores/asr650x/projects/PSoC4/cyutils.c new file mode 100644 index 00000000..a9eb657a --- /dev/null +++ b/cores/asr650x/projects/PSoC4/cyutils.c @@ -0,0 +1,75 @@ +/***************************************************************************//** +* \file cyutils.c +* \version 5.70 +* +* \brief Provides a function to handle 24-bit value writes. +* +******************************************************************************** +* \copyright +* Copyright 2008-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" + +#if (!CY_PSOC3) + + /*************************************************************************** + * Function Name: CySetReg24 + ************************************************************************//** + * + * Writes a 24-bit value to the specified register. + * + * \param addr The address where data must be written. + * \param value The data that must be written. + * + * \reentrant No + * + ***************************************************************************/ + void CySetReg24(uint32 volatile * addr, uint32 value) + { + uint8 volatile *tmpAddr; + + tmpAddr = (uint8 volatile *) addr; + + tmpAddr[0u] = (uint8) value; + tmpAddr[1u] = (uint8) (value >> 8u); + tmpAddr[2u] = (uint8) (value >> 16u); + } + + + #if(CY_PSOC4) + + /*************************************************************************** + * Function Name: CyGetReg24 + ************************************************************************//** + * + * Reads the 24-bit value from the specified register. + * + * \param addr The address where data must be read. + * + * \reentrant No + * + ***************************************************************************/ + uint32 CyGetReg24(uint32 const volatile * addr) + { + uint8 const volatile *tmpAddr; + uint32 value; + + tmpAddr = (uint8 const volatile *) addr; + + value = (uint32) tmpAddr[0u]; + value |= ((uint32) tmpAddr[1u] << 8u ); + value |= ((uint32) tmpAddr[2u] << 16u); + + return(value); + } + + #endif /*(CY_PSOC4)*/ + +#endif /* (!CY_PSOC3) */ + + +/* [] END OF FILE */ diff --git a/cores/asr650x/projects/PSoC4/exported_symbols.txt b/cores/asr650x/projects/PSoC4/exported_symbols.txt new file mode 100644 index 00000000..e69de29b diff --git a/cores/asr650x/projects/PSoC4/project.h b/cores/asr650x/projects/PSoC4/project.h new file mode 100644 index 00000000..4d22057e --- /dev/null +++ b/cores/asr650x/projects/PSoC4/project.h @@ -0,0 +1,69 @@ +/******************************************************************************* +* File Name: project.h +* +* PSoC Creator 4.2 +* +* Description: +* It contains references to all generated header files and should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "cyfitter_cfg.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "cydisabledsheets.h" +#include "UART_1.h" +#include "UART_1_SPI_UART.h" +#include "UART_1_PINS.h" +#include "UART_1_SPI_UART_PVT.h" +#include "UART_1_PVT.h" +#include "UART_1_BOOT.h" +#include "SPI_1.h" +#include "SPI_1_SPI_UART.h" +#include "SPI_1_PINS.h" +#include "SPI_1_SPI_UART_PVT.h" +#include "SPI_1_PVT.h" +#include "SPI_1_BOOT.h" +#include "RTC.h" +#include "Bootloadable_1.h" +#include "UART_1_SCBCLK.h" +#include "UART_1_rx_wake.h" +#include "UART_1_rx_wake_aliases.h" +#include "UART_1_RX_WAKEUP_IRQ.h" +#include "UART_1_tx.h" +#include "UART_1_tx_aliases.h" +#include "UART_1_SCB_IRQ.h" +#include "SPI_1_SCBCLK.h" +#include "SPI_1_sclk_m.h" +#include "SPI_1_sclk_m_aliases.h" +#include "SPI_1_miso_m.h" +#include "SPI_1_miso_m_aliases.h" +#include "SPI_1_mosi_m.h" +#include "SPI_1_mosi_m_aliases.h" +#include "cy_em_eeprom.h" +#include "CyFlash.h" +#include "CyLib.h" +#include "cyPm.h" +#include "cytypes.h" +#include "cypins.h" +#include "core_cm0plus_psoc4.h" +#include "CyDMA.h" +#include "CyLFClk.h" +#include "ASR_Arduino.h" +#include "irq.h" +#include "I2C.h" +#include "I2C_I2C.h" +#include "ADC_SAR_Seq.h" +#include "PWM1.h" +#include "PWM2.h" +#include "PWM1_ISR.h" +#include "PWM2_ISR.h" + +/*[]*/ + diff --git a/cores/asr650x/projects/PSoC4/renamed_symbols.txt b/cores/asr650x/projects/PSoC4/renamed_symbols.txt new file mode 100644 index 00000000..e69de29b diff --git a/cores/asr650x/projects/cyapicallbacks.h b/cores/asr650x/projects/cyapicallbacks.h new file mode 100644 index 00000000..e618a6ed --- /dev/null +++ b/cores/asr650x/projects/cyapicallbacks.h @@ -0,0 +1,20 @@ +/* ======================================== + * + * Copyright YOUR COMPANY, THE YEAR + * All Rights Reserved + * UNPUBLISHED, LICENSED SOFTWARE. + * + * CONFIDENTIAL AND PROPRIETARY INFORMATION + * WHICH IS THE PROPERTY OF your company. + * + * ======================================== +*/ +#ifndef CYAPICALLBACKS_H +#define CYAPICALLBACKS_H + + +/*Define your macro callbacks here */ +/*For more information, refer to the Writing Code topic in the PSoC Creator Help.*/ + +#endif /* CYAPICALLBACKS_H */ +/* [] */ diff --git a/libraries/AT24C32N/examples/AT24C32N/AT24C32N.ino b/libraries/AT24C32N/examples/AT24C32N/AT24C32N.ino new file mode 100644 index 00000000..e7b71c7d --- /dev/null +++ b/libraries/AT24C32N/examples/AT24C32N/AT24C32N.ino @@ -0,0 +1,59 @@ +#include +#include + + +EEPROM_AT24C32N rtcEeprom; +#define AT24C32N_ADDRESS 0x50 + +uint16_t StartP; + +void setup () +{ + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW); //SET POWER + Serial.begin(115200); + Wire.begin(); // SDA, SCL + + Serial.println(""); + Serial.println(""); + Serial.println("Started"); + delay(1000); + StartP = 5; +} + + + +void loop () +{ + uint16_t VarLen; + char VarToRead[70]; + char ToWrite[] = "abcdefghijklmonpqrstuvwxyz0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + uint8_t lp; + + VarLen = strlen(ToWrite); + + Serial.printf("About to write [%s] \r\nwhich is [%d] bytes long at memory address [%d]\r\n",ToWrite,VarLen,StartP); + + rtcEeprom.WriteBytes(StartP,VarLen,ToWrite); + memset(VarToRead,0,70); + rtcEeprom.RetrieveBytes(VarToRead, VarLen, StartP, true); + Serial.printf("Wrote : [%s]\r\nReceived : [%s]",ToWrite,VarToRead); + + if(strcmp(ToWrite,VarToRead)!=0) + { + Serial.print("FAIL FAIL "); + for (lp=0;lp4000) StartP=4; + Serial.printf("\n"); + delay(10000); +} + + diff --git a/libraries/AT24C32N/library.properties b/libraries/AT24C32N/library.properties new file mode 100644 index 00000000..c4cf2da1 --- /dev/null +++ b/libraries/AT24C32N/library.properties @@ -0,0 +1,9 @@ +name=AT24C32N +version=1.0 +author=Heltec +maintainer= +sentence= +paragraph= +category=Timing +url= +architectures=CubeCell diff --git a/libraries/AT24C32N/src/AT24C32N.cpp b/libraries/AT24C32N/src/AT24C32N.cpp new file mode 100644 index 00000000..017cb112 --- /dev/null +++ b/libraries/AT24C32N/src/AT24C32N.cpp @@ -0,0 +1,87 @@ +// The AT24C32N is an EEPROM, usually added to the DS1307 breakout board +// - Endurance: 1 Million Write Cycles +// - Data Retention: 100 Years + +#include +#include + +#define AT24C32N_ADDRESS 0x50 +#define MaxMemSize 4096 // 32,768 bits + + + #include // capital A so it is error prone on case-sensitive filesystems + // Macro to deal with the difference in I2C write functions from old and new Arduino versions. + #define _I2C_WRITE write + #define _I2C_READ read + +//-------------------------------------------------------------------------------- +void EEPROM_AT24C32N::begin(int sda, int scl) +{ +Wire.begin(sda,scl); +// there is also write protection and a cycle memory reset sequence that can be called here +} +//-------------------------------------------------------------------------------- +void EEPROM_AT24C32N::SetMemLoc(uint16_t address) +{ +byte HByte,LByte; + +HByte = address >> 8; Wire._I2C_WRITE(HByte); +LByte = address - (HByte << 8); Wire._I2C_WRITE(LByte); +delay(10); +} +//-------------------------------------------------------------------------------- +bool EEPROM_AT24C32N::WriteBytes(uint16_t StartAddress,uint16_t SizeOfVar,void* ValToWrite) +{ +uint8_t lp,xval; + +if ((SizeOfVar+StartAddress)>MaxMemSize) {Serial.println("Error - Fatal : Size problem");return(false);} +//-- +for (lp = 0; lp0) {Wire.endTransmission();delay(10);} + Wire.beginTransmission(AT24C32N_ADDRESS);delay(10); + SetMemLoc(StartAddress+lp); + } + Wire._I2C_WRITE(xval); + delay(10); + } +Wire.endTransmission(); +delay(10); +return(true); +} +//-------------------------------------------------------------------------------- +bool EEPROM_AT24C32N::WriteBytes(uint16_t StartAddress,char* ValToWrite) +{ +uint16_t vlen; + +vlen = strlen(ValToWrite)+1; // +1 to allow for terminating zero +return(WriteBytes(StartAddress,vlen,(void*)ValToWrite)); +} +//-------------------------------------------------------------------------------- +bool EEPROM_AT24C32N::RetrieveBytes(char* buf, uint16_t StorageVarSize, uint16_t StartAddress, bool ZeroTerminated) +{ +uint16_t addrByte,lp; +char ReadByte; + +addrByte = StartAddress+StorageVarSize; +if (addrByte>MaxMemSize) {Serial.println("Error - Fatal : Size problem");return(false);} +for (lp = 0; lp < StorageVarSize; ++lp) + { + if ((((StartAddress+lp) % 32)==0) || (lp==0)) // internally organized as 256 pages of 32 bytes each + { + Wire.beginTransmission(AT24C32N_ADDRESS);delay(10); + SetMemLoc(StartAddress+lp); + Wire.endTransmission();delay(10); + Wire.requestFrom(AT24C32N_ADDRESS, (StorageVarSize-lp));delay(10); + } + ReadByte = Wire._I2C_READ(); + buf[lp] = ReadByte; + if (ZeroTerminated && (!ReadByte)) break; // if zero terminated and a zero byte was just read then get out. + delay(10); + } +return(true); +} +//----------------------------------------------------------------------------- \ No newline at end of file diff --git a/libraries/AT24C32N/src/AT24C32N.h b/libraries/AT24C32N/src/AT24C32N.h new file mode 100644 index 00000000..504aff92 --- /dev/null +++ b/libraries/AT24C32N/src/AT24C32N.h @@ -0,0 +1,18 @@ +#ifndef AT24C32_h +#define AT24C32_h + +// The AT24C32 is an EEPROM, usually added to the DS1307 breakout board +// - Endurance: 1 Million Write Cycles +// ** note that the DS1307 already has 56 bytes NVRAM, so not sure what to write here in 4kb! + +class EEPROM_AT24C32N + { + public: + void begin(int sda, int scl); + bool WriteBytes(uint16_t StartAddress,uint16_t SizeOfVar,void* ValToWrite); + bool WriteBytes(uint16_t StartAddress,char* ValToWrite); + bool RetrieveBytes(char* buf, uint16_t StorageVarSize, uint16_t StartAddress, bool ZeroTerminated); + private: + void SetMemLoc(uint16_t address); + }; +#endif \ No newline at end of file diff --git a/libraries/BH1750/examples/BH1750advanced/BH1750advanced.ino b/libraries/BH1750/examples/BH1750advanced/BH1750advanced.ino new file mode 100644 index 00000000..c7361d60 --- /dev/null +++ b/libraries/BH1750/examples/BH1750advanced/BH1750advanced.ino @@ -0,0 +1,96 @@ +/* + + Advanced BH1750 library usage example + + This example has some comments about advanced usage features. + + Connection: + + VCC -> 3V3 or 5V + GND -> GND + SCL -> SCL + SDA -> SDA + ADD -> (not connected) or GND + + ADD pin is used to set sensor I2C address. If it has voltage greater or equal to + 0.7VCC voltage (e.g. you've connected it to VCC) the sensor address will be + 0x5C. In other case (if ADD voltage less than 0.7 * VCC) the sensor address will + be 0x23 (by default). + +*/ + +#include +#include + +/* + BH1750 can be physically configured to use two I2C addresses: + - 0x23 (most common) (if ADD pin had < 0.7VCC voltage) + - 0x5C (if ADD pin had > 0.7VCC voltage) + + Library uses 0x23 address as default, but you can define any other address. + If you had troubles with default value - try to change it to 0x5C. + +*/ +BH1750 lightMeter(0x23); + +void setup(){ + + Serial.begin(115200); + + //Vext ON + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW); + + + /* + + BH1750 has six different measurement modes. They are divided in two groups; + continuous and one-time measurements. In continuous mode, sensor continuously + measures lightness value. In one-time mode the sensor makes only one + measurement and then goes into Power Down mode. + + Each mode, has three different precisions: + + - Low Resolution Mode - (4 lx precision, 16ms measurement time) + - High Resolution Mode - (1 lx precision, 120ms measurement time) + - High Resolution Mode 2 - (0.5 lx precision, 120ms measurement time) + + By default, the library uses Continuous High Resolution Mode, but you can + set any other mode, by passing it to BH1750.begin() or BH1750.configure() + functions. + + [!] Remember, if you use One-Time mode, your sensor will go to Power Down + mode each time, when it completes a measurement and you've read it. + + Full mode list: + + BH1750_CONTINUOUS_LOW_RES_MODE + BH1750_CONTINUOUS_HIGH_RES_MODE (default) + BH1750_CONTINUOUS_HIGH_RES_MODE_2 + + BH1750_ONE_TIME_LOW_RES_MODE + BH1750_ONE_TIME_HIGH_RES_MODE + BH1750_ONE_TIME_HIGH_RES_MODE_2 + + */ + + // begin returns a boolean that can be used to detect setup problems. + if (lightMeter.begin(BH1750::CONTINUOUS_HIGH_RES_MODE)) { + Serial.println(F("BH1750 Advanced begin")); + } + else { + Serial.println(F("Error initialising BH1750")); + } + +} + + +void loop() { + + float lux = lightMeter.readLightLevel(); + Serial.print("Light: "); + Serial.print(lux); + Serial.println(" lx"); + delay(1000); + +} diff --git a/libraries/BH1750/examples/BH1750autoadjust/BH1750autoadjust.ino b/libraries/BH1750/examples/BH1750autoadjust/BH1750autoadjust.ino new file mode 100644 index 00000000..c9973a1a --- /dev/null +++ b/libraries/BH1750/examples/BH1750autoadjust/BH1750autoadjust.ino @@ -0,0 +1,96 @@ +/* + + Example of BH1750 library usage. + + This example initialises the BH1750 object using the default high resolution + one shot mode and then makes a light level reading every five seconds. + + After the measurement the MTreg value is changed according to the result: + lux > 40000 ==> MTreg = 32 + lux < 40000 ==> MTreg = 69 (default) + lux < 10 ==> MTreg = 138 + Remember to test your specific sensor! Maybe the MTreg value range from 32 + up to 254 is not applicable to your unit. + + Connection: + + VCC -> 3V3 or 5V + GND -> GND + SCL -> SCL + SDA -> + ADD -> (not connected) or GND + + ADD pin is used to set sensor I2C address. If it has voltage greater or equal to + 0.7VCC voltage (e.g. you've connected it to VCC) the sensor address will be + 0x5C. In other case (if ADD voltage less than 0.7 * VCC) the sensor address will + be 0x23 (by default). + +*/ + +#include +#include + +BH1750 lightMeter; + +void setup(){ + + Serial.begin(115200); + + //Vext ON + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW); + + lightMeter.begin(BH1750::ONE_TIME_HIGH_RES_MODE); + //lightMeter.setMTreg(69); // not needed, only mentioning it + + Serial.println(F("BH1750 Test begin")); + +} + +void loop() { + //we use here the maxWait option due fail save + float lux = lightMeter.readLightLevel(true); + Serial.print(F("Light: ")); + Serial.print(lux); + Serial.println(F(" lx")); + + if (lux < 0) { + Serial.println(F("Error condition detected")); + } + else { + if (lux > 40000.0) { + // reduce measurement time - needed in direct sun light + if (lightMeter.setMTreg(32)) { + Serial.println(F("Setting MTReg to low value for high light environment")); + } + else { + Serial.println(F("Error setting MTReg to low value for high light environment")); + } + } + else { + if (lux > 10.0) { + // typical light environment + if (lightMeter.setMTreg(69)) { + Serial.println(F("Setting MTReg to default value for normal light environment")); + } + else { + Serial.println(F("Error setting MTReg to default value for normal light environment")); + } + } + else { + if (lux <= 10.0) { + //very low light environment + if (lightMeter.setMTreg(138)) { + Serial.println(F("Setting MTReg to high value for low light environment")); + } + else { + Serial.println(F("Error setting MTReg to high value for low light environment")); + } + } + } + } + + } + Serial.println(F("--------------------------------------")); + delay(5000); +} diff --git a/libraries/BH1750/examples/BH1750onetime/BH1750onetime.ino b/libraries/BH1750/examples/BH1750onetime/BH1750onetime.ino new file mode 100644 index 00000000..136830de --- /dev/null +++ b/libraries/BH1750/examples/BH1750onetime/BH1750onetime.ino @@ -0,0 +1,43 @@ +/* + + Example of BH1750 library usage. + + This example initialises the BH1750 object using the high resolution + one-time mode and then makes a light level reading every second. + + The BH1750 component starts up in default mode when it next powers up. + The BH1750 library automatically reconfigures the one-time mode in + preparation for the next measurement. + +*/ + +#include +#include + +BH1750 lightMeter; + +void setup(){ + + Serial.begin(115200); + + //Vext ON + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW); + + + lightMeter.begin(BH1750::ONE_TIME_HIGH_RES_MODE); + + Serial.println(F("BH1750 One-Time Test")); + +} + + +void loop() { + + float lux = lightMeter.readLightLevel(); + Serial.print("Light: "); + Serial.print(lux); + Serial.println(" lx"); + delay(1000); + +} diff --git a/libraries/BH1750/examples/BH1750test/BH1750test.ino b/libraries/BH1750/examples/BH1750test/BH1750test.ino new file mode 100644 index 00000000..eb66be03 --- /dev/null +++ b/libraries/BH1750/examples/BH1750test/BH1750test.ino @@ -0,0 +1,53 @@ +/* + + Example of BH1750 library usage. + + This example initialises the BH1750 object using the default high resolution + continuous mode and then makes a light level reading every second. + + Connection: + + VCC -> 3V3 or 5V + GND -> GND + SCL -> SCL + SDA -> SDA + ADD -> (not connected) or GND + + ADD pin is used to set sensor I2C address. If it has voltage greater or equal to + 0.7VCC voltage (e.g. you've connected it to VCC) the sensor address will be + 0x5C. In other case (if ADD voltage less than 0.7 * VCC) the sensor address will + be 0x23 (by default). + +*/ + + +#include +#include + +BH1750 lightMeter; + + +void setup(){ + + Serial.begin(115200); + + //Vext ON + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW); + + lightMeter.begin(); + + Serial.println(F("BH1750 Test begin")); + +} + + +void loop() { + + float lux = lightMeter.readLightLevel(); + Serial.print("Light: "); + Serial.print(lux); + Serial.println(" lx"); + delay(1000); + +} diff --git a/libraries/BH1750/keywords.txt b/libraries/BH1750/keywords.txt new file mode 100644 index 00000000..fa9a9216 --- /dev/null +++ b/libraries/BH1750/keywords.txt @@ -0,0 +1,34 @@ +####################################### +# Syntax Coloring Map For BH1750 +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +BH1750 KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +configure KEYWORD2 +setMTreg KEYWORD2 +readLightLevel KEYWORD2 + +####################################### +# Instances (KEYWORD2) +####################################### + + +####################################### +# Constants (LITERAL1) +####################################### +BH1750_CONTINUOUS_HIGH_RES_MODE LITERAL1 +BH1750_CONTINUOUS_HIGH_RES_MODE_2 LITERAL1 +BH1750_CONTINUOUS_LOW_RES_MODE LITERAL1 +BH1750_ONE_TIME_HIGH_RES_MODE LITERAL1 +BH1750_ONE_TIME_HIGH_RES_MODE_2 LITERAL1 +BH1750_ONE_TIME_LOW_RES_MODE LITERAL1 +BH1750_DEFAULT_MTREG LITERAL1 diff --git a/libraries/BH1750/library.properties b/libraries/BH1750/library.properties new file mode 100644 index 00000000..24986681 --- /dev/null +++ b/libraries/BH1750/library.properties @@ -0,0 +1,10 @@ +name=BH1750 +version=1.0 +author= +maintainer= +sentence= +paragraph= +category=Sensors +url= +architectures=CubeCell + diff --git a/libraries/BH1750/src/BH1750.cpp b/libraries/BH1750/src/BH1750.cpp new file mode 100644 index 00000000..e1ecbcf6 --- /dev/null +++ b/libraries/BH1750/src/BH1750.cpp @@ -0,0 +1,271 @@ +/* + + This is a library for the BH1750FVI Digital Light Sensor breakout board. + + The BH1750 board uses I2C for communication. Two pins are required to + interface to the device. Configuring the I2C bus is expected to be done + in user code. The BH1750 library doesn't do this automatically. + + Written by Christopher Laws, March, 2013. + +*/ + +#include "BH1750.h" +#include + +#define _delay_ms(ms) delay(ms) + + +// Legacy Wire.write() function fix +#define __wire_write(d) Wire.write(d) + + +// Legacy Wire.read() function fix +#define __wire_read() Wire.read() + +/** + * Constructor + * @params addr Sensor address (0x76 or 0x72, see datasheet) + * + * On most sensor boards, it was 0x76 + */ +BH1750::BH1750(byte addr) { + + BH1750_I2CADDR = addr; + +} + + +/** + * Configure sensor + * @param mode Measurement mode + */ +bool BH1750::begin(Mode mode) { + + Wire.begin(); + + // Configure sensor in specified mode + return configure(mode); + +} + +void BH1750::end() { + Wire.end(); +} + + +/** + * Configure BH1750 with specified mode + * @param mode Measurement mode + */ +bool BH1750::configure(Mode mode) { + + // default transmission result to a value out of normal range + byte ack = 5; + + // Check measurement mode is valid + switch (mode) { + + case BH1750::CONTINUOUS_HIGH_RES_MODE: + case BH1750::CONTINUOUS_HIGH_RES_MODE_2: + case BH1750::CONTINUOUS_LOW_RES_MODE: + case BH1750::ONE_TIME_HIGH_RES_MODE: + case BH1750::ONE_TIME_HIGH_RES_MODE_2: + case BH1750::ONE_TIME_LOW_RES_MODE: + + // Send mode to sensor + Wire.beginTransmission(BH1750_I2CADDR); + __wire_write((uint8_t)BH1750_MODE); + ack = Wire.endTransmission(); + + // Wait a few moments to wake up + _delay_ms(10); + break; + + default: + // Invalid measurement mode + Serial.println(F("[BH1750] ERROR: Invalid mode")); + break; + + } + + // Check result code + switch (ack) { + case 0: + BH1750_MODE = mode; + return true; + case 1: // too long for transmit buffer + Serial.println(F("[BH1750] ERROR: too long for transmit buffer")); + break; + case 2: // received NACK on transmit of address + Serial.println(F("[BH1750] ERROR: received NACK on transmit of address")); + break; + case 3: // received NACK on transmit of data + Serial.println(F("[BH1750] ERROR: received NACK on transmit of data")); + break; + case 4: // other error + Serial.println(F("[BH1750] ERROR: other error")); + break; + default: + Serial.println(F("[BH1750] ERROR: undefined error")); + break; + } + + return false; + +} + +/** + * Configure BH1750 MTreg value + * MT reg = Measurement Time register + * @param MTreg a value between 32 and 254. Default: 69 + * @return bool true if MTReg successful set + * false if MTreg not changed or parameter out of range + */ +bool BH1750::setMTreg(byte MTreg) { + //Bug: lowest value seems to be 32! + if (MTreg <= 31 || MTreg > 254) { + Serial.println(F("[BH1750] ERROR: MTreg out of range")); + return false; + } + byte ack = 5; + // Send MTreg and the current mode to the sensor + // High bit: 01000_MT[7,6,5] + // Low bit: 011_MT[4,3,2,1,0] + Wire.beginTransmission(BH1750_I2CADDR); + __wire_write((0b01000 << 3) | (MTreg >> 5)); + ack = Wire.endTransmission(); + Wire.beginTransmission(BH1750_I2CADDR); + __wire_write((0b011 << 5 ) | (MTreg & 0b11111)); + ack = ack | Wire.endTransmission(); + Wire.beginTransmission(BH1750_I2CADDR); + __wire_write(BH1750_MODE); + ack = ack | Wire.endTransmission(); + + // Wait a few moments to wake up + _delay_ms(10); + + // Check result code + switch (ack) { + case 0: + BH1750_MTreg = MTreg; + // Delay for specific continuous mode to get valid values + switch (BH1750_MODE) { + case BH1750::CONTINUOUS_LOW_RES_MODE: + _delay_ms(24 * BH1750_MTreg/(byte)BH1750_DEFAULT_MTREG); + break; + case BH1750::CONTINUOUS_HIGH_RES_MODE: + case BH1750::CONTINUOUS_HIGH_RES_MODE_2: + _delay_ms(180 * BH1750_MTreg/(byte)BH1750_DEFAULT_MTREG); + break; + default: + break; + } + return true; + case 1: // too long for transmit buffer + Serial.println(F("[BH1750] ERROR: too long for transmit buffer")); + break; + case 2: // received NACK on transmit of address + Serial.println(F("[BH1750] ERROR: received NACK on transmit of address")); + break; + case 3: // received NACK on transmit of data + Serial.println(F("[BH1750] ERROR: received NACK on transmit of data")); + break; + case 4: // other error + Serial.println(F("[BH1750] ERROR: other error")); + break; + default: + Serial.println(F("[BH1750] ERROR: undefined error")); + break; + } + + return false; +} + +/** + * Read light level from sensor + * The return value range differs if the MTreg value is changed. The global + * maximum value is noted in the square brackets. + * @return Light level in lux (0.0 ~ 54612,5 [117758,203]) + * -1 : no valid return value + * -2 : sensor not configured + */ +float BH1750::readLightLevel(bool maxWait) { + + if (BH1750_MODE == UNCONFIGURED) { + Serial.println(F("[BH1750] Device is not configured!")); + return -2.0; + } + + // Measurement result will be stored here + float level = -1.0; + + // Send mode to sensor + Wire.beginTransmission(BH1750_I2CADDR); + __wire_write((uint8_t)BH1750_MODE); + Wire.endTransmission(); + + // Wait for measurement to be taken. + // Measurements have a maximum measurement time and a typical measurement + // time. The maxWait argument determines which measurement wait time is + // used when a one-time mode is being used. The typical (shorter) + // measurement time is used by default and if maxWait is set to True then + // the maximum measurement time will be used. See data sheet pages 2, 5 + // and 7 for more details. + // A continuous mode measurement can be read immediately after re-sending + // the mode command. + + switch (BH1750_MODE) { + + case BH1750::ONE_TIME_LOW_RES_MODE: + maxWait ? _delay_ms(24 * BH1750_MTreg/(byte)BH1750_DEFAULT_MTREG) : _delay_ms(16 * BH1750_MTreg/(byte)BH1750_DEFAULT_MTREG); + break; + case BH1750::ONE_TIME_HIGH_RES_MODE: + case BH1750::ONE_TIME_HIGH_RES_MODE_2: + maxWait ? _delay_ms(180 * BH1750_MTreg/(byte)BH1750_DEFAULT_MTREG) :_delay_ms(120 * BH1750_MTreg/(byte)BH1750_DEFAULT_MTREG); + break; + default: + break; + } + + // Read two bytes from the sensor, which are low and high parts of the sensor + // value + if (2 == Wire.requestFrom((int)BH1750_I2CADDR, (int)2)) { + unsigned int tmp = 0; + tmp = __wire_read(); + tmp <<= 8; + tmp |= __wire_read(); + level = tmp; + } + + if (level != -1.0) { + // Print raw value if debug enabled + #ifdef BH1750_DEBUG + Serial.print(F("[BH1750] Raw value: ")); + Serial.println(level); + #endif + + if (BH1750_MTreg != BH1750_DEFAULT_MTREG) { + level *= (float)((byte)BH1750_DEFAULT_MTREG/(float)BH1750_MTreg); + // Print MTreg factor if debug enabled + #ifdef BH1750_DEBUG + Serial.print(F("[BH1750] MTreg factor: ")); + Serial.println( String((float)((byte)BH1750_DEFAULT_MTREG/(float)BH1750_MTreg)) ); + #endif + } + if (BH1750_MODE == BH1750::ONE_TIME_HIGH_RES_MODE_2 || BH1750_MODE == BH1750::CONTINUOUS_HIGH_RES_MODE_2) { + level /= 2; + } + // Convert raw value to lux + level /= BH1750_CONV_FACTOR; + + // Print converted value if debug enabled + #ifdef BH1750_DEBUG + Serial.print(F("[BH1750] Converted float value: ")); + Serial.println(level); + #endif + } + + return level; + +} diff --git a/libraries/BH1750/src/BH1750.h b/libraries/BH1750/src/BH1750.h new file mode 100644 index 00000000..61a840af --- /dev/null +++ b/libraries/BH1750/src/BH1750.h @@ -0,0 +1,76 @@ +/* + + This is a library for the BH1750FVI Digital Light Sensor breakout board. + + The BH1750 board uses I2C for communication. Two pins are required to + interface to the device. Configuring the I2C bus is expected to be done + in user code. The BH1750 library doesn't do this automatically. + + Datasheet: http://www.elechouse.com/elechouse/images/product/Digital%20light%20Sensor/bh1750fvi-e.pdf + + Written by Christopher Laws, March, 2013. + +*/ + +#ifndef BH1750_h +#define BH1750_h + + +#include +#include "Wire.h" + +// Uncomment, to enable debug messages +// #define BH1750_DEBUG + +// No active state +#define BH1750_POWER_DOWN 0x00 + +// Waiting for measurement command +#define BH1750_POWER_ON 0x01 + +// Reset data register value - not accepted in POWER_DOWN mode +#define BH1750_RESET 0x07 + +// Default MTreg value +#define BH1750_DEFAULT_MTREG 69 + +class BH1750 { + + public: + + enum Mode + { + UNCONFIGURED = 0, + // Measurement at 1 lux resolution. Measurement time is approx 120ms. + CONTINUOUS_HIGH_RES_MODE = 0x10, + // Measurement at 0.5 lux resolution. Measurement time is approx 120ms. + CONTINUOUS_HIGH_RES_MODE_2 = 0x11, + // Measurement at 4 lux resolution. Measurement time is approx 16ms. + CONTINUOUS_LOW_RES_MODE = 0x13, + // Measurement at 1 lux resolution. Measurement time is approx 120ms. + ONE_TIME_HIGH_RES_MODE = 0x20, + // Measurement at 0.5 lux resolution. Measurement time is approx 120ms. + ONE_TIME_HIGH_RES_MODE_2 = 0x21, + // Measurement at 4 lux resolution. Measurement time is approx 16ms. + ONE_TIME_LOW_RES_MODE = 0x23 + }; + + BH1750(byte addr = 0x23); + bool begin(Mode mode = CONTINUOUS_HIGH_RES_MODE); + void end(); + bool configure(Mode mode); + bool setMTreg(byte MTreg); + float readLightLevel(bool maxWait = false); + + private: + byte BH1750_I2CADDR; + byte BH1750_MTreg = (byte)BH1750_DEFAULT_MTREG; + // Correction factor used to calculate lux. Typical value is 1.2 but can + // range from 0.96 to 1.44. See the data sheet (p.2, Measurement Accuracy) + // for more information. + const float BH1750_CONV_FACTOR = 1.2; + Mode BH1750_MODE = UNCONFIGURED; + +}; + +#endif diff --git a/libraries/Basics/examples/ADC/ADC.ino b/libraries/Basics/examples/ADC/ADC.ino new file mode 100644 index 00000000..391829d6 --- /dev/null +++ b/libraries/Basics/examples/ADC/ADC.ino @@ -0,0 +1,18 @@ +#include "Arduino.h" + + +void setup() { + // put your setup code here, to run once: + Serial.begin(115200); +} + +uint16_t voltage; + +void loop() { + // put your main code here, to run repeatedly: + voltage=analogRead(ADC);//return the voltage in mV, max value can be read is 3300mV + Serial.print(millis()); + Serial.print(" "); + Serial.println(voltage); + delay(1000); +} diff --git a/libraries/Basics/examples/PWM/PWM.ino b/libraries/Basics/examples/PWM/PWM.ino new file mode 100644 index 00000000..cb9eb4b3 --- /dev/null +++ b/libraries/Basics/examples/PWM/PWM.ino @@ -0,0 +1,20 @@ +#include "Arduino.h" + + +void setup() { + // put your setup code here, to run once: + pinMode(PWM1,OUTPUT); + pinMode(PWM2,OUTPUT); +} + +uint8_t a=0; +uint8_t b=0; + +void loop() { + // put your main code here, to run repeatedly: + analogWrite(PWM1,a); + analogWrite(PWM2,b); + delay(1); + a++; + b--; +} diff --git a/libraries/Basics/examples/facorytest/facorytest.ino b/libraries/Basics/examples/facorytest/facorytest.ino new file mode 100644 index 00000000..242b2f56 --- /dev/null +++ b/libraries/Basics/examples/facorytest/facorytest.ino @@ -0,0 +1,222 @@ +#include "LoRaWan_APP.h" +#include "Arduino.h" +#include "heltec.h" +/* + * set LoraWan_RGB to 1,the RGB active + * RGB red means sending; + * RGB green means received done; + */ +#ifndef LoraWan_RGB +#define LoraWan_RGB 0 +#endif + +#define RF_FREQUENCY 470000000 // Hz + +#define TX_OUTPUT_POWER 14 // dBm + +#define LORA_BANDWIDTH 0 // [0: 125 kHz, + // 1: 250 kHz, + // 2: 500 kHz, + // 3: Reserved] +#define LORA_SPREADING_FACTOR 7 // [SF7..SF12] +#define LORA_CODINGRATE 1 // [1: 4/5, + // 2: 4/6, + // 3: 4/7, + // 4: 4/8] +#define LORA_PREAMBLE_LENGTH 8 // Same for Tx and Rx +#define LORA_SYMBOL_TIMEOUT 0 // Symbols +#define LORA_FIX_LENGTH_PAYLOAD_ON false +#define LORA_IQ_INVERSION_ON false + + +#define RX_TIMEOUT_VALUE 1000 +#define BUFFER_SIZE 30 // Define the payload size here + +char txpacket[BUFFER_SIZE]; +char rxpacket[BUFFER_SIZE]; + +static RadioEvents_t RadioEvents; +void OnTxDone( void ); +void OnTxTimeout( void ); +void OnRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ); +void displayInof(); +void sleep(void); +void RGB_test(void); + +typedef enum +{ + LOWPOWER, + RX, + TX +}States_t; + +int16_t txnumber; +States_t state; +bool sleepmode = false; +int16_t RSSI,rxSize; + + + +void setup() { + BoardInitMcu( ); + Heltec.begin(true /*DisplayEnable Enable*/, true /*Serial Enable*/); + Serial.begin(115200); + + RGB_test(); + + + txnumber=0; + RSSI=0; + + pinMode(P3_3,INPUT); + attachInterrupt(P3_3,sleep,FALLING); + RadioEvents.TxDone = OnTxDone; + RadioEvents.TxTimeout = OnTxTimeout; + RadioEvents.RxDone = OnRxDone; + + Radio.Init( &RadioEvents ); + Radio.SetChannel( RF_FREQUENCY ); + Radio.SetTxConfig( MODEM_LORA, TX_OUTPUT_POWER, 0, LORA_BANDWIDTH, + LORA_SPREADING_FACTOR, LORA_CODINGRATE, + LORA_PREAMBLE_LENGTH, LORA_FIX_LENGTH_PAYLOAD_ON, + true, 0, 0, LORA_IQ_INVERSION_ON, 3000 ); + + Radio.SetRxConfig( MODEM_LORA, LORA_BANDWIDTH, LORA_SPREADING_FACTOR, + LORA_CODINGRATE, 0, LORA_PREAMBLE_LENGTH, + LORA_SYMBOL_TIMEOUT, LORA_FIX_LENGTH_PAYLOAD_ON, + 0, true, 0, 0, LORA_IQ_INVERSION_ON, true ); + + state=TX; +} + + + +void loop() +{ + switch(state) + { + case TX: + delay(200); + txnumber++; + sprintf(txpacket,"%s","hello"); + sprintf(txpacket+strlen(txpacket),"%d",txnumber); + sprintf(txpacket+strlen(txpacket),"%s"," rssi : "); + sprintf(txpacket+strlen(txpacket),"%d",RSSI); + RGB_ON(0x100000,0); + + Serial.printf("\r\nsending packet \"%s\" , length %d\r\n",txpacket, strlen(txpacket)); + + Radio.Send( (uint8_t *)txpacket, strlen(txpacket) ); + state=LOWPOWER; + break; + case RX: + Serial.println("into RX mode"); + Radio.Rx( 0 ); + state=LOWPOWER; + break; + case LOWPOWER: + if(sleepmode) + { + Radio.Sleep( ); + Wire.end(); + detachInterrupt(RADIO_DIO_1); + RGB_OFF(); + pinMode(GPIO0,ANALOG); + pinMode(GPIO1,ANALOG); + pinMode(GPIO2,ANALOG); + pinMode(GPIO3,ANALOG); + pinMode(GPIO5,ANALOG); + pinMode(ADC,ANALOG); + } + LowPower_Handler(); + break; + default: + break; + } + Radio.IrqProcess( ); +} + +void OnTxDone( void ) +{ + Serial.print("TX done......"); + displayInof(); + RGB_ON(0,0); + state=RX; +} + +void OnTxTimeout( void ) +{ + Radio.Sleep( ); + Serial.print("TX Timeout......"); + state=TX; +} +void OnRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ) +{ + gpioOn(); + RSSI=rssi; + rxSize=size; + memcpy(rxpacket, payload, size ); + rxpacket[size]='\0'; + RGB_ON(0x001000,100); + RGB_ON(0,0); + Radio.Sleep( ); + + Serial.printf("\r\nreceived packet \"%s\" with RSSI %d , length %d\r\n",rxpacket,RSSI,rxSize); + Serial.println("wait to send next packet"); + displayInof(); + + state=TX; +} + +void displayInof() +{ + Heltec.display -> clear(); + Heltec.display -> drawString(0, 50, "Packet " + String(txnumber,DEC) + " sent done"); + Heltec.display -> drawString(0, 0, "Received Size" + String(rxSize,DEC) + " packages:"); + Heltec.display -> drawString(0, 15, rxpacket); + Heltec.display -> drawString(0, 30, "With RSSI " + String(RSSI,DEC)); + Heltec.display -> display(); +} + + +void sleep(void) +{ + delay(10); + if(digitalRead(P3_3)==0) + { + sleepmode = true; + } +} + +void RGB_test(void) +{ + Heltec.display -> drawString(0, 20, "RGB Testing"); + Heltec.display -> display(); + for(uint32_t i=0;i<=30;i++) + { + RGB_ON(i<<16,10); + } + for(uint32_t i=0;i<=30;i++) + { + RGB_ON(i<<8,10); + } + for(uint32_t i=0;i<=30;i++) + { + RGB_ON(i,10); + } + RGB_ON(0,0); +} + +void gpioOn(void) +{ + pinMode(GPIO0,OUTPUT); + pinMode(GPIO1,OUTPUT); + pinMode(GPIO2,OUTPUT); + pinMode(GPIO3,OUTPUT); + pinMode(GPIO5,OUTPUT); + digitalWrite(GPIO0,HIGH); + digitalWrite(GPIO1,HIGH); + digitalWrite(GPIO2,HIGH); + digitalWrite(GPIO3,HIGH); + digitalWrite(GPIO5,HIGH); +} diff --git a/libraries/Basics/examples/i2c_scan/i2c_scan.ino b/libraries/Basics/examples/i2c_scan/i2c_scan.ino new file mode 100644 index 00000000..a0d1ad3c --- /dev/null +++ b/libraries/Basics/examples/i2c_scan/i2c_scan.ino @@ -0,0 +1,68 @@ +/* Heltec Automation I2C scanner example (also it's a basic example how to use I2C1) + * + * ESP32 have two I2C (I2C0 and I2C1) bus + * + * OLED is connected to I2C0, so if scan with Wire (I2C0), the return address should be 0x3C. + * + * If you need scan other device address in I2C1... + * - Comment all Wire.***() codes; + * + * I2C scan example and I2C1 + * + * HelTec AutoMation, Chengdu, China + * 成都惠利特自动化科技有限公司 + * www.heltec.org + * + * this project also realess in GitHub: + * https://github.com/HelTecAutomation/Heltec_ESP32 + * */ + +#include "Arduino.h" +#include "Wire.h" + +void setup() +{ + Serial.begin(115200); + Wire.begin(); + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW);//set vext to high +} + +void loop() +{ + byte error, address; + int nDevices; + + Serial.println("Scanning..."); + + nDevices = 0; + for(address = 1; address < 127; address++ ) + { + Wire.beginTransmission(address); + error = Wire.endTransmission(); + + if (error == 0) + { + Serial.print("I2C device found at address 0x"); + if (address<16) + Serial.print("0"); + Serial.print(address,HEX); + Serial.println(" !"); + + nDevices++; + } + else if (error==4) + { + Serial.print("Unknown error at address 0x"); + if (address<16) + Serial.print("0"); + Serial.println(address,HEX); + } + } + if (nDevices == 0) + Serial.println("No I2C devices found\n"); + else + Serial.println("done\n"); + + delay(5000); +} \ No newline at end of file diff --git a/libraries/Basics/examples/pingpong/pingpong.ino b/libraries/Basics/examples/pingpong/pingpong.ino new file mode 100644 index 00000000..1df06ade --- /dev/null +++ b/libraries/Basics/examples/pingpong/pingpong.ino @@ -0,0 +1,147 @@ +#include "LoRaWan_APP.h" +#include "Arduino.h" + +/* + * set LoraWan_RGB to 1,the RGB active in loraWan + * RGB red means sending; + * RGB green means received done; + */ +#ifndef LoraWan_RGB +#define LoraWan_RGB 0 +#endif + +#define RF_FREQUENCY 868000000 // Hz + +#define TX_OUTPUT_POWER 14 // dBm + +#define LORA_BANDWIDTH 0 // [0: 125 kHz, + // 1: 250 kHz, + // 2: 500 kHz, + // 3: Reserved] +#define LORA_SPREADING_FACTOR 7 // [SF7..SF12] +#define LORA_CODINGRATE 1 // [1: 4/5, + // 2: 4/6, + // 3: 4/7, + // 4: 4/8] +#define LORA_PREAMBLE_LENGTH 8 // Same for Tx and Rx +#define LORA_SYMBOL_TIMEOUT 0 // Symbols +#define LORA_FIX_LENGTH_PAYLOAD_ON false +#define LORA_IQ_INVERSION_ON false + + +#define RX_TIMEOUT_VALUE 1000 +#define BUFFER_SIZE 30 // Define the payload size here + +char txpacket[BUFFER_SIZE]; +char rxpacket[BUFFER_SIZE]; + +static RadioEvents_t RadioEvents; +void OnTxDone( void ); +void OnTxTimeout( void ); +void OnRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ); + + + +typedef enum +{ + LOWPOWER, + RX, + TX +}States_t; + +int16_t txnumber; +States_t state; +bool sleepmode = false; +int16_t RSSI,rxSize; + + +void setup() { + BoardInitMcu( ); + Serial.begin(115200); + + txnumber=0; + RSSI=0; + + RadioEvents.TxDone = OnTxDone; + RadioEvents.TxTimeout = OnTxTimeout; + RadioEvents.RxDone = OnRxDone; + + Radio.Init( &RadioEvents ); + Radio.SetChannel( RF_FREQUENCY ); + Radio.SetTxConfig( MODEM_LORA, TX_OUTPUT_POWER, 0, LORA_BANDWIDTH, + LORA_SPREADING_FACTOR, LORA_CODINGRATE, + LORA_PREAMBLE_LENGTH, LORA_FIX_LENGTH_PAYLOAD_ON, + true, 0, 0, LORA_IQ_INVERSION_ON, 3000 ); + + Radio.SetRxConfig( MODEM_LORA, LORA_BANDWIDTH, LORA_SPREADING_FACTOR, + LORA_CODINGRATE, 0, LORA_PREAMBLE_LENGTH, + LORA_SYMBOL_TIMEOUT, LORA_FIX_LENGTH_PAYLOAD_ON, + 0, true, 0, 0, LORA_IQ_INVERSION_ON, true ); + state=TX; +} + + + +void loop() +{ + switch(state) + { + case TX: + delay(1000); + txnumber++; + sprintf(txpacket,"%s","hello"); + sprintf(txpacket+strlen(txpacket),"%d",txnumber); + sprintf(txpacket+strlen(txpacket),"%s"," rssi : "); + sprintf(txpacket+strlen(txpacket),"%d",RSSI); + RGB_ON(COLOR_SEND,0); + + Serial.printf("\r\nsending packet \"%s\" , length %d\r\n",txpacket, strlen(txpacket)); + + Radio.Send( (uint8_t *)txpacket, strlen(txpacket) ); + state=LOWPOWER; + break; + case RX: + Serial.println("into RX mode"); + Radio.Rx( 0 ); + state=LOWPOWER; + break; + case LOWPOWER: + LowPower_Handler(); + break; + default: + break; + } + Radio.IrqProcess( ); +} + +void OnTxDone( void ) +{ + Serial.print("TX done......"); + RGB_ON(0,0); + state=RX; +} + +void OnTxTimeout( void ) +{ + Radio.Sleep( ); + Serial.print("TX Timeout......"); + state=TX; +} +void OnRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ) +{ + RSSI=rssi; + rxSize=size; + memcpy(rxpacket, payload, size ); + rxpacket[size]='\0'; + RGB_ON(COLOR_RECEIVED,0); + Radio.Sleep( ); + + Serial.printf("\r\nreceived packet \"%s\" with RSSI %d , length %d\r\n",rxpacket,RSSI,rxSize); + Serial.println("wait to send next packet"); + + state=TX; +} + + + + diff --git a/libraries/Basics/library.properties b/libraries/Basics/library.properties new file mode 100644 index 00000000..b81b5359 --- /dev/null +++ b/libraries/Basics/library.properties @@ -0,0 +1,9 @@ +name=Basics +version=1.0 +author=Heltec +maintainer= +sentence= +paragraph= +category=Timing +url= +architectures=CubeCell diff --git a/libraries/Basics/src/Basics.h b/libraries/Basics/src/Basics.h new file mode 100644 index 00000000..e69de29b diff --git a/libraries/HDC1080/examples/hdc1080demo/hdc1080demo.ino b/libraries/HDC1080/examples/hdc1080demo/hdc1080demo.ino new file mode 100644 index 00000000..f7154440 --- /dev/null +++ b/libraries/HDC1080/examples/hdc1080demo/hdc1080demo.ino @@ -0,0 +1,45 @@ +#include +#include "HDC1080.h" + +HDC1080 hdc1080; + +void setup() +{ + //vext on + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW); + + Serial.begin(115200); + Serial.println("HDC1080 Arduino Test"); + + // Default settings: + // - Heater off + // - 14 bit Temperature and Humidity Measurement Resolutions + hdc1080.begin(0x40); + + Serial.print("Manufacturer ID=0x"); + Serial.println(hdc1080.readManufacturerId(), HEX); // 0x5449 ID of Texas Instruments + Serial.print("Device ID=0x"); + Serial.println(hdc1080.readDeviceId(), HEX); // 0x1050 ID of the device + + printSerialNumber(); + +} + +void loop() +{ + Serial.print("T="); + Serial.print(hdc1080.readTemperature()); + Serial.print("C, RH="); + Serial.print(hdc1080.readHumidity()); + Serial.println("%"); + delay(3000); +} + +void printSerialNumber() { + Serial.print("Device Serial Number="); + HDC1080_SerialNumber sernum = hdc1080.readSerialNumber(); + char format[12]; + sprintf(format, "%02X-%04X-%04X", sernum.serialFirst, sernum.serialMid, sernum.serialLast); + Serial.println(format); +} diff --git a/libraries/HDC1080/examples/hdc1080heater/hdc1080heater.ino b/libraries/HDC1080/examples/hdc1080heater/hdc1080heater.ino new file mode 100644 index 00000000..3ff9928a --- /dev/null +++ b/libraries/HDC1080/examples/hdc1080heater/hdc1080heater.ino @@ -0,0 +1,84 @@ + +#include +#include "HDC1080.h" + +HDC1080 hdc1080; + +void setup() +{ + //vext on + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW); + + Serial.begin(115200); + Serial.println("HDC1080 Heater Arduino Test"); + Serial.println(); + + // Default settings: + // - Heater off + // - 14 bit Temperature and Humidity Measurement Resolutions + hdc1080.begin(0x40); + + Serial.print("Manufacturer ID=0x"); + Serial.println(hdc1080.readManufacturerId(), HEX); // 0x5449 ID of Texas Instruments + Serial.print("Device ID=0x"); + Serial.println(hdc1080.readDeviceId(), HEX); // 0x1050 ID of the device + + printSerialNumber(); + + uint8_t huTime = 10; + Serial.print("Heating up for approx. "); + Serial.print(huTime); + Serial.println(" seconds. Please wait..."); + + hdc1080.heatUp(huTime); + hdc1080.heatUp(10); // approx 10 sec + printRegister(hdc1080.readRegister()); +} + +void loop() +{ + Serial.print("T="); + Serial.print(hdc1080.readTemperature()); + Serial.print("C, RH="); + Serial.print(hdc1080.readHumidity()); + Serial.println("%"); + delay(300); +} + +void printRegister(HDC1080_Registers reg) { + Serial.println("HDC1080 Configuration Register"); + Serial.println("------------------------------"); + + Serial.print("Software reset bit: "); + Serial.print(reg.SoftwareReset, BIN); + Serial.println(" (0=Normal Operation, 1=Software Reset)"); + + Serial.print("Heater: "); + Serial.print(reg.Heater, BIN); + Serial.println(" (0=Disabled, 1=Enabled)"); + + Serial.print("Mode of Acquisition: "); + Serial.print(reg.ModeOfAcquisition, BIN); + Serial.println(" (0=T or RH is acquired, 1=T and RH are acquired in sequence, T first)"); + + Serial.print("Battery Status: "); + Serial.print(reg.BatteryStatus, BIN); + Serial.println(" (0=Battery voltage > 2.8V, 1=Battery voltage < 2.8V)"); + + Serial.print("T Measurement Resolution: "); + Serial.print(reg.TemperatureMeasurementResolution, BIN); + Serial.println(" (0=14 bit, 1=11 bit)"); + + Serial.print("RH Measurement Resolution: "); + Serial.print(reg.HumidityMeasurementResolution, BIN); + Serial.println(" (00=14 bit, 01=11 bit, 10=8 bit)"); +} + +void printSerialNumber() { + Serial.print("Device Serial Number="); + HDC1080_SerialNumber sernum = hdc1080.readSerialNumber(); + char format[12]; + sprintf(format, "%02X-%04X-%04X", sernum.serialFirst, sernum.serialMid, sernum.serialLast); + Serial.println(format); +} diff --git a/libraries/HDC1080/examples/hdc1080measurement/hdc1080measurement.ino b/libraries/HDC1080/examples/hdc1080measurement/hdc1080measurement.ino new file mode 100644 index 00000000..c256bcc1 --- /dev/null +++ b/libraries/HDC1080/examples/hdc1080measurement/hdc1080measurement.ino @@ -0,0 +1,57 @@ +#include +#include "HDC1080.h" + +HDC1080 hdc1080; + +void setup() +{ + //vext on + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW); + + Serial.begin(115200); + Serial.println("HDC1080 Measurement Resolutions Arduino Test"); + + hdc1080.begin(0x40); + + Serial.print("Manufacturer ID=0x"); + Serial.println(hdc1080.readManufacturerId(), HEX); // 0x5449 ID of Texas Instruments + Serial.print("Device ID=0x"); + Serial.println(hdc1080.readDeviceId(), HEX); // 0x1050 ID of the device + + printTandRH(HDC1080_RESOLUTION_8BIT, HDC1080_RESOLUTION_11BIT); + printTandRH(HDC1080_RESOLUTION_11BIT, HDC1080_RESOLUTION_11BIT); + printTandRH(HDC1080_RESOLUTION_14BIT, HDC1080_RESOLUTION_11BIT); + printTandRH(HDC1080_RESOLUTION_8BIT, HDC1080_RESOLUTION_14BIT); + printTandRH(HDC1080_RESOLUTION_11BIT, HDC1080_RESOLUTION_14BIT); + printTandRH(HDC1080_RESOLUTION_14BIT, HDC1080_RESOLUTION_14BIT); + +} + +void loop() +{ +} + +void printTandRH(HDC1080_MeasurementResolution humidity, HDC1080_MeasurementResolution temperature) { + hdc1080.setResolution(humidity, temperature); + + HDC1080_Registers reg = hdc1080.readRegister(); + printRegister(reg); + + Serial.print("T="); + Serial.print(hdc1080.readTemperature()); + Serial.print("C, RH="); + Serial.print(hdc1080.readHumidity()); + Serial.println("%"); +} + +void printRegister(HDC1080_Registers reg) { + Serial.print("Measurement Resolution: T="); + Serial.print(reg.TemperatureMeasurementResolution, BIN); + Serial.print(" (0=14 bit, 1=11 bit)"); + + Serial.print(" RH="); + Serial.print(reg.HumidityMeasurementResolution, BIN); + Serial.println(" (00=14 bit, 01=11 bit, 10=8 bit)"); +} + diff --git a/libraries/HDC1080/library.properties b/libraries/HDC1080/library.properties new file mode 100644 index 00000000..27fd4c42 --- /dev/null +++ b/libraries/HDC1080/library.properties @@ -0,0 +1,9 @@ +name=HDC1080 +version=1.0 +author= +maintainer= +sentence= +paragraph= +category=Sensors +url= +architectures=CubeCell diff --git a/libraries/HDC1080/src/HDC1080.cpp b/libraries/HDC1080/src/HDC1080.cpp new file mode 100644 index 00000000..b93f564f --- /dev/null +++ b/libraries/HDC1080/src/HDC1080.cpp @@ -0,0 +1,160 @@ +/* + +Arduino Library for Texas Instruments HDC1080 Digital Humidity and Temperature Sensor +Written by AA for ClosedCube +--- + +The MIT License (MIT) + +Copyright (c) 2016-2017 ClosedCube Limited + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +#include + +#include "HDC1080.h" + + +HDC1080::HDC1080() +{ +} + +void HDC1080::begin(uint8_t address) { + _address = address; + Wire.begin(); + + setResolution(HDC1080_RESOLUTION_14BIT, HDC1080_RESOLUTION_14BIT); +} + +void HDC1080::end() { + Wire.end(); +} + + +void HDC1080::setResolution(HDC1080_MeasurementResolution humidity, HDC1080_MeasurementResolution temperature) { + HDC1080_Registers reg; + reg.HumidityMeasurementResolution = 0; + reg.TemperatureMeasurementResolution = 0; + + if (temperature == HDC1080_RESOLUTION_11BIT) + reg.TemperatureMeasurementResolution = 0x01; + + switch (humidity) + { + case HDC1080_RESOLUTION_8BIT: + reg.HumidityMeasurementResolution = 0x02; + break; + case HDC1080_RESOLUTION_11BIT: + reg.HumidityMeasurementResolution = 0x01; + break; + default: + break; + } + + writeRegister(reg); +} + +HDC1080_SerialNumber HDC1080::readSerialNumber() { + HDC1080_SerialNumber sernum; + sernum.serialFirst = readData(HDC1080_SERIAL_ID_FIRST); + sernum.serialMid = readData(HDC1080_SERIAL_ID_MID); + sernum.serialLast = readData(HDC1080_SERIAL_ID_LAST); + return sernum; +} + +HDC1080_Registers HDC1080::readRegister() { + HDC1080_Registers reg; + reg.rawData = (readData(HDC1080_CONFIGURATION) >> 8); + return reg; +} + +void HDC1080::writeRegister(HDC1080_Registers reg) { + Wire.beginTransmission(_address); + Wire.write(HDC1080_CONFIGURATION); + Wire.write(reg.rawData); + Wire.write(0x00); + Wire.endTransmission(); + delay(10); +} + +void HDC1080::heatUp(uint8_t seconds) { + HDC1080_Registers reg = readRegister(); + reg.Heater = 1; + reg.ModeOfAcquisition = 1; + writeRegister(reg); + + uint8_t buf[4]; + for (int i = 1; i < (seconds*66); i++) { + Wire.beginTransmission(_address); + Wire.write(0x00); + Wire.endTransmission(); + delay(20); + Wire.requestFrom(_address, (uint8_t)4); + Wire.readBytes(buf, (size_t)4); + } + reg.Heater = 0; + reg.ModeOfAcquisition = 0; + writeRegister(reg); +} + + +double HDC1080::readT() { + return readTemperature(); +} + +double HDC1080::readTemperature() { + uint16_t rawT = readData(HDC1080_TEMPERATURE); + return (rawT / pow(2, 16)) * 165.0 - 40.0; +} + +double HDC1080::readH() { + return readHumidity(); +} + +double HDC1080::readHumidity() { + uint16_t rawH = readData(HDC1080_HUMIDITY); + return (rawH / pow(2, 16)) * 100.0; +} + +uint16_t HDC1080::readManufacturerId() { + return readData(HDC1080_MANUFACTURER_ID); +} + +uint16_t HDC1080::readDeviceId() { + return readData(HDC1080_DEVICE_ID); +} + +uint16_t HDC1080::readData(uint8_t pointer) { + Wire.beginTransmission(_address); + Wire.write(pointer); + Wire.endTransmission(); + + delay(9); + Wire.requestFrom(_address, (uint8_t)2); + + byte msb = Wire.read(); + byte lsb = Wire.read(); + + return msb << 8 | lsb; +} + + + diff --git a/libraries/HDC1080/src/HDC1080.h b/libraries/HDC1080/src/HDC1080.h new file mode 100644 index 00000000..83d4a85f --- /dev/null +++ b/libraries/HDC1080/src/HDC1080.h @@ -0,0 +1,106 @@ +/* + +Arduino Library for Texas Instruments HDC1080 Digital Humidity and Temperature Sensor +Written by AA for ClosedCube +--- + +The MIT License (MIT) + +Copyright (c) 2016-2017 ClosedCube Limited + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +#ifndef _HDC1080_h + +#define _HDC1080_h +#include + +typedef enum { + HDC1080_RESOLUTION_8BIT, + HDC1080_RESOLUTION_11BIT, + HDC1080_RESOLUTION_14BIT, +} HDC1080_MeasurementResolution; + +typedef enum { + HDC1080_TEMPERATURE = 0x00, + HDC1080_HUMIDITY = 0x01, + HDC1080_CONFIGURATION = 0x02, + HDC1080_MANUFACTURER_ID = 0xFE, + HDC1080_DEVICE_ID = 0xFF, + HDC1080_SERIAL_ID_FIRST = 0xFB, + HDC1080_SERIAL_ID_MID = 0xFC, + HDC1080_SERIAL_ID_LAST = 0xFD, +} HDC1080_Pointers; + +typedef union { + uint8_t rawData[6]; + struct { + uint16_t serialFirst; + uint16_t serialMid; + uint16_t serialLast; + }; +} HDC1080_SerialNumber; + +typedef union { + uint8_t rawData; + struct { + uint8_t HumidityMeasurementResolution : 2; + uint8_t TemperatureMeasurementResolution : 1; + uint8_t BatteryStatus : 1; + uint8_t ModeOfAcquisition : 1; + uint8_t Heater : 1; + uint8_t ReservedAgain : 1; + uint8_t SoftwareReset : 1; + }; +} HDC1080_Registers; + +class HDC1080 { +public: + HDC1080(); + + void begin(uint8_t address); + void end(); + uint16_t readManufacturerId(); // 0x5449 ID of Texas Instruments + uint16_t readDeviceId(); // 0x1050 ID of the device + + HDC1080_Registers readRegister(); + void writeRegister(HDC1080_Registers reg); + + HDC1080_SerialNumber readSerialNumber(); + + void heatUp(uint8_t seconds); + + void setResolution(HDC1080_MeasurementResolution humidity, HDC1080_MeasurementResolution temperature); + + double readTemperature(); + double readHumidity(); + + double readT(); // short-cut for readTemperature + double readH(); // short-cut for readHumidity + +private: + uint8_t _address; + uint16_t readData(uint8_t pointer); + +}; + +#endif + diff --git a/libraries/LoRaWan/examples/LoRaWan/LoRaWan.ino b/libraries/LoRaWan/examples/LoRaWan/LoRaWan.ino new file mode 100644 index 00000000..43e4284e --- /dev/null +++ b/libraries/LoRaWan/examples/LoRaWan/LoRaWan.ino @@ -0,0 +1,133 @@ +#include "LoRaWan_APP.h" +#include "Arduino.h" + + +#ifndef ACTIVE_REGION +#define ACTIVE_REGION LORAMAC_REGION_CN470 +#endif + +#ifndef CLASS_MODE +#define CLASS_MODE CLASS_A +#endif + +DeviceClass_t CLASS=CLASS_MODE; + +/* + * set LoraWan_RGB to 1,the RGB active in loraWan + * RGB red means sending; + * RGB purple means joined done; + * RGB blue means RxWindow1; + * RGB yellow means RxWindow2; + * RGB green means received done; + */ +#ifndef LoraWan_RGB +#define LoraWan_RGB 0 +#endif + +/* set to 1 the enable AT mode/ set to 0 the disable support AT mode */ +#define AT_SUPPORT 1 + +/*! + * When set to true the application uses the Over-the-Air activation procedure + * When set to false the application uses the Personalization activation procedure + */ +bool OVER_THE_AIR_ACTIVATION = true; + +/* LoRaWAN Adaptive Data Rate */ +bool LORAWAN_ADR_ON = true; + +/* Indicates if the node is sending confirmed or unconfirmed messages */ +bool IsTxConfirmed = true; + +/*! +* Number of trials to transmit the frame, if the LoRaMAC layer did not +* receive an acknowledgment. The MAC performs a datarate adaptation, +* according to the LoRaWAN Specification V1.0.2, chapter 18.4, according +* to the following table: +* +* Transmission nb | Data Rate +* ----------------|----------- +* 1 (first) | DR +* 2 | DR +* 3 | max(DR-1,0) +* 4 | max(DR-1,0) +* 5 | max(DR-2,0) +* 6 | max(DR-2,0) +* 7 | max(DR-3,0) +* 8 | max(DR-3,0) +* +* Note, that if NbTrials is set to 1 or 2, the MAC will not decrease +* the datarate, in case the LoRaMAC layer did not receive an acknowledgment +*/ +uint8_t ConfirmedNbTrials = 8; + +/* Application port */ +uint8_t AppPort = 2; + +/*the application data transmission duty cycle. value in [ms].*/ +uint32_t APP_TX_DUTYCYCLE = 15000; + +/* Prepares the payload of the frame */ +static void PrepareTxFrame( uint8_t port ) +{ + AppDataSize = 4;//AppDataSize max value is 64 + AppData[0] = 0x00; + AppData[1] = 0x01; + AppData[2] = 0x02; + AppData[3] = 0x03; +} + +void setup() { + BoardInitMcu(); + Serial.begin(115200); + DeviceState = DEVICE_STATE_INIT; +} + +void loop() +{ + switch( DeviceState ) + { + case DEVICE_STATE_INIT: + { + Serial.printf("LoRaWan Class%X test start! \r\n",CLASS+10); +#if(AT_SUPPORT) + Enable_AT(); + getDevParam(); +#endif + printDevParam(); + LoRaWAN.Init(CLASS,ACTIVE_REGION); + DeviceState = DEVICE_STATE_JOIN; + break; + } + case DEVICE_STATE_JOIN: + { + LoRaWAN.Join(); + break; + } + case DEVICE_STATE_SEND: + { + PrepareTxFrame( AppPort ); + LoRaWAN.Send(); + TxDutyCycleTime = APP_TX_DUTYCYCLE + randr( 0, APP_TX_DUTYCYCLE_RND ); + DeviceState = DEVICE_STATE_CYCLE; + break; + } + case DEVICE_STATE_CYCLE: + { + // Schedule next packet transmission + DeviceState = DEVICE_STATE_SLEEP; + LoRaWAN.Cycle(TxDutyCycleTime); + break; + } + case DEVICE_STATE_SLEEP: + { + LoRaWAN.Sleep(); + break; + } + default: + { + DeviceState = DEVICE_STATE_INIT; + break; + } + } +} \ No newline at end of file diff --git a/libraries/LoRaWan/examples/LoRaWan_BH1750/LoRaWan_BH1750.ino b/libraries/LoRaWan/examples/LoRaWan_BH1750/LoRaWan_BH1750.ino new file mode 100644 index 00000000..8333a0f2 --- /dev/null +++ b/libraries/LoRaWan/examples/LoRaWan_BH1750/LoRaWan_BH1750.ino @@ -0,0 +1,168 @@ +#include "LoRaWan_APP.h" +#include "Arduino.h" +#include +#include + + + +#ifndef ACTIVE_REGION +#define ACTIVE_REGION LORAMAC_REGION_CN470 +#endif + +#ifndef CLASS_MODE +#define CLASS_MODE CLASS_A +#endif + +DeviceClass_t CLASS=CLASS_MODE; + +/* + * set LoraWan_RGB to 1,the RGB active in loraWan + * RGB red means sending; + * RGB purple means joined done; + * RGB blue means RxWindow1; + * RGB yellow means RxWindow2; + * RGB green means received done; + */ +#ifndef LoraWan_RGB +#define LoraWan_RGB 0 +#endif + +/* + set to 1 the enable AT mode + set to 0 the disable support AT mode +*/ +#define AT_SUPPORT 1 + +/*! + When set to true the application uses the Over-the-Air activation procedure + When set to false the application uses the Personalization activation procedure +*/ +bool OVER_THE_AIR_ACTIVATION = true; + +/* LoRaWAN Adaptive Data Rate */ +bool LORAWAN_ADR_ON = true; + +/* Indicates if the node is sending confirmed or unconfirmed messages */ +bool IsTxConfirmed = true; + +/*! +* Number of trials to transmit the frame, if the LoRaMAC layer did not +* receive an acknowledgment. The MAC performs a datarate adaptation, +* according to the LoRaWAN Specification V1.0.2, chapter 18.4, according +* to the following table: +* +* Transmission nb | Data Rate +* ----------------|----------- +* 1 (first) | DR +* 2 | DR +* 3 | max(DR-1,0) +* 4 | max(DR-1,0) +* 5 | max(DR-2,0) +* 6 | max(DR-2,0) +* 7 | max(DR-3,0) +* 8 | max(DR-3,0) +* +* Note, that if NbTrials is set to 1 or 2, the MAC will not decrease +* the datarate, in case the LoRaMAC layer did not receive an acknowledgment +*/ +uint8_t ConfirmedNbTrials = 8; + +/* Application port */ +uint8_t AppPort = 2; + +/*the application data transmission duty cycle. value in [ms].*/ +uint32_t APP_TX_DUTYCYCLE = 15000; + +/* get the BatteryVoltage in mV. */ +static uint16_t GetBatteryVoltage(void) +{ + pinMode(ADC_CTL,OUTPUT); + digitalWrite(ADC_CTL,LOW); + uint16_t volt=analogRead(ADC)*2; + digitalWrite(ADC_CTL,HIGH); + return volt; +} + +/* Prepares the payload of the frame */ +BH1750 lightMeter; +static void PrepareTxFrame( uint8_t port ) +{ + pinMode(Vext, OUTPUT); + digitalWrite(Vext, LOW); + lightMeter.begin(BH1750::ONE_TIME_HIGH_RES_MODE_2); + float lux = lightMeter.readLightLevel(); + lightMeter.end(); + digitalWrite(Vext, HIGH); + uint16_t BatteryVoltage = GetBatteryVoltage(); + + unsigned char *puc; + puc = (unsigned char *)(&lux); + AppDataSize = 6;//AppDataSize max value is 64 + AppData[0] = puc[0]; + AppData[1] = puc[1]; + AppData[2] = puc[2]; + AppData[3] = puc[3]; + AppData[4] = (uint8_t)(BatteryVoltage>>8); + AppData[5] = (uint8_t)BatteryVoltage; + + Serial.print("Light: "); + Serial.print(lux); + Serial.print(" lx,");Serial.print("BatteryVoltage:"); + Serial.println(BatteryVoltage); +} + + +void setup() { + BoardInitMcu(); + Serial.begin(115200); + DeviceState = DEVICE_STATE_INIT; +} + +void loop() +{ + switch( DeviceState ) + { + case DEVICE_STATE_INIT: + { + Serial.printf("LoRaWan Class%X test start! \r\n",CLASS+10); +#if(AT_SUPPORT) + Enable_AT(); + getDevParam(); +#endif + printDevParam(); + LoRaWAN.Init(CLASS,ACTIVE_REGION); + DeviceState = DEVICE_STATE_JOIN; + break; + } + case DEVICE_STATE_JOIN: + { + LoRaWAN.Join(); + break; + } + case DEVICE_STATE_SEND: + { + PrepareTxFrame( AppPort ); + LoRaWAN.Send(); + TxDutyCycleTime = APP_TX_DUTYCYCLE + randr( 0, APP_TX_DUTYCYCLE_RND ); + DeviceState = DEVICE_STATE_CYCLE; + break; + } + case DEVICE_STATE_CYCLE: + { + // Schedule next packet transmission + DeviceState = DEVICE_STATE_SLEEP; + LoRaWAN.Cycle(TxDutyCycleTime); + break; + } + case DEVICE_STATE_SLEEP: + { + LoRaWAN.Sleep(); + break; + } + default: + { + DeviceState = DEVICE_STATE_INIT; + break; + } + } +} \ No newline at end of file diff --git a/libraries/LoRaWan/examples/LoRaWan_HDC1080/LoRaWan_HDC1080.ino b/libraries/LoRaWan/examples/LoRaWan_HDC1080/LoRaWan_HDC1080.ino new file mode 100644 index 00000000..3b4a3748 --- /dev/null +++ b/libraries/LoRaWan/examples/LoRaWan_HDC1080/LoRaWan_HDC1080.ino @@ -0,0 +1,180 @@ +#include "LoRaWan_APP.h" +#include "Arduino.h" +#include +#include "HDC1080.h" + +#ifndef ACTIVE_REGION +#define ACTIVE_REGION LORAMAC_REGION_CN470 +#endif + +#ifndef CLASS_MODE +#define CLASS_MODE CLASS_A +#endif + +DeviceClass_t CLASS=CLASS_MODE; + +/* + * set LoraWan_RGB to 1,the RGB active in loraWan + * RGB red means sending; + * RGB purple means joined done; + * RGB blue means RxWindow1; + * RGB yellow means RxWindow2; + * RGB green means received done; + */ +#ifndef LoraWan_RGB +#define LoraWan_RGB 0 +#endif + +/* + * set to 1 the enable AT mode + * set to 0 the disable support AT mode + */ +#define AT_SUPPORT 1 + +/*! + * When set to true the application uses the Over-the-Air activation procedure + * When set to false the application uses the Personalization activation procedure + */ +bool OVER_THE_AIR_ACTIVATION = true; + +/* LoRaWAN Adaptive Data Rate */ +bool LORAWAN_ADR_ON = true; + +/* Indicates if the node is sending confirmed or unconfirmed messages */ +bool IsTxConfirmed = true; + +/*! +* Number of trials to transmit the frame, if the LoRaMAC layer did not +* receive an acknowledgment. The MAC performs a datarate adaptation, +* according to the LoRaWAN Specification V1.0.2, chapter 18.4, according +* to the following table: +* +* Transmission nb | Data Rate +* ----------------|----------- +* 1 (first) | DR +* 2 | DR +* 3 | max(DR-1,0) +* 4 | max(DR-1,0) +* 5 | max(DR-2,0) +* 6 | max(DR-2,0) +* 7 | max(DR-3,0) +* 8 | max(DR-3,0) +* +* Note, that if NbTrials is set to 1 or 2, the MAC will not decrease +* the datarate, in case the LoRaMAC layer did not receive an acknowledgment +*/ +uint8_t ConfirmedNbTrials = 8; + +/* Application port */ +uint8_t AppPort = 2; + +/*the application data transmission duty cycle. value in [ms].*/ +uint32_t APP_TX_DUTYCYCLE = 15000; + + +/* get the BatteryVoltage in mV. */ +static uint16_t GetBatteryVoltage(void) +{ + pinMode(ADC_CTL,OUTPUT); + digitalWrite(ADC_CTL,LOW); + uint16_t volt=analogRead(ADC)*2; + digitalWrite(ADC_CTL,HIGH); + return volt; +} + +/*! + * \brief Prepares the payload of the frame + */ +HDC1080 hdc1080; +static void PrepareTxFrame( uint8_t port ) +{ + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW); + hdc1080.begin(0x40); + float Temperature = (float)(hdc1080.readTemperature()); + float Humidity = (float)(hdc1080.readHumidity()); + hdc1080.end(); + digitalWrite(Vext,HIGH); + uint16_t BatteryVoltage = GetBatteryVoltage(); + unsigned char *puc; + + puc = (unsigned char *)(&Temperature); + AppDataSize = 10;//AppDataSize max value is 64 + AppData[0] = puc[0]; + AppData[1] = puc[1]; + AppData[2] = puc[2]; + AppData[3] = puc[3]; + + puc = (unsigned char *)(&Humidity); + AppData[4] = puc[0]; + AppData[5] = puc[1]; + AppData[6] = puc[2]; + AppData[7] = puc[3]; + + AppData[8] = (uint8_t)(BatteryVoltage>>8); + AppData[9] = (uint8_t)BatteryVoltage; + + Serial.print("T="); + Serial.print(Temperature); + Serial.print("C, RH="); + Serial.print(Humidity); + Serial.print("%,"); + Serial.print("BatteryVoltage:"); + Serial.println(BatteryVoltage); +} + + +void setup() { + BoardInitMcu( ); + Serial.begin(115200); + DeviceState = DEVICE_STATE_INIT; +} + +void loop() +{ + switch( DeviceState ) + { + case DEVICE_STATE_INIT: + { + Serial.printf("LoRaWan Class%X test start! \r\n",CLASS+10); +#if(AT_SUPPORT) + Enable_AT(); + getDevParam(); +#endif + printDevParam(); + LoRaWAN.Init(CLASS,ACTIVE_REGION); + DeviceState = DEVICE_STATE_JOIN; + break; + } + case DEVICE_STATE_JOIN: + { + LoRaWAN.Join(); + break; + } + case DEVICE_STATE_SEND: + { + PrepareTxFrame( AppPort ); + LoRaWAN.Send(); + TxDutyCycleTime = APP_TX_DUTYCYCLE + randr( 0, APP_TX_DUTYCYCLE_RND ); + DeviceState = DEVICE_STATE_CYCLE; + break; + } + case DEVICE_STATE_CYCLE: + { + // Schedule next packet transmission + DeviceState = DEVICE_STATE_SLEEP; + LoRaWAN.Cycle(TxDutyCycleTime); + break; + } + case DEVICE_STATE_SLEEP: + { + LoRaWAN.Sleep(); + break; + } + default: + { + DeviceState = DEVICE_STATE_INIT; + break; + } + } +} \ No newline at end of file diff --git a/libraries/LoRaWan/examples/LoRaWan_PASSMODE/LoRaWan_PASSMODE.ino b/libraries/LoRaWan/examples/LoRaWan_PASSMODE/LoRaWan_PASSMODE.ino new file mode 100644 index 00000000..802baeea --- /dev/null +++ b/libraries/LoRaWan/examples/LoRaWan_PASSMODE/LoRaWan_PASSMODE.ino @@ -0,0 +1,130 @@ +#include "LoRaWan_APP.h" +#include "Arduino.h" + + +#ifndef ACTIVE_REGION +#define ACTIVE_REGION LORAMAC_REGION_CN470 +#endif + +#ifndef CLASS_MODE +#define CLASS_MODE CLASS_A +#endif + +DeviceClass_t CLASS=CLASS_MODE; + +/* + * set LoraWan_RGB to 1,the RGB active in loraWan + * RGB red means sending; + * RGB purple means joined done; + * RGB blue means RxWindow1; + * RGB yellow means RxWindow2; + * RGB green means received done; + */ +#ifndef LoraWan_RGB +#define LoraWan_RGB 0 +#endif + +/*! + * When set to true the application uses the Over-the-Air activation procedure + * When set to false the application uses the Personalization activation procedure + */ +bool OVER_THE_AIR_ACTIVATION = true; + +/* LoRaWAN Adaptive Data Rate */ +bool LORAWAN_ADR_ON = true; + +/* Indicates if the node is sending confirmed or unconfirmed messages */ +bool IsTxConfirmed = true; + +/*! +* Number of trials to transmit the frame, if the LoRaMAC layer did not +* receive an acknowledgment. The MAC performs a datarate adaptation, +* according to the LoRaWAN Specification V1.0.2, chapter 18.4, according +* to the following table: +* +* Transmission nb | Data Rate +* ----------------|----------- +* 1 (first) | DR +* 2 | DR +* 3 | max(DR-1,0) +* 4 | max(DR-1,0) +* 5 | max(DR-2,0) +* 6 | max(DR-2,0) +* 7 | max(DR-3,0) +* 8 | max(DR-3,0) +* +* Note, that if NbTrials is set to 1 or 2, the MAC will not decrease +* the datarate, in case the LoRaMAC layer did not receive an acknowledgment +*/ +uint8_t ConfirmedNbTrials = 8; + +/* Application port */ +uint8_t AppPort = 2; + +/*the application data transmission duty cycle. value in [ms].*/ +uint32_t APP_TX_DUTYCYCLE = 15000; + +/* Prepares the payload of the frame */ +static void PrepareTxFrame( uint8_t port ) +{ + AppDataSize = 4;//AppDataSize max value is 64 + AppData[0] = 0x00; + AppData[1] = 0x01; + AppData[2] = 0x02; + AppData[3] = 0x03; +} + +void setup() { + BoardInitMcu(); + Serial.begin(115200); + PassthroughMode = true; + Enable_AT(); + Serial.printf("LoRaWan PassthroughMode start!\r\n"); + getDevParam(); + printDevParam(); + Serial.printf("please start with AT command\r\n"); + DeviceState = DEVICE_STATE_SLEEP; +} + +void loop() +{ + switch( DeviceState ) + { + case DEVICE_STATE_INIT: + { + getDevParam(); + printDevParam(); + LoRaWAN.Init(CLASS,ACTIVE_REGION); + DeviceState = DEVICE_STATE_JOIN; + break; + } + case DEVICE_STATE_JOIN: + { + LoRaWAN.Join(); + break; + } + case DEVICE_STATE_SEND: + { + LoRaWAN.Send(); + DeviceState = DEVICE_STATE_SLEEP; + break; + } + case DEVICE_STATE_CYCLE: + { + // only used while joining + DeviceState = DEVICE_STATE_SLEEP; + LoRaWAN.Cycle(TxDutyCycleTime); + break; + } + case DEVICE_STATE_SLEEP: + { + LoRaWAN.Sleep(); + break; + } + default: + { + DeviceState = DEVICE_STATE_INIT; + break; + } + } +} \ No newline at end of file diff --git a/libraries/LoRaWan/library.properties b/libraries/LoRaWan/library.properties new file mode 100644 index 00000000..cacb859c --- /dev/null +++ b/libraries/LoRaWan/library.properties @@ -0,0 +1,9 @@ +name=LoRaWan +version=1.0 +author=Heltec +maintainer= +sentence= +paragraph= +category=Timing +url= +architectures=CubeCell diff --git a/libraries/LoRaWan/src/Commissioning.h b/libraries/LoRaWan/src/Commissioning.h new file mode 100644 index 00000000..aa2b0cba --- /dev/null +++ b/libraries/LoRaWan/src/Commissioning.h @@ -0,0 +1,81 @@ +/*! + * \file Commissioning.h + * + * \brief End device commissioning parameters + * + * \copyright Revised BSD License, see section \ref LICENSE. + * + * \code + * ______ _ + * / _____) _ | | + * ( (____ _____ ____ _| |_ _____ ____| |__ + * \____ \| ___ | (_ _) ___ |/ ___) _ \ + * _____) ) ____| | | || |_| ____( (___| | | | + * (______/|_____)_|_|_| \__)_____)\____)_| |_| + * (C)2013-2017 Semtech + * + * \endcode + * + * \author Miguel Luis ( Semtech ) + * + * \author Gregory Cristian ( Semtech ) + */ +#ifndef __LORA_COMMISSIONING_H__ +#define __LORA_COMMISSIONING_H__ + +#include "LoRaMac.h" + +/*! + * User application data buffer size + */ +#define LORAWAN_APP_DATA_MAX_SIZE 64 //if use AT mode, don't modify this value or may run dead + +/*! + * Indicates if the end-device is to be connected to a private or public network + */ +#define LORAWAN_PUBLIC_NETWORK true + +/*! + * Mote device IEEE EUI (big endian) + * + * \remark In this application the value is automatically generated by calling + * BoardGetUniqueId function + */ +#define LORAWAN_DEVICE_EUI { 0x22, 0x32, 0x33, 0x00, 0x00, 0x88, 0x88, 0x02} + +/*! + * Application IEEE EUI (big endian) + */ +#define LORAWAN_APPLICATION_EUI { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } + +/*! + * AES encryption/decryption cipher application key + */ +#define LORAWAN_APPLICATION_KEY { 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x66, 0x01 } + +/*! + * Current network ID + */ +#define LORAWAN_NETWORK_ID ( uint32_t )0 + +/*! + * Device address on the network (big endian) + * + * \remark In this application the value is automatically generated using + * a pseudo random generator seeded with a value derived from + * BoardUniqueId value if LORAWAN_DEVICE_ADDRESS is set to 0 + */ +#define LORAWAN_DEVICE_ADDRESS ( uint32_t )0x007e6ae1 + +/*! + * AES encryption/decryption cipher network session key + */ +#define LORAWAN_NWKSKEY { 0xd7, 0x2c, 0x78, 0x75, 0x8c, 0xdc, 0xca, 0xbf, 0x55, 0xee, 0x4a, 0x77, 0x8d, 0x16, 0xef,0x67 } + +/*! + * AES encryption/decryption cipher application session key + */ +#define LORAWAN_APPSKEY { 0x15, 0xb1, 0xd0, 0xef, 0xa4, 0x63, 0xdf, 0xbe, 0x3d, 0x11, 0x18, 0x1e, 0x1e, 0xc7, 0xda,0x85 } + + +#endif // __LORA_COMMISSIONING_H__ diff --git a/libraries/LoRaWan/src/LoRaWan_APP.cpp b/libraries/LoRaWan/src/LoRaWan_APP.cpp new file mode 100644 index 00000000..b2eab33f --- /dev/null +++ b/libraries/LoRaWan/src/LoRaWan_APP.cpp @@ -0,0 +1,502 @@ +#include +#if LoraWan_RGB==1 +#include "Adafruit_NeoPixel.h" +Adafruit_NeoPixel pixels(1, RGB, NEO_GRB + NEO_KHZ800); +#endif + + +/*! + * Default datarate + */ +#define LORAWAN_DEFAULT_DATARATE DR_5 + +uint8_t DevEui[] = LORAWAN_DEVICE_EUI; +uint8_t AppEui[] = LORAWAN_APPLICATION_EUI; +uint8_t AppKey[] = LORAWAN_APPLICATION_KEY; + +uint8_t NwkSKey[] = LORAWAN_NWKSKEY; +uint8_t AppSKey[] = LORAWAN_APPSKEY; +uint32_t DevAddr = LORAWAN_DEVICE_ADDRESS; + + +/*! + * User application data size + */ +uint8_t AppDataSize = 4; + +/*! + * User application data + */ +uint8_t AppData[LORAWAN_APP_DATA_MAX_SIZE]; + + +/*! + * Defines the application data transmission duty cycle + */ +uint32_t TxDutyCycleTime; + +/*! + * Timer to handle the application data transmission duty cycle + */ +static TimerEvent_t TxNextPacketTimer; + +/*! + * PassthroughMode mode enable/disable. don't modify it. + * when use PassthroughMode, set it true in app.ino , Reference the example LoRaWan_PASSMODE.ino + */ +bool PassthroughMode = false; + +/*! + * Indicates if a new packet can be sent + */ +static bool NextTx = true; + + +enum eDeviceState DeviceState; + +/*! + * \brief Prepares the payload of the frame + * + * \retval [0: frame could be send, 1: error] + */ +bool SendFrame( void ) +{ + McpsReq_t mcpsReq; + LoRaMacTxInfo_t txInfo; + + if( LoRaMacQueryTxPossible( AppDataSize, &txInfo ) != LORAMAC_STATUS_OK ) + { + // Send empty frame in order to flush MAC commands + mcpsReq.Type = MCPS_UNCONFIRMED; + mcpsReq.Req.Unconfirmed.fBuffer = NULL; + mcpsReq.Req.Unconfirmed.fBufferSize = 0; + mcpsReq.Req.Unconfirmed.Datarate = LORAWAN_DEFAULT_DATARATE; + } + else + { + if( IsTxConfirmed == false ) + { + printf("unconfirmed uplink sending ...\r\n"); + mcpsReq.Type = MCPS_UNCONFIRMED; + mcpsReq.Req.Unconfirmed.fPort = AppPort; + mcpsReq.Req.Unconfirmed.fBuffer = AppData; + mcpsReq.Req.Unconfirmed.fBufferSize = AppDataSize; + mcpsReq.Req.Unconfirmed.Datarate = LORAWAN_DEFAULT_DATARATE; + } + else + { + printf("confirmed uplink sending ...\r\n"); + mcpsReq.Type = MCPS_CONFIRMED; + mcpsReq.Req.Confirmed.fPort = AppPort; + mcpsReq.Req.Confirmed.fBuffer = AppData; + mcpsReq.Req.Confirmed.fBufferSize = AppDataSize; + mcpsReq.Req.Confirmed.NbTrials = ConfirmedNbTrials; + mcpsReq.Req.Confirmed.Datarate = LORAWAN_DEFAULT_DATARATE; + } + } + if( LoRaMacMcpsRequest( &mcpsReq ) == LORAMAC_STATUS_OK ) + { + return false; + } + return true; +} + +/*! + * \brief Function executed on TxNextPacket Timeout event + */ +static void OnTxNextPacketTimerEvent( void ) +{ + MibRequestConfirm_t mibReq; + LoRaMacStatus_t status; + + TimerStop( &TxNextPacketTimer ); + + mibReq.Type = MIB_NETWORK_JOINED; + status = LoRaMacMibGetRequestConfirm( &mibReq ); + + if( status == LORAMAC_STATUS_OK ) + { + if( mibReq.Param.IsNetworkJoined == true ) + { + DeviceState = DEVICE_STATE_SEND; + NextTx = true; + } + else + { + // Network not joined yet. Try to join again + MlmeReq_t mlmeReq; + mlmeReq.Type = MLME_JOIN; + mlmeReq.Req.Join.DevEui = DevEui; + mlmeReq.Req.Join.AppEui = AppEui; + mlmeReq.Req.Join.AppKey = AppKey; + + if( LoRaMacMlmeRequest( &mlmeReq ) == LORAMAC_STATUS_OK ) + { + DeviceState = DEVICE_STATE_SLEEP; + } + else + { + DeviceState = DEVICE_STATE_CYCLE; + } + } + } +} + +/*! + * \brief MCPS-Confirm event function + * + * \param [IN] mcpsConfirm - Pointer to the confirm structure, + * containing confirm attributes. + */ +static void McpsConfirm( McpsConfirm_t *mcpsConfirm ) +{ + if( mcpsConfirm->Status == LORAMAC_EVENT_INFO_STATUS_OK ) + { + switch( mcpsConfirm->McpsRequest ) + { + case MCPS_UNCONFIRMED: + { + // Check Datarate + // Check TxPower + break; + } + case MCPS_CONFIRMED: + { + // Check Datarate + // Check TxPower + // Check AckReceived + // Check NbTrials + break; + } + case MCPS_PROPRIETARY: + { + break; + } + default: + break; + } + } + NextTx = true; +} + +#if LoraWan_RGB==1 + +void RGB_ON(uint32_t color,uint32_t time) +{ + uint8_t red,green,blue; + red=(uint8_t)(color>>16); + green=(uint8_t)(color>>8); + blue=(uint8_t)color; + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW); //SET POWER + pixels.begin(); // INITIALIZE RGB strip object (REQUIRED) + pixels.clear(); // Set all pixel colors to 'off' + pixels.setPixelColor(0, pixels.Color(red, green, blue)); + pixels.show(); // Send the updated pixel colors to the hardware. + if(time>0) + { + delay(time); + } +} + +void RGB_OFF(void) +{ + RGB_ON(0,0); + digitalWrite(Vext,HIGH); +} +#endif + +/*! + * \brief MCPS-Indication event function + * + * \param [IN] mcpsIndication - Pointer to the indication structure, + * containing indication attributes. + */ +static void McpsIndication( McpsIndication_t *mcpsIndication ) +{ + if( mcpsIndication->Status != LORAMAC_EVENT_INFO_STATUS_OK ) + { + return; + } + + + printf( "receive data: rssi = %d, snr = %d, datarate = %d\r\n", mcpsIndication->Rssi, (int)mcpsIndication->Snr,(int)mcpsIndication->RxDatarate); + +#if (LoraWan_RGB==1) + RGB_ON(COLOR_RECEIVED, 200); + RGB_OFF(); +#endif + + switch( mcpsIndication->McpsIndication ) + { + case MCPS_UNCONFIRMED: + { + break; + } + case MCPS_CONFIRMED: + { + break; + } + case MCPS_PROPRIETARY: + { + break; + } + case MCPS_MULTICAST: + { + break; + } + default: + break; + } + if( mcpsIndication->RxData == true ) + { + //memset(temp,0,200); + //memset(temp1,0,200); + + //HexToString((const char *)(mcpsIndication->Buffer),mcpsIndication->BufferSize,(char *)(temp1)); + //temp1[mcpsIndication->BufferSize * 2]='\0'; + + printf("+REV MSG:%s,RXSIZE %d,\r\n",mcpsIndication->RxSlot?"RXWIN2":"RXWIN1",mcpsIndication->BufferSize); + } + // Check Multicast + // Check Port + // Check Datarate + // Check FramePending + if( mcpsIndication->FramePending == true ) + { + // The server signals that it has pending data to be sent. + // We schedule an uplink as soon as possible to flush the server. + OnTxNextPacketTimerEvent( ); + } + // Check Buffer + // Check BufferSize + // Check Rssi + // Check Snr + // Check RxSlot + if( mcpsIndication->RxData == true ) + { + } +} + +/*! + * \brief MLME-Confirm event function + * + * \param [IN] mlmeConfirm - Pointer to the confirm structure, + * containing confirm attributes. + */ +static void MlmeConfirm( MlmeConfirm_t *mlmeConfirm ) +{ + switch( mlmeConfirm->MlmeRequest ) + { + case MLME_JOIN: + { + if( mlmeConfirm->Status == LORAMAC_EVENT_INFO_STATUS_OK ) + { + +#if (LoraWan_RGB==1) + RGB_ON(COLOR_JOINED,500); + RGB_OFF(); +#endif + printf("joined\r\n"); + + //in PassthroughMode,do nothing while joined + if(PassthroughMode == false) + { + // Status is OK, node has joined the network + DeviceState = DEVICE_STATE_SEND; + } + } + else + { + uint32_t rejoin_delay = 30000; + printf("join failed\r\n"); + TimerSetValue( &TxNextPacketTimer, rejoin_delay ); + TimerStart( &TxNextPacketTimer ); + } + break; + } + case MLME_LINK_CHECK: + { + if( mlmeConfirm->Status == LORAMAC_EVENT_INFO_STATUS_OK ) + { + // Check DemodMargin + // Check NbGateways + } + break; + } + default: + break; + } + NextTx = true; +} + +/*! + * \brief MLME-Indication event function + * + * \param [IN] mlmeIndication - Pointer to the indication structure. + */ +static void MlmeIndication( MlmeIndication_t *mlmeIndication ) +{ + switch( mlmeIndication->MlmeIndication ) + { + case MLME_SCHEDULE_UPLINK: + {// The MAC signals that we shall provide an uplink as soon as possible + OnTxNextPacketTimerEvent( ); + break; + } + default: + break; + } +} + + +static void lwan_dev_params_update( void ) +{ + MibRequestConfirm_t mibReq; + uint16_t channelsMaskTemp[6]; + channelsMaskTemp[0] = 0x00FF; + channelsMaskTemp[1] = 0x0000; + channelsMaskTemp[2] = 0x0000; + channelsMaskTemp[3] = 0x0000; + channelsMaskTemp[4] = 0x0000; + channelsMaskTemp[5] = 0x0000; + + mibReq.Type = MIB_CHANNELS_DEFAULT_MASK; + mibReq.Param.ChannelsMask = channelsMaskTemp; + LoRaMacMibSetRequestConfirm(&mibReq); + + mibReq.Type = MIB_CHANNELS_MASK; + mibReq.Param.ChannelsMask = channelsMaskTemp; + LoRaMacMibSetRequestConfirm(&mibReq); +} + +uint8_t BoardGetBatteryLevel() +{ + return 100; +} + +LoRaMacPrimitives_t LoRaMacPrimitive; +LoRaMacCallback_t LoRaMacCallback; + +void LoRaWanClass::Init(DeviceClass_t CLASS,LoRaMacRegion_t REGION) +{ + + MibRequestConfirm_t mibReq; + + LoRaMacPrimitive.MacMcpsConfirm = McpsConfirm; + LoRaMacPrimitive.MacMcpsIndication = McpsIndication; + LoRaMacPrimitive.MacMlmeConfirm = MlmeConfirm; + LoRaMacPrimitive.MacMlmeIndication = MlmeIndication; + LoRaMacCallback.GetBatteryLevel = BoardGetBatteryLevel; + LoRaMacCallback.GetTemperatureLevel = NULL; + LoRaMacInitialization( &LoRaMacPrimitive, &LoRaMacCallback,REGION); + TimerInit( &TxNextPacketTimer, OnTxNextPacketTimerEvent ); + + mibReq.Type = MIB_ADR; + mibReq.Param.AdrEnable = LORAWAN_ADR_ON; + LoRaMacMibSetRequestConfirm( &mibReq ); + + mibReq.Type = MIB_PUBLIC_NETWORK; + mibReq.Param.EnablePublicNetwork = LORAWAN_PUBLIC_NETWORK; + LoRaMacMibSetRequestConfirm( &mibReq ); + + + lwan_dev_params_update(); + + DeviceState = DEVICE_STATE_JOIN; +} + +void LoRaWanClass::Join() +{ + printf("joining..."); + if( OVER_THE_AIR_ACTIVATION != 0 ) + { + MlmeReq_t mlmeReq; + + mlmeReq.Type = MLME_JOIN; + + mlmeReq.Req.Join.DevEui = DevEui; + mlmeReq.Req.Join.AppEui = AppEui; + mlmeReq.Req.Join.AppKey = AppKey; + + if( LoRaMacMlmeRequest( &mlmeReq ) == LORAMAC_STATUS_OK ) + { + DeviceState = DEVICE_STATE_SLEEP; + } + else + { + DeviceState = DEVICE_STATE_CYCLE; + } + } + else + { + MibRequestConfirm_t mibReq; + + mibReq.Type = MIB_NET_ID; + mibReq.Param.NetID = LORAWAN_NETWORK_ID; + LoRaMacMibSetRequestConfirm( &mibReq ); + + mibReq.Type = MIB_DEV_ADDR; + mibReq.Param.DevAddr = DevAddr; + LoRaMacMibSetRequestConfirm( &mibReq ); + + mibReq.Type = MIB_NWK_SKEY; + mibReq.Param.NwkSKey = NwkSKey; + LoRaMacMibSetRequestConfirm( &mibReq ); + + mibReq.Type = MIB_APP_SKEY; + mibReq.Param.AppSKey = AppSKey; + LoRaMacMibSetRequestConfirm( &mibReq ); + + mibReq.Type = MIB_NETWORK_JOINED; + mibReq.Param.IsNetworkJoined = true; + LoRaMacMibSetRequestConfirm( &mibReq ); + + DeviceState = DEVICE_STATE_SEND; + } +} + +void LoRaWanClass::Send() +{ + if( NextTx == true ) + { + MibRequestConfirm_t mibReq; + mibReq.Type = MIB_DEVICE_CLASS; + LoRaMacMibGetRequestConfirm( &mibReq ); + + if(CLASS == CLASS_C) + { + if( mibReq.Param.Class!= CLASS_C ) + { + mibReq.Param.Class = CLASS_C; + LoRaMacMibSetRequestConfirm( &mibReq ); + } + } + + if(CLASS == CLASS_A) + { + if( mibReq.Param.Class!= CLASS_A ) + { + mibReq.Param.Class = CLASS_A; + LoRaMacMibSetRequestConfirm( &mibReq ); + } + } + + NextTx = SendFrame( ); + } +} + +void LoRaWanClass::Cycle(uint32_t dutycycle) +{ + TimerSetValue( &TxNextPacketTimer, TxDutyCycleTime ); + TimerStart( &TxNextPacketTimer ); +} + +void LoRaWanClass::Sleep() +{ + LowPower_Handler( ); + // Process Radio IRQ + Radio.IrqProcess( ); +} +LoRaWanClass LoRaWAN; + diff --git a/libraries/LoRaWan/src/LoRaWan_APP.h b/libraries/LoRaWan/src/LoRaWan_APP.h new file mode 100644 index 00000000..b5e6f082 --- /dev/null +++ b/libraries/LoRaWan/src/LoRaWan_APP.h @@ -0,0 +1,67 @@ +#ifndef LoRaWan_APP_H +#define LoRaWan_APP_H + +#include +#include "utilities.h" +#include "board.h" +#include "gpio.h" +#include "LoRaMac.h" +#include "Commissioning.h" +#include "hw.h" +#include "low_power.h" +#include "spi-board.h" +#include "rtc-board.h" +#include "asr_timer.h" +#include "sx126x.h" +#include "board-config.h" +#include "hw_conf.h" +#include +#include "AT_Command.h" + + +extern uint8_t AppData[LORAWAN_APP_DATA_MAX_SIZE]; +extern uint8_t AppDataSize; +extern uint8_t AppPort; +extern uint32_t TxDutyCycleTime; +extern bool OVER_THE_AIR_ACTIVATION; +extern bool LORAWAN_ADR_ON; +extern bool IsTxConfirmed; +extern uint32_t APP_TX_DUTYCYCLE; +extern DeviceClass_t CLASS; +extern uint8_t AppPort; +extern bool PassthroughMode; +extern uint8_t ConfirmedNbTrials; +/*! + * Defines a random delay for application data transmission duty cycle. 1s, + * value in [ms]. + */ +#define APP_TX_DUTYCYCLE_RND 1000 + +/*! + * Device states + */ +enum eDeviceState +{ + DEVICE_STATE_INIT, + DEVICE_STATE_JOIN, + DEVICE_STATE_SEND, + DEVICE_STATE_CYCLE, + DEVICE_STATE_SLEEP +}; + +extern enum eDeviceState DeviceState; + +class LoRaWanClass{ +public: + void Init(DeviceClass_t CLASS,LoRaMacRegion_t REGION); + void Join(); + void Send(); + void Cycle(uint32_t dutycycle); + void Sleep(); +}; +extern "C" bool SendFrame( void ); +extern "C" void RGB_ON(uint32_t color,uint32_t time); +extern "C" void RGB_OFF(void); +extern LoRaWanClass LoRaWAN; + +#endif diff --git a/libraries/RGB/examples/RGB/RGB.ino b/libraries/RGB/examples/RGB/RGB.ino new file mode 100644 index 00000000..135225d5 --- /dev/null +++ b/libraries/RGB/examples/RGB/RGB.ino @@ -0,0 +1,37 @@ +#include "Adafruit_NeoPixel.h" +Adafruit_NeoPixel pixels(1, RGB, NEO_GRB + NEO_KHZ800); + +void setup() { + // put your setup code here, to run once: + pinMode(Vext,OUTPUT); + digitalWrite(Vext,LOW); //SET POWER + pixels.begin(); // INITIALIZE NeoPixel strip object (REQUIRED) + pixels.clear(); // Set all pixel colors to 'off' +} +uint8_t i=0; + +void loop() { + // put your main code here, to run repeatedly: + + pixels.setPixelColor(0, pixels.Color(i, 0, 0)); + + pixels.show(); // Send the updated pixel colors to the hardware. + + delay(200); // Pause before next pass through loop + + pixels.setPixelColor(0, pixels.Color(0, i, 0)); + + pixels.show(); // Send the updated pixel colors to the hardware. + + + delay(200); // Pause before next pass through loop + + pixels.setPixelColor(0, pixels.Color(0, 0, i)); + + pixels.show(); // Send the updated pixel colors to the hardware. + + delay(200); // Pause before next pass through loop + + i+=10; + +} diff --git a/libraries/RGB/library.properties b/libraries/RGB/library.properties new file mode 100644 index 00000000..4850c9c4 --- /dev/null +++ b/libraries/RGB/library.properties @@ -0,0 +1,9 @@ +name=RGB +version=1.0 +author=Heltec +maintainer= +sentence= +paragraph= +category=Timing +url= +architectures=CubeCell diff --git a/libraries/RGB/src/Adafruit_NeoPixel.cpp b/libraries/RGB/src/Adafruit_NeoPixel.cpp new file mode 100644 index 00000000..9588ccf9 --- /dev/null +++ b/libraries/RGB/src/Adafruit_NeoPixel.cpp @@ -0,0 +1,580 @@ +/*! + * @file Adafruit_NeoPixel.cpp + * + * @mainpage Arduino Library for driving Adafruit NeoPixel addressable LEDs, + * FLORA RGB Smart Pixels and compatible devicess -- WS2811, WS2812, WS2812B, + * SK6812, etc. + * + * @section intro_sec Introduction + * + * This is the documentation for Adafruit's NeoPixel library for the + * Arduino platform, allowing a broad range of microcontroller boards + * (most AVR boards, many ARM devices, ESP8266 and ESP32, among others) + * to control Adafruit NeoPixels, FLORA RGB Smart Pixels and compatible + * devices -- WS2811, WS2812, WS2812B, SK6812, etc. + * + * Adafruit invests time and resources providing this open source code, + * please support Adafruit and open-source hardware by purchasing products + * from Adafruit! + * + * @section author Author + * + * Written by Phil "Paint Your Dragon" Burgess for Adafruit Industries, + * with contributions by PJRC, Michael Miller and other members of the + * open source community. + * + * @section license License + * + * This file is part of the Adafruit_NeoPixel library. + * + * Adafruit_NeoPixel is free software: you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation, either version 3 of the + * License, or (at your option) any later version. + * + * Adafruit_NeoPixel is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with NeoPixel. If not, see + * . + * + */ + +#include "Adafruit_NeoPixel.h" +#include "project.h" + +/*! + @brief NeoPixel constructor when length, pin and pixel type are known + at compile-time. + @param n Number of NeoPixels in strand. + @param p Arduino pin number which will drive the NeoPixel data in. + @param t Pixel type -- add together NEO_* constants defined in + Adafruit_NeoPixel.h, for example NEO_GRB+NEO_KHZ800 for + NeoPixels expecting an 800 KHz (vs 400 KHz) data stream + with color bytes expressed in green, red, blue order per + pixel. + @return Adafruit_NeoPixel object. Call the begin() function before use. +*/ +Adafruit_NeoPixel::Adafruit_NeoPixel(uint16_t n, uint8_t p, neoPixelType t) : + begun(false), brightness(0), pixels(NULL), endTime(0) { + updateType(t); + updateLength(n); + setPin(p); +} + +/*! + @brief "Empty" NeoPixel constructor when length, pin and/or pixel type + are not known at compile-time, and must be initialized later with + updateType(), updateLength() and setPin(). + @return Adafruit_NeoPixel object. Call the begin() function before use. + @note This function is deprecated, here only for old projects that + may still be calling it. New projects should instead use the + 'new' keyword with the first constructor syntax (length, pin, + type). +*/ +Adafruit_NeoPixel::Adafruit_NeoPixel() : +#ifdef NEO_KHZ400 + is800KHz(true), +#endif + begun(false), numLEDs(0), numBytes(0), pin(-1), brightness(0), pixels(NULL), + rOffset(1), gOffset(0), bOffset(2), wOffset(1), endTime(0) { +} + +/*! + @brief Deallocate Adafruit_NeoPixel object, set data pin back to INPUT. +*/ +Adafruit_NeoPixel::~Adafruit_NeoPixel() { + free(pixels); + if(pin >= 0) pinMode(pin, INPUT); +} + +/*! + @brief Configure NeoPixel pin for output. +*/ +void Adafruit_NeoPixel::begin(void) { + if(pin >= 0) { + pinMode(pin, OUTPUT); + digitalWrite(pin, LOW); + } + begun = true; +} + +/*! + @brief Change the length of a previously-declared Adafruit_NeoPixel + strip object. Old data is deallocated and new data is cleared. + Pin number and pixel format are unchanged. + @param n New length of strip, in pixels. + @note This function is deprecated, here only for old projects that + may still be calling it. New projects should instead use the + 'new' keyword with the first constructor syntax (length, pin, + type). +*/ +void Adafruit_NeoPixel::updateLength(uint16_t n) { + free(pixels); // Free existing data (if any) + + // Allocate new data -- note: ALL PIXELS ARE CLEARED + numBytes = n * ((wOffset == rOffset) ? 3 : 4); + if((pixels = (uint8_t *)malloc(numBytes))) { + memset(pixels, 0, numBytes); + numLEDs = n; + } else { + numLEDs = numBytes = 0; + } +} + +/*! + @brief Change the pixel format of a previously-declared + Adafruit_NeoPixel strip object. If format changes from one of + the RGB variants to an RGBW variant (or RGBW to RGB), the old + data will be deallocated and new data is cleared. Otherwise, + the old data will remain in RAM and is not reordered to the + new format, so it's advisable to follow up with clear(). + @param t Pixel type -- add together NEO_* constants defined in + Adafruit_NeoPixel.h, for example NEO_GRB+NEO_KHZ800 for + NeoPixels expecting an 800 KHz (vs 400 KHz) data stream + with color bytes expressed in green, red, blue order per + pixel. + @note This function is deprecated, here only for old projects that + may still be calling it. New projects should instead use the + 'new' keyword with the first constructor syntax + (length, pin, type). +*/ +void Adafruit_NeoPixel::updateType(neoPixelType t) { + boolean oldThreeBytesPerPixel = (wOffset == rOffset); // false if RGBW + + wOffset = (t >> 6) & 0b11; // See notes in header file + rOffset = (t >> 4) & 0b11; // regarding R/G/B/W offsets + gOffset = (t >> 2) & 0b11; + bOffset = t & 0b11; +#ifdef NEO_KHZ400 + is800KHz = (t < 256); // 400 KHz flag is 1<<8 +#endif + + // If bytes-per-pixel has changed (and pixel data was previously + // allocated), re-allocate to new size. Will clear any data. + if(pixels) { + boolean newThreeBytesPerPixel = (wOffset == rOffset); + if(newThreeBytesPerPixel != oldThreeBytesPerPixel) updateLength(numLEDs); + } +} + +extern "C" void ASR_NeoPixelShow( + uint8_t pin, uint8_t *pixels, uint32_t numBytes, uint8_t type); + +/*! + @brief Transmit pixel data in RAM to NeoPixels. + @note On most architectures, interrupts are temporarily disabled in + order to achieve the correct NeoPixel signal timing. This means + that the Arduino millis() and micros() functions, which require + interrupts, will lose small intervals of time whenever this + function is called (about 30 microseconds per RGB pixel, 40 for + RGBW pixels). There's no easy fix for this, but a few + specialized alternative or companion libraries exist that use + very device-specific peripherals to work around it. +*/ +void Adafruit_NeoPixel::show(void) { + + if(!pixels) return; + + // Data latch = 300+ microsecond pause in the output stream. Rather than + // put a delay at the end of the function, the ending time is noted and + // the function will simply hold off (if needed) on issuing the + // subsequent round of data until the latch time has elapsed. This + // allows the mainline code to start generating the next frame of data + // rather than stalling for the latch. + //while(!canShow()); + // endTime is a private member (rather than global var) so that multiple + // instances on different pins can be quickly issued in succession (each + // instance doesn't delay the next). + + // In order to make this code runtime-configurable to work with any pin, + // SBI/CBI instructions are eschewed in favor of full PORT writes via the + // OUT or ST instructions. It relies on two facts: that peripheral + // functions (such as PWM) take precedence on output pins, so our PORT- + // wide writes won't interfere, and that interrupts are globally disabled + // while data is being issued to the LEDs, so no other code will be + // accessing the PORT. The code takes an initial 'snapshot' of the PORT + // state, computes 'pin high' and 'pin low' values, and writes these back + // to the PORT register as needed. + + + noInterrupts(); + + ASR_NeoPixelShow(pin, pixels, numBytes, is800KHz); + + interrupts(); +} + +/*! + @brief Set/change the NeoPixel output pin number. Previous pin, + if any, is set to INPUT and the new pin is set to OUTPUT. + @param p Arduino pin number (-1 = no pin). +*/ +void Adafruit_NeoPixel::setPin(uint8_t p) { + if(begun && (pin >= 0)) pinMode(pin, INPUT); + pin = p; + if(begun) { + pinMode(p, OUTPUT); + digitalWrite(p, LOW); + } + +} + +/*! + @brief Set a pixel's color using separate red, green and blue + components. If using RGBW pixels, white will be set to 0. + @param n Pixel index, starting from 0. + @param r Red brightness, 0 = minimum (off), 255 = maximum. + @param g Green brightness, 0 = minimum (off), 255 = maximum. + @param b Blue brightness, 0 = minimum (off), 255 = maximum. +*/ +void Adafruit_NeoPixel::setPixelColor( + uint16_t n, uint8_t r, uint8_t g, uint8_t b) { + + if(n < numLEDs) { + if(brightness) { // See notes in setBrightness() + r = (r * brightness) >> 8; + g = (g * brightness) >> 8; + b = (b * brightness) >> 8; + } + uint8_t *p; + if(wOffset == rOffset) { // Is an RGB-type strip + p = &pixels[n * 3]; // 3 bytes per pixel + } else { // Is a WRGB-type strip + p = &pixels[n * 4]; // 4 bytes per pixel + p[wOffset] = 0; // But only R,G,B passed -- set W to 0 + } + p[rOffset] = r; // R,G,B always stored + p[gOffset] = g; + p[bOffset] = b; + } +} + +/*! + @brief Set a pixel's color using separate red, green, blue and white + components (for RGBW NeoPixels only). + @param n Pixel index, starting from 0. + @param r Red brightness, 0 = minimum (off), 255 = maximum. + @param g Green brightness, 0 = minimum (off), 255 = maximum. + @param b Blue brightness, 0 = minimum (off), 255 = maximum. + @param w White brightness, 0 = minimum (off), 255 = maximum, ignored + if using RGB pixels. +*/ +void Adafruit_NeoPixel::setPixelColor( + uint16_t n, uint8_t r, uint8_t g, uint8_t b, uint8_t w) { + + if(n < numLEDs) { + if(brightness) { // See notes in setBrightness() + r = (r * brightness) >> 8; + g = (g * brightness) >> 8; + b = (b * brightness) >> 8; + w = (w * brightness) >> 8; + } + uint8_t *p; + if(wOffset == rOffset) { // Is an RGB-type strip + p = &pixels[n * 3]; // 3 bytes per pixel (ignore W) + } else { // Is a WRGB-type strip + p = &pixels[n * 4]; // 4 bytes per pixel + p[wOffset] = w; // Store W + } + p[rOffset] = r; // Store R,G,B + p[gOffset] = g; + p[bOffset] = b; + } +} + +/*! + @brief Set a pixel's color using a 32-bit 'packed' RGB or RGBW value. + @param n Pixel index, starting from 0. + @param c 32-bit color value. Most significant byte is white (for RGBW + pixels) or ignored (for RGB pixels), next is red, then green, + and least significant byte is blue. +*/ +void Adafruit_NeoPixel::setPixelColor(uint16_t n, uint32_t c) { + if(n < numLEDs) { + uint8_t *p, + r = (uint8_t)(c >> 16), + g = (uint8_t)(c >> 8), + b = (uint8_t)c; + if(brightness) { // See notes in setBrightness() + r = (r * brightness) >> 8; + g = (g * brightness) >> 8; + b = (b * brightness) >> 8; + } + if(wOffset == rOffset) { + p = &pixels[n * 3]; + } else { + p = &pixels[n * 4]; + uint8_t w = (uint8_t)(c >> 24); + p[wOffset] = brightness ? ((w * brightness) >> 8) : w; + } + p[rOffset] = r; + p[gOffset] = g; + p[bOffset] = b; + } +} + +/*! + @brief Fill all or part of the NeoPixel strip with a color. + @param c 32-bit color value. Most significant byte is white (for + RGBW pixels) or ignored (for RGB pixels), next is red, + then green, and least significant byte is blue. If all + arguments are unspecified, this will be 0 (off). + @param first Index of first pixel to fill, starting from 0. Must be + in-bounds, no clipping is performed. 0 if unspecified. + @param count Number of pixels to fill, as a positive value. Passing + 0 or leaving unspecified will fill to end of strip. +*/ +void Adafruit_NeoPixel::fill(uint32_t c, uint16_t first, uint16_t count) { + uint16_t i, end; + + if(first >= numLEDs) { + return; // If first LED is past end of strip, nothing to do + } + + // Calculate the index ONE AFTER the last pixel to fill + if(count == 0) { + // Fill to end of strip + end = numLEDs; + } else { + // Ensure that the loop won't go past the last pixel + end = first + count; + if(end > numLEDs) end = numLEDs; + } + + for(i = first; i < end; i++) { + this->setPixelColor(i, c); + } +} + +/*! + @brief Convert hue, saturation and value into a packed 32-bit RGB color + that can be passed to setPixelColor() or other RGB-compatible + functions. + @param hue An unsigned 16-bit value, 0 to 65535, representing one full + loop of the color wheel, which allows 16-bit hues to "roll + over" while still doing the expected thing (and allowing + more precision than the wheel() function that was common to + prior NeoPixel examples). + @param sat Saturation, 8-bit value, 0 (min or pure grayscale) to 255 + (max or pure hue). Default of 255 if unspecified. + @param val Value (brightness), 8-bit value, 0 (min / black / off) to + 255 (max or full brightness). Default of 255 if unspecified. + @return Packed 32-bit RGB with the most significant byte set to 0 -- the + white element of WRGB pixels is NOT utilized. Result is linearly + but not perceptually correct, so you may want to pass the result + through the gamma32() function (or your own gamma-correction + operation) else colors may appear washed out. This is not done + automatically by this function because coders may desire a more + refined gamma-correction function than the simplified + one-size-fits-all operation of gamma32(). Diffusing the LEDs also + really seems to help when using low-saturation colors. +*/ +uint32_t Adafruit_NeoPixel::ColorHSV(uint16_t hue, uint8_t sat, uint8_t val) { + + uint8_t r, g, b; + + // Remap 0-65535 to 0-1529. Pure red is CENTERED on the 64K rollover; + // 0 is not the start of pure red, but the midpoint...a few values above + // zero and a few below 65536 all yield pure red (similarly, 32768 is the + // midpoint, not start, of pure cyan). The 8-bit RGB hexcone (256 values + // each for red, green, blue) really only allows for 1530 distinct hues + // (not 1536, more on that below), but the full unsigned 16-bit type was + // chosen for hue so that one's code can easily handle a contiguous color + // wheel by allowing hue to roll over in either direction. + hue = (hue * 1530L + 32768) / 65536; + // Because red is centered on the rollover point (the +32768 above, + // essentially a fixed-point +0.5), the above actually yields 0 to 1530, + // where 0 and 1530 would yield the same thing. Rather than apply a + // costly modulo operator, 1530 is handled as a special case below. + + // So you'd think that the color "hexcone" (the thing that ramps from + // pure red, to pure yellow, to pure green and so forth back to red, + // yielding six slices), and with each color component having 256 + // possible values (0-255), might have 1536 possible items (6*256), + // but in reality there's 1530. This is because the last element in + // each 256-element slice is equal to the first element of the next + // slice, and keeping those in there this would create small + // discontinuities in the color wheel. So the last element of each + // slice is dropped...we regard only elements 0-254, with item 255 + // being picked up as element 0 of the next slice. Like this: + // Red to not-quite-pure-yellow is: 255, 0, 0 to 255, 254, 0 + // Pure yellow to not-quite-pure-green is: 255, 255, 0 to 1, 255, 0 + // Pure green to not-quite-pure-cyan is: 0, 255, 0 to 0, 255, 254 + // and so forth. Hence, 1530 distinct hues (0 to 1529), and hence why + // the constants below are not the multiples of 256 you might expect. + + // Convert hue to R,G,B (nested ifs faster than divide+mod+switch): + if(hue < 510) { // Red to Green-1 + b = 0; + if(hue < 255) { // Red to Yellow-1 + r = 255; + g = hue; // g = 0 to 254 + } else { // Yellow to Green-1 + r = 510 - hue; // r = 255 to 1 + g = 255; + } + } else if(hue < 1020) { // Green to Blue-1 + r = 0; + if(hue < 765) { // Green to Cyan-1 + g = 255; + b = hue - 510; // b = 0 to 254 + } else { // Cyan to Blue-1 + g = 1020 - hue; // g = 255 to 1 + b = 255; + } + } else if(hue < 1530) { // Blue to Red-1 + g = 0; + if(hue < 1275) { // Blue to Magenta-1 + r = hue - 1020; // r = 0 to 254 + b = 255; + } else { // Magenta to Red-1 + r = 255; + b = 1530 - hue; // b = 255 to 1 + } + } else { // Last 0.5 Red (quicker than % operator) + r = 255; + g = b = 0; + } + + // Apply saturation and value to R,G,B, pack into 32-bit result: + uint32_t v1 = 1 + val; // 1 to 256; allows >>8 instead of /255 + uint16_t s1 = 1 + sat; // 1 to 256; same reason + uint8_t s2 = 255 - sat; // 255 to 0 + return ((((((r * s1) >> 8) + s2) * v1) & 0xff00) << 8) | + (((((g * s1) >> 8) + s2) * v1) & 0xff00) | + ( ((((b * s1) >> 8) + s2) * v1) >> 8); +} + +/*! + @brief Query the color of a previously-set pixel. + @param n Index of pixel to read (0 = first). + @return 'Packed' 32-bit RGB or WRGB value. Most significant byte is white + (for RGBW pixels) or 0 (for RGB pixels), next is red, then green, + and least significant byte is blue. + @note If the strip brightness has been changed from the default value + of 255, the color read from a pixel may not exactly match what + was previously written with one of the setPixelColor() functions. + This gets more pronounced at lower brightness levels. +*/ +uint32_t Adafruit_NeoPixel::getPixelColor(uint16_t n) const { + if(n >= numLEDs) return 0; // Out of bounds, return no color. + + uint8_t *p; + + if(wOffset == rOffset) { // Is RGB-type device + p = &pixels[n * 3]; + if(brightness) { + // Stored color was decimated by setBrightness(). Returned value + // attempts to scale back to an approximation of the original 24-bit + // value used when setting the pixel color, but there will always be + // some error -- those bits are simply gone. Issue is most + // pronounced at low brightness levels. + return (((uint32_t)(p[rOffset] << 8) / brightness) << 16) | + (((uint32_t)(p[gOffset] << 8) / brightness) << 8) | + ( (uint32_t)(p[bOffset] << 8) / brightness ); + } else { + // No brightness adjustment has been made -- return 'raw' color + return ((uint32_t)p[rOffset] << 16) | + ((uint32_t)p[gOffset] << 8) | + (uint32_t)p[bOffset]; + } + } else { // Is RGBW-type device + p = &pixels[n * 4]; + if(brightness) { // Return scaled color + return (((uint32_t)(p[wOffset] << 8) / brightness) << 24) | + (((uint32_t)(p[rOffset] << 8) / brightness) << 16) | + (((uint32_t)(p[gOffset] << 8) / brightness) << 8) | + ( (uint32_t)(p[bOffset] << 8) / brightness ); + } else { // Return raw color + return ((uint32_t)p[wOffset] << 24) | + ((uint32_t)p[rOffset] << 16) | + ((uint32_t)p[gOffset] << 8) | + (uint32_t)p[bOffset]; + } + } +} + + +/*! + @brief Adjust output brightness. Does not immediately affect what's + currently displayed on the LEDs. The next call to show() will + refresh the LEDs at this level. + @param b Brightness setting, 0=minimum (off), 255=brightest. + @note This was intended for one-time use in one's setup() function, + not as an animation effect in itself. Because of the way this + library "pre-multiplies" LED colors in RAM, changing the + brightness is often a "lossy" operation -- what you write to + pixels isn't necessary the same as what you'll read back. + Repeated brightness changes using this function exacerbate the + problem. Smart programs therefore treat the strip as a + write-only resource, maintaining their own state to render each + frame of an animation, not relying on read-modify-write. +*/ +void Adafruit_NeoPixel::setBrightness(uint8_t b) { + // Stored brightness value is different than what's passed. + // This simplifies the actual scaling math later, allowing a fast + // 8x8-bit multiply and taking the MSB. 'brightness' is a uint8_t, + // adding 1 here may (intentionally) roll over...so 0 = max brightness + // (color values are interpreted literally; no scaling), 1 = min + // brightness (off), 255 = just below max brightness. + uint8_t newBrightness = b + 1; + if(newBrightness != brightness) { // Compare against prior value + // Brightness has changed -- re-scale existing data in RAM, + // This process is potentially "lossy," especially when increasing + // brightness. The tight timing in the WS2811/WS2812 code means there + // aren't enough free cycles to perform this scaling on the fly as data + // is issued. So we make a pass through the existing color data in RAM + // and scale it (subsequent graphics commands also work at this + // brightness level). If there's a significant step up in brightness, + // the limited number of steps (quantization) in the old data will be + // quite visible in the re-scaled version. For a non-destructive + // change, you'll need to re-render the full strip data. C'est la vie. + uint8_t c, + *ptr = pixels, + oldBrightness = brightness - 1; // De-wrap old brightness value + uint16_t scale; + if(oldBrightness == 0) scale = 0; // Avoid /0 + else if(b == 255) scale = 65535 / oldBrightness; + else scale = (((uint16_t)newBrightness << 8) - 1) / oldBrightness; + for(uint16_t i=0; i> 8; + } + brightness = newBrightness; + } +} + +/*! + @brief Retrieve the last-set brightness value for the strip. + @return Brightness value: 0 = minimum (off), 255 = maximum. +*/ +uint8_t Adafruit_NeoPixel::getBrightness(void) const { + return brightness - 1; +} + +/*! + @brief Fill the whole NeoPixel strip with 0 / black / off. +*/ +void Adafruit_NeoPixel::clear(void) { + memset(pixels, 0, numBytes); +} + +// A 32-bit variant of gamma8() that applies the same function +// to all components of a packed RGB or WRGB value. +uint32_t Adafruit_NeoPixel::gamma32(uint32_t x) { + uint8_t *y = (uint8_t *)&x; + // All four bytes of a 32-bit value are filtered even if RGB (not WRGB), + // to avoid a bunch of shifting and masking that would be necessary for + // properly handling different endianisms (and each byte is a fairly + // trivial operation, so it might not even be wasting cycles vs a check + // and branch for the RGB case). In theory this might cause trouble *if* + // someone's storing information in the unused most significant byte + // of an RGB value, but this seems exceedingly rare and if it's + // encountered in reality they can mask values going in or coming out. + for(uint8_t i=0; i<4; i++) y[i] = gamma8(y[i]); + return x; // Packed 32-bit return +} diff --git a/libraries/RGB/src/Adafruit_NeoPixel.h b/libraries/RGB/src/Adafruit_NeoPixel.h new file mode 100644 index 00000000..b9f28fad --- /dev/null +++ b/libraries/RGB/src/Adafruit_NeoPixel.h @@ -0,0 +1,345 @@ +/*! + * @file Adafruit_NeoPixel.h + * + * This is part of Adafruit's NeoPixel library for the Arduino platform, + * allowing a broad range of microcontroller boards (most AVR boards, + * many ARM devices, ESP8266 and ESP32, among others) to control Adafruit + * NeoPixels, FLORA RGB Smart Pixels and compatible devices -- WS2811, + * WS2812, WS2812B, SK6812, etc. + * + * Adafruit invests time and resources providing this open source code, + * please support Adafruit and open-source hardware by purchasing products + * from Adafruit! + * + * Written by Phil "Paint Your Dragon" Burgess for Adafruit Industries, + * with contributions by PJRC, Michael Miller and other members of the + * open source community. + * + * This file is part of the Adafruit_NeoPixel library. + * + * Adafruit_NeoPixel is free software: you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation, either version 3 of the + * License, or (at your option) any later version. + * + * Adafruit_NeoPixel is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with NeoPixel. If not, see + * . + * + */ + +#ifndef ADAFRUIT_NEOPIXEL_H +#define ADAFRUIT_NEOPIXEL_H + + + #include + + +// The order of primary colors in the NeoPixel data stream can vary among +// device types, manufacturers and even different revisions of the same +// item. The third parameter to the Adafruit_NeoPixel constructor encodes +// the per-pixel byte offsets of the red, green and blue primaries (plus +// white, if present) in the data stream -- the following #defines provide +// an easier-to-use named version for each permutation. e.g. NEO_GRB +// indicates a NeoPixel-compatible device expecting three bytes per pixel, +// with the first byte transmitted containing the green value, second +// containing red and third containing blue. The in-memory representation +// of a chain of NeoPixels is the same as the data-stream order; no +// re-ordering of bytes is required when issuing data to the chain. +// Most of these values won't exist in real-world devices, but it's done +// this way so we're ready for it (also, if using the WS2811 driver IC, +// one might have their pixels set up in any weird permutation). + +// Bits 5,4 of this value are the offset (0-3) from the first byte of a +// pixel to the location of the red color byte. Bits 3,2 are the green +// offset and 1,0 are the blue offset. If it is an RGBW-type device +// (supporting a white primary in addition to R,G,B), bits 7,6 are the +// offset to the white byte...otherwise, bits 7,6 are set to the same value +// as 5,4 (red) to indicate an RGB (not RGBW) device. +// i.e. binary representation: +// 0bWWRRGGBB for RGBW devices +// 0bRRRRGGBB for RGB + +// RGB NeoPixel permutations; white and red offsets are always same +// Offset: W R G B +#define NEO_RGB ((0<<6) | (0<<4) | (1<<2) | (2)) ///< Transmit as R,G,B +#define NEO_RBG ((0<<6) | (0<<4) | (2<<2) | (1)) ///< Transmit as R,B,G +#define NEO_GRB ((1<<6) | (1<<4) | (0<<2) | (2)) ///< Transmit as G,R,B +#define NEO_GBR ((2<<6) | (2<<4) | (0<<2) | (1)) ///< Transmit as G,B,R +#define NEO_BRG ((1<<6) | (1<<4) | (2<<2) | (0)) ///< Transmit as B,R,G +#define NEO_BGR ((2<<6) | (2<<4) | (1<<2) | (0)) ///< Transmit as B,G,R + +// RGBW NeoPixel permutations; all 4 offsets are distinct +// Offset: W R G B +#define NEO_WRGB ((0<<6) | (1<<4) | (2<<2) | (3)) ///< Transmit as W,R,G,B +#define NEO_WRBG ((0<<6) | (1<<4) | (3<<2) | (2)) ///< Transmit as W,R,B,G +#define NEO_WGRB ((0<<6) | (2<<4) | (1<<2) | (3)) ///< Transmit as W,G,R,B +#define NEO_WGBR ((0<<6) | (3<<4) | (1<<2) | (2)) ///< Transmit as W,G,B,R +#define NEO_WBRG ((0<<6) | (2<<4) | (3<<2) | (1)) ///< Transmit as W,B,R,G +#define NEO_WBGR ((0<<6) | (3<<4) | (2<<2) | (1)) ///< Transmit as W,B,G,R + +#define NEO_RWGB ((1<<6) | (0<<4) | (2<<2) | (3)) ///< Transmit as R,W,G,B +#define NEO_RWBG ((1<<6) | (0<<4) | (3<<2) | (2)) ///< Transmit as R,W,B,G +#define NEO_RGWB ((2<<6) | (0<<4) | (1<<2) | (3)) ///< Transmit as R,G,W,B +#define NEO_RGBW ((3<<6) | (0<<4) | (1<<2) | (2)) ///< Transmit as R,G,B,W +#define NEO_RBWG ((2<<6) | (0<<4) | (3<<2) | (1)) ///< Transmit as R,B,W,G +#define NEO_RBGW ((3<<6) | (0<<4) | (2<<2) | (1)) ///< Transmit as R,B,G,W + +#define NEO_GWRB ((1<<6) | (2<<4) | (0<<2) | (3)) ///< Transmit as G,W,R,B +#define NEO_GWBR ((1<<6) | (3<<4) | (0<<2) | (2)) ///< Transmit as G,W,B,R +#define NEO_GRWB ((2<<6) | (1<<4) | (0<<2) | (3)) ///< Transmit as G,R,W,B +#define NEO_GRBW ((3<<6) | (1<<4) | (0<<2) | (2)) ///< Transmit as G,R,B,W +#define NEO_GBWR ((2<<6) | (3<<4) | (0<<2) | (1)) ///< Transmit as G,B,W,R +#define NEO_GBRW ((3<<6) | (2<<4) | (0<<2) | (1)) ///< Transmit as G,B,R,W + +#define NEO_BWRG ((1<<6) | (2<<4) | (3<<2) | (0)) ///< Transmit as B,W,R,G +#define NEO_BWGR ((1<<6) | (3<<4) | (2<<2) | (0)) ///< Transmit as B,W,G,R +#define NEO_BRWG ((2<<6) | (1<<4) | (3<<2) | (0)) ///< Transmit as B,R,W,G +#define NEO_BRGW ((3<<6) | (1<<4) | (2<<2) | (0)) ///< Transmit as B,R,G,W +#define NEO_BGWR ((2<<6) | (3<<4) | (1<<2) | (0)) ///< Transmit as B,G,W,R +#define NEO_BGRW ((3<<6) | (2<<4) | (1<<2) | (0)) ///< Transmit as B,G,R,W + +// Add NEO_KHZ400 to the color order value to indicate a 400 KHz device. +// All but the earliest v1 NeoPixels expect an 800 KHz data stream, this is +// the default if unspecified. Because flash space is very limited on ATtiny +// devices (e.g. Trinket, Gemma), v1 NeoPixels aren't handled by default on +// those chips, though it can be enabled by removing the ifndef/endif below, +// but code will be bigger. Conversely, can disable the NEO_KHZ400 line on +// other MCUs to remove v1 support and save a little space. + +#define NEO_KHZ800 0x0000 ///< 800 KHz data transmission +#ifndef __AVR_ATtiny85__ +#define NEO_KHZ400 0x0100 ///< 400 KHz data transmission +#endif + +// If 400 KHz support is enabled, the third parameter to the constructor +// requires a 16-bit value (in order to select 400 vs 800 KHz speed). +// If only 800 KHz is enabled (as is default on ATtiny), an 8-bit value +// is sufficient to encode pixel color order, saving some space. + +#ifdef NEO_KHZ400 +typedef uint16_t neoPixelType; ///< 3rd arg to Adafruit_NeoPixel constructor +#else +typedef uint8_t neoPixelType; ///< 3rd arg to Adafruit_NeoPixel constructor +#endif + +// These two tables are declared outside the Adafruit_NeoPixel class +// because some boards may require oldschool compilers that don't +// handle the C++11 constexpr keyword. + +/* A PROGMEM (flash mem) table containing 8-bit unsigned sine wave (0-255). + Copy & paste this snippet into a Python REPL to regenerate: +import math +for x in range(256): + print("{:3},".format(int((math.sin(x/128.0*math.pi)+1.0)*127.5+0.5))), + if x&15 == 15: print +*/ +static const uint8_t PROGMEM _NeoPixelSineTable[256] = { + 128,131,134,137,140,143,146,149,152,155,158,162,165,167,170,173, + 176,179,182,185,188,190,193,196,198,201,203,206,208,211,213,215, + 218,220,222,224,226,228,230,232,234,235,237,238,240,241,243,244, + 245,246,248,249,250,250,251,252,253,253,254,254,254,255,255,255, + 255,255,255,255,254,254,254,253,253,252,251,250,250,249,248,246, + 245,244,243,241,240,238,237,235,234,232,230,228,226,224,222,220, + 218,215,213,211,208,206,203,201,198,196,193,190,188,185,182,179, + 176,173,170,167,165,162,158,155,152,149,146,143,140,137,134,131, + 128,124,121,118,115,112,109,106,103,100, 97, 93, 90, 88, 85, 82, + 79, 76, 73, 70, 67, 65, 62, 59, 57, 54, 52, 49, 47, 44, 42, 40, + 37, 35, 33, 31, 29, 27, 25, 23, 21, 20, 18, 17, 15, 14, 12, 11, + 10, 9, 7, 6, 5, 5, 4, 3, 2, 2, 1, 1, 1, 0, 0, 0, + 0, 0, 0, 0, 1, 1, 1, 2, 2, 3, 4, 5, 5, 6, 7, 9, + 10, 11, 12, 14, 15, 17, 18, 20, 21, 23, 25, 27, 29, 31, 33, 35, + 37, 40, 42, 44, 47, 49, 52, 54, 57, 59, 62, 65, 67, 70, 73, 76, + 79, 82, 85, 88, 90, 93, 97,100,103,106,109,112,115,118,121,124}; + +/* Similar to above, but for an 8-bit gamma-correction table. + Copy & paste this snippet into a Python REPL to regenerate: +import math +gamma=2.6 +for x in range(256): + print("{:3},".format(int(math.pow((x)/255.0,gamma)*255.0+0.5))), + if x&15 == 15: print +*/ +static const uint8_t PROGMEM _NeoPixelGammaTable[256] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, + 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6, 6, 7, + 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, + 13, 13, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 19, 19, 20, + 20, 21, 21, 22, 22, 23, 24, 24, 25, 25, 26, 27, 27, 28, 29, 29, + 30, 31, 31, 32, 33, 34, 34, 35, 36, 37, 38, 38, 39, 40, 41, 42, + 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, + 58, 59, 60, 61, 62, 63, 64, 65, 66, 68, 69, 70, 71, 72, 73, 75, + 76, 77, 78, 80, 81, 82, 84, 85, 86, 88, 89, 90, 92, 93, 94, 96, + 97, 99,100,102,103,105,106,108,109,111,112,114,115,117,119,120, + 122,124,125,127,129,130,132,134,136,137,139,141,143,145,146,148, + 150,152,154,156,158,160,162,164,166,168,170,172,174,176,178,180, + 182,184,186,188,191,193,195,197,199,202,204,206,209,211,213,215, + 218,220,223,225,227,230,232,235,237,240,242,245,247,250,252,255}; + +/*! + @brief Class that stores state and functions for interacting with + Adafruit NeoPixels and compatible devices. +*/ +class Adafruit_NeoPixel { + + public: + + // Constructor: number of LEDs, pin number, LED type + Adafruit_NeoPixel(uint16_t n, uint8_t pin=6, + neoPixelType type=NEO_GRB + NEO_KHZ800); + Adafruit_NeoPixel(void); + ~Adafruit_NeoPixel(); + + void begin(void); + void show(void); + void setPin(uint8_t p); + void setPixelColor(uint16_t n, uint8_t r, uint8_t g, uint8_t b); + void setPixelColor(uint16_t n, uint8_t r, uint8_t g, uint8_t b, + uint8_t w); + void setPixelColor(uint16_t n, uint32_t c); + void fill(uint32_t c=0, uint16_t first=0, uint16_t count=0); + void setBrightness(uint8_t); + void clear(void); + void updateLength(uint16_t n); + void updateType(neoPixelType t); + /*! + @brief Check whether a call to show() will start sending data + immediately or will 'block' for a required interval. NeoPixels + require a short quiet time (about 300 microseconds) after the + last bit is received before the data 'latches' and new data can + start being received. Usually one's sketch is implicitly using + this time to generate a new frame of animation...but if it + finishes very quickly, this function could be used to see if + there's some idle time available for some low-priority + concurrent task. + @return 1 or true if show() will start sending immediately, 0 or false + if show() would block (meaning some idle time is available). + */ + boolean canShow(void) { return 1; } + /*! + @brief Get a pointer directly to the NeoPixel data buffer in RAM. + Pixel data is stored in a device-native format (a la the NEO_* + constants) and is not translated here. Applications that access + this buffer will need to be aware of the specific data format + and handle colors appropriately. + @return Pointer to NeoPixel buffer (uint8_t* array). + @note This is for high-performance applications where calling + setPixelColor() on every single pixel would be too slow (e.g. + POV or light-painting projects). There is no bounds checking + on the array, creating tremendous potential for mayhem if one + writes past the ends of the buffer. Great power, great + responsibility and all that. + */ + uint8_t *getPixels(void) const { return pixels; }; + uint8_t getBrightness(void) const; + /*! + @brief Retrieve the pin number used for NeoPixel data output. + @return Arduino pin number (-1 if not set). + */ + int8_t getPin(void) const { return pin; }; + /*! + @brief Return the number of pixels in an Adafruit_NeoPixel strip object. + @return Pixel count (0 if not set). + */ + uint16_t numPixels(void) const { return numLEDs; } + uint32_t getPixelColor(uint16_t n) const; + /*! + @brief An 8-bit integer sine wave function, not directly compatible + with standard trigonometric units like radians or degrees. + @param x Input angle, 0-255; 256 would loop back to zero, completing + the circle (equivalent to 360 degrees or 2 pi radians). + One can therefore use an unsigned 8-bit variable and simply + add or subtract, allowing it to overflow/underflow and it + still does the expected contiguous thing. + @return Sine result, 0 to 255, or -128 to +127 if type-converted to + a signed int8_t, but you'll most likely want unsigned as this + output is often used for pixel brightness in animation effects. + */ + static uint8_t sine8(uint8_t x) { + return pgm_read_byte(&_NeoPixelSineTable[x]); // 0-255 in, 0-255 out + } + /*! + @brief An 8-bit gamma-correction function for basic pixel brightness + adjustment. Makes color transitions appear more perceptially + correct. + @param x Input brightness, 0 (minimum or off/black) to 255 (maximum). + @return Gamma-adjusted brightness, can then be passed to one of the + setPixelColor() functions. This uses a fixed gamma correction + exponent of 2.6, which seems reasonably okay for average + NeoPixels in average tasks. If you need finer control you'll + need to provide your own gamma-correction function instead. + */ + static uint8_t gamma8(uint8_t x) { + return pgm_read_byte(&_NeoPixelGammaTable[x]); // 0-255 in, 0-255 out + } + /*! + @brief Convert separate red, green and blue values into a single + "packed" 32-bit RGB color. + @param r Red brightness, 0 to 255. + @param g Green brightness, 0 to 255. + @param b Blue brightness, 0 to 255. + @return 32-bit packed RGB value, which can then be assigned to a + variable for later use or passed to the setPixelColor() + function. Packed RGB format is predictable, regardless of + LED strand color order. + */ + static uint32_t Color(uint8_t r, uint8_t g, uint8_t b) { + return ((uint32_t)r << 16) | ((uint32_t)g << 8) | b; + } + /*! + @brief Convert separate red, green, blue and white values into a + single "packed" 32-bit WRGB color. + @param r Red brightness, 0 to 255. + @param g Green brightness, 0 to 255. + @param b Blue brightness, 0 to 255. + @param w White brightness, 0 to 255. + @return 32-bit packed WRGB value, which can then be assigned to a + variable for later use or passed to the setPixelColor() + function. Packed WRGB format is predictable, regardless of + LED strand color order. + */ + static uint32_t Color(uint8_t r, uint8_t g, uint8_t b, uint8_t w) { + return ((uint32_t)w << 24) | ((uint32_t)r << 16) | ((uint32_t)g << 8) | b; + } + static uint32_t ColorHSV(uint16_t hue, uint8_t sat=255, uint8_t val=255); + /*! + @brief A gamma-correction function for 32-bit packed RGB or WRGB + colors. Makes color transitions appear more perceptially + correct. + @param x 32-bit packed RGB or WRGB color. + @return Gamma-adjusted packed color, can then be passed in one of the + setPixelColor() functions. Like gamma8(), this uses a fixed + gamma correction exponent of 2.6, which seems reasonably okay + for average NeoPixels in average tasks. If you need finer + control you'll need to provide your own gamma-correction + function instead. + */ + static uint32_t gamma32(uint32_t x); + + protected: + +#ifdef NEO_KHZ400 // If 400 KHz NeoPixel support enabled... + boolean is800KHz; ///< true if 800 KHz pixels +#endif + boolean begun; ///< true if begin() previously called + uint16_t numLEDs; ///< Number of RGB LEDs in strip + uint16_t numBytes; ///< Size of 'pixels' buffer below + int8_t pin; ///< Output pin number (-1 if not yet set) + uint8_t brightness; ///< Strip brightness 0-255 (stored as +1) + uint8_t *pixels; ///< Holds LED color values (3 or 4 bytes each) + uint8_t rOffset; ///< Red index within each 3- or 4-byte pixel + uint8_t gOffset; ///< Index of green byte + uint8_t bOffset; ///< Index of blue byte + uint8_t wOffset; ///< Index of white (==rOffset if no white) + uint32_t endTime; ///< Latch timing reference + +}; + +#endif // ADAFRUIT_NEOPIXEL_H diff --git a/libraries/SSD1306_I2C/examples/SSD1306DrawingDemo/SSD1306DrawingDemo.ino b/libraries/SSD1306_I2C/examples/SSD1306DrawingDemo/SSD1306DrawingDemo.ino new file mode 100644 index 00000000..0d4b3a7e --- /dev/null +++ b/libraries/SSD1306_I2C/examples/SSD1306DrawingDemo/SSD1306DrawingDemo.ino @@ -0,0 +1,186 @@ +/* + * HelTec Automation(TM) ESP32 Series Dev boards OLED Drawing Function test code + * + * - Some OLED Drawing Function function test; + * + * by lxyzn from HelTec AutoMation, ChengDu, China + *  + * www.heltec.cn + * + * this project also realess in GitHub: + * https://github.com/HelTecAutomation/Heltec_ESP32 +*/ + + +// This example just provide basic function test; +// For more informations, please vist www.heltec.cn or mail to support@heltec.cn + +#include "Arduino.h" +#include "heltec.h" + +#define DISPLAY_HEIGHT 64 +#define DISPLAY_WIDTH 128 +// Adapted from Adafruit_SSD1306 +void drawLines() { + for (int16_t i=0; idrawLine(0, 0, i, DISPLAY_HEIGHT-1); + Heltec.display->display(); + delay(10); + } + for (int16_t i=0; idrawLine(0, 0, DISPLAY_WIDTH-1, i); + Heltec.display->display(); + delay(10); + } + delay(250); + + Heltec.display->clear(); + for (int16_t i=0; idrawLine(0, DISPLAY_HEIGHT-1, i, 0); + Heltec.display->display(); + delay(10); + } + for (int16_t i=DISPLAY_HEIGHT-1; i>=0; i-=4) { + Heltec.display->drawLine(0, DISPLAY_HEIGHT-1, DISPLAY_WIDTH-1, i); + Heltec.display->display(); + delay(10); + } + delay(250); + + Heltec.display->clear(); + for (int16_t i=DISPLAY_WIDTH-1; i>=0; i-=4) { + Heltec.display->drawLine(DISPLAY_WIDTH-1, DISPLAY_HEIGHT-1, i, 0); + Heltec.display->display(); + delay(10); + } + for (int16_t i=DISPLAY_HEIGHT-1; i>=0; i-=4) { + Heltec.display->drawLine(DISPLAY_WIDTH-1, DISPLAY_HEIGHT-1, 0, i); + Heltec.display->display(); + delay(10); + } + delay(250); + Heltec.display->clear(); + for (int16_t i=0; idrawLine(DISPLAY_WIDTH-1, 0, 0, i); + Heltec.display->display(); + delay(10); + } + for (int16_t i=0; idrawLine(DISPLAY_WIDTH-1, 0, i, DISPLAY_HEIGHT-1); + Heltec.display->display(); + delay(10); + } + delay(250); +} + +// Adapted from Adafruit_SSD1306 +void drawRect(void) { + for (int16_t i=0; idrawRect(i, i, DISPLAY_WIDTH-2*i, DISPLAY_HEIGHT-2*i); + Heltec.display->display(); + delay(10); + } +} + +// Adapted from Adafruit_SSD1306 +void fillRect(void) { + uint8_t color = 1; + for (int16_t i=0; isetColor((color % 2 == 0) ? BLACK : WHITE); // alternate colors + Heltec.display->fillRect(i, i, DISPLAY_WIDTH - i*2, DISPLAY_HEIGHT - i*2); + Heltec.display->display(); + delay(10); + color++; + } + // Reset back to WHITE + Heltec.display->setColor(WHITE); +} + +// Adapted from Adafruit_SSD1306 +void drawCircle(void) { + for (int16_t i=0; idrawCircle(DISPLAY_WIDTH/2, DISPLAY_HEIGHT/2, i); + Heltec.display->display(); + delay(10); + } + delay(1000); + Heltec.display->clear(); + + // This will draw the part of the circel in quadrant 1 + // Quadrants are numberd like this: + // 0010 | 0001 + // ------|----- + // 0100 | 1000 + // + Heltec.display->drawCircleQuads(DISPLAY_WIDTH/2, DISPLAY_HEIGHT/2, DISPLAY_HEIGHT/4, 0b00000001); + Heltec.display->display(); + delay(200); + Heltec.display->drawCircleQuads(DISPLAY_WIDTH/2, DISPLAY_HEIGHT/2, DISPLAY_HEIGHT/4, 0b00000011); + Heltec.display->display(); + delay(200); + Heltec.display->drawCircleQuads(DISPLAY_WIDTH/2, DISPLAY_HEIGHT/2, DISPLAY_HEIGHT/4, 0b00000111); + Heltec.display->display(); + delay(200); + Heltec.display->drawCircleQuads(DISPLAY_WIDTH/2, DISPLAY_HEIGHT/2, DISPLAY_HEIGHT/4, 0b00001111); + Heltec.display->display(); +} + +void printBuffer(void) { + // Initialize the log buffer + // allocate memory to store 8 lines of text and 30 chars per line. + Heltec.display->setLogBuffer(5, 30); + + // Some test data + const char* test[] = { + "Hello", + "World" , + "----", + "Show off", + "how", + "the log buffer", + "is", + "working.", + "Even", + "scrolling is", + "working" + }; + + for (uint8_t i = 0; i < 11; i++) { + Heltec.display->clear(); + // Print to the screen + Heltec.display->println(test[i]); + // Draw it to the internal screen buffer + Heltec.display->drawLogBuffer(0, 0); + // Display it on the screen + Heltec.display->display(); + delay(500); + } +} + +void setup() { + Heltec.begin(true /*DisplayEnable Enable*/, true /*Serial Enable*/); + + Heltec.display->setContrast(255); + + drawLines(); + delay(1000); + Heltec.display->clear(); + + drawRect(); + delay(1000); + Heltec.display->clear(); + + fillRect(); + delay(1000); + Heltec.display->clear(); + + drawCircle(); + delay(1000); + Heltec.display->clear(); + + printBuffer(); + delay(1000); + Heltec.display->clear(); +} + +void loop() { } diff --git a/libraries/SSD1306_I2C/examples/SSD1306SimpleDemo/SSD1306SimpleDemo.ino b/libraries/SSD1306_I2C/examples/SSD1306SimpleDemo/SSD1306SimpleDemo.ino new file mode 100644 index 00000000..cb94f604 --- /dev/null +++ b/libraries/SSD1306_I2C/examples/SSD1306SimpleDemo/SSD1306SimpleDemo.ino @@ -0,0 +1,142 @@ +/* + * HelTec Automation(TM) ESP32 Series Dev boards OLED draw Simple Function test code + * + * - Some OLED draw Simple Function function test; + * + * by LXYZN from HelTec AutoMation, ChengDu, China + *  + * www.heltec.cn + * + * this project also realess in GitHub: + * https://github.com/HelTecAutomation/Heltec_ESP32 +*/ + + +// This example just provide basic function test; +// For more informations, please vist www.heltec.cn or mail to support@heltec.cn + +#include "Arduino.h" +#include "heltec.h" +#include "images.h" + + + +#define DEMO_DURATION 3000 +typedef void (*Demo)(void); + +int demoMode = 0; +int counter = 1; + +void setup() { + Heltec.begin(true /*DisplayEnable Enable*/, true /*Serial Enable*/); + + + + Heltec.display->flipScreenVertically(); + Heltec.display->setFont(ArialMT_Plain_10); + +} + +void drawFontFaceDemo() { + // Font Demo1 + // create more fonts at http://oleddisplay.squix.ch/ + Heltec.display->setTextAlignment(TEXT_ALIGN_LEFT); + Heltec.display->setFont(ArialMT_Plain_10); + Heltec.display->drawString(0, 0, "Hello world"); + Heltec.display->setFont(ArialMT_Plain_16); + Heltec.display->drawString(0, 10, "Hello world"); + Heltec.display->setFont(ArialMT_Plain_24); + Heltec.display->drawString(0, 26, "Hello world"); +} + +void drawTextFlowDemo() { + Heltec.display->setFont(ArialMT_Plain_10); + Heltec.display->setTextAlignment(TEXT_ALIGN_LEFT); + Heltec.display->drawStringMaxWidth(0, 0, 128, + "Lorem ipsum\n dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore." ); +} + +void drawTextAlignmentDemo() { + // Text alignment demo + Heltec.display->setFont(ArialMT_Plain_10); + + // The coordinates define the left starting point of the text + Heltec.display->setTextAlignment(TEXT_ALIGN_LEFT); + Heltec.display->drawString(0, 10, "Left aligned (0,10)"); + + // The coordinates define the center of the text + Heltec.display->setTextAlignment(TEXT_ALIGN_CENTER); + Heltec.display->drawString(64, 22, "Center aligned (64,22)"); + + // The coordinates define the right end of the text + Heltec.display->setTextAlignment(TEXT_ALIGN_RIGHT); + Heltec.display->drawString(128, 33, "Right aligned (128,33)"); +} + +void drawRectDemo() { + // Draw a pixel at given position + for (int i = 0; i < 10; i++) { + Heltec.display->setPixel(i, i); + Heltec.display->setPixel(10 - i, i); + } + Heltec.display->drawRect(12, 12, 20, 20); + + // Fill the rectangle + Heltec.display->fillRect(14, 14, 17, 17); + + // Draw a line horizontally + Heltec.display->drawHorizontalLine(0, 40, 20); + + // Draw a line horizontally + Heltec.display->drawVerticalLine(40, 0, 20); +} + +void drawCircleDemo() { + for (int i=1; i < 8; i++) { + Heltec.display->setColor(WHITE); + Heltec.display->drawCircle(32, 32, i*3); + if (i % 2 == 0) { + Heltec.display->setColor(BLACK); + } + Heltec.display->fillCircle(96, 32, 32 - i* 3); + } +} + +void drawProgressBarDemo() { + int progress = (counter / 5) % 100; + // draw the progress bar + Heltec.display->drawProgressBar(0, 32, 120, 10, progress); + + // draw the percentage as String + Heltec.display->setTextAlignment(TEXT_ALIGN_CENTER); + Heltec.display->drawString(64, 15, String(progress) + "%"); +} + +void drawImageDemo() { + // see http://blog.squix.org/2015/05/esp8266-nodemcu-how-to-create-xbm.html + // on how to create xbm files + Heltec.display->drawXbm(34, 14, WiFi_Logo_width, WiFi_Logo_height, WiFi_Logo_bits); +} + +Demo demos[] = {drawFontFaceDemo, drawTextFlowDemo, drawTextAlignmentDemo, drawRectDemo, drawCircleDemo, drawProgressBarDemo, drawImageDemo}; +int demoLength = (sizeof(demos) / sizeof(Demo)); +long timeSinceLastModeSwitch = 0; + +void loop() { + // clear the display + Heltec.display->clear(); + // draw the current demo method + demos[demoMode](); + + Heltec.display->setTextAlignment(TEXT_ALIGN_RIGHT); + Heltec.display->drawString(10, 128, String(millis())); + // write the buffer to the display + Heltec.display->display(); + + if (millis() - timeSinceLastModeSwitch > DEMO_DURATION) { + demoMode = (demoMode + 1) % demoLength; + timeSinceLastModeSwitch = millis(); + } + counter++; + delay(10); +} diff --git a/libraries/SSD1306_I2C/examples/SSD1306SimpleDemo/images.h b/libraries/SSD1306_I2C/examples/SSD1306SimpleDemo/images.h new file mode 100644 index 00000000..b7cc9087 --- /dev/null +++ b/libraries/SSD1306_I2C/examples/SSD1306SimpleDemo/images.h @@ -0,0 +1,52 @@ +#define WiFi_Logo_width 60 +#define WiFi_Logo_height 36 +const unsigned char WiFi_Logo_bits[] PROGMEM = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0xFF, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, + 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + 0x00, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0x83, 0x01, 0x80, 0xFF, 0xFF, 0xFF, + 0x01, 0x00, 0x07, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x0C, 0x00, + 0xC0, 0xFF, 0xFF, 0x7C, 0x00, 0x60, 0x0C, 0x00, 0xC0, 0x31, 0x46, 0x7C, + 0xFC, 0x77, 0x08, 0x00, 0xE0, 0x23, 0xC6, 0x3C, 0xFC, 0x67, 0x18, 0x00, + 0xE0, 0x23, 0xE4, 0x3F, 0x1C, 0x00, 0x18, 0x00, 0xE0, 0x23, 0x60, 0x3C, + 0x1C, 0x70, 0x18, 0x00, 0xE0, 0x03, 0x60, 0x3C, 0x1C, 0x70, 0x18, 0x00, + 0xE0, 0x07, 0x60, 0x3C, 0xFC, 0x73, 0x18, 0x00, 0xE0, 0x87, 0x70, 0x3C, + 0xFC, 0x73, 0x18, 0x00, 0xE0, 0x87, 0x70, 0x3C, 0x1C, 0x70, 0x18, 0x00, + 0xE0, 0x87, 0x70, 0x3C, 0x1C, 0x70, 0x18, 0x00, 0xE0, 0x8F, 0x71, 0x3C, + 0x1C, 0x70, 0x18, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x08, 0x00, + 0xC0, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x0C, 0x00, 0x80, 0xFF, 0xFF, 0x1F, + 0x00, 0x00, 0x06, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x07, 0x00, + 0x00, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0xF8, 0xFF, 0xFF, + 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x01, 0x00, 0x00, + 0x00, 0x00, 0xFC, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + +//Added by Sloeber +#pragma once + + +//Added by Sloeber +#pragma once + + +//Added by Sloeber +#pragma once + + +//Added by Sloeber +#pragma once + + +//Added by Sloeber +#pragma once + + +//Added by Sloeber +#pragma once + diff --git a/libraries/SSD1306_I2C/library.properties b/libraries/SSD1306_I2C/library.properties new file mode 100644 index 00000000..c43464fb --- /dev/null +++ b/libraries/SSD1306_I2C/library.properties @@ -0,0 +1,9 @@ +name=SSD1306_I2C +version=1.0 +author=Heltec +maintainer= +sentence= +paragraph= +category=Timing +url= +architectures=CubeCell diff --git a/libraries/SSD1306_I2C/src/OLEDDisplay.cpp b/libraries/SSD1306_I2C/src/OLEDDisplay.cpp new file mode 100644 index 00000000..55d00b87 --- /dev/null +++ b/libraries/SSD1306_I2C/src/OLEDDisplay.cpp @@ -0,0 +1,957 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + +#include "OLEDDisplay.h" + +OLEDDisplay::~OLEDDisplay() { + end(); +} + +bool OLEDDisplay::init() { + if (!(this->connect())) { + DEBUG_OLEDDISPLAY("[OLEDDISPLAY][init] Can't establish connection to display\n"); + return false; + } + if(this->buffer==NULL) { + this->buffer = (uint8_t*) malloc(sizeof(uint8_t) * displayBufferSize); + + if(!this->buffer) { + DEBUG_OLEDDISPLAY("[OLEDDISPLAY][init] Not enough memory to create display\n"); + return false; + } + } + + #ifdef OLEDDISPLAY_DOUBLE_BUFFER + if(this->buffer_back==NULL) { + this->buffer_back = (uint8_t*) malloc(sizeof(uint8_t) * displayBufferSize); + + if(!this->buffer_back) { + DEBUG_OLEDDISPLAY("[OLEDDISPLAY][init] Not enough memory to create back buffer\n"); + free(this->buffer); + return false; + } + } + #endif + +// resetDisplay(16); + sendInitCommands(); + resetDisplay(); + + return true; +} + +void OLEDDisplay::end() { + if (this->buffer) { free(this->buffer); this->buffer = NULL; } + #ifdef OLEDDISPLAY_DOUBLE_BUFFER + if (this->buffer_back) { free(this->buffer_back); this->buffer_back = NULL; } + #endif + if (this->logBuffer != NULL) { free(this->logBuffer); this->logBuffer = NULL; } +} + +void OLEDDisplay::sleep() { + sendCommand(0x8D); + sendCommand(0x10); + sendCommand(0xAE); +} + +void OLEDDisplay::wakeup() { + sendCommand(0x8D); + sendCommand(0x14); + sendCommand(0xAF); +} + +void OLEDDisplay::resetDisplay() { + clear(); + #ifdef OLEDDISPLAY_DOUBLE_BUFFER + memset(buffer_back, 1, displayBufferSize); + #endif + display(); +} + +void OLEDDisplay::setColor(OLEDDISPLAY_COLOR color) { + this->color = color; +} + +OLEDDISPLAY_COLOR OLEDDisplay::getColor() { + return this->color; +} + +void OLEDDisplay::setPixel(int16_t x, int16_t y) { + if (x >= 0 && x < this->width() && y >= 0 && y < this->height()) { + switch (color) { + case WHITE: buffer[x + (y / 8) * this->width()] |= (1 << (y & 7)); break; + case BLACK: buffer[x + (y / 8) * this->width()] &= ~(1 << (y & 7)); break; + case INVERSE: buffer[x + (y / 8) * this->width()] ^= (1 << (y & 7)); break; + } + } +} + +// Bresenham's algorithm - thx wikipedia and Adafruit_GFX +void OLEDDisplay::drawLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1) { + int16_t steep = abs(y1 - y0) > abs(x1 - x0); + if (steep) { + _swap_int16_t(x0, y0); + _swap_int16_t(x1, y1); + } + + if (x0 > x1) { + _swap_int16_t(x0, x1); + _swap_int16_t(y0, y1); + } + + int16_t dx, dy; + dx = x1 - x0; + dy = abs(y1 - y0); + + int16_t err = dx / 2; + int16_t ystep; + + if (y0 < y1) { + ystep = 1; + } else { + ystep = -1; + } + + for (; x0<=x1; x0++) { + if (steep) { + setPixel(y0, x0); + } else { + setPixel(x0, y0); + } + err -= dy; + if (err < 0) { + y0 += ystep; + err += dx; + } + } +} + +void OLEDDisplay::drawRect(int16_t x, int16_t y, int16_t width, int16_t height) { + drawHorizontalLine(x, y, width); + drawVerticalLine(x, y, height); + drawVerticalLine(x + width - 1, y, height); + drawHorizontalLine(x, y + height - 1, width); +} + +void OLEDDisplay::fillRect(int16_t xMove, int16_t yMove, int16_t width, int16_t height) { + for (int16_t x = xMove; x < xMove + width; x++) { + drawVerticalLine(x, yMove, height); + } +} + +void OLEDDisplay::drawCircle(int16_t x0, int16_t y0, int16_t radius) { + int16_t x = 0, y = radius; + int16_t dp = 1 - radius; + do { + if (dp < 0) + dp = dp + 2 * (++x) + 3; + else + dp = dp + 2 * (++x) - 2 * (--y) + 5; + + setPixel(x0 + x, y0 + y); //For the 8 octants + setPixel(x0 - x, y0 + y); + setPixel(x0 + x, y0 - y); + setPixel(x0 - x, y0 - y); + setPixel(x0 + y, y0 + x); + setPixel(x0 - y, y0 + x); + setPixel(x0 + y, y0 - x); + setPixel(x0 - y, y0 - x); + + } while (x < y); + + setPixel(x0 + radius, y0); + setPixel(x0, y0 + radius); + setPixel(x0 - radius, y0); + setPixel(x0, y0 - radius); +} + +void OLEDDisplay::drawCircleQuads(int16_t x0, int16_t y0, int16_t radius, uint8_t quads) { + int16_t x = 0, y = radius; + int16_t dp = 1 - radius; + while (x < y) { + if (dp < 0) + dp = dp + 2 * (++x) + 3; + else + dp = dp + 2 * (++x) - 2 * (--y) + 5; + if (quads & 0x1) { + setPixel(x0 + x, y0 - y); + setPixel(x0 + y, y0 - x); + } + if (quads & 0x2) { + setPixel(x0 - y, y0 - x); + setPixel(x0 - x, y0 - y); + } + if (quads & 0x4) { + setPixel(x0 - y, y0 + x); + setPixel(x0 - x, y0 + y); + } + if (quads & 0x8) { + setPixel(x0 + x, y0 + y); + setPixel(x0 + y, y0 + x); + } + } + if (quads & 0x1 && quads & 0x8) { + setPixel(x0 + radius, y0); + } + if (quads & 0x4 && quads & 0x8) { + setPixel(x0, y0 + radius); + } + if (quads & 0x2 && quads & 0x4) { + setPixel(x0 - radius, y0); + } + if (quads & 0x1 && quads & 0x2) { + setPixel(x0, y0 - radius); + } +} + + +void OLEDDisplay::fillCircle(int16_t x0, int16_t y0, int16_t radius) { + int16_t x = 0, y = radius; + int16_t dp = 1 - radius; + do { + if (dp < 0) + dp = dp + 2 * (++x) + 3; + else + dp = dp + 2 * (++x) - 2 * (--y) + 5; + + drawHorizontalLine(x0 - x, y0 - y, 2*x); + drawHorizontalLine(x0 - x, y0 + y, 2*x); + drawHorizontalLine(x0 - y, y0 - x, 2*y); + drawHorizontalLine(x0 - y, y0 + x, 2*y); + + + } while (x < y); + drawHorizontalLine(x0 - radius, y0, 2 * radius); + +} + +void OLEDDisplay::drawHorizontalLine(int16_t x, int16_t y, int16_t length) { + if (y < 0 || y >= this->height()) { return; } + + if (x < 0) { + length += x; + x = 0; + } + + if ( (x + length) > this->width()) { + length = (this->width() - x); + } + + if (length <= 0) { return; } + + uint8_t * bufferPtr = buffer; + bufferPtr += (y >> 3) * this->width(); + bufferPtr += x; + + uint8_t drawBit = 1 << (y & 7); + + switch (color) { + case WHITE: while (length--) { + *bufferPtr++ |= drawBit; + }; break; + case BLACK: drawBit = ~drawBit; while (length--) { + *bufferPtr++ &= drawBit; + }; break; + case INVERSE: while (length--) { + *bufferPtr++ ^= drawBit; + }; break; + } +} + +void OLEDDisplay::drawVerticalLine(int16_t x, int16_t y, int16_t length) { + if (x < 0 || x >= this->width()) return; + + if (y < 0) { + length += y; + y = 0; + } + + if ( (y + length) > this->height()) { + length = (this->height() - y); + } + + if (length <= 0) return; + + + uint8_t yOffset = y & 7; + uint8_t drawBit; + uint8_t *bufferPtr = buffer; + + bufferPtr += (y >> 3) * this->width(); + bufferPtr += x; + + if (yOffset) { + yOffset = 8 - yOffset; + drawBit = ~(0xFF >> (yOffset)); + + if (length < yOffset) { + drawBit &= (0xFF >> (yOffset - length)); + } + + switch (color) { + case WHITE: *bufferPtr |= drawBit; break; + case BLACK: *bufferPtr &= ~drawBit; break; + case INVERSE: *bufferPtr ^= drawBit; break; + } + + if (length < yOffset) return; + + length -= yOffset; + bufferPtr += this->width(); + } + + if (length >= 8) { + switch (color) { + case WHITE: + case BLACK: + drawBit = (color == WHITE) ? 0xFF : 0x00; + do { + *bufferPtr = drawBit; + bufferPtr += this->width(); + length -= 8; + } while (length >= 8); + break; + case INVERSE: + do { + *bufferPtr = ~(*bufferPtr); + bufferPtr += this->width(); + length -= 8; + } while (length >= 8); + break; + } + } + + if (length > 0) { + drawBit = (1 << (length & 7)) - 1; + switch (color) { + case WHITE: *bufferPtr |= drawBit; break; + case BLACK: *bufferPtr &= ~drawBit; break; + case INVERSE: *bufferPtr ^= drawBit; break; + } + } +} + +void OLEDDisplay::drawProgressBar(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint8_t progress) { + uint16_t radius = height / 2; + uint16_t xRadius = x + radius; + uint16_t yRadius = y + radius; + uint16_t doubleRadius = 2 * radius; + uint16_t innerRadius = radius - 2; + + setColor(WHITE); + drawCircleQuads(xRadius, yRadius, radius, 0b00000110); + drawHorizontalLine(xRadius, y, width - doubleRadius + 1); + drawHorizontalLine(xRadius, y + height, width - doubleRadius + 1); + drawCircleQuads(x + width - radius, yRadius, radius, 0b00001001); + + uint16_t maxProgressWidth = (width - doubleRadius + 1) * progress / 100; + + fillCircle(xRadius, yRadius, innerRadius); + fillRect(xRadius + 1, y + 2, maxProgressWidth, height - 3); + fillCircle(xRadius + maxProgressWidth, yRadius, innerRadius); +} + +void OLEDDisplay::drawFastImage(int16_t xMove, int16_t yMove, int16_t width, int16_t height, const uint8_t *image) { + drawInternal(xMove, yMove, width, height, image, 0, 0); +} + +void OLEDDisplay::drawXbm(int16_t xMove, int16_t yMove, int16_t width, int16_t height, const uint8_t *xbm) { + int16_t widthInXbm = (width + 7) / 8; + uint8_t data = 0; + + for(int16_t y = 0; y < height; y++) { + for(int16_t x = 0; x < width; x++ ) { + if (x & 7) { + data >>= 1; // Move a bit + } else { // Read new data every 8 bit + data = pgm_read_byte(xbm + (x / 8) + y * widthInXbm); + } + // if there is a bit draw it + if (data & 0x01) { + setPixel(xMove + x, yMove + y); + } + } + } +} + +void OLEDDisplay::drawStringInternal(int16_t xMove, int16_t yMove, char* text, uint16_t textLength, uint16_t textWidth) { + uint8_t textHeight = pgm_read_byte(fontData + HEIGHT_POS); + uint8_t firstChar = pgm_read_byte(fontData + FIRST_CHAR_POS); + uint16_t sizeOfJumpTable = pgm_read_byte(fontData + CHAR_NUM_POS) * JUMPTABLE_BYTES; + + uint8_t cursorX = 0; + uint8_t cursorY = 0; + + switch (textAlignment) { + case TEXT_ALIGN_CENTER_BOTH: + yMove -= textHeight >> 1; + // Fallthrough + case TEXT_ALIGN_CENTER: + xMove -= textWidth >> 1; // divide by 2 + break; + case TEXT_ALIGN_RIGHT: + xMove -= textWidth; + break; + case TEXT_ALIGN_LEFT: + break; + } + + // Don't draw anything if it is not on the screen. + if (xMove + textWidth < 0 || xMove > this->width() ) {return;} + if (yMove + textHeight < 0 || yMove > this->width() ) {return;} + + for (uint16_t j = 0; j < textLength; j++) { + int16_t xPos = xMove + cursorX; + int16_t yPos = yMove + cursorY; + + byte code = text[j]; + if (code >= firstChar) { + byte charCode = code - firstChar; + + // 4 Bytes per char code + byte msbJumpToChar = pgm_read_byte( fontData + JUMPTABLE_START + charCode * JUMPTABLE_BYTES ); // MSB \ JumpAddress + byte lsbJumpToChar = pgm_read_byte( fontData + JUMPTABLE_START + charCode * JUMPTABLE_BYTES + JUMPTABLE_LSB); // LSB / + byte charByteSize = pgm_read_byte( fontData + JUMPTABLE_START + charCode * JUMPTABLE_BYTES + JUMPTABLE_SIZE); // Size + byte currentCharWidth = pgm_read_byte( fontData + JUMPTABLE_START + charCode * JUMPTABLE_BYTES + JUMPTABLE_WIDTH); // Width + + // Test if the char is drawable + if (!(msbJumpToChar == 255 && lsbJumpToChar == 255)) { + // Get the position of the char data + uint16_t charDataPosition = JUMPTABLE_START + sizeOfJumpTable + ((msbJumpToChar << 8) + lsbJumpToChar); + drawInternal(xPos, yPos, currentCharWidth, textHeight, fontData, charDataPosition, charByteSize); + } + + cursorX += currentCharWidth; + } + } +} + + +void OLEDDisplay::drawString(int16_t xMove, int16_t yMove, String strUser) { + uint16_t lineHeight = pgm_read_byte(fontData + HEIGHT_POS); + + // char* text must be freed! + char* text = utf8ascii(strUser); + + uint16_t yOffset = 0; + // If the string should be centered vertically too + // we need to now how heigh the string is. + if (textAlignment == TEXT_ALIGN_CENTER_BOTH) { + uint16_t lb = 0; + // Find number of linebreaks in text + for (uint16_t i=0;text[i] != 0; i++) { + lb += (text[i] == 10); + } + // Calculate center + yOffset = (lb * lineHeight) / 2; + } + + uint16_t line = 0; + char* textPart = strtok(text,"\n"); + while (textPart != NULL) { + uint16_t length = strlen(textPart); + drawStringInternal(xMove, yMove - yOffset + (line++) * lineHeight, textPart, length, getStringWidth(textPart, length)); + textPart = strtok(NULL, "\n"); + } + free(text); +} +//void OLEDDisplay::drawdata(int16_t xMove, int16_t yMove, int16_t Num) { +// uint16_t lineHeight = pgm_read_byte(fontData + HEIGHT_POS); +// unsigned char c = 0,i = 0,j = 0,ch[3]; +// String strUser; +// +// ch[0] = Num/100 + 48;//加上十进制的48是为了给Num加上ASCLL码的高4位0011 0000； +// ch[1] = Num%100/10 + 48; +// ch[2] = Num%10 + 48; +// +// if(ch[0] == 48) //用于把依次每位为"0"时，变成空格（即不显示） +// { +// ch[0] = 32; +// if(ch[1] == 48) +// { +// ch[1] = 32; +// if(ch[2] == 48) +// { +// ch[2] = 32; +// } +// else{ch[2] = Num%10 + 48;} +// } +// else{ch[1] = Num%100/10 + 48;} +// } +// else {ch[0] = Num/100 + 48;} +// +// // char* text must be freed! +// char* text = utf8ascii(strUser); +// +// uint16_t yOffset = 0; +// // If the string should be centered vertically too +// // we need to now how heigh the string is. +// if (textAlignment == TEXT_ALIGN_CENTER_BOTH) { +// uint16_t lb = 0; +// // Find number of linebreaks in text +// for (uint16_t i=0;text[i] != 0; i++) { +// lb += (text[i] == 10); +// } +// // Calculate center +// yOffset = (lb * lineHeight) / 2; +// } +// +// uint16_t line = 0; +// char* textPart = strtok(text,"\n"); +// while (textPart != NULL) { +// uint16_t length = strlen(textPart); +// drawStringInternal(xMove, yMove - yOffset + (line++) * lineHeight, textPart, length, getStringWidth(textPart, length)); +// textPart = strtok(NULL, "\n"); +// } +// free(text); +//} + +void OLEDDisplay::drawStringMaxWidth(int16_t xMove, int16_t yMove, uint16_t maxLineWidth, String strUser) { + uint16_t firstChar = pgm_read_byte(fontData + FIRST_CHAR_POS); + uint16_t lineHeight = pgm_read_byte(fontData + HEIGHT_POS); + + char* text = utf8ascii(strUser); + + uint16_t length = strlen(text); + uint16_t lastDrawnPos = 0; + uint16_t lineNumber = 0; + uint16_t strWidth = 0; + + uint16_t preferredBreakpoint = 0; + uint16_t widthAtBreakpoint = 0; + + for (uint16_t i = 0; i < length; i++) { + strWidth += pgm_read_byte(fontData + JUMPTABLE_START + (text[i] - firstChar) * JUMPTABLE_BYTES + JUMPTABLE_WIDTH); + + // Always try to break on a space or dash + if (text[i] == ' ' || text[i]== '-') { + preferredBreakpoint = i; + widthAtBreakpoint = strWidth; + } + + if (strWidth >= maxLineWidth) { + if (preferredBreakpoint == 0) { + preferredBreakpoint = i; + widthAtBreakpoint = strWidth; + } + drawStringInternal(xMove, yMove + (lineNumber++) * lineHeight , &text[lastDrawnPos], preferredBreakpoint - lastDrawnPos, widthAtBreakpoint); + lastDrawnPos = preferredBreakpoint + 1; + // It is possible that we did not draw all letters to i so we need + // to account for the width of the chars from `i - preferredBreakpoint` + // by calculating the width we did not draw yet. + strWidth = strWidth - widthAtBreakpoint; + preferredBreakpoint = 0; + } + } + + // Draw last part if needed + if (lastDrawnPos < length) { + drawStringInternal(xMove, yMove + lineNumber * lineHeight , &text[lastDrawnPos], length - lastDrawnPos, getStringWidth(&text[lastDrawnPos], length - lastDrawnPos)); + } + + free(text); +} + +uint16_t OLEDDisplay::getStringWidth(const char* text, uint16_t length) { + uint16_t firstChar = pgm_read_byte(fontData + FIRST_CHAR_POS); + + uint16_t stringWidth = 0; + uint16_t maxWidth = 0; + + while (length--) { + stringWidth += pgm_read_byte(fontData + JUMPTABLE_START + (text[length] - firstChar) * JUMPTABLE_BYTES + JUMPTABLE_WIDTH); + if (text[length] == 10) { + maxWidth = max(maxWidth, stringWidth); + stringWidth = 0; + } + } + + return max(maxWidth, stringWidth); +} + +uint16_t OLEDDisplay::getStringWidth(String strUser) { + char* text = utf8ascii(strUser); + uint16_t length = strlen(text); + uint16_t width = getStringWidth(text, length); + free(text); + return width; +} + +void OLEDDisplay::setTextAlignment(OLEDDISPLAY_TEXT_ALIGNMENT textAlignment) { + this->textAlignment = textAlignment; +} + +void OLEDDisplay::setFont(const uint8_t *fontData) { + this->fontData = fontData; +} + +void OLEDDisplay::displayOn(void) { + sendCommand(DISPLAYON); +} + +void OLEDDisplay::displayOff(void) { + sendCommand(DISPLAYOFF); +} + +void OLEDDisplay::invertDisplay(void) { + sendCommand(INVERTDISPLAY); +} + +void OLEDDisplay::normalDisplay(void) { + sendCommand(NORMALDISPLAY); +} + +void OLEDDisplay::setContrast(uint8_t contrast, uint8_t precharge, uint8_t comdetect) { + sendCommand(SETPRECHARGE); //0xD9 + sendCommand(precharge); //0xF1 default, to lower the contrast, put 1-1F + sendCommand(SETCONTRAST); + sendCommand(contrast); // 0-255 + sendCommand(SETVCOMDETECT); //0xDB, (additionally needed to lower the contrast) + sendCommand(comdetect); //0x40 default, to lower the contrast, put 0 + sendCommand(DISPLAYALLON_RESUME); + sendCommand(NORMALDISPLAY); + sendCommand(DISPLAYON); +} + +void OLEDDisplay::setBrightness(uint8_t brightness) { + uint8_t contrast = brightness; + if (brightness < 128) { + // Magic values to get a smooth/ step-free transition + contrast = brightness * 1.171; + } else { + contrast = brightness * 1.171 - 43; + } + + uint8_t precharge = 241; + if (brightness == 0) { + precharge = 0; + } + uint8_t comdetect = brightness / 8; + + setContrast(contrast, precharge, comdetect); +} + +void OLEDDisplay::resetOrientation() { + sendCommand(SEGREMAP); + sendCommand(COMSCANINC); //Reset screen rotation or mirroring +} + +void OLEDDisplay::flipScreenVertically() { + sendCommand(SEGREMAP | 0x01); + sendCommand(COMSCANDEC); //Rotate screen 180 Deg +} + +void OLEDDisplay::mirrorScreen() { + sendCommand(SEGREMAP); + sendCommand(COMSCANDEC); //Mirror screen +} + +void OLEDDisplay::clear(void) { + memset(buffer, 0, displayBufferSize); +} + +void OLEDDisplay::drawLogBuffer(uint16_t xMove, uint16_t yMove) { + uint16_t lineHeight = pgm_read_byte(fontData + HEIGHT_POS); + // Always align left + setTextAlignment(TEXT_ALIGN_LEFT); + + // State values + uint16_t length = 0; + uint16_t line = 0; + uint16_t lastPos = 0; + + for (uint16_t i=0;ilogBufferFilled;i++){ + // Everytime we have a \n print + if (this->logBuffer[i] == 10) { + length++; + // Draw string on line `line` from lastPos to length + // Passing 0 as the lenght because we are in TEXT_ALIGN_LEFT + drawStringInternal(xMove, yMove + (line++) * lineHeight, &this->logBuffer[lastPos], length, 0); + // Remember last pos + lastPos = i; + // Reset length + length = 0; + } else { + // Count chars until next linebreak + length++; + } + } + // Draw the remaining string + if (length > 0) { + drawStringInternal(xMove, yMove + line * lineHeight, &this->logBuffer[lastPos], length, 0); + } +} + +uint16_t OLEDDisplay::getWidth(void) { + return displayWidth; +} + +uint16_t OLEDDisplay::getHeight(void) { + return displayHeight; +} + +bool OLEDDisplay::setLogBuffer(uint16_t lines, uint16_t chars){ + if (logBuffer != NULL) free(logBuffer); + uint16_t size = lines * chars; + if (size > 0) { + this->logBufferLine = 0; // Lines printed + this->logBufferFilled = 0; // Nothing stored yet + this->logBufferMaxLines = lines; // Lines max printable + this->logBufferSize = size; // Total number of characters the buffer can hold + this->logBuffer = (char *) malloc(size * sizeof(uint8_t)); + if(!this->logBuffer) { + DEBUG_OLEDDISPLAY("[OLEDDISPLAY][setLogBuffer] Not enough memory to create log buffer\n"); + return false; + } + } + return true; +} + +size_t OLEDDisplay::write(uint8_t c) { + if (this->logBufferSize > 0) { + // Don't waste space on \r\n line endings, dropping \r + if (c == 13) return 1; + + // convert UTF-8 character to font table index + c = (this->fontTableLookupFunction)(c); + // drop unknown character + if (c == 0) return 1; + + bool maxLineNotReached = this->logBufferLine < this->logBufferMaxLines; + bool bufferNotFull = this->logBufferFilled < this->logBufferSize; + + // Can we write to the buffer? + if (bufferNotFull && maxLineNotReached) { + this->logBuffer[logBufferFilled] = c; + this->logBufferFilled++; + // Keep track of lines written + if (c == 10) this->logBufferLine++; + } else { + // Max line number is reached + if (!maxLineNotReached) this->logBufferLine--; + + // Find the end of the first line + uint16_t firstLineEnd = 0; + for (uint16_t i=0;ilogBufferFilled;i++) { + if (this->logBuffer[i] == 10){ + // Include last char too + firstLineEnd = i + 1; + break; + } + } + // If there was a line ending + if (firstLineEnd > 0) { + // Calculate the new logBufferFilled value + this->logBufferFilled = logBufferFilled - firstLineEnd; + // Now we move the lines infront of the buffer + memcpy(this->logBuffer, &this->logBuffer[firstLineEnd], logBufferFilled); + } else { + // Let's reuse the buffer if it was full + if (!bufferNotFull) { + this->logBufferFilled = 0; + }// else { + // Nothing to do here + //} + } + write(c); + } + } + // We are always writing all uint8_t to the buffer + return 1; +} + +size_t OLEDDisplay::write(const char* str) { + if (str == NULL) return 0; + size_t length = strlen(str); + for (size_t i = 0; i < length; i++) { + write(str[i]); + } + return length; +} + +// Private functions +void OLEDDisplay::setGeometry(OLEDDISPLAY_GEOMETRY g) { + this->geometry = g; + if (g == GEOMETRY_128_64) { + this->displayWidth = 128; + this->displayHeight = 64; + } else if (g == GEOMETRY_128_32) { + this->displayWidth = 128; + this->displayHeight = 32; + } else if (g == GEOMETRY_64_32) { + this->displayWidth = 64; + this->displayHeight = 32; + } + this->displayBufferSize = displayWidth*displayHeight/8; +} + +void OLEDDisplay::sendInitCommands(void) { + sendCommand(DISPLAYOFF); + sendCommand(SETDISPLAYCLOCKDIV); + sendCommand(0xF0); // Increase speed of the display max ~96Hz + sendCommand(SETMULTIPLEX); + sendCommand(this->height() - 1); + sendCommand(SETDISPLAYOFFSET); + sendCommand(0x00); + sendCommand(SETSTARTLINE); + sendCommand(CHARGEPUMP); + sendCommand(0x14); + sendCommand(MEMORYMODE); + sendCommand(0x00); + sendCommand(SEGREMAP); + sendCommand(COMSCANINC); + sendCommand(SETCOMPINS); + + if ((geometry == GEOMETRY_128_64) || (geometry == GEOMETRY_64_32)) { + sendCommand(0x12); + } else if (geometry == GEOMETRY_128_32) { + sendCommand(0x02); + } + + sendCommand(SETCONTRAST); + + if ((geometry == GEOMETRY_128_64) || (geometry == GEOMETRY_64_32)) { + sendCommand(0xCF); + } else if (geometry == GEOMETRY_128_32) { + sendCommand(0x8F); + } + + sendCommand(SETPRECHARGE); + sendCommand(0xF1); + sendCommand(SETVCOMDETECT); //0xDB, (additionally needed to lower the contrast) + sendCommand(0x40); //0x40 default, to lower the contrast, put 0 + sendCommand(DISPLAYALLON_RESUME); + sendCommand(NORMALDISPLAY); + sendCommand(0x2e); // stop scroll + sendCommand(DISPLAYON); +} + +void inline OLEDDisplay::drawInternal(int16_t xMove, int16_t yMove, int16_t width, int16_t height, const uint8_t *data, uint16_t offset, uint16_t bytesInData) { + if (width < 0 || height < 0) return; + if (yMove + height < 0 || yMove > this->height()) return; + if (xMove + width < 0 || xMove > this->width()) return; + + uint8_t rasterHeight = 1 + ((height - 1) >> 3); // fast ceil(height / 8.0) + int8_t yOffset = yMove & 7; + + bytesInData = bytesInData == 0 ? width * rasterHeight : bytesInData; + + int16_t initYMove = yMove; + int8_t initYOffset = yOffset; + + + for (uint16_t i = 0; i < bytesInData; i++) { + + // Reset if next horizontal drawing phase is started. + if ( i % rasterHeight == 0) { + yMove = initYMove; + yOffset = initYOffset; + } + + byte currentByte = pgm_read_byte(data + offset + i); + + int16_t xPos = xMove + (i / rasterHeight); + int16_t yPos = ((yMove >> 3) + (i % rasterHeight)) * this->width(); + +// int16_t yScreenPos = yMove + yOffset; + int16_t dataPos = xPos + yPos; + + if (dataPos >= 0 && dataPos < displayBufferSize && + xPos >= 0 && xPos < this->width() ) { + + if (yOffset >= 0) { + switch (this->color) { + case WHITE: buffer[dataPos] |= currentByte << yOffset; break; + case BLACK: buffer[dataPos] &= ~(currentByte << yOffset); break; + case INVERSE: buffer[dataPos] ^= currentByte << yOffset; break; + } + + if (dataPos < (displayBufferSize - this->width())) { + switch (this->color) { + case WHITE: buffer[dataPos + this->width()] |= currentByte >> (8 - yOffset); break; + case BLACK: buffer[dataPos + this->width()] &= ~(currentByte >> (8 - yOffset)); break; + case INVERSE: buffer[dataPos + this->width()] ^= currentByte >> (8 - yOffset); break; + } + } + } else { + // Make new offset position + yOffset = -yOffset; + + switch (this->color) { + case WHITE: buffer[dataPos] |= currentByte >> yOffset; break; + case BLACK: buffer[dataPos] &= ~(currentByte >> yOffset); break; + case INVERSE: buffer[dataPos] ^= currentByte >> yOffset; break; + } + + // Prepare for next iteration by moving one block up + yMove -= 8; + + // and setting the new yOffset + yOffset = 8 - yOffset; + } + +// yield(); + } + } +} + +// You need to free the char! +char* OLEDDisplay::utf8ascii(String str) { + uint16_t k = 0; + uint16_t length = str.length() + 1; + + // Copy the string into a char array + char* s = (char*) malloc(length * sizeof(char)); + if(!s) { + DEBUG_OLEDDISPLAY("[OLEDDISPLAY][utf8ascii] Can't allocate another char array. Drop support for UTF-8.\n"); + return (char*) str.c_str(); + } + str.toCharArray(s, length); + + length--; + + for (uint16_t i=0; i < length; i++) { + char c = (this->fontTableLookupFunction)(s[i]); + if (c!=0) { + s[k++]=c; + } + } + + s[k]=0; + + // This will leak 's' be sure to free it in the calling function. + return s; +} + +void OLEDDisplay::setFontTableLookupFunction(FontTableLookupFunction function) { + this->fontTableLookupFunction = function; +} + + diff --git a/libraries/SSD1306_I2C/src/OLEDDisplay.h b/libraries/SSD1306_I2C/src/OLEDDisplay.h new file mode 100644 index 00000000..993e56be --- /dev/null +++ b/libraries/SSD1306_I2C/src/OLEDDisplay.h @@ -0,0 +1,335 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + +#ifndef OLEDDISPLAY_h +#define OLEDDISPLAY_h + +#include +#include "OLEDDisplayFonts.h" + +//#define DEBUG_OLEDDISPLAY(...) Serial.printf( __VA_ARGS__ ) + +#ifndef DEBUG_OLEDDISPLAY +#define DEBUG_OLEDDISPLAY(...) +#endif + +// Use DOUBLE BUFFERING by default +#ifndef OLEDDISPLAY_REDUCE_MEMORY +#define OLEDDISPLAY_DOUBLE_BUFFER +#endif + +// Header Values +#define JUMPTABLE_BYTES 4 + +#define JUMPTABLE_LSB 1 +#define JUMPTABLE_SIZE 2 +#define JUMPTABLE_WIDTH 3 +#define JUMPTABLE_START 4 + +#define WIDTH_POS 0 +#define HEIGHT_POS 1 +#define FIRST_CHAR_POS 2 +#define CHAR_NUM_POS 3 + + +// Display commands +#define CHARGEPUMP 0x8D +#define COLUMNADDR 0x21 +#define COMSCANDEC 0xC8 +#define COMSCANINC 0xC0 +#define DISPLAYALLON 0xA5 +#define DISPLAYALLON_RESUME 0xA4 +#define DISPLAYOFF 0xAE +#define DISPLAYON 0xAF +#define EXTERNALVCC 0x1 +#define INVERTDISPLAY 0xA7 +#define MEMORYMODE 0x20 +#define NORMALDISPLAY 0xA6 +#define PAGEADDR 0x22 +#define SEGREMAP 0xA0 +#define SETCOMPINS 0xDA +#define SETCONTRAST 0x81 +#define SETDISPLAYCLOCKDIV 0xD5 +#define SETDISPLAYOFFSET 0xD3 +#define SETHIGHCOLUMN 0x10 +#define SETLOWCOLUMN 0x00 +#define SETMULTIPLEX 0xA8 +#define SETPRECHARGE 0xD9 +#define SETSEGMENTREMAP 0xA1 +#define SETSTARTLINE 0x40 +#define SETVCOMDETECT 0xDB +#define SWITCHCAPVCC 0x2 + +#ifndef _swap_int16_t +#define _swap_int16_t(a, b) { int16_t t = a; a = b; b = t; } +#endif + +enum OLEDDISPLAY_COLOR { + BLACK = 0, + WHITE = 1, + INVERSE = 2 +}; + +enum OLEDDISPLAY_TEXT_ALIGNMENT { + TEXT_ALIGN_LEFT = 0, + TEXT_ALIGN_RIGHT = 1, + TEXT_ALIGN_CENTER = 2, + TEXT_ALIGN_CENTER_BOTH = 3 +}; + + +enum OLEDDISPLAY_GEOMETRY { + GEOMETRY_128_64 = 0, + GEOMETRY_128_32 = 1, + GEOMETRY_64_32 = 2 //Wireless Stick +}; + +typedef byte (*FontTableLookupFunction)(const byte ch); + + +class OLEDDisplay : public Print { + + public: + virtual ~OLEDDisplay(); + + uint16_t width(void) const { return displayWidth; }; + uint16_t height(void) const { return displayHeight; }; + + // Initialize the display + bool init(); + + // Free the memory used by the display + void end(); + + void sleep(); + + void wakeup(); + + // Cycle through the initialization + void resetDisplay(); + + /* Drawing functions */ + // Sets the color of all pixel operations + void setColor(OLEDDISPLAY_COLOR color); + + // Returns the current color. + OLEDDISPLAY_COLOR getColor(); + + // Draw a pixel at given position + void setPixel(int16_t x, int16_t y); + + // Draw a line from position 0 to position 1 + void drawLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1); + + // Draw the border of a rectangle at the given location + void drawRect(int16_t x, int16_t y, int16_t width, int16_t height); + + // Fill the rectangle + void fillRect(int16_t x, int16_t y, int16_t width, int16_t height); + + // Draw the border of a circle + void drawCircle(int16_t x, int16_t y, int16_t radius); + + // Draw all Quadrants specified in the quads bit mask + void drawCircleQuads(int16_t x0, int16_t y0, int16_t radius, uint8_t quads); + + // Fill circle + void fillCircle(int16_t x, int16_t y, int16_t radius); + + // Draw a line horizontally + void drawHorizontalLine(int16_t x, int16_t y, int16_t length); + + // Draw a line vertically + void drawVerticalLine(int16_t x, int16_t y, int16_t length); + + // Draws a rounded progress bar with the outer dimensions given by width and height. Progress is + // a unsigned byte value between 0 and 100 + void drawProgressBar(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint8_t progress); + + // Draw a bitmap in the internal image format + void drawFastImage(int16_t x, int16_t y, int16_t width, int16_t height, const uint8_t *image); + + // Draw a XBM + void drawXbm(int16_t x, int16_t y, int16_t width, int16_t height, const uint8_t *xbm); + + /* Text functions */ + + // Draws a string at the given location + void drawString(int16_t x, int16_t y, String text); + + // Draws a String with a maximum width at the given location. + // If the given String is wider than the specified width + // The text will be wrapped to the next line at a space or dash + void drawStringMaxWidth(int16_t x, int16_t y, uint16_t maxLineWidth, String text); + + // Returns the width of the const char* with the current + // font settings + uint16_t getStringWidth(const char* text, uint16_t length); + + // Convencience method for the const char version + uint16_t getStringWidth(String text); + + // Specifies relative to which anchor point + // the text is rendered. Available constants: + // TEXT_ALIGN_LEFT, TEXT_ALIGN_CENTER, TEXT_ALIGN_RIGHT, TEXT_ALIGN_CENTER_BOTH + void setTextAlignment(OLEDDISPLAY_TEXT_ALIGNMENT textAlignment); + + // Sets the current font. Available default fonts + // ArialMT_Plain_10, ArialMT_Plain_16, ArialMT_Plain_24 + void setFont(const uint8_t *fontData); + + // Set the function that will convert utf-8 to font table index + void setFontTableLookupFunction(FontTableLookupFunction function); + + /* Display functions */ + + // Turn the display on + void displayOn(void); + + // Turn the display offs + void displayOff(void); + + // Inverted display mode + void invertDisplay(void); + + // Normal display mode + void normalDisplay(void); + + // Set display contrast + // really low brightness & contrast: contrast = 10, precharge = 5, comdetect = 0 + // normal brightness & contrast: contrast = 100 + void setContrast(uint8_t contrast, uint8_t precharge = 241, uint8_t comdetect = 64); + + // Convenience method to access + void setBrightness(uint8_t); + + // Reset display rotation or mirroring + void resetOrientation(); + + // Turn the display upside down + void flipScreenVertically(); + + // Mirror the display (to be used in a mirror or as a projector) + void mirrorScreen(); + + // Write the buffer to the display memory + virtual void display(void) = 0; + + // Clear the local pixel buffer + void clear(void); + + // Log buffer implementation + + // This will define the lines and characters you can + // print to the screen. When you exeed the buffer size (lines * chars) + // the output may be truncated due to the size constraint. + bool setLogBuffer(uint16_t lines, uint16_t chars); + + // Draw the log buffer at position (x, y) + void drawLogBuffer(uint16_t x, uint16_t y); + + // Get screen geometry + uint16_t getWidth(void); + uint16_t getHeight(void); + + // Implement needed function to be compatible with Print class + size_t write(uint8_t c); + size_t write(const char* s); + + uint8_t *buffer = NULL; + + #ifdef OLEDDISPLAY_DOUBLE_BUFFER + uint8_t *buffer_back = NULL; + #endif + + protected: + + OLEDDISPLAY_GEOMETRY geometry = GEOMETRY_128_64; + + uint16_t displayWidth = 128; + uint16_t displayHeight = 64; + uint16_t displayBufferSize = 1024; + + // Set the correct height, width and buffer for the geometry + void setGeometry(OLEDDISPLAY_GEOMETRY g); + + OLEDDISPLAY_TEXT_ALIGNMENT textAlignment = TEXT_ALIGN_LEFT; + OLEDDISPLAY_COLOR color = WHITE; + + const uint8_t *fontData = ArialMT_Plain_10; + + // State values for logBuffer + uint16_t logBufferSize = 0; + uint16_t logBufferFilled = 0; + uint16_t logBufferLine = 0; + uint16_t logBufferMaxLines = 0; + char *logBuffer = NULL; + + // Send a command to the display (low level function) + virtual void sendCommand(uint8_t com) {(void)com;}; + + // Connect to the display + virtual bool connect() { return false; }; + + // Send all the init commands + void sendInitCommands(); + + // converts utf8 characters to extended ascii + char* utf8ascii(String s); + + void inline drawInternal(int16_t xMove, int16_t yMove, int16_t width, int16_t height, const uint8_t *data, uint16_t offset, uint16_t bytesInData) __attribute__((always_inline)); + + void drawStringInternal(int16_t xMove, int16_t yMove, char* text, uint16_t textLength, uint16_t textWidth); + + // UTF-8 to font table index converter + // Code form http://playground.arduino.cc/Main/Utf8ascii + FontTableLookupFunction fontTableLookupFunction = [](const byte ch) { + static uint8_t LASTCHAR; + + if (ch < 128) { // Standard ASCII-set 0..0x7F handling + LASTCHAR = 0; + return ch; + } + + uint8_t last = LASTCHAR; // get last char + LASTCHAR = ch; + + switch (last) { // conversion depnding on first UTF8-character + case 0xC2: return (uint8_t) ch; + case 0xC3: return (uint8_t) (ch | 0xC0); + case 0x82: if (ch == 0xAC) return (uint8_t) 0x80; // special case Euro-symbol + } + + return (uint8_t) 0; // otherwise: return zero, if character has to be ignored + }; +}; + +#endif + diff --git a/libraries/SSD1306_I2C/src/OLEDDisplayFonts.h b/libraries/SSD1306_I2C/src/OLEDDisplayFonts.h new file mode 100644 index 00000000..3544edb8 --- /dev/null +++ b/libraries/SSD1306_I2C/src/OLEDDisplayFonts.h @@ -0,0 +1,1274 @@ +#ifndef OLEDDISPLAYFONTS_h +#define OLEDDISPLAYFONTS_h + +const uint8_t ArialMT_Plain_10[] PROGMEM = { + 0x0A, // Width: 10 + 0x0D, // Height: 13 + 0x20, // First Char: 32 + 0xE0, // Numbers of Chars: 224 + + // Jump Table: + 0xFF, 0xFF, 0x00, 0x03, // 32:65535 + 0x00, 0x00, 0x04, 0x03, // 33:0 + 0x00, 0x04, 0x05, 0x04, // 34:4 + 0x00, 0x09, 0x09, 0x06, // 35:9 + 0x00, 0x12, 0x0A, 0x06, // 36:18 + 0x00, 0x1C, 0x10, 0x09, // 37:28 + 0x00, 0x2C, 0x0E, 0x07, // 38:44 + 0x00, 0x3A, 0x01, 0x02, // 39:58 + 0x00, 0x3B, 0x06, 0x03, // 40:59 + 0x00, 0x41, 0x06, 0x03, // 41:65 + 0x00, 0x47, 0x05, 0x04, // 42:71 + 0x00, 0x4C, 0x09, 0x06, // 43:76 + 0x00, 0x55, 0x04, 0x03, // 44:85 + 0x00, 0x59, 0x03, 0x03, // 45:89 + 0x00, 0x5C, 0x04, 0x03, // 46:92 + 0x00, 0x60, 0x05, 0x03, // 47:96 + 0x00, 0x65, 0x0A, 0x06, // 48:101 + 0x00, 0x6F, 0x08, 0x06, // 49:111 + 0x00, 0x77, 0x0A, 0x06, // 50:119 + 0x00, 0x81, 0x0A, 0x06, // 51:129 + 0x00, 0x8B, 0x0B, 0x06, // 52:139 + 0x00, 0x96, 0x0A, 0x06, // 53:150 + 0x00, 0xA0, 0x0A, 0x06, // 54:160 + 0x00, 0xAA, 0x09, 0x06, // 55:170 + 0x00, 0xB3, 0x0A, 0x06, // 56:179 + 0x00, 0xBD, 0x0A, 0x06, // 57:189 + 0x00, 0xC7, 0x04, 0x03, // 58:199 + 0x00, 0xCB, 0x04, 0x03, // 59:203 + 0x00, 0xCF, 0x0A, 0x06, // 60:207 + 0x00, 0xD9, 0x09, 0x06, // 61:217 + 0x00, 0xE2, 0x09, 0x06, // 62:226 + 0x00, 0xEB, 0x0B, 0x06, // 63:235 + 0x00, 0xF6, 0x14, 0x0A, // 64:246 + 0x01, 0x0A, 0x0E, 0x07, // 65:266 + 0x01, 0x18, 0x0C, 0x07, // 66:280 + 0x01, 0x24, 0x0C, 0x07, // 67:292 + 0x01, 0x30, 0x0B, 0x07, // 68:304 + 0x01, 0x3B, 0x0C, 0x07, // 69:315 + 0x01, 0x47, 0x09, 0x06, // 70:327 + 0x01, 0x50, 0x0D, 0x08, // 71:336 + 0x01, 0x5D, 0x0C, 0x07, // 72:349 + 0x01, 0x69, 0x04, 0x03, // 73:361 + 0x01, 0x6D, 0x08, 0x05, // 74:365 + 0x01, 0x75, 0x0E, 0x07, // 75:373 + 0x01, 0x83, 0x0C, 0x06, // 76:387 + 0x01, 0x8F, 0x10, 0x08, // 77:399 + 0x01, 0x9F, 0x0C, 0x07, // 78:415 + 0x01, 0xAB, 0x0E, 0x08, // 79:427 + 0x01, 0xB9, 0x0B, 0x07, // 80:441 + 0x01, 0xC4, 0x0E, 0x08, // 81:452 + 0x01, 0xD2, 0x0C, 0x07, // 82:466 + 0x01, 0xDE, 0x0C, 0x07, // 83:478 + 0x01, 0xEA, 0x0B, 0x06, // 84:490 + 0x01, 0xF5, 0x0C, 0x07, // 85:501 + 0x02, 0x01, 0x0D, 0x07, // 86:513 + 0x02, 0x0E, 0x11, 0x09, // 87:526 + 0x02, 0x1F, 0x0E, 0x07, // 88:543 + 0x02, 0x2D, 0x0D, 0x07, // 89:557 + 0x02, 0x3A, 0x0C, 0x06, // 90:570 + 0x02, 0x46, 0x06, 0x03, // 91:582 + 0x02, 0x4C, 0x06, 0x03, // 92:588 + 0x02, 0x52, 0x04, 0x03, // 93:594 + 0x02, 0x56, 0x09, 0x05, // 94:598 + 0x02, 0x5F, 0x0C, 0x06, // 95:607 + 0x02, 0x6B, 0x03, 0x03, // 96:619 + 0x02, 0x6E, 0x0A, 0x06, // 97:622 + 0x02, 0x78, 0x0A, 0x06, // 98:632 + 0x02, 0x82, 0x0A, 0x05, // 99:642 + 0x02, 0x8C, 0x0A, 0x06, // 100:652 + 0x02, 0x96, 0x0A, 0x06, // 101:662 + 0x02, 0xA0, 0x05, 0x03, // 102:672 + 0x02, 0xA5, 0x0A, 0x06, // 103:677 + 0x02, 0xAF, 0x0A, 0x06, // 104:687 + 0x02, 0xB9, 0x04, 0x02, // 105:697 + 0x02, 0xBD, 0x04, 0x02, // 106:701 + 0x02, 0xC1, 0x08, 0x05, // 107:705 + 0x02, 0xC9, 0x04, 0x02, // 108:713 + 0x02, 0xCD, 0x10, 0x08, // 109:717 + 0x02, 0xDD, 0x0A, 0x06, // 110:733 + 0x02, 0xE7, 0x0A, 0x06, // 111:743 + 0x02, 0xF1, 0x0A, 0x06, // 112:753 + 0x02, 0xFB, 0x0A, 0x06, // 113:763 + 0x03, 0x05, 0x05, 0x03, // 114:773 + 0x03, 0x0A, 0x08, 0x05, // 115:778 + 0x03, 0x12, 0x06, 0x03, // 116:786 + 0x03, 0x18, 0x0A, 0x06, // 117:792 + 0x03, 0x22, 0x09, 0x05, // 118:802 + 0x03, 0x2B, 0x0E, 0x07, // 119:811 + 0x03, 0x39, 0x0A, 0x05, // 120:825 + 0x03, 0x43, 0x09, 0x05, // 121:835 + 0x03, 0x4C, 0x0A, 0x05, // 122:844 + 0x03, 0x56, 0x06, 0x03, // 123:854 + 0x03, 0x5C, 0x04, 0x03, // 124:860 + 0x03, 0x60, 0x05, 0x03, // 125:864 + 0x03, 0x65, 0x09, 0x06, // 126:869 + 0xFF, 0xFF, 0x00, 0x00, // 127:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 128:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 129:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 130:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 131:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 132:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 133:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 134:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 135:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 136:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 137:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 138:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 139:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 140:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 141:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 142:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 143:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 144:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 145:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 146:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 147:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 148:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 149:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 150:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 151:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 152:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 153:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 154:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 155:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 156:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 157:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 158:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 159:65535 + 0xFF, 0xFF, 0x00, 0x03, // 160:65535 + 0x03, 0x6E, 0x04, 0x03, // 161:878 + 0x03, 0x72, 0x0A, 0x06, // 162:882 + 0x03, 0x7C, 0x0C, 0x06, // 163:892 + 0x03, 0x88, 0x0A, 0x06, // 164:904 + 0x03, 0x92, 0x0A, 0x06, // 165:914 + 0x03, 0x9C, 0x04, 0x03, // 166:924 + 0x03, 0xA0, 0x0A, 0x06, // 167:928 + 0x03, 0xAA, 0x05, 0x03, // 168:938 + 0x03, 0xAF, 0x0D, 0x07, // 169:943 + 0x03, 0xBC, 0x07, 0x04, // 170:956 + 0x03, 0xC3, 0x0A, 0x06, // 171:963 + 0x03, 0xCD, 0x09, 0x06, // 172:973 + 0x03, 0xD6, 0x03, 0x03, // 173:982 + 0x03, 0xD9, 0x0D, 0x07, // 174:985 + 0x03, 0xE6, 0x0B, 0x06, // 175:998 + 0x03, 0xF1, 0x07, 0x04, // 176:1009 + 0x03, 0xF8, 0x0A, 0x05, // 177:1016 + 0x04, 0x02, 0x05, 0x03, // 178:1026 + 0x04, 0x07, 0x05, 0x03, // 179:1031 + 0x04, 0x0C, 0x05, 0x03, // 180:1036 + 0x04, 0x11, 0x0A, 0x06, // 181:1041 + 0x04, 0x1B, 0x09, 0x05, // 182:1051 + 0x04, 0x24, 0x03, 0x03, // 183:1060 + 0x04, 0x27, 0x06, 0x03, // 184:1063 + 0x04, 0x2D, 0x05, 0x03, // 185:1069 + 0x04, 0x32, 0x07, 0x04, // 186:1074 + 0x04, 0x39, 0x0A, 0x06, // 187:1081 + 0x04, 0x43, 0x10, 0x08, // 188:1091 + 0x04, 0x53, 0x10, 0x08, // 189:1107 + 0x04, 0x63, 0x10, 0x08, // 190:1123 + 0x04, 0x73, 0x0A, 0x06, // 191:1139 + 0x04, 0x7D, 0x0E, 0x07, // 192:1149 + 0x04, 0x8B, 0x0E, 0x07, // 193:1163 + 0x04, 0x99, 0x0E, 0x07, // 194:1177 + 0x04, 0xA7, 0x0E, 0x07, // 195:1191 + 0x04, 0xB5, 0x0E, 0x07, // 196:1205 + 0x04, 0xC3, 0x0E, 0x07, // 197:1219 + 0x04, 0xD1, 0x12, 0x0A, // 198:1233 + 0x04, 0xE3, 0x0C, 0x07, // 199:1251 + 0x04, 0xEF, 0x0C, 0x07, // 200:1263 + 0x04, 0xFB, 0x0C, 0x07, // 201:1275 + 0x05, 0x07, 0x0C, 0x07, // 202:1287 + 0x05, 0x13, 0x0C, 0x07, // 203:1299 + 0x05, 0x1F, 0x05, 0x03, // 204:1311 + 0x05, 0x24, 0x04, 0x03, // 205:1316 + 0x05, 0x28, 0x04, 0x03, // 206:1320 + 0x05, 0x2C, 0x05, 0x03, // 207:1324 + 0x05, 0x31, 0x0B, 0x07, // 208:1329 + 0x05, 0x3C, 0x0C, 0x07, // 209:1340 + 0x05, 0x48, 0x0E, 0x08, // 210:1352 + 0x05, 0x56, 0x0E, 0x08, // 211:1366 + 0x05, 0x64, 0x0E, 0x08, // 212:1380 + 0x05, 0x72, 0x0E, 0x08, // 213:1394 + 0x05, 0x80, 0x0E, 0x08, // 214:1408 + 0x05, 0x8E, 0x0A, 0x06, // 215:1422 + 0x05, 0x98, 0x0D, 0x08, // 216:1432 + 0x05, 0xA5, 0x0C, 0x07, // 217:1445 + 0x05, 0xB1, 0x0C, 0x07, // 218:1457 + 0x05, 0xBD, 0x0C, 0x07, // 219:1469 + 0x05, 0xC9, 0x0C, 0x07, // 220:1481 + 0x05, 0xD5, 0x0D, 0x07, // 221:1493 + 0x05, 0xE2, 0x0B, 0x07, // 222:1506 + 0x05, 0xED, 0x0C, 0x06, // 223:1517 + 0x05, 0xF9, 0x0A, 0x06, // 224:1529 + 0x06, 0x03, 0x0A, 0x06, // 225:1539 + 0x06, 0x0D, 0x0A, 0x06, // 226:1549 + 0x06, 0x17, 0x0A, 0x06, // 227:1559 + 0x06, 0x21, 0x0A, 0x06, // 228:1569 + 0x06, 0x2B, 0x0A, 0x06, // 229:1579 + 0x06, 0x35, 0x10, 0x09, // 230:1589 + 0x06, 0x45, 0x0A, 0x05, // 231:1605 + 0x06, 0x4F, 0x0A, 0x06, // 232:1615 + 0x06, 0x59, 0x0A, 0x06, // 233:1625 + 0x06, 0x63, 0x0A, 0x06, // 234:1635 + 0x06, 0x6D, 0x0A, 0x06, // 235:1645 + 0x06, 0x77, 0x05, 0x03, // 236:1655 + 0x06, 0x7C, 0x04, 0x03, // 237:1660 + 0x06, 0x80, 0x05, 0x03, // 238:1664 + 0x06, 0x85, 0x05, 0x03, // 239:1669 + 0x06, 0x8A, 0x0A, 0x06, // 240:1674 + 0x06, 0x94, 0x0A, 0x06, // 241:1684 + 0x06, 0x9E, 0x0A, 0x06, // 242:1694 + 0x06, 0xA8, 0x0A, 0x06, // 243:1704 + 0x06, 0xB2, 0x0A, 0x06, // 244:1714 + 0x06, 0xBC, 0x0A, 0x06, // 245:1724 + 0x06, 0xC6, 0x0A, 0x06, // 246:1734 + 0x06, 0xD0, 0x09, 0x05, // 247:1744 + 0x06, 0xD9, 0x0A, 0x06, // 248:1753 + 0x06, 0xE3, 0x0A, 0x06, // 249:1763 + 0x06, 0xED, 0x0A, 0x06, // 250:1773 + 0x06, 0xF7, 0x0A, 0x06, // 251:1783 + 0x07, 0x01, 0x0A, 0x06, // 252:1793 + 0x07, 0x0B, 0x09, 0x05, // 253:1803 + 0x07, 0x14, 0x0A, 0x06, // 254:1812 + 0x07, 0x1E, 0x09, 0x05, // 255:1822 + + // Font Data: + 0x00,0x00,0xF8,0x02, // 33 + 0x38,0x00,0x00,0x00,0x38, // 34 + 0xA0,0x03,0xE0,0x00,0xB8,0x03,0xE0,0x00,0xB8, // 35 + 0x30,0x01,0x28,0x02,0xF8,0x07,0x48,0x02,0x90,0x01, // 36 + 0x00,0x00,0x30,0x00,0x48,0x00,0x30,0x03,0xC0,0x00,0xB0,0x01,0x48,0x02,0x80,0x01, // 37 + 0x80,0x01,0x50,0x02,0x68,0x02,0xA8,0x02,0x18,0x01,0x80,0x03,0x80,0x02, // 38 + 0x38, // 39 + 0xE0,0x03,0x10,0x04,0x08,0x08, // 40 + 0x08,0x08,0x10,0x04,0xE0,0x03, // 41 + 0x28,0x00,0x18,0x00,0x28, // 42 + 0x40,0x00,0x40,0x00,0xF0,0x01,0x40,0x00,0x40, // 43 + 0x00,0x00,0x00,0x06, // 44 + 0x80,0x00,0x80, // 45 + 0x00,0x00,0x00,0x02, // 46 + 0x00,0x03,0xE0,0x00,0x18, // 47 + 0xF0,0x01,0x08,0x02,0x08,0x02,0x08,0x02,0xF0,0x01, // 48 + 0x00,0x00,0x20,0x00,0x10,0x00,0xF8,0x03, // 49 + 0x10,0x02,0x08,0x03,0x88,0x02,0x48,0x02,0x30,0x02, // 50 + 0x10,0x01,0x08,0x02,0x48,0x02,0x48,0x02,0xB0,0x01, // 51 + 0xC0,0x00,0xA0,0x00,0x90,0x00,0x88,0x00,0xF8,0x03,0x80, // 52 + 0x60,0x01,0x38,0x02,0x28,0x02,0x28,0x02,0xC8,0x01, // 53 + 0xF0,0x01,0x28,0x02,0x28,0x02,0x28,0x02,0xD0,0x01, // 54 + 0x08,0x00,0x08,0x03,0xC8,0x00,0x38,0x00,0x08, // 55 + 0xB0,0x01,0x48,0x02,0x48,0x02,0x48,0x02,0xB0,0x01, // 56 + 0x70,0x01,0x88,0x02,0x88,0x02,0x88,0x02,0xF0,0x01, // 57 + 0x00,0x00,0x20,0x02, // 58 + 0x00,0x00,0x20,0x06, // 59 + 0x00,0x00,0x40,0x00,0xA0,0x00,0xA0,0x00,0x10,0x01, // 60 + 0xA0,0x00,0xA0,0x00,0xA0,0x00,0xA0,0x00,0xA0, // 61 + 0x00,0x00,0x10,0x01,0xA0,0x00,0xA0,0x00,0x40, // 62 + 0x10,0x00,0x08,0x00,0x08,0x00,0xC8,0x02,0x48,0x00,0x30, // 63 + 0x00,0x00,0xC0,0x03,0x30,0x04,0xD0,0x09,0x28,0x0A,0x28,0x0A,0xC8,0x0B,0x68,0x0A,0x10,0x05,0xE0,0x04, // 64 + 0x00,0x02,0xC0,0x01,0xB0,0x00,0x88,0x00,0xB0,0x00,0xC0,0x01,0x00,0x02, // 65 + 0x00,0x00,0xF8,0x03,0x48,0x02,0x48,0x02,0x48,0x02,0xF0,0x01, // 66 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x08,0x02,0x08,0x02,0x10,0x01, // 67 + 0x00,0x00,0xF8,0x03,0x08,0x02,0x08,0x02,0x10,0x01,0xE0, // 68 + 0x00,0x00,0xF8,0x03,0x48,0x02,0x48,0x02,0x48,0x02,0x48,0x02, // 69 + 0x00,0x00,0xF8,0x03,0x48,0x00,0x48,0x00,0x08, // 70 + 0x00,0x00,0xE0,0x00,0x10,0x01,0x08,0x02,0x48,0x02,0x50,0x01,0xC0, // 71 + 0x00,0x00,0xF8,0x03,0x40,0x00,0x40,0x00,0x40,0x00,0xF8,0x03, // 72 + 0x00,0x00,0xF8,0x03, // 73 + 0x00,0x03,0x00,0x02,0x00,0x02,0xF8,0x01, // 74 + 0x00,0x00,0xF8,0x03,0x80,0x00,0x60,0x00,0x90,0x00,0x08,0x01,0x00,0x02, // 75 + 0x00,0x00,0xF8,0x03,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02, // 76 + 0x00,0x00,0xF8,0x03,0x30,0x00,0xC0,0x01,0x00,0x02,0xC0,0x01,0x30,0x00,0xF8,0x03, // 77 + 0x00,0x00,0xF8,0x03,0x30,0x00,0x40,0x00,0x80,0x01,0xF8,0x03, // 78 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x08,0x02,0x08,0x02,0x08,0x02,0xF0,0x01, // 79 + 0x00,0x00,0xF8,0x03,0x48,0x00,0x48,0x00,0x48,0x00,0x30, // 80 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x08,0x02,0x08,0x03,0x08,0x03,0xF0,0x02, // 81 + 0x00,0x00,0xF8,0x03,0x48,0x00,0x48,0x00,0xC8,0x00,0x30,0x03, // 82 + 0x00,0x00,0x30,0x01,0x48,0x02,0x48,0x02,0x48,0x02,0x90,0x01, // 83 + 0x00,0x00,0x08,0x00,0x08,0x00,0xF8,0x03,0x08,0x00,0x08, // 84 + 0x00,0x00,0xF8,0x01,0x00,0x02,0x00,0x02,0x00,0x02,0xF8,0x01, // 85 + 0x08,0x00,0x70,0x00,0x80,0x01,0x00,0x02,0x80,0x01,0x70,0x00,0x08, // 86 + 0x18,0x00,0xE0,0x01,0x00,0x02,0xF0,0x01,0x08,0x00,0xF0,0x01,0x00,0x02,0xE0,0x01,0x18, // 87 + 0x00,0x02,0x08,0x01,0x90,0x00,0x60,0x00,0x90,0x00,0x08,0x01,0x00,0x02, // 88 + 0x08,0x00,0x10,0x00,0x20,0x00,0xC0,0x03,0x20,0x00,0x10,0x00,0x08, // 89 + 0x08,0x03,0x88,0x02,0xC8,0x02,0x68,0x02,0x38,0x02,0x18,0x02, // 90 + 0x00,0x00,0xF8,0x0F,0x08,0x08, // 91 + 0x18,0x00,0xE0,0x00,0x00,0x03, // 92 + 0x08,0x08,0xF8,0x0F, // 93 + 0x40,0x00,0x30,0x00,0x08,0x00,0x30,0x00,0x40, // 94 + 0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x08, // 95 + 0x08,0x00,0x10, // 96 + 0x00,0x00,0x00,0x03,0xA0,0x02,0xA0,0x02,0xE0,0x03, // 97 + 0x00,0x00,0xF8,0x03,0x20,0x02,0x20,0x02,0xC0,0x01, // 98 + 0x00,0x00,0xC0,0x01,0x20,0x02,0x20,0x02,0x40,0x01, // 99 + 0x00,0x00,0xC0,0x01,0x20,0x02,0x20,0x02,0xF8,0x03, // 100 + 0x00,0x00,0xC0,0x01,0xA0,0x02,0xA0,0x02,0xC0,0x02, // 101 + 0x20,0x00,0xF0,0x03,0x28, // 102 + 0x00,0x00,0xC0,0x05,0x20,0x0A,0x20,0x0A,0xE0,0x07, // 103 + 0x00,0x00,0xF8,0x03,0x20,0x00,0x20,0x00,0xC0,0x03, // 104 + 0x00,0x00,0xE8,0x03, // 105 + 0x00,0x08,0xE8,0x07, // 106 + 0xF8,0x03,0x80,0x00,0xC0,0x01,0x20,0x02, // 107 + 0x00,0x00,0xF8,0x03, // 108 + 0x00,0x00,0xE0,0x03,0x20,0x00,0x20,0x00,0xE0,0x03,0x20,0x00,0x20,0x00,0xC0,0x03, // 109 + 0x00,0x00,0xE0,0x03,0x20,0x00,0x20,0x00,0xC0,0x03, // 110 + 0x00,0x00,0xC0,0x01,0x20,0x02,0x20,0x02,0xC0,0x01, // 111 + 0x00,0x00,0xE0,0x0F,0x20,0x02,0x20,0x02,0xC0,0x01, // 112 + 0x00,0x00,0xC0,0x01,0x20,0x02,0x20,0x02,0xE0,0x0F, // 113 + 0x00,0x00,0xE0,0x03,0x20, // 114 + 0x40,0x02,0xA0,0x02,0xA0,0x02,0x20,0x01, // 115 + 0x20,0x00,0xF8,0x03,0x20,0x02, // 116 + 0x00,0x00,0xE0,0x01,0x00,0x02,0x00,0x02,0xE0,0x03, // 117 + 0x20,0x00,0xC0,0x01,0x00,0x02,0xC0,0x01,0x20, // 118 + 0xE0,0x01,0x00,0x02,0xC0,0x01,0x20,0x00,0xC0,0x01,0x00,0x02,0xE0,0x01, // 119 + 0x20,0x02,0x40,0x01,0x80,0x00,0x40,0x01,0x20,0x02, // 120 + 0x20,0x00,0xC0,0x09,0x00,0x06,0xC0,0x01,0x20, // 121 + 0x20,0x02,0x20,0x03,0xA0,0x02,0x60,0x02,0x20,0x02, // 122 + 0x80,0x00,0x78,0x0F,0x08,0x08, // 123 + 0x00,0x00,0xF8,0x0F, // 124 + 0x08,0x08,0x78,0x0F,0x80, // 125 + 0xC0,0x00,0x40,0x00,0xC0,0x00,0x80,0x00,0xC0, // 126 + 0x00,0x00,0xA0,0x0F, // 161 + 0x00,0x00,0xC0,0x01,0xA0,0x0F,0x78,0x02,0x40,0x01, // 162 + 0x40,0x02,0x70,0x03,0xC8,0x02,0x48,0x02,0x08,0x02,0x10,0x02, // 163 + 0x00,0x00,0xE0,0x01,0x20,0x01,0x20,0x01,0xE0,0x01, // 164 + 0x48,0x01,0x70,0x01,0xC0,0x03,0x70,0x01,0x48,0x01, // 165 + 0x00,0x00,0x38,0x0F, // 166 + 0xD0,0x04,0x28,0x09,0x48,0x09,0x48,0x0A,0x90,0x05, // 167 + 0x08,0x00,0x00,0x00,0x08, // 168 + 0xE0,0x00,0x10,0x01,0x48,0x02,0xA8,0x02,0xA8,0x02,0x10,0x01,0xE0, // 169 + 0x68,0x00,0x68,0x00,0x68,0x00,0x78, // 170 + 0x00,0x00,0x80,0x01,0x40,0x02,0x80,0x01,0x40,0x02, // 171 + 0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0xE0, // 172 + 0x80,0x00,0x80, // 173 + 0xE0,0x00,0x10,0x01,0xE8,0x02,0x68,0x02,0xC8,0x02,0x10,0x01,0xE0, // 174 + 0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02, // 175 + 0x00,0x00,0x38,0x00,0x28,0x00,0x38, // 176 + 0x40,0x02,0x40,0x02,0xF0,0x03,0x40,0x02,0x40,0x02, // 177 + 0x48,0x00,0x68,0x00,0x58, // 178 + 0x48,0x00,0x58,0x00,0x68, // 179 + 0x00,0x00,0x10,0x00,0x08, // 180 + 0x00,0x00,0xE0,0x0F,0x00,0x02,0x00,0x02,0xE0,0x03, // 181 + 0x70,0x00,0xF8,0x0F,0x08,0x00,0xF8,0x0F,0x08, // 182 + 0x00,0x00,0x40, // 183 + 0x00,0x00,0x00,0x14,0x00,0x18, // 184 + 0x00,0x00,0x10,0x00,0x78, // 185 + 0x30,0x00,0x48,0x00,0x48,0x00,0x30, // 186 + 0x00,0x00,0x40,0x02,0x80,0x01,0x40,0x02,0x80,0x01, // 187 + 0x00,0x00,0x10,0x02,0x78,0x01,0xC0,0x00,0x20,0x01,0x90,0x01,0xC8,0x03,0x00,0x01, // 188 + 0x00,0x00,0x10,0x02,0x78,0x01,0x80,0x00,0x60,0x00,0x50,0x02,0x48,0x03,0xC0,0x02, // 189 + 0x48,0x00,0x58,0x00,0x68,0x03,0x80,0x00,0x60,0x01,0x90,0x01,0xC8,0x03,0x00,0x01, // 190 + 0x00,0x00,0x00,0x06,0x00,0x09,0xA0,0x09,0x00,0x04, // 191 + 0x00,0x02,0xC0,0x01,0xB0,0x00,0x89,0x00,0xB2,0x00,0xC0,0x01,0x00,0x02, // 192 + 0x00,0x02,0xC0,0x01,0xB0,0x00,0x8A,0x00,0xB1,0x00,0xC0,0x01,0x00,0x02, // 193 + 0x00,0x02,0xC0,0x01,0xB2,0x00,0x89,0x00,0xB2,0x00,0xC0,0x01,0x00,0x02, // 194 + 0x00,0x02,0xC2,0x01,0xB1,0x00,0x8A,0x00,0xB1,0x00,0xC0,0x01,0x00,0x02, // 195 + 0x00,0x02,0xC0,0x01,0xB2,0x00,0x88,0x00,0xB2,0x00,0xC0,0x01,0x00,0x02, // 196 + 0x00,0x02,0xC0,0x01,0xBE,0x00,0x8A,0x00,0xBE,0x00,0xC0,0x01,0x00,0x02, // 197 + 0x00,0x03,0xC0,0x00,0xE0,0x00,0x98,0x00,0x88,0x00,0xF8,0x03,0x48,0x02,0x48,0x02,0x48,0x02, // 198 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x08,0x16,0x08,0x1A,0x10,0x01, // 199 + 0x00,0x00,0xF8,0x03,0x49,0x02,0x4A,0x02,0x48,0x02,0x48,0x02, // 200 + 0x00,0x00,0xF8,0x03,0x48,0x02,0x4A,0x02,0x49,0x02,0x48,0x02, // 201 + 0x00,0x00,0xFA,0x03,0x49,0x02,0x4A,0x02,0x48,0x02,0x48,0x02, // 202 + 0x00,0x00,0xF8,0x03,0x4A,0x02,0x48,0x02,0x4A,0x02,0x48,0x02, // 203 + 0x00,0x00,0xF9,0x03,0x02, // 204 + 0x02,0x00,0xF9,0x03, // 205 + 0x01,0x00,0xFA,0x03, // 206 + 0x02,0x00,0xF8,0x03,0x02, // 207 + 0x40,0x00,0xF8,0x03,0x48,0x02,0x48,0x02,0x10,0x01,0xE0, // 208 + 0x00,0x00,0xFA,0x03,0x31,0x00,0x42,0x00,0x81,0x01,0xF8,0x03, // 209 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x09,0x02,0x0A,0x02,0x08,0x02,0xF0,0x01, // 210 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x0A,0x02,0x09,0x02,0x08,0x02,0xF0,0x01, // 211 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x0A,0x02,0x09,0x02,0x0A,0x02,0xF0,0x01, // 212 + 0x00,0x00,0xF0,0x01,0x0A,0x02,0x09,0x02,0x0A,0x02,0x09,0x02,0xF0,0x01, // 213 + 0x00,0x00,0xF0,0x01,0x0A,0x02,0x08,0x02,0x0A,0x02,0x08,0x02,0xF0,0x01, // 214 + 0x10,0x01,0xA0,0x00,0xE0,0x00,0xA0,0x00,0x10,0x01, // 215 + 0x00,0x00,0xF0,0x02,0x08,0x03,0xC8,0x02,0x28,0x02,0x18,0x03,0xE8, // 216 + 0x00,0x00,0xF8,0x01,0x01,0x02,0x02,0x02,0x00,0x02,0xF8,0x01, // 217 + 0x00,0x00,0xF8,0x01,0x02,0x02,0x01,0x02,0x00,0x02,0xF8,0x01, // 218 + 0x00,0x00,0xF8,0x01,0x02,0x02,0x01,0x02,0x02,0x02,0xF8,0x01, // 219 + 0x00,0x00,0xF8,0x01,0x02,0x02,0x00,0x02,0x02,0x02,0xF8,0x01, // 220 + 0x08,0x00,0x10,0x00,0x20,0x00,0xC2,0x03,0x21,0x00,0x10,0x00,0x08, // 221 + 0x00,0x00,0xF8,0x03,0x10,0x01,0x10,0x01,0x10,0x01,0xE0, // 222 + 0x00,0x00,0xF0,0x03,0x08,0x01,0x48,0x02,0xB0,0x02,0x80,0x01, // 223 + 0x00,0x00,0x00,0x03,0xA4,0x02,0xA8,0x02,0xE0,0x03, // 224 + 0x00,0x00,0x00,0x03,0xA8,0x02,0xA4,0x02,0xE0,0x03, // 225 + 0x00,0x00,0x00,0x03,0xA8,0x02,0xA4,0x02,0xE8,0x03, // 226 + 0x00,0x00,0x08,0x03,0xA4,0x02,0xA8,0x02,0xE4,0x03, // 227 + 0x00,0x00,0x00,0x03,0xA8,0x02,0xA0,0x02,0xE8,0x03, // 228 + 0x00,0x00,0x00,0x03,0xAE,0x02,0xAA,0x02,0xEE,0x03, // 229 + 0x00,0x00,0x40,0x03,0xA0,0x02,0xA0,0x02,0xC0,0x01,0xA0,0x02,0xA0,0x02,0xC0,0x02, // 230 + 0x00,0x00,0xC0,0x01,0x20,0x16,0x20,0x1A,0x40,0x01, // 231 + 0x00,0x00,0xC0,0x01,0xA4,0x02,0xA8,0x02,0xC0,0x02, // 232 + 0x00,0x00,0xC0,0x01,0xA8,0x02,0xA4,0x02,0xC0,0x02, // 233 + 0x00,0x00,0xC0,0x01,0xA8,0x02,0xA4,0x02,0xC8,0x02, // 234 + 0x00,0x00,0xC0,0x01,0xA8,0x02,0xA0,0x02,0xC8,0x02, // 235 + 0x00,0x00,0xE4,0x03,0x08, // 236 + 0x08,0x00,0xE4,0x03, // 237 + 0x08,0x00,0xE4,0x03,0x08, // 238 + 0x08,0x00,0xE0,0x03,0x08, // 239 + 0x00,0x00,0xC0,0x01,0x28,0x02,0x38,0x02,0xE0,0x01, // 240 + 0x00,0x00,0xE8,0x03,0x24,0x00,0x28,0x00,0xC4,0x03, // 241 + 0x00,0x00,0xC0,0x01,0x24,0x02,0x28,0x02,0xC0,0x01, // 242 + 0x00,0x00,0xC0,0x01,0x28,0x02,0x24,0x02,0xC0,0x01, // 243 + 0x00,0x00,0xC0,0x01,0x28,0x02,0x24,0x02,0xC8,0x01, // 244 + 0x00,0x00,0xC8,0x01,0x24,0x02,0x28,0x02,0xC4,0x01, // 245 + 0x00,0x00,0xC0,0x01,0x28,0x02,0x20,0x02,0xC8,0x01, // 246 + 0x40,0x00,0x40,0x00,0x50,0x01,0x40,0x00,0x40, // 247 + 0x00,0x00,0xC0,0x02,0xA0,0x03,0x60,0x02,0xA0,0x01, // 248 + 0x00,0x00,0xE0,0x01,0x04,0x02,0x08,0x02,0xE0,0x03, // 249 + 0x00,0x00,0xE0,0x01,0x08,0x02,0x04,0x02,0xE0,0x03, // 250 + 0x00,0x00,0xE8,0x01,0x04,0x02,0x08,0x02,0xE0,0x03, // 251 + 0x00,0x00,0xE0,0x01,0x08,0x02,0x00,0x02,0xE8,0x03, // 252 + 0x20,0x00,0xC0,0x09,0x08,0x06,0xC4,0x01,0x20, // 253 + 0x00,0x00,0xF8,0x0F,0x20,0x02,0x20,0x02,0xC0,0x01, // 254 + 0x20,0x00,0xC8,0x09,0x00,0x06,0xC8,0x01,0x20 // 255 +}; + +const uint8_t ArialMT_Plain_16[] PROGMEM = { + 0x10, // Width: 16 + 0x13, // Height: 19 + 0x20, // First Char: 32 + 0xE0, // Numbers of Chars: 224 + + // Jump Table: + 0xFF, 0xFF, 0x00, 0x04, // 32:65535 + 0x00, 0x00, 0x08, 0x04, // 33:0 + 0x00, 0x08, 0x0D, 0x06, // 34:8 + 0x00, 0x15, 0x1A, 0x09, // 35:21 + 0x00, 0x2F, 0x17, 0x09, // 36:47 + 0x00, 0x46, 0x26, 0x0E, // 37:70 + 0x00, 0x6C, 0x1D, 0x0B, // 38:108 + 0x00, 0x89, 0x04, 0x03, // 39:137 + 0x00, 0x8D, 0x0C, 0x05, // 40:141 + 0x00, 0x99, 0x0B, 0x05, // 41:153 + 0x00, 0xA4, 0x0D, 0x06, // 42:164 + 0x00, 0xB1, 0x17, 0x09, // 43:177 + 0x00, 0xC8, 0x09, 0x04, // 44:200 + 0x00, 0xD1, 0x0B, 0x05, // 45:209 + 0x00, 0xDC, 0x08, 0x04, // 46:220 + 0x00, 0xE4, 0x0A, 0x04, // 47:228 + 0x00, 0xEE, 0x17, 0x09, // 48:238 + 0x01, 0x05, 0x11, 0x09, // 49:261 + 0x01, 0x16, 0x17, 0x09, // 50:278 + 0x01, 0x2D, 0x17, 0x09, // 51:301 + 0x01, 0x44, 0x17, 0x09, // 52:324 + 0x01, 0x5B, 0x17, 0x09, // 53:347 + 0x01, 0x72, 0x17, 0x09, // 54:370 + 0x01, 0x89, 0x16, 0x09, // 55:393 + 0x01, 0x9F, 0x17, 0x09, // 56:415 + 0x01, 0xB6, 0x17, 0x09, // 57:438 + 0x01, 0xCD, 0x05, 0x04, // 58:461 + 0x01, 0xD2, 0x06, 0x04, // 59:466 + 0x01, 0xD8, 0x17, 0x09, // 60:472 + 0x01, 0xEF, 0x17, 0x09, // 61:495 + 0x02, 0x06, 0x17, 0x09, // 62:518 + 0x02, 0x1D, 0x16, 0x09, // 63:541 + 0x02, 0x33, 0x2F, 0x10, // 64:563 + 0x02, 0x62, 0x1D, 0x0B, // 65:610 + 0x02, 0x7F, 0x1D, 0x0B, // 66:639 + 0x02, 0x9C, 0x20, 0x0C, // 67:668 + 0x02, 0xBC, 0x20, 0x0C, // 68:700 + 0x02, 0xDC, 0x1D, 0x0B, // 69:732 + 0x02, 0xF9, 0x19, 0x0A, // 70:761 + 0x03, 0x12, 0x20, 0x0C, // 71:786 + 0x03, 0x32, 0x1D, 0x0C, // 72:818 + 0x03, 0x4F, 0x05, 0x04, // 73:847 + 0x03, 0x54, 0x14, 0x08, // 74:852 + 0x03, 0x68, 0x1D, 0x0B, // 75:872 + 0x03, 0x85, 0x17, 0x09, // 76:901 + 0x03, 0x9C, 0x23, 0x0D, // 77:924 + 0x03, 0xBF, 0x1D, 0x0C, // 78:959 + 0x03, 0xDC, 0x20, 0x0C, // 79:988 + 0x03, 0xFC, 0x1C, 0x0B, // 80:1020 + 0x04, 0x18, 0x20, 0x0C, // 81:1048 + 0x04, 0x38, 0x1D, 0x0C, // 82:1080 + 0x04, 0x55, 0x1D, 0x0B, // 83:1109 + 0x04, 0x72, 0x19, 0x0A, // 84:1138 + 0x04, 0x8B, 0x1D, 0x0C, // 85:1163 + 0x04, 0xA8, 0x1C, 0x0B, // 86:1192 + 0x04, 0xC4, 0x2B, 0x0F, // 87:1220 + 0x04, 0xEF, 0x20, 0x0B, // 88:1263 + 0x05, 0x0F, 0x19, 0x0B, // 89:1295 + 0x05, 0x28, 0x1A, 0x0A, // 90:1320 + 0x05, 0x42, 0x0C, 0x04, // 91:1346 + 0x05, 0x4E, 0x0B, 0x04, // 92:1358 + 0x05, 0x59, 0x09, 0x04, // 93:1369 + 0x05, 0x62, 0x14, 0x08, // 94:1378 + 0x05, 0x76, 0x1B, 0x09, // 95:1398 + 0x05, 0x91, 0x07, 0x05, // 96:1425 + 0x05, 0x98, 0x17, 0x09, // 97:1432 + 0x05, 0xAF, 0x17, 0x09, // 98:1455 + 0x05, 0xC6, 0x14, 0x08, // 99:1478 + 0x05, 0xDA, 0x17, 0x09, // 100:1498 + 0x05, 0xF1, 0x17, 0x09, // 101:1521 + 0x06, 0x08, 0x0A, 0x04, // 102:1544 + 0x06, 0x12, 0x17, 0x09, // 103:1554 + 0x06, 0x29, 0x14, 0x09, // 104:1577 + 0x06, 0x3D, 0x05, 0x04, // 105:1597 + 0x06, 0x42, 0x06, 0x04, // 106:1602 + 0x06, 0x48, 0x17, 0x08, // 107:1608 + 0x06, 0x5F, 0x05, 0x04, // 108:1631 + 0x06, 0x64, 0x23, 0x0D, // 109:1636 + 0x06, 0x87, 0x14, 0x09, // 110:1671 + 0x06, 0x9B, 0x17, 0x09, // 111:1691 + 0x06, 0xB2, 0x17, 0x09, // 112:1714 + 0x06, 0xC9, 0x18, 0x09, // 113:1737 + 0x06, 0xE1, 0x0D, 0x05, // 114:1761 + 0x06, 0xEE, 0x14, 0x08, // 115:1774 + 0x07, 0x02, 0x0B, 0x04, // 116:1794 + 0x07, 0x0D, 0x14, 0x09, // 117:1805 + 0x07, 0x21, 0x13, 0x08, // 118:1825 + 0x07, 0x34, 0x1F, 0x0C, // 119:1844 + 0x07, 0x53, 0x14, 0x08, // 120:1875 + 0x07, 0x67, 0x13, 0x08, // 121:1895 + 0x07, 0x7A, 0x14, 0x08, // 122:1914 + 0x07, 0x8E, 0x0F, 0x05, // 123:1934 + 0x07, 0x9D, 0x06, 0x04, // 124:1949 + 0x07, 0xA3, 0x0E, 0x05, // 125:1955 + 0x07, 0xB1, 0x17, 0x09, // 126:1969 + 0xFF, 0xFF, 0x00, 0x00, // 127:65535 + 0xFF, 0xFF, 0x00, 0x10, // 128:65535 + 0xFF, 0xFF, 0x00, 0x10, // 129:65535 + 0xFF, 0xFF, 0x00, 0x10, // 130:65535 + 0xFF, 0xFF, 0x00, 0x10, // 131:65535 + 0xFF, 0xFF, 0x00, 0x10, // 132:65535 + 0xFF, 0xFF, 0x00, 0x10, // 133:65535 + 0xFF, 0xFF, 0x00, 0x10, // 134:65535 + 0xFF, 0xFF, 0x00, 0x10, // 135:65535 + 0xFF, 0xFF, 0x00, 0x10, // 136:65535 + 0xFF, 0xFF, 0x00, 0x10, // 137:65535 + 0xFF, 0xFF, 0x00, 0x10, // 138:65535 + 0xFF, 0xFF, 0x00, 0x10, // 139:65535 + 0xFF, 0xFF, 0x00, 0x10, // 140:65535 + 0xFF, 0xFF, 0x00, 0x10, // 141:65535 + 0xFF, 0xFF, 0x00, 0x10, // 142:65535 + 0xFF, 0xFF, 0x00, 0x10, // 143:65535 + 0xFF, 0xFF, 0x00, 0x10, // 144:65535 + 0xFF, 0xFF, 0x00, 0x10, // 145:65535 + 0xFF, 0xFF, 0x00, 0x10, // 146:65535 + 0xFF, 0xFF, 0x00, 0x10, // 147:65535 + 0xFF, 0xFF, 0x00, 0x10, // 148:65535 + 0xFF, 0xFF, 0x00, 0x10, // 149:65535 + 0xFF, 0xFF, 0x00, 0x10, // 150:65535 + 0xFF, 0xFF, 0x00, 0x10, // 151:65535 + 0xFF, 0xFF, 0x00, 0x10, // 152:65535 + 0xFF, 0xFF, 0x00, 0x10, // 153:65535 + 0xFF, 0xFF, 0x00, 0x10, // 154:65535 + 0xFF, 0xFF, 0x00, 0x10, // 155:65535 + 0xFF, 0xFF, 0x00, 0x10, // 156:65535 + 0xFF, 0xFF, 0x00, 0x10, // 157:65535 + 0xFF, 0xFF, 0x00, 0x10, // 158:65535 + 0xFF, 0xFF, 0x00, 0x10, // 159:65535 + 0xFF, 0xFF, 0x00, 0x04, // 160:65535 + 0x07, 0xC8, 0x09, 0x05, // 161:1992 + 0x07, 0xD1, 0x17, 0x09, // 162:2001 + 0x07, 0xE8, 0x17, 0x09, // 163:2024 + 0x07, 0xFF, 0x14, 0x09, // 164:2047 + 0x08, 0x13, 0x1A, 0x09, // 165:2067 + 0x08, 0x2D, 0x06, 0x04, // 166:2093 + 0x08, 0x33, 0x17, 0x09, // 167:2099 + 0x08, 0x4A, 0x07, 0x05, // 168:2122 + 0x08, 0x51, 0x23, 0x0C, // 169:2129 + 0x08, 0x74, 0x0E, 0x06, // 170:2164 + 0x08, 0x82, 0x14, 0x09, // 171:2178 + 0x08, 0x96, 0x17, 0x09, // 172:2198 + 0x08, 0xAD, 0x0B, 0x05, // 173:2221 + 0x08, 0xB8, 0x23, 0x0C, // 174:2232 + 0x08, 0xDB, 0x19, 0x09, // 175:2267 + 0x08, 0xF4, 0x0D, 0x06, // 176:2292 + 0x09, 0x01, 0x17, 0x09, // 177:2305 + 0x09, 0x18, 0x0E, 0x05, // 178:2328 + 0x09, 0x26, 0x0D, 0x05, // 179:2342 + 0x09, 0x33, 0x0A, 0x05, // 180:2355 + 0x09, 0x3D, 0x17, 0x09, // 181:2365 + 0x09, 0x54, 0x19, 0x09, // 182:2388 + 0x09, 0x6D, 0x08, 0x05, // 183:2413 + 0x09, 0x75, 0x0C, 0x05, // 184:2421 + 0x09, 0x81, 0x0B, 0x05, // 185:2433 + 0x09, 0x8C, 0x0D, 0x06, // 186:2444 + 0x09, 0x99, 0x17, 0x09, // 187:2457 + 0x09, 0xB0, 0x26, 0x0D, // 188:2480 + 0x09, 0xD6, 0x26, 0x0D, // 189:2518 + 0x09, 0xFC, 0x26, 0x0D, // 190:2556 + 0x0A, 0x22, 0x1A, 0x0A, // 191:2594 + 0x0A, 0x3C, 0x1D, 0x0B, // 192:2620 + 0x0A, 0x59, 0x1D, 0x0B, // 193:2649 + 0x0A, 0x76, 0x1D, 0x0B, // 194:2678 + 0x0A, 0x93, 0x1D, 0x0B, // 195:2707 + 0x0A, 0xB0, 0x1D, 0x0B, // 196:2736 + 0x0A, 0xCD, 0x1D, 0x0B, // 197:2765 + 0x0A, 0xEA, 0x2C, 0x10, // 198:2794 + 0x0B, 0x16, 0x20, 0x0C, // 199:2838 + 0x0B, 0x36, 0x1D, 0x0B, // 200:2870 + 0x0B, 0x53, 0x1D, 0x0B, // 201:2899 + 0x0B, 0x70, 0x1D, 0x0B, // 202:2928 + 0x0B, 0x8D, 0x1D, 0x0B, // 203:2957 + 0x0B, 0xAA, 0x05, 0x04, // 204:2986 + 0x0B, 0xAF, 0x07, 0x04, // 205:2991 + 0x0B, 0xB6, 0x0A, 0x04, // 206:2998 + 0x0B, 0xC0, 0x07, 0x04, // 207:3008 + 0x0B, 0xC7, 0x20, 0x0C, // 208:3015 + 0x0B, 0xE7, 0x1D, 0x0C, // 209:3047 + 0x0C, 0x04, 0x20, 0x0C, // 210:3076 + 0x0C, 0x24, 0x20, 0x0C, // 211:3108 + 0x0C, 0x44, 0x20, 0x0C, // 212:3140 + 0x0C, 0x64, 0x20, 0x0C, // 213:3172 + 0x0C, 0x84, 0x20, 0x0C, // 214:3204 + 0x0C, 0xA4, 0x17, 0x09, // 215:3236 + 0x0C, 0xBB, 0x20, 0x0C, // 216:3259 + 0x0C, 0xDB, 0x1D, 0x0C, // 217:3291 + 0x0C, 0xF8, 0x1D, 0x0C, // 218:3320 + 0x0D, 0x15, 0x1D, 0x0C, // 219:3349 + 0x0D, 0x32, 0x1D, 0x0C, // 220:3378 + 0x0D, 0x4F, 0x19, 0x0B, // 221:3407 + 0x0D, 0x68, 0x1D, 0x0B, // 222:3432 + 0x0D, 0x85, 0x17, 0x0A, // 223:3461 + 0x0D, 0x9C, 0x17, 0x09, // 224:3484 + 0x0D, 0xB3, 0x17, 0x09, // 225:3507 + 0x0D, 0xCA, 0x17, 0x09, // 226:3530 + 0x0D, 0xE1, 0x17, 0x09, // 227:3553 + 0x0D, 0xF8, 0x17, 0x09, // 228:3576 + 0x0E, 0x0F, 0x17, 0x09, // 229:3599 + 0x0E, 0x26, 0x29, 0x0E, // 230:3622 + 0x0E, 0x4F, 0x14, 0x08, // 231:3663 + 0x0E, 0x63, 0x17, 0x09, // 232:3683 + 0x0E, 0x7A, 0x17, 0x09, // 233:3706 + 0x0E, 0x91, 0x17, 0x09, // 234:3729 + 0x0E, 0xA8, 0x17, 0x09, // 235:3752 + 0x0E, 0xBF, 0x05, 0x04, // 236:3775 + 0x0E, 0xC4, 0x07, 0x04, // 237:3780 + 0x0E, 0xCB, 0x0A, 0x04, // 238:3787 + 0x0E, 0xD5, 0x07, 0x04, // 239:3797 + 0x0E, 0xDC, 0x17, 0x09, // 240:3804 + 0x0E, 0xF3, 0x14, 0x09, // 241:3827 + 0x0F, 0x07, 0x17, 0x09, // 242:3847 + 0x0F, 0x1E, 0x17, 0x09, // 243:3870 + 0x0F, 0x35, 0x17, 0x09, // 244:3893 + 0x0F, 0x4C, 0x17, 0x09, // 245:3916 + 0x0F, 0x63, 0x17, 0x09, // 246:3939 + 0x0F, 0x7A, 0x17, 0x09, // 247:3962 + 0x0F, 0x91, 0x17, 0x0A, // 248:3985 + 0x0F, 0xA8, 0x14, 0x09, // 249:4008 + 0x0F, 0xBC, 0x14, 0x09, // 250:4028 + 0x0F, 0xD0, 0x14, 0x09, // 251:4048 + 0x0F, 0xE4, 0x14, 0x09, // 252:4068 + 0x0F, 0xF8, 0x13, 0x08, // 253:4088 + 0x10, 0x0B, 0x17, 0x09, // 254:4107 + 0x10, 0x22, 0x13, 0x08, // 255:4130 + + // Font Data: + 0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x5F, // 33 + 0x00,0x00,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78, // 34 + 0x80,0x08,0x00,0x80,0x78,0x00,0xC0,0x0F,0x00,0xB8,0x08,0x00,0x80,0x08,0x00,0x80,0x78,0x00,0xC0,0x0F,0x00,0xB8,0x08,0x00,0x80,0x08, // 35 + 0x00,0x00,0x00,0xE0,0x10,0x00,0x10,0x21,0x00,0x08,0x41,0x00,0xFC,0xFF,0x00,0x08,0x42,0x00,0x10,0x22,0x00,0x20,0x1C, // 36 + 0x00,0x00,0x00,0xF0,0x00,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0x08,0x61,0x00,0xF0,0x18,0x00,0x00,0x06,0x00,0xC0,0x01,0x00,0x30,0x3C,0x00,0x08,0x42,0x00,0x00,0x42,0x00,0x00,0x42,0x00,0x00,0x3C, // 37 + 0x00,0x00,0x00,0x00,0x1C,0x00,0x70,0x22,0x00,0x88,0x41,0x00,0x08,0x43,0x00,0x88,0x44,0x00,0x70,0x28,0x00,0x00,0x10,0x00,0x00,0x28,0x00,0x00,0x44, // 38 + 0x00,0x00,0x00,0x78, // 39 + 0x00,0x00,0x00,0x80,0x3F,0x00,0x70,0xC0,0x01,0x08,0x00,0x02, // 40 + 0x00,0x00,0x00,0x08,0x00,0x02,0x70,0xC0,0x01,0x80,0x3F, // 41 + 0x10,0x00,0x00,0xD0,0x00,0x00,0x38,0x00,0x00,0xD0,0x00,0x00,0x10, // 42 + 0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0xC0,0x1F,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02, // 43 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x01, // 44 + 0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08, // 45 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40, // 46 + 0x00,0x60,0x00,0x00,0x1E,0x00,0xE0,0x01,0x00,0x18, // 47 + 0x00,0x00,0x00,0xE0,0x1F,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0xE0,0x1F, // 48 + 0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0xF8,0x7F, // 49 + 0x00,0x00,0x00,0x20,0x40,0x00,0x10,0x60,0x00,0x08,0x50,0x00,0x08,0x48,0x00,0x08,0x44,0x00,0x10,0x43,0x00,0xE0,0x40, // 50 + 0x00,0x00,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x88,0x41,0x00,0xF0,0x22,0x00,0x00,0x1C, // 51 + 0x00,0x0C,0x00,0x00,0x0A,0x00,0x00,0x09,0x00,0xC0,0x08,0x00,0x20,0x08,0x00,0x10,0x08,0x00,0xF8,0x7F,0x00,0x00,0x08, // 52 + 0x00,0x00,0x00,0xC0,0x11,0x00,0xB8,0x20,0x00,0x88,0x40,0x00,0x88,0x40,0x00,0x88,0x40,0x00,0x08,0x21,0x00,0x08,0x1E, // 53 + 0x00,0x00,0x00,0xE0,0x1F,0x00,0x10,0x21,0x00,0x88,0x40,0x00,0x88,0x40,0x00,0x88,0x40,0x00,0x10,0x21,0x00,0x20,0x1E, // 54 + 0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x78,0x00,0x08,0x07,0x00,0xC8,0x00,0x00,0x28,0x00,0x00,0x18, // 55 + 0x00,0x00,0x00,0x60,0x1C,0x00,0x90,0x22,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x90,0x22,0x00,0x60,0x1C, // 56 + 0x00,0x00,0x00,0xE0,0x11,0x00,0x10,0x22,0x00,0x08,0x44,0x00,0x08,0x44,0x00,0x08,0x44,0x00,0x10,0x22,0x00,0xE0,0x1F, // 57 + 0x00,0x00,0x00,0x40,0x40, // 58 + 0x00,0x00,0x00,0x40,0xC0,0x01, // 59 + 0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x05,0x00,0x00,0x05,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x40,0x10, // 60 + 0x00,0x00,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08, // 61 + 0x00,0x00,0x00,0x40,0x10,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x00,0x05,0x00,0x00,0x05,0x00,0x00,0x02, // 62 + 0x00,0x00,0x00,0x60,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x08,0x5C,0x00,0x08,0x02,0x00,0x10,0x01,0x00,0xE0, // 63 + 0x00,0x00,0x00,0x00,0x3F,0x00,0xC0,0x40,0x00,0x20,0x80,0x00,0x10,0x1E,0x01,0x10,0x21,0x01,0x88,0x40,0x02,0x48,0x40,0x02,0x48,0x40,0x02,0x48,0x20,0x02,0x88,0x7C,0x02,0xC8,0x43,0x02,0x10,0x40,0x02,0x10,0x20,0x01,0x60,0x10,0x01,0x80,0x8F, // 64 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x70,0x04,0x00,0x08,0x04,0x00,0x70,0x04,0x00,0x80,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 65 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x90,0x22,0x00,0x60,0x1C, // 66 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10, // 67 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 68 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x40, // 69 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08, // 70 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x42,0x00,0x08,0x42,0x00,0x10,0x22,0x00,0x20,0x12,0x00,0x00,0x0E, // 71 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0xF8,0x7F, // 72 + 0x00,0x00,0x00,0xF8,0x7F, // 73 + 0x00,0x00,0x00,0x00,0x38,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0xF8,0x3F, // 74 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x00,0x04,0x00,0x00,0x02,0x00,0x00,0x01,0x00,0x80,0x03,0x00,0x40,0x04,0x00,0x20,0x18,0x00,0x10,0x20,0x00,0x08,0x40, // 75 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40, // 76 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x30,0x00,0x00,0xC0,0x00,0x00,0x00,0x03,0x00,0x00,0x1C,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x00,0x03,0x00,0xC0,0x00,0x00,0x30,0x00,0x00,0xF8,0x7F, // 77 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x10,0x00,0x00,0x60,0x00,0x00,0x80,0x00,0x00,0x00,0x03,0x00,0x00,0x04,0x00,0x00,0x18,0x00,0x00,0x20,0x00,0xF8,0x7F, // 78 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 79 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x10,0x01,0x00,0xE0, // 80 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x50,0x00,0x08,0x50,0x00,0x10,0x20,0x00,0x20,0x70,0x00,0xC0,0x4F, // 81 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x06,0x00,0x08,0x1A,0x00,0x10,0x21,0x00,0xE0,0x40, // 82 + 0x00,0x00,0x00,0x60,0x10,0x00,0x90,0x20,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x42,0x00,0x08,0x42,0x00,0x10,0x22,0x00,0x20,0x1C, // 83 + 0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0xF8,0x7F,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08, // 84 + 0x00,0x00,0x00,0xF8,0x1F,0x00,0x00,0x20,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xF8,0x1F, // 85 + 0x00,0x00,0x00,0x18,0x00,0x00,0xE0,0x00,0x00,0x00,0x07,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x18,0x00,0x00,0x07,0x00,0xE0,0x00,0x00,0x18, // 86 + 0x18,0x00,0x00,0xE0,0x01,0x00,0x00,0x1E,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x03,0x00,0x70,0x00,0x00,0x08,0x00,0x00,0x70,0x00,0x00,0x80,0x03,0x00,0x00,0x1C,0x00,0x00,0x60,0x00,0x00,0x1E,0x00,0xE0,0x01,0x00,0x18, // 87 + 0x00,0x40,0x00,0x08,0x20,0x00,0x10,0x10,0x00,0x60,0x0C,0x00,0x80,0x02,0x00,0x00,0x01,0x00,0x80,0x02,0x00,0x60,0x0C,0x00,0x10,0x10,0x00,0x08,0x20,0x00,0x00,0x40, // 88 + 0x08,0x00,0x00,0x30,0x00,0x00,0x40,0x00,0x00,0x80,0x01,0x00,0x00,0x7E,0x00,0x80,0x01,0x00,0x40,0x00,0x00,0x30,0x00,0x00,0x08, // 89 + 0x00,0x40,0x00,0x08,0x60,0x00,0x08,0x58,0x00,0x08,0x44,0x00,0x08,0x43,0x00,0x88,0x40,0x00,0x68,0x40,0x00,0x18,0x40,0x00,0x08,0x40, // 90 + 0x00,0x00,0x00,0xF8,0xFF,0x03,0x08,0x00,0x02,0x08,0x00,0x02, // 91 + 0x18,0x00,0x00,0xE0,0x01,0x00,0x00,0x1E,0x00,0x00,0x60, // 92 + 0x08,0x00,0x02,0x08,0x00,0x02,0xF8,0xFF,0x03, // 93 + 0x00,0x01,0x00,0xC0,0x00,0x00,0x30,0x00,0x00,0x08,0x00,0x00,0x30,0x00,0x00,0xC0,0x00,0x00,0x00,0x01, // 94 + 0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02, // 95 + 0x00,0x00,0x00,0x08,0x00,0x00,0x10, // 96 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x42,0x00,0x40,0x22,0x00,0x80,0x7F, // 97 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 98 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20, // 99 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0xF8,0x7F, // 100 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x24,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x80,0x24,0x00,0x00,0x17, // 101 + 0x40,0x00,0x00,0xF0,0x7F,0x00,0x48,0x00,0x00,0x48, // 102 + 0x00,0x00,0x00,0x00,0x1F,0x01,0x80,0x20,0x02,0x40,0x40,0x02,0x40,0x40,0x02,0x40,0x40,0x02,0x80,0x20,0x01,0xC0,0xFF, // 103 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x80,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x80,0x7F, // 104 + 0x00,0x00,0x00,0xC8,0x7F, // 105 + 0x00,0x00,0x02,0xC8,0xFF,0x01, // 106 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x00,0x08,0x00,0x00,0x04,0x00,0x00,0x06,0x00,0x00,0x19,0x00,0x80,0x20,0x00,0x40,0x40, // 107 + 0x00,0x00,0x00,0xF8,0x7F, // 108 + 0x00,0x00,0x00,0xC0,0x7F,0x00,0x80,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x80,0x7F,0x00,0x80,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x80,0x7F, // 109 + 0x00,0x00,0x00,0xC0,0x7F,0x00,0x80,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x80,0x7F, // 110 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 111 + 0x00,0x00,0x00,0xC0,0xFF,0x03,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 112 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0xC0,0xFF,0x03, // 113 + 0x00,0x00,0x00,0xC0,0x7F,0x00,0x80,0x00,0x00,0x40,0x00,0x00,0x40, // 114 + 0x00,0x00,0x00,0x80,0x23,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x80,0x38, // 115 + 0x40,0x00,0x00,0xF0,0x7F,0x00,0x40,0x40,0x00,0x40,0x40, // 116 + 0x00,0x00,0x00,0xC0,0x3F,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xC0,0x7F, // 117 + 0xC0,0x00,0x00,0x00,0x03,0x00,0x00,0x1C,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x00,0x03,0x00,0xC0, // 118 + 0xC0,0x00,0x00,0x00,0x1F,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x00,0x03,0x00,0xC0,0x00,0x00,0x00,0x03,0x00,0x00,0x1C,0x00,0x00,0x60,0x00,0x00,0x1F,0x00,0xC0, // 119 + 0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1B,0x00,0x00,0x04,0x00,0x00,0x1B,0x00,0x80,0x20,0x00,0x40,0x40, // 120 + 0xC0,0x01,0x00,0x00,0x06,0x02,0x00,0x38,0x02,0x00,0xE0,0x01,0x00,0x38,0x00,0x00,0x07,0x00,0xC0, // 121 + 0x40,0x40,0x00,0x40,0x60,0x00,0x40,0x58,0x00,0x40,0x44,0x00,0x40,0x43,0x00,0xC0,0x40,0x00,0x40,0x40, // 122 + 0x00,0x04,0x00,0x00,0x04,0x00,0xF0,0xFB,0x01,0x08,0x00,0x02,0x08,0x00,0x02, // 123 + 0x00,0x00,0x00,0xF8,0xFF,0x03, // 124 + 0x08,0x00,0x02,0x08,0x00,0x02,0xF0,0xFB,0x01,0x00,0x04,0x00,0x00,0x04, // 125 + 0x00,0x02,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x01, // 126 + 0x00,0x00,0x00,0x00,0x00,0x00,0x40,0xFF,0x03, // 161 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x03,0x40,0xF0,0x00,0x40,0x4E,0x00,0xC0,0x41,0x00,0xB8,0x20,0x00,0x00,0x11, // 162 + 0x00,0x41,0x00,0xE0,0x31,0x00,0x10,0x2F,0x00,0x08,0x21,0x00,0x08,0x21,0x00,0x08,0x40,0x00,0x10,0x40,0x00,0x20,0x20, // 163 + 0x00,0x00,0x00,0x40,0x0B,0x00,0x80,0x04,0x00,0x40,0x08,0x00,0x40,0x08,0x00,0x80,0x04,0x00,0x40,0x0B, // 164 + 0x08,0x0A,0x00,0x10,0x0A,0x00,0x60,0x0A,0x00,0x80,0x0B,0x00,0x00,0x7E,0x00,0x80,0x0B,0x00,0x60,0x0A,0x00,0x10,0x0A,0x00,0x08,0x0A, // 165 + 0x00,0x00,0x00,0xF8,0xF1,0x03, // 166 + 0x00,0x86,0x00,0x70,0x09,0x01,0xC8,0x10,0x02,0x88,0x10,0x02,0x08,0x21,0x02,0x08,0x61,0x02,0x30,0xD2,0x01,0x00,0x0C, // 167 + 0x08,0x00,0x00,0x00,0x00,0x00,0x08, // 168 + 0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0xC8,0x47,0x00,0x28,0x48,0x00,0x28,0x48,0x00,0x28,0x48,0x00,0x28,0x48,0x00,0x48,0x44,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 169 + 0xD0,0x00,0x00,0x48,0x01,0x00,0x28,0x01,0x00,0x28,0x01,0x00,0xF0,0x01, // 170 + 0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x1B,0x00,0x80,0x20,0x00,0x00,0x04,0x00,0x00,0x1B,0x00,0x80,0x20, // 171 + 0x00,0x00,0x00,0x80,0x00,0x00,0x80,0x00,0x00,0x80,0x00,0x00,0x80,0x00,0x00,0x80,0x00,0x00,0x80,0x00,0x00,0x80,0x0F, // 172 + 0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08, // 173 + 0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0xE8,0x4F,0x00,0x28,0x41,0x00,0x28,0x41,0x00,0x28,0x43,0x00,0x28,0x45,0x00,0xC8,0x48,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 174 + 0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04, // 175 + 0x00,0x00,0x00,0x30,0x00,0x00,0x48,0x00,0x00,0x48,0x00,0x00,0x30, // 176 + 0x00,0x00,0x00,0x00,0x41,0x00,0x00,0x41,0x00,0x00,0x41,0x00,0xE0,0x4F,0x00,0x00,0x41,0x00,0x00,0x41,0x00,0x00,0x41, // 177 + 0x10,0x01,0x00,0x88,0x01,0x00,0x48,0x01,0x00,0x48,0x01,0x00,0x30,0x01, // 178 + 0x90,0x00,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0x28,0x01,0x00,0xD8, // 179 + 0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x08, // 180 + 0x00,0x00,0x00,0xC0,0xFF,0x03,0x00,0x20,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xC0,0x7F, // 181 + 0xF0,0x00,0x00,0xF8,0x00,0x00,0xF8,0x01,0x00,0xF8,0x01,0x00,0xF8,0xFF,0x03,0x08,0x00,0x00,0x08,0x00,0x00,0xF8,0xFF,0x03,0x08, // 182 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02, // 183 + 0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x80,0x02,0x00,0x00,0x03, // 184 + 0x00,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0xF8,0x01, // 185 + 0xF0,0x00,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0xF0, // 186 + 0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x20,0x00,0x00,0x1B,0x00,0x00,0x04,0x00,0x80,0x20,0x00,0x00,0x1B,0x00,0x00,0x04, // 187 + 0x00,0x00,0x00,0x10,0x00,0x00,0x08,0x40,0x00,0xF8,0x21,0x00,0x00,0x10,0x00,0x00,0x0C,0x00,0x00,0x02,0x00,0x80,0x01,0x00,0x40,0x30,0x00,0x30,0x28,0x00,0x08,0x24,0x00,0x00,0x7E,0x00,0x00,0x20, // 188 + 0x00,0x00,0x00,0x10,0x00,0x00,0x08,0x40,0x00,0xF8,0x31,0x00,0x00,0x08,0x00,0x00,0x04,0x00,0x00,0x03,0x00,0x80,0x00,0x00,0x60,0x44,0x00,0x10,0x62,0x00,0x08,0x52,0x00,0x00,0x52,0x00,0x00,0x4C, // 189 + 0x90,0x00,0x00,0x08,0x01,0x00,0x08,0x41,0x00,0x28,0x21,0x00,0xD8,0x18,0x00,0x00,0x04,0x00,0x00,0x03,0x00,0x80,0x00,0x00,0x40,0x30,0x00,0x30,0x28,0x00,0x08,0x24,0x00,0x00,0x7E,0x00,0x00,0x20, // 190 + 0x00,0x00,0x00,0x00,0xE0,0x00,0x00,0x10,0x01,0x00,0x08,0x02,0x40,0x07,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x01,0x00,0xC0, // 191 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x71,0x04,0x00,0x0A,0x04,0x00,0x70,0x04,0x00,0x80,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 192 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x70,0x04,0x00,0x0A,0x04,0x00,0x71,0x04,0x00,0x80,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 193 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x72,0x04,0x00,0x09,0x04,0x00,0x71,0x04,0x00,0x82,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 194 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x72,0x04,0x00,0x09,0x04,0x00,0x72,0x04,0x00,0x81,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 195 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x72,0x04,0x00,0x08,0x04,0x00,0x72,0x04,0x00,0x80,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 196 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x7E,0x04,0x00,0x0A,0x04,0x00,0x7E,0x04,0x00,0x80,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 197 + 0x00,0x60,0x00,0x00,0x18,0x00,0x00,0x06,0x00,0x80,0x05,0x00,0x60,0x04,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41, // 198 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x02,0x08,0xC0,0x02,0x08,0x40,0x03,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10, // 199 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x09,0x41,0x00,0x0A,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x40, // 200 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x0A,0x41,0x00,0x09,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x40, // 201 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x0A,0x41,0x00,0x09,0x41,0x00,0x09,0x41,0x00,0x0A,0x41,0x00,0x08,0x41,0x00,0x08,0x40, // 202 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x0A,0x41,0x00,0x08,0x41,0x00,0x0A,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x40, // 203 + 0x01,0x00,0x00,0xFA,0x7F, // 204 + 0x00,0x00,0x00,0xFA,0x7F,0x00,0x01, // 205 + 0x02,0x00,0x00,0xF9,0x7F,0x00,0x01,0x00,0x00,0x02, // 206 + 0x02,0x00,0x00,0xF8,0x7F,0x00,0x02, // 207 + 0x00,0x02,0x00,0xF8,0x7F,0x00,0x08,0x42,0x00,0x08,0x42,0x00,0x08,0x42,0x00,0x08,0x42,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 208 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x10,0x00,0x00,0x60,0x00,0x00,0x82,0x00,0x00,0x01,0x03,0x00,0x02,0x04,0x00,0x01,0x18,0x00,0x00,0x20,0x00,0xF8,0x7F, // 209 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x09,0x40,0x00,0x0A,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 210 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x0A,0x40,0x00,0x09,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 211 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x0A,0x40,0x00,0x09,0x40,0x00,0x09,0x40,0x00,0x0A,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 212 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x0A,0x40,0x00,0x09,0x40,0x00,0x0A,0x40,0x00,0x09,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 213 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x0A,0x40,0x00,0x08,0x40,0x00,0x0A,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 214 + 0x00,0x00,0x00,0x40,0x10,0x00,0x80,0x08,0x00,0x00,0x05,0x00,0x00,0x07,0x00,0x00,0x05,0x00,0x80,0x08,0x00,0x40,0x10, // 215 + 0x00,0x00,0x00,0xC0,0x4F,0x00,0x20,0x30,0x00,0x10,0x30,0x00,0x08,0x4C,0x00,0x08,0x42,0x00,0x08,0x41,0x00,0xC8,0x40,0x00,0x30,0x20,0x00,0x30,0x10,0x00,0xC8,0x0F, // 216 + 0x00,0x00,0x00,0xF8,0x1F,0x00,0x00,0x20,0x00,0x00,0x40,0x00,0x01,0x40,0x00,0x02,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xF8,0x1F, // 217 + 0x00,0x00,0x00,0xF8,0x1F,0x00,0x00,0x20,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x02,0x40,0x00,0x01,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xF8,0x1F, // 218 + 0x00,0x00,0x00,0xF8,0x1F,0x00,0x00,0x20,0x00,0x00,0x40,0x00,0x02,0x40,0x00,0x01,0x40,0x00,0x01,0x40,0x00,0x02,0x40,0x00,0x00,0x20,0x00,0xF8,0x1F, // 219 + 0x00,0x00,0x00,0xF8,0x1F,0x00,0x00,0x20,0x00,0x00,0x40,0x00,0x02,0x40,0x00,0x00,0x40,0x00,0x02,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xF8,0x1F, // 220 + 0x08,0x00,0x00,0x30,0x00,0x00,0x40,0x00,0x00,0x80,0x01,0x00,0x02,0x7E,0x00,0x81,0x01,0x00,0x40,0x00,0x00,0x30,0x00,0x00,0x08, // 221 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x20,0x10,0x00,0x20,0x10,0x00,0x20,0x10,0x00,0x20,0x10,0x00,0x20,0x10,0x00,0x20,0x10,0x00,0x40,0x08,0x00,0x80,0x07, // 222 + 0x00,0x00,0x00,0xE0,0x7F,0x00,0x10,0x00,0x00,0x08,0x20,0x00,0x88,0x43,0x00,0x70,0x42,0x00,0x00,0x44,0x00,0x00,0x38, // 223 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x40,0x44,0x00,0x48,0x44,0x00,0x50,0x42,0x00,0x40,0x22,0x00,0x80,0x7F, // 224 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x40,0x44,0x00,0x50,0x44,0x00,0x48,0x42,0x00,0x40,0x22,0x00,0x80,0x7F, // 225 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x50,0x44,0x00,0x48,0x44,0x00,0x48,0x42,0x00,0x50,0x22,0x00,0x80,0x7F, // 226 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x50,0x44,0x00,0x48,0x44,0x00,0x50,0x42,0x00,0x48,0x22,0x00,0x80,0x7F, // 227 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x50,0x44,0x00,0x40,0x44,0x00,0x50,0x42,0x00,0x40,0x22,0x00,0x80,0x7F, // 228 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x5C,0x44,0x00,0x54,0x44,0x00,0x5C,0x42,0x00,0x40,0x22,0x00,0x80,0x7F, // 229 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x42,0x00,0x40,0x22,0x00,0x80,0x3F,0x00,0x80,0x24,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x80,0x24,0x00,0x00,0x17, // 230 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x02,0x40,0xC0,0x02,0x40,0x40,0x03,0x80,0x20, // 231 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x24,0x00,0x48,0x44,0x00,0x50,0x44,0x00,0x40,0x44,0x00,0x80,0x24,0x00,0x00,0x17, // 232 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x24,0x00,0x40,0x44,0x00,0x50,0x44,0x00,0x48,0x44,0x00,0x80,0x24,0x00,0x00,0x17, // 233 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x24,0x00,0x50,0x44,0x00,0x48,0x44,0x00,0x48,0x44,0x00,0x90,0x24,0x00,0x00,0x17, // 234 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x24,0x00,0x50,0x44,0x00,0x40,0x44,0x00,0x50,0x44,0x00,0x80,0x24,0x00,0x00,0x17, // 235 + 0x08,0x00,0x00,0xD0,0x7F, // 236 + 0x00,0x00,0x00,0xD0,0x7F,0x00,0x08, // 237 + 0x10,0x00,0x00,0xC8,0x7F,0x00,0x08,0x00,0x00,0x10, // 238 + 0x10,0x00,0x00,0xC0,0x7F,0x00,0x10, // 239 + 0x00,0x00,0x00,0x00,0x1F,0x00,0xA0,0x20,0x00,0x68,0x40,0x00,0x58,0x40,0x00,0x70,0x40,0x00,0xE8,0x20,0x00,0x00,0x1F, // 240 + 0x00,0x00,0x00,0xC0,0x7F,0x00,0x90,0x00,0x00,0x48,0x00,0x00,0x50,0x00,0x00,0x48,0x00,0x00,0x80,0x7F, // 241 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x48,0x40,0x00,0x50,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 242 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x50,0x40,0x00,0x48,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 243 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x50,0x40,0x00,0x48,0x40,0x00,0x48,0x40,0x00,0x90,0x20,0x00,0x00,0x1F, // 244 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x50,0x40,0x00,0x48,0x40,0x00,0x50,0x40,0x00,0x88,0x20,0x00,0x00,0x1F, // 245 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x50,0x40,0x00,0x40,0x40,0x00,0x50,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 246 + 0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x80,0x0A,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02, // 247 + 0x00,0x00,0x00,0x00,0x5F,0x00,0x80,0x30,0x00,0x40,0x48,0x00,0x40,0x44,0x00,0x40,0x42,0x00,0x80,0x21,0x00,0x40,0x1F, // 248 + 0x00,0x00,0x00,0xC0,0x3F,0x00,0x00,0x40,0x00,0x08,0x40,0x00,0x10,0x40,0x00,0x00,0x20,0x00,0xC0,0x7F, // 249 + 0x00,0x00,0x00,0xC0,0x3F,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x10,0x40,0x00,0x08,0x20,0x00,0xC0,0x7F, // 250 + 0x00,0x00,0x00,0xC0,0x3F,0x00,0x10,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0xC0,0x7F, // 251 + 0x00,0x00,0x00,0xD0,0x3F,0x00,0x00,0x40,0x00,0x10,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xC0,0x7F, // 252 + 0xC0,0x01,0x00,0x00,0x06,0x02,0x00,0x38,0x02,0x10,0xE0,0x01,0x08,0x38,0x00,0x00,0x07,0x00,0xC0, // 253 + 0x00,0x00,0x00,0xF8,0xFF,0x03,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 254 + 0xC0,0x01,0x00,0x00,0x06,0x02,0x10,0x38,0x02,0x00,0xE0,0x01,0x10,0x38,0x00,0x00,0x07,0x00,0xC0 // 255 +}; +const uint8_t ArialMT_Plain_24[] PROGMEM = { + 0x18, // Width: 24 + 0x1C, // Height: 28 + 0x20, // First Char: 32 + 0xE0, // Numbers of Chars: 224 + + // Jump Table: + 0xFF, 0xFF, 0x00, 0x07, // 32:65535 + 0x00, 0x00, 0x13, 0x07, // 33:0 + 0x00, 0x13, 0x1A, 0x09, // 34:19 + 0x00, 0x2D, 0x33, 0x0D, // 35:45 + 0x00, 0x60, 0x2F, 0x0D, // 36:96 + 0x00, 0x8F, 0x4F, 0x15, // 37:143 + 0x00, 0xDE, 0x3B, 0x10, // 38:222 + 0x01, 0x19, 0x0A, 0x05, // 39:281 + 0x01, 0x23, 0x1C, 0x08, // 40:291 + 0x01, 0x3F, 0x1B, 0x08, // 41:319 + 0x01, 0x5A, 0x21, 0x09, // 42:346 + 0x01, 0x7B, 0x32, 0x0E, // 43:379 + 0x01, 0xAD, 0x10, 0x07, // 44:429 + 0x01, 0xBD, 0x1B, 0x08, // 45:445 + 0x01, 0xD8, 0x0F, 0x07, // 46:472 + 0x01, 0xE7, 0x19, 0x07, // 47:487 + 0x02, 0x00, 0x2F, 0x0D, // 48:512 + 0x02, 0x2F, 0x23, 0x0D, // 49:559 + 0x02, 0x52, 0x2F, 0x0D, // 50:594 + 0x02, 0x81, 0x2F, 0x0D, // 51:641 + 0x02, 0xB0, 0x2F, 0x0D, // 52:688 + 0x02, 0xDF, 0x2F, 0x0D, // 53:735 + 0x03, 0x0E, 0x2F, 0x0D, // 54:782 + 0x03, 0x3D, 0x2D, 0x0D, // 55:829 + 0x03, 0x6A, 0x2F, 0x0D, // 56:874 + 0x03, 0x99, 0x2F, 0x0D, // 57:921 + 0x03, 0xC8, 0x0F, 0x07, // 58:968 + 0x03, 0xD7, 0x10, 0x07, // 59:983 + 0x03, 0xE7, 0x2F, 0x0E, // 60:999 + 0x04, 0x16, 0x2F, 0x0E, // 61:1046 + 0x04, 0x45, 0x2E, 0x0E, // 62:1093 + 0x04, 0x73, 0x2E, 0x0D, // 63:1139 + 0x04, 0xA1, 0x5B, 0x18, // 64:1185 + 0x04, 0xFC, 0x3B, 0x10, // 65:1276 + 0x05, 0x37, 0x3B, 0x10, // 66:1335 + 0x05, 0x72, 0x3F, 0x11, // 67:1394 + 0x05, 0xB1, 0x3F, 0x11, // 68:1457 + 0x05, 0xF0, 0x3B, 0x10, // 69:1520 + 0x06, 0x2B, 0x35, 0x0F, // 70:1579 + 0x06, 0x60, 0x43, 0x13, // 71:1632 + 0x06, 0xA3, 0x3B, 0x11, // 72:1699 + 0x06, 0xDE, 0x0F, 0x07, // 73:1758 + 0x06, 0xED, 0x27, 0x0C, // 74:1773 + 0x07, 0x14, 0x3F, 0x10, // 75:1812 + 0x07, 0x53, 0x2F, 0x0D, // 76:1875 + 0x07, 0x82, 0x43, 0x14, // 77:1922 + 0x07, 0xC5, 0x3B, 0x11, // 78:1989 + 0x08, 0x00, 0x47, 0x13, // 79:2048 + 0x08, 0x47, 0x3A, 0x10, // 80:2119 + 0x08, 0x81, 0x47, 0x13, // 81:2177 + 0x08, 0xC8, 0x3F, 0x11, // 82:2248 + 0x09, 0x07, 0x3B, 0x10, // 83:2311 + 0x09, 0x42, 0x35, 0x0F, // 84:2370 + 0x09, 0x77, 0x3B, 0x11, // 85:2423 + 0x09, 0xB2, 0x39, 0x10, // 86:2482 + 0x09, 0xEB, 0x59, 0x17, // 87:2539 + 0x0A, 0x44, 0x3B, 0x10, // 88:2628 + 0x0A, 0x7F, 0x3D, 0x10, // 89:2687 + 0x0A, 0xBC, 0x37, 0x0F, // 90:2748 + 0x0A, 0xF3, 0x14, 0x07, // 91:2803 + 0x0B, 0x07, 0x1B, 0x07, // 92:2823 + 0x0B, 0x22, 0x18, 0x07, // 93:2850 + 0x0B, 0x3A, 0x2A, 0x0B, // 94:2874 + 0x0B, 0x64, 0x34, 0x0D, // 95:2916 + 0x0B, 0x98, 0x11, 0x08, // 96:2968 + 0x0B, 0xA9, 0x2F, 0x0D, // 97:2985 + 0x0B, 0xD8, 0x33, 0x0D, // 98:3032 + 0x0C, 0x0B, 0x2B, 0x0C, // 99:3083 + 0x0C, 0x36, 0x2F, 0x0D, // 100:3126 + 0x0C, 0x65, 0x2F, 0x0D, // 101:3173 + 0x0C, 0x94, 0x1A, 0x07, // 102:3220 + 0x0C, 0xAE, 0x2F, 0x0D, // 103:3246 + 0x0C, 0xDD, 0x2F, 0x0D, // 104:3293 + 0x0D, 0x0C, 0x0F, 0x05, // 105:3340 + 0x0D, 0x1B, 0x10, 0x05, // 106:3355 + 0x0D, 0x2B, 0x2F, 0x0C, // 107:3371 + 0x0D, 0x5A, 0x0F, 0x05, // 108:3418 + 0x0D, 0x69, 0x47, 0x14, // 109:3433 + 0x0D, 0xB0, 0x2F, 0x0D, // 110:3504 + 0x0D, 0xDF, 0x2F, 0x0D, // 111:3551 + 0x0E, 0x0E, 0x33, 0x0D, // 112:3598 + 0x0E, 0x41, 0x30, 0x0D, // 113:3649 + 0x0E, 0x71, 0x1E, 0x08, // 114:3697 + 0x0E, 0x8F, 0x2B, 0x0C, // 115:3727 + 0x0E, 0xBA, 0x1B, 0x07, // 116:3770 + 0x0E, 0xD5, 0x2F, 0x0D, // 117:3797 + 0x0F, 0x04, 0x2A, 0x0C, // 118:3844 + 0x0F, 0x2E, 0x42, 0x11, // 119:3886 + 0x0F, 0x70, 0x2B, 0x0C, // 120:3952 + 0x0F, 0x9B, 0x2A, 0x0C, // 121:3995 + 0x0F, 0xC5, 0x2B, 0x0C, // 122:4037 + 0x0F, 0xF0, 0x1C, 0x08, // 123:4080 + 0x10, 0x0C, 0x10, 0x06, // 124:4108 + 0x10, 0x1C, 0x1B, 0x08, // 125:4124 + 0x10, 0x37, 0x32, 0x0E, // 126:4151 + 0xFF, 0xFF, 0x00, 0x00, // 127:65535 + 0xFF, 0xFF, 0x00, 0x18, // 128:65535 + 0xFF, 0xFF, 0x00, 0x18, // 129:65535 + 0xFF, 0xFF, 0x00, 0x18, // 130:65535 + 0xFF, 0xFF, 0x00, 0x18, // 131:65535 + 0xFF, 0xFF, 0x00, 0x18, // 132:65535 + 0xFF, 0xFF, 0x00, 0x18, // 133:65535 + 0xFF, 0xFF, 0x00, 0x18, // 134:65535 + 0xFF, 0xFF, 0x00, 0x18, // 135:65535 + 0xFF, 0xFF, 0x00, 0x18, // 136:65535 + 0xFF, 0xFF, 0x00, 0x18, // 137:65535 + 0xFF, 0xFF, 0x00, 0x18, // 138:65535 + 0xFF, 0xFF, 0x00, 0x18, // 139:65535 + 0xFF, 0xFF, 0x00, 0x18, // 140:65535 + 0xFF, 0xFF, 0x00, 0x18, // 141:65535 + 0xFF, 0xFF, 0x00, 0x18, // 142:65535 + 0xFF, 0xFF, 0x00, 0x18, // 143:65535 + 0xFF, 0xFF, 0x00, 0x18, // 144:65535 + 0xFF, 0xFF, 0x00, 0x18, // 145:65535 + 0xFF, 0xFF, 0x00, 0x18, // 146:65535 + 0xFF, 0xFF, 0x00, 0x18, // 147:65535 + 0xFF, 0xFF, 0x00, 0x18, // 148:65535 + 0xFF, 0xFF, 0x00, 0x18, // 149:65535 + 0xFF, 0xFF, 0x00, 0x18, // 150:65535 + 0xFF, 0xFF, 0x00, 0x18, // 151:65535 + 0xFF, 0xFF, 0x00, 0x18, // 152:65535 + 0xFF, 0xFF, 0x00, 0x18, // 153:65535 + 0xFF, 0xFF, 0x00, 0x18, // 154:65535 + 0xFF, 0xFF, 0x00, 0x18, // 155:65535 + 0xFF, 0xFF, 0x00, 0x18, // 156:65535 + 0xFF, 0xFF, 0x00, 0x18, // 157:65535 + 0xFF, 0xFF, 0x00, 0x18, // 158:65535 + 0xFF, 0xFF, 0x00, 0x18, // 159:65535 + 0xFF, 0xFF, 0x00, 0x07, // 160:65535 + 0x10, 0x69, 0x14, 0x08, // 161:4201 + 0x10, 0x7D, 0x2B, 0x0D, // 162:4221 + 0x10, 0xA8, 0x2F, 0x0D, // 163:4264 + 0x10, 0xD7, 0x33, 0x0D, // 164:4311 + 0x11, 0x0A, 0x31, 0x0D, // 165:4362 + 0x11, 0x3B, 0x10, 0x06, // 166:4411 + 0x11, 0x4B, 0x2F, 0x0D, // 167:4427 + 0x11, 0x7A, 0x19, 0x08, // 168:4474 + 0x11, 0x93, 0x46, 0x12, // 169:4499 + 0x11, 0xD9, 0x1A, 0x09, // 170:4569 + 0x11, 0xF3, 0x27, 0x0D, // 171:4595 + 0x12, 0x1A, 0x2F, 0x0E, // 172:4634 + 0x12, 0x49, 0x1B, 0x08, // 173:4681 + 0x12, 0x64, 0x46, 0x12, // 174:4708 + 0x12, 0xAA, 0x31, 0x0D, // 175:4778 + 0x12, 0xDB, 0x1E, 0x0A, // 176:4827 + 0x12, 0xF9, 0x33, 0x0D, // 177:4857 + 0x13, 0x2C, 0x1A, 0x08, // 178:4908 + 0x13, 0x46, 0x1A, 0x08, // 179:4934 + 0x13, 0x60, 0x19, 0x08, // 180:4960 + 0x13, 0x79, 0x2F, 0x0E, // 181:4985 + 0x13, 0xA8, 0x31, 0x0D, // 182:5032 + 0x13, 0xD9, 0x12, 0x08, // 183:5081 + 0x13, 0xEB, 0x18, 0x08, // 184:5099 + 0x14, 0x03, 0x16, 0x08, // 185:5123 + 0x14, 0x19, 0x1E, 0x09, // 186:5145 + 0x14, 0x37, 0x2E, 0x0D, // 187:5175 + 0x14, 0x65, 0x4F, 0x14, // 188:5221 + 0x14, 0xB4, 0x4B, 0x14, // 189:5300 + 0x14, 0xFF, 0x4B, 0x14, // 190:5375 + 0x15, 0x4A, 0x33, 0x0F, // 191:5450 + 0x15, 0x7D, 0x3B, 0x10, // 192:5501 + 0x15, 0xB8, 0x3B, 0x10, // 193:5560 + 0x15, 0xF3, 0x3B, 0x10, // 194:5619 + 0x16, 0x2E, 0x3B, 0x10, // 195:5678 + 0x16, 0x69, 0x3B, 0x10, // 196:5737 + 0x16, 0xA4, 0x3B, 0x10, // 197:5796 + 0x16, 0xDF, 0x5B, 0x18, // 198:5855 + 0x17, 0x3A, 0x3F, 0x11, // 199:5946 + 0x17, 0x79, 0x3B, 0x10, // 200:6009 + 0x17, 0xB4, 0x3B, 0x10, // 201:6068 + 0x17, 0xEF, 0x3B, 0x10, // 202:6127 + 0x18, 0x2A, 0x3B, 0x10, // 203:6186 + 0x18, 0x65, 0x11, 0x07, // 204:6245 + 0x18, 0x76, 0x11, 0x07, // 205:6262 + 0x18, 0x87, 0x15, 0x07, // 206:6279 + 0x18, 0x9C, 0x15, 0x07, // 207:6300 + 0x18, 0xB1, 0x3F, 0x11, // 208:6321 + 0x18, 0xF0, 0x3B, 0x11, // 209:6384 + 0x19, 0x2B, 0x47, 0x13, // 210:6443 + 0x19, 0x72, 0x47, 0x13, // 211:6514 + 0x19, 0xB9, 0x47, 0x13, // 212:6585 + 0x1A, 0x00, 0x47, 0x13, // 213:6656 + 0x1A, 0x47, 0x47, 0x13, // 214:6727 + 0x1A, 0x8E, 0x2B, 0x0E, // 215:6798 + 0x1A, 0xB9, 0x47, 0x13, // 216:6841 + 0x1B, 0x00, 0x3B, 0x11, // 217:6912 + 0x1B, 0x3B, 0x3B, 0x11, // 218:6971 + 0x1B, 0x76, 0x3B, 0x11, // 219:7030 + 0x1B, 0xB1, 0x3B, 0x11, // 220:7089 + 0x1B, 0xEC, 0x3D, 0x10, // 221:7148 + 0x1C, 0x29, 0x3A, 0x10, // 222:7209 + 0x1C, 0x63, 0x37, 0x0F, // 223:7267 + 0x1C, 0x9A, 0x2F, 0x0D, // 224:7322 + 0x1C, 0xC9, 0x2F, 0x0D, // 225:7369 + 0x1C, 0xF8, 0x2F, 0x0D, // 226:7416 + 0x1D, 0x27, 0x2F, 0x0D, // 227:7463 + 0x1D, 0x56, 0x2F, 0x0D, // 228:7510 + 0x1D, 0x85, 0x2F, 0x0D, // 229:7557 + 0x1D, 0xB4, 0x53, 0x15, // 230:7604 + 0x1E, 0x07, 0x2B, 0x0C, // 231:7687 + 0x1E, 0x32, 0x2F, 0x0D, // 232:7730 + 0x1E, 0x61, 0x2F, 0x0D, // 233:7777 + 0x1E, 0x90, 0x2F, 0x0D, // 234:7824 + 0x1E, 0xBF, 0x2F, 0x0D, // 235:7871 + 0x1E, 0xEE, 0x11, 0x07, // 236:7918 + 0x1E, 0xFF, 0x11, 0x07, // 237:7935 + 0x1F, 0x10, 0x15, 0x07, // 238:7952 + 0x1F, 0x25, 0x15, 0x07, // 239:7973 + 0x1F, 0x3A, 0x2F, 0x0D, // 240:7994 + 0x1F, 0x69, 0x2F, 0x0D, // 241:8041 + 0x1F, 0x98, 0x2F, 0x0D, // 242:8088 + 0x1F, 0xC7, 0x2F, 0x0D, // 243:8135 + 0x1F, 0xF6, 0x2F, 0x0D, // 244:8182 + 0x20, 0x25, 0x2F, 0x0D, // 245:8229 + 0x20, 0x54, 0x2F, 0x0D, // 246:8276 + 0x20, 0x83, 0x32, 0x0D, // 247:8323 + 0x20, 0xB5, 0x33, 0x0F, // 248:8373 + 0x20, 0xE8, 0x2F, 0x0D, // 249:8424 + 0x21, 0x17, 0x2F, 0x0D, // 250:8471 + 0x21, 0x46, 0x2F, 0x0D, // 251:8518 + 0x21, 0x75, 0x2F, 0x0D, // 252:8565 + 0x21, 0xA4, 0x2A, 0x0C, // 253:8612 + 0x21, 0xCE, 0x2F, 0x0D, // 254:8654 + 0x21, 0xFD, 0x2A, 0x0C, // 255:8701 + + // Font Data: + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x33,0x00,0xE0,0xFF,0x33, // 33 + 0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xE0,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xE0,0x07, // 34 + 0x00,0x0C,0x03,0x00,0x00,0x0C,0x33,0x00,0x00,0x0C,0x3F,0x00,0x00,0xFC,0x0F,0x00,0x80,0xFF,0x03,0x00,0xE0,0x0F,0x03,0x00,0x60,0x0C,0x33,0x00,0x00,0x0C,0x3F,0x00,0x00,0xFC,0x0F,0x00,0x80,0xFF,0x03,0x00,0xE0,0x0F,0x03,0x00,0x60,0x0C,0x03,0x00,0x00,0x0C,0x03, // 35 + 0x00,0x00,0x00,0x00,0x80,0x07,0x06,0x00,0xC0,0x0F,0x1E,0x00,0xC0,0x18,0x1C,0x00,0x60,0x18,0x38,0x00,0x60,0x30,0x30,0x00,0xF0,0xFF,0xFF,0x00,0x60,0x30,0x30,0x00,0x60,0x60,0x38,0x00,0xC0,0x60,0x18,0x00,0xC0,0xC1,0x1F,0x00,0x00,0x81,0x07, // 36 + 0x00,0x00,0x00,0x00,0x80,0x0F,0x00,0x00,0xC0,0x1F,0x00,0x00,0x60,0x30,0x00,0x00,0x20,0x20,0x00,0x00,0x20,0x20,0x20,0x00,0x60,0x30,0x38,0x00,0xC0,0x1F,0x1E,0x00,0x80,0x8F,0x0F,0x00,0x00,0xC0,0x03,0x00,0x00,0xF0,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0x8F,0x0F,0x00,0xC0,0xC3,0x1F,0x00,0xE0,0x60,0x30,0x00,0x20,0x20,0x20,0x00,0x00,0x20,0x20,0x00,0x00,0x60,0x30,0x00,0x00,0xC0,0x1F,0x00,0x00,0x80,0x0F, // 37 + 0x00,0x00,0x00,0x00,0x00,0x80,0x07,0x00,0x00,0xC0,0x0F,0x00,0x80,0xE3,0x1C,0x00,0xC0,0x77,0x38,0x00,0xE0,0x3C,0x30,0x00,0x60,0x38,0x30,0x00,0x60,0x78,0x30,0x00,0xE0,0xEC,0x38,0x00,0xC0,0x8F,0x1B,0x00,0x80,0x03,0x1F,0x00,0x00,0x00,0x0F,0x00,0x00,0xC0,0x1F,0x00,0x00,0xC0,0x38,0x00,0x00,0x00,0x10, // 38 + 0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xE0,0x07, // 39 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x0F,0x00,0x00,0xFE,0x7F,0x00,0x80,0x0F,0xF0,0x01,0xC0,0x01,0x80,0x03,0x60,0x00,0x00,0x06,0x20,0x00,0x00,0x04, // 40 + 0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x04,0x60,0x00,0x00,0x06,0xC0,0x01,0x80,0x03,0x80,0x0F,0xF0,0x01,0x00,0xFE,0x7F,0x00,0x00,0xF0,0x0F, // 41 + 0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x04,0x00,0x00,0x80,0x0F,0x00,0x00,0xE0,0x03,0x00,0x00,0xE0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x80,0x04,0x00,0x00,0x80, // 42 + 0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xFF,0x0F,0x00,0x00,0xFF,0x0F,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60, // 43 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x03,0x00,0x00,0xF0,0x01, // 44 + 0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01, // 45 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30, // 46 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0xE0,0x0F,0x00,0x00,0xFC,0x01,0x00,0x80,0x3F,0x00,0x00,0xE0,0x03,0x00,0x00,0x60, // 47 + 0x00,0x00,0x00,0x00,0x00,0xFE,0x03,0x00,0x80,0xFF,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xE0,0x00,0x38,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x38,0x00,0xC0,0x01,0x1C,0x00,0x80,0xFF,0x0F,0x00,0x00,0xFE,0x03, // 48 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x03,0x00,0x00,0x80,0x01,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 49 + 0x00,0x00,0x00,0x00,0x00,0x03,0x30,0x00,0xC0,0x03,0x38,0x00,0xC0,0x00,0x3C,0x00,0x60,0x00,0x36,0x00,0x60,0x00,0x33,0x00,0x60,0x80,0x31,0x00,0x60,0xC0,0x30,0x00,0x60,0x60,0x30,0x00,0xC0,0x30,0x30,0x00,0xC0,0x1F,0x30,0x00,0x00,0x0F,0x30, // 50 + 0x00,0x00,0x00,0x00,0x00,0x01,0x06,0x00,0xC0,0x01,0x0E,0x00,0xC0,0x00,0x1C,0x00,0x60,0x00,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0xC0,0x38,0x30,0x00,0xC0,0x6F,0x18,0x00,0x80,0xC7,0x0F,0x00,0x00,0x80,0x07, // 51 + 0x00,0x00,0x00,0x00,0x00,0x80,0x03,0x00,0x00,0xC0,0x03,0x00,0x00,0xF0,0x03,0x00,0x00,0x3C,0x03,0x00,0x00,0x0E,0x03,0x00,0x80,0x07,0x03,0x00,0xC0,0x01,0x03,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x03, // 52 + 0x00,0x00,0x00,0x00,0x00,0x30,0x06,0x00,0x80,0x3F,0x0E,0x00,0xE0,0x1F,0x18,0x00,0x60,0x08,0x30,0x00,0x60,0x0C,0x30,0x00,0x60,0x0C,0x30,0x00,0x60,0x0C,0x30,0x00,0x60,0x0C,0x30,0x00,0x60,0x18,0x1C,0x00,0x60,0xF0,0x0F,0x00,0x00,0xE0,0x03, // 53 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x03,0x00,0x80,0xFF,0x0F,0x00,0xC0,0x63,0x1C,0x00,0xC0,0x30,0x38,0x00,0x60,0x18,0x30,0x00,0x60,0x18,0x30,0x00,0x60,0x18,0x30,0x00,0x60,0x18,0x30,0x00,0xE0,0x30,0x18,0x00,0xC0,0xF1,0x0F,0x00,0x80,0xC1,0x07, // 54 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x3C,0x00,0x60,0x80,0x3F,0x00,0x60,0xE0,0x03,0x00,0x60,0x78,0x00,0x00,0x60,0x0E,0x00,0x00,0x60,0x03,0x00,0x00,0xE0,0x01,0x00,0x00,0x60, // 55 + 0x00,0x00,0x00,0x00,0x00,0x80,0x07,0x00,0x80,0xC7,0x1F,0x00,0xC0,0x6F,0x18,0x00,0xE0,0x38,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0xE0,0x38,0x30,0x00,0xC0,0x6F,0x18,0x00,0x80,0xC7,0x1F,0x00,0x00,0x80,0x07, // 56 + 0x00,0x00,0x00,0x00,0x00,0x1F,0x0C,0x00,0x80,0x7F,0x1C,0x00,0xC0,0x61,0x38,0x00,0x60,0xC0,0x30,0x00,0x60,0xC0,0x30,0x00,0x60,0xC0,0x30,0x00,0x60,0xC0,0x30,0x00,0x60,0x60,0x18,0x00,0xC0,0x31,0x1E,0x00,0x80,0xFF,0x0F,0x00,0x00,0xFE,0x01, // 57 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30, // 58 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x30,0x03,0x00,0x06,0xF0,0x01, // 59 + 0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x50,0x00,0x00,0x00,0xD8,0x00,0x00,0x00,0xD8,0x00,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x04,0x01,0x00,0x00,0x06,0x03,0x00,0x00,0x06,0x03,0x00,0x00,0x03,0x06, // 60 + 0x00,0x00,0x00,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01, // 61 + 0x00,0x00,0x00,0x00,0x00,0x03,0x06,0x00,0x00,0x06,0x03,0x00,0x00,0x06,0x03,0x00,0x00,0x04,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0xD8,0x00,0x00,0x00,0xD8,0x00,0x00,0x00,0x50,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x20, // 62 + 0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x80,0x03,0x00,0x00,0xC0,0x01,0x00,0x00,0xE0,0x00,0x00,0x00,0x60,0x80,0x33,0x00,0x60,0xC0,0x33,0x00,0x60,0xE0,0x00,0x00,0x60,0x30,0x00,0x00,0xC0,0x38,0x00,0x00,0xC0,0x1F,0x00,0x00,0x00,0x07, // 63 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x0F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x1E,0xF0,0x00,0x00,0x07,0xC0,0x01,0x80,0xC3,0x87,0x01,0xC0,0xF1,0x9F,0x03,0xC0,0x38,0x18,0x03,0xC0,0x0C,0x30,0x03,0x60,0x0E,0x30,0x06,0x60,0x06,0x30,0x06,0x60,0x06,0x18,0x06,0x60,0x06,0x0C,0x06,0x60,0x0C,0x1E,0x06,0x60,0xF8,0x3F,0x06,0xE0,0xFE,0x31,0x06,0xC0,0x0E,0x30,0x06,0xC0,0x01,0x18,0x03,0x80,0x03,0x1C,0x03,0x00,0x07,0x8F,0x01,0x00,0xFE,0x87,0x01,0x00,0xF8,0xC1,0x00,0x00,0x00,0x40, // 64 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x80,0x8F,0x01,0x00,0xE0,0x83,0x01,0x00,0x60,0x80,0x01,0x00,0xE0,0x83,0x01,0x00,0x80,0x8F,0x01,0x00,0x00,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 65 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0xC0,0x78,0x30,0x00,0xC0,0xFF,0x18,0x00,0x80,0xC7,0x1F,0x00,0x00,0x80,0x07, // 66 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x03,0x0F,0x00,0x00,0x02,0x03, // 67 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x03,0x0E,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 68 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 69 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60, // 70 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x18,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x60,0x30,0x00,0x60,0x60,0x30,0x00,0xE0,0x60,0x38,0x00,0xC0,0x60,0x18,0x00,0xC0,0x61,0x18,0x00,0x80,0xE3,0x0F,0x00,0x00,0xE2,0x0F, // 71 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 72 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 73 + 0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x38,0x00,0xE0,0xFF,0x1F,0x00,0xE0,0xFF,0x0F, // 74 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0xE0,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x7C,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0xE7,0x01,0x00,0x80,0x83,0x07,0x00,0xC0,0x01,0x0F,0x00,0xE0,0x00,0x1E,0x00,0x60,0x00,0x38,0x00,0x20,0x00,0x30,0x00,0x00,0x00,0x20, // 75 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30, // 76 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0x01,0x00,0x00,0xC0,0x0F,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x3F,0x00,0x00,0xE0,0x07,0x00,0x00,0xFE,0x00,0x00,0xC0,0x0F,0x00,0x00,0xE0,0x01,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 77 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0xC0,0x01,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0xE0,0x01,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x0F,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 78 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x38,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 79 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0xC0,0x30,0x00,0x00,0xC0,0x3F,0x00,0x00,0x00,0x0F, // 80 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x0C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x18,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x36,0x00,0x60,0x00,0x36,0x00,0xE0,0x00,0x3C,0x00,0xC0,0x00,0x1C,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x3F,0x00,0x00,0xFF,0x77,0x00,0x00,0xFC,0x61, // 81 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x70,0x00,0x00,0x60,0xF0,0x00,0x00,0x60,0xF0,0x03,0x00,0x60,0xB0,0x07,0x00,0xE0,0x18,0x1F,0x00,0xC0,0x1F,0x3C,0x00,0x80,0x0F,0x30,0x00,0x00,0x00,0x20, // 82 + 0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x07,0x0F,0x00,0xC0,0x1F,0x1C,0x00,0xC0,0x18,0x18,0x00,0x60,0x38,0x38,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x70,0x30,0x00,0xC0,0x60,0x18,0x00,0xC0,0xE1,0x18,0x00,0x80,0xC3,0x0F,0x00,0x00,0x83,0x07, // 83 + 0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60, // 84 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x03,0x00,0xE0,0xFF,0x0F,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x0F,0x00,0xE0,0xFF,0x03, // 85 + 0x20,0x00,0x00,0x00,0xE0,0x01,0x00,0x00,0xC0,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0xF8,0x01,0x00,0x00,0xC0,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x3E,0x00,0x00,0xC0,0x0F,0x00,0x00,0xF8,0x01,0x00,0x00,0x3E,0x00,0x00,0xC0,0x0F,0x00,0x00,0xE0,0x01,0x00,0x00,0x20, // 86 + 0x60,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0x80,0xFF,0x00,0x00,0x00,0xF8,0x0F,0x00,0x00,0x80,0x3F,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x3F,0x00,0x00,0xE0,0x0F,0x00,0x00,0xFC,0x01,0x00,0x80,0x1F,0x00,0x00,0xE0,0x03,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0x80,0x1F,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xE0,0x0F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x30,0x00,0x00,0x80,0x3F,0x00,0x00,0xF8,0x0F,0x00,0x80,0xFF,0x00,0x00,0xE0,0x07,0x00,0x00,0x60, // 87 + 0x00,0x00,0x20,0x00,0x20,0x00,0x30,0x00,0x60,0x00,0x3C,0x00,0xE0,0x01,0x1E,0x00,0xC0,0x83,0x07,0x00,0x00,0xCF,0x03,0x00,0x00,0xFE,0x01,0x00,0x00,0x38,0x00,0x00,0x00,0xFE,0x01,0x00,0x00,0xCF,0x03,0x00,0xC0,0x03,0x07,0x00,0xE0,0x01,0x1E,0x00,0x60,0x00,0x3C,0x00,0x20,0x00,0x30,0x00,0x00,0x00,0x20, // 88 + 0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xC0,0x01,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0xF0,0x3F,0x00,0x00,0xF0,0x3F,0x00,0x00,0x3C,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x07,0x00,0x00,0xC0,0x03,0x00,0x00,0xE0,0x01,0x00,0x00,0x60,0x00,0x00,0x00,0x20, // 89 + 0x00,0x00,0x30,0x00,0x60,0x00,0x38,0x00,0x60,0x00,0x3C,0x00,0x60,0x00,0x37,0x00,0x60,0x80,0x33,0x00,0x60,0xC0,0x31,0x00,0x60,0xE0,0x30,0x00,0x60,0x38,0x30,0x00,0x60,0x1C,0x30,0x00,0x60,0x0E,0x30,0x00,0x60,0x07,0x30,0x00,0xE0,0x01,0x30,0x00,0xE0,0x00,0x30,0x00,0x60,0x00,0x30, // 90 + 0x00,0x00,0x00,0x00,0xE0,0xFF,0xFF,0x07,0xE0,0xFF,0xFF,0x07,0x60,0x00,0x00,0x06,0x60,0x00,0x00,0x06, // 91 + 0x60,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0x80,0x3F,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xE0,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 92 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x06,0x60,0x00,0x00,0x06,0xE0,0xFF,0xFF,0x07,0xE0,0xFF,0xFF,0x07, // 93 + 0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1F,0x00,0x00,0xC0,0x07,0x00,0x00,0xE0,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0xC0,0x07,0x00,0x00,0x00,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x20, // 94 + 0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06, // 95 + 0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0x80, // 96 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0x00,0x8C,0x39,0x00,0x00,0x86,0x31,0x00,0x00,0x86,0x31,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x18,0x00,0x00,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 97 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x18,0x0C,0x00,0x00,0x0C,0x18,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xE0,0x03, // 98 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0x18,0x0C, // 99 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0C,0x18,0x00,0x00,0x18,0x0C,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 100 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0xDC,0x1C,0x00,0x00,0xCE,0x38,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xCE,0x38,0x00,0x00,0xDC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xF0,0x04, // 101 + 0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0xC0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x06,0x00,0x00,0x60,0x06,0x00,0x00,0x60,0x06, // 102 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x83,0x01,0x00,0xF8,0x8F,0x03,0x00,0x1C,0x1C,0x07,0x00,0x0E,0x38,0x06,0x00,0x06,0x30,0x06,0x00,0x06,0x30,0x06,0x00,0x06,0x30,0x06,0x00,0x0C,0x18,0x07,0x00,0x18,0x8C,0x03,0x00,0xFE,0xFF,0x01,0x00,0xFE,0xFF, // 103 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x18,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0xFC,0x3F,0x00,0x00,0xF8,0x3F, // 104 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0xFE,0x3F,0x00,0x60,0xFE,0x3F, // 105 + 0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x60,0xFE,0xFF,0x07,0x60,0xFE,0xFF,0x03, // 106 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0xC0,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0xF0,0x01,0x00,0x00,0x98,0x07,0x00,0x00,0x0C,0x0E,0x00,0x00,0x06,0x3C,0x00,0x00,0x02,0x30,0x00,0x00,0x00,0x20, // 107 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 108 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F,0x00,0x00,0x0C,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0xFC,0x3F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x0C,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0xFC,0x3F,0x00,0x00,0xF8,0x3F, // 109 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F,0x00,0x00,0x18,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0xFC,0x3F,0x00,0x00,0xF8,0x3F, // 110 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 111 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0xFF,0x07,0x00,0xFE,0xFF,0x07,0x00,0x18,0x0C,0x00,0x00,0x0C,0x18,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xE0,0x03, // 112 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0C,0x18,0x00,0x00,0x18,0x0C,0x00,0x00,0xFE,0xFF,0x07,0x00,0xFE,0xFF,0x07, // 113 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F,0x00,0x00,0x0C,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06, // 114 + 0x00,0x00,0x00,0x00,0x00,0x38,0x0C,0x00,0x00,0x7C,0x1C,0x00,0x00,0xEE,0x38,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x31,0x00,0x00,0xC6,0x31,0x00,0x00,0x8E,0x39,0x00,0x00,0x9C,0x1F,0x00,0x00,0x18,0x0F, // 115 + 0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0xC0,0xFF,0x1F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30, // 116 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x0F,0x00,0x00,0xFE,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x0C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 117 + 0x00,0x06,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0xC0,0x07,0x00,0x00,0x00,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1F,0x00,0x00,0xC0,0x07,0x00,0x00,0xF8,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x06, // 118 + 0x00,0x0E,0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x80,0x1F,0x00,0x00,0xE0,0x03,0x00,0x00,0x7C,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x7C,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0x80,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x80,0x1F,0x00,0x00,0xF0,0x03,0x00,0x00,0x7E,0x00,0x00,0x00,0x0E, // 119 + 0x00,0x02,0x20,0x00,0x00,0x06,0x30,0x00,0x00,0x1E,0x3C,0x00,0x00,0x38,0x0E,0x00,0x00,0xF0,0x07,0x00,0x00,0xC0,0x01,0x00,0x00,0xE0,0x07,0x00,0x00,0x38,0x0E,0x00,0x00,0x1C,0x3C,0x00,0x00,0x0E,0x30,0x00,0x00,0x02,0x20, // 120 + 0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x7E,0x00,0x06,0x00,0xF0,0x01,0x06,0x00,0x80,0x0F,0x07,0x00,0x00,0xFE,0x03,0x00,0x00,0xFC,0x00,0x00,0xC0,0x1F,0x00,0x00,0xF8,0x03,0x00,0x00,0x3E,0x00,0x00,0x00,0x06, // 121 + 0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x06,0x3C,0x00,0x00,0x06,0x3E,0x00,0x00,0x06,0x37,0x00,0x00,0xC6,0x33,0x00,0x00,0xE6,0x30,0x00,0x00,0x76,0x30,0x00,0x00,0x3E,0x30,0x00,0x00,0x1E,0x30,0x00,0x00,0x06,0x30, // 122 + 0x00,0x00,0x00,0x00,0x00,0x80,0x01,0x00,0x00,0xC0,0x03,0x00,0xC0,0x7F,0xFE,0x03,0xE0,0x3F,0xFC,0x07,0x60,0x00,0x00,0x06,0x60,0x00,0x00,0x06, // 123 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0xFF,0x0F,0xE0,0xFF,0xFF,0x0F, // 124 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x06,0x60,0x00,0x00,0x06,0xE0,0x3F,0xFC,0x07,0xC0,0x7F,0xFF,0x03,0x00,0xC0,0x03,0x00,0x00,0x80,0x01, // 125 + 0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0x60, // 126 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE6,0xFF,0x07,0x00,0xE6,0xFF,0x07, // 161 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x9C,0x07,0x00,0x0E,0x78,0x00,0x00,0x06,0x3F,0x00,0x00,0xF6,0x30,0x00,0x00,0x0E,0x30,0x00,0xE0,0x0D,0x1C,0x00,0x00,0x1C,0x0E,0x00,0x00,0x10,0x06, // 162 + 0x00,0x60,0x10,0x00,0x00,0x60,0x38,0x00,0x00,0x7F,0x1C,0x00,0xC0,0xFF,0x1F,0x00,0xE0,0xE0,0x19,0x00,0x60,0x60,0x18,0x00,0x60,0x60,0x18,0x00,0x60,0x60,0x30,0x00,0xE0,0x00,0x30,0x00,0xC0,0x01,0x30,0x00,0x80,0x01,0x38,0x00,0x00,0x00,0x10, // 163 + 0x00,0x00,0x00,0x00,0x00,0x02,0x04,0x00,0x00,0xF7,0x0E,0x00,0x00,0xFE,0x07,0x00,0x00,0x0C,0x03,0x00,0x00,0x06,0x06,0x00,0x00,0x06,0x06,0x00,0x00,0x06,0x06,0x00,0x00,0x06,0x06,0x00,0x00,0x0C,0x03,0x00,0x00,0xFE,0x07,0x00,0x00,0xF7,0x0E,0x00,0x00,0x02,0x04, // 164 + 0xE0,0x60,0x06,0x00,0xC0,0x61,0x06,0x00,0x80,0x67,0x06,0x00,0x00,0x7E,0x06,0x00,0x00,0x7C,0x06,0x00,0x00,0xF0,0x3F,0x00,0x00,0xF0,0x3F,0x00,0x00,0x7C,0x06,0x00,0x00,0x7E,0x06,0x00,0x80,0x67,0x06,0x00,0xC0,0x61,0x06,0x00,0xE0,0x60,0x06,0x00,0x20, // 165 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x7F,0xF8,0x0F,0xE0,0x7F,0xF8,0x0F, // 166 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x00,0x00,0x80,0xF3,0xC1,0x00,0xC0,0x1F,0xC3,0x03,0xE0,0x0C,0x07,0x03,0x60,0x1C,0x06,0x06,0x60,0x18,0x0C,0x06,0x60,0x30,0x1C,0x06,0xE0,0x70,0x38,0x07,0xC0,0xE1,0xF4,0x03,0x80,0xC1,0xE7,0x01,0x00,0x80,0x03, // 167 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60, // 168 + 0x00,0xF8,0x00,0x00,0x00,0xFE,0x03,0x00,0x00,0x07,0x07,0x00,0x80,0x01,0x0C,0x00,0xC0,0x79,0x1C,0x00,0xC0,0xFE,0x19,0x00,0x60,0x86,0x31,0x00,0x60,0x03,0x33,0x00,0x60,0x03,0x33,0x00,0x60,0x03,0x33,0x00,0x60,0x03,0x33,0x00,0x60,0x87,0x33,0x00,0xC0,0x86,0x19,0x00,0xC0,0x85,0x1C,0x00,0x80,0x01,0x0C,0x00,0x00,0x07,0x07,0x00,0x00,0xFE,0x03,0x00,0x00,0xF8, // 169 + 0x00,0x00,0x00,0x00,0xC0,0x1C,0x00,0x00,0xE0,0x3E,0x00,0x00,0x60,0x32,0x00,0x00,0x60,0x32,0x00,0x00,0xE0,0x3F,0x00,0x00,0xC0,0x3F, // 170 + 0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0x78,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x84,0x10,0x00,0x00,0xE0,0x03,0x00,0x00,0x78,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x04,0x10, // 171 + 0x00,0x00,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFC,0x01, // 172 + 0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01, // 173 + 0x00,0xF8,0x00,0x00,0x00,0xFE,0x03,0x00,0x00,0x07,0x07,0x00,0x80,0x01,0x0C,0x00,0xC0,0x01,0x1C,0x00,0xC0,0xFE,0x1B,0x00,0x60,0xFE,0x33,0x00,0x60,0x66,0x30,0x00,0x60,0x66,0x30,0x00,0x60,0xE6,0x30,0x00,0x60,0xFE,0x31,0x00,0x60,0x3C,0x33,0x00,0xC0,0x00,0x1A,0x00,0xC0,0x01,0x1C,0x00,0x80,0x01,0x0C,0x00,0x00,0x07,0x07,0x00,0x00,0xFE,0x03,0x00,0x00,0xF8, // 174 + 0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C, // 175 + 0x00,0x00,0x00,0x00,0x80,0x03,0x00,0x00,0x40,0x04,0x00,0x00,0x20,0x08,0x00,0x00,0x20,0x08,0x00,0x00,0x20,0x08,0x00,0x00,0x40,0x04,0x00,0x00,0x80,0x03, // 176 + 0x00,0x00,0x00,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0xFF,0x3F,0x00,0x00,0xFF,0x3F,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30, // 177 + 0x40,0x20,0x00,0x00,0x60,0x30,0x00,0x00,0x20,0x38,0x00,0x00,0x20,0x2C,0x00,0x00,0x20,0x26,0x00,0x00,0xE0,0x23,0x00,0x00,0xC0,0x21, // 178 + 0x40,0x10,0x00,0x00,0x60,0x30,0x00,0x00,0x20,0x20,0x00,0x00,0x20,0x22,0x00,0x00,0x20,0x22,0x00,0x00,0xE0,0x3D,0x00,0x00,0xC0,0x1D, // 179 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x20, // 180 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0xFF,0x07,0x00,0xFE,0xFF,0x07,0x00,0x00,0x1C,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x1C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 181 + 0x00,0x0F,0x00,0x00,0xC0,0x3F,0x00,0x00,0xC0,0x3F,0x00,0x00,0xE0,0x7F,0x00,0x00,0xE0,0x7F,0x00,0x00,0xE0,0xFF,0xFF,0x07,0xE0,0xFF,0xFF,0x07,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0xFF,0xFF,0x07,0xE0,0xFF,0xFF,0x07,0x60,0x00,0x00,0x00,0x60, // 182 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60, // 183 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0xC0,0x02,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x01, // 184 + 0x00,0x00,0x00,0x00,0x80,0x01,0x00,0x00,0xC0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0xE0,0x3F,0x00,0x00,0xE0,0x3F, // 185 + 0x00,0x00,0x00,0x00,0x80,0x0F,0x00,0x00,0xC0,0x1F,0x00,0x00,0xE0,0x38,0x00,0x00,0x60,0x30,0x00,0x00,0xE0,0x38,0x00,0x00,0xC0,0x1F,0x00,0x00,0x80,0x0F, // 186 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x10,0x00,0x00,0x1C,0x1C,0x00,0x00,0x78,0x0F,0x00,0x00,0xE0,0x03,0x00,0x00,0x84,0x10,0x00,0x00,0x1C,0x1C,0x00,0x00,0x78,0x0F,0x00,0x00,0xE0,0x03,0x00,0x00,0x80, // 187 + 0x00,0x00,0x00,0x00,0x80,0x01,0x00,0x00,0xC0,0x00,0x00,0x00,0xC0,0x00,0x20,0x00,0xE0,0x3F,0x38,0x00,0xE0,0x3F,0x1C,0x00,0x00,0x00,0x0E,0x00,0x00,0x80,0x03,0x00,0x00,0xC0,0x01,0x00,0x00,0xE0,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x07,0x0C,0x00,0xC0,0x01,0x0E,0x00,0xE0,0x80,0x0B,0x00,0x60,0xC0,0x08,0x00,0x00,0xE0,0x3F,0x00,0x00,0xE0,0x3F,0x00,0x00,0x00,0x08, // 188 + 0x00,0x00,0x00,0x00,0x80,0x01,0x00,0x00,0xC0,0x00,0x00,0x00,0xC0,0x00,0x20,0x00,0xE0,0x3F,0x30,0x00,0xE0,0x3F,0x1C,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x07,0x00,0x00,0xC0,0x01,0x00,0x00,0xE0,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x4E,0x20,0x00,0x00,0x67,0x30,0x00,0xC0,0x21,0x38,0x00,0xE0,0x20,0x2C,0x00,0x60,0x20,0x26,0x00,0x00,0xE0,0x27,0x00,0x00,0xC0,0x21, // 189 + 0x40,0x10,0x00,0x00,0x60,0x30,0x00,0x00,0x20,0x20,0x00,0x00,0x20,0x22,0x20,0x00,0x20,0x22,0x30,0x00,0xE0,0x3D,0x38,0x00,0xC0,0x1D,0x0E,0x00,0x00,0x00,0x07,0x00,0x00,0x80,0x03,0x00,0x00,0xE0,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x0E,0x0C,0x00,0x00,0x07,0x0E,0x00,0x80,0x83,0x0B,0x00,0xE0,0xC0,0x08,0x00,0x60,0xE0,0x3F,0x00,0x20,0xE0,0x3F,0x00,0x00,0x00,0x08, // 190 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0xF8,0x03,0x00,0x00,0x1E,0x03,0x00,0x00,0x07,0x07,0x00,0xE6,0x03,0x06,0x00,0xE6,0x01,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x80,0x03,0x00,0x00,0xC0,0x01,0x00,0x00,0xC0, // 191 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x82,0x8F,0x01,0x00,0xE6,0x83,0x01,0x00,0x6E,0x80,0x01,0x00,0xE8,0x83,0x01,0x00,0x80,0x8F,0x01,0x00,0x00,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 192 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x80,0x8F,0x01,0x00,0xE8,0x83,0x01,0x00,0x6E,0x80,0x01,0x00,0xE6,0x83,0x01,0x00,0x82,0x8F,0x01,0x00,0x00,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 193 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x88,0x8F,0x01,0x00,0xEC,0x83,0x01,0x00,0x66,0x80,0x01,0x00,0xE6,0x83,0x01,0x00,0x8C,0x8F,0x01,0x00,0x08,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 194 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x0C,0xFE,0x01,0x00,0x8E,0x8F,0x01,0x00,0xE6,0x83,0x01,0x00,0x66,0x80,0x01,0x00,0xEC,0x83,0x01,0x00,0x8C,0x8F,0x01,0x00,0x0E,0xFE,0x01,0x00,0x06,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 195 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x8C,0x8F,0x01,0x00,0xEC,0x83,0x01,0x00,0x60,0x80,0x01,0x00,0xE0,0x83,0x01,0x00,0x8C,0x8F,0x01,0x00,0x0C,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 196 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x9C,0x8F,0x01,0x00,0xE2,0x83,0x01,0x00,0x62,0x80,0x01,0x00,0xE2,0x83,0x01,0x00,0x9C,0x8F,0x01,0x00,0x00,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 197 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0x0F,0x00,0x00,0xC0,0x03,0x00,0x00,0xF0,0x01,0x00,0x00,0xBC,0x01,0x00,0x00,0x8F,0x01,0x00,0xC0,0x83,0x01,0x00,0xE0,0x80,0x01,0x00,0x60,0x80,0x01,0x00,0x60,0x80,0x01,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 198 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0x60,0x00,0x30,0x02,0x60,0x00,0x30,0x02,0x60,0x00,0xF0,0x02,0x60,0x00,0xB0,0x03,0x60,0x00,0x30,0x01,0x60,0x00,0x30,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x03,0x0F,0x00,0x00,0x02,0x03, // 199 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x62,0x30,0x30,0x00,0x66,0x30,0x30,0x00,0x6E,0x30,0x30,0x00,0x68,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 200 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x68,0x30,0x30,0x00,0x6E,0x30,0x30,0x00,0x66,0x30,0x30,0x00,0x62,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 201 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x68,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x66,0x30,0x30,0x00,0x66,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x68,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 202 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 203 + 0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0xE6,0xFF,0x3F,0x00,0xEE,0xFF,0x3F,0x00,0x08, // 204 + 0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0xEE,0xFF,0x3F,0x00,0xE6,0xFF,0x3F,0x00,0x02, // 205 + 0x08,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0xE6,0xFF,0x3F,0x00,0xE6,0xFF,0x3F,0x00,0x0C,0x00,0x00,0x00,0x08, // 206 + 0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x0C,0x00,0x00,0x00,0x0C, // 207 + 0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x03,0x0E,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 208 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0xC0,0x01,0x00,0x00,0x8C,0x03,0x00,0x00,0x0E,0x0E,0x00,0x00,0x06,0x3C,0x00,0x00,0x06,0x70,0x00,0x00,0x0C,0xE0,0x01,0x00,0x0C,0x80,0x03,0x00,0x0E,0x00,0x0F,0x00,0x06,0x00,0x1C,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 209 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x38,0x00,0x62,0x00,0x30,0x00,0x66,0x00,0x30,0x00,0x6E,0x00,0x30,0x00,0x68,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 210 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x38,0x00,0x60,0x00,0x30,0x00,0x68,0x00,0x30,0x00,0x6E,0x00,0x30,0x00,0x66,0x00,0x30,0x00,0x62,0x00,0x30,0x00,0xE0,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 211 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x38,0x00,0x68,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0x66,0x00,0x30,0x00,0x66,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0xE8,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 212 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xCC,0x00,0x18,0x00,0xEE,0x00,0x38,0x00,0x66,0x00,0x30,0x00,0x66,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0x6E,0x00,0x30,0x00,0xE6,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 213 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x38,0x00,0x6C,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0xEC,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 214 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x03,0x00,0x00,0x8E,0x03,0x00,0x00,0xDC,0x01,0x00,0x00,0xF8,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0xDC,0x01,0x00,0x00,0x8E,0x03,0x00,0x00,0x06,0x03, // 215 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x21,0x00,0x00,0xFF,0x77,0x00,0x80,0x07,0x3F,0x00,0xC0,0x01,0x1E,0x00,0xC0,0x00,0x1F,0x00,0xE0,0x80,0x3B,0x00,0x60,0xC0,0x31,0x00,0x60,0xE0,0x30,0x00,0x60,0x70,0x30,0x00,0x60,0x38,0x30,0x00,0x60,0x1C,0x30,0x00,0xE0,0x0E,0x38,0x00,0xC0,0x07,0x18,0x00,0xC0,0x03,0x1C,0x00,0xE0,0x07,0x0F,0x00,0x70,0xFF,0x07,0x00,0x20,0xFC,0x01, // 216 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x03,0x00,0xE0,0xFF,0x0F,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x38,0x00,0x02,0x00,0x30,0x00,0x06,0x00,0x30,0x00,0x0E,0x00,0x30,0x00,0x08,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x0F,0x00,0xE0,0xFF,0x03, // 217 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x03,0x00,0xE0,0xFF,0x0F,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x30,0x00,0x08,0x00,0x30,0x00,0x0E,0x00,0x30,0x00,0x06,0x00,0x30,0x00,0x02,0x00,0x30,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x0F,0x00,0xE0,0xFF,0x03, // 218 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x03,0x00,0xE0,0xFF,0x0F,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x38,0x00,0x08,0x00,0x30,0x00,0x0C,0x00,0x30,0x00,0x06,0x00,0x30,0x00,0x06,0x00,0x30,0x00,0x0C,0x00,0x30,0x00,0x08,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x0F,0x00,0xE0,0xFF,0x03, // 219 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x03,0x00,0xE0,0xFF,0x0F,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x38,0x00,0x0C,0x00,0x30,0x00,0x0C,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x0C,0x00,0x30,0x00,0x0C,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x0F,0x00,0xE0,0xFF,0x03, // 220 + 0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xC0,0x01,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x3C,0x00,0x00,0x08,0xF0,0x3F,0x00,0x0E,0xF0,0x3F,0x00,0x06,0x3C,0x00,0x00,0x02,0x1E,0x00,0x00,0x00,0x07,0x00,0x00,0xC0,0x03,0x00,0x00,0xE0,0x01,0x00,0x00,0x60,0x00,0x00,0x00,0x20, // 221 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x07,0x00,0x00,0x86,0x03,0x00,0x00,0xFE,0x01,0x00,0x00,0xF8, // 222 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xFF,0x3F,0x00,0xC0,0xFF,0x3F,0x00,0xC0,0x00,0x00,0x00,0x60,0x00,0x08,0x00,0x60,0x00,0x1C,0x00,0x60,0x00,0x38,0x00,0xE0,0x78,0x30,0x00,0xC0,0x7F,0x30,0x00,0x80,0xC7,0x30,0x00,0x00,0x80,0x39,0x00,0x00,0x80,0x1F,0x00,0x00,0x00,0x0F, // 223 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0x00,0x8C,0x39,0x00,0x20,0x86,0x31,0x00,0x60,0x86,0x31,0x00,0xE0,0xC6,0x30,0x00,0x80,0xC6,0x18,0x00,0x00,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 224 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0x00,0x8C,0x39,0x00,0x00,0x86,0x31,0x00,0x80,0x86,0x31,0x00,0xE0,0xC6,0x30,0x00,0x60,0xC6,0x18,0x00,0x20,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 225 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0x80,0x8C,0x39,0x00,0xC0,0x86,0x31,0x00,0x60,0x86,0x31,0x00,0x60,0xC6,0x30,0x00,0xC0,0xC6,0x18,0x00,0x80,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 226 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0xC0,0x1C,0x1F,0x00,0xE0,0x8C,0x39,0x00,0x60,0x86,0x31,0x00,0x60,0x86,0x31,0x00,0xC0,0xC6,0x30,0x00,0xC0,0xC6,0x18,0x00,0xE0,0xCE,0x0C,0x00,0x60,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 227 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0xC0,0x8C,0x39,0x00,0xC0,0x86,0x31,0x00,0x00,0x86,0x31,0x00,0x00,0xC6,0x30,0x00,0xC0,0xC6,0x18,0x00,0xC0,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 228 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0x00,0x8C,0x39,0x00,0x70,0x86,0x31,0x00,0x88,0x86,0x31,0x00,0x88,0xC6,0x30,0x00,0x88,0xC6,0x18,0x00,0x70,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 229 + 0x00,0x00,0x00,0x00,0x00,0x10,0x0F,0x00,0x00,0x9C,0x1F,0x00,0x00,0xCC,0x39,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0x66,0x18,0x00,0x00,0x6E,0x1C,0x00,0x00,0xFC,0x0F,0x00,0x00,0xFC,0x1F,0x00,0x00,0xCC,0x1C,0x00,0x00,0xCE,0x38,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xCC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xE0,0x04, // 230 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x02,0x00,0x06,0x30,0x02,0x00,0x06,0xF0,0x02,0x00,0x06,0xB0,0x03,0x00,0x0E,0x38,0x01,0x00,0x1C,0x1C,0x00,0x00,0x18,0x0C, // 231 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0xDC,0x1C,0x00,0x20,0xCE,0x38,0x00,0x60,0xC6,0x30,0x00,0xE0,0xC6,0x30,0x00,0x80,0xC6,0x30,0x00,0x00,0xCE,0x38,0x00,0x00,0xDC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xF0,0x04, // 232 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0xDC,0x1C,0x00,0x00,0xCE,0x38,0x00,0x80,0xC6,0x30,0x00,0xE0,0xC6,0x30,0x00,0x60,0xC6,0x30,0x00,0x20,0xCE,0x38,0x00,0x00,0xDC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xF0,0x04, // 233 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0xDC,0x1C,0x00,0x80,0xCE,0x38,0x00,0xC0,0xC6,0x30,0x00,0x60,0xC6,0x30,0x00,0x60,0xC6,0x30,0x00,0xC0,0xCE,0x38,0x00,0x80,0xDC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xF0,0x04, // 234 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0xDC,0x1C,0x00,0xC0,0xCE,0x38,0x00,0xC0,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0xC0,0xCE,0x38,0x00,0xC0,0xDC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xF0,0x04, // 235 + 0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0xFE,0x3F,0x00,0xE0,0xFE,0x3F,0x00,0x80, // 236 + 0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xE0,0xFE,0x3F,0x00,0x60,0xFE,0x3F,0x00,0x20, // 237 + 0x80,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x60,0xFE,0x3F,0x00,0x60,0xFE,0x3F,0x00,0xC0,0x00,0x00,0x00,0x80, // 238 + 0xC0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F,0x00,0xC0,0x00,0x00,0x00,0xC0, // 239 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1D,0x1C,0x00,0xA0,0x0F,0x38,0x00,0xA0,0x06,0x30,0x00,0xE0,0x06,0x30,0x00,0xC0,0x06,0x30,0x00,0xC0,0x0F,0x38,0x00,0x20,0x1F,0x1C,0x00,0x00,0xFC,0x0F,0x00,0x00,0xE0,0x07, // 240 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x3F,0x00,0xC0,0xFE,0x3F,0x00,0xE0,0x18,0x00,0x00,0x60,0x0C,0x00,0x00,0x60,0x06,0x00,0x00,0xC0,0x06,0x00,0x00,0xC0,0x06,0x00,0x00,0xE0,0x0E,0x00,0x00,0x60,0xFC,0x3F,0x00,0x00,0xF8,0x3F, // 241 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x20,0x0E,0x38,0x00,0x60,0x06,0x30,0x00,0xE0,0x06,0x30,0x00,0x80,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 242 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x00,0x80,0x06,0x30,0x00,0xE0,0x06,0x30,0x00,0x60,0x06,0x30,0x00,0x20,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 243 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x80,0x0E,0x38,0x00,0xC0,0x06,0x30,0x00,0x60,0x06,0x30,0x00,0x60,0x06,0x30,0x00,0xC0,0x0E,0x38,0x00,0x80,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 244 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0xC0,0x1C,0x1C,0x00,0xE0,0x0E,0x38,0x00,0x60,0x06,0x30,0x00,0x60,0x06,0x30,0x00,0xC0,0x06,0x30,0x00,0xC0,0x0E,0x38,0x00,0xE0,0x1C,0x1C,0x00,0x60,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 245 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0xC0,0x0E,0x38,0x00,0xC0,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0xC0,0x0E,0x38,0x00,0xC0,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 246 + 0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0xB6,0x01,0x00,0x00,0xB6,0x01,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30, // 247 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x67,0x00,0x00,0xF8,0x7F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x3F,0x00,0x00,0x86,0x33,0x00,0x00,0xE6,0x31,0x00,0x00,0x76,0x30,0x00,0x00,0x3E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xFF,0x0F,0x00,0x00,0xF3,0x07, // 248 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x0F,0x00,0x00,0xFE,0x1F,0x00,0x20,0x00,0x38,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x30,0x00,0x80,0x00,0x30,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x0C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 249 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x0F,0x00,0x00,0xFE,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x30,0x00,0x80,0x00,0x30,0x00,0xE0,0x00,0x30,0x00,0x60,0x00,0x18,0x00,0x20,0x00,0x0C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 250 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x0F,0x00,0x00,0xFE,0x1F,0x00,0x80,0x00,0x38,0x00,0xC0,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xC0,0x00,0x18,0x00,0x80,0x00,0x0C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 251 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x0F,0x00,0x00,0xFE,0x1F,0x00,0xC0,0x00,0x38,0x00,0xC0,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0xC0,0x00,0x18,0x00,0xC0,0x00,0x0C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 252 + 0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x7E,0x00,0x06,0x00,0xF0,0x01,0x06,0x00,0x80,0x0F,0x07,0x80,0x00,0xFE,0x03,0xE0,0x00,0xFC,0x00,0x60,0xC0,0x1F,0x00,0x20,0xF8,0x03,0x00,0x00,0x3E,0x00,0x00,0x00,0x06, // 253 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0xFF,0x07,0xE0,0xFF,0xFF,0x07,0x00,0x1C,0x18,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x03, // 254 + 0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x7E,0x00,0x06,0xC0,0xF0,0x01,0x06,0xC0,0x80,0x0F,0x07,0x00,0x00,0xFE,0x03,0x00,0x00,0xFC,0x00,0xC0,0xC0,0x1F,0x00,0xC0,0xF8,0x03,0x00,0x00,0x3E,0x00,0x00,0x00,0x06 // 255 +}; +#endif diff --git a/libraries/SSD1306_I2C/src/OLEDDisplayUi.cpp b/libraries/SSD1306_I2C/src/OLEDDisplayUi.cpp new file mode 100644 index 00000000..79d25715 --- /dev/null +++ b/libraries/SSD1306_I2C/src/OLEDDisplayUi.cpp @@ -0,0 +1,422 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + +#include "OLEDDisplayUi.h" + +OLEDDisplayUi::OLEDDisplayUi(OLEDDisplay *display) { + this->display = display; +} + +void OLEDDisplayUi::init() { + this->display->init(); +} + +void OLEDDisplayUi::setTargetFPS(uint8_t fps){ + float oldInterval = this->updateInterval; + this->updateInterval = ((float) 1.0 / (float) fps) * 1000; + + // Calculate new ticksPerFrame + float changeRatio = oldInterval / (float) this->updateInterval; + this->ticksPerFrame *= changeRatio; + this->ticksPerTransition *= changeRatio; +} + +// -/------ Automatic controll ------\- + +void OLEDDisplayUi::enableAutoTransition(){ + this->autoTransition = true; +} +void OLEDDisplayUi::disableAutoTransition(){ + this->autoTransition = false; +} +void OLEDDisplayUi::setAutoTransitionForwards(){ + this->state.frameTransitionDirection = 1; + this->lastTransitionDirection = 1; +} +void OLEDDisplayUi::setAutoTransitionBackwards(){ + this->state.frameTransitionDirection = -1; + this->lastTransitionDirection = -1; +} +void OLEDDisplayUi::setTimePerFrame(uint16_t time){ + this->ticksPerFrame = (uint16_t) ( (float) time / (float) updateInterval); +} +void OLEDDisplayUi::setTimePerTransition(uint16_t time){ + this->ticksPerTransition = (uint16_t) ( (float) time / (float) updateInterval); +} + +// -/------ Customize indicator position and style -------\- +void OLEDDisplayUi::enableIndicator(){ + this->state.isIndicatorDrawen = true; +} + +void OLEDDisplayUi::disableIndicator(){ + this->state.isIndicatorDrawen = false; +} + +void OLEDDisplayUi::enableAllIndicators(){ + this->shouldDrawIndicators = true; +} + +void OLEDDisplayUi::disableAllIndicators(){ + this->shouldDrawIndicators = false; +} + +void OLEDDisplayUi::setIndicatorPosition(IndicatorPosition pos) { + this->indicatorPosition = pos; +} +void OLEDDisplayUi::setIndicatorDirection(IndicatorDirection dir) { + this->indicatorDirection = dir; +} +void OLEDDisplayUi::setActiveSymbol(const uint8_t* symbol) { + this->activeSymbol = symbol; +} +void OLEDDisplayUi::setInactiveSymbol(const uint8_t* symbol) { + this->inactiveSymbol = symbol; +} + + +// -/----- Frame settings -----\- +void OLEDDisplayUi::setFrameAnimation(AnimationDirection dir) { + this->frameAnimationDirection = dir; +} +void OLEDDisplayUi::setFrames(FrameCallback* frameFunctions, uint8_t frameCount) { + this->frameFunctions = frameFunctions; + this->frameCount = frameCount; + this->resetState(); +} + +// -/----- Overlays ------\- +void OLEDDisplayUi::setOverlays(OverlayCallback* overlayFunctions, uint8_t overlayCount){ + this->overlayFunctions = overlayFunctions; + this->overlayCount = overlayCount; +} + +// -/----- Loading Process -----\- + +void OLEDDisplayUi::setLoadingDrawFunction(LoadingDrawFunction loadingDrawFunction) { + this->loadingDrawFunction = loadingDrawFunction; +} + +void OLEDDisplayUi::runLoadingProcess(LoadingStage* stages, uint8_t stagesCount) { + uint8_t progress = 0; + uint8_t increment = 100 / stagesCount; + + for (uint8_t i = 0; i < stagesCount; i++) { + display->clear(); + this->loadingDrawFunction(this->display, &stages[i], progress); + display->display(); + + stages[i].callback(); + + progress += increment; + yield(); + } + + display->clear(); + this->loadingDrawFunction(this->display, &stages[stagesCount-1], progress); + display->display(); + + delay(150); +} + +// -/----- Manuel control -----\- +void OLEDDisplayUi::nextFrame() { + if (this->state.frameState != IN_TRANSITION) { + this->state.manuelControll = true; + this->state.frameState = IN_TRANSITION; + this->state.ticksSinceLastStateSwitch = 0; + this->lastTransitionDirection = this->state.frameTransitionDirection; + this->state.frameTransitionDirection = 1; + } +} +void OLEDDisplayUi::previousFrame() { + if (this->state.frameState != IN_TRANSITION) { + this->state.manuelControll = true; + this->state.frameState = IN_TRANSITION; + this->state.ticksSinceLastStateSwitch = 0; + this->lastTransitionDirection = this->state.frameTransitionDirection; + this->state.frameTransitionDirection = -1; + } +} + +void OLEDDisplayUi::switchToFrame(uint8_t frame) { + if (frame >= this->frameCount) return; + this->state.ticksSinceLastStateSwitch = 0; + if (frame == this->state.currentFrame) return; + this->state.frameState = FIXED; + this->state.currentFrame = frame; + this->state.isIndicatorDrawen = true; +} + +void OLEDDisplayUi::transitionToFrame(uint8_t frame) { + if (frame >= this->frameCount) return; + this->state.ticksSinceLastStateSwitch = 0; + if (frame == this->state.currentFrame) return; + this->nextFrameNumber = frame; + this->lastTransitionDirection = this->state.frameTransitionDirection; + this->state.manuelControll = true; + this->state.frameState = IN_TRANSITION; + this->state.frameTransitionDirection = frame < this->state.currentFrame ? -1 : 1; +} + + +// -/----- State information -----\- +OLEDDisplayUiState* OLEDDisplayUi::getUiState(){ + return &this->state; +} + + +int8_t OLEDDisplayUi::update(){ + unsigned long frameStart = millis(); + int8_t timeBudget = this->updateInterval - (frameStart - this->state.lastUpdate); + if ( timeBudget <= 0) { + // Implement frame skipping to ensure time budget is keept + if (this->autoTransition && this->state.lastUpdate != 0) this->state.ticksSinceLastStateSwitch += ceil(0-(timeBudget / this->updateInterval)); + + this->state.lastUpdate = frameStart; + this->tick(); + } + return this->updateInterval - (millis() - frameStart); +} + + +void OLEDDisplayUi::tick() { + this->state.ticksSinceLastStateSwitch++; + + switch (this->state.frameState) { + case IN_TRANSITION: + if (this->state.ticksSinceLastStateSwitch >= this->ticksPerTransition){ + this->state.frameState = FIXED; + this->state.currentFrame = getNextFrameNumber(); + this->state.ticksSinceLastStateSwitch = 0; + this->nextFrameNumber = -1; + } + break; + case FIXED: + // Revert manuelControll + if (this->state.manuelControll) { + this->state.frameTransitionDirection = this->lastTransitionDirection; + this->state.manuelControll = false; + } + if (this->state.ticksSinceLastStateSwitch >= this->ticksPerFrame){ + if (this->autoTransition){ + this->state.frameState = IN_TRANSITION; + } + this->state.ticksSinceLastStateSwitch = 0; + } + break; + } + + this->display->clear(); + this->drawFrame(); + if (shouldDrawIndicators) { + this->drawIndicator(); + } + this->drawOverlays(); + this->display->display(); +} + +void OLEDDisplayUi::resetState() { + this->state.lastUpdate = 0; + this->state.ticksSinceLastStateSwitch = 0; + this->state.frameState = FIXED; + this->state.currentFrame = 0; + this->state.isIndicatorDrawen = true; +} + +void OLEDDisplayUi::drawFrame(){ + switch (this->state.frameState){ + case IN_TRANSITION: { + float progress = (float) this->state.ticksSinceLastStateSwitch / (float) this->ticksPerTransition; + int16_t x = 0, y = 0, x1 = 0, y1 = 0; + switch(this->frameAnimationDirection){ + case SLIDE_LEFT: + x = 0-(this->display->width() * progress); + y = 0; + x1 = x + this->display->width(); + y1 = 0; + break; + case SLIDE_RIGHT: + x = this->display->width() * progress; + y = 0; + x1 = x - this->display->width(); + y1 = 0; + break; + case SLIDE_UP: + x = 0; + y = 0-(this->display->height() * progress); + x1 = 0; + y1 = y + this->display->height(); + break; + case SLIDE_DOWN: + default: + x = 0; + y = this->display->height() * progress; + x1 = 0; + y1 = y - this->display->height(); + break; + } + + // Invert animation if direction is reversed. + int8_t dir = this->state.frameTransitionDirection >= 0 ? 1 : -1; + x *= dir; y *= dir; x1 *= dir; y1 *= dir; + + bool drawenCurrentFrame; + + + // Prope each frameFunction for the indicator Drawen state + this->enableIndicator(); + (this->frameFunctions[this->state.currentFrame])(this->display, &this->state, x, y); + drawenCurrentFrame = this->state.isIndicatorDrawen; + + this->enableIndicator(); + (this->frameFunctions[this->getNextFrameNumber()])(this->display, &this->state, x1, y1); + + // Build up the indicatorDrawState + if (drawenCurrentFrame && !this->state.isIndicatorDrawen) { + // Drawen now but not next + this->indicatorDrawState = 2; + } else if (!drawenCurrentFrame && this->state.isIndicatorDrawen) { + // Not drawen now but next + this->indicatorDrawState = 1; + } else if (!drawenCurrentFrame && !this->state.isIndicatorDrawen) { + // Not drawen in both frames + this->indicatorDrawState = 3; + } + + // If the indicator isn't draw in the current frame + // reflect it in state.isIndicatorDrawen + if (!drawenCurrentFrame) this->state.isIndicatorDrawen = false; + + break; + } + case FIXED: + // Always assume that the indicator is drawn! + // And set indicatorDrawState to "not known yet" + this->indicatorDrawState = 0; + this->enableIndicator(); + (this->frameFunctions[this->state.currentFrame])(this->display, &this->state, 0, 0); + break; + } +} + +void OLEDDisplayUi::drawIndicator() { + + // Only draw if the indicator is invisible + // for both frames or + // the indiactor is shown and we are IN_TRANSITION + if (this->indicatorDrawState == 3 || (!this->state.isIndicatorDrawen && this->state.frameState != IN_TRANSITION)) { + return; + } + + uint8_t posOfHighlightFrame = 0; + float indicatorFadeProgress = 0; + + // if the indicator needs to be slided in we want to + // highlight the next frame in the transition + uint8_t frameToHighlight = this->indicatorDrawState == 1 ? this->getNextFrameNumber() : this->state.currentFrame; + + // Calculate the frame that needs to be highlighted + // based on the Direction the indiactor is drawn + switch (this->indicatorDirection){ + case LEFT_RIGHT: + posOfHighlightFrame = frameToHighlight; + break; + case RIGHT_LEFT: + default: + posOfHighlightFrame = this->frameCount - frameToHighlight; + break; + } + + switch (this->indicatorDrawState) { + case 1: // Indicator was not drawn in this frame but will be in next + // Slide IN + indicatorFadeProgress = 1 - ((float) this->state.ticksSinceLastStateSwitch / (float) this->ticksPerTransition); + break; + case 2: // Indicator was drawn in this frame but not in next + // Slide OUT + indicatorFadeProgress = ((float) this->state.ticksSinceLastStateSwitch / (float) this->ticksPerTransition); + break; + } + + //Space between indicators - reduce for small screen sizes + uint16_t indicatorSpacing = 12; + if (this->display->getHeight() < 64 && (this->indicatorPosition == RIGHT || this->indicatorPosition == LEFT)) { + indicatorSpacing = 6; + } + + uint16_t frameStartPos = (indicatorSpacing * frameCount / 2); + const uint8_t *image; + + uint16_t x = 0,y = 0; + + + for (byte i = 0; i < this->frameCount; i++) { + + switch (this->indicatorPosition){ + case TOP: + y = 0 - (8 * indicatorFadeProgress); + x = (this->display->width() / 2) - frameStartPos + 12 * i; + break; + case BOTTOM: + y = (this->display->height() - 8) + (8 * indicatorFadeProgress); + x = (this->display->width() / 2) - frameStartPos + 12 * i; + break; + case RIGHT: + x = (this->display->width() - 8) + (8 * indicatorFadeProgress); + y = (this->display->height() / 2) - frameStartPos + 2 + 12 * i; + break; + case LEFT: + default: + x = 0 - (8 * indicatorFadeProgress); + y = (this->display->height() / 2) - frameStartPos + 2 + indicatorSpacing * i; + break; + } + + if (posOfHighlightFrame == i) { + image = this->activeSymbol; + } else { + image = this->inactiveSymbol; + } + + this->display->drawFastImage(x, y, 8, 8, image); + } +} + +void OLEDDisplayUi::drawOverlays() { + for (uint8_t i=0;ioverlayCount;i++){ + (this->overlayFunctions[i])(this->display, &this->state); + } +} + +uint8_t OLEDDisplayUi::getNextFrameNumber(){ + if (this->nextFrameNumber != -1) return this->nextFrameNumber; + return (this->state.currentFrame + this->frameCount + this->state.frameTransitionDirection) % this->frameCount; +} diff --git a/libraries/SSD1306_I2C/src/OLEDDisplayUi.h b/libraries/SSD1306_I2C/src/OLEDDisplayUi.h new file mode 100644 index 00000000..2cabf300 --- /dev/null +++ b/libraries/SSD1306_I2C/src/OLEDDisplayUi.h @@ -0,0 +1,309 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + +#ifndef OLEDDISPLAYUI_h +#define OLEDDISPLAYUI_h + +#include +#include "OLEDDisplay.h" + +//#define DEBUG_OLEDDISPLAYUI(...) Serial.printf( __VA_ARGS__ ) + +#ifndef DEBUG_OLEDDISPLAYUI +#define DEBUG_OLEDDISPLAYUI(...) +#endif + +enum AnimationDirection { + SLIDE_UP, + SLIDE_DOWN, + SLIDE_LEFT, + SLIDE_RIGHT +}; + +enum IndicatorPosition { + TOP, + RIGHT, + BOTTOM, + LEFT +}; + +enum IndicatorDirection { + LEFT_RIGHT, + RIGHT_LEFT +}; + +enum FrameState { + IN_TRANSITION, + FIXED +}; + + +const uint8_t ANIMATION_activeSymbol[] PROGMEM = { + 0x00, 0x18, 0x3c, 0x7e, 0x7e, 0x3c, 0x18, 0x00 +}; + +const uint8_t ANIMATION_inactiveSymbol[] PROGMEM = { + 0x00, 0x0, 0x0, 0x18, 0x18, 0x0, 0x0, 0x00 +}; + + +// Structure of the UiState +struct OLEDDisplayUiState { + uint64_t lastUpdate = 0; + uint16_t ticksSinceLastStateSwitch = 0; + + FrameState frameState = FIXED; + uint8_t currentFrame = 0; + + bool isIndicatorDrawen = true; + + // Normal = 1, Inverse = -1; + int8_t frameTransitionDirection = 1; + + bool manuelControll = false; + + // Custom data that can be used by the user + void* userData = NULL; +}; + +struct LoadingStage { + const char* process; + void (*callback)(); +}; + +typedef void (*FrameCallback)(OLEDDisplay *display, OLEDDisplayUiState* state, int16_t x, int16_t y); +typedef void (*OverlayCallback)(OLEDDisplay *display, OLEDDisplayUiState* state); +typedef void (*LoadingDrawFunction)(OLEDDisplay *display, LoadingStage* stage, uint8_t progress); + +class OLEDDisplayUi { + private: + OLEDDisplay *display; + + // Symbols for the Indicator + IndicatorPosition indicatorPosition = BOTTOM; + IndicatorDirection indicatorDirection = LEFT_RIGHT; + + const uint8_t* activeSymbol = ANIMATION_activeSymbol; + const uint8_t* inactiveSymbol = ANIMATION_inactiveSymbol; + + bool shouldDrawIndicators = true; + + // Values for the Frames + AnimationDirection frameAnimationDirection = SLIDE_RIGHT; + + int8_t lastTransitionDirection = 1; + + uint16_t ticksPerFrame = 151; // ~ 5000ms at 30 FPS + uint16_t ticksPerTransition = 15; // ~ 500ms at 30 FPS + + bool autoTransition = true; + + FrameCallback* frameFunctions; + uint8_t frameCount = 0; + + // Internally used to transition to a specific frame + int8_t nextFrameNumber = -1; + + // Values for Overlays + OverlayCallback* overlayFunctions; + uint8_t overlayCount = 0; + + // Will the Indicator be drawen + // 3 Not drawn in both frames + // 2 Drawn this frame but not next + // 1 Not drown this frame but next + // 0 Not known yet + uint8_t indicatorDrawState = 1; + + // Loading screen + LoadingDrawFunction loadingDrawFunction = [](OLEDDisplay *display, LoadingStage* stage, uint8_t progress) { + display->setTextAlignment(TEXT_ALIGN_CENTER); + display->setFont(ArialMT_Plain_10); + display->drawString(64, 18, stage->process); + display->drawProgressBar(4, 32, 120, 8, progress); + }; + + // UI State + OLEDDisplayUiState state; + + // Bookeeping for update + uint8_t updateInterval = 33; + + uint8_t getNextFrameNumber(); + void drawIndicator(); + void drawFrame(); + void drawOverlays(); + void tick(); + void resetState(); + + public: + + OLEDDisplayUi(OLEDDisplay *display); + + /** + * Initialise the display + */ + void init(); + + /** + * Configure the internal used target FPS + */ + void setTargetFPS(uint8_t fps); + + // Automatic Controll + /** + * Enable automatic transition to next frame after the some time can be configured with `setTimePerFrame` and `setTimePerTransition`. + */ + void enableAutoTransition(); + + /** + * Disable automatic transition to next frame. + */ + void disableAutoTransition(); + + /** + * Set the direction if the automatic transitioning + */ + void setAutoTransitionForwards(); + void setAutoTransitionBackwards(); + + /** + * Set the approx. time a frame is displayed + */ + void setTimePerFrame(uint16_t time); + + /** + * Set the approx. time a transition will take + */ + void setTimePerTransition(uint16_t time); + + // Customize indicator position and style + + /** + * Draw the indicator. + * This is the defaut state for all frames if + * the indicator was hidden on the previous frame + * it will be slided in. + */ + void enableIndicator(); + + /** + * Don't draw the indicator. + * This will slide out the indicator + * when transitioning to the next frame. + */ + void disableIndicator(); + + /** + * Enable drawing of indicators + */ + void enableAllIndicators(); + + /** + * Disable draw of indicators. + */ + void disableAllIndicators(); + + /** + * Set the position of the indicator bar. + */ + void setIndicatorPosition(IndicatorPosition pos); + + /** + * Set the direction of the indicator bar. Defining the order of frames ASCENDING / DESCENDING + */ + void setIndicatorDirection(IndicatorDirection dir); + + /** + * Set the symbol to indicate an active frame in the indicator bar. + */ + void setActiveSymbol(const uint8_t* symbol); + + /** + * Set the symbol to indicate an inactive frame in the indicator bar. + */ + void setInactiveSymbol(const uint8_t* symbol); + + + // Frame settings + + /** + * Configure what animation is used to transition from one frame to another + */ + void setFrameAnimation(AnimationDirection dir); + + /** + * Add frame drawing functions + */ + void setFrames(FrameCallback* frameFunctions, uint8_t frameCount); + + // Overlay + + /** + * Add overlays drawing functions that are draw independent of the Frames + */ + void setOverlays(OverlayCallback* overlayFunctions, uint8_t overlayCount); + + + // Loading animation + /** + * Set the function that will draw each step + * in the loading animation + */ + void setLoadingDrawFunction(LoadingDrawFunction loadingFunction); + + + /** + * Run the loading process + */ + void runLoadingProcess(LoadingStage* stages, uint8_t stagesCount); + + + // Manual Control + void nextFrame(); + void previousFrame(); + + /** + * Switch without transition to frame `frame`. + */ + void switchToFrame(uint8_t frame); + + /** + * Transition to frame `frame`, when the `frame` number is bigger than the current + * frame the forward animation will be used, otherwise the backwards animation is used. + */ + void transitionToFrame(uint8_t frame); + + // State Info + OLEDDisplayUiState* getUiState(); + + int8_t update(); +}; +#endif diff --git a/libraries/SSD1306_I2C/src/SSD1306.h b/libraries/SSD1306_I2C/src/SSD1306.h new file mode 100644 index 00000000..f6bd554c --- /dev/null +++ b/libraries/SSD1306_I2C/src/SSD1306.h @@ -0,0 +1,39 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + +#ifndef SSD1306_h +#define SSD1306_h +#include "SSD1306Wire.h" + +// For legacy support make SSD1306 an alias for SSD1306 +typedef SSD1306Wire SSD1306; + + +#endif diff --git a/libraries/SSD1306_I2C/src/SSD1306Wire.h b/libraries/SSD1306_I2C/src/SSD1306Wire.h new file mode 100644 index 00000000..524a47a0 --- /dev/null +++ b/libraries/SSD1306_I2C/src/SSD1306Wire.h @@ -0,0 +1,177 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + +#ifndef SSD1306Wire_h +#define SSD1306Wire_h + +#include "OLEDDisplay.h" +#include + + +class SSD1306Wire : public OLEDDisplay { + private: + uint8_t _address; + uint8_t _sda; + uint8_t _scl; + uint8_t _rst; + bool _doI2cAutoInit = false; + + public: + SSD1306Wire(uint8_t _address, uint8_t _sda, uint8_t _scl, uint8_t _rst, OLEDDISPLAY_GEOMETRY g = GEOMETRY_128_64) { + setGeometry(g); + + this->_address = _address; + this->_sda = _sda; + this->_scl = _scl; + this->_rst = _rst; + } + + + bool connect() { + Wire.begin(this->_sda, this->_scl); + // Let's use ~700khz if ESP8266 is in 160Mhz mode + return true; + } + + void display(void) { + initI2cIfNeccesary(); + const int x_offset = (128 - this->width()) / 2; + #ifdef OLEDDISPLAY_DOUBLE_BUFFER + uint8_t minBoundY = UINT8_MAX; + uint8_t maxBoundY = 0; + + uint8_t minBoundX = UINT8_MAX; + uint8_t maxBoundX = 0; + uint8_t x, y; + + // Calculate the Y bounding box of changes + // and copy buffer[pos] to buffer_back[pos]; + for (y = 0; y < (this->height() / 8); y++) { + for (x = 0; x < this->width(); x++) { + uint16_t pos = x + y * this->width(); + if (buffer[pos] != buffer_back[pos]) { + minBoundY = _min(minBoundY, y); + maxBoundY = _max(maxBoundY, y); + minBoundX = _min(minBoundX, x); + maxBoundX = _max(maxBoundX, x); + } + buffer_back[pos] = buffer[pos]; + } +// yield(); + } + + // If the minBoundY wasn't updated + // we can savely assume that buffer_back[pos] == buffer[pos] + // holdes true for all values of pos + + if (minBoundY == UINT8_MAX) return; + + sendCommand(COLUMNADDR); + sendCommand(x_offset + minBoundX); + sendCommand(x_offset + maxBoundX); + + sendCommand(PAGEADDR); + sendCommand(minBoundY); + sendCommand(maxBoundY); + + byte k = 0; + for (y = minBoundY; y <= maxBoundY; y++) { + for (x = minBoundX; x <= maxBoundX; x++) { + if (k == 0) { + Wire.beginTransmission(_address); + Wire.write(0x40); + } + + Wire.write(buffer[x + y * this->width()]); + k++; + if (k == 16) { + Wire.endTransmission(); + k = 0; + } + } +// yield(); + } + + if (k != 0) { + Wire.endTransmission(); + } + #else + + sendCommand(COLUMNADDR); + sendCommand(x_offset); + sendCommand(x_offset + (this->width() - 1)); + + sendCommand(PAGEADDR); + sendCommand(0x0); + sendCommand((this->height() / 8) - 1); + + if (geometry == GEOMETRY_128_64) { + sendCommand(0x7); + } else if (geometry == GEOMETRY_128_32) { + sendCommand(0x3); + } + + for (uint16_t i=0; i < displayBufferSize; i++) { + Wire.beginTransmission(this->_address); + Wire.write(0x40); + for (uint8_t x = 0; x < 16; x++) { + Wire.write(buffer[i]); + i++; + } + i--; + Wire.endTransmission(); + } + #endif + } + + void setI2cAutoInit(bool doI2cAutoInit) { + _doI2cAutoInit = doI2cAutoInit; + } + + private: + inline void sendCommand(uint8_t command) __attribute__((always_inline)){ + initI2cIfNeccesary(); + Wire.beginTransmission(_address); + Wire.write(0x80); + Wire.write(command); + Wire.endTransmission(); + } + + void initI2cIfNeccesary() { + if (_doI2cAutoInit) { + Wire.begin(this->_sda, this->_scl); + } + } + +}; + +//SSD1306Wire display; + +#endif diff --git a/libraries/SSD1306_I2C/src/heltec.cpp b/libraries/SSD1306_I2C/src/heltec.cpp new file mode 100644 index 00000000..fb8a94ac --- /dev/null +++ b/libraries/SSD1306_I2C/src/heltec.cpp @@ -0,0 +1,62 @@ +// Copyright (c) Heltec Automation. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "heltec.h" + + +Heltec_CubeCell::Heltec_CubeCell(){ + + display = new SSD1306Wire(0x3c, SDA, SCL, GEOMETRY_128_64); +} + +Heltec_CubeCell::~Heltec_CubeCell(){ + delete display; +} + +void Heltec_CubeCell::begin(bool DisplayEnable, bool SerialEnable) { + + + VextON(); + + // UART + if (SerialEnable) { + Serial.begin(115200); + Serial.flush(); + delay(50); + Serial.print("Serial initial done\r\n"); + } + + // OLED + if (DisplayEnable) + { + display->init(); + display->flipScreenVertically(); + display->setFont(ArialMT_Plain_10); + display->drawString(0, 0, "OLED initial done!"); + display->display(); + delay(300); + if (SerialEnable){ + Serial.print("you can see OLED printed OLED initial done!\r\n"); + } + + } +} + +void Heltec_CubeCell::VextON(void) +{ + pinMode(Vext,OUTPUT); + digitalWrite(Vext, LOW); +} + +void Heltec_CubeCell::VextOFF(void) //Vext default OFF +{ + pinMode(Vext,OUTPUT); + digitalWrite(Vext, HIGH); +} + +void Heltec_CubeCell::end() +{ + Serial.end(); + Wire.end(); +} +Heltec_CubeCell Heltec; diff --git a/libraries/SSD1306_I2C/src/heltec.h b/libraries/SSD1306_I2C/src/heltec.h new file mode 100644 index 00000000..394c5010 --- /dev/null +++ b/libraries/SSD1306_I2C/src/heltec.h @@ -0,0 +1,28 @@ + + +#ifndef _HELTEC_H_ +#define _HELTEC_H_ + +#include +#include +#include "SSD1306Wire.h" + + +class Heltec_CubeCell { + + public: + Heltec_CubeCell(); + ~Heltec_CubeCell(); + + void begin(bool DisplayEnable=true, bool SerialEnable=true); + void end(); + + SSD1306Wire *display; + + void VextON(void); + void VextOFF(void); +}; + +extern Heltec_CubeCell Heltec; + +#endif diff --git a/libraries/SSD1306_SPI/OLEDDisplay.cpp b/libraries/SSD1306_SPI/OLEDDisplay.cpp new file mode 100644 index 00000000..7b166c1e --- /dev/null +++ b/libraries/SSD1306_SPI/OLEDDisplay.cpp @@ -0,0 +1,985 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * Copyright (c) 2019 by Helmut Tschemernjak - www.radioshuttle.de + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + + /* + * TODO Helmut + * - test/finish dislplay.printf() on mbed-os + * - Finish _putc with drawLogBuffer when running display + */ + +#include "OLEDDisplay.h" + +OLEDDisplay::OLEDDisplay() { + + displayWidth = 128; + displayHeight = 64; + displayBufferSize = displayWidth * displayHeight / 8; + color = WHITE; + geometry = GEOMETRY_128_64; + textAlignment = TEXT_ALIGN_LEFT; + fontData = ArialMT_Plain_10; + fontTableLookupFunction = DefaultFontTableLookup; + buffer = NULL; +#ifdef OLEDDISPLAY_DOUBLE_BUFFER + buffer_back = NULL; +#endif +} + +OLEDDisplay::~OLEDDisplay() { + end(); +} + +bool OLEDDisplay::init() { + + logBufferSize = 0; + logBufferFilled = 0; + logBufferLine = 0; + logBufferMaxLines = 0; + logBuffer = NULL; + + if (!this->connect()) { + DEBUG_OLEDDISPLAY("[OLEDDISPLAY][init] Can't establish connection to display\n"); + return false; + } + + if(this->buffer==NULL) { + this->buffer = (uint8_t*) malloc((sizeof(uint8_t) * displayBufferSize) + getBufferOffset()); + this->buffer += getBufferOffset(); + + if(!this->buffer) { + DEBUG_OLEDDISPLAY("[OLEDDISPLAY][init] Not enough memory to create display\n"); + return false; + } + } + + #ifdef OLEDDISPLAY_DOUBLE_BUFFER + if(this->buffer_back==NULL) { + this->buffer_back = (uint8_t*) malloc((sizeof(uint8_t) * displayBufferSize) + getBufferOffset()); + this->buffer_back += getBufferOffset(); + + if(!this->buffer_back) { + DEBUG_OLEDDISPLAY("[OLEDDISPLAY][init] Not enough memory to create back buffer\n"); + free(this->buffer - getBufferOffset()); + return false; + } + } + #endif + + sendInitCommands(); + resetDisplay(); + + return true; +} + +void OLEDDisplay::end() { + if (this->buffer) { free(this->buffer - getBufferOffset()); this->buffer = NULL; } + #ifdef OLEDDISPLAY_DOUBLE_BUFFER + if (this->buffer_back) { free(this->buffer_back - getBufferOffset()); this->buffer_back = NULL; } + #endif + if (this->logBuffer != NULL) { free(this->logBuffer); this->logBuffer = NULL; } +} + +void OLEDDisplay::resetDisplay(void) { + clear(); + #ifdef OLEDDISPLAY_DOUBLE_BUFFER + memset(buffer_back, 1, displayBufferSize); + #endif + display(); +} + +void OLEDDisplay::setColor(OLEDDISPLAY_COLOR color) { + this->color = color; +} + +OLEDDISPLAY_COLOR OLEDDisplay::getColor() { + return this->color; +} + +void OLEDDisplay::setPixel(int16_t x, int16_t y) { + if (x >= 0 && x < this->width() && y >= 0 && y < this->height()) { + switch (color) { + case WHITE: buffer[x + (y / 8) * this->width()] |= (1 << (y & 7)); break; + case BLACK: buffer[x + (y / 8) * this->width()] &= ~(1 << (y & 7)); break; + case INVERSE: buffer[x + (y / 8) * this->width()] ^= (1 << (y & 7)); break; + } + } +} + +void OLEDDisplay::clearPixel(int16_t x, int16_t y) { + if (x >= 0 && x < this->width() && y >= 0 && y < this->height()) { + switch (color) { + case BLACK: buffer[x + (y / 8) * this->width()] |= (1 << (y & 7)); break; + case WHITE: buffer[x + (y / 8) * this->width()] &= ~(1 << (y & 7)); break; + case INVERSE: buffer[x + (y / 8) * this->width()] ^= (1 << (y & 7)); break; + } + } +} + + +// Bresenham's algorithm - thx wikipedia and Adafruit_GFX +void OLEDDisplay::drawLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1) { + int16_t steep = abs(y1 - y0) > abs(x1 - x0); + if (steep) { + _swap_int16_t(x0, y0); + _swap_int16_t(x1, y1); + } + + if (x0 > x1) { + _swap_int16_t(x0, x1); + _swap_int16_t(y0, y1); + } + + int16_t dx, dy; + dx = x1 - x0; + dy = abs(y1 - y0); + + int16_t err = dx / 2; + int16_t ystep; + + if (y0 < y1) { + ystep = 1; + } else { + ystep = -1; + } + + for (; x0<=x1; x0++) { + if (steep) { + setPixel(y0, x0); + } else { + setPixel(x0, y0); + } + err -= dy; + if (err < 0) { + y0 += ystep; + err += dx; + } + } +} + +void OLEDDisplay::drawRect(int16_t x, int16_t y, int16_t width, int16_t height) { + drawHorizontalLine(x, y, width); + drawVerticalLine(x, y, height); + drawVerticalLine(x + width - 1, y, height); + drawHorizontalLine(x, y + height - 1, width); +} + +void OLEDDisplay::fillRect(int16_t xMove, int16_t yMove, int16_t width, int16_t height) { + for (int16_t x = xMove; x < xMove + width; x++) { + drawVerticalLine(x, yMove, height); + } +} + +void OLEDDisplay::drawCircle(int16_t x0, int16_t y0, int16_t radius) { + int16_t x = 0, y = radius; + int16_t dp = 1 - radius; + do { + if (dp < 0) + dp = dp + 2 * (x++) + 3; + else + dp = dp + 2 * (x++) - 2 * (y--) + 5; + + setPixel(x0 + x, y0 + y); //For the 8 octants + setPixel(x0 - x, y0 + y); + setPixel(x0 + x, y0 - y); + setPixel(x0 - x, y0 - y); + setPixel(x0 + y, y0 + x); + setPixel(x0 - y, y0 + x); + setPixel(x0 + y, y0 - x); + setPixel(x0 - y, y0 - x); + + } while (x < y); + + setPixel(x0 + radius, y0); + setPixel(x0, y0 + radius); + setPixel(x0 - radius, y0); + setPixel(x0, y0 - radius); +} + +void OLEDDisplay::drawCircleQuads(int16_t x0, int16_t y0, int16_t radius, uint8_t quads) { + int16_t x = 0, y = radius; + int16_t dp = 1 - radius; + while (x < y) { + if (dp < 0) + dp = dp + 2 * (x++) + 3; + else + dp = dp + 2 * (x++) - 2 * (y--) + 5; + if (quads & 0x1) { + setPixel(x0 + x, y0 - y); + setPixel(x0 + y, y0 - x); + } + if (quads & 0x2) { + setPixel(x0 - y, y0 - x); + setPixel(x0 - x, y0 - y); + } + if (quads & 0x4) { + setPixel(x0 - y, y0 + x); + setPixel(x0 - x, y0 + y); + } + if (quads & 0x8) { + setPixel(x0 + x, y0 + y); + setPixel(x0 + y, y0 + x); + } + } + if (quads & 0x1 && quads & 0x8) { + setPixel(x0 + radius, y0); + } + if (quads & 0x4 && quads & 0x8) { + setPixel(x0, y0 + radius); + } + if (quads & 0x2 && quads & 0x4) { + setPixel(x0 - radius, y0); + } + if (quads & 0x1 && quads & 0x2) { + setPixel(x0, y0 - radius); + } +} + + +void OLEDDisplay::fillCircle(int16_t x0, int16_t y0, int16_t radius) { + int16_t x = 0, y = radius; + int16_t dp = 1 - radius; + do { + if (dp < 0) + dp = dp + 2 * (x++) + 3; + else + dp = dp + 2 * (x++) - 2 * (y--) + 5; + + drawHorizontalLine(x0 - x, y0 - y, 2*x); + drawHorizontalLine(x0 - x, y0 + y, 2*x); + drawHorizontalLine(x0 - y, y0 - x, 2*y); + drawHorizontalLine(x0 - y, y0 + x, 2*y); + + + } while (x < y); + drawHorizontalLine(x0 - radius, y0, 2 * radius); + +} + +void OLEDDisplay::drawHorizontalLine(int16_t x, int16_t y, int16_t length) { + if (y < 0 || y >= this->height()) { return; } + + if (x < 0) { + length += x; + x = 0; + } + + if ( (x + length) > this->width()) { + length = (this->width() - x); + } + + if (length <= 0) { return; } + + uint8_t * bufferPtr = buffer; + bufferPtr += (y >> 3) * this->width(); + bufferPtr += x; + + uint8_t drawBit = 1 << (y & 7); + + switch (color) { + case WHITE: while (length--) { + *bufferPtr++ |= drawBit; + }; break; + case BLACK: drawBit = ~drawBit; while (length--) { + *bufferPtr++ &= drawBit; + }; break; + case INVERSE: while (length--) { + *bufferPtr++ ^= drawBit; + }; break; + } +} + +void OLEDDisplay::drawVerticalLine(int16_t x, int16_t y, int16_t length) { + if (x < 0 || x >= this->width()) return; + + if (y < 0) { + length += y; + y = 0; + } + + if ( (y + length) > this->height()) { + length = (this->height() - y); + } + + if (length <= 0) return; + + + uint8_t yOffset = y & 7; + uint8_t drawBit; + uint8_t *bufferPtr = buffer; + + bufferPtr += (y >> 3) * this->width(); + bufferPtr += x; + + if (yOffset) { + yOffset = 8 - yOffset; + drawBit = ~(0xFF >> (yOffset)); + + if (length < yOffset) { + drawBit &= (0xFF >> (yOffset - length)); + } + + switch (color) { + case WHITE: *bufferPtr |= drawBit; break; + case BLACK: *bufferPtr &= ~drawBit; break; + case INVERSE: *bufferPtr ^= drawBit; break; + } + + if (length < yOffset) return; + + length -= yOffset; + bufferPtr += this->width(); + } + + if (length >= 8) { + switch (color) { + case WHITE: + case BLACK: + drawBit = (color == WHITE) ? 0xFF : 0x00; + do { + *bufferPtr = drawBit; + bufferPtr += this->width(); + length -= 8; + } while (length >= 8); + break; + case INVERSE: + do { + *bufferPtr = ~(*bufferPtr); + bufferPtr += this->width(); + length -= 8; + } while (length >= 8); + break; + } + } + + if (length > 0) { + drawBit = (1 << (length & 7)) - 1; + switch (color) { + case WHITE: *bufferPtr |= drawBit; break; + case BLACK: *bufferPtr &= ~drawBit; break; + case INVERSE: *bufferPtr ^= drawBit; break; + } + } +} + +void OLEDDisplay::drawProgressBar(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint8_t progress) { + uint16_t radius = height / 2; + uint16_t xRadius = x + radius; + uint16_t yRadius = y + radius; + uint16_t doubleRadius = 2 * radius; + uint16_t innerRadius = radius - 2; + + setColor(WHITE); + drawCircleQuads(xRadius, yRadius, radius, 0b00000110); + drawHorizontalLine(xRadius, y, width - doubleRadius + 1); + drawHorizontalLine(xRadius, y + height, width - doubleRadius + 1); + drawCircleQuads(x + width - radius, yRadius, radius, 0b00001001); + + uint16_t maxProgressWidth = (width - doubleRadius + 1) * progress / 100; + + fillCircle(xRadius, yRadius, innerRadius); + fillRect(xRadius + 1, y + 2, maxProgressWidth, height - 3); + fillCircle(xRadius + maxProgressWidth, yRadius, innerRadius); +} + +void OLEDDisplay::drawFastImage(int16_t xMove, int16_t yMove, int16_t width, int16_t height, const uint8_t *image) { + drawInternal(xMove, yMove, width, height, image, 0, 0); +} + +void OLEDDisplay::drawXbm(int16_t xMove, int16_t yMove, int16_t width, int16_t height, const uint8_t *xbm) { + int16_t widthInXbm = (width + 7) / 8; + uint8_t data = 0; + + for(int16_t y = 0; y < height; y++) { + for(int16_t x = 0; x < width; x++ ) { + if (x & 7) { + data >>= 1; // Move a bit + } else { // Read new data every 8 bit + data = pgm_read_byte(xbm + (x / 8) + y * widthInXbm); + } + // if there is a bit draw it + if (data & 0x01) { + setPixel(xMove + x, yMove + y); + } + } + } +} + +void OLEDDisplay::drawStringInternal(int16_t xMove, int16_t yMove, char* text, uint16_t textLength, uint16_t textWidth) { + uint8_t textHeight = pgm_read_byte(fontData + HEIGHT_POS); + uint8_t firstChar = pgm_read_byte(fontData + FIRST_CHAR_POS); + uint16_t sizeOfJumpTable = pgm_read_byte(fontData + CHAR_NUM_POS) * JUMPTABLE_BYTES; + + uint16_t cursorX = 0; + uint16_t cursorY = 0; + + switch (textAlignment) { + case TEXT_ALIGN_CENTER_BOTH: + yMove -= textHeight >> 1; + // Fallthrough + case TEXT_ALIGN_CENTER: + xMove -= textWidth >> 1; // divide by 2 + break; + case TEXT_ALIGN_RIGHT: + xMove -= textWidth; + break; + case TEXT_ALIGN_LEFT: + break; + } + + // Don't draw anything if it is not on the screen. + if (xMove + textWidth < 0 || xMove > this->width() ) {return;} + if (yMove + textHeight < 0 || yMove > this->width() ) {return;} + + for (uint16_t j = 0; j < textLength; j++) { + int16_t xPos = xMove + cursorX; + int16_t yPos = yMove + cursorY; + + uint8_t code = text[j]; + if (code >= firstChar) { + uint8_t charCode = code - firstChar; + + // 4 Bytes per char code + uint8_t msbJumpToChar = pgm_read_byte( fontData + JUMPTABLE_START + charCode * JUMPTABLE_BYTES ); // MSB \ JumpAddress + uint8_t lsbJumpToChar = pgm_read_byte( fontData + JUMPTABLE_START + charCode * JUMPTABLE_BYTES + JUMPTABLE_LSB); // LSB / + uint8_t charByteSize = pgm_read_byte( fontData + JUMPTABLE_START + charCode * JUMPTABLE_BYTES + JUMPTABLE_SIZE); // Size + uint8_t currentCharWidth = pgm_read_byte( fontData + JUMPTABLE_START + charCode * JUMPTABLE_BYTES + JUMPTABLE_WIDTH); // Width + + // Test if the char is drawable + if (!(msbJumpToChar == 255 && lsbJumpToChar == 255)) { + // Get the position of the char data + uint16_t charDataPosition = JUMPTABLE_START + sizeOfJumpTable + ((msbJumpToChar << 8) + lsbJumpToChar); + drawInternal(xPos, yPos, currentCharWidth, textHeight, fontData, charDataPosition, charByteSize); + } + + cursorX += currentCharWidth; + } + } +} + + +void OLEDDisplay::drawString(int16_t xMove, int16_t yMove, String strUser) { + uint16_t lineHeight = pgm_read_byte(fontData + HEIGHT_POS); + + // char* text must be freed! + char* text = utf8ascii(strUser); + + uint16_t yOffset = 0; + // If the string should be centered vertically too + // we need to now how heigh the string is. + if (textAlignment == TEXT_ALIGN_CENTER_BOTH) { + uint16_t lb = 0; + // Find number of linebreaks in text + for (uint16_t i=0;text[i] != 0; i++) { + lb += (text[i] == 10); + } + // Calculate center + yOffset = (lb * lineHeight) / 2; + } + + uint16_t line = 0; + char* textPart = strtok(text,"\n"); + while (textPart != NULL) { + uint16_t length = strlen(textPart); + drawStringInternal(xMove, yMove - yOffset + (line++) * lineHeight, textPart, length, getStringWidth(textPart, length)); + textPart = strtok(NULL, "\n"); + } + free(text); +} + +void OLEDDisplay::drawStringMaxWidth(int16_t xMove, int16_t yMove, uint16_t maxLineWidth, String strUser) { + uint16_t firstChar = pgm_read_byte(fontData + FIRST_CHAR_POS); + uint16_t lineHeight = pgm_read_byte(fontData + HEIGHT_POS); + + char* text = utf8ascii(strUser); + + uint16_t length = strlen(text); + uint16_t lastDrawnPos = 0; + uint16_t lineNumber = 0; + uint16_t strWidth = 0; + + uint16_t preferredBreakpoint = 0; + uint16_t widthAtBreakpoint = 0; + + for (uint16_t i = 0; i < length; i++) { + strWidth += pgm_read_byte(fontData + JUMPTABLE_START + (text[i] - firstChar) * JUMPTABLE_BYTES + JUMPTABLE_WIDTH); + + // Always try to break on a space or dash + if (text[i] == ' ' || text[i]== '-') { + preferredBreakpoint = i; + widthAtBreakpoint = strWidth; + } + + if (strWidth >= maxLineWidth) { + if (preferredBreakpoint == 0) { + preferredBreakpoint = i; + widthAtBreakpoint = strWidth; + } + drawStringInternal(xMove, yMove + (lineNumber++) * lineHeight , &text[lastDrawnPos], preferredBreakpoint - lastDrawnPos, widthAtBreakpoint); + lastDrawnPos = preferredBreakpoint + 1; + // It is possible that we did not draw all letters to i so we need + // to account for the width of the chars from `i - preferredBreakpoint` + // by calculating the width we did not draw yet. + strWidth = strWidth - widthAtBreakpoint; + preferredBreakpoint = 0; + } + } + + // Draw last part if needed + if (lastDrawnPos < length) { + drawStringInternal(xMove, yMove + lineNumber * lineHeight , &text[lastDrawnPos], length - lastDrawnPos, getStringWidth(&text[lastDrawnPos], length - lastDrawnPos)); + } + + free(text); +} + +uint16_t OLEDDisplay::getStringWidth(const char* text, uint16_t length) { + uint16_t firstChar = pgm_read_byte(fontData + FIRST_CHAR_POS); + + uint16_t stringWidth = 0; + uint16_t maxWidth = 0; + + while (length--) { + stringWidth += pgm_read_byte(fontData + JUMPTABLE_START + (text[length] - firstChar) * JUMPTABLE_BYTES + JUMPTABLE_WIDTH); + if (text[length] == 10) { + maxWidth = max(maxWidth, stringWidth); + stringWidth = 0; + } + } + + return max(maxWidth, stringWidth); +} + +uint16_t OLEDDisplay::getStringWidth(String strUser) { + char* text = utf8ascii(strUser); + uint16_t length = strlen(text); + uint16_t width = getStringWidth(text, length); + free(text); + return width; +} + +void OLEDDisplay::setTextAlignment(OLEDDISPLAY_TEXT_ALIGNMENT textAlignment) { + this->textAlignment = textAlignment; +} + +void OLEDDisplay::setFont(const uint8_t *fontData) { + this->fontData = fontData; +} + +void OLEDDisplay::displayOn(void) { + sendCommand(DISPLAYON); +} + +void OLEDDisplay::displayOff(void) { + sendCommand(DISPLAYOFF); +} + +void OLEDDisplay::invertDisplay(void) { + sendCommand(INVERTDISPLAY); +} + +void OLEDDisplay::normalDisplay(void) { + sendCommand(NORMALDISPLAY); +} + +void OLEDDisplay::setContrast(uint8_t contrast, uint8_t precharge, uint8_t comdetect) { + sendCommand(SETPRECHARGE); //0xD9 + sendCommand(precharge); //0xF1 default, to lower the contrast, put 1-1F + sendCommand(SETCONTRAST); + sendCommand(contrast); // 0-255 + sendCommand(SETVCOMDETECT); //0xDB, (additionally needed to lower the contrast) + sendCommand(comdetect); //0x40 default, to lower the contrast, put 0 + sendCommand(DISPLAYALLON_RESUME); + sendCommand(NORMALDISPLAY); + sendCommand(DISPLAYON); +} + +void OLEDDisplay::setBrightness(uint8_t brightness) { + uint8_t contrast = brightness; + if (brightness < 128) { + // Magic values to get a smooth/ step-free transition + contrast = brightness * 1.171; + } else { + contrast = brightness * 1.171 - 43; + } + + uint8_t precharge = 241; + if (brightness == 0) { + precharge = 0; + } + uint8_t comdetect = brightness / 8; + + setContrast(contrast, precharge, comdetect); +} + +void OLEDDisplay::resetOrientation() { + sendCommand(SEGREMAP); + sendCommand(COMSCANINC); //Reset screen rotation or mirroring +} + +void OLEDDisplay::flipScreenVertically() { + sendCommand(SEGREMAP | 0x01); + sendCommand(COMSCANDEC); //Rotate screen 180 Deg +} + +void OLEDDisplay::mirrorScreen() { + sendCommand(SEGREMAP); + sendCommand(COMSCANDEC); //Mirror screen +} + +void OLEDDisplay::clear(void) { + memset(buffer, 0, displayBufferSize); +} + +void OLEDDisplay::drawLogBuffer(uint16_t xMove, uint16_t yMove) { + uint16_t lineHeight = pgm_read_byte(fontData + HEIGHT_POS); + // Always align left + setTextAlignment(TEXT_ALIGN_LEFT); + + // State values + uint16_t length = 0; + uint16_t line = 0; + uint16_t lastPos = 0; + + for (uint16_t i=0;ilogBufferFilled;i++){ + // Everytime we have a \n print + if (this->logBuffer[i] == 10) { + length++; + // Draw string on line `line` from lastPos to length + // Passing 0 as the lenght because we are in TEXT_ALIGN_LEFT + drawStringInternal(xMove, yMove + (line++) * lineHeight, &this->logBuffer[lastPos], length, 0); + // Remember last pos + lastPos = i; + // Reset length + length = 0; + } else { + // Count chars until next linebreak + length++; + } + } + // Draw the remaining string + if (length > 0) { + drawStringInternal(xMove, yMove + line * lineHeight, &this->logBuffer[lastPos], length, 0); + } +} + +uint16_t OLEDDisplay::getWidth(void) { + return displayWidth; +} + +uint16_t OLEDDisplay::getHeight(void) { + return displayHeight; +} + +bool OLEDDisplay::setLogBuffer(uint16_t lines, uint16_t chars){ + if (logBuffer != NULL) free(logBuffer); + uint16_t size = lines * chars; + if (size > 0) { + this->logBufferLine = 0; // Lines printed + this->logBufferFilled = 0; // Nothing stored yet + this->logBufferMaxLines = lines; // Lines max printable + this->logBufferSize = size; // Total number of characters the buffer can hold + this->logBuffer = (char *) malloc(size * sizeof(uint8_t)); + if(!this->logBuffer) { + DEBUG_OLEDDISPLAY("[OLEDDISPLAY][setLogBuffer] Not enough memory to create log buffer\n"); + return false; + } + } + return true; +} + +size_t OLEDDisplay::write(uint8_t c) { + if (this->logBufferSize > 0) { + // Don't waste space on \r\n line endings, dropping \r + if (c == 13) return 1; + + // convert UTF-8 character to font table index + c = (this->fontTableLookupFunction)(c); + // drop unknown character + if (c == 0) return 1; + + bool maxLineNotReached = this->logBufferLine < this->logBufferMaxLines; + bool bufferNotFull = this->logBufferFilled < this->logBufferSize; + + // Can we write to the buffer? + if (bufferNotFull && maxLineNotReached) { + this->logBuffer[logBufferFilled] = c; + this->logBufferFilled++; + // Keep track of lines written + if (c == 10) this->logBufferLine++; + } else { + // Max line number is reached + if (!maxLineNotReached) this->logBufferLine--; + + // Find the end of the first line + uint16_t firstLineEnd = 0; + for (uint16_t i=0;ilogBufferFilled;i++) { + if (this->logBuffer[i] == 10){ + // Include last char too + firstLineEnd = i + 1; + break; + } + } + // If there was a line ending + if (firstLineEnd > 0) { + // Calculate the new logBufferFilled value + this->logBufferFilled = logBufferFilled - firstLineEnd; + // Now we move the lines infront of the buffer + memcpy(this->logBuffer, &this->logBuffer[firstLineEnd], logBufferFilled); + } else { + // Let's reuse the buffer if it was full + if (!bufferNotFull) { + this->logBufferFilled = 0; + }// else { + // Nothing to do here + //} + } + write(c); + } + } + // We are always writing all uint8_t to the buffer + return 1; +} + +size_t OLEDDisplay::write(const char* str) { + if (str == NULL) return 0; + size_t length = strlen(str); + for (size_t i = 0; i < length; i++) { + write(str[i]); + } + return length; +} + +#ifdef __MBED__ +int OLEDDisplay::_putc(int c) { + + if (!fontData) + return 1; + if (!logBufferSize) { + uint8_t textHeight = pgm_read_byte(fontData + HEIGHT_POS); + uint16_t lines = this->displayHeight / textHeight; + uint16_t chars = 2 * (this->displayWidth / textHeight); + + if (this->displayHeight % textHeight) + lines++; + if (this->displayWidth % textHeight) + chars++; + setLogBuffer(lines, chars); + } + + return this->write((uint8_t)c); +} +#endif + +// Private functions +void OLEDDisplay::setGeometry(OLEDDISPLAY_GEOMETRY g, uint16_t width, uint16_t height) { + this->geometry = g; + switch (g) { + case GEOMETRY_128_64: + this->displayWidth = 128; + this->displayHeight = 64; + break; + case GEOMETRY_128_32: + this->displayWidth = 128; + this->displayHeight = 32; + break; + case GEOMETRY_RAWMODE: + this->displayWidth = width > 0 ? width : 128; + this->displayHeight = height > 0 ? height : 64; + break; + } + this->displayBufferSize = displayWidth * displayHeight /8; +} + +void OLEDDisplay::sendInitCommands(void) { + if (geometry == GEOMETRY_RAWMODE) + return; + sendCommand(DISPLAYOFF); + sendCommand(SETDISPLAYCLOCKDIV); + sendCommand(0xF0); // Increase speed of the display max ~96Hz + sendCommand(SETMULTIPLEX); + sendCommand(this->height() - 1); + sendCommand(SETDISPLAYOFFSET); + sendCommand(0x00); + sendCommand(SETSTARTLINE); + sendCommand(CHARGEPUMP); + sendCommand(0x14); + sendCommand(MEMORYMODE); + sendCommand(0x00); + sendCommand(SEGREMAP); + sendCommand(COMSCANINC); + sendCommand(SETCOMPINS); + + if (geometry == GEOMETRY_128_64) { + sendCommand(0x12); + } else if (geometry == GEOMETRY_128_32) { + sendCommand(0x02); + } + + sendCommand(SETCONTRAST); + + if (geometry == GEOMETRY_128_64) { + sendCommand(0xCF); + } else if (geometry == GEOMETRY_128_32) { + sendCommand(0x8F); + } + + sendCommand(SETPRECHARGE); + sendCommand(0xF1); + sendCommand(SETVCOMDETECT); //0xDB, (additionally needed to lower the contrast) + sendCommand(0x40); //0x40 default, to lower the contrast, put 0 + sendCommand(DISPLAYALLON_RESUME); + sendCommand(NORMALDISPLAY); + sendCommand(0x2e); // stop scroll + sendCommand(DISPLAYON); +} + +void inline OLEDDisplay::drawInternal(int16_t xMove, int16_t yMove, int16_t width, int16_t height, const uint8_t *data, uint16_t offset, uint16_t bytesInData) { + if (width < 0 || height < 0) return; + if (yMove + height < 0 || yMove > this->height()) return; + if (xMove + width < 0 || xMove > this->width()) return; + + uint8_t rasterHeight = 1 + ((height - 1) >> 3); // fast ceil(height / 8.0) + int8_t yOffset = yMove & 7; + + bytesInData = bytesInData == 0 ? width * rasterHeight : bytesInData; + + int16_t initYMove = yMove; + int8_t initYOffset = yOffset; + + + for (uint16_t i = 0; i < bytesInData; i++) { + + // Reset if next horizontal drawing phase is started. + if ( i % rasterHeight == 0) { + yMove = initYMove; + yOffset = initYOffset; + } + + uint8_t currentByte = pgm_read_byte(data + offset + i); + + int16_t xPos = xMove + (i / rasterHeight); + int16_t yPos = ((yMove >> 3) + (i % rasterHeight)) * this->width(); + +// int16_t yScreenPos = yMove + yOffset; + int16_t dataPos = xPos + yPos; + + if (dataPos >= 0 && dataPos < displayBufferSize && + xPos >= 0 && xPos < this->width() ) { + + if (yOffset >= 0) { + switch (this->color) { + case WHITE: buffer[dataPos] |= currentByte << yOffset; break; + case BLACK: buffer[dataPos] &= ~(currentByte << yOffset); break; + case INVERSE: buffer[dataPos] ^= currentByte << yOffset; break; + } + + if (dataPos < (displayBufferSize - this->width())) { + switch (this->color) { + case WHITE: buffer[dataPos + this->width()] |= currentByte >> (8 - yOffset); break; + case BLACK: buffer[dataPos + this->width()] &= ~(currentByte >> (8 - yOffset)); break; + case INVERSE: buffer[dataPos + this->width()] ^= currentByte >> (8 - yOffset); break; + } + } + } else { + // Make new offset position + yOffset = -yOffset; + + switch (this->color) { + case WHITE: buffer[dataPos] |= currentByte >> yOffset; break; + case BLACK: buffer[dataPos] &= ~(currentByte >> yOffset); break; + case INVERSE: buffer[dataPos] ^= currentByte >> yOffset; break; + } + + // Prepare for next iteration by moving one block up + yMove -= 8; + + // and setting the new yOffset + yOffset = 8 - yOffset; + } + //yield(); + } + } +} + +// You need to free the char! +char* OLEDDisplay::utf8ascii(String str) { + uint16_t k = 0; + uint16_t length = str.length() + 1; + + // Copy the string into a char array + char* s = (char*) malloc(length * sizeof(char)); + if(!s) { + DEBUG_OLEDDISPLAY("[OLEDDISPLAY][utf8ascii] Can't allocate another char array. Drop support for UTF-8.\n"); + return (char*) str.c_str(); + } + str.toCharArray(s, length); + + length--; + + for (uint16_t i=0; i < length; i++) { + char c = (this->fontTableLookupFunction)(s[i]); + if (c!=0) { + s[k++]=c; + } + } + + s[k]=0; + + // This will leak 's' be sure to free it in the calling function. + return s; +} + +void OLEDDisplay::setFontTableLookupFunction(FontTableLookupFunction function) { + this->fontTableLookupFunction = function; +} + + +char DefaultFontTableLookup(const uint8_t ch) { + // UTF-8 to font table index converter + // Code form http://playground.arduino.cc/Main/Utf8ascii + static uint8_t LASTCHAR; + + if (ch < 128) { // Standard ASCII-set 0..0x7F handling + LASTCHAR = 0; + return ch; + } + + uint8_t last = LASTCHAR; // get last char + LASTCHAR = ch; + + switch (last) { // conversion depnding on first UTF8-character + case 0xC2: return (uint8_t) ch; + case 0xC3: return (uint8_t) (ch | 0xC0); + case 0x82: if (ch == 0xAC) return (uint8_t) 0x80; // special case Euro-symbol + } + + return (uint8_t) 0; // otherwise: return zero, if character has to be ignored +} diff --git a/libraries/SSD1306_SPI/OLEDDisplay.h b/libraries/SSD1306_SPI/OLEDDisplay.h new file mode 100644 index 00000000..d323b654 --- /dev/null +++ b/libraries/SSD1306_SPI/OLEDDisplay.h @@ -0,0 +1,333 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * Copyright (c) 2019 by Helmut Tschemernjak - www.radioshuttle.de + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + +#ifndef OLEDDISPLAY_h +#define OLEDDISPLAY_h + + +#include + + +#include "OLEDDisplayFonts.h" + +#define DEBUG_OLEDDISPLAY(...) Serial.printf( __VA_ARGS__ ) +//#define DEBUG_OLEDDISPLAY(...) dprintf("%s", __VA_ARGS__ ) + +#ifndef DEBUG_OLEDDISPLAY +#define DEBUG_OLEDDISPLAY(...) +#endif + +// Use DOUBLE BUFFERING by default +#ifndef OLEDDISPLAY_REDUCE_MEMORY +#define OLEDDISPLAY_DOUBLE_BUFFER +#endif + +// Header Values +#define JUMPTABLE_BYTES 4 + +#define JUMPTABLE_LSB 1 +#define JUMPTABLE_SIZE 2 +#define JUMPTABLE_WIDTH 3 +#define JUMPTABLE_START 4 + +#define WIDTH_POS 0 +#define HEIGHT_POS 1 +#define FIRST_CHAR_POS 2 +#define CHAR_NUM_POS 3 + + +// Display commands +#define CHARGEPUMP 0x8D +#define COLUMNADDR 0x21 +#define COMSCANDEC 0xC8 +#define COMSCANINC 0xC0 +#define DISPLAYALLON 0xA5 +#define DISPLAYALLON_RESUME 0xA4 +#define DISPLAYOFF 0xAE +#define DISPLAYON 0xAF +#define EXTERNALVCC 0x1 +#define INVERTDISPLAY 0xA7 +#define MEMORYMODE 0x20 +#define NORMALDISPLAY 0xA6 +#define PAGEADDR 0x22 +#define SEGREMAP 0xA0 +#define SETCOMPINS 0xDA +#define SETCONTRAST 0x81 +#define SETDISPLAYCLOCKDIV 0xD5 +#define SETDISPLAYOFFSET 0xD3 +#define SETHIGHCOLUMN 0x10 +#define SETLOWCOLUMN 0x00 +#define SETMULTIPLEX 0xA8 +#define SETPRECHARGE 0xD9 +#define SETSEGMENTREMAP 0xA1 +#define SETSTARTLINE 0x40 +#define SETVCOMDETECT 0xDB +#define SWITCHCAPVCC 0x2 + +#ifndef _swap_int16_t +#define _swap_int16_t(a, b) { int16_t t = a; a = b; b = t; } +#endif + +enum OLEDDISPLAY_COLOR { + BLACK = 0, + WHITE = 1, + INVERSE = 2 +}; + +enum OLEDDISPLAY_TEXT_ALIGNMENT { + TEXT_ALIGN_LEFT = 0, + TEXT_ALIGN_RIGHT = 1, + TEXT_ALIGN_CENTER = 2, + TEXT_ALIGN_CENTER_BOTH = 3 +}; + + +enum OLEDDISPLAY_GEOMETRY { + GEOMETRY_128_64 = 0, + GEOMETRY_128_32, + GEOMETRY_RAWMODE, +}; + +typedef char (*FontTableLookupFunction)(const uint8_t ch); +char DefaultFontTableLookup(const uint8_t ch); + + + +class OLEDDisplay : public Print { + + + public: + OLEDDisplay(); + virtual ~OLEDDisplay(); + + uint16_t width(void) const { return displayWidth; }; + uint16_t height(void) const { return displayHeight; }; + + // Initialize the display + bool init(); + + // Free the memory used by the display + void end(); + + // Cycle through the initialization + void resetDisplay(void); + + /* Drawing functions */ + // Sets the color of all pixel operations + void setColor(OLEDDISPLAY_COLOR color); + + // Returns the current color. + OLEDDISPLAY_COLOR getColor(); + + // Draw a pixel at given position + void setPixel(int16_t x, int16_t y); + + // Clear a pixel at given position FIXME: INVERSE is untested with this function + void clearPixel(int16_t x, int16_t y); + + // Draw a line from position 0 to position 1 + void drawLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1); + + // Draw the border of a rectangle at the given location + void drawRect(int16_t x, int16_t y, int16_t width, int16_t height); + + // Fill the rectangle + void fillRect(int16_t x, int16_t y, int16_t width, int16_t height); + + // Draw the border of a circle + void drawCircle(int16_t x, int16_t y, int16_t radius); + + // Draw all Quadrants specified in the quads bit mask + void drawCircleQuads(int16_t x0, int16_t y0, int16_t radius, uint8_t quads); + + // Fill circle + void fillCircle(int16_t x, int16_t y, int16_t radius); + + // Draw a line horizontally + void drawHorizontalLine(int16_t x, int16_t y, int16_t length); + + // Draw a line vertically + void drawVerticalLine(int16_t x, int16_t y, int16_t length); + + // Draws a rounded progress bar with the outer dimensions given by width and height. Progress is + // a unsigned byte value between 0 and 100 + void drawProgressBar(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint8_t progress); + + // Draw a bitmap in the internal image format + void drawFastImage(int16_t x, int16_t y, int16_t width, int16_t height, const uint8_t *image); + + // Draw a XBM + void drawXbm(int16_t x, int16_t y, int16_t width, int16_t height, const uint8_t *xbm); + + /* Text functions */ + + // Draws a string at the given location + void drawString(int16_t x, int16_t y, String text); + + // Draws a String with a maximum width at the given location. + // If the given String is wider than the specified width + // The text will be wrapped to the next line at a space or dash + void drawStringMaxWidth(int16_t x, int16_t y, uint16_t maxLineWidth, String text); + + // Returns the width of the const char* with the current + // font settings + uint16_t getStringWidth(const char* text, uint16_t length); + + // Convencience method for the const char version + uint16_t getStringWidth(String text); + + // Specifies relative to which anchor point + // the text is rendered. Available constants: + // TEXT_ALIGN_LEFT, TEXT_ALIGN_CENTER, TEXT_ALIGN_RIGHT, TEXT_ALIGN_CENTER_BOTH + void setTextAlignment(OLEDDISPLAY_TEXT_ALIGNMENT textAlignment); + + // Sets the current font. Available default fonts + // ArialMT_Plain_10, ArialMT_Plain_16, ArialMT_Plain_24 + void setFont(const uint8_t *fontData); + + // Set the function that will convert utf-8 to font table index + void setFontTableLookupFunction(FontTableLookupFunction function); + + /* Display functions */ + + // Turn the display on + void displayOn(void); + + // Turn the display offs + void displayOff(void); + + // Inverted display mode + void invertDisplay(void); + + // Normal display mode + void normalDisplay(void); + + // Set display contrast + // really low brightness & contrast: contrast = 10, precharge = 5, comdetect = 0 + // normal brightness & contrast: contrast = 100 + void setContrast(uint8_t contrast, uint8_t precharge = 241, uint8_t comdetect = 64); + + // Convenience method to access + void setBrightness(uint8_t); + + // Reset display rotation or mirroring + void resetOrientation(); + + // Turn the display upside down + void flipScreenVertically(); + + // Mirror the display (to be used in a mirror or as a projector) + void mirrorScreen(); + + // Write the buffer to the display memory + virtual void display(void) = 0; + + // Clear the local pixel buffer + void clear(void); + + // Log buffer implementation + + // This will define the lines and characters you can + // print to the screen. When you exeed the buffer size (lines * chars) + // the output may be truncated due to the size constraint. + bool setLogBuffer(uint16_t lines, uint16_t chars); + + // Draw the log buffer at position (x, y) + void drawLogBuffer(uint16_t x, uint16_t y); + + // Get screen geometry + uint16_t getWidth(void); + uint16_t getHeight(void); + + // Implement needed function to be compatible with Print class + size_t write(uint8_t c); + size_t write(const char* s); + + // Implement needed function to be compatible with Stream class +#ifdef __MBED__ + int _putc(int c); + int _getc() { return -1; }; +#endif + + + uint8_t *buffer; + + #ifdef OLEDDISPLAY_DOUBLE_BUFFER + uint8_t *buffer_back; + #endif + + protected: + + OLEDDISPLAY_GEOMETRY geometry; + + uint16_t displayWidth; + uint16_t displayHeight; + uint16_t displayBufferSize; + + // Set the correct height, width and buffer for the geometry + void setGeometry(OLEDDISPLAY_GEOMETRY g, uint16_t width = 0, uint16_t height = 0); + + OLEDDISPLAY_TEXT_ALIGNMENT textAlignment; + OLEDDISPLAY_COLOR color; + + const uint8_t *fontData; + + // State values for logBuffer + uint16_t logBufferSize; + uint16_t logBufferFilled; + uint16_t logBufferLine; + uint16_t logBufferMaxLines; + char *logBuffer; + + + // the header size of the buffer used, e.g. for the SPI command header + virtual int getBufferOffset(void) = 0; + + // Send a command to the display (low level function) + virtual void sendCommand(uint8_t com) {(void)com;}; + + // Connect to the display + virtual bool connect() { return false; }; + + // Send all the init commands + void sendInitCommands(); + + // converts utf8 characters to extended ascii + char* utf8ascii(String s); + + void inline drawInternal(int16_t xMove, int16_t yMove, int16_t width, int16_t height, const uint8_t *data, uint16_t offset, uint16_t bytesInData) __attribute__((always_inline)); + + void drawStringInternal(int16_t xMove, int16_t yMove, char* text, uint16_t textLength, uint16_t textWidth); + + FontTableLookupFunction fontTableLookupFunction; +}; + +#endif diff --git a/libraries/SSD1306_SPI/OLEDDisplayFonts.h b/libraries/SSD1306_SPI/OLEDDisplayFonts.h new file mode 100644 index 00000000..abc61ba1 --- /dev/null +++ b/libraries/SSD1306_SPI/OLEDDisplayFonts.h @@ -0,0 +1,1278 @@ +#ifndef OLEDDISPLAYFONTS_h +#define OLEDDISPLAYFONTS_h + +#ifdef __MBED__ +#define PROGMEM +#endif + +const uint8_t ArialMT_Plain_10[] PROGMEM = { + 0x0A, // Width: 10 + 0x0D, // Height: 13 + 0x20, // First Char: 32 + 0xE0, // Numbers of Chars: 224 + + // Jump Table: + 0xFF, 0xFF, 0x00, 0x03, // 32:65535 + 0x00, 0x00, 0x04, 0x03, // 33:0 + 0x00, 0x04, 0x05, 0x04, // 34:4 + 0x00, 0x09, 0x09, 0x06, // 35:9 + 0x00, 0x12, 0x0A, 0x06, // 36:18 + 0x00, 0x1C, 0x10, 0x09, // 37:28 + 0x00, 0x2C, 0x0E, 0x07, // 38:44 + 0x00, 0x3A, 0x01, 0x02, // 39:58 + 0x00, 0x3B, 0x06, 0x03, // 40:59 + 0x00, 0x41, 0x06, 0x03, // 41:65 + 0x00, 0x47, 0x05, 0x04, // 42:71 + 0x00, 0x4C, 0x09, 0x06, // 43:76 + 0x00, 0x55, 0x04, 0x03, // 44:85 + 0x00, 0x59, 0x03, 0x03, // 45:89 + 0x00, 0x5C, 0x04, 0x03, // 46:92 + 0x00, 0x60, 0x05, 0x03, // 47:96 + 0x00, 0x65, 0x0A, 0x06, // 48:101 + 0x00, 0x6F, 0x08, 0x06, // 49:111 + 0x00, 0x77, 0x0A, 0x06, // 50:119 + 0x00, 0x81, 0x0A, 0x06, // 51:129 + 0x00, 0x8B, 0x0B, 0x06, // 52:139 + 0x00, 0x96, 0x0A, 0x06, // 53:150 + 0x00, 0xA0, 0x0A, 0x06, // 54:160 + 0x00, 0xAA, 0x09, 0x06, // 55:170 + 0x00, 0xB3, 0x0A, 0x06, // 56:179 + 0x00, 0xBD, 0x0A, 0x06, // 57:189 + 0x00, 0xC7, 0x04, 0x03, // 58:199 + 0x00, 0xCB, 0x04, 0x03, // 59:203 + 0x00, 0xCF, 0x0A, 0x06, // 60:207 + 0x00, 0xD9, 0x09, 0x06, // 61:217 + 0x00, 0xE2, 0x09, 0x06, // 62:226 + 0x00, 0xEB, 0x0B, 0x06, // 63:235 + 0x00, 0xF6, 0x14, 0x0A, // 64:246 + 0x01, 0x0A, 0x0E, 0x07, // 65:266 + 0x01, 0x18, 0x0C, 0x07, // 66:280 + 0x01, 0x24, 0x0C, 0x07, // 67:292 + 0x01, 0x30, 0x0B, 0x07, // 68:304 + 0x01, 0x3B, 0x0C, 0x07, // 69:315 + 0x01, 0x47, 0x09, 0x06, // 70:327 + 0x01, 0x50, 0x0D, 0x08, // 71:336 + 0x01, 0x5D, 0x0C, 0x07, // 72:349 + 0x01, 0x69, 0x04, 0x03, // 73:361 + 0x01, 0x6D, 0x08, 0x05, // 74:365 + 0x01, 0x75, 0x0E, 0x07, // 75:373 + 0x01, 0x83, 0x0C, 0x06, // 76:387 + 0x01, 0x8F, 0x10, 0x08, // 77:399 + 0x01, 0x9F, 0x0C, 0x07, // 78:415 + 0x01, 0xAB, 0x0E, 0x08, // 79:427 + 0x01, 0xB9, 0x0B, 0x07, // 80:441 + 0x01, 0xC4, 0x0E, 0x08, // 81:452 + 0x01, 0xD2, 0x0C, 0x07, // 82:466 + 0x01, 0xDE, 0x0C, 0x07, // 83:478 + 0x01, 0xEA, 0x0B, 0x06, // 84:490 + 0x01, 0xF5, 0x0C, 0x07, // 85:501 + 0x02, 0x01, 0x0D, 0x07, // 86:513 + 0x02, 0x0E, 0x11, 0x09, // 87:526 + 0x02, 0x1F, 0x0E, 0x07, // 88:543 + 0x02, 0x2D, 0x0D, 0x07, // 89:557 + 0x02, 0x3A, 0x0C, 0x06, // 90:570 + 0x02, 0x46, 0x06, 0x03, // 91:582 + 0x02, 0x4C, 0x06, 0x03, // 92:588 + 0x02, 0x52, 0x04, 0x03, // 93:594 + 0x02, 0x56, 0x09, 0x05, // 94:598 + 0x02, 0x5F, 0x0C, 0x06, // 95:607 + 0x02, 0x6B, 0x03, 0x03, // 96:619 + 0x02, 0x6E, 0x0A, 0x06, // 97:622 + 0x02, 0x78, 0x0A, 0x06, // 98:632 + 0x02, 0x82, 0x0A, 0x05, // 99:642 + 0x02, 0x8C, 0x0A, 0x06, // 100:652 + 0x02, 0x96, 0x0A, 0x06, // 101:662 + 0x02, 0xA0, 0x05, 0x03, // 102:672 + 0x02, 0xA5, 0x0A, 0x06, // 103:677 + 0x02, 0xAF, 0x0A, 0x06, // 104:687 + 0x02, 0xB9, 0x04, 0x02, // 105:697 + 0x02, 0xBD, 0x04, 0x02, // 106:701 + 0x02, 0xC1, 0x08, 0x05, // 107:705 + 0x02, 0xC9, 0x04, 0x02, // 108:713 + 0x02, 0xCD, 0x10, 0x08, // 109:717 + 0x02, 0xDD, 0x0A, 0x06, // 110:733 + 0x02, 0xE7, 0x0A, 0x06, // 111:743 + 0x02, 0xF1, 0x0A, 0x06, // 112:753 + 0x02, 0xFB, 0x0A, 0x06, // 113:763 + 0x03, 0x05, 0x05, 0x03, // 114:773 + 0x03, 0x0A, 0x08, 0x05, // 115:778 + 0x03, 0x12, 0x06, 0x03, // 116:786 + 0x03, 0x18, 0x0A, 0x06, // 117:792 + 0x03, 0x22, 0x09, 0x05, // 118:802 + 0x03, 0x2B, 0x0E, 0x07, // 119:811 + 0x03, 0x39, 0x0A, 0x05, // 120:825 + 0x03, 0x43, 0x09, 0x05, // 121:835 + 0x03, 0x4C, 0x0A, 0x05, // 122:844 + 0x03, 0x56, 0x06, 0x03, // 123:854 + 0x03, 0x5C, 0x04, 0x03, // 124:860 + 0x03, 0x60, 0x05, 0x03, // 125:864 + 0x03, 0x65, 0x09, 0x06, // 126:869 + 0xFF, 0xFF, 0x00, 0x00, // 127:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 128:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 129:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 130:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 131:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 132:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 133:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 134:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 135:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 136:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 137:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 138:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 139:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 140:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 141:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 142:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 143:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 144:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 145:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 146:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 147:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 148:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 149:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 150:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 151:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 152:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 153:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 154:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 155:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 156:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 157:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 158:65535 + 0xFF, 0xFF, 0x00, 0x0A, // 159:65535 + 0xFF, 0xFF, 0x00, 0x03, // 160:65535 + 0x03, 0x6E, 0x04, 0x03, // 161:878 + 0x03, 0x72, 0x0A, 0x06, // 162:882 + 0x03, 0x7C, 0x0C, 0x06, // 163:892 + 0x03, 0x88, 0x0A, 0x06, // 164:904 + 0x03, 0x92, 0x0A, 0x06, // 165:914 + 0x03, 0x9C, 0x04, 0x03, // 166:924 + 0x03, 0xA0, 0x0A, 0x06, // 167:928 + 0x03, 0xAA, 0x05, 0x03, // 168:938 + 0x03, 0xAF, 0x0D, 0x07, // 169:943 + 0x03, 0xBC, 0x07, 0x04, // 170:956 + 0x03, 0xC3, 0x0A, 0x06, // 171:963 + 0x03, 0xCD, 0x09, 0x06, // 172:973 + 0x03, 0xD6, 0x03, 0x03, // 173:982 + 0x03, 0xD9, 0x0D, 0x07, // 174:985 + 0x03, 0xE6, 0x0B, 0x06, // 175:998 + 0x03, 0xF1, 0x07, 0x04, // 176:1009 + 0x03, 0xF8, 0x0A, 0x05, // 177:1016 + 0x04, 0x02, 0x05, 0x03, // 178:1026 + 0x04, 0x07, 0x05, 0x03, // 179:1031 + 0x04, 0x0C, 0x05, 0x03, // 180:1036 + 0x04, 0x11, 0x0A, 0x06, // 181:1041 + 0x04, 0x1B, 0x09, 0x05, // 182:1051 + 0x04, 0x24, 0x03, 0x03, // 183:1060 + 0x04, 0x27, 0x06, 0x03, // 184:1063 + 0x04, 0x2D, 0x05, 0x03, // 185:1069 + 0x04, 0x32, 0x07, 0x04, // 186:1074 + 0x04, 0x39, 0x0A, 0x06, // 187:1081 + 0x04, 0x43, 0x10, 0x08, // 188:1091 + 0x04, 0x53, 0x10, 0x08, // 189:1107 + 0x04, 0x63, 0x10, 0x08, // 190:1123 + 0x04, 0x73, 0x0A, 0x06, // 191:1139 + 0x04, 0x7D, 0x0E, 0x07, // 192:1149 + 0x04, 0x8B, 0x0E, 0x07, // 193:1163 + 0x04, 0x99, 0x0E, 0x07, // 194:1177 + 0x04, 0xA7, 0x0E, 0x07, // 195:1191 + 0x04, 0xB5, 0x0E, 0x07, // 196:1205 + 0x04, 0xC3, 0x0E, 0x07, // 197:1219 + 0x04, 0xD1, 0x12, 0x0A, // 198:1233 + 0x04, 0xE3, 0x0C, 0x07, // 199:1251 + 0x04, 0xEF, 0x0C, 0x07, // 200:1263 + 0x04, 0xFB, 0x0C, 0x07, // 201:1275 + 0x05, 0x07, 0x0C, 0x07, // 202:1287 + 0x05, 0x13, 0x0C, 0x07, // 203:1299 + 0x05, 0x1F, 0x05, 0x03, // 204:1311 + 0x05, 0x24, 0x04, 0x03, // 205:1316 + 0x05, 0x28, 0x04, 0x03, // 206:1320 + 0x05, 0x2C, 0x05, 0x03, // 207:1324 + 0x05, 0x31, 0x0B, 0x07, // 208:1329 + 0x05, 0x3C, 0x0C, 0x07, // 209:1340 + 0x05, 0x48, 0x0E, 0x08, // 210:1352 + 0x05, 0x56, 0x0E, 0x08, // 211:1366 + 0x05, 0x64, 0x0E, 0x08, // 212:1380 + 0x05, 0x72, 0x0E, 0x08, // 213:1394 + 0x05, 0x80, 0x0E, 0x08, // 214:1408 + 0x05, 0x8E, 0x0A, 0x06, // 215:1422 + 0x05, 0x98, 0x0D, 0x08, // 216:1432 + 0x05, 0xA5, 0x0C, 0x07, // 217:1445 + 0x05, 0xB1, 0x0C, 0x07, // 218:1457 + 0x05, 0xBD, 0x0C, 0x07, // 219:1469 + 0x05, 0xC9, 0x0C, 0x07, // 220:1481 + 0x05, 0xD5, 0x0D, 0x07, // 221:1493 + 0x05, 0xE2, 0x0B, 0x07, // 222:1506 + 0x05, 0xED, 0x0C, 0x06, // 223:1517 + 0x05, 0xF9, 0x0A, 0x06, // 224:1529 + 0x06, 0x03, 0x0A, 0x06, // 225:1539 + 0x06, 0x0D, 0x0A, 0x06, // 226:1549 + 0x06, 0x17, 0x0A, 0x06, // 227:1559 + 0x06, 0x21, 0x0A, 0x06, // 228:1569 + 0x06, 0x2B, 0x0A, 0x06, // 229:1579 + 0x06, 0x35, 0x10, 0x09, // 230:1589 + 0x06, 0x45, 0x0A, 0x05, // 231:1605 + 0x06, 0x4F, 0x0A, 0x06, // 232:1615 + 0x06, 0x59, 0x0A, 0x06, // 233:1625 + 0x06, 0x63, 0x0A, 0x06, // 234:1635 + 0x06, 0x6D, 0x0A, 0x06, // 235:1645 + 0x06, 0x77, 0x05, 0x03, // 236:1655 + 0x06, 0x7C, 0x04, 0x03, // 237:1660 + 0x06, 0x80, 0x05, 0x03, // 238:1664 + 0x06, 0x85, 0x05, 0x03, // 239:1669 + 0x06, 0x8A, 0x0A, 0x06, // 240:1674 + 0x06, 0x94, 0x0A, 0x06, // 241:1684 + 0x06, 0x9E, 0x0A, 0x06, // 242:1694 + 0x06, 0xA8, 0x0A, 0x06, // 243:1704 + 0x06, 0xB2, 0x0A, 0x06, // 244:1714 + 0x06, 0xBC, 0x0A, 0x06, // 245:1724 + 0x06, 0xC6, 0x0A, 0x06, // 246:1734 + 0x06, 0xD0, 0x09, 0x05, // 247:1744 + 0x06, 0xD9, 0x0A, 0x06, // 248:1753 + 0x06, 0xE3, 0x0A, 0x06, // 249:1763 + 0x06, 0xED, 0x0A, 0x06, // 250:1773 + 0x06, 0xF7, 0x0A, 0x06, // 251:1783 + 0x07, 0x01, 0x0A, 0x06, // 252:1793 + 0x07, 0x0B, 0x09, 0x05, // 253:1803 + 0x07, 0x14, 0x0A, 0x06, // 254:1812 + 0x07, 0x1E, 0x09, 0x05, // 255:1822 + + // Font Data: + 0x00,0x00,0xF8,0x02, // 33 + 0x38,0x00,0x00,0x00,0x38, // 34 + 0xA0,0x03,0xE0,0x00,0xB8,0x03,0xE0,0x00,0xB8, // 35 + 0x30,0x01,0x28,0x02,0xF8,0x07,0x48,0x02,0x90,0x01, // 36 + 0x00,0x00,0x30,0x00,0x48,0x00,0x30,0x03,0xC0,0x00,0xB0,0x01,0x48,0x02,0x80,0x01, // 37 + 0x80,0x01,0x50,0x02,0x68,0x02,0xA8,0x02,0x18,0x01,0x80,0x03,0x80,0x02, // 38 + 0x38, // 39 + 0xE0,0x03,0x10,0x04,0x08,0x08, // 40 + 0x08,0x08,0x10,0x04,0xE0,0x03, // 41 + 0x28,0x00,0x18,0x00,0x28, // 42 + 0x40,0x00,0x40,0x00,0xF0,0x01,0x40,0x00,0x40, // 43 + 0x00,0x00,0x00,0x06, // 44 + 0x80,0x00,0x80, // 45 + 0x00,0x00,0x00,0x02, // 46 + 0x00,0x03,0xE0,0x00,0x18, // 47 + 0xF0,0x01,0x08,0x02,0x08,0x02,0x08,0x02,0xF0,0x01, // 48 + 0x00,0x00,0x20,0x00,0x10,0x00,0xF8,0x03, // 49 + 0x10,0x02,0x08,0x03,0x88,0x02,0x48,0x02,0x30,0x02, // 50 + 0x10,0x01,0x08,0x02,0x48,0x02,0x48,0x02,0xB0,0x01, // 51 + 0xC0,0x00,0xA0,0x00,0x90,0x00,0x88,0x00,0xF8,0x03,0x80, // 52 + 0x60,0x01,0x38,0x02,0x28,0x02,0x28,0x02,0xC8,0x01, // 53 + 0xF0,0x01,0x28,0x02,0x28,0x02,0x28,0x02,0xD0,0x01, // 54 + 0x08,0x00,0x08,0x03,0xC8,0x00,0x38,0x00,0x08, // 55 + 0xB0,0x01,0x48,0x02,0x48,0x02,0x48,0x02,0xB0,0x01, // 56 + 0x70,0x01,0x88,0x02,0x88,0x02,0x88,0x02,0xF0,0x01, // 57 + 0x00,0x00,0x20,0x02, // 58 + 0x00,0x00,0x20,0x06, // 59 + 0x00,0x00,0x40,0x00,0xA0,0x00,0xA0,0x00,0x10,0x01, // 60 + 0xA0,0x00,0xA0,0x00,0xA0,0x00,0xA0,0x00,0xA0, // 61 + 0x00,0x00,0x10,0x01,0xA0,0x00,0xA0,0x00,0x40, // 62 + 0x10,0x00,0x08,0x00,0x08,0x00,0xC8,0x02,0x48,0x00,0x30, // 63 + 0x00,0x00,0xC0,0x03,0x30,0x04,0xD0,0x09,0x28,0x0A,0x28,0x0A,0xC8,0x0B,0x68,0x0A,0x10,0x05,0xE0,0x04, // 64 + 0x00,0x02,0xC0,0x01,0xB0,0x00,0x88,0x00,0xB0,0x00,0xC0,0x01,0x00,0x02, // 65 + 0x00,0x00,0xF8,0x03,0x48,0x02,0x48,0x02,0x48,0x02,0xF0,0x01, // 66 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x08,0x02,0x08,0x02,0x10,0x01, // 67 + 0x00,0x00,0xF8,0x03,0x08,0x02,0x08,0x02,0x10,0x01,0xE0, // 68 + 0x00,0x00,0xF8,0x03,0x48,0x02,0x48,0x02,0x48,0x02,0x48,0x02, // 69 + 0x00,0x00,0xF8,0x03,0x48,0x00,0x48,0x00,0x08, // 70 + 0x00,0x00,0xE0,0x00,0x10,0x01,0x08,0x02,0x48,0x02,0x50,0x01,0xC0, // 71 + 0x00,0x00,0xF8,0x03,0x40,0x00,0x40,0x00,0x40,0x00,0xF8,0x03, // 72 + 0x00,0x00,0xF8,0x03, // 73 + 0x00,0x03,0x00,0x02,0x00,0x02,0xF8,0x01, // 74 + 0x00,0x00,0xF8,0x03,0x80,0x00,0x60,0x00,0x90,0x00,0x08,0x01,0x00,0x02, // 75 + 0x00,0x00,0xF8,0x03,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02, // 76 + 0x00,0x00,0xF8,0x03,0x30,0x00,0xC0,0x01,0x00,0x02,0xC0,0x01,0x30,0x00,0xF8,0x03, // 77 + 0x00,0x00,0xF8,0x03,0x30,0x00,0x40,0x00,0x80,0x01,0xF8,0x03, // 78 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x08,0x02,0x08,0x02,0x08,0x02,0xF0,0x01, // 79 + 0x00,0x00,0xF8,0x03,0x48,0x00,0x48,0x00,0x48,0x00,0x30, // 80 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x08,0x02,0x08,0x03,0x08,0x03,0xF0,0x02, // 81 + 0x00,0x00,0xF8,0x03,0x48,0x00,0x48,0x00,0xC8,0x00,0x30,0x03, // 82 + 0x00,0x00,0x30,0x01,0x48,0x02,0x48,0x02,0x48,0x02,0x90,0x01, // 83 + 0x00,0x00,0x08,0x00,0x08,0x00,0xF8,0x03,0x08,0x00,0x08, // 84 + 0x00,0x00,0xF8,0x01,0x00,0x02,0x00,0x02,0x00,0x02,0xF8,0x01, // 85 + 0x08,0x00,0x70,0x00,0x80,0x01,0x00,0x02,0x80,0x01,0x70,0x00,0x08, // 86 + 0x18,0x00,0xE0,0x01,0x00,0x02,0xF0,0x01,0x08,0x00,0xF0,0x01,0x00,0x02,0xE0,0x01,0x18, // 87 + 0x00,0x02,0x08,0x01,0x90,0x00,0x60,0x00,0x90,0x00,0x08,0x01,0x00,0x02, // 88 + 0x08,0x00,0x10,0x00,0x20,0x00,0xC0,0x03,0x20,0x00,0x10,0x00,0x08, // 89 + 0x08,0x03,0x88,0x02,0xC8,0x02,0x68,0x02,0x38,0x02,0x18,0x02, // 90 + 0x00,0x00,0xF8,0x0F,0x08,0x08, // 91 + 0x18,0x00,0xE0,0x00,0x00,0x03, // 92 + 0x08,0x08,0xF8,0x0F, // 93 + 0x40,0x00,0x30,0x00,0x08,0x00,0x30,0x00,0x40, // 94 + 0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x08, // 95 + 0x08,0x00,0x10, // 96 + 0x00,0x00,0x00,0x03,0xA0,0x02,0xA0,0x02,0xE0,0x03, // 97 + 0x00,0x00,0xF8,0x03,0x20,0x02,0x20,0x02,0xC0,0x01, // 98 + 0x00,0x00,0xC0,0x01,0x20,0x02,0x20,0x02,0x40,0x01, // 99 + 0x00,0x00,0xC0,0x01,0x20,0x02,0x20,0x02,0xF8,0x03, // 100 + 0x00,0x00,0xC0,0x01,0xA0,0x02,0xA0,0x02,0xC0,0x02, // 101 + 0x20,0x00,0xF0,0x03,0x28, // 102 + 0x00,0x00,0xC0,0x05,0x20,0x0A,0x20,0x0A,0xE0,0x07, // 103 + 0x00,0x00,0xF8,0x03,0x20,0x00,0x20,0x00,0xC0,0x03, // 104 + 0x00,0x00,0xE8,0x03, // 105 + 0x00,0x08,0xE8,0x07, // 106 + 0xF8,0x03,0x80,0x00,0xC0,0x01,0x20,0x02, // 107 + 0x00,0x00,0xF8,0x03, // 108 + 0x00,0x00,0xE0,0x03,0x20,0x00,0x20,0x00,0xE0,0x03,0x20,0x00,0x20,0x00,0xC0,0x03, // 109 + 0x00,0x00,0xE0,0x03,0x20,0x00,0x20,0x00,0xC0,0x03, // 110 + 0x00,0x00,0xC0,0x01,0x20,0x02,0x20,0x02,0xC0,0x01, // 111 + 0x00,0x00,0xE0,0x0F,0x20,0x02,0x20,0x02,0xC0,0x01, // 112 + 0x00,0x00,0xC0,0x01,0x20,0x02,0x20,0x02,0xE0,0x0F, // 113 + 0x00,0x00,0xE0,0x03,0x20, // 114 + 0x40,0x02,0xA0,0x02,0xA0,0x02,0x20,0x01, // 115 + 0x20,0x00,0xF8,0x03,0x20,0x02, // 116 + 0x00,0x00,0xE0,0x01,0x00,0x02,0x00,0x02,0xE0,0x03, // 117 + 0x20,0x00,0xC0,0x01,0x00,0x02,0xC0,0x01,0x20, // 118 + 0xE0,0x01,0x00,0x02,0xC0,0x01,0x20,0x00,0xC0,0x01,0x00,0x02,0xE0,0x01, // 119 + 0x20,0x02,0x40,0x01,0x80,0x00,0x40,0x01,0x20,0x02, // 120 + 0x20,0x00,0xC0,0x09,0x00,0x06,0xC0,0x01,0x20, // 121 + 0x20,0x02,0x20,0x03,0xA0,0x02,0x60,0x02,0x20,0x02, // 122 + 0x80,0x00,0x78,0x0F,0x08,0x08, // 123 + 0x00,0x00,0xF8,0x0F, // 124 + 0x08,0x08,0x78,0x0F,0x80, // 125 + 0xC0,0x00,0x40,0x00,0xC0,0x00,0x80,0x00,0xC0, // 126 + 0x00,0x00,0xA0,0x0F, // 161 + 0x00,0x00,0xC0,0x01,0xA0,0x0F,0x78,0x02,0x40,0x01, // 162 + 0x40,0x02,0x70,0x03,0xC8,0x02,0x48,0x02,0x08,0x02,0x10,0x02, // 163 + 0x00,0x00,0xE0,0x01,0x20,0x01,0x20,0x01,0xE0,0x01, // 164 + 0x48,0x01,0x70,0x01,0xC0,0x03,0x70,0x01,0x48,0x01, // 165 + 0x00,0x00,0x38,0x0F, // 166 + 0xD0,0x04,0x28,0x09,0x48,0x09,0x48,0x0A,0x90,0x05, // 167 + 0x08,0x00,0x00,0x00,0x08, // 168 + 0xE0,0x00,0x10,0x01,0x48,0x02,0xA8,0x02,0xA8,0x02,0x10,0x01,0xE0, // 169 + 0x68,0x00,0x68,0x00,0x68,0x00,0x78, // 170 + 0x00,0x00,0x80,0x01,0x40,0x02,0x80,0x01,0x40,0x02, // 171 + 0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0xE0, // 172 + 0x80,0x00,0x80, // 173 + 0xE0,0x00,0x10,0x01,0xE8,0x02,0x68,0x02,0xC8,0x02,0x10,0x01,0xE0, // 174 + 0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02, // 175 + 0x00,0x00,0x38,0x00,0x28,0x00,0x38, // 176 + 0x40,0x02,0x40,0x02,0xF0,0x03,0x40,0x02,0x40,0x02, // 177 + 0x48,0x00,0x68,0x00,0x58, // 178 + 0x48,0x00,0x58,0x00,0x68, // 179 + 0x00,0x00,0x10,0x00,0x08, // 180 + 0x00,0x00,0xE0,0x0F,0x00,0x02,0x00,0x02,0xE0,0x03, // 181 + 0x70,0x00,0xF8,0x0F,0x08,0x00,0xF8,0x0F,0x08, // 182 + 0x00,0x00,0x40, // 183 + 0x00,0x00,0x00,0x14,0x00,0x18, // 184 + 0x00,0x00,0x10,0x00,0x78, // 185 + 0x30,0x00,0x48,0x00,0x48,0x00,0x30, // 186 + 0x00,0x00,0x40,0x02,0x80,0x01,0x40,0x02,0x80,0x01, // 187 + 0x00,0x00,0x10,0x02,0x78,0x01,0xC0,0x00,0x20,0x01,0x90,0x01,0xC8,0x03,0x00,0x01, // 188 + 0x00,0x00,0x10,0x02,0x78,0x01,0x80,0x00,0x60,0x00,0x50,0x02,0x48,0x03,0xC0,0x02, // 189 + 0x48,0x00,0x58,0x00,0x68,0x03,0x80,0x00,0x60,0x01,0x90,0x01,0xC8,0x03,0x00,0x01, // 190 + 0x00,0x00,0x00,0x06,0x00,0x09,0xA0,0x09,0x00,0x04, // 191 + 0x00,0x02,0xC0,0x01,0xB0,0x00,0x89,0x00,0xB2,0x00,0xC0,0x01,0x00,0x02, // 192 + 0x00,0x02,0xC0,0x01,0xB0,0x00,0x8A,0x00,0xB1,0x00,0xC0,0x01,0x00,0x02, // 193 + 0x00,0x02,0xC0,0x01,0xB2,0x00,0x89,0x00,0xB2,0x00,0xC0,0x01,0x00,0x02, // 194 + 0x00,0x02,0xC2,0x01,0xB1,0x00,0x8A,0x00,0xB1,0x00,0xC0,0x01,0x00,0x02, // 195 + 0x00,0x02,0xC0,0x01,0xB2,0x00,0x88,0x00,0xB2,0x00,0xC0,0x01,0x00,0x02, // 196 + 0x00,0x02,0xC0,0x01,0xBE,0x00,0x8A,0x00,0xBE,0x00,0xC0,0x01,0x00,0x02, // 197 + 0x00,0x03,0xC0,0x00,0xE0,0x00,0x98,0x00,0x88,0x00,0xF8,0x03,0x48,0x02,0x48,0x02,0x48,0x02, // 198 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x08,0x16,0x08,0x1A,0x10,0x01, // 199 + 0x00,0x00,0xF8,0x03,0x49,0x02,0x4A,0x02,0x48,0x02,0x48,0x02, // 200 + 0x00,0x00,0xF8,0x03,0x48,0x02,0x4A,0x02,0x49,0x02,0x48,0x02, // 201 + 0x00,0x00,0xFA,0x03,0x49,0x02,0x4A,0x02,0x48,0x02,0x48,0x02, // 202 + 0x00,0x00,0xF8,0x03,0x4A,0x02,0x48,0x02,0x4A,0x02,0x48,0x02, // 203 + 0x00,0x00,0xF9,0x03,0x02, // 204 + 0x02,0x00,0xF9,0x03, // 205 + 0x01,0x00,0xFA,0x03, // 206 + 0x02,0x00,0xF8,0x03,0x02, // 207 + 0x40,0x00,0xF8,0x03,0x48,0x02,0x48,0x02,0x10,0x01,0xE0, // 208 + 0x00,0x00,0xFA,0x03,0x31,0x00,0x42,0x00,0x81,0x01,0xF8,0x03, // 209 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x09,0x02,0x0A,0x02,0x08,0x02,0xF0,0x01, // 210 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x0A,0x02,0x09,0x02,0x08,0x02,0xF0,0x01, // 211 + 0x00,0x00,0xF0,0x01,0x08,0x02,0x0A,0x02,0x09,0x02,0x0A,0x02,0xF0,0x01, // 212 + 0x00,0x00,0xF0,0x01,0x0A,0x02,0x09,0x02,0x0A,0x02,0x09,0x02,0xF0,0x01, // 213 + 0x00,0x00,0xF0,0x01,0x0A,0x02,0x08,0x02,0x0A,0x02,0x08,0x02,0xF0,0x01, // 214 + 0x10,0x01,0xA0,0x00,0xE0,0x00,0xA0,0x00,0x10,0x01, // 215 + 0x00,0x00,0xF0,0x02,0x08,0x03,0xC8,0x02,0x28,0x02,0x18,0x03,0xE8, // 216 + 0x00,0x00,0xF8,0x01,0x01,0x02,0x02,0x02,0x00,0x02,0xF8,0x01, // 217 + 0x00,0x00,0xF8,0x01,0x02,0x02,0x01,0x02,0x00,0x02,0xF8,0x01, // 218 + 0x00,0x00,0xF8,0x01,0x02,0x02,0x01,0x02,0x02,0x02,0xF8,0x01, // 219 + 0x00,0x00,0xF8,0x01,0x02,0x02,0x00,0x02,0x02,0x02,0xF8,0x01, // 220 + 0x08,0x00,0x10,0x00,0x20,0x00,0xC2,0x03,0x21,0x00,0x10,0x00,0x08, // 221 + 0x00,0x00,0xF8,0x03,0x10,0x01,0x10,0x01,0x10,0x01,0xE0, // 222 + 0x00,0x00,0xF0,0x03,0x08,0x01,0x48,0x02,0xB0,0x02,0x80,0x01, // 223 + 0x00,0x00,0x00,0x03,0xA4,0x02,0xA8,0x02,0xE0,0x03, // 224 + 0x00,0x00,0x00,0x03,0xA8,0x02,0xA4,0x02,0xE0,0x03, // 225 + 0x00,0x00,0x00,0x03,0xA8,0x02,0xA4,0x02,0xE8,0x03, // 226 + 0x00,0x00,0x08,0x03,0xA4,0x02,0xA8,0x02,0xE4,0x03, // 227 + 0x00,0x00,0x00,0x03,0xA8,0x02,0xA0,0x02,0xE8,0x03, // 228 + 0x00,0x00,0x00,0x03,0xAE,0x02,0xAA,0x02,0xEE,0x03, // 229 + 0x00,0x00,0x40,0x03,0xA0,0x02,0xA0,0x02,0xC0,0x01,0xA0,0x02,0xA0,0x02,0xC0,0x02, // 230 + 0x00,0x00,0xC0,0x01,0x20,0x16,0x20,0x1A,0x40,0x01, // 231 + 0x00,0x00,0xC0,0x01,0xA4,0x02,0xA8,0x02,0xC0,0x02, // 232 + 0x00,0x00,0xC0,0x01,0xA8,0x02,0xA4,0x02,0xC0,0x02, // 233 + 0x00,0x00,0xC0,0x01,0xA8,0x02,0xA4,0x02,0xC8,0x02, // 234 + 0x00,0x00,0xC0,0x01,0xA8,0x02,0xA0,0x02,0xC8,0x02, // 235 + 0x00,0x00,0xE4,0x03,0x08, // 236 + 0x08,0x00,0xE4,0x03, // 237 + 0x08,0x00,0xE4,0x03,0x08, // 238 + 0x08,0x00,0xE0,0x03,0x08, // 239 + 0x00,0x00,0xC0,0x01,0x28,0x02,0x38,0x02,0xE0,0x01, // 240 + 0x00,0x00,0xE8,0x03,0x24,0x00,0x28,0x00,0xC4,0x03, // 241 + 0x00,0x00,0xC0,0x01,0x24,0x02,0x28,0x02,0xC0,0x01, // 242 + 0x00,0x00,0xC0,0x01,0x28,0x02,0x24,0x02,0xC0,0x01, // 243 + 0x00,0x00,0xC0,0x01,0x28,0x02,0x24,0x02,0xC8,0x01, // 244 + 0x00,0x00,0xC8,0x01,0x24,0x02,0x28,0x02,0xC4,0x01, // 245 + 0x00,0x00,0xC0,0x01,0x28,0x02,0x20,0x02,0xC8,0x01, // 246 + 0x40,0x00,0x40,0x00,0x50,0x01,0x40,0x00,0x40, // 247 + 0x00,0x00,0xC0,0x02,0xA0,0x03,0x60,0x02,0xA0,0x01, // 248 + 0x00,0x00,0xE0,0x01,0x04,0x02,0x08,0x02,0xE0,0x03, // 249 + 0x00,0x00,0xE0,0x01,0x08,0x02,0x04,0x02,0xE0,0x03, // 250 + 0x00,0x00,0xE8,0x01,0x04,0x02,0x08,0x02,0xE0,0x03, // 251 + 0x00,0x00,0xE0,0x01,0x08,0x02,0x00,0x02,0xE8,0x03, // 252 + 0x20,0x00,0xC0,0x09,0x08,0x06,0xC4,0x01,0x20, // 253 + 0x00,0x00,0xF8,0x0F,0x20,0x02,0x20,0x02,0xC0,0x01, // 254 + 0x20,0x00,0xC8,0x09,0x00,0x06,0xC8,0x01,0x20 // 255 +}; + +const uint8_t ArialMT_Plain_16[] PROGMEM = { + 0x10, // Width: 16 + 0x13, // Height: 19 + 0x20, // First Char: 32 + 0xE0, // Numbers of Chars: 224 + + // Jump Table: + 0xFF, 0xFF, 0x00, 0x04, // 32:65535 + 0x00, 0x00, 0x08, 0x04, // 33:0 + 0x00, 0x08, 0x0D, 0x06, // 34:8 + 0x00, 0x15, 0x1A, 0x09, // 35:21 + 0x00, 0x2F, 0x17, 0x09, // 36:47 + 0x00, 0x46, 0x26, 0x0E, // 37:70 + 0x00, 0x6C, 0x1D, 0x0B, // 38:108 + 0x00, 0x89, 0x04, 0x03, // 39:137 + 0x00, 0x8D, 0x0C, 0x05, // 40:141 + 0x00, 0x99, 0x0B, 0x05, // 41:153 + 0x00, 0xA4, 0x0D, 0x06, // 42:164 + 0x00, 0xB1, 0x17, 0x09, // 43:177 + 0x00, 0xC8, 0x09, 0x04, // 44:200 + 0x00, 0xD1, 0x0B, 0x05, // 45:209 + 0x00, 0xDC, 0x08, 0x04, // 46:220 + 0x00, 0xE4, 0x0A, 0x04, // 47:228 + 0x00, 0xEE, 0x17, 0x09, // 48:238 + 0x01, 0x05, 0x11, 0x09, // 49:261 + 0x01, 0x16, 0x17, 0x09, // 50:278 + 0x01, 0x2D, 0x17, 0x09, // 51:301 + 0x01, 0x44, 0x17, 0x09, // 52:324 + 0x01, 0x5B, 0x17, 0x09, // 53:347 + 0x01, 0x72, 0x17, 0x09, // 54:370 + 0x01, 0x89, 0x16, 0x09, // 55:393 + 0x01, 0x9F, 0x17, 0x09, // 56:415 + 0x01, 0xB6, 0x17, 0x09, // 57:438 + 0x01, 0xCD, 0x05, 0x04, // 58:461 + 0x01, 0xD2, 0x06, 0x04, // 59:466 + 0x01, 0xD8, 0x17, 0x09, // 60:472 + 0x01, 0xEF, 0x17, 0x09, // 61:495 + 0x02, 0x06, 0x17, 0x09, // 62:518 + 0x02, 0x1D, 0x16, 0x09, // 63:541 + 0x02, 0x33, 0x2F, 0x10, // 64:563 + 0x02, 0x62, 0x1D, 0x0B, // 65:610 + 0x02, 0x7F, 0x1D, 0x0B, // 66:639 + 0x02, 0x9C, 0x20, 0x0C, // 67:668 + 0x02, 0xBC, 0x20, 0x0C, // 68:700 + 0x02, 0xDC, 0x1D, 0x0B, // 69:732 + 0x02, 0xF9, 0x19, 0x0A, // 70:761 + 0x03, 0x12, 0x20, 0x0C, // 71:786 + 0x03, 0x32, 0x1D, 0x0C, // 72:818 + 0x03, 0x4F, 0x05, 0x04, // 73:847 + 0x03, 0x54, 0x14, 0x08, // 74:852 + 0x03, 0x68, 0x1D, 0x0B, // 75:872 + 0x03, 0x85, 0x17, 0x09, // 76:901 + 0x03, 0x9C, 0x23, 0x0D, // 77:924 + 0x03, 0xBF, 0x1D, 0x0C, // 78:959 + 0x03, 0xDC, 0x20, 0x0C, // 79:988 + 0x03, 0xFC, 0x1C, 0x0B, // 80:1020 + 0x04, 0x18, 0x20, 0x0C, // 81:1048 + 0x04, 0x38, 0x1D, 0x0C, // 82:1080 + 0x04, 0x55, 0x1D, 0x0B, // 83:1109 + 0x04, 0x72, 0x19, 0x0A, // 84:1138 + 0x04, 0x8B, 0x1D, 0x0C, // 85:1163 + 0x04, 0xA8, 0x1C, 0x0B, // 86:1192 + 0x04, 0xC4, 0x2B, 0x0F, // 87:1220 + 0x04, 0xEF, 0x20, 0x0B, // 88:1263 + 0x05, 0x0F, 0x19, 0x0B, // 89:1295 + 0x05, 0x28, 0x1A, 0x0A, // 90:1320 + 0x05, 0x42, 0x0C, 0x04, // 91:1346 + 0x05, 0x4E, 0x0B, 0x04, // 92:1358 + 0x05, 0x59, 0x09, 0x04, // 93:1369 + 0x05, 0x62, 0x14, 0x08, // 94:1378 + 0x05, 0x76, 0x1B, 0x09, // 95:1398 + 0x05, 0x91, 0x07, 0x05, // 96:1425 + 0x05, 0x98, 0x17, 0x09, // 97:1432 + 0x05, 0xAF, 0x17, 0x09, // 98:1455 + 0x05, 0xC6, 0x14, 0x08, // 99:1478 + 0x05, 0xDA, 0x17, 0x09, // 100:1498 + 0x05, 0xF1, 0x17, 0x09, // 101:1521 + 0x06, 0x08, 0x0A, 0x04, // 102:1544 + 0x06, 0x12, 0x17, 0x09, // 103:1554 + 0x06, 0x29, 0x14, 0x09, // 104:1577 + 0x06, 0x3D, 0x05, 0x04, // 105:1597 + 0x06, 0x42, 0x06, 0x04, // 106:1602 + 0x06, 0x48, 0x17, 0x08, // 107:1608 + 0x06, 0x5F, 0x05, 0x04, // 108:1631 + 0x06, 0x64, 0x23, 0x0D, // 109:1636 + 0x06, 0x87, 0x14, 0x09, // 110:1671 + 0x06, 0x9B, 0x17, 0x09, // 111:1691 + 0x06, 0xB2, 0x17, 0x09, // 112:1714 + 0x06, 0xC9, 0x18, 0x09, // 113:1737 + 0x06, 0xE1, 0x0D, 0x05, // 114:1761 + 0x06, 0xEE, 0x14, 0x08, // 115:1774 + 0x07, 0x02, 0x0B, 0x04, // 116:1794 + 0x07, 0x0D, 0x14, 0x09, // 117:1805 + 0x07, 0x21, 0x13, 0x08, // 118:1825 + 0x07, 0x34, 0x1F, 0x0C, // 119:1844 + 0x07, 0x53, 0x14, 0x08, // 120:1875 + 0x07, 0x67, 0x13, 0x08, // 121:1895 + 0x07, 0x7A, 0x14, 0x08, // 122:1914 + 0x07, 0x8E, 0x0F, 0x05, // 123:1934 + 0x07, 0x9D, 0x06, 0x04, // 124:1949 + 0x07, 0xA3, 0x0E, 0x05, // 125:1955 + 0x07, 0xB1, 0x17, 0x09, // 126:1969 + 0xFF, 0xFF, 0x00, 0x00, // 127:65535 + 0xFF, 0xFF, 0x00, 0x10, // 128:65535 + 0xFF, 0xFF, 0x00, 0x10, // 129:65535 + 0xFF, 0xFF, 0x00, 0x10, // 130:65535 + 0xFF, 0xFF, 0x00, 0x10, // 131:65535 + 0xFF, 0xFF, 0x00, 0x10, // 132:65535 + 0xFF, 0xFF, 0x00, 0x10, // 133:65535 + 0xFF, 0xFF, 0x00, 0x10, // 134:65535 + 0xFF, 0xFF, 0x00, 0x10, // 135:65535 + 0xFF, 0xFF, 0x00, 0x10, // 136:65535 + 0xFF, 0xFF, 0x00, 0x10, // 137:65535 + 0xFF, 0xFF, 0x00, 0x10, // 138:65535 + 0xFF, 0xFF, 0x00, 0x10, // 139:65535 + 0xFF, 0xFF, 0x00, 0x10, // 140:65535 + 0xFF, 0xFF, 0x00, 0x10, // 141:65535 + 0xFF, 0xFF, 0x00, 0x10, // 142:65535 + 0xFF, 0xFF, 0x00, 0x10, // 143:65535 + 0xFF, 0xFF, 0x00, 0x10, // 144:65535 + 0xFF, 0xFF, 0x00, 0x10, // 145:65535 + 0xFF, 0xFF, 0x00, 0x10, // 146:65535 + 0xFF, 0xFF, 0x00, 0x10, // 147:65535 + 0xFF, 0xFF, 0x00, 0x10, // 148:65535 + 0xFF, 0xFF, 0x00, 0x10, // 149:65535 + 0xFF, 0xFF, 0x00, 0x10, // 150:65535 + 0xFF, 0xFF, 0x00, 0x10, // 151:65535 + 0xFF, 0xFF, 0x00, 0x10, // 152:65535 + 0xFF, 0xFF, 0x00, 0x10, // 153:65535 + 0xFF, 0xFF, 0x00, 0x10, // 154:65535 + 0xFF, 0xFF, 0x00, 0x10, // 155:65535 + 0xFF, 0xFF, 0x00, 0x10, // 156:65535 + 0xFF, 0xFF, 0x00, 0x10, // 157:65535 + 0xFF, 0xFF, 0x00, 0x10, // 158:65535 + 0xFF, 0xFF, 0x00, 0x10, // 159:65535 + 0xFF, 0xFF, 0x00, 0x04, // 160:65535 + 0x07, 0xC8, 0x09, 0x05, // 161:1992 + 0x07, 0xD1, 0x17, 0x09, // 162:2001 + 0x07, 0xE8, 0x17, 0x09, // 163:2024 + 0x07, 0xFF, 0x14, 0x09, // 164:2047 + 0x08, 0x13, 0x1A, 0x09, // 165:2067 + 0x08, 0x2D, 0x06, 0x04, // 166:2093 + 0x08, 0x33, 0x17, 0x09, // 167:2099 + 0x08, 0x4A, 0x07, 0x05, // 168:2122 + 0x08, 0x51, 0x23, 0x0C, // 169:2129 + 0x08, 0x74, 0x0E, 0x06, // 170:2164 + 0x08, 0x82, 0x14, 0x09, // 171:2178 + 0x08, 0x96, 0x17, 0x09, // 172:2198 + 0x08, 0xAD, 0x0B, 0x05, // 173:2221 + 0x08, 0xB8, 0x23, 0x0C, // 174:2232 + 0x08, 0xDB, 0x19, 0x09, // 175:2267 + 0x08, 0xF4, 0x0D, 0x06, // 176:2292 + 0x09, 0x01, 0x17, 0x09, // 177:2305 + 0x09, 0x18, 0x0E, 0x05, // 178:2328 + 0x09, 0x26, 0x0D, 0x05, // 179:2342 + 0x09, 0x33, 0x0A, 0x05, // 180:2355 + 0x09, 0x3D, 0x17, 0x09, // 181:2365 + 0x09, 0x54, 0x19, 0x09, // 182:2388 + 0x09, 0x6D, 0x08, 0x05, // 183:2413 + 0x09, 0x75, 0x0C, 0x05, // 184:2421 + 0x09, 0x81, 0x0B, 0x05, // 185:2433 + 0x09, 0x8C, 0x0D, 0x06, // 186:2444 + 0x09, 0x99, 0x17, 0x09, // 187:2457 + 0x09, 0xB0, 0x26, 0x0D, // 188:2480 + 0x09, 0xD6, 0x26, 0x0D, // 189:2518 + 0x09, 0xFC, 0x26, 0x0D, // 190:2556 + 0x0A, 0x22, 0x1A, 0x0A, // 191:2594 + 0x0A, 0x3C, 0x1D, 0x0B, // 192:2620 + 0x0A, 0x59, 0x1D, 0x0B, // 193:2649 + 0x0A, 0x76, 0x1D, 0x0B, // 194:2678 + 0x0A, 0x93, 0x1D, 0x0B, // 195:2707 + 0x0A, 0xB0, 0x1D, 0x0B, // 196:2736 + 0x0A, 0xCD, 0x1D, 0x0B, // 197:2765 + 0x0A, 0xEA, 0x2C, 0x10, // 198:2794 + 0x0B, 0x16, 0x20, 0x0C, // 199:2838 + 0x0B, 0x36, 0x1D, 0x0B, // 200:2870 + 0x0B, 0x53, 0x1D, 0x0B, // 201:2899 + 0x0B, 0x70, 0x1D, 0x0B, // 202:2928 + 0x0B, 0x8D, 0x1D, 0x0B, // 203:2957 + 0x0B, 0xAA, 0x05, 0x04, // 204:2986 + 0x0B, 0xAF, 0x07, 0x04, // 205:2991 + 0x0B, 0xB6, 0x0A, 0x04, // 206:2998 + 0x0B, 0xC0, 0x07, 0x04, // 207:3008 + 0x0B, 0xC7, 0x20, 0x0C, // 208:3015 + 0x0B, 0xE7, 0x1D, 0x0C, // 209:3047 + 0x0C, 0x04, 0x20, 0x0C, // 210:3076 + 0x0C, 0x24, 0x20, 0x0C, // 211:3108 + 0x0C, 0x44, 0x20, 0x0C, // 212:3140 + 0x0C, 0x64, 0x20, 0x0C, // 213:3172 + 0x0C, 0x84, 0x20, 0x0C, // 214:3204 + 0x0C, 0xA4, 0x17, 0x09, // 215:3236 + 0x0C, 0xBB, 0x20, 0x0C, // 216:3259 + 0x0C, 0xDB, 0x1D, 0x0C, // 217:3291 + 0x0C, 0xF8, 0x1D, 0x0C, // 218:3320 + 0x0D, 0x15, 0x1D, 0x0C, // 219:3349 + 0x0D, 0x32, 0x1D, 0x0C, // 220:3378 + 0x0D, 0x4F, 0x19, 0x0B, // 221:3407 + 0x0D, 0x68, 0x1D, 0x0B, // 222:3432 + 0x0D, 0x85, 0x17, 0x0A, // 223:3461 + 0x0D, 0x9C, 0x17, 0x09, // 224:3484 + 0x0D, 0xB3, 0x17, 0x09, // 225:3507 + 0x0D, 0xCA, 0x17, 0x09, // 226:3530 + 0x0D, 0xE1, 0x17, 0x09, // 227:3553 + 0x0D, 0xF8, 0x17, 0x09, // 228:3576 + 0x0E, 0x0F, 0x17, 0x09, // 229:3599 + 0x0E, 0x26, 0x29, 0x0E, // 230:3622 + 0x0E, 0x4F, 0x14, 0x08, // 231:3663 + 0x0E, 0x63, 0x17, 0x09, // 232:3683 + 0x0E, 0x7A, 0x17, 0x09, // 233:3706 + 0x0E, 0x91, 0x17, 0x09, // 234:3729 + 0x0E, 0xA8, 0x17, 0x09, // 235:3752 + 0x0E, 0xBF, 0x05, 0x04, // 236:3775 + 0x0E, 0xC4, 0x07, 0x04, // 237:3780 + 0x0E, 0xCB, 0x0A, 0x04, // 238:3787 + 0x0E, 0xD5, 0x07, 0x04, // 239:3797 + 0x0E, 0xDC, 0x17, 0x09, // 240:3804 + 0x0E, 0xF3, 0x14, 0x09, // 241:3827 + 0x0F, 0x07, 0x17, 0x09, // 242:3847 + 0x0F, 0x1E, 0x17, 0x09, // 243:3870 + 0x0F, 0x35, 0x17, 0x09, // 244:3893 + 0x0F, 0x4C, 0x17, 0x09, // 245:3916 + 0x0F, 0x63, 0x17, 0x09, // 246:3939 + 0x0F, 0x7A, 0x17, 0x09, // 247:3962 + 0x0F, 0x91, 0x17, 0x0A, // 248:3985 + 0x0F, 0xA8, 0x14, 0x09, // 249:4008 + 0x0F, 0xBC, 0x14, 0x09, // 250:4028 + 0x0F, 0xD0, 0x14, 0x09, // 251:4048 + 0x0F, 0xE4, 0x14, 0x09, // 252:4068 + 0x0F, 0xF8, 0x13, 0x08, // 253:4088 + 0x10, 0x0B, 0x17, 0x09, // 254:4107 + 0x10, 0x22, 0x13, 0x08, // 255:4130 + + // Font Data: + 0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x5F, // 33 + 0x00,0x00,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78, // 34 + 0x80,0x08,0x00,0x80,0x78,0x00,0xC0,0x0F,0x00,0xB8,0x08,0x00,0x80,0x08,0x00,0x80,0x78,0x00,0xC0,0x0F,0x00,0xB8,0x08,0x00,0x80,0x08, // 35 + 0x00,0x00,0x00,0xE0,0x10,0x00,0x10,0x21,0x00,0x08,0x41,0x00,0xFC,0xFF,0x00,0x08,0x42,0x00,0x10,0x22,0x00,0x20,0x1C, // 36 + 0x00,0x00,0x00,0xF0,0x00,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0x08,0x61,0x00,0xF0,0x18,0x00,0x00,0x06,0x00,0xC0,0x01,0x00,0x30,0x3C,0x00,0x08,0x42,0x00,0x00,0x42,0x00,0x00,0x42,0x00,0x00,0x3C, // 37 + 0x00,0x00,0x00,0x00,0x1C,0x00,0x70,0x22,0x00,0x88,0x41,0x00,0x08,0x43,0x00,0x88,0x44,0x00,0x70,0x28,0x00,0x00,0x10,0x00,0x00,0x28,0x00,0x00,0x44, // 38 + 0x00,0x00,0x00,0x78, // 39 + 0x00,0x00,0x00,0x80,0x3F,0x00,0x70,0xC0,0x01,0x08,0x00,0x02, // 40 + 0x00,0x00,0x00,0x08,0x00,0x02,0x70,0xC0,0x01,0x80,0x3F, // 41 + 0x10,0x00,0x00,0xD0,0x00,0x00,0x38,0x00,0x00,0xD0,0x00,0x00,0x10, // 42 + 0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0xC0,0x1F,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02, // 43 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x01, // 44 + 0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08, // 45 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40, // 46 + 0x00,0x60,0x00,0x00,0x1E,0x00,0xE0,0x01,0x00,0x18, // 47 + 0x00,0x00,0x00,0xE0,0x1F,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0xE0,0x1F, // 48 + 0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0xF8,0x7F, // 49 + 0x00,0x00,0x00,0x20,0x40,0x00,0x10,0x60,0x00,0x08,0x50,0x00,0x08,0x48,0x00,0x08,0x44,0x00,0x10,0x43,0x00,0xE0,0x40, // 50 + 0x00,0x00,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x88,0x41,0x00,0xF0,0x22,0x00,0x00,0x1C, // 51 + 0x00,0x0C,0x00,0x00,0x0A,0x00,0x00,0x09,0x00,0xC0,0x08,0x00,0x20,0x08,0x00,0x10,0x08,0x00,0xF8,0x7F,0x00,0x00,0x08, // 52 + 0x00,0x00,0x00,0xC0,0x11,0x00,0xB8,0x20,0x00,0x88,0x40,0x00,0x88,0x40,0x00,0x88,0x40,0x00,0x08,0x21,0x00,0x08,0x1E, // 53 + 0x00,0x00,0x00,0xE0,0x1F,0x00,0x10,0x21,0x00,0x88,0x40,0x00,0x88,0x40,0x00,0x88,0x40,0x00,0x10,0x21,0x00,0x20,0x1E, // 54 + 0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x78,0x00,0x08,0x07,0x00,0xC8,0x00,0x00,0x28,0x00,0x00,0x18, // 55 + 0x00,0x00,0x00,0x60,0x1C,0x00,0x90,0x22,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x90,0x22,0x00,0x60,0x1C, // 56 + 0x00,0x00,0x00,0xE0,0x11,0x00,0x10,0x22,0x00,0x08,0x44,0x00,0x08,0x44,0x00,0x08,0x44,0x00,0x10,0x22,0x00,0xE0,0x1F, // 57 + 0x00,0x00,0x00,0x40,0x40, // 58 + 0x00,0x00,0x00,0x40,0xC0,0x01, // 59 + 0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x05,0x00,0x00,0x05,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x40,0x10, // 60 + 0x00,0x00,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08, // 61 + 0x00,0x00,0x00,0x40,0x10,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x80,0x08,0x00,0x00,0x05,0x00,0x00,0x05,0x00,0x00,0x02, // 62 + 0x00,0x00,0x00,0x60,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x08,0x5C,0x00,0x08,0x02,0x00,0x10,0x01,0x00,0xE0, // 63 + 0x00,0x00,0x00,0x00,0x3F,0x00,0xC0,0x40,0x00,0x20,0x80,0x00,0x10,0x1E,0x01,0x10,0x21,0x01,0x88,0x40,0x02,0x48,0x40,0x02,0x48,0x40,0x02,0x48,0x20,0x02,0x88,0x7C,0x02,0xC8,0x43,0x02,0x10,0x40,0x02,0x10,0x20,0x01,0x60,0x10,0x01,0x80,0x8F, // 64 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x70,0x04,0x00,0x08,0x04,0x00,0x70,0x04,0x00,0x80,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 65 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x90,0x22,0x00,0x60,0x1C, // 66 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10, // 67 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 68 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x40, // 69 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08, // 70 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x42,0x00,0x08,0x42,0x00,0x10,0x22,0x00,0x20,0x12,0x00,0x00,0x0E, // 71 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0xF8,0x7F, // 72 + 0x00,0x00,0x00,0xF8,0x7F, // 73 + 0x00,0x00,0x00,0x00,0x38,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0xF8,0x3F, // 74 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x00,0x04,0x00,0x00,0x02,0x00,0x00,0x01,0x00,0x80,0x03,0x00,0x40,0x04,0x00,0x20,0x18,0x00,0x10,0x20,0x00,0x08,0x40, // 75 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40, // 76 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x30,0x00,0x00,0xC0,0x00,0x00,0x00,0x03,0x00,0x00,0x1C,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x00,0x03,0x00,0xC0,0x00,0x00,0x30,0x00,0x00,0xF8,0x7F, // 77 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x10,0x00,0x00,0x60,0x00,0x00,0x80,0x00,0x00,0x00,0x03,0x00,0x00,0x04,0x00,0x00,0x18,0x00,0x00,0x20,0x00,0xF8,0x7F, // 78 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 79 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x10,0x01,0x00,0xE0, // 80 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x08,0x50,0x00,0x08,0x50,0x00,0x10,0x20,0x00,0x20,0x70,0x00,0xC0,0x4F, // 81 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x02,0x00,0x08,0x06,0x00,0x08,0x1A,0x00,0x10,0x21,0x00,0xE0,0x40, // 82 + 0x00,0x00,0x00,0x60,0x10,0x00,0x90,0x20,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x42,0x00,0x08,0x42,0x00,0x10,0x22,0x00,0x20,0x1C, // 83 + 0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0xF8,0x7F,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08, // 84 + 0x00,0x00,0x00,0xF8,0x1F,0x00,0x00,0x20,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xF8,0x1F, // 85 + 0x00,0x00,0x00,0x18,0x00,0x00,0xE0,0x00,0x00,0x00,0x07,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x18,0x00,0x00,0x07,0x00,0xE0,0x00,0x00,0x18, // 86 + 0x18,0x00,0x00,0xE0,0x01,0x00,0x00,0x1E,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x03,0x00,0x70,0x00,0x00,0x08,0x00,0x00,0x70,0x00,0x00,0x80,0x03,0x00,0x00,0x1C,0x00,0x00,0x60,0x00,0x00,0x1E,0x00,0xE0,0x01,0x00,0x18, // 87 + 0x00,0x40,0x00,0x08,0x20,0x00,0x10,0x10,0x00,0x60,0x0C,0x00,0x80,0x02,0x00,0x00,0x01,0x00,0x80,0x02,0x00,0x60,0x0C,0x00,0x10,0x10,0x00,0x08,0x20,0x00,0x00,0x40, // 88 + 0x08,0x00,0x00,0x30,0x00,0x00,0x40,0x00,0x00,0x80,0x01,0x00,0x00,0x7E,0x00,0x80,0x01,0x00,0x40,0x00,0x00,0x30,0x00,0x00,0x08, // 89 + 0x00,0x40,0x00,0x08,0x60,0x00,0x08,0x58,0x00,0x08,0x44,0x00,0x08,0x43,0x00,0x88,0x40,0x00,0x68,0x40,0x00,0x18,0x40,0x00,0x08,0x40, // 90 + 0x00,0x00,0x00,0xF8,0xFF,0x03,0x08,0x00,0x02,0x08,0x00,0x02, // 91 + 0x18,0x00,0x00,0xE0,0x01,0x00,0x00,0x1E,0x00,0x00,0x60, // 92 + 0x08,0x00,0x02,0x08,0x00,0x02,0xF8,0xFF,0x03, // 93 + 0x00,0x01,0x00,0xC0,0x00,0x00,0x30,0x00,0x00,0x08,0x00,0x00,0x30,0x00,0x00,0xC0,0x00,0x00,0x00,0x01, // 94 + 0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02, // 95 + 0x00,0x00,0x00,0x08,0x00,0x00,0x10, // 96 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x42,0x00,0x40,0x22,0x00,0x80,0x7F, // 97 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 98 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20, // 99 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0xF8,0x7F, // 100 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x24,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x80,0x24,0x00,0x00,0x17, // 101 + 0x40,0x00,0x00,0xF0,0x7F,0x00,0x48,0x00,0x00,0x48, // 102 + 0x00,0x00,0x00,0x00,0x1F,0x01,0x80,0x20,0x02,0x40,0x40,0x02,0x40,0x40,0x02,0x40,0x40,0x02,0x80,0x20,0x01,0xC0,0xFF, // 103 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x80,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x80,0x7F, // 104 + 0x00,0x00,0x00,0xC8,0x7F, // 105 + 0x00,0x00,0x02,0xC8,0xFF,0x01, // 106 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x00,0x08,0x00,0x00,0x04,0x00,0x00,0x06,0x00,0x00,0x19,0x00,0x80,0x20,0x00,0x40,0x40, // 107 + 0x00,0x00,0x00,0xF8,0x7F, // 108 + 0x00,0x00,0x00,0xC0,0x7F,0x00,0x80,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x80,0x7F,0x00,0x80,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x80,0x7F, // 109 + 0x00,0x00,0x00,0xC0,0x7F,0x00,0x80,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x80,0x7F, // 110 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 111 + 0x00,0x00,0x00,0xC0,0xFF,0x03,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 112 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0xC0,0xFF,0x03, // 113 + 0x00,0x00,0x00,0xC0,0x7F,0x00,0x80,0x00,0x00,0x40,0x00,0x00,0x40, // 114 + 0x00,0x00,0x00,0x80,0x23,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x80,0x38, // 115 + 0x40,0x00,0x00,0xF0,0x7F,0x00,0x40,0x40,0x00,0x40,0x40, // 116 + 0x00,0x00,0x00,0xC0,0x3F,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xC0,0x7F, // 117 + 0xC0,0x00,0x00,0x00,0x03,0x00,0x00,0x1C,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x00,0x03,0x00,0xC0, // 118 + 0xC0,0x00,0x00,0x00,0x1F,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x00,0x03,0x00,0xC0,0x00,0x00,0x00,0x03,0x00,0x00,0x1C,0x00,0x00,0x60,0x00,0x00,0x1F,0x00,0xC0, // 119 + 0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1B,0x00,0x00,0x04,0x00,0x00,0x1B,0x00,0x80,0x20,0x00,0x40,0x40, // 120 + 0xC0,0x01,0x00,0x00,0x06,0x02,0x00,0x38,0x02,0x00,0xE0,0x01,0x00,0x38,0x00,0x00,0x07,0x00,0xC0, // 121 + 0x40,0x40,0x00,0x40,0x60,0x00,0x40,0x58,0x00,0x40,0x44,0x00,0x40,0x43,0x00,0xC0,0x40,0x00,0x40,0x40, // 122 + 0x00,0x04,0x00,0x00,0x04,0x00,0xF0,0xFB,0x01,0x08,0x00,0x02,0x08,0x00,0x02, // 123 + 0x00,0x00,0x00,0xF8,0xFF,0x03, // 124 + 0x08,0x00,0x02,0x08,0x00,0x02,0xF0,0xFB,0x01,0x00,0x04,0x00,0x00,0x04, // 125 + 0x00,0x02,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x01, // 126 + 0x00,0x00,0x00,0x00,0x00,0x00,0x40,0xFF,0x03, // 161 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x03,0x40,0xF0,0x00,0x40,0x4E,0x00,0xC0,0x41,0x00,0xB8,0x20,0x00,0x00,0x11, // 162 + 0x00,0x41,0x00,0xE0,0x31,0x00,0x10,0x2F,0x00,0x08,0x21,0x00,0x08,0x21,0x00,0x08,0x40,0x00,0x10,0x40,0x00,0x20,0x20, // 163 + 0x00,0x00,0x00,0x40,0x0B,0x00,0x80,0x04,0x00,0x40,0x08,0x00,0x40,0x08,0x00,0x80,0x04,0x00,0x40,0x0B, // 164 + 0x08,0x0A,0x00,0x10,0x0A,0x00,0x60,0x0A,0x00,0x80,0x0B,0x00,0x00,0x7E,0x00,0x80,0x0B,0x00,0x60,0x0A,0x00,0x10,0x0A,0x00,0x08,0x0A, // 165 + 0x00,0x00,0x00,0xF8,0xF1,0x03, // 166 + 0x00,0x86,0x00,0x70,0x09,0x01,0xC8,0x10,0x02,0x88,0x10,0x02,0x08,0x21,0x02,0x08,0x61,0x02,0x30,0xD2,0x01,0x00,0x0C, // 167 + 0x08,0x00,0x00,0x00,0x00,0x00,0x08, // 168 + 0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0xC8,0x47,0x00,0x28,0x48,0x00,0x28,0x48,0x00,0x28,0x48,0x00,0x28,0x48,0x00,0x48,0x44,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 169 + 0xD0,0x00,0x00,0x48,0x01,0x00,0x28,0x01,0x00,0x28,0x01,0x00,0xF0,0x01, // 170 + 0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x1B,0x00,0x80,0x20,0x00,0x00,0x04,0x00,0x00,0x1B,0x00,0x80,0x20, // 171 + 0x00,0x00,0x00,0x80,0x00,0x00,0x80,0x00,0x00,0x80,0x00,0x00,0x80,0x00,0x00,0x80,0x00,0x00,0x80,0x00,0x00,0x80,0x0F, // 172 + 0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08, // 173 + 0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0xE8,0x4F,0x00,0x28,0x41,0x00,0x28,0x41,0x00,0x28,0x43,0x00,0x28,0x45,0x00,0xC8,0x48,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 174 + 0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04, // 175 + 0x00,0x00,0x00,0x30,0x00,0x00,0x48,0x00,0x00,0x48,0x00,0x00,0x30, // 176 + 0x00,0x00,0x00,0x00,0x41,0x00,0x00,0x41,0x00,0x00,0x41,0x00,0xE0,0x4F,0x00,0x00,0x41,0x00,0x00,0x41,0x00,0x00,0x41, // 177 + 0x10,0x01,0x00,0x88,0x01,0x00,0x48,0x01,0x00,0x48,0x01,0x00,0x30,0x01, // 178 + 0x90,0x00,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0x28,0x01,0x00,0xD8, // 179 + 0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x08, // 180 + 0x00,0x00,0x00,0xC0,0xFF,0x03,0x00,0x20,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xC0,0x7F, // 181 + 0xF0,0x00,0x00,0xF8,0x00,0x00,0xF8,0x01,0x00,0xF8,0x01,0x00,0xF8,0xFF,0x03,0x08,0x00,0x00,0x08,0x00,0x00,0xF8,0xFF,0x03,0x08, // 182 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02, // 183 + 0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x80,0x02,0x00,0x00,0x03, // 184 + 0x00,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0xF8,0x01, // 185 + 0xF0,0x00,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0xF0, // 186 + 0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x20,0x00,0x00,0x1B,0x00,0x00,0x04,0x00,0x80,0x20,0x00,0x00,0x1B,0x00,0x00,0x04, // 187 + 0x00,0x00,0x00,0x10,0x00,0x00,0x08,0x40,0x00,0xF8,0x21,0x00,0x00,0x10,0x00,0x00,0x0C,0x00,0x00,0x02,0x00,0x80,0x01,0x00,0x40,0x30,0x00,0x30,0x28,0x00,0x08,0x24,0x00,0x00,0x7E,0x00,0x00,0x20, // 188 + 0x00,0x00,0x00,0x10,0x00,0x00,0x08,0x40,0x00,0xF8,0x31,0x00,0x00,0x08,0x00,0x00,0x04,0x00,0x00,0x03,0x00,0x80,0x00,0x00,0x60,0x44,0x00,0x10,0x62,0x00,0x08,0x52,0x00,0x00,0x52,0x00,0x00,0x4C, // 189 + 0x90,0x00,0x00,0x08,0x01,0x00,0x08,0x41,0x00,0x28,0x21,0x00,0xD8,0x18,0x00,0x00,0x04,0x00,0x00,0x03,0x00,0x80,0x00,0x00,0x40,0x30,0x00,0x30,0x28,0x00,0x08,0x24,0x00,0x00,0x7E,0x00,0x00,0x20, // 190 + 0x00,0x00,0x00,0x00,0xE0,0x00,0x00,0x10,0x01,0x00,0x08,0x02,0x40,0x07,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x01,0x00,0xC0, // 191 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x71,0x04,0x00,0x0A,0x04,0x00,0x70,0x04,0x00,0x80,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 192 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x70,0x04,0x00,0x0A,0x04,0x00,0x71,0x04,0x00,0x80,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 193 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x72,0x04,0x00,0x09,0x04,0x00,0x71,0x04,0x00,0x82,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 194 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x72,0x04,0x00,0x09,0x04,0x00,0x72,0x04,0x00,0x81,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 195 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x72,0x04,0x00,0x08,0x04,0x00,0x72,0x04,0x00,0x80,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 196 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x1C,0x00,0x80,0x07,0x00,0x7E,0x04,0x00,0x0A,0x04,0x00,0x7E,0x04,0x00,0x80,0x07,0x00,0x00,0x1C,0x00,0x00,0x60, // 197 + 0x00,0x60,0x00,0x00,0x18,0x00,0x00,0x06,0x00,0x80,0x05,0x00,0x60,0x04,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41, // 198 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x08,0x40,0x02,0x08,0xC0,0x02,0x08,0x40,0x03,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10, // 199 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x09,0x41,0x00,0x0A,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x40, // 200 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x0A,0x41,0x00,0x09,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x40, // 201 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x0A,0x41,0x00,0x09,0x41,0x00,0x09,0x41,0x00,0x0A,0x41,0x00,0x08,0x41,0x00,0x08,0x40, // 202 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x0A,0x41,0x00,0x08,0x41,0x00,0x0A,0x41,0x00,0x08,0x41,0x00,0x08,0x41,0x00,0x08,0x40, // 203 + 0x01,0x00,0x00,0xFA,0x7F, // 204 + 0x00,0x00,0x00,0xFA,0x7F,0x00,0x01, // 205 + 0x02,0x00,0x00,0xF9,0x7F,0x00,0x01,0x00,0x00,0x02, // 206 + 0x02,0x00,0x00,0xF8,0x7F,0x00,0x02, // 207 + 0x00,0x02,0x00,0xF8,0x7F,0x00,0x08,0x42,0x00,0x08,0x42,0x00,0x08,0x42,0x00,0x08,0x42,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 208 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x10,0x00,0x00,0x60,0x00,0x00,0x82,0x00,0x00,0x01,0x03,0x00,0x02,0x04,0x00,0x01,0x18,0x00,0x00,0x20,0x00,0xF8,0x7F, // 209 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x09,0x40,0x00,0x0A,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 210 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x0A,0x40,0x00,0x09,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 211 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x0A,0x40,0x00,0x09,0x40,0x00,0x09,0x40,0x00,0x0A,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 212 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x0A,0x40,0x00,0x09,0x40,0x00,0x0A,0x40,0x00,0x09,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 213 + 0x00,0x00,0x00,0xC0,0x0F,0x00,0x20,0x10,0x00,0x10,0x20,0x00,0x08,0x40,0x00,0x0A,0x40,0x00,0x08,0x40,0x00,0x0A,0x40,0x00,0x10,0x20,0x00,0x20,0x10,0x00,0xC0,0x0F, // 214 + 0x00,0x00,0x00,0x40,0x10,0x00,0x80,0x08,0x00,0x00,0x05,0x00,0x00,0x07,0x00,0x00,0x05,0x00,0x80,0x08,0x00,0x40,0x10, // 215 + 0x00,0x00,0x00,0xC0,0x4F,0x00,0x20,0x30,0x00,0x10,0x30,0x00,0x08,0x4C,0x00,0x08,0x42,0x00,0x08,0x41,0x00,0xC8,0x40,0x00,0x30,0x20,0x00,0x30,0x10,0x00,0xC8,0x0F, // 216 + 0x00,0x00,0x00,0xF8,0x1F,0x00,0x00,0x20,0x00,0x00,0x40,0x00,0x01,0x40,0x00,0x02,0x40,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xF8,0x1F, // 217 + 0x00,0x00,0x00,0xF8,0x1F,0x00,0x00,0x20,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x02,0x40,0x00,0x01,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xF8,0x1F, // 218 + 0x00,0x00,0x00,0xF8,0x1F,0x00,0x00,0x20,0x00,0x00,0x40,0x00,0x02,0x40,0x00,0x01,0x40,0x00,0x01,0x40,0x00,0x02,0x40,0x00,0x00,0x20,0x00,0xF8,0x1F, // 219 + 0x00,0x00,0x00,0xF8,0x1F,0x00,0x00,0x20,0x00,0x00,0x40,0x00,0x02,0x40,0x00,0x00,0x40,0x00,0x02,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xF8,0x1F, // 220 + 0x08,0x00,0x00,0x30,0x00,0x00,0x40,0x00,0x00,0x80,0x01,0x00,0x02,0x7E,0x00,0x81,0x01,0x00,0x40,0x00,0x00,0x30,0x00,0x00,0x08, // 221 + 0x00,0x00,0x00,0xF8,0x7F,0x00,0x20,0x10,0x00,0x20,0x10,0x00,0x20,0x10,0x00,0x20,0x10,0x00,0x20,0x10,0x00,0x20,0x10,0x00,0x40,0x08,0x00,0x80,0x07, // 222 + 0x00,0x00,0x00,0xE0,0x7F,0x00,0x10,0x00,0x00,0x08,0x20,0x00,0x88,0x43,0x00,0x70,0x42,0x00,0x00,0x44,0x00,0x00,0x38, // 223 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x40,0x44,0x00,0x48,0x44,0x00,0x50,0x42,0x00,0x40,0x22,0x00,0x80,0x7F, // 224 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x40,0x44,0x00,0x50,0x44,0x00,0x48,0x42,0x00,0x40,0x22,0x00,0x80,0x7F, // 225 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x50,0x44,0x00,0x48,0x44,0x00,0x48,0x42,0x00,0x50,0x22,0x00,0x80,0x7F, // 226 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x50,0x44,0x00,0x48,0x44,0x00,0x50,0x42,0x00,0x48,0x22,0x00,0x80,0x7F, // 227 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x50,0x44,0x00,0x40,0x44,0x00,0x50,0x42,0x00,0x40,0x22,0x00,0x80,0x7F, // 228 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x5C,0x44,0x00,0x54,0x44,0x00,0x5C,0x42,0x00,0x40,0x22,0x00,0x80,0x7F, // 229 + 0x00,0x00,0x00,0x00,0x39,0x00,0x80,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x42,0x00,0x40,0x22,0x00,0x80,0x3F,0x00,0x80,0x24,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x40,0x44,0x00,0x80,0x24,0x00,0x00,0x17, // 230 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x02,0x40,0xC0,0x02,0x40,0x40,0x03,0x80,0x20, // 231 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x24,0x00,0x48,0x44,0x00,0x50,0x44,0x00,0x40,0x44,0x00,0x80,0x24,0x00,0x00,0x17, // 232 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x24,0x00,0x40,0x44,0x00,0x50,0x44,0x00,0x48,0x44,0x00,0x80,0x24,0x00,0x00,0x17, // 233 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x24,0x00,0x50,0x44,0x00,0x48,0x44,0x00,0x48,0x44,0x00,0x90,0x24,0x00,0x00,0x17, // 234 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x24,0x00,0x50,0x44,0x00,0x40,0x44,0x00,0x50,0x44,0x00,0x80,0x24,0x00,0x00,0x17, // 235 + 0x08,0x00,0x00,0xD0,0x7F, // 236 + 0x00,0x00,0x00,0xD0,0x7F,0x00,0x08, // 237 + 0x10,0x00,0x00,0xC8,0x7F,0x00,0x08,0x00,0x00,0x10, // 238 + 0x10,0x00,0x00,0xC0,0x7F,0x00,0x10, // 239 + 0x00,0x00,0x00,0x00,0x1F,0x00,0xA0,0x20,0x00,0x68,0x40,0x00,0x58,0x40,0x00,0x70,0x40,0x00,0xE8,0x20,0x00,0x00,0x1F, // 240 + 0x00,0x00,0x00,0xC0,0x7F,0x00,0x90,0x00,0x00,0x48,0x00,0x00,0x50,0x00,0x00,0x48,0x00,0x00,0x80,0x7F, // 241 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x48,0x40,0x00,0x50,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 242 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x40,0x40,0x00,0x50,0x40,0x00,0x48,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 243 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x50,0x40,0x00,0x48,0x40,0x00,0x48,0x40,0x00,0x90,0x20,0x00,0x00,0x1F, // 244 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x50,0x40,0x00,0x48,0x40,0x00,0x50,0x40,0x00,0x88,0x20,0x00,0x00,0x1F, // 245 + 0x00,0x00,0x00,0x00,0x1F,0x00,0x80,0x20,0x00,0x50,0x40,0x00,0x40,0x40,0x00,0x50,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 246 + 0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x80,0x0A,0x00,0x00,0x02,0x00,0x00,0x02,0x00,0x00,0x02, // 247 + 0x00,0x00,0x00,0x00,0x5F,0x00,0x80,0x30,0x00,0x40,0x48,0x00,0x40,0x44,0x00,0x40,0x42,0x00,0x80,0x21,0x00,0x40,0x1F, // 248 + 0x00,0x00,0x00,0xC0,0x3F,0x00,0x00,0x40,0x00,0x08,0x40,0x00,0x10,0x40,0x00,0x00,0x20,0x00,0xC0,0x7F, // 249 + 0x00,0x00,0x00,0xC0,0x3F,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x10,0x40,0x00,0x08,0x20,0x00,0xC0,0x7F, // 250 + 0x00,0x00,0x00,0xC0,0x3F,0x00,0x10,0x40,0x00,0x08,0x40,0x00,0x08,0x40,0x00,0x10,0x20,0x00,0xC0,0x7F, // 251 + 0x00,0x00,0x00,0xD0,0x3F,0x00,0x00,0x40,0x00,0x10,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0xC0,0x7F, // 252 + 0xC0,0x01,0x00,0x00,0x06,0x02,0x00,0x38,0x02,0x10,0xE0,0x01,0x08,0x38,0x00,0x00,0x07,0x00,0xC0, // 253 + 0x00,0x00,0x00,0xF8,0xFF,0x03,0x80,0x20,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x80,0x20,0x00,0x00,0x1F, // 254 + 0xC0,0x01,0x00,0x00,0x06,0x02,0x10,0x38,0x02,0x00,0xE0,0x01,0x10,0x38,0x00,0x00,0x07,0x00,0xC0 // 255 +}; +const uint8_t ArialMT_Plain_24[] PROGMEM = { + 0x18, // Width: 24 + 0x1C, // Height: 28 + 0x20, // First Char: 32 + 0xE0, // Numbers of Chars: 224 + + // Jump Table: + 0xFF, 0xFF, 0x00, 0x07, // 32:65535 + 0x00, 0x00, 0x13, 0x07, // 33:0 + 0x00, 0x13, 0x1A, 0x09, // 34:19 + 0x00, 0x2D, 0x33, 0x0D, // 35:45 + 0x00, 0x60, 0x2F, 0x0D, // 36:96 + 0x00, 0x8F, 0x4F, 0x15, // 37:143 + 0x00, 0xDE, 0x3B, 0x10, // 38:222 + 0x01, 0x19, 0x0A, 0x05, // 39:281 + 0x01, 0x23, 0x1C, 0x08, // 40:291 + 0x01, 0x3F, 0x1B, 0x08, // 41:319 + 0x01, 0x5A, 0x21, 0x09, // 42:346 + 0x01, 0x7B, 0x32, 0x0E, // 43:379 + 0x01, 0xAD, 0x10, 0x07, // 44:429 + 0x01, 0xBD, 0x1B, 0x08, // 45:445 + 0x01, 0xD8, 0x0F, 0x07, // 46:472 + 0x01, 0xE7, 0x19, 0x07, // 47:487 + 0x02, 0x00, 0x2F, 0x0D, // 48:512 + 0x02, 0x2F, 0x23, 0x0D, // 49:559 + 0x02, 0x52, 0x2F, 0x0D, // 50:594 + 0x02, 0x81, 0x2F, 0x0D, // 51:641 + 0x02, 0xB0, 0x2F, 0x0D, // 52:688 + 0x02, 0xDF, 0x2F, 0x0D, // 53:735 + 0x03, 0x0E, 0x2F, 0x0D, // 54:782 + 0x03, 0x3D, 0x2D, 0x0D, // 55:829 + 0x03, 0x6A, 0x2F, 0x0D, // 56:874 + 0x03, 0x99, 0x2F, 0x0D, // 57:921 + 0x03, 0xC8, 0x0F, 0x07, // 58:968 + 0x03, 0xD7, 0x10, 0x07, // 59:983 + 0x03, 0xE7, 0x2F, 0x0E, // 60:999 + 0x04, 0x16, 0x2F, 0x0E, // 61:1046 + 0x04, 0x45, 0x2E, 0x0E, // 62:1093 + 0x04, 0x73, 0x2E, 0x0D, // 63:1139 + 0x04, 0xA1, 0x5B, 0x18, // 64:1185 + 0x04, 0xFC, 0x3B, 0x10, // 65:1276 + 0x05, 0x37, 0x3B, 0x10, // 66:1335 + 0x05, 0x72, 0x3F, 0x11, // 67:1394 + 0x05, 0xB1, 0x3F, 0x11, // 68:1457 + 0x05, 0xF0, 0x3B, 0x10, // 69:1520 + 0x06, 0x2B, 0x35, 0x0F, // 70:1579 + 0x06, 0x60, 0x43, 0x13, // 71:1632 + 0x06, 0xA3, 0x3B, 0x11, // 72:1699 + 0x06, 0xDE, 0x0F, 0x07, // 73:1758 + 0x06, 0xED, 0x27, 0x0C, // 74:1773 + 0x07, 0x14, 0x3F, 0x10, // 75:1812 + 0x07, 0x53, 0x2F, 0x0D, // 76:1875 + 0x07, 0x82, 0x43, 0x14, // 77:1922 + 0x07, 0xC5, 0x3B, 0x11, // 78:1989 + 0x08, 0x00, 0x47, 0x13, // 79:2048 + 0x08, 0x47, 0x3A, 0x10, // 80:2119 + 0x08, 0x81, 0x47, 0x13, // 81:2177 + 0x08, 0xC8, 0x3F, 0x11, // 82:2248 + 0x09, 0x07, 0x3B, 0x10, // 83:2311 + 0x09, 0x42, 0x35, 0x0F, // 84:2370 + 0x09, 0x77, 0x3B, 0x11, // 85:2423 + 0x09, 0xB2, 0x39, 0x10, // 86:2482 + 0x09, 0xEB, 0x59, 0x17, // 87:2539 + 0x0A, 0x44, 0x3B, 0x10, // 88:2628 + 0x0A, 0x7F, 0x3D, 0x10, // 89:2687 + 0x0A, 0xBC, 0x37, 0x0F, // 90:2748 + 0x0A, 0xF3, 0x14, 0x07, // 91:2803 + 0x0B, 0x07, 0x1B, 0x07, // 92:2823 + 0x0B, 0x22, 0x18, 0x07, // 93:2850 + 0x0B, 0x3A, 0x2A, 0x0B, // 94:2874 + 0x0B, 0x64, 0x34, 0x0D, // 95:2916 + 0x0B, 0x98, 0x11, 0x08, // 96:2968 + 0x0B, 0xA9, 0x2F, 0x0D, // 97:2985 + 0x0B, 0xD8, 0x33, 0x0D, // 98:3032 + 0x0C, 0x0B, 0x2B, 0x0C, // 99:3083 + 0x0C, 0x36, 0x2F, 0x0D, // 100:3126 + 0x0C, 0x65, 0x2F, 0x0D, // 101:3173 + 0x0C, 0x94, 0x1A, 0x07, // 102:3220 + 0x0C, 0xAE, 0x2F, 0x0D, // 103:3246 + 0x0C, 0xDD, 0x2F, 0x0D, // 104:3293 + 0x0D, 0x0C, 0x0F, 0x05, // 105:3340 + 0x0D, 0x1B, 0x10, 0x05, // 106:3355 + 0x0D, 0x2B, 0x2F, 0x0C, // 107:3371 + 0x0D, 0x5A, 0x0F, 0x05, // 108:3418 + 0x0D, 0x69, 0x47, 0x14, // 109:3433 + 0x0D, 0xB0, 0x2F, 0x0D, // 110:3504 + 0x0D, 0xDF, 0x2F, 0x0D, // 111:3551 + 0x0E, 0x0E, 0x33, 0x0D, // 112:3598 + 0x0E, 0x41, 0x30, 0x0D, // 113:3649 + 0x0E, 0x71, 0x1E, 0x08, // 114:3697 + 0x0E, 0x8F, 0x2B, 0x0C, // 115:3727 + 0x0E, 0xBA, 0x1B, 0x07, // 116:3770 + 0x0E, 0xD5, 0x2F, 0x0D, // 117:3797 + 0x0F, 0x04, 0x2A, 0x0C, // 118:3844 + 0x0F, 0x2E, 0x42, 0x11, // 119:3886 + 0x0F, 0x70, 0x2B, 0x0C, // 120:3952 + 0x0F, 0x9B, 0x2A, 0x0C, // 121:3995 + 0x0F, 0xC5, 0x2B, 0x0C, // 122:4037 + 0x0F, 0xF0, 0x1C, 0x08, // 123:4080 + 0x10, 0x0C, 0x10, 0x06, // 124:4108 + 0x10, 0x1C, 0x1B, 0x08, // 125:4124 + 0x10, 0x37, 0x32, 0x0E, // 126:4151 + 0xFF, 0xFF, 0x00, 0x00, // 127:65535 + 0xFF, 0xFF, 0x00, 0x18, // 128:65535 + 0xFF, 0xFF, 0x00, 0x18, // 129:65535 + 0xFF, 0xFF, 0x00, 0x18, // 130:65535 + 0xFF, 0xFF, 0x00, 0x18, // 131:65535 + 0xFF, 0xFF, 0x00, 0x18, // 132:65535 + 0xFF, 0xFF, 0x00, 0x18, // 133:65535 + 0xFF, 0xFF, 0x00, 0x18, // 134:65535 + 0xFF, 0xFF, 0x00, 0x18, // 135:65535 + 0xFF, 0xFF, 0x00, 0x18, // 136:65535 + 0xFF, 0xFF, 0x00, 0x18, // 137:65535 + 0xFF, 0xFF, 0x00, 0x18, // 138:65535 + 0xFF, 0xFF, 0x00, 0x18, // 139:65535 + 0xFF, 0xFF, 0x00, 0x18, // 140:65535 + 0xFF, 0xFF, 0x00, 0x18, // 141:65535 + 0xFF, 0xFF, 0x00, 0x18, // 142:65535 + 0xFF, 0xFF, 0x00, 0x18, // 143:65535 + 0xFF, 0xFF, 0x00, 0x18, // 144:65535 + 0xFF, 0xFF, 0x00, 0x18, // 145:65535 + 0xFF, 0xFF, 0x00, 0x18, // 146:65535 + 0xFF, 0xFF, 0x00, 0x18, // 147:65535 + 0xFF, 0xFF, 0x00, 0x18, // 148:65535 + 0xFF, 0xFF, 0x00, 0x18, // 149:65535 + 0xFF, 0xFF, 0x00, 0x18, // 150:65535 + 0xFF, 0xFF, 0x00, 0x18, // 151:65535 + 0xFF, 0xFF, 0x00, 0x18, // 152:65535 + 0xFF, 0xFF, 0x00, 0x18, // 153:65535 + 0xFF, 0xFF, 0x00, 0x18, // 154:65535 + 0xFF, 0xFF, 0x00, 0x18, // 155:65535 + 0xFF, 0xFF, 0x00, 0x18, // 156:65535 + 0xFF, 0xFF, 0x00, 0x18, // 157:65535 + 0xFF, 0xFF, 0x00, 0x18, // 158:65535 + 0xFF, 0xFF, 0x00, 0x18, // 159:65535 + 0xFF, 0xFF, 0x00, 0x07, // 160:65535 + 0x10, 0x69, 0x14, 0x08, // 161:4201 + 0x10, 0x7D, 0x2B, 0x0D, // 162:4221 + 0x10, 0xA8, 0x2F, 0x0D, // 163:4264 + 0x10, 0xD7, 0x33, 0x0D, // 164:4311 + 0x11, 0x0A, 0x31, 0x0D, // 165:4362 + 0x11, 0x3B, 0x10, 0x06, // 166:4411 + 0x11, 0x4B, 0x2F, 0x0D, // 167:4427 + 0x11, 0x7A, 0x19, 0x08, // 168:4474 + 0x11, 0x93, 0x46, 0x12, // 169:4499 + 0x11, 0xD9, 0x1A, 0x09, // 170:4569 + 0x11, 0xF3, 0x27, 0x0D, // 171:4595 + 0x12, 0x1A, 0x2F, 0x0E, // 172:4634 + 0x12, 0x49, 0x1B, 0x08, // 173:4681 + 0x12, 0x64, 0x46, 0x12, // 174:4708 + 0x12, 0xAA, 0x31, 0x0D, // 175:4778 + 0x12, 0xDB, 0x1E, 0x0A, // 176:4827 + 0x12, 0xF9, 0x33, 0x0D, // 177:4857 + 0x13, 0x2C, 0x1A, 0x08, // 178:4908 + 0x13, 0x46, 0x1A, 0x08, // 179:4934 + 0x13, 0x60, 0x19, 0x08, // 180:4960 + 0x13, 0x79, 0x2F, 0x0E, // 181:4985 + 0x13, 0xA8, 0x31, 0x0D, // 182:5032 + 0x13, 0xD9, 0x12, 0x08, // 183:5081 + 0x13, 0xEB, 0x18, 0x08, // 184:5099 + 0x14, 0x03, 0x16, 0x08, // 185:5123 + 0x14, 0x19, 0x1E, 0x09, // 186:5145 + 0x14, 0x37, 0x2E, 0x0D, // 187:5175 + 0x14, 0x65, 0x4F, 0x14, // 188:5221 + 0x14, 0xB4, 0x4B, 0x14, // 189:5300 + 0x14, 0xFF, 0x4B, 0x14, // 190:5375 + 0x15, 0x4A, 0x33, 0x0F, // 191:5450 + 0x15, 0x7D, 0x3B, 0x10, // 192:5501 + 0x15, 0xB8, 0x3B, 0x10, // 193:5560 + 0x15, 0xF3, 0x3B, 0x10, // 194:5619 + 0x16, 0x2E, 0x3B, 0x10, // 195:5678 + 0x16, 0x69, 0x3B, 0x10, // 196:5737 + 0x16, 0xA4, 0x3B, 0x10, // 197:5796 + 0x16, 0xDF, 0x5B, 0x18, // 198:5855 + 0x17, 0x3A, 0x3F, 0x11, // 199:5946 + 0x17, 0x79, 0x3B, 0x10, // 200:6009 + 0x17, 0xB4, 0x3B, 0x10, // 201:6068 + 0x17, 0xEF, 0x3B, 0x10, // 202:6127 + 0x18, 0x2A, 0x3B, 0x10, // 203:6186 + 0x18, 0x65, 0x11, 0x07, // 204:6245 + 0x18, 0x76, 0x11, 0x07, // 205:6262 + 0x18, 0x87, 0x15, 0x07, // 206:6279 + 0x18, 0x9C, 0x15, 0x07, // 207:6300 + 0x18, 0xB1, 0x3F, 0x11, // 208:6321 + 0x18, 0xF0, 0x3B, 0x11, // 209:6384 + 0x19, 0x2B, 0x47, 0x13, // 210:6443 + 0x19, 0x72, 0x47, 0x13, // 211:6514 + 0x19, 0xB9, 0x47, 0x13, // 212:6585 + 0x1A, 0x00, 0x47, 0x13, // 213:6656 + 0x1A, 0x47, 0x47, 0x13, // 214:6727 + 0x1A, 0x8E, 0x2B, 0x0E, // 215:6798 + 0x1A, 0xB9, 0x47, 0x13, // 216:6841 + 0x1B, 0x00, 0x3B, 0x11, // 217:6912 + 0x1B, 0x3B, 0x3B, 0x11, // 218:6971 + 0x1B, 0x76, 0x3B, 0x11, // 219:7030 + 0x1B, 0xB1, 0x3B, 0x11, // 220:7089 + 0x1B, 0xEC, 0x3D, 0x10, // 221:7148 + 0x1C, 0x29, 0x3A, 0x10, // 222:7209 + 0x1C, 0x63, 0x37, 0x0F, // 223:7267 + 0x1C, 0x9A, 0x2F, 0x0D, // 224:7322 + 0x1C, 0xC9, 0x2F, 0x0D, // 225:7369 + 0x1C, 0xF8, 0x2F, 0x0D, // 226:7416 + 0x1D, 0x27, 0x2F, 0x0D, // 227:7463 + 0x1D, 0x56, 0x2F, 0x0D, // 228:7510 + 0x1D, 0x85, 0x2F, 0x0D, // 229:7557 + 0x1D, 0xB4, 0x53, 0x15, // 230:7604 + 0x1E, 0x07, 0x2B, 0x0C, // 231:7687 + 0x1E, 0x32, 0x2F, 0x0D, // 232:7730 + 0x1E, 0x61, 0x2F, 0x0D, // 233:7777 + 0x1E, 0x90, 0x2F, 0x0D, // 234:7824 + 0x1E, 0xBF, 0x2F, 0x0D, // 235:7871 + 0x1E, 0xEE, 0x11, 0x07, // 236:7918 + 0x1E, 0xFF, 0x11, 0x07, // 237:7935 + 0x1F, 0x10, 0x15, 0x07, // 238:7952 + 0x1F, 0x25, 0x15, 0x07, // 239:7973 + 0x1F, 0x3A, 0x2F, 0x0D, // 240:7994 + 0x1F, 0x69, 0x2F, 0x0D, // 241:8041 + 0x1F, 0x98, 0x2F, 0x0D, // 242:8088 + 0x1F, 0xC7, 0x2F, 0x0D, // 243:8135 + 0x1F, 0xF6, 0x2F, 0x0D, // 244:8182 + 0x20, 0x25, 0x2F, 0x0D, // 245:8229 + 0x20, 0x54, 0x2F, 0x0D, // 246:8276 + 0x20, 0x83, 0x32, 0x0D, // 247:8323 + 0x20, 0xB5, 0x33, 0x0F, // 248:8373 + 0x20, 0xE8, 0x2F, 0x0D, // 249:8424 + 0x21, 0x17, 0x2F, 0x0D, // 250:8471 + 0x21, 0x46, 0x2F, 0x0D, // 251:8518 + 0x21, 0x75, 0x2F, 0x0D, // 252:8565 + 0x21, 0xA4, 0x2A, 0x0C, // 253:8612 + 0x21, 0xCE, 0x2F, 0x0D, // 254:8654 + 0x21, 0xFD, 0x2A, 0x0C, // 255:8701 + + // Font Data: + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x33,0x00,0xE0,0xFF,0x33, // 33 + 0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xE0,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xE0,0x07, // 34 + 0x00,0x0C,0x03,0x00,0x00,0x0C,0x33,0x00,0x00,0x0C,0x3F,0x00,0x00,0xFC,0x0F,0x00,0x80,0xFF,0x03,0x00,0xE0,0x0F,0x03,0x00,0x60,0x0C,0x33,0x00,0x00,0x0C,0x3F,0x00,0x00,0xFC,0x0F,0x00,0x80,0xFF,0x03,0x00,0xE0,0x0F,0x03,0x00,0x60,0x0C,0x03,0x00,0x00,0x0C,0x03, // 35 + 0x00,0x00,0x00,0x00,0x80,0x07,0x06,0x00,0xC0,0x0F,0x1E,0x00,0xC0,0x18,0x1C,0x00,0x60,0x18,0x38,0x00,0x60,0x30,0x30,0x00,0xF0,0xFF,0xFF,0x00,0x60,0x30,0x30,0x00,0x60,0x60,0x38,0x00,0xC0,0x60,0x18,0x00,0xC0,0xC1,0x1F,0x00,0x00,0x81,0x07, // 36 + 0x00,0x00,0x00,0x00,0x80,0x0F,0x00,0x00,0xC0,0x1F,0x00,0x00,0x60,0x30,0x00,0x00,0x20,0x20,0x00,0x00,0x20,0x20,0x20,0x00,0x60,0x30,0x38,0x00,0xC0,0x1F,0x1E,0x00,0x80,0x8F,0x0F,0x00,0x00,0xC0,0x03,0x00,0x00,0xF0,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0x8F,0x0F,0x00,0xC0,0xC3,0x1F,0x00,0xE0,0x60,0x30,0x00,0x20,0x20,0x20,0x00,0x00,0x20,0x20,0x00,0x00,0x60,0x30,0x00,0x00,0xC0,0x1F,0x00,0x00,0x80,0x0F, // 37 + 0x00,0x00,0x00,0x00,0x00,0x80,0x07,0x00,0x00,0xC0,0x0F,0x00,0x80,0xE3,0x1C,0x00,0xC0,0x77,0x38,0x00,0xE0,0x3C,0x30,0x00,0x60,0x38,0x30,0x00,0x60,0x78,0x30,0x00,0xE0,0xEC,0x38,0x00,0xC0,0x8F,0x1B,0x00,0x80,0x03,0x1F,0x00,0x00,0x00,0x0F,0x00,0x00,0xC0,0x1F,0x00,0x00,0xC0,0x38,0x00,0x00,0x00,0x10, // 38 + 0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xE0,0x07, // 39 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x0F,0x00,0x00,0xFE,0x7F,0x00,0x80,0x0F,0xF0,0x01,0xC0,0x01,0x80,0x03,0x60,0x00,0x00,0x06,0x20,0x00,0x00,0x04, // 40 + 0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x04,0x60,0x00,0x00,0x06,0xC0,0x01,0x80,0x03,0x80,0x0F,0xF0,0x01,0x00,0xFE,0x7F,0x00,0x00,0xF0,0x0F, // 41 + 0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x04,0x00,0x00,0x80,0x0F,0x00,0x00,0xE0,0x03,0x00,0x00,0xE0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x80,0x04,0x00,0x00,0x80, // 42 + 0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xFF,0x0F,0x00,0x00,0xFF,0x0F,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60, // 43 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x03,0x00,0x00,0xF0,0x01, // 44 + 0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01, // 45 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30, // 46 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0xE0,0x0F,0x00,0x00,0xFC,0x01,0x00,0x80,0x3F,0x00,0x00,0xE0,0x03,0x00,0x00,0x60, // 47 + 0x00,0x00,0x00,0x00,0x00,0xFE,0x03,0x00,0x80,0xFF,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xE0,0x00,0x38,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x38,0x00,0xC0,0x01,0x1C,0x00,0x80,0xFF,0x0F,0x00,0x00,0xFE,0x03, // 48 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x03,0x00,0x00,0x80,0x01,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 49 + 0x00,0x00,0x00,0x00,0x00,0x03,0x30,0x00,0xC0,0x03,0x38,0x00,0xC0,0x00,0x3C,0x00,0x60,0x00,0x36,0x00,0x60,0x00,0x33,0x00,0x60,0x80,0x31,0x00,0x60,0xC0,0x30,0x00,0x60,0x60,0x30,0x00,0xC0,0x30,0x30,0x00,0xC0,0x1F,0x30,0x00,0x00,0x0F,0x30, // 50 + 0x00,0x00,0x00,0x00,0x00,0x01,0x06,0x00,0xC0,0x01,0x0E,0x00,0xC0,0x00,0x1C,0x00,0x60,0x00,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0xC0,0x38,0x30,0x00,0xC0,0x6F,0x18,0x00,0x80,0xC7,0x0F,0x00,0x00,0x80,0x07, // 51 + 0x00,0x00,0x00,0x00,0x00,0x80,0x03,0x00,0x00,0xC0,0x03,0x00,0x00,0xF0,0x03,0x00,0x00,0x3C,0x03,0x00,0x00,0x0E,0x03,0x00,0x80,0x07,0x03,0x00,0xC0,0x01,0x03,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x03, // 52 + 0x00,0x00,0x00,0x00,0x00,0x30,0x06,0x00,0x80,0x3F,0x0E,0x00,0xE0,0x1F,0x18,0x00,0x60,0x08,0x30,0x00,0x60,0x0C,0x30,0x00,0x60,0x0C,0x30,0x00,0x60,0x0C,0x30,0x00,0x60,0x0C,0x30,0x00,0x60,0x18,0x1C,0x00,0x60,0xF0,0x0F,0x00,0x00,0xE0,0x03, // 53 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x03,0x00,0x80,0xFF,0x0F,0x00,0xC0,0x63,0x1C,0x00,0xC0,0x30,0x38,0x00,0x60,0x18,0x30,0x00,0x60,0x18,0x30,0x00,0x60,0x18,0x30,0x00,0x60,0x18,0x30,0x00,0xE0,0x30,0x18,0x00,0xC0,0xF1,0x0F,0x00,0x80,0xC1,0x07, // 54 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x3C,0x00,0x60,0x80,0x3F,0x00,0x60,0xE0,0x03,0x00,0x60,0x78,0x00,0x00,0x60,0x0E,0x00,0x00,0x60,0x03,0x00,0x00,0xE0,0x01,0x00,0x00,0x60, // 55 + 0x00,0x00,0x00,0x00,0x00,0x80,0x07,0x00,0x80,0xC7,0x1F,0x00,0xC0,0x6F,0x18,0x00,0xE0,0x38,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0xE0,0x38,0x30,0x00,0xC0,0x6F,0x18,0x00,0x80,0xC7,0x1F,0x00,0x00,0x80,0x07, // 56 + 0x00,0x00,0x00,0x00,0x00,0x1F,0x0C,0x00,0x80,0x7F,0x1C,0x00,0xC0,0x61,0x38,0x00,0x60,0xC0,0x30,0x00,0x60,0xC0,0x30,0x00,0x60,0xC0,0x30,0x00,0x60,0xC0,0x30,0x00,0x60,0x60,0x18,0x00,0xC0,0x31,0x1E,0x00,0x80,0xFF,0x0F,0x00,0x00,0xFE,0x01, // 57 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30, // 58 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x30,0x03,0x00,0x06,0xF0,0x01, // 59 + 0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x50,0x00,0x00,0x00,0xD8,0x00,0x00,0x00,0xD8,0x00,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x04,0x01,0x00,0x00,0x06,0x03,0x00,0x00,0x06,0x03,0x00,0x00,0x03,0x06, // 60 + 0x00,0x00,0x00,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01, // 61 + 0x00,0x00,0x00,0x00,0x00,0x03,0x06,0x00,0x00,0x06,0x03,0x00,0x00,0x06,0x03,0x00,0x00,0x04,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0x8C,0x01,0x00,0x00,0xD8,0x00,0x00,0x00,0xD8,0x00,0x00,0x00,0x50,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x20, // 62 + 0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x80,0x03,0x00,0x00,0xC0,0x01,0x00,0x00,0xE0,0x00,0x00,0x00,0x60,0x80,0x33,0x00,0x60,0xC0,0x33,0x00,0x60,0xE0,0x00,0x00,0x60,0x30,0x00,0x00,0xC0,0x38,0x00,0x00,0xC0,0x1F,0x00,0x00,0x00,0x07, // 63 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x0F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x1E,0xF0,0x00,0x00,0x07,0xC0,0x01,0x80,0xC3,0x87,0x01,0xC0,0xF1,0x9F,0x03,0xC0,0x38,0x18,0x03,0xC0,0x0C,0x30,0x03,0x60,0x0E,0x30,0x06,0x60,0x06,0x30,0x06,0x60,0x06,0x18,0x06,0x60,0x06,0x0C,0x06,0x60,0x0C,0x1E,0x06,0x60,0xF8,0x3F,0x06,0xE0,0xFE,0x31,0x06,0xC0,0x0E,0x30,0x06,0xC0,0x01,0x18,0x03,0x80,0x03,0x1C,0x03,0x00,0x07,0x8F,0x01,0x00,0xFE,0x87,0x01,0x00,0xF8,0xC1,0x00,0x00,0x00,0x40, // 64 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x80,0x8F,0x01,0x00,0xE0,0x83,0x01,0x00,0x60,0x80,0x01,0x00,0xE0,0x83,0x01,0x00,0x80,0x8F,0x01,0x00,0x00,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 65 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0xC0,0x78,0x30,0x00,0xC0,0xFF,0x18,0x00,0x80,0xC7,0x1F,0x00,0x00,0x80,0x07, // 66 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x03,0x0F,0x00,0x00,0x02,0x03, // 67 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x03,0x0E,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 68 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 69 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60, // 70 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x18,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x60,0x30,0x00,0x60,0x60,0x30,0x00,0xE0,0x60,0x38,0x00,0xC0,0x60,0x18,0x00,0xC0,0x61,0x18,0x00,0x80,0xE3,0x0F,0x00,0x00,0xE2,0x0F, // 71 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 72 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 73 + 0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x38,0x00,0xE0,0xFF,0x1F,0x00,0xE0,0xFF,0x0F, // 74 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0xE0,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x7C,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0xE7,0x01,0x00,0x80,0x83,0x07,0x00,0xC0,0x01,0x0F,0x00,0xE0,0x00,0x1E,0x00,0x60,0x00,0x38,0x00,0x20,0x00,0x30,0x00,0x00,0x00,0x20, // 75 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30, // 76 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0x01,0x00,0x00,0xC0,0x0F,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x3F,0x00,0x00,0xE0,0x07,0x00,0x00,0xFE,0x00,0x00,0xC0,0x0F,0x00,0x00,0xE0,0x01,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 77 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0xC0,0x01,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0xE0,0x01,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x0F,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 78 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x38,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 79 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0x60,0x60,0x00,0x00,0xC0,0x30,0x00,0x00,0xC0,0x3F,0x00,0x00,0x00,0x0F, // 80 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x0C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x18,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x36,0x00,0x60,0x00,0x36,0x00,0xE0,0x00,0x3C,0x00,0xC0,0x00,0x1C,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x3F,0x00,0x00,0xFF,0x77,0x00,0x00,0xFC,0x61, // 81 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x70,0x00,0x00,0x60,0xF0,0x00,0x00,0x60,0xF0,0x03,0x00,0x60,0xB0,0x07,0x00,0xE0,0x18,0x1F,0x00,0xC0,0x1F,0x3C,0x00,0x80,0x0F,0x30,0x00,0x00,0x00,0x20, // 82 + 0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x07,0x0F,0x00,0xC0,0x1F,0x1C,0x00,0xC0,0x18,0x18,0x00,0x60,0x38,0x38,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x70,0x30,0x00,0xC0,0x60,0x18,0x00,0xC0,0xE1,0x18,0x00,0x80,0xC3,0x0F,0x00,0x00,0x83,0x07, // 83 + 0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60, // 84 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x03,0x00,0xE0,0xFF,0x0F,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x0F,0x00,0xE0,0xFF,0x03, // 85 + 0x20,0x00,0x00,0x00,0xE0,0x01,0x00,0x00,0xC0,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0xF8,0x01,0x00,0x00,0xC0,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x3E,0x00,0x00,0xC0,0x0F,0x00,0x00,0xF8,0x01,0x00,0x00,0x3E,0x00,0x00,0xC0,0x0F,0x00,0x00,0xE0,0x01,0x00,0x00,0x20, // 86 + 0x60,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0x80,0xFF,0x00,0x00,0x00,0xF8,0x0F,0x00,0x00,0x80,0x3F,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x3F,0x00,0x00,0xE0,0x0F,0x00,0x00,0xFC,0x01,0x00,0x80,0x1F,0x00,0x00,0xE0,0x03,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0x80,0x1F,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xE0,0x0F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x30,0x00,0x00,0x80,0x3F,0x00,0x00,0xF8,0x0F,0x00,0x80,0xFF,0x00,0x00,0xE0,0x07,0x00,0x00,0x60, // 87 + 0x00,0x00,0x20,0x00,0x20,0x00,0x30,0x00,0x60,0x00,0x3C,0x00,0xE0,0x01,0x1E,0x00,0xC0,0x83,0x07,0x00,0x00,0xCF,0x03,0x00,0x00,0xFE,0x01,0x00,0x00,0x38,0x00,0x00,0x00,0xFE,0x01,0x00,0x00,0xCF,0x03,0x00,0xC0,0x03,0x07,0x00,0xE0,0x01,0x1E,0x00,0x60,0x00,0x3C,0x00,0x20,0x00,0x30,0x00,0x00,0x00,0x20, // 88 + 0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xC0,0x01,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0xF0,0x3F,0x00,0x00,0xF0,0x3F,0x00,0x00,0x3C,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x07,0x00,0x00,0xC0,0x03,0x00,0x00,0xE0,0x01,0x00,0x00,0x60,0x00,0x00,0x00,0x20, // 89 + 0x00,0x00,0x30,0x00,0x60,0x00,0x38,0x00,0x60,0x00,0x3C,0x00,0x60,0x00,0x37,0x00,0x60,0x80,0x33,0x00,0x60,0xC0,0x31,0x00,0x60,0xE0,0x30,0x00,0x60,0x38,0x30,0x00,0x60,0x1C,0x30,0x00,0x60,0x0E,0x30,0x00,0x60,0x07,0x30,0x00,0xE0,0x01,0x30,0x00,0xE0,0x00,0x30,0x00,0x60,0x00,0x30, // 90 + 0x00,0x00,0x00,0x00,0xE0,0xFF,0xFF,0x07,0xE0,0xFF,0xFF,0x07,0x60,0x00,0x00,0x06,0x60,0x00,0x00,0x06, // 91 + 0x60,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0x80,0x3F,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xE0,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 92 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x06,0x60,0x00,0x00,0x06,0xE0,0xFF,0xFF,0x07,0xE0,0xFF,0xFF,0x07, // 93 + 0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1F,0x00,0x00,0xC0,0x07,0x00,0x00,0xE0,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0xC0,0x07,0x00,0x00,0x00,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x20, // 94 + 0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06, // 95 + 0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0x80, // 96 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0x00,0x8C,0x39,0x00,0x00,0x86,0x31,0x00,0x00,0x86,0x31,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x18,0x00,0x00,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 97 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x18,0x0C,0x00,0x00,0x0C,0x18,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xE0,0x03, // 98 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0x18,0x0C, // 99 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0C,0x18,0x00,0x00,0x18,0x0C,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 100 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0xDC,0x1C,0x00,0x00,0xCE,0x38,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xCE,0x38,0x00,0x00,0xDC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xF0,0x04, // 101 + 0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0xC0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x06,0x00,0x00,0x60,0x06,0x00,0x00,0x60,0x06, // 102 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x83,0x01,0x00,0xF8,0x8F,0x03,0x00,0x1C,0x1C,0x07,0x00,0x0E,0x38,0x06,0x00,0x06,0x30,0x06,0x00,0x06,0x30,0x06,0x00,0x06,0x30,0x06,0x00,0x0C,0x18,0x07,0x00,0x18,0x8C,0x03,0x00,0xFE,0xFF,0x01,0x00,0xFE,0xFF, // 103 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x18,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0xFC,0x3F,0x00,0x00,0xF8,0x3F, // 104 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0xFE,0x3F,0x00,0x60,0xFE,0x3F, // 105 + 0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x60,0xFE,0xFF,0x07,0x60,0xFE,0xFF,0x03, // 106 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0xC0,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0xF0,0x01,0x00,0x00,0x98,0x07,0x00,0x00,0x0C,0x0E,0x00,0x00,0x06,0x3C,0x00,0x00,0x02,0x30,0x00,0x00,0x00,0x20, // 107 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 108 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F,0x00,0x00,0x0C,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0xFC,0x3F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x0C,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0xFC,0x3F,0x00,0x00,0xF8,0x3F, // 109 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F,0x00,0x00,0x18,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0xFC,0x3F,0x00,0x00,0xF8,0x3F, // 110 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 111 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0xFF,0x07,0x00,0xFE,0xFF,0x07,0x00,0x18,0x0C,0x00,0x00,0x0C,0x18,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xE0,0x03, // 112 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0C,0x18,0x00,0x00,0x18,0x0C,0x00,0x00,0xFE,0xFF,0x07,0x00,0xFE,0xFF,0x07, // 113 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F,0x00,0x00,0x0C,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x06, // 114 + 0x00,0x00,0x00,0x00,0x00,0x38,0x0C,0x00,0x00,0x7C,0x1C,0x00,0x00,0xEE,0x38,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x31,0x00,0x00,0xC6,0x31,0x00,0x00,0x8E,0x39,0x00,0x00,0x9C,0x1F,0x00,0x00,0x18,0x0F, // 115 + 0x00,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0xC0,0xFF,0x1F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30, // 116 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x0F,0x00,0x00,0xFE,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x0C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 117 + 0x00,0x06,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0xC0,0x07,0x00,0x00,0x00,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1F,0x00,0x00,0xC0,0x07,0x00,0x00,0xF8,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x06, // 118 + 0x00,0x0E,0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x80,0x1F,0x00,0x00,0xE0,0x03,0x00,0x00,0x7C,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x7C,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0x80,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x80,0x1F,0x00,0x00,0xF0,0x03,0x00,0x00,0x7E,0x00,0x00,0x00,0x0E, // 119 + 0x00,0x02,0x20,0x00,0x00,0x06,0x30,0x00,0x00,0x1E,0x3C,0x00,0x00,0x38,0x0E,0x00,0x00,0xF0,0x07,0x00,0x00,0xC0,0x01,0x00,0x00,0xE0,0x07,0x00,0x00,0x38,0x0E,0x00,0x00,0x1C,0x3C,0x00,0x00,0x0E,0x30,0x00,0x00,0x02,0x20, // 120 + 0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x7E,0x00,0x06,0x00,0xF0,0x01,0x06,0x00,0x80,0x0F,0x07,0x00,0x00,0xFE,0x03,0x00,0x00,0xFC,0x00,0x00,0xC0,0x1F,0x00,0x00,0xF8,0x03,0x00,0x00,0x3E,0x00,0x00,0x00,0x06, // 121 + 0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x06,0x3C,0x00,0x00,0x06,0x3E,0x00,0x00,0x06,0x37,0x00,0x00,0xC6,0x33,0x00,0x00,0xE6,0x30,0x00,0x00,0x76,0x30,0x00,0x00,0x3E,0x30,0x00,0x00,0x1E,0x30,0x00,0x00,0x06,0x30, // 122 + 0x00,0x00,0x00,0x00,0x00,0x80,0x01,0x00,0x00,0xC0,0x03,0x00,0xC0,0x7F,0xFE,0x03,0xE0,0x3F,0xFC,0x07,0x60,0x00,0x00,0x06,0x60,0x00,0x00,0x06, // 123 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0xFF,0x0F,0xE0,0xFF,0xFF,0x0F, // 124 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x06,0x60,0x00,0x00,0x06,0xE0,0x3F,0xFC,0x07,0xC0,0x7F,0xFF,0x03,0x00,0xC0,0x03,0x00,0x00,0x80,0x01, // 125 + 0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0x60, // 126 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE6,0xFF,0x07,0x00,0xE6,0xFF,0x07, // 161 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x9C,0x07,0x00,0x0E,0x78,0x00,0x00,0x06,0x3F,0x00,0x00,0xF6,0x30,0x00,0x00,0x0E,0x30,0x00,0xE0,0x0D,0x1C,0x00,0x00,0x1C,0x0E,0x00,0x00,0x10,0x06, // 162 + 0x00,0x60,0x10,0x00,0x00,0x60,0x38,0x00,0x00,0x7F,0x1C,0x00,0xC0,0xFF,0x1F,0x00,0xE0,0xE0,0x19,0x00,0x60,0x60,0x18,0x00,0x60,0x60,0x18,0x00,0x60,0x60,0x30,0x00,0xE0,0x00,0x30,0x00,0xC0,0x01,0x30,0x00,0x80,0x01,0x38,0x00,0x00,0x00,0x10, // 163 + 0x00,0x00,0x00,0x00,0x00,0x02,0x04,0x00,0x00,0xF7,0x0E,0x00,0x00,0xFE,0x07,0x00,0x00,0x0C,0x03,0x00,0x00,0x06,0x06,0x00,0x00,0x06,0x06,0x00,0x00,0x06,0x06,0x00,0x00,0x06,0x06,0x00,0x00,0x0C,0x03,0x00,0x00,0xFE,0x07,0x00,0x00,0xF7,0x0E,0x00,0x00,0x02,0x04, // 164 + 0xE0,0x60,0x06,0x00,0xC0,0x61,0x06,0x00,0x80,0x67,0x06,0x00,0x00,0x7E,0x06,0x00,0x00,0x7C,0x06,0x00,0x00,0xF0,0x3F,0x00,0x00,0xF0,0x3F,0x00,0x00,0x7C,0x06,0x00,0x00,0x7E,0x06,0x00,0x80,0x67,0x06,0x00,0xC0,0x61,0x06,0x00,0xE0,0x60,0x06,0x00,0x20, // 165 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x7F,0xF8,0x0F,0xE0,0x7F,0xF8,0x0F, // 166 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x00,0x00,0x80,0xF3,0xC1,0x00,0xC0,0x1F,0xC3,0x03,0xE0,0x0C,0x07,0x03,0x60,0x1C,0x06,0x06,0x60,0x18,0x0C,0x06,0x60,0x30,0x1C,0x06,0xE0,0x70,0x38,0x07,0xC0,0xE1,0xF4,0x03,0x80,0xC1,0xE7,0x01,0x00,0x80,0x03, // 167 + 0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60, // 168 + 0x00,0xF8,0x00,0x00,0x00,0xFE,0x03,0x00,0x00,0x07,0x07,0x00,0x80,0x01,0x0C,0x00,0xC0,0x79,0x1C,0x00,0xC0,0xFE,0x19,0x00,0x60,0x86,0x31,0x00,0x60,0x03,0x33,0x00,0x60,0x03,0x33,0x00,0x60,0x03,0x33,0x00,0x60,0x03,0x33,0x00,0x60,0x87,0x33,0x00,0xC0,0x86,0x19,0x00,0xC0,0x85,0x1C,0x00,0x80,0x01,0x0C,0x00,0x00,0x07,0x07,0x00,0x00,0xFE,0x03,0x00,0x00,0xF8, // 169 + 0x00,0x00,0x00,0x00,0xC0,0x1C,0x00,0x00,0xE0,0x3E,0x00,0x00,0x60,0x32,0x00,0x00,0x60,0x32,0x00,0x00,0xE0,0x3F,0x00,0x00,0xC0,0x3F, // 170 + 0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xE0,0x03,0x00,0x00,0x78,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x84,0x10,0x00,0x00,0xE0,0x03,0x00,0x00,0x78,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x04,0x10, // 171 + 0x00,0x00,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFC,0x01, // 172 + 0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01,0x00,0x00,0x80,0x01, // 173 + 0x00,0xF8,0x00,0x00,0x00,0xFE,0x03,0x00,0x00,0x07,0x07,0x00,0x80,0x01,0x0C,0x00,0xC0,0x01,0x1C,0x00,0xC0,0xFE,0x1B,0x00,0x60,0xFE,0x33,0x00,0x60,0x66,0x30,0x00,0x60,0x66,0x30,0x00,0x60,0xE6,0x30,0x00,0x60,0xFE,0x31,0x00,0x60,0x3C,0x33,0x00,0xC0,0x00,0x1A,0x00,0xC0,0x01,0x1C,0x00,0x80,0x01,0x0C,0x00,0x00,0x07,0x07,0x00,0x00,0xFE,0x03,0x00,0x00,0xF8, // 174 + 0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x0C, // 175 + 0x00,0x00,0x00,0x00,0x80,0x03,0x00,0x00,0x40,0x04,0x00,0x00,0x20,0x08,0x00,0x00,0x20,0x08,0x00,0x00,0x20,0x08,0x00,0x00,0x40,0x04,0x00,0x00,0x80,0x03, // 176 + 0x00,0x00,0x00,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0xFF,0x3F,0x00,0x00,0xFF,0x3F,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30,0x00,0x00,0x60,0x30, // 177 + 0x40,0x20,0x00,0x00,0x60,0x30,0x00,0x00,0x20,0x38,0x00,0x00,0x20,0x2C,0x00,0x00,0x20,0x26,0x00,0x00,0xE0,0x23,0x00,0x00,0xC0,0x21, // 178 + 0x40,0x10,0x00,0x00,0x60,0x30,0x00,0x00,0x20,0x20,0x00,0x00,0x20,0x22,0x00,0x00,0x20,0x22,0x00,0x00,0xE0,0x3D,0x00,0x00,0xC0,0x1D, // 179 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x20, // 180 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0xFF,0x07,0x00,0xFE,0xFF,0x07,0x00,0x00,0x1C,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x1C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 181 + 0x00,0x0F,0x00,0x00,0xC0,0x3F,0x00,0x00,0xC0,0x3F,0x00,0x00,0xE0,0x7F,0x00,0x00,0xE0,0x7F,0x00,0x00,0xE0,0xFF,0xFF,0x07,0xE0,0xFF,0xFF,0x07,0x60,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0xFF,0xFF,0x07,0xE0,0xFF,0xFF,0x07,0x60,0x00,0x00,0x00,0x60, // 182 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x60, // 183 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0xC0,0x02,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x01, // 184 + 0x00,0x00,0x00,0x00,0x80,0x01,0x00,0x00,0xC0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0xE0,0x3F,0x00,0x00,0xE0,0x3F, // 185 + 0x00,0x00,0x00,0x00,0x80,0x0F,0x00,0x00,0xC0,0x1F,0x00,0x00,0xE0,0x38,0x00,0x00,0x60,0x30,0x00,0x00,0xE0,0x38,0x00,0x00,0xC0,0x1F,0x00,0x00,0x80,0x0F, // 186 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x10,0x00,0x00,0x1C,0x1C,0x00,0x00,0x78,0x0F,0x00,0x00,0xE0,0x03,0x00,0x00,0x84,0x10,0x00,0x00,0x1C,0x1C,0x00,0x00,0x78,0x0F,0x00,0x00,0xE0,0x03,0x00,0x00,0x80, // 187 + 0x00,0x00,0x00,0x00,0x80,0x01,0x00,0x00,0xC0,0x00,0x00,0x00,0xC0,0x00,0x20,0x00,0xE0,0x3F,0x38,0x00,0xE0,0x3F,0x1C,0x00,0x00,0x00,0x0E,0x00,0x00,0x80,0x03,0x00,0x00,0xC0,0x01,0x00,0x00,0xE0,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x07,0x0C,0x00,0xC0,0x01,0x0E,0x00,0xE0,0x80,0x0B,0x00,0x60,0xC0,0x08,0x00,0x00,0xE0,0x3F,0x00,0x00,0xE0,0x3F,0x00,0x00,0x00,0x08, // 188 + 0x00,0x00,0x00,0x00,0x80,0x01,0x00,0x00,0xC0,0x00,0x00,0x00,0xC0,0x00,0x20,0x00,0xE0,0x3F,0x30,0x00,0xE0,0x3F,0x1C,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x07,0x00,0x00,0xC0,0x01,0x00,0x00,0xE0,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x4E,0x20,0x00,0x00,0x67,0x30,0x00,0xC0,0x21,0x38,0x00,0xE0,0x20,0x2C,0x00,0x60,0x20,0x26,0x00,0x00,0xE0,0x27,0x00,0x00,0xC0,0x21, // 189 + 0x40,0x10,0x00,0x00,0x60,0x30,0x00,0x00,0x20,0x20,0x00,0x00,0x20,0x22,0x20,0x00,0x20,0x22,0x30,0x00,0xE0,0x3D,0x38,0x00,0xC0,0x1D,0x0E,0x00,0x00,0x00,0x07,0x00,0x00,0x80,0x03,0x00,0x00,0xE0,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x0E,0x0C,0x00,0x00,0x07,0x0E,0x00,0x80,0x83,0x0B,0x00,0xE0,0xC0,0x08,0x00,0x60,0xE0,0x3F,0x00,0x20,0xE0,0x3F,0x00,0x00,0x00,0x08, // 190 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0xF8,0x03,0x00,0x00,0x1E,0x03,0x00,0x00,0x07,0x07,0x00,0xE6,0x03,0x06,0x00,0xE6,0x01,0x06,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x80,0x03,0x00,0x00,0xC0,0x01,0x00,0x00,0xC0, // 191 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x82,0x8F,0x01,0x00,0xE6,0x83,0x01,0x00,0x6E,0x80,0x01,0x00,0xE8,0x83,0x01,0x00,0x80,0x8F,0x01,0x00,0x00,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 192 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x80,0x8F,0x01,0x00,0xE8,0x83,0x01,0x00,0x6E,0x80,0x01,0x00,0xE6,0x83,0x01,0x00,0x82,0x8F,0x01,0x00,0x00,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 193 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x88,0x8F,0x01,0x00,0xEC,0x83,0x01,0x00,0x66,0x80,0x01,0x00,0xE6,0x83,0x01,0x00,0x8C,0x8F,0x01,0x00,0x08,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 194 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x0C,0xFE,0x01,0x00,0x8E,0x8F,0x01,0x00,0xE6,0x83,0x01,0x00,0x66,0x80,0x01,0x00,0xEC,0x83,0x01,0x00,0x8C,0x8F,0x01,0x00,0x0E,0xFE,0x01,0x00,0x06,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 195 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x8C,0x8F,0x01,0x00,0xEC,0x83,0x01,0x00,0x60,0x80,0x01,0x00,0xE0,0x83,0x01,0x00,0x8C,0x8F,0x01,0x00,0x0C,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 196 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3E,0x00,0x00,0x80,0x0F,0x00,0x00,0xF0,0x03,0x00,0x00,0xFE,0x01,0x00,0x9C,0x8F,0x01,0x00,0xE2,0x83,0x01,0x00,0x62,0x80,0x01,0x00,0xE2,0x83,0x01,0x00,0x9C,0x8F,0x01,0x00,0x00,0xFE,0x01,0x00,0x00,0xF0,0x03,0x00,0x00,0x80,0x0F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x30, // 197 + 0x00,0x00,0x30,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0x0F,0x00,0x00,0xC0,0x03,0x00,0x00,0xF0,0x01,0x00,0x00,0xBC,0x01,0x00,0x00,0x8F,0x01,0x00,0xC0,0x83,0x01,0x00,0xE0,0x80,0x01,0x00,0x60,0x80,0x01,0x00,0x60,0x80,0x01,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 198 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0x60,0x00,0x30,0x02,0x60,0x00,0x30,0x02,0x60,0x00,0xF0,0x02,0x60,0x00,0xB0,0x03,0x60,0x00,0x30,0x01,0x60,0x00,0x30,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x03,0x0F,0x00,0x00,0x02,0x03, // 199 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x62,0x30,0x30,0x00,0x66,0x30,0x30,0x00,0x6E,0x30,0x30,0x00,0x68,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 200 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x68,0x30,0x30,0x00,0x6E,0x30,0x30,0x00,0x66,0x30,0x30,0x00,0x62,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 201 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x68,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x66,0x30,0x30,0x00,0x66,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x68,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 202 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x6C,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30, // 203 + 0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0xE6,0xFF,0x3F,0x00,0xEE,0xFF,0x3F,0x00,0x08, // 204 + 0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0xEE,0xFF,0x3F,0x00,0xE6,0xFF,0x3F,0x00,0x02, // 205 + 0x08,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0xE6,0xFF,0x3F,0x00,0xE6,0xFF,0x3F,0x00,0x0C,0x00,0x00,0x00,0x08, // 206 + 0x0C,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x0C,0x00,0x00,0x00,0x0C, // 207 + 0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x30,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x03,0x0E,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 208 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0xC0,0x01,0x00,0x00,0x8C,0x03,0x00,0x00,0x0E,0x0E,0x00,0x00,0x06,0x3C,0x00,0x00,0x06,0x70,0x00,0x00,0x0C,0xE0,0x01,0x00,0x0C,0x80,0x03,0x00,0x0E,0x00,0x0F,0x00,0x06,0x00,0x1C,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F, // 209 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x38,0x00,0x62,0x00,0x30,0x00,0x66,0x00,0x30,0x00,0x6E,0x00,0x30,0x00,0x68,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 210 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x38,0x00,0x60,0x00,0x30,0x00,0x68,0x00,0x30,0x00,0x6E,0x00,0x30,0x00,0x66,0x00,0x30,0x00,0x62,0x00,0x30,0x00,0xE0,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 211 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x38,0x00,0x68,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0x66,0x00,0x30,0x00,0x66,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0xE8,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 212 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xCC,0x00,0x18,0x00,0xEE,0x00,0x38,0x00,0x66,0x00,0x30,0x00,0x66,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0x6E,0x00,0x30,0x00,0xE6,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 213 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x00,0x00,0xFF,0x07,0x00,0x80,0x07,0x0F,0x00,0xC0,0x01,0x1C,0x00,0xC0,0x00,0x18,0x00,0xE0,0x00,0x38,0x00,0x6C,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x6C,0x00,0x30,0x00,0xEC,0x00,0x38,0x00,0xC0,0x00,0x18,0x00,0xC0,0x01,0x1C,0x00,0x80,0x07,0x0F,0x00,0x00,0xFF,0x07,0x00,0x00,0xFC,0x01, // 214 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x03,0x00,0x00,0x8E,0x03,0x00,0x00,0xDC,0x01,0x00,0x00,0xF8,0x00,0x00,0x00,0x70,0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0xDC,0x01,0x00,0x00,0x8E,0x03,0x00,0x00,0x06,0x03, // 215 + 0x00,0x00,0x00,0x00,0x00,0xFC,0x21,0x00,0x00,0xFF,0x77,0x00,0x80,0x07,0x3F,0x00,0xC0,0x01,0x1E,0x00,0xC0,0x00,0x1F,0x00,0xE0,0x80,0x3B,0x00,0x60,0xC0,0x31,0x00,0x60,0xE0,0x30,0x00,0x60,0x70,0x30,0x00,0x60,0x38,0x30,0x00,0x60,0x1C,0x30,0x00,0xE0,0x0E,0x38,0x00,0xC0,0x07,0x18,0x00,0xC0,0x03,0x1C,0x00,0xE0,0x07,0x0F,0x00,0x70,0xFF,0x07,0x00,0x20,0xFC,0x01, // 216 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x03,0x00,0xE0,0xFF,0x0F,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x38,0x00,0x02,0x00,0x30,0x00,0x06,0x00,0x30,0x00,0x0E,0x00,0x30,0x00,0x08,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x0F,0x00,0xE0,0xFF,0x03, // 217 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x03,0x00,0xE0,0xFF,0x0F,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x30,0x00,0x08,0x00,0x30,0x00,0x0E,0x00,0x30,0x00,0x06,0x00,0x30,0x00,0x02,0x00,0x30,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x0F,0x00,0xE0,0xFF,0x03, // 218 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x03,0x00,0xE0,0xFF,0x0F,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x38,0x00,0x08,0x00,0x30,0x00,0x0C,0x00,0x30,0x00,0x06,0x00,0x30,0x00,0x06,0x00,0x30,0x00,0x0C,0x00,0x30,0x00,0x08,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x0F,0x00,0xE0,0xFF,0x03, // 219 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x03,0x00,0xE0,0xFF,0x0F,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x38,0x00,0x0C,0x00,0x30,0x00,0x0C,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x0C,0x00,0x30,0x00,0x0C,0x00,0x38,0x00,0x00,0x00,0x1C,0x00,0xE0,0xFF,0x0F,0x00,0xE0,0xFF,0x03, // 220 + 0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xC0,0x01,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x3C,0x00,0x00,0x08,0xF0,0x3F,0x00,0x0E,0xF0,0x3F,0x00,0x06,0x3C,0x00,0x00,0x02,0x1E,0x00,0x00,0x00,0x07,0x00,0x00,0xC0,0x03,0x00,0x00,0xE0,0x01,0x00,0x00,0x60,0x00,0x00,0x00,0x20, // 221 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0x3F,0x00,0xE0,0xFF,0x3F,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x06,0x00,0x00,0x03,0x07,0x00,0x00,0x86,0x03,0x00,0x00,0xFE,0x01,0x00,0x00,0xF8, // 222 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xFF,0x3F,0x00,0xC0,0xFF,0x3F,0x00,0xC0,0x00,0x00,0x00,0x60,0x00,0x08,0x00,0x60,0x00,0x1C,0x00,0x60,0x00,0x38,0x00,0xE0,0x78,0x30,0x00,0xC0,0x7F,0x30,0x00,0x80,0xC7,0x30,0x00,0x00,0x80,0x39,0x00,0x00,0x80,0x1F,0x00,0x00,0x00,0x0F, // 223 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0x00,0x8C,0x39,0x00,0x20,0x86,0x31,0x00,0x60,0x86,0x31,0x00,0xE0,0xC6,0x30,0x00,0x80,0xC6,0x18,0x00,0x00,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 224 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0x00,0x8C,0x39,0x00,0x00,0x86,0x31,0x00,0x80,0x86,0x31,0x00,0xE0,0xC6,0x30,0x00,0x60,0xC6,0x18,0x00,0x20,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 225 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0x80,0x8C,0x39,0x00,0xC0,0x86,0x31,0x00,0x60,0x86,0x31,0x00,0x60,0xC6,0x30,0x00,0xC0,0xC6,0x18,0x00,0x80,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 226 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0xC0,0x1C,0x1F,0x00,0xE0,0x8C,0x39,0x00,0x60,0x86,0x31,0x00,0x60,0x86,0x31,0x00,0xC0,0xC6,0x30,0x00,0xC0,0xC6,0x18,0x00,0xE0,0xCE,0x0C,0x00,0x60,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 227 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0xC0,0x8C,0x39,0x00,0xC0,0x86,0x31,0x00,0x00,0x86,0x31,0x00,0x00,0xC6,0x30,0x00,0xC0,0xC6,0x18,0x00,0xC0,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 228 + 0x00,0x00,0x00,0x00,0x00,0x18,0x0E,0x00,0x00,0x1C,0x1F,0x00,0x00,0x8C,0x39,0x00,0x70,0x86,0x31,0x00,0x88,0x86,0x31,0x00,0x88,0xC6,0x30,0x00,0x88,0xC6,0x18,0x00,0x70,0xCE,0x0C,0x00,0x00,0xFC,0x1F,0x00,0x00,0xF8,0x3F,0x00,0x00,0x00,0x20, // 229 + 0x00,0x00,0x00,0x00,0x00,0x10,0x0F,0x00,0x00,0x9C,0x1F,0x00,0x00,0xCC,0x39,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0x66,0x18,0x00,0x00,0x6E,0x1C,0x00,0x00,0xFC,0x0F,0x00,0x00,0xFC,0x1F,0x00,0x00,0xCC,0x1C,0x00,0x00,0xCE,0x38,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xCC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xE0,0x04, // 230 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x02,0x00,0x06,0x30,0x02,0x00,0x06,0xF0,0x02,0x00,0x06,0xB0,0x03,0x00,0x0E,0x38,0x01,0x00,0x1C,0x1C,0x00,0x00,0x18,0x0C, // 231 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0xDC,0x1C,0x00,0x20,0xCE,0x38,0x00,0x60,0xC6,0x30,0x00,0xE0,0xC6,0x30,0x00,0x80,0xC6,0x30,0x00,0x00,0xCE,0x38,0x00,0x00,0xDC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xF0,0x04, // 232 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0xDC,0x1C,0x00,0x00,0xCE,0x38,0x00,0x80,0xC6,0x30,0x00,0xE0,0xC6,0x30,0x00,0x60,0xC6,0x30,0x00,0x20,0xCE,0x38,0x00,0x00,0xDC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xF0,0x04, // 233 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0xDC,0x1C,0x00,0x80,0xCE,0x38,0x00,0xC0,0xC6,0x30,0x00,0x60,0xC6,0x30,0x00,0x60,0xC6,0x30,0x00,0xC0,0xCE,0x38,0x00,0x80,0xDC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xF0,0x04, // 234 + 0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0xDC,0x1C,0x00,0xC0,0xCE,0x38,0x00,0xC0,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0x00,0xC6,0x30,0x00,0xC0,0xCE,0x38,0x00,0xC0,0xDC,0x18,0x00,0x00,0xF8,0x0C,0x00,0x00,0xF0,0x04, // 235 + 0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0xFE,0x3F,0x00,0xE0,0xFE,0x3F,0x00,0x80, // 236 + 0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xE0,0xFE,0x3F,0x00,0x60,0xFE,0x3F,0x00,0x20, // 237 + 0x80,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x60,0xFE,0x3F,0x00,0x60,0xFE,0x3F,0x00,0xC0,0x00,0x00,0x00,0x80, // 238 + 0xC0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F,0x00,0xC0,0x00,0x00,0x00,0xC0, // 239 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1D,0x1C,0x00,0xA0,0x0F,0x38,0x00,0xA0,0x06,0x30,0x00,0xE0,0x06,0x30,0x00,0xC0,0x06,0x30,0x00,0xC0,0x0F,0x38,0x00,0x20,0x1F,0x1C,0x00,0x00,0xFC,0x0F,0x00,0x00,0xE0,0x07, // 240 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x3F,0x00,0xC0,0xFE,0x3F,0x00,0xE0,0x18,0x00,0x00,0x60,0x0C,0x00,0x00,0x60,0x06,0x00,0x00,0xC0,0x06,0x00,0x00,0xC0,0x06,0x00,0x00,0xE0,0x0E,0x00,0x00,0x60,0xFC,0x3F,0x00,0x00,0xF8,0x3F, // 241 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x20,0x0E,0x38,0x00,0x60,0x06,0x30,0x00,0xE0,0x06,0x30,0x00,0x80,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 242 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x38,0x00,0x80,0x06,0x30,0x00,0xE0,0x06,0x30,0x00,0x60,0x06,0x30,0x00,0x20,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 243 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0x80,0x0E,0x38,0x00,0xC0,0x06,0x30,0x00,0x60,0x06,0x30,0x00,0x60,0x06,0x30,0x00,0xC0,0x0E,0x38,0x00,0x80,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 244 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0xC0,0x1C,0x1C,0x00,0xE0,0x0E,0x38,0x00,0x60,0x06,0x30,0x00,0x60,0x06,0x30,0x00,0xC0,0x06,0x30,0x00,0xC0,0x0E,0x38,0x00,0xE0,0x1C,0x1C,0x00,0x60,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 245 + 0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x00,0x00,0xF8,0x0F,0x00,0x00,0x1C,0x1C,0x00,0xC0,0x0E,0x38,0x00,0xC0,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0xC0,0x0E,0x38,0x00,0xC0,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x07, // 246 + 0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0xB6,0x01,0x00,0x00,0xB6,0x01,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30, // 247 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x67,0x00,0x00,0xF8,0x7F,0x00,0x00,0x1C,0x1C,0x00,0x00,0x0E,0x3F,0x00,0x00,0x86,0x33,0x00,0x00,0xE6,0x31,0x00,0x00,0x76,0x30,0x00,0x00,0x3E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xFF,0x0F,0x00,0x00,0xF3,0x07, // 248 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x0F,0x00,0x00,0xFE,0x1F,0x00,0x20,0x00,0x38,0x00,0x60,0x00,0x30,0x00,0xE0,0x00,0x30,0x00,0x80,0x00,0x30,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x0C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 249 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x0F,0x00,0x00,0xFE,0x1F,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x30,0x00,0x80,0x00,0x30,0x00,0xE0,0x00,0x30,0x00,0x60,0x00,0x18,0x00,0x20,0x00,0x0C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 250 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x0F,0x00,0x00,0xFE,0x1F,0x00,0x80,0x00,0x38,0x00,0xC0,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0x60,0x00,0x30,0x00,0xC0,0x00,0x18,0x00,0x80,0x00,0x0C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 251 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x0F,0x00,0x00,0xFE,0x1F,0x00,0xC0,0x00,0x38,0x00,0xC0,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x30,0x00,0xC0,0x00,0x18,0x00,0xC0,0x00,0x0C,0x00,0x00,0xFE,0x3F,0x00,0x00,0xFE,0x3F, // 252 + 0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x7E,0x00,0x06,0x00,0xF0,0x01,0x06,0x00,0x80,0x0F,0x07,0x80,0x00,0xFE,0x03,0xE0,0x00,0xFC,0x00,0x60,0xC0,0x1F,0x00,0x20,0xF8,0x03,0x00,0x00,0x3E,0x00,0x00,0x00,0x06, // 253 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0xFF,0xFF,0x07,0xE0,0xFF,0xFF,0x07,0x00,0x1C,0x18,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x1C,0x1C,0x00,0x00,0xF8,0x0F,0x00,0x00,0xF0,0x03, // 254 + 0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x7E,0x00,0x06,0xC0,0xF0,0x01,0x06,0xC0,0x80,0x0F,0x07,0x00,0x00,0xFE,0x03,0x00,0x00,0xFC,0x00,0xC0,0xC0,0x1F,0x00,0xC0,0xF8,0x03,0x00,0x00,0x3E,0x00,0x00,0x00,0x06 // 255 +}; +#endif diff --git a/libraries/SSD1306_SPI/OLEDDisplayUi.cpp b/libraries/SSD1306_SPI/OLEDDisplayUi.cpp new file mode 100644 index 00000000..d7a6ba84 --- /dev/null +++ b/libraries/SSD1306_SPI/OLEDDisplayUi.cpp @@ -0,0 +1,460 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * Copyright (c) 2019 by Helmut Tschemernjak - www.radioshuttle.de + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + +#include "OLEDDisplayUi.h" + +void LoadingDrawDefault(OLEDDisplay *display, LoadingStage* stage, uint8_t progress) { + display->setTextAlignment(TEXT_ALIGN_CENTER); + display->setFont(ArialMT_Plain_10); + display->drawString(64, 18, stage->process); + display->drawProgressBar(4, 32, 120, 8, progress); +}; + + +OLEDDisplayUi::OLEDDisplayUi(OLEDDisplay *display) { + this->display = display; + + indicatorPosition = BOTTOM; + indicatorDirection = LEFT_RIGHT; + activeSymbol = ANIMATION_activeSymbol; + inactiveSymbol = ANIMATION_inactiveSymbol; + frameAnimationDirection = SLIDE_RIGHT; + lastTransitionDirection = 1; + ticksPerFrame = 151; // ~ 5000ms at 30 FPS + ticksPerTransition = 15; // ~ 500ms at 30 FPS + frameCount = 0; + nextFrameNumber = -1; + overlayCount = 0; + indicatorDrawState = 1; + loadingDrawFunction = LoadingDrawDefault; + updateInterval = 33; + state.lastUpdate = 0; + state.ticksSinceLastStateSwitch = 0; + state.frameState = FIXED; + state.currentFrame = 0; + state.frameTransitionDirection = 1; + state.isIndicatorDrawen = true; + state.manuelControll = false; + state.userData = NULL; + shouldDrawIndicators = true; + autoTransition = true; +} + +void OLEDDisplayUi::init() { + this->display->init(); +} + +void OLEDDisplayUi::setTargetFPS(uint8_t fps){ + float oldInterval = this->updateInterval; + this->updateInterval = ((float) 1.0 / (float) fps) * 1000; + + // Calculate new ticksPerFrame + float changeRatio = oldInterval / (float) this->updateInterval; + this->ticksPerFrame *= changeRatio; + this->ticksPerTransition *= changeRatio; +} + +// -/------ Automatic controll ------\- + +void OLEDDisplayUi::enableAutoTransition(){ + this->autoTransition = true; +} +void OLEDDisplayUi::disableAutoTransition(){ + this->autoTransition = false; +} +void OLEDDisplayUi::setAutoTransitionForwards(){ + this->state.frameTransitionDirection = 1; + this->lastTransitionDirection = 1; +} +void OLEDDisplayUi::setAutoTransitionBackwards(){ + this->state.frameTransitionDirection = -1; + this->lastTransitionDirection = -1; +} +void OLEDDisplayUi::setTimePerFrame(uint16_t time){ + this->ticksPerFrame = (uint16_t) ( (float) time / (float) updateInterval); +} +void OLEDDisplayUi::setTimePerTransition(uint16_t time){ + this->ticksPerTransition = (uint16_t) ( (float) time / (float) updateInterval); +} + +// -/------ Customize indicator position and style -------\- +void OLEDDisplayUi::enableIndicator(){ + this->state.isIndicatorDrawen = true; +} + +void OLEDDisplayUi::disableIndicator(){ + this->state.isIndicatorDrawen = false; +} + +void OLEDDisplayUi::enableAllIndicators(){ + this->shouldDrawIndicators = true; +} + +void OLEDDisplayUi::disableAllIndicators(){ + this->shouldDrawIndicators = false; +} + +void OLEDDisplayUi::setIndicatorPosition(IndicatorPosition pos) { + this->indicatorPosition = pos; +} +void OLEDDisplayUi::setIndicatorDirection(IndicatorDirection dir) { + this->indicatorDirection = dir; +} +void OLEDDisplayUi::setActiveSymbol(const uint8_t* symbol) { + this->activeSymbol = symbol; +} +void OLEDDisplayUi::setInactiveSymbol(const uint8_t* symbol) { + this->inactiveSymbol = symbol; +} + + +// -/----- Frame settings -----\- +void OLEDDisplayUi::setFrameAnimation(AnimationDirection dir) { + this->frameAnimationDirection = dir; +} +void OLEDDisplayUi::setFrames(FrameCallback* frameFunctions, uint8_t frameCount) { + this->frameFunctions = frameFunctions; + this->frameCount = frameCount; + this->resetState(); +} + +// -/----- Overlays ------\- +void OLEDDisplayUi::setOverlays(OverlayCallback* overlayFunctions, uint8_t overlayCount){ + this->overlayFunctions = overlayFunctions; + this->overlayCount = overlayCount; +} + +// -/----- Loading Process -----\- + +void OLEDDisplayUi::setLoadingDrawFunction(LoadingDrawFunction loadingDrawFunction) { + this->loadingDrawFunction = loadingDrawFunction; +} + +void OLEDDisplayUi::runLoadingProcess(LoadingStage* stages, uint8_t stagesCount) { + uint8_t progress = 0; + uint8_t increment = 100 / stagesCount; + + for (uint8_t i = 0; i < stagesCount; i++) { + display->clear(); + this->loadingDrawFunction(this->display, &stages[i], progress); + display->display(); + + stages[i].callback(); + + progress += increment; + yield(); + } + + display->clear(); + this->loadingDrawFunction(this->display, &stages[stagesCount-1], progress); + display->display(); + + delay(150); +} + +// -/----- Manuel control -----\- +void OLEDDisplayUi::nextFrame() { + if (this->state.frameState != IN_TRANSITION) { + this->state.manuelControll = true; + this->state.frameState = IN_TRANSITION; + this->state.ticksSinceLastStateSwitch = 0; + this->lastTransitionDirection = this->state.frameTransitionDirection; + this->state.frameTransitionDirection = 1; + } +} +void OLEDDisplayUi::previousFrame() { + if (this->state.frameState != IN_TRANSITION) { + this->state.manuelControll = true; + this->state.frameState = IN_TRANSITION; + this->state.ticksSinceLastStateSwitch = 0; + this->lastTransitionDirection = this->state.frameTransitionDirection; + this->state.frameTransitionDirection = -1; + } +} + +void OLEDDisplayUi::switchToFrame(uint8_t frame) { + if (frame >= this->frameCount) return; + this->state.ticksSinceLastStateSwitch = 0; + if (frame == this->state.currentFrame) return; + this->state.frameState = FIXED; + this->state.currentFrame = frame; + this->state.isIndicatorDrawen = true; +} + +void OLEDDisplayUi::transitionToFrame(uint8_t frame) { + if (frame >= this->frameCount) return; + this->state.ticksSinceLastStateSwitch = 0; + if (frame == this->state.currentFrame) return; + this->nextFrameNumber = frame; + this->lastTransitionDirection = this->state.frameTransitionDirection; + this->state.manuelControll = true; + this->state.frameState = IN_TRANSITION; + this->state.frameTransitionDirection = frame < this->state.currentFrame ? -1 : 1; +} + + +// -/----- State information -----\- +OLEDDisplayUiState* OLEDDisplayUi::getUiState(){ + return &this->state; +} + + +int8_t OLEDDisplayUi::update(){ + + unsigned long frameStart = millis(); + + int8_t timeBudget = this->updateInterval - (frameStart - this->state.lastUpdate); + if ( timeBudget <= 0) { + // Implement frame skipping to ensure time budget is keept + if (this->autoTransition && this->state.lastUpdate != 0) this->state.ticksSinceLastStateSwitch += ceil((double)-timeBudget / (double)this->updateInterval); + + this->state.lastUpdate = frameStart; + this->tick(); + } + + return this->updateInterval - (millis() - frameStart); + +} + + +void OLEDDisplayUi::tick() { + this->state.ticksSinceLastStateSwitch++; + + switch (this->state.frameState) { + case IN_TRANSITION: + if (this->state.ticksSinceLastStateSwitch >= this->ticksPerTransition){ + this->state.frameState = FIXED; + this->state.currentFrame = getNextFrameNumber(); + this->state.ticksSinceLastStateSwitch = 0; + this->nextFrameNumber = -1; + } + break; + case FIXED: + // Revert manuelControll + if (this->state.manuelControll) { + this->state.frameTransitionDirection = this->lastTransitionDirection; + this->state.manuelControll = false; + } + if (this->state.ticksSinceLastStateSwitch >= this->ticksPerFrame){ + if (this->autoTransition){ + this->state.frameState = IN_TRANSITION; + } + this->state.ticksSinceLastStateSwitch = 0; + } + break; + } + + this->display->clear(); + this->drawFrame(); + if (shouldDrawIndicators) { + this->drawIndicator(); + } + this->drawOverlays(); + this->display->display(); +} + +void OLEDDisplayUi::resetState() { + this->state.lastUpdate = 0; + this->state.ticksSinceLastStateSwitch = 0; + this->state.frameState = FIXED; + this->state.currentFrame = 0; + this->state.isIndicatorDrawen = true; +} + +void OLEDDisplayUi::drawFrame(){ + switch (this->state.frameState){ + case IN_TRANSITION: { + float progress = (float) this->state.ticksSinceLastStateSwitch / (float) this->ticksPerTransition; + int16_t x = 0, y = 0, x1 = 0, y1 = 0; + switch(this->frameAnimationDirection){ + case SLIDE_LEFT: + x = -this->display->width() * progress; + y = 0; + x1 = x + this->display->width(); + y1 = 0; + break; + case SLIDE_RIGHT: + x = this->display->width() * progress; + y = 0; + x1 = x - this->display->width(); + y1 = 0; + break; + case SLIDE_UP: + x = 0; + y = -this->display->height() * progress; + x1 = 0; + y1 = y + this->display->height(); + break; + case SLIDE_DOWN: + default: + x = 0; + y = this->display->height() * progress; + x1 = 0; + y1 = y - this->display->height(); + break; + } + + // Invert animation if direction is reversed. + int8_t dir = this->state.frameTransitionDirection >= 0 ? 1 : -1; + x *= dir; y *= dir; x1 *= dir; y1 *= dir; + + bool drawenCurrentFrame; + + + // Prope each frameFunction for the indicator Drawen state + this->enableIndicator(); + (this->frameFunctions[this->state.currentFrame])(this->display, &this->state, x, y); + drawenCurrentFrame = this->state.isIndicatorDrawen; + + this->enableIndicator(); + (this->frameFunctions[this->getNextFrameNumber()])(this->display, &this->state, x1, y1); + + // Build up the indicatorDrawState + if (drawenCurrentFrame && !this->state.isIndicatorDrawen) { + // Drawen now but not next + this->indicatorDrawState = 2; + } else if (!drawenCurrentFrame && this->state.isIndicatorDrawen) { + // Not drawen now but next + this->indicatorDrawState = 1; + } else if (!drawenCurrentFrame && !this->state.isIndicatorDrawen) { + // Not drawen in both frames + this->indicatorDrawState = 3; + } + + // If the indicator isn't draw in the current frame + // reflect it in state.isIndicatorDrawen + if (!drawenCurrentFrame) this->state.isIndicatorDrawen = false; + + break; + } + case FIXED: + // Always assume that the indicator is drawn! + // And set indicatorDrawState to "not known yet" + this->indicatorDrawState = 0; + this->enableIndicator(); + (this->frameFunctions[this->state.currentFrame])(this->display, &this->state, 0, 0); + break; + } +} + +void OLEDDisplayUi::drawIndicator() { + + // Only draw if the indicator is invisible + // for both frames or + // the indiactor is shown and we are IN_TRANSITION + if (this->indicatorDrawState == 3 || (!this->state.isIndicatorDrawen && this->state.frameState != IN_TRANSITION)) { + return; + } + + uint8_t posOfHighlightFrame = 0; + float indicatorFadeProgress = 0; + + // if the indicator needs to be slided in we want to + // highlight the next frame in the transition + uint8_t frameToHighlight = this->indicatorDrawState == 1 ? this->getNextFrameNumber() : this->state.currentFrame; + + // Calculate the frame that needs to be highlighted + // based on the Direction the indiactor is drawn + switch (this->indicatorDirection){ + case LEFT_RIGHT: + posOfHighlightFrame = frameToHighlight; + break; + case RIGHT_LEFT: + default: + posOfHighlightFrame = this->frameCount - frameToHighlight; + break; + } + + switch (this->indicatorDrawState) { + case 1: // Indicator was not drawn in this frame but will be in next + // Slide IN + indicatorFadeProgress = 1 - ((float) this->state.ticksSinceLastStateSwitch / (float) this->ticksPerTransition); + break; + case 2: // Indicator was drawn in this frame but not in next + // Slide OUT + indicatorFadeProgress = ((float) this->state.ticksSinceLastStateSwitch / (float) this->ticksPerTransition); + break; + } + + //Space between indicators - reduce for small screen sizes + uint16_t indicatorSpacing = 12; + if (this->display->getHeight() < 64 && (this->indicatorPosition == RIGHT || this->indicatorPosition == LEFT)) { + indicatorSpacing = 6; + } + + uint16_t frameStartPos = (indicatorSpacing * frameCount / 2); + const uint8_t *image; + + uint16_t x = 0,y = 0; + + + for (uint8_t i = 0; i < this->frameCount; i++) { + + switch (this->indicatorPosition){ + case TOP: + y = 0 - (8 * indicatorFadeProgress); + x = (this->display->width() / 2) - frameStartPos + 12 * i; + break; + case BOTTOM: + y = (this->display->height() - 8) + (8 * indicatorFadeProgress); + x = (this->display->width() / 2) - frameStartPos + 12 * i; + break; + case RIGHT: + x = (this->display->width() - 8) + (8 * indicatorFadeProgress); + y = (this->display->height() / 2) - frameStartPos + 2 + 12 * i; + break; + case LEFT: + default: + x = 0 - (8 * indicatorFadeProgress); + y = (this->display->height() / 2) - frameStartPos + 2 + indicatorSpacing * i; + break; + } + + if (posOfHighlightFrame == i) { + image = this->activeSymbol; + } else { + image = this->inactiveSymbol; + } + + this->display->drawFastImage(x, y, 8, 8, image); + } +} + +void OLEDDisplayUi::drawOverlays() { + for (uint8_t i=0;ioverlayCount;i++){ + (this->overlayFunctions[i])(this->display, &this->state); + } +} + +uint8_t OLEDDisplayUi::getNextFrameNumber(){ + if (this->nextFrameNumber != -1) return this->nextFrameNumber; + return (this->state.currentFrame + this->frameCount + this->state.frameTransitionDirection) % this->frameCount; +} diff --git a/libraries/SSD1306_SPI/OLEDDisplayUi.h b/libraries/SSD1306_SPI/OLEDDisplayUi.h new file mode 100644 index 00000000..749ebfae --- /dev/null +++ b/libraries/SSD1306_SPI/OLEDDisplayUi.h @@ -0,0 +1,309 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * Copyright (c) 2019 by Helmut Tschemernjak - www.radioshuttle.de + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + +#ifndef OLEDDISPLAYUI_h +#define OLEDDISPLAYUI_h + + +#include + + + +#include "OLEDDisplay.h" + +//#define DEBUG_OLEDDISPLAYUI(...) Serial.printf( __VA_ARGS__ ) + +#ifndef DEBUG_OLEDDISPLAYUI +#define DEBUG_OLEDDISPLAYUI(...) +#endif + +enum AnimationDirection { + SLIDE_UP, + SLIDE_DOWN, + SLIDE_LEFT, + SLIDE_RIGHT +}; + +enum IndicatorPosition { + TOP, + RIGHT, + BOTTOM, + LEFT +}; + +enum IndicatorDirection { + LEFT_RIGHT, + RIGHT_LEFT +}; + +enum FrameState { + IN_TRANSITION, + FIXED +}; + + +const uint8_t ANIMATION_activeSymbol[] PROGMEM = { + 0x00, 0x18, 0x3c, 0x7e, 0x7e, 0x3c, 0x18, 0x00 +}; + +const uint8_t ANIMATION_inactiveSymbol[] PROGMEM = { + 0x00, 0x0, 0x0, 0x18, 0x18, 0x0, 0x0, 0x00 +}; + + +// Structure of the UiState +struct OLEDDisplayUiState { + uint64_t lastUpdate; + uint16_t ticksSinceLastStateSwitch; + + FrameState frameState; + uint8_t currentFrame; + + bool isIndicatorDrawen; + + // Normal = 1, Inverse = -1; + int8_t frameTransitionDirection; + + bool manuelControll; + + // Custom data that can be used by the user + void* userData; +}; + +struct LoadingStage { + const char* process; + void (*callback)(); +}; + +typedef void (*FrameCallback)(OLEDDisplay *display, OLEDDisplayUiState* state, int16_t x, int16_t y); +typedef void (*OverlayCallback)(OLEDDisplay *display, OLEDDisplayUiState* state); +typedef void (*LoadingDrawFunction)(OLEDDisplay *display, LoadingStage* stage, uint8_t progress); + +class OLEDDisplayUi { + private: + OLEDDisplay *display; + + // Symbols for the Indicator + IndicatorPosition indicatorPosition; + IndicatorDirection indicatorDirection; + + const uint8_t* activeSymbol; + const uint8_t* inactiveSymbol; + + bool shouldDrawIndicators; + + // Values for the Frames + AnimationDirection frameAnimationDirection; + + int8_t lastTransitionDirection; + + uint16_t ticksPerFrame; // ~ 5000ms at 30 FPS + uint16_t ticksPerTransition; // ~ 500ms at 30 FPS + + bool autoTransition; + + FrameCallback* frameFunctions; + uint8_t frameCount; + + // Internally used to transition to a specific frame + int8_t nextFrameNumber; + + // Values for Overlays + OverlayCallback* overlayFunctions; + uint8_t overlayCount; + + // Will the Indicator be drawen + // 3 Not drawn in both frames + // 2 Drawn this frame but not next + // 1 Not drown this frame but next + // 0 Not known yet + uint8_t indicatorDrawState; + + // Loading screen + LoadingDrawFunction loadingDrawFunction; + + // UI State + OLEDDisplayUiState state; + + // Bookeeping for update + uint8_t updateInterval; + + uint8_t getNextFrameNumber(); + void drawIndicator(); + void drawFrame(); + void drawOverlays(); + void tick(); + void resetState(); + + public: + + OLEDDisplayUi(OLEDDisplay *display); + + /** + * Initialise the display + */ + void init(); + + /** + * Configure the internal used target FPS + */ + void setTargetFPS(uint8_t fps); + + // Automatic Controll + /** + * Enable automatic transition to next frame after the some time can be configured with `setTimePerFrame` and `setTimePerTransition`. + */ + void enableAutoTransition(); + + /** + * Disable automatic transition to next frame. + */ + void disableAutoTransition(); + + /** + * Set the direction if the automatic transitioning + */ + void setAutoTransitionForwards(); + void setAutoTransitionBackwards(); + + /** + * Set the approx. time a frame is displayed + */ + void setTimePerFrame(uint16_t time); + + /** + * Set the approx. time a transition will take + */ + void setTimePerTransition(uint16_t time); + + // Customize indicator position and style + + /** + * Draw the indicator. + * This is the defaut state for all frames if + * the indicator was hidden on the previous frame + * it will be slided in. + */ + void enableIndicator(); + + /** + * Don't draw the indicator. + * This will slide out the indicator + * when transitioning to the next frame. + */ + void disableIndicator(); + + /** + * Enable drawing of indicators + */ + void enableAllIndicators(); + + /** + * Disable draw of indicators. + */ + void disableAllIndicators(); + + /** + * Set the position of the indicator bar. + */ + void setIndicatorPosition(IndicatorPosition pos); + + /** + * Set the direction of the indicator bar. Defining the order of frames ASCENDING / DESCENDING + */ + void setIndicatorDirection(IndicatorDirection dir); + + /** + * Set the symbol to indicate an active frame in the indicator bar. + */ + void setActiveSymbol(const uint8_t* symbol); + + /** + * Set the symbol to indicate an inactive frame in the indicator bar. + */ + void setInactiveSymbol(const uint8_t* symbol); + + + // Frame settings + + /** + * Configure what animation is used to transition from one frame to another + */ + void setFrameAnimation(AnimationDirection dir); + + /** + * Add frame drawing functions + */ + void setFrames(FrameCallback* frameFunctions, uint8_t frameCount); + + // Overlay + + /** + * Add overlays drawing functions that are draw independent of the Frames + */ + void setOverlays(OverlayCallback* overlayFunctions, uint8_t overlayCount); + + + // Loading animation + /** + * Set the function that will draw each step + * in the loading animation + */ + void setLoadingDrawFunction(LoadingDrawFunction loadingFunction); + + + /** + * Run the loading process + */ + void runLoadingProcess(LoadingStage* stages, uint8_t stagesCount); + + + // Manual Control + void nextFrame(); + void previousFrame(); + + /** + * Switch without transition to frame `frame`. + */ + void switchToFrame(uint8_t frame); + + /** + * Transition to frame `frame`, when the `frame` number is bigger than the current + * frame the forward animation will be used, otherwise the backwards animation is used. + */ + void transitionToFrame(uint8_t frame); + + // State Info + OLEDDisplayUiState* getUiState(); + + int8_t update(); +}; +#endif diff --git a/libraries/SSD1306_SPI/SSD1306.h b/libraries/SSD1306_SPI/SSD1306.h new file mode 100644 index 00000000..f6bd554c --- /dev/null +++ b/libraries/SSD1306_SPI/SSD1306.h @@ -0,0 +1,39 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + +#ifndef SSD1306_h +#define SSD1306_h +#include "SSD1306Wire.h" + +// For legacy support make SSD1306 an alias for SSD1306 +typedef SSD1306Wire SSD1306; + + +#endif diff --git a/libraries/SSD1306_SPI/SSD1306Spi.h b/libraries/SSD1306_SPI/SSD1306Spi.h new file mode 100644 index 00000000..3041c6fb --- /dev/null +++ b/libraries/SSD1306_SPI/SSD1306Spi.h @@ -0,0 +1,162 @@ +/** + * The MIT License (MIT) + * + * Copyright (c) 2018 by ThingPulse, Daniel Eichhorn + * Copyright (c) 2018 by Fabrice Weinberg + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * ThingPulse invests considerable time and money to develop these open source libraries. + * Please support us by buying our products (and not the clones) from + * https://thingpulse.com + * + */ + +#ifndef SSD1306Spi_h +#define SSD1306Spi_h + +#include "OLEDDisplay.h" +#include + +#if F_CPU == 160000000L + #define BRZO_I2C_SPEED 1000 +#else + #define BRZO_I2C_SPEED 800 +#endif + +class SSD1306Spi : public OLEDDisplay { + private: + uint8_t _rst; + uint8_t _dc; + uint8_t _cs; + + public: + SSD1306Spi(uint8_t _rst, uint8_t _dc, uint8_t _cs, OLEDDISPLAY_GEOMETRY g = GEOMETRY_128_64) { + setGeometry(g); + + this->_rst = _rst; + this->_dc = _dc; + this->_cs = _cs; + } + + bool connect(){ + pinMode(_dc, OUTPUT); + pinMode(_cs, OUTPUT); + pinMode(_rst, OUTPUT); + + SPI.begin (); + + // Pulse Reset low for 10ms + digitalWrite(_rst, HIGH); + delay(1); + digitalWrite(_rst, LOW); + delay(10); + digitalWrite(_rst, HIGH); + return true; + } + + void display(void) { + #ifdef OLEDDISPLAY_DOUBLE_BUFFER + uint8_t minBoundY = UINT8_MAX; + uint8_t maxBoundY = 0; + + uint8_t minBoundX = UINT8_MAX; + uint8_t maxBoundX = 0; + + uint8_t x, y; + + // Calculate the Y bounding box of changes + // and copy buffer[pos] to buffer_back[pos]; + for (y = 0; y < (displayHeight / 8); y++) { + for (x = 0; x < displayWidth; x++) { + uint16_t pos = x + y * displayWidth; + if (buffer[pos] != buffer_back[pos]) { + minBoundY = _min(minBoundY, y); + maxBoundY = _max(maxBoundY, y); + minBoundX = _min(minBoundX, x); + maxBoundX = _max(maxBoundX, x); + } + buffer_back[pos] = buffer[pos]; + } + // yield(); + } + + // If the minBoundY wasn't updated + // we can savely assume that buffer_back[pos] == buffer[pos] + // holdes true for all values of pos + if (minBoundY == UINT8_MAX) return; + + sendCommand(COLUMNADDR); + sendCommand(minBoundX); + sendCommand(maxBoundX); + + sendCommand(PAGEADDR); + sendCommand(minBoundY); + sendCommand(maxBoundY); + + digitalWrite(_cs, HIGH); + digitalWrite(_dc, HIGH); // data mode + digitalWrite(_cs, LOW); + for (y = minBoundY; y <= maxBoundY; y++) { + for (x = minBoundX; x <= maxBoundX; x++) { + SPI.transfer(buffer[x + y * displayWidth]); + } + // yield(); + } + digitalWrite(_cs, HIGH); + #else + // No double buffering + sendCommand(COLUMNADDR); + sendCommand(0x0); + sendCommand(0x7F); + + sendCommand(PAGEADDR); + sendCommand(0x0); + + if (geometry == GEOMETRY_128_64) { + sendCommand(0x7); + } else if (geometry == GEOMETRY_128_32) { + sendCommand(0x3); + } + + digitalWrite(_cs, HIGH); + digitalWrite(_dc, HIGH); // data mode + digitalWrite(_cs, LOW); + for (uint16_t i=0; i=0; i-=4) { + display.drawLine(0, display.getHeight()-1, display.getWidth()-1, i); + display.display(); + delay(10); + } + delay(250); + + display.clear(); + for (int16_t i=display.getWidth()-1; i>=0; i-=4) { + display.drawLine(display.getWidth()-1, display.getHeight()-1, i, 0); + display.display(); + delay(10); + } + for (int16_t i=display.getHeight()-1; i>=0; i-=4) { + display.drawLine(display.getWidth()-1, display.getHeight()-1, 0, i); + display.display(); + delay(10); + } + delay(250); + display.clear(); + for (int16_t i=0; i // Only needed for Arduino 1.6.5 and earlier +#include "SSD1306Wire.h" // legacy: #include "SSD1306.h" +// OR #include "SH1106Wire.h" // legacy: #include "SH1106.h" + +// For a connection via I2C using brzo_i2c (must be installed) include: +// #include // Only needed for Arduino 1.6.5 and earlier +// #include "SSD1306Brzo.h" +// OR #include "SH1106Brzo.h" + +// For a connection via SPI include: +// #include // Only needed for Arduino 1.6.5 and earlier +// #include "SSD1306Spi.h" +// OR #include "SH1106SPi.h" + + +// Optionally include custom images +#include "images.h" + + +// Initialize the OLED display using Arduino Wire: +SSD1306Wire display(0x3c, SDA, SCL); // ADDRESS, SDA, SCL - SDA and SCL usually populate automatically based on your board's pins_arduino.h + + +#define DEMO_DURATION 3000 +typedef void (*Demo)(void); + +int demoMode = 0; +int counter = 1; + +void setup() { + Serial.begin(115200); + Serial.println(); + Serial.println(); + + + // Initialising the UI will init the display too. + display.init(); + + display.flipScreenVertically(); + display.setFont(ArialMT_Plain_10); + +} + +void drawFontFaceDemo() { + // Font Demo1 + // create more fonts at http://oleddisplay.squix.ch/ + display.setTextAlignment(TEXT_ALIGN_LEFT); + display.setFont(ArialMT_Plain_10); + display.drawString(0, 0, "Hello world"); + display.setFont(ArialMT_Plain_16); + display.drawString(0, 10, "Hello world"); + display.setFont(ArialMT_Plain_24); + display.drawString(0, 26, "Hello world"); +} + +void drawTextFlowDemo() { + display.setFont(ArialMT_Plain_10); + display.setTextAlignment(TEXT_ALIGN_LEFT); + display.drawStringMaxWidth(0, 0, 128, + "Lorem ipsum\n dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore." ); +} + +void drawTextAlignmentDemo() { + // Text alignment demo + display.setFont(ArialMT_Plain_10); + + // The coordinates define the left starting point of the text + display.setTextAlignment(TEXT_ALIGN_LEFT); + display.drawString(0, 10, "Left aligned (0,10)"); + + // The coordinates define the center of the text + display.setTextAlignment(TEXT_ALIGN_CENTER); + display.drawString(64, 22, "Center aligned (64,22)"); + + // The coordinates define the right end of the text + display.setTextAlignment(TEXT_ALIGN_RIGHT); + display.drawString(128, 33, "Right aligned (128,33)"); +} + +void drawRectDemo() { + // Draw a pixel at given position + for (int i = 0; i < 10; i++) { + display.setPixel(i, i); + display.setPixel(10 - i, i); + } + display.drawRect(12, 12, 20, 20); + + // Fill the rectangle + display.fillRect(14, 14, 17, 17); + + // Draw a line horizontally + display.drawHorizontalLine(0, 40, 20); + + // Draw a line horizontally + display.drawVerticalLine(40, 0, 20); +} + +void drawCircleDemo() { + for (int i=1; i < 8; i++) { + display.setColor(WHITE); + display.drawCircle(32, 32, i*3); + if (i % 2 == 0) { + display.setColor(BLACK); + } + display.fillCircle(96, 32, 32 - i* 3); + } +} + +void drawProgressBarDemo() { + int progress = (counter / 5) % 100; + // draw the progress bar + display.drawProgressBar(0, 32, 120, 10, progress); + + // draw the percentage as String + display.setTextAlignment(TEXT_ALIGN_CENTER); + display.drawString(64, 15, String(progress) + "%"); +} + +void drawImageDemo() { + // see http://blog.squix.org/2015/05/esp8266-nodemcu-how-to-create-xbm.html + // on how to create xbm files + display.drawXbm(34, 14, WiFi_Logo_width, WiFi_Logo_height, WiFi_Logo_bits); +} + +Demo demos[] = {drawFontFaceDemo, drawTextFlowDemo, drawTextAlignmentDemo, drawRectDemo, drawCircleDemo, drawProgressBarDemo, drawImageDemo}; +int demoLength = (sizeof(demos) / sizeof(Demo)); +long timeSinceLastModeSwitch = 0; + +void loop() { + // clear the display + display.clear(); + // draw the current demo method + demos[demoMode](); + + display.setTextAlignment(TEXT_ALIGN_RIGHT); + display.drawString(10, 128, String(millis())); + // write the buffer to the display + display.display(); + + if (millis() - timeSinceLastModeSwitch > DEMO_DURATION) { + demoMode = (demoMode + 1) % demoLength; + timeSinceLastModeSwitch = millis(); + } + counter++; + delay(10); +} diff --git a/libraries/SSD1306_SPI/examples/SSD1306SimpleDemo/images.h b/libraries/SSD1306_SPI/examples/SSD1306SimpleDemo/images.h new file mode 100644 index 00000000..2f06c31f --- /dev/null +++ b/libraries/SSD1306_SPI/examples/SSD1306SimpleDemo/images.h @@ -0,0 +1,36 @@ +#define WiFi_Logo_width 60 +#define WiFi_Logo_height 36 +const uint8_t WiFi_Logo_bits[] PROGMEM = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0xFF, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, + 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + 0x00, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0x83, 0x01, 0x80, 0xFF, 0xFF, 0xFF, + 0x01, 0x00, 0x07, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x0C, 0x00, + 0xC0, 0xFF, 0xFF, 0x7C, 0x00, 0x60, 0x0C, 0x00, 0xC0, 0x31, 0x46, 0x7C, + 0xFC, 0x77, 0x08, 0x00, 0xE0, 0x23, 0xC6, 0x3C, 0xFC, 0x67, 0x18, 0x00, + 0xE0, 0x23, 0xE4, 0x3F, 0x1C, 0x00, 0x18, 0x00, 0xE0, 0x23, 0x60, 0x3C, + 0x1C, 0x70, 0x18, 0x00, 0xE0, 0x03, 0x60, 0x3C, 0x1C, 0x70, 0x18, 0x00, + 0xE0, 0x07, 0x60, 0x3C, 0xFC, 0x73, 0x18, 0x00, 0xE0, 0x87, 0x70, 0x3C, + 0xFC, 0x73, 0x18, 0x00, 0xE0, 0x87, 0x70, 0x3C, 0x1C, 0x70, 0x18, 0x00, + 0xE0, 0x87, 0x70, 0x3C, 0x1C, 0x70, 0x18, 0x00, 0xE0, 0x8F, 0x71, 0x3C, + 0x1C, 0x70, 0x18, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x08, 0x00, + 0xC0, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x0C, 0x00, 0x80, 0xFF, 0xFF, 0x1F, + 0x00, 0x00, 0x06, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x07, 0x00, + 0x00, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0xF8, 0xFF, 0xFF, + 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x01, 0x00, 0x00, + 0x00, 0x00, 0xFC, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + +//Added by Sloeber +#pragma once + + +//Added by Sloeber +#pragma once + diff --git a/package/package_CubeCell_index.template.json b/package/package_CubeCell_index.template.json new file mode 100644 index 00000000..f9624a9b --- /dev/null +++ b/package/package_CubeCell_index.template.json @@ -0,0 +1,133 @@ +{ + "packages": [ + { + "maintainer": "Heltec Automation(TM)", + "help": { + "online": "http://heltec.cn" + }, + "websiteURL": "https://github.com/Heltec-Aaron-Lee/CubeCell", + "platforms": [ + { + "category": "CubeCell", + "name": "CubeCell Dev-boards", + "url": "http://119.23.153.38/download/CubeCell-0.0.1.zip", + "checksum": "SHA-256:eadce33ffba2c50c68cd661800961f3afe3a45da14441a02383abe468d53f322", + "help": { + "online": "" + }, + "version": "0.0.1", + "architecture": "CubeCell", + "archiveFileName": "CubeCell-0.0.1.zip", + "boards": [ + {"name": "CubeCell-Board"}, + {"name": "CubeCell-Cupsule"}, + {"name": "CubeCell-Module"} + ], + "toolsDependencies": [ + { + "packager": "CubeCell", + "version": "8-2019-q3", + "name": "gcc-arm-none-eabi" + }, + { + "packager": "CubeCell", + "version": "0.0.1", + "name": "CubeCellelftool" + }, + { + "packager": "CubeCell", + "version": "0.0.1", + "name": "CubeCellflash" + } + ], + "size": "1159168" + } + ], + "tools": [ + { + "version": "0.0.1", + "name": "CubeCellelftool", + "systems": [ + { + "url": "http://119.23.153.38/download/CubeCellelftool-0.0.1-windows.zip", + "checksum": "SHA-256:5deffed88f98ccee3ad525552f61c47d3677807777d9db7e26806d89c77810d5", + "host": "i686-mingw32", + "archiveFileName": "CubeCellelftool-0.0.1-windows.zip", + "size": "5947392" + }, + { + "url": "http://119.23.153.38/download/CubeCellelftool-0.0.1-macos.tar.gz", + "checksum": "SHA-256:a721a52f5692489dd49195f54e8e99eebac55b26dba6c354e1e6eb6518f62282", + "host": "x86_64-apple-darwin", + "archiveFileName": "CubeCellelftool-0.0.1-macos.tar.gz", + "size": "9457664" + }, + { + "url": "http://119.23.153.38/download/CubeCellelftool-0.0.1-linux.tar.gz", + "checksum": "SHA-256:a50699eb3b4ab43899a3da55e5bcec00cfc1b3979495e7bddf1ef8da8d8c3079", + "host": "x86_64-pc-linux-gnu", + "archiveFileName": "CubeCellelftool-0.0.1-linux.tar.gz", + "size": "9949184" + } + ] + }, + { + "version": "0.0.1", + "name": "CubeCellflash", + "systems": [ + { + "url": "http://119.23.153.38/download/CubeCellflash-0.0.1-windows.zip", + "checksum": "SHA-256:8e6da70ca70097db40971333a0222930c40c7a1da3fd3b5264b08aa7cbb906a1", + "host": "i686-mingw32", + "archiveFileName": "CubeCellflash-0.0.1-windows.zip", + "size": "6139904" + }, + { + "url": "http://119.23.153.38/download/CubeCellflash-0.0.1-macos.tar.gz", + "checksum": "SHA-256:0e2afe8fe9829923a147f6be182909964e6469695da98491f2a4d141c39b14c7", + "host": "x86_64-apple-darwin", + "archiveFileName": "CubeCellflash-0.0.1-macos.tar.gz", + "size": "9920512" + }, + { + "url": "http://119.23.153.38/download/CubeCellflash-0.0.1-linux.tar.gz", + "checksum": "SHA-256:ea61a2f8059d43e037102c5532576e8721234d577704e64ee8252fcbcd14f924", + "host": "x86_64-pc-linux-gnu", + "archiveFileName": "CubeCellflash-0.0.1-linux.tar.gz", + "size": "10706944" + } + ] + }, + { + "version": "8-2019-q3", + "name": "gcc-arm-none-eabi", + "systems": [ + { + "url": "http://119.23.153.38/download/gcc-arm-none-eabi-8-2019-q3-update-win32.zip", + "checksum": "SHA-256:67faf63af878ce35b377657a5ddcbce3fdeeaec2ee4147fb57da2841e4ad7560", + "host": "i686-mingw32", + "archiveFileName": "gcc-arm-none-eabi-8-2019-q3-update-win32.zip", + "size": "92114944" + }, + { + "url": "http://119.23.153.38/download/gcc-arm-none-eabi-8-2019-q3-update-macos.tar.gz", + "checksum": "SHA-256:26e7cca13d397c21002d5946c93135b81d827eda2c9081e9701c3de56f6adbab", + "host": "x86_64-apple-darwin", + "archiveFileName": "gcc-arm-none-eabi-8-2019-q3-update-macos.tar.gz", + "size": "123871232" + }, + { + "url": "http://119.23.153.38/download/gcc-arm-none-eabi-8-2019-q3-update-linux.tar.gz", + "checksum": "SHA-256:276e58f03ab31405ea8bc5d6b0792fa40bec2a2bf049b354a3ee152764b472a9", + "host": "x86_64-pc-linux-gnu", + "archiveFileName": "gcc-arm-none-eabi-8-2019-q3-update-linux.tar.gz", + "size": "123871232" + } + ] + } + ], + "email": "support@heltec.cn", + "name": "CubeCell" + } + ] +} \ No newline at end of file diff --git a/platform.txt b/platform.txt new file mode 100644 index 00000000..8151464d --- /dev/null +++ b/platform.txt @@ -0,0 +1,79 @@ +name=CubeCell +version=0.0.1 + +tools.CubeCellflash.cmd.windows={runtime.tools.CubeCellflash.path}/CubeCellflash.exe +tools.CubeCellflash.cmd.linux={runtime.tools.CubeCellflash.path}/CubeCellflash +tools.CubeCellflash.cmd.macosx={runtime.tools.CubeCellflash.path}/CubeCellflash + +tools.CubeCellelftool.cmd.windows={runtime.tools.CubeCellelftool.path}/CubeCellelftool.exe +tools.CubeCellelftool.cmd.linux={runtime.tools.CubeCellelftool.path}/CubeCellelftool +tools.CubeCellelftool.cmd.macosx={runtime.tools.CubeCellelftool.path}/CubeCellelftool + +compiler.warning_flags=-w +compiler.warning_flags.none=-w +compiler.warning_flags.default= +compiler.warning_flags.more=-Wall +compiler.warning_flags.all=-Wall -Wextra + +compiler.path={runtime.tools.gcc-arm-none-eabi.path}/bin/ + +compiler.sdk.path={runtime.platform.path}/cores/asr650x +compiler.cpreprocessor.flags=-D{build.band} -DACTIVE_REGION=LORAMAC_{build.band} -DCLASS_MODE={build.LORAWAN_MODE} -DLoraWan_RGB={build.RGB} -DCY_CORE_ID=0 -DCONFIG_LORA_USE_TCXO -DCONFIG_MANUFACTURER="ASR" -DCONFIG_DEVICE_MODEL="6501" -DCONFIG_VERSION="v4.0" "-I{compiler.sdk.path}/board/" "-I{compiler.sdk.path}/board/src/" "-I{compiler.sdk.path}/board/inc/" "-I{compiler.sdk.path}/device/asr6501_lrwan/" "-I{compiler.sdk.path}/device/sx126x/" "-I{compiler.sdk.path}/kernel/protocols/lorawan/lora/mac/" "-I{compiler.sdk.path}/kernel/protocols/lorawan/lora/mac/region/" "-I{compiler.sdk.path}/kernel/protocols/lorawan/lora/system/" "-I{compiler.sdk.path}/kernel/protocols/lorawan/lora/system/crypto/" "-I{compiler.sdk.path}/port/" "-I{compiler.sdk.path}/port/include/" "-I{compiler.sdk.path}/projects/" "-I{compiler.sdk.path}/projects/PSoC4/" "-I{compiler.sdk.path}/cores/" "-I{compiler.sdk.path}/Serial/" "-I{compiler.sdk.path}/Wire/" "-I{compiler.sdk.path}/SPI/" + +compiler.c.cmd=arm-none-eabi-gcc +compiler.c.flags=-mcpu=cortex-m0plus -mthumb -g -gdwarf-2 -MD -w -Os -mapcs-frame -mthumb-interwork -Wall -ffunction-sections -ffat-lto-objects -Os -fno-common -fno-builtin-printf -fno-builtin-fflush -fno-builtin-sprintf -fno-builtin-snprintf -Wno-strict-aliasing -c + +compiler.cpp.cmd=arm-none-eabi-g++ +compiler.cpp.flags=-mcpu=cortex-m0plus -mthumb -g -gdwarf-2 -MD -w -Os -mapcs-frame -mthumb-interwork -Wall -ffunction-sections -ffat-lto-objects -Os -fno-common -fno-builtin-printf -fno-builtin-fflush -fno-builtin-sprintf -fno-builtin-snprintf -Wno-strict-aliasing -c -fno-exceptions -fexceptions -fno-rtti + +compiler.S.cmd=arm-none-eabi-as +compiler.S.flags=-mcpu=cortex-m0plus -mthumb -g -w --gdwarf-2 "-I{compiler.sdk.path}/projects/PSoC4" + +compiler.c.elf.cmd=arm-none-eabi-gcc +compiler.c.elf.flags=-mcpu=cortex-m0plus -mthumb "-L{compiler.sdk.path}/projects/Generated_Source/PSoC4" "{compiler.sdk.path}/projects/AsrLib.a" "-T{compiler.sdk.path}/projects/Generated_Source\PSoC4\cm0plusgcc.ld" "-Wl,-Map,{build.path}/{build.project_name}.map" -specs=nano.specs -Wl,--gc-sections -Wl,--wrap=printf -Wl,--wrap=fflush -Wl,--wrap=sprintf -Wl,--wrap=snprintf -g -ffunction-sections -Os -ffat-lto-objects + +compiler.as.cmd=arm-none-eabi-as + +compiler.ar.cmd=arm-none-eabi-ar +compiler.ar.flags=-rcs + +compiler.objcopy.cmd=arm-none-eabi-objcopy + +compiler.size.cmd=arm-none-eabi-size + + +# These can be overridden in platform.local.txt +compiler.c.extra_flags= +compiler.c.elf.extra_flags= +compiler.S.extra_flags= +compiler.cpp.extra_flags= +compiler.ar.extra_flags= +compiler.objcopy.eep.extra_flags= +compiler.elf2hex.extra_flags= +compiler.ldflags= + +## Compile c files +recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.flags} {compiler.c.flags} {compiler.c.extra_flags} {includes} "{source_file}" -o "{object_file}" + + +## Compile c++ files +recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpreprocessor.flags} {compiler.cpp.flags} {compiler.cpp.extra_flags} {includes} "{source_file}" -o "{object_file}" + +#### Compile S files +recipe.S.o.pattern="{compiler.path}{compiler.S.cmd}" {compiler.S.flags} "{source_file}" -o "{object_file}" + +## Create archives +recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" + +## Combine gc-sections, archives, and objects +recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" -Wl,--start-group "-L{build.path}" -mcpu=cortex-m0plus -mthumb -mthumb-interwork "-L{compiler.sdk.path}/projects/PSoC4" {compiler.c.elf.extra_flags} "-T{compiler.sdk.path}/projects/PSoC4/cm0plusgcc.ld" -lstdc++ -lm "{compiler.sdk.path}/projects/CubeCellLib.a" "-Wl,-Map,{build.path}/{build.project_name}.map" -specs=nano.specs -Wl,--gc-sections -Wl,--wrap=printf -Wl,--wrap=fflush -Wl,--wrap=sprintf -Wl,--wrap=snprintf -g -ffunction-sections -Os -ffat-lto-objects {compiler.ldflags} -o "{build.path}/{build.project_name}.elf" {object_files} -lm "{build.path}/{archive_file}" -Wl,--end-group + +recipe.objcopy.hex.pattern={tools.CubeCellelftool.cmd} "{compiler.path}{compiler.objcopy.cmd}" "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.hex" "{build.path}/{build.project_name}.cyacd" + +recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf" +recipe.size.regex=\.text\s+([0-9]+).* + +tools.CubeCellflash.upload.protocol= +tools.CubeCellflash.upload.params.verbose= +tools.CubeCellflash.upload.params.quiet= +tools.CubeCellflash.upload.pattern="{cmd}" -serial "{serial.port}" "{build.path}/{build.project_name}.cyacd" \ No newline at end of file diff --git a/tools/get.exe b/tools/get.exe new file mode 100644 index 00000000..78fd4652 Binary files /dev/null and b/tools/get.exe differ diff --git a/tools/get.py b/tools/get.py new file mode 100644 index 00000000..f2680799 --- /dev/null +++ b/tools/get.py @@ -0,0 +1,161 @@ +#!/usr/bin/env python + +from __future__ import print_function + +import os +import shutil +import errno +import os.path +import hashlib +import json +import platform +import sys +import tarfile +import zipfile +import re + + +if sys.version_info[0] == 3: + from urllib.request import urlretrieve + unicode = lambda s: str(s) +else: + # Not Python 3 - today, it is most likely to be Python 2 + from urllib import urlretrieve + +if 'Windows' in platform.system(): + import urllib.request + +current_dir = os.path.dirname(os.path.realpath(unicode(__file__))) +dist_dir = current_dir + '/dist/' + +def sha256sum(filename, blocksize=65536): + hash = hashlib.sha256() + with open(filename, "rb") as f: + for block in iter(lambda: f.read(blocksize), b""): + hash.update(block) + return hash.hexdigest() + +def mkdir_p(path): + if not os.path.exists(path): + os.mkdir(path) + else: + for root, dirs, files in os.walk(path, topdown=False): + for name in files: + os.remove(os.path.join(root, name)) + for name in dirs: + os.rmdir(os.path.join(root, name)) + os.removedirs(path) + os.mkdir(path) + #try: + # os.makedirs(path) + #except OSError as exc: + # if exc.errno != errno.EEXIST or not os.path.isdir(path): + # raise + + +def format_size(bytes): + try: + bytes = float(bytes) + kb = bytes / 1024 + except: + return "Error" + if kb >= 1024: + M = kb / 1024 + if M >= 1024: + G = M / 1024 + return "%.2fG" % (G) + else: + return "%.2fM" % (M) + else: + return "%.2fK" % (kb) + + +def report_progress(blocknum, blocksize, totalsize): + percent = int(blocknum*blocksize*100/totalsize) + percent = min(100, percent) + totalsize_str = " totalsize: %s" % format_size(totalsize) + sys.stdout.write("\r%d%% " % percent+totalsize_str) + sys.stdout.flush() + +def unpack(filename, destination): + dirname = '' + print('Extracting {0}'.format(os.path.basename(filename))) + sys.stdout.flush() + if filename.endswith('tar.gz'): + tfile = tarfile.open(filename, 'r:gz') + tfile.extractall(destination) + dirname = tfile.getnames()[0] + elif filename.endswith('zip'): + zfile = zipfile.ZipFile(filename) + zfile.extractall(destination) + dirname = zfile.namelist()[0] + else: + raise NotImplementedError('Unsupported archive type') + +def get_tool(tool): + sys_name = platform.system() + archive_name = tool['archiveFileName'] + local_path = dist_dir + archive_name + url = tool['url'] + #real_hash = tool['checksum'].split(':')[1] + if not os.path.isfile(local_path): + print('Downloading ' + archive_name) + sys.stdout.flush() + if 'CYGWIN_NT' in sys_name: + import ssl + ctx = ssl.create_default_context() + ctx.check_hostname = False + ctx.verify_mode = ssl.CERT_NONE + urlretrieve(url, local_path, report_progress, context=ctx) + elif 'Windows' in sys_name: + urllib.request.urlretrieve(url, local_path, report_progress,) + else: + urlretrieve(url, local_path, report_progress) + sys.stdout.write("\r\nDone\n") + sys.stdout.flush() + else: + print('Tool {0} already downloaded'.format(archive_name)) + sys.stdout.flush() + #local_hash = sha256sum(local_path) + #if local_hash != real_hash: + # print('Hash mismatch for {0}, delete the file and try again'.format(local_path)) + # raise RuntimeError() + unpack(local_path, '.') + +def load_tools_list(filename, platform): + tools_info = json.load(open(filename))['packages'][0]['tools'] + tools_to_download = [] + for t in tools_info: + tool_platform = [p for p in t['systems'] if p['host'] == platform] + if len(tool_platform) == 0: + continue + tools_to_download.append(tool_platform[0]) + return tools_to_download + +def identify_platform(): + arduino_platform_names = {'Darwin' : {32 : 'i386-apple-darwin', 64 : 'x86_64-apple-darwin'}, + 'Linux' : {32 : 'i686-pc-linux-gnu', 64 : 'x86_64-pc-linux-gnu'}, + 'LinuxARM': {32 : 'arm-linux-gnueabihf', 64 : 'aarch64-linux-gnu'}, + 'Windows' : {32 : 'i686-mingw32', 64 : 'i686-mingw32'}} + bits = 32 + if sys.maxsize > 2**32: + bits = 64 + sys_name = platform.system() + sys_platform = platform.platform() + print('System: %s, Info: %s' % (sys_name, sys_platform)) + if 'Linux' in sys_name and sys_platform.find('arm') > 0: + sys_name = 'LinuxARM' + if 'CYGWIN_NT' in sys_name: + sys_name = 'Windows' + return arduino_platform_names[sys_name][bits] + +if __name__ == '__main__': + identified_platform = identify_platform() + print('Platform: {0}'.format(identified_platform)) + tools_to_download = load_tools_list(current_dir + '/../package/package_CubeCell_index.template.json', identified_platform) + mkdir_p(dist_dir) + for tool in tools_to_download: + get_tool(tool) + platform_dir=os.path.abspath(os.path.join(os.getcwd(), "..")) + shutil.copy("platform.txt",platform_dir) + print('Done') \ No newline at end of file diff --git a/tools/platform.txt b/tools/platform.txt new file mode 100644 index 00000000..9ec186a5 --- /dev/null +++ b/tools/platform.txt @@ -0,0 +1,79 @@ +name=CubeCell +version=0.0.1 + +tools.CubeCellflash.cmd.windows={runtime.platform.path}/tools/CubeCellflash/CubeCellflash.exe +tools.CubeCellflash.cmd.linux={runtime.platform.path}/tools/CubeCellflash/CubeCellflash +tools.CubeCellflash.cmd.macosx={{runtime.platform.path}/tools/CubeCellflash/CubeCellflash + +tools.CubeCellelftool.cmd.windows={runtime.platform.path}/tools/CubeCellelftool/CubeCellelftool.exe +tools.CubeCellelftool.cmd.linux={runtime.platform.path}/tools/CubeCellelftool/CubeCellelftool +tools.CubeCellelftool.cmd.macosx={runtime.platform.path}/tools/CubeCellelftool/CubeCellelftool + +compiler.warning_flags=-w +compiler.warning_flags.none=-w +compiler.warning_flags.default= +compiler.warning_flags.more=-Wall +compiler.warning_flags.all=-Wall -Wextra + +compiler.path={runtime.platform.path}/tools/gcc-arm-none-eabi/bin/ + +compiler.sdk.path={runtime.platform.path}/cores/asr650x +compiler.cpreprocessor.flags=-D{build.band} -DACTIVE_REGION=LORAMAC_{build.band} -DCLASS_MODE={build.LORAWAN_MODE} -DLoraWan_RGB={build.RGB} -DCY_CORE_ID=0 -DCONFIG_LORA_USE_TCXO -DCONFIG_MANUFACTURER="ASR" -DCONFIG_DEVICE_MODEL="6501" -DCONFIG_VERSION="v4.0" "-I{compiler.sdk.path}/board/" "-I{compiler.sdk.path}/board/src/" "-I{compiler.sdk.path}/board/inc/" "-I{compiler.sdk.path}/device/asr6501_lrwan/" "-I{compiler.sdk.path}/device/sx126x/" "-I{compiler.sdk.path}/kernel/protocols/lorawan/lora/mac/" "-I{compiler.sdk.path}/kernel/protocols/lorawan/lora/mac/region/" "-I{compiler.sdk.path}/kernel/protocols/lorawan/lora/system/" "-I{compiler.sdk.path}/kernel/protocols/lorawan/lora/system/crypto/" "-I{compiler.sdk.path}/port/" "-I{compiler.sdk.path}/port/include/" "-I{compiler.sdk.path}/projects/" "-I{compiler.sdk.path}/projects/PSoC4/" "-I{compiler.sdk.path}/cores/" "-I{compiler.sdk.path}/Serial/" "-I{compiler.sdk.path}/Wire/" "-I{compiler.sdk.path}/SPI/" + +compiler.c.cmd=arm-none-eabi-gcc +compiler.c.flags=-mcpu=cortex-m0plus -mthumb -g -gdwarf-2 -MD -w -Os -mapcs-frame -mthumb-interwork -Wall -ffunction-sections -ffat-lto-objects -Os -fno-common -fno-builtin-printf -fno-builtin-fflush -fno-builtin-sprintf -fno-builtin-snprintf -Wno-strict-aliasing -c + +compiler.cpp.cmd=arm-none-eabi-g++ +compiler.cpp.flags=-mcpu=cortex-m0plus -mthumb -g -gdwarf-2 -MD -w -Os -mapcs-frame -mthumb-interwork -Wall -ffunction-sections -ffat-lto-objects -Os -fno-common -fno-builtin-printf -fno-builtin-fflush -fno-builtin-sprintf -fno-builtin-snprintf -Wno-strict-aliasing -c -fno-exceptions -fexceptions -fno-rtti + +compiler.S.cmd=arm-none-eabi-as +compiler.S.flags=-mcpu=cortex-m0plus -mthumb -g -w --gdwarf-2 "-I{compiler.sdk.path}/projects/PSoC4" + +compiler.c.elf.cmd=arm-none-eabi-gcc +compiler.c.elf.flags=-mcpu=cortex-m0plus -mthumb "-L{compiler.sdk.path}/projects/Generated_Source/PSoC4" "{compiler.sdk.path}/projects/AsrLib.a" "-T{compiler.sdk.path}/projects/Generated_Source\PSoC4\cm0plusgcc.ld" "-Wl,-Map,{build.path}/{build.project_name}.map" -specs=nano.specs -Wl,--gc-sections -Wl,--wrap=printf -Wl,--wrap=fflush -Wl,--wrap=sprintf -Wl,--wrap=snprintf -g -ffunction-sections -Os -ffat-lto-objects + +compiler.as.cmd=arm-none-eabi-as + +compiler.ar.cmd=arm-none-eabi-ar +compiler.ar.flags=-rcs + +compiler.objcopy.cmd=arm-none-eabi-objcopy + +compiler.size.cmd=arm-none-eabi-size + + +# These can be overridden in platform.local.txt +compiler.c.extra_flags= +compiler.c.elf.extra_flags= +compiler.S.extra_flags= +compiler.cpp.extra_flags= +compiler.ar.extra_flags= +compiler.objcopy.eep.extra_flags= +compiler.elf2hex.extra_flags= +compiler.ldflags= + +## Compile c files +recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.flags} {compiler.c.flags} {compiler.c.extra_flags} {includes} "{source_file}" -o "{object_file}" + + +## Compile c++ files +recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpreprocessor.flags} {compiler.cpp.flags} {compiler.cpp.extra_flags} {includes} "{source_file}" -o "{object_file}" + +#### Compile S files +recipe.S.o.pattern="{compiler.path}{compiler.S.cmd}" {compiler.S.flags} "{source_file}" -o "{object_file}" + +## Create archives +recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" + +## Combine gc-sections, archives, and objects +recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" -Wl,--start-group "-L{build.path}" -mcpu=cortex-m0plus -mthumb -mthumb-interwork "-L{compiler.sdk.path}/projects/PSoC4" {compiler.c.elf.extra_flags} "-T{compiler.sdk.path}/projects/PSoC4/cm0plusgcc.ld" -lstdc++ -lm "{compiler.sdk.path}/projects/CubeCellLib.a" "-Wl,-Map,{build.path}/{build.project_name}.map" -specs=nano.specs -Wl,--gc-sections -Wl,--wrap=printf -Wl,--wrap=fflush -Wl,--wrap=sprintf -Wl,--wrap=snprintf -g -ffunction-sections -Os -ffat-lto-objects {compiler.ldflags} -o "{build.path}/{build.project_name}.elf" {object_files} -lm "{build.path}/{archive_file}" -Wl,--end-group + +recipe.objcopy.hex.pattern={tools.CubeCellelftool.cmd} "{compiler.path}{compiler.objcopy.cmd}" "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.hex" "{build.path}/{build.project_name}.cyacd" + +recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf" +recipe.size.regex=\.text\s+([0-9]+).* + +tools.CubeCellflash.upload.protocol= +tools.CubeCellflash.upload.params.verbose= +tools.CubeCellflash.upload.params.quiet= +tools.CubeCellflash.upload.pattern="{cmd}" -serial "{serial.port}" "{build.path}/{build.project_name}.cyacd" \ No newline at end of file